[llvm-branch-commits] [llvm] cddd3fa - [CSKY] Add visibility macro to fix link error
Author: Zi Xuan Wu
Date: 2021-01-11T16:18:01+08:00
New Revision: cddd3faf5debdfd2c09bb5b723f579fa8c8d5027
URL:
https://github.com/llvm/llvm-project/commit/cddd3faf5debdfd2c09bb5b723f579fa8c8d5027
DIFF:
https://github.com/llvm/llvm-project/commit/cddd3faf5debdfd2c09bb5b723f579fa8c8d5027.diff
LOG: [CSKY] Add visibility macro to fix link error
Add LLVM_EXTERNAL_VISIBILITY macro to fix link error of
https://reviews.llvm.org/D88466#2476378
Added:
Modified:
llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
Removed:
diff --git a/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
b/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
index 800b10517aa7..1af2e672ff42 100644
--- a/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
+++ b/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
@@ -15,6 +15,6 @@ Target &llvm::getTheCSKYTarget() {
return TheCSKYTarget;
}
-extern "C" void LLVMInitializeCSKYTargetInfo() {
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTargetInfo() {
RegisterTarget X(getTheCSKYTarget(), "csky", "C-SKY", "CSKY");
}
___
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[llvm-branch-commits] [llvm] ec17c4f - [CSKY 3/n] Add bare-bones C-SKY MCTargetDesc
Author: Zi Xuan Wu
Date: 2020-12-22T11:32:39+08:00
New Revision: ec17c4f0755bdc37e6788113909368a63d0a3b97
URL:
https://github.com/llvm/llvm-project/commit/ec17c4f0755bdc37e6788113909368a63d0a3b97
DIFF:
https://github.com/llvm/llvm-project/commit/ec17c4f0755bdc37e6788113909368a63d0a3b97.diff
LOG: [CSKY 3/n] Add bare-bones C-SKY MCTargetDesc
Add basis of CSKY MCTargetDesc and it's enough to compile and link but doesn't
yet do anything particularly useful.
Once an ASM parser and printer are added in the next two patches, the whole
thing can be usefully tested.
Differential Revision: https://reviews.llvm.org/D93372
Added:
llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h
Modified:
llvm/lib/Target/CSKY/CMakeLists.txt
llvm/lib/Target/CSKY/CSKYInstrInfo.td
llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
Removed:
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt
b/llvm/lib/Target/CSKY/CMakeLists.txt
index 390b8ea4c8ce..ec487ed34bbf 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -4,6 +4,7 @@ set(LLVM_TARGET_DEFINITIONS CSKY.td)
tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
add_public_tablegen_target(CSKYCommonTableGen)
@@ -22,3 +23,4 @@ add_llvm_target(CSKYCodeGen
)
add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index afc82437e649..7add217530e1 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -24,17 +24,17 @@ include "CSKYInstrFormats.td"
class oimm : Operand,
ImmLeaf(Imm - 1);"> {
- let EncoderMethod = "getOImmOpValue<"#num#">";
+ let EncoderMethod = "getOImmOpValue";
}
class uimm : Operand,
ImmLeaf(Imm);"> {
- let EncoderMethod = "getImmOpValue<"#num#", "#shift#">";
+ let EncoderMethod = "getImmOpValue<"#shift#">";
}
class simm : Operand,
ImmLeaf(Imm);"> {
- let EncoderMethod = "getImmOpValue<"#num#", "#shift#">";
+ let EncoderMethod = "getImmOpValue<"#shift#">";
}
def nimm_XFORM : SDNodeXFormhttps://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "CSKYAsmBackend.h"
+#include "MCTargetDesc/CSKYMCTargetDesc.h"
+#include "llvm/MC/MCAsmLayout.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "csky-asmbackend"
+
+using namespace llvm;
+
+std::unique_ptr
+CSKYAsmBackend::createObjectTargetWriter() const {
+ return createCSKYELFObjectWriter();
+}
+
+unsigned int CSKYAsmBackend::getNumFixupKinds() const { return 1; }
+
+void CSKYAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+const MCValue &Target,
+MutableArrayRef Data, uint64_t Value,
+bool IsResolved,
+const MCSubtargetInfo *STI) const {
+ return;
+}
+
+bool CSKYAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+ const MCRelaxableFragment *DF,
+ const MCAsmLayout &Layout) const {
+ return false;
+}
+
+void CSKYAsmBackend::relaxInstruction(MCInst &Inst,
+ const MCSubtargetInfo &STI) const {
+ llvm_unreachable("CSKYAsmBackend::relaxInstruction() unimplemented");
+}
+
+bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+ if (Count % 2)
+return false;
+
+ // MOV32 r0, r0
+ while (Count >= 4) {
+OS.write("\xc4\x00\x48\x20", 4);
+Count -= 4;
+ }
+ // MOV16 r0, r0
+ if (Count)
+OS.write("\x6c\x03", 2);
+
+ return true;
+}
+
+MCAsmBackend *llvm::createCSKYAsmBackend(const Target &T,
+ const MCSubtargetInfo &STI,
+ const MCRegisterInfo &MRI,
+ const MCTargetOptions &Options) {
+ return new CSKYAsmBackend(STI, Options);
+}
diff --git a
[llvm-branch-commits] [llvm] cac5736 - [RFC][Target] Add a new triple called Triple::csky
Author: Zi Xuan Wu
Date: 2020-09-02T12:25:54+08:00
New Revision: cac57361292aeb97484dec16c9e1c8174cf5a940
URL:
https://github.com/llvm/llvm-project/commit/cac57361292aeb97484dec16c9e1c8174cf5a940
DIFF:
https://github.com/llvm/llvm-project/commit/cac57361292aeb97484dec16c9e1c8174cf5a940.diff
LOG: [RFC][Target] Add a new triple called Triple::csky
Before upstream a new target called CSKY, make a new triple of that called
Triple::csky.
For now, it's a 32-bit little endian target and the detail can be referred at
D86269.
This is the split part of D86269, which add a new target called CSKY.
Differential Revision: https://reviews.llvm.org/D86505
Added:
Modified:
llvm/include/llvm/ADT/Triple.h
llvm/lib/Support/Triple.cpp
llvm/unittests/ADT/TripleTest.cpp
Removed:
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index 7c3a4b2b699a..b67da41f30cf 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -56,6 +56,7 @@ class Triple {
avr,// AVR: Atmel AVR microcontroller
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
+csky, // CSKY: csky
hexagon,// Hexagon: hexagon
mips, // MIPS: mips, mipsallegrex, mipsr6
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
@@ -755,6 +756,11 @@ class Triple {
return getArch() == Triple::wasm32 || getArch() == Triple::wasm64;
}
+ // Tests whether the target is CSKY
+ bool isCSKY() const {
+return getArch() == Triple::csky;
+ }
+
/// Tests whether the target supports comdat
bool supportsCOMDAT() const {
return !(isOSBinFormatMachO() || isOSBinFormatXCOFF());
diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp
index 7c2c44a53805..b1b4c3e63481 100644
--- a/llvm/lib/Support/Triple.cpp
+++ b/llvm/lib/Support/Triple.cpp
@@ -36,6 +36,7 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case avr:return "avr";
case bpfeb: return "bpfeb";
case bpfel: return "bpfel";
+ case csky: return "csky";
case hexagon:return "hexagon";
case hsail64:return "hsail64";
case hsail: return "hsail";
@@ -151,6 +152,7 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case riscv64: return "riscv";
case ve: return "ve";
+ case csky:return "csky";
}
}
@@ -319,6 +321,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef
Name) {
.Case("renderscript32", renderscript32)
.Case("renderscript64", renderscript64)
.Case("ve", ve)
+.Case("csky", csky)
.Default(UnknownArch);
}
@@ -448,6 +451,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Case("ve", Triple::ve)
.Case("wasm32", Triple::wasm32)
.Case("wasm64", Triple::wasm64)
+.Case("csky", Triple::csky)
.Default(Triple::UnknownArch);
// Some architectures require special parsing logic just to compute the
@@ -678,6 +682,7 @@ static Triple::ObjectFormatType getDefaultFormat(const
Triple &T) {
case Triple::avr:
case Triple::bpfeb:
case Triple::bpfel:
+ case Triple::csky:
case Triple::hexagon:
case Triple::hsail64:
case Triple::hsail:
@@ -1251,6 +1256,7 @@ static unsigned
getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::arc:
case llvm::Triple::arm:
case llvm::Triple::armeb:
+ case llvm::Triple::csky:
case llvm::Triple::hexagon:
case llvm::Triple::hsail:
case llvm::Triple::kalimba:
@@ -1334,6 +1340,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::arc:
case Triple::arm:
case Triple::armeb:
+ case Triple::csky:
case Triple::hexagon:
case Triple::hsail:
case Triple::kalimba:
@@ -1385,6 +1392,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::UnknownArch:
case Triple::arc:
case Triple::avr:
+ case Triple::csky:
case Triple::hexagon:
case Triple::kalimba:
case Triple::lanai:
@@ -1478,6 +1486,7 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::x86_64:
case Triple::xcore:
case Triple::ve:
+ case Triple::csky:
// ARM is intentionally unsupported here, changing the architecture would
// drop any arch suffixes.
@@ -1541,6 +1550,7 @@ bool Triple::isLittleEndian() const {
case Triple::arm:
case Triple::avr:
case Triple::bpfel:
+ case Triple::csky:
case Triple::hexagon:
case Triple::hsail64:
case Triple::hsail:
diff --git a/llvm/unittests/ADT/TripleTest.cpp
b/llvm/unittests/ADT/TripleTest.cpp
index 1a6b0557bf50..9b1c5acff424 100644
--- a/llvm/unittests/ADT/TripleTest.cpp
+++ b/llvm/unittests/ADT/TripleTest.cpp
@@ -303,6 +303,18 @@ TEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::Linux, T.getOS());
EXPECT_EQ(Triple::Unk
[llvm-branch-commits] [llvm] 365c405 - [CSKY 2/n] Add basic tablegen infra for CSKY
Author: Zi Xuan Wu
Date: 2020-12-07T11:56:09+08:00
New Revision: 365c405411461cbaa6abed6746e68faeb3f00995
URL:
https://github.com/llvm/llvm-project/commit/365c405411461cbaa6abed6746e68faeb3f00995
DIFF:
https://github.com/llvm/llvm-project/commit/365c405411461cbaa6abed6746e68faeb3f00995.diff
LOG: [CSKY 2/n] Add basic tablegen infra for CSKY
This introduce basic tablegen infra such as
CSKY{InstrFormats,InstrInfo,RegisterInfo,}.td.
For now, only add instruction definitions for basic CSKY ISA operations, and
the instruction format and register info are almost complete.
Our initial target is a working MC layer rather than codegen, so appropriate
SelectionDAG patterns will come later.
Differential Revision: https://reviews.llvm.org/D89180
Added:
llvm/lib/Target/CSKY/CSKY.td
llvm/lib/Target/CSKY/CSKYInstrFormats.td
llvm/lib/Target/CSKY/CSKYInstrInfo.td
llvm/lib/Target/CSKY/CSKYRegisterInfo.td
Modified:
llvm/lib/Target/CSKY/CMakeLists.txt
Removed:
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt
b/llvm/lib/Target/CSKY/CMakeLists.txt
index 51b7b02e727b..390b8ea4c8ce 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -1,5 +1,12 @@
add_llvm_component_group(CSKY)
+set(LLVM_TARGET_DEFINITIONS CSKY.td)
+
+tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
+
+add_public_tablegen_target(CSKYCommonTableGen)
+
add_llvm_target(CSKYCodeGen
CSKYTargetMachine.cpp
diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
new file mode 100644
index ..da6151befa1b
--- /dev/null
+++ b/llvm/lib/Target/CSKY/CSKY.td
@@ -0,0 +1,32 @@
+//===-- CSKY.td - Describe the CSKY Target Machine -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+include "llvm/Target/Target.td"
+
+//===--===//
+// Registers, calling conventions, instruction descriptions.
+//===--===//
+
+include "CSKYRegisterInfo.td"
+include "CSKYInstrInfo.td"
+
+//===--===//
+// CSKY processors supported.
+//===--===//
+
+def : ProcessorModel<"generic-csky", NoSchedModel, []>;
+
+//===--===//
+// Define the CSKY target.
+//===--===//
+
+def CSKYInstrInfo : InstrInfo;
+
+def CSKY : Target {
+ let InstructionSet = CSKYInstrInfo;
+}
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
new file mode 100644
index ..86f9dd0b7da3
--- /dev/null
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -0,0 +1,528 @@
+//===-- CSKYInstrFormats.td - CSKY Instruction Formats -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+class AddrMode val> {
+ bits<5> Value = val;
+}
+
+def AddrModeNone : AddrMode<0>;
+def AddrMode32B : AddrMode<1>; // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
+def AddrMode32H : AddrMode<2>; // ld32.h, ld32.hs, st32.h, st32.hs, +8kb
+def AddrMode32WD : AddrMode<3>; // ld32.w, st32.w, ld32.d, st32.d, +16kb
+def AddrMode16B : AddrMode<4>; // ld16.b, +32b
+def AddrMode16H : AddrMode<5>; // ld16.h, +64b
+def AddrMode16W : AddrMode<6>; // ld16.w, +128b or +1kb
+def AddrMode32SDF : AddrMode<7>; // flds, fldd, +1kb
+
+class CSKYInst pattern> : Instruction {
+ let Namespace = "CSKY";
+ int Size = sz;
+ AddrMode AM = am;
+
+ let OutOperandList = outs;
+ let InOperandList = ins;
+ let AsmString = asmstr;
+ let Pattern = pattern;
+ let Itinerary = NoItinerary;
+ let TSFlags{4 - 0} = AM.Value;
+}
+
+class CSKYPseudo pattern>
+: CSKYInst {
+ let isCodeGenOnly = 1;
+ let isPseudo = 1;
+}
+
+class CSKY32Inst opcode, dag outs, dag ins, string asmstr,
+ list pattern>
+: CSKYInst {
+ field bits<32> Inst;
+ let Inst{31 - 26} = opcode;
+}
+
+// CSKY 32-bit instruction
+// Format< OP[6] | Offset[26] >
+// Instruction(1): bsr32
+class J opcode, dag outs, dag ins, string op, list pattern>
+: CSKY32Inst {
+ bits<26> offset;
+ let Inst{25 - 0} = offset;
+}
+
+// Format< OP[6] | RZ[5] | S
