[llvm-branch-commits] [mlir] 3bd620d - [mlir] Correct 2 places that result in corrupted conversion rollbacks
Author: Tres Popp
Date: 2021-01-13T20:31:15+01:00
New Revision: 3bd620d4504915615b8368b20eb9e5c34f3fb779
URL:
https://github.com/llvm/llvm-project/commit/3bd620d4504915615b8368b20eb9e5c34f3fb779
DIFF:
https://github.com/llvm/llvm-project/commit/3bd620d4504915615b8368b20eb9e5c34f3fb779.diff
LOG: [mlir] Correct 2 places that result in corrupted conversion rollbacks
This corrects the last 2 issues caught by tests when causing dialect
conversion rollbacks to occur.
Differential Revision: https://reviews.llvm.org/D94623
Added:
Modified:
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
mlir/lib/Transforms/Utils/DialectConversion.cpp
Removed:
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index b895c904d623..0e0d568c3440 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -2144,7 +2144,7 @@ Value mlir::LLVM::createGlobalString(Location loc,
OpBuilder &builder,
assert(module && "builder points to an op outside of a module");
// Create the global at the entry of the module.
- OpBuilder moduleBuilder(module.getBodyRegion());
+ OpBuilder moduleBuilder(module.getBodyRegion(), builder.getListener());
MLIRContext *ctx = builder.getContext();
auto type = LLVM::LLVMArrayType::get(IntegerType::get(ctx, 8), value.size());
auto global = moduleBuilder.create(
diff --git a/mlir/lib/Transforms/Utils/DialectConversion.cpp
b/mlir/lib/Transforms/Utils/DialectConversion.cpp
index 33101a4102dd..f1fa1e250610 100644
--- a/mlir/lib/Transforms/Utils/DialectConversion.cpp
+++ b/mlir/lib/Transforms/Utils/DialectConversion.cpp
@@ -849,6 +849,7 @@ static void detachNestedAndErase(Operation *op) {
block.dropAllDefinedValueUses();
}
}
+ op->dropAllUses();
op->erase();
}
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[llvm-branch-commits] [mlir] 5cf2696 - [mlir] Remove TosaToLinalg dependency on all Passes
Author: Tres Popp Date: 2021-01-14T21:08:32+01:00 New Revision: 5cf2696317afb0631a4a09414ae40a4e226a905e URL: https://github.com/llvm/llvm-project/commit/5cf2696317afb0631a4a09414ae40a4e226a905e DIFF: https://github.com/llvm/llvm-project/commit/5cf2696317afb0631a4a09414ae40a4e226a905e.diff LOG: [mlir] Remove TosaToLinalg dependency on all Passes TosaToLinalg was depending on its header file indirectly through Passes.h rather than directly. This removes that indirection. Differential Revision: https://reviews.llvm.org/D94706 Added: Modified: mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp Removed: diff --git a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp index 98fd534a0bb6..6ad5a256f98a 100644 --- a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp +++ b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp @@ -10,7 +10,7 @@ // //===--===// -#include "mlir/Conversion/Passes.h" +#include "mlir/Conversion/TosaToLinalg/TosaToLinalg.h" #include "mlir/Dialect/Linalg/IR/LinalgOps.h" #include "mlir/Dialect/StandardOps/IR/Ops.h" #include "mlir/Dialect/Tosa/IR/TosaOps.h" ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 3bd2457 - Revert "[PowerPC] support register pressure reduction in machine combiner."
Author: Tres Popp
Date: 2021-01-18T12:01:57+01:00
New Revision: 3bd24574c7d0187e69780540fe0681914d71794f
URL:
https://github.com/llvm/llvm-project/commit/3bd24574c7d0187e69780540fe0681914d71794f
DIFF:
https://github.com/llvm/llvm-project/commit/3bd24574c7d0187e69780540fe0681914d71794f.diff
LOG: Revert "[PowerPC] support register pressure reduction in machine combiner."
This reverts commit 26a396c4ef481cb159bba631982841736a125a9c.
See https://reviews.llvm.org/D92071 for a description of the issue.
Added:
Modified:
llvm/include/llvm/CodeGen/MachineCombinerPattern.h
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
Removed:
llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index ac0cc70744d1..e9f52fb064e1 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -29,11 +29,6 @@ enum class MachineCombinerPattern {
REASSOC_XY_AMM_BMM,
REASSOC_XMM_AMM_BMM,
- // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
- // reduce register pressure.
- REASSOC_XY_BCA,
- REASSOC_XY_BAC,
-
// These are multiply-add patterns matched by the AArch64 machine combiner.
MULADDW_OP1,
MULADDW_OP2,
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp
b/llvm/lib/CodeGen/MachineCombiner.cpp
index e2b6cfe55c16..878912a6032b 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -279,9 +279,6 @@ static CombinerObjective
getCombinerObjective(MachineCombinerPattern P) {
case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
return CombinerObjective::MustReduceDepth;
- case MachineCombinerPattern::REASSOC_XY_BCA:
- case MachineCombinerPattern::REASSOC_XY_BAC:
-return CombinerObjective::MustReduceRegisterPressure;
default:
return CombinerObjective::Default;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 71d9fb2c179e..75a498b807cd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -21,15 +21,12 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/CodeGen/RegisterClassInfo.h"
-#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
@@ -76,14 +73,6 @@ static cl::opt
UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
cl::desc("Use the old (incorrect) instruction latency calculation"));
-static cl::opt
-FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
-cl::desc("register pressure factor for the transformations."));
-
-static cl::opt EnableFMARegPressureReduction(
-"ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
-cl::desc("enable register pressure reduce in machine combiner pass."));
-
// Pin the vtable to this file.
void PPCInstrInfo::anchor() {}
@@ -289,23 +278,21 @@ bool PPCInstrInfo::isAssociativeAndCommutative(const
MachineInstr &Inst) const {
#define InfoArrayIdxFMULInst 2
#define InfoArrayIdxAddOpIdx 3
#define InfoArrayIdxMULOpIdx 4
-#define InfoArrayIdxFSubInst 5
// Array keeps info for FMA instructions:
// Index 0(InfoArrayIdxFMAInst): FMA instruction;
-// Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA;
-// Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA;
+// Index 1(InfoArrayIdxFAddInst): ADD instruction assoaicted with FMA;
+// Index 2(InfoArrayIdxFMULInst): MUL instruction assoaicted with FMA;
// Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands;
// Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands;
-//second MUL operand index is plus 1;
-// Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA.
-static const uint16_t FMAOpIdxInfo[][6] = {
+//second MUL operand index is plus 1.
+static const uint16_t FMAOpIdxInfo[][5] = {
// FIXME: Add more FMA instructions like XSNMADDADP and so on.
-{PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
-{PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
-{PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC:
[llvm-branch-commits] [llvm] 170199f - [llvm][nvptx] add atomicity to counter in ISelLowering
Author: Tres Popp
Date: 2021-01-19T10:20:20+01:00
New Revision: 170199f56262cc3c80591d332da3128bc25ada96
URL:
https://github.com/llvm/llvm-project/commit/170199f56262cc3c80591d332da3128bc25ada96
DIFF:
https://github.com/llvm/llvm-project/commit/170199f56262cc3c80591d332da3128bc25ada96.diff
LOG: [llvm][nvptx] add atomicity to counter in ISelLowering
Previously uniqueCallSite could have race conditions between different
threads. Now it is accessed with an atomic RMW and will be unique
between different threads.
Differential Revision: https://reviews.llvm.org/D94784
Added:
Modified:
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/lib/Target/NVPTX/NVPTXISelLowering.h
Removed:
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 05a071300ac5..8860e90f2806 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -65,7 +65,7 @@
using namespace llvm;
-static unsigned int uniqueCallSite = 0;
+static std::atomic GlobalUniqueCallSite;
static cl::opt sched4reg(
"nvptx-sched4reg",
@@ -1243,7 +1243,7 @@ NVPTXTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
std::string NVPTXTargetLowering::getPrototype(
const DataLayout &DL, Type *retTy, const ArgListTy &Args,
const SmallVectorImpl &Outs, MaybeAlign retAlignment,
-const CallBase &CB) const {
+const CallBase &CB, unsigned UniqueCallSite) const {
auto PtrVT = getPointerTy(DL);
bool isABI = (STI.getSmVersion() >= 20);
@@ -1252,7 +1252,7 @@ std::string NVPTXTargetLowering::getPrototype(
return "";
std::stringstream O;
- O << "prototype_" << uniqueCallSite << " : .callprototype ";
+ O << "prototype_" << UniqueCallSite << " : .callprototype ";
if (retTy->getTypeID() == Type::VoidTyID) {
O << "()";
@@ -1422,8 +1422,9 @@ SDValue
NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (!isABI)
return Chain;
+ unsigned UniqueCallSite = GlobalUniqueCallSite.fetch_add(1);
SDValue tempChain = Chain;
- Chain = DAG.getCALLSEQ_START(Chain, uniqueCallSite, 0, dl);
+ Chain = DAG.getCALLSEQ_START(Chain, UniqueCallSite, 0, dl);
SDValue InFlag = Chain.getValue(1);
unsigned paramCount = 0;
@@ -1678,7 +1679,8 @@ SDValue
NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// The prototype is embedded in a string and put as the operand for a
// CallPrototype SDNode which will print out to the value of the string.
SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
-std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, *CB);
+std::string Proto =
+getPrototype(DL, RetTy, Args, Outs, retAlignment, *CB, UniqueCallSite);
const char *ProtoStr =
nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
SDValue ProtoOps[] = {
@@ -1734,9 +1736,8 @@ SDValue
NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (isIndirectCall) {
SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
-SDValue PrototypeOps[] = { Chain,
- DAG.getConstant(uniqueCallSite, dl, MVT::i32),
- InFlag };
+SDValue PrototypeOps[] = {
+Chain, DAG.getConstant(UniqueCallSite, dl, MVT::i32), InFlag};
Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
InFlag = Chain.getValue(1);
}
@@ -1832,13 +1833,10 @@ SDValue
NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
}
}
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getIntPtrConstant(uniqueCallSite, dl, true),
- DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
- true),
- InFlag, dl);
+ Chain = DAG.getCALLSEQ_END(
+ Chain, DAG.getIntPtrConstant(UniqueCallSite, dl, true),
+ DAG.getIntPtrConstant(UniqueCallSite + 1, dl, true), InFlag, dl);
InFlag = Chain.getValue(1);
- uniqueCallSite++;
// Append ProxyReg instructions to the chain to make sure that `callseq_end`
// will not get lost. Otherwise, during libcalls expansion, the nodes can
become
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index df9cd4159962..13829b924d4b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -491,7 +491,8 @@ class NVPTXTargetLowering : public TargetLowering {
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
const SmallVectorImpl &,
- MaybeAlign retAlignment, const CallBase &CB) const;
+ MaybeAlign retAlignment, const CallBase &CB,
[llvm-branch-commits] [llvm] a003f26 - [llvm] Prevent infinite loop in InstCombine of select statements
Author: Tres Popp Date: 2021-01-19T10:31:48+01:00 New Revision: a003f26539cf4db744655e76c41f4c4a8913f116 URL: https://github.com/llvm/llvm-project/commit/a003f26539cf4db744655e76c41f4c4a8913f116 DIFF: https://github.com/llvm/llvm-project/commit/a003f26539cf4db744655e76c41f4c4a8913f116.diff LOG: [llvm] Prevent infinite loop in InstCombine of select statements This fixes an issue where the RHS and LHS the comparison operation creating the predicate were swapped back and forth forever. Differential Revision: https://reviews.llvm.org/D94934 Added: Modified: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp Removed: diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 9360adc2d3ad..9870abb3b6cb 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1123,7 +1123,7 @@ Instruction *InstCombinerImpl::foldSelectValueEquivalence(SelectInst &Sel, // else. Only do this if CmpRHS is a constant, as profitability is not // clear for other cases. // FIXME: The replacement could be performed recursively. -if (isa(CmpRHS) && !isa(CmpRHS)) +if (match(CmpRHS, m_ImmConstant()) && !match(CmpLHS, m_ImmConstant())) if (auto *I = dyn_cast(TrueVal)) if (I->hasOneUse()) for (Use &U : I->operands()) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] cbda2cb - [mlir] Fully specify removeAttr return type
Author: Tres Popp
Date: 2021-01-06T00:52:35+01:00
New Revision: cbda2cba4f8e4d236d56158cecfb008e03341a70
URL:
https://github.com/llvm/llvm-project/commit/cbda2cba4f8e4d236d56158cecfb008e03341a70
DIFF:
https://github.com/llvm/llvm-project/commit/cbda2cba4f8e4d236d56158cecfb008e03341a70.diff
LOG: [mlir] Fully specify removeAttr return type
This was added without full specification like other generated methods.
This then leads to other downstream dialects failing to compile the
generated code when they are not in the mlir namespace.
Differential Revision: https://reviews.llvm.org/D94132
Added:
Modified:
mlir/test/mlir-tblgen/op-attribute.td
mlir/test/mlir-tblgen/op-decl.td
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Removed:
diff --git a/mlir/test/mlir-tblgen/op-attribute.td
b/mlir/test/mlir-tblgen/op-attribute.td
index b4c193c30c51..2f1d44016b62 100644
--- a/mlir/test/mlir-tblgen/op-attribute.td
+++ b/mlir/test/mlir-tblgen/op-attribute.td
@@ -80,7 +80,7 @@ def AOp : NS_Op<"a_op", []> {
// Test remove methods
// ---
-// DEF: Attribute AOp::removeCAttrAttr() {
+// DEF: ::mlir::Attribute AOp::removeCAttrAttr() {
// DEF-NEXT: return (*this)->removeAttr("cAttr");
// Test build methods
@@ -271,7 +271,7 @@ def UnitAttrOp : NS_Op<"unit_attr_op", []> {
// DEF: bool UnitAttrOp::attr() {
// DEF: return {{.*}} != nullptr
-// DEF: Attribute UnitAttrOp::removeAttrAttr() {
+// DEF: ::mlir::Attribute UnitAttrOp::removeAttrAttr() {
// DEF-NEXT: (*this)->removeAttr("attr");
// DEF: build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState,
/*optional*/::mlir::UnitAttr attr)
@@ -288,7 +288,7 @@ def SomeTypedArrayAttr : TypedArrayAttrBase;
def Test_Dialect_2 : Dialect {
let name = "dialect_2";
}
-def MyStruct : StructAttr<"MyStruct", Test_Dialect_2,
+def MyStruct : StructAttr<"MyStruct", Test_Dialect_2,
[StructFieldAttr<"potatoes", I64ElementsAttr>]> {
let description = "A structure describing a number of potatoes.";
}
diff --git a/mlir/test/mlir-tblgen/op-decl.td
b/mlir/test/mlir-tblgen/op-decl.td
index d4d1a8b012c6..3d4d46ceb42f 100644
--- a/mlir/test/mlir-tblgen/op-decl.td
+++ b/mlir/test/mlir-tblgen/op-decl.td
@@ -81,7 +81,7 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove,
IsolatedFromAbove]> {
// CHECK: uint32_t attr1();
// CHECK: ::mlir::FloatAttr attr2Attr()
// CHECK: ::llvm::Optional< ::llvm::APFloat > attr2();
-// CHECK: Attribute removeAttr2Attr();
+// CHECK: ::mlir::Attribute removeAttr2Attr();
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, Value val);
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, int integer = 0);
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::TypeRange s,
::mlir::Value a, ::mlir::ValueRange b, ::mlir::IntegerAttr attr1,
/*optional*/::mlir::FloatAttr attr2, unsigned someRegionsCount)
diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
index 468fd7848d82..b1c86522c6b5 100644
--- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
@@ -788,7 +788,7 @@ void OpEmitter::genOptionalAttrRemovers() {
auto upperInitial = name.take_front().upper();
auto suffix = name.drop_front();
auto *method = opClass.addMethodAndPrune(
-"Attribute", ("remove" + upperInitial + suffix + "Attr").str());
+"::mlir::Attribute", ("remove" + upperInitial + suffix +
"Attr").str());
if (!method)
return;
auto &body = method->body();
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[llvm-branch-commits] [mlir] 73c5804 - [mlir] Add std op for X raised to the power of Y
Author: Tres Popp
Date: 2020-12-15T17:06:26+01:00
New Revision: 73c580405ffae0243c113a1db6b77c0b595adf05
URL:
https://github.com/llvm/llvm-project/commit/73c580405ffae0243c113a1db6b77c0b595adf05
DIFF:
https://github.com/llvm/llvm-project/commit/73c580405ffae0243c113a1db6b77c0b595adf05.diff
LOG: [mlir] Add std op for X raised to the power of Y
Proposal:
https://llvm.discourse.group/t/rfc-standard-add-powop-to-std-dialect/2377
Differential Revision: https://reviews.llvm.org/D93119
Added:
Modified:
mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
mlir/test/IR/core-ops.mlir
Removed:
diff --git a/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
b/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
index c218618eb111..481dfaf4b34d 100644
--- a/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
+++ b/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
@@ -2352,6 +2352,39 @@ def OrOp : IntArithmeticOp<"or", [Commutative]> {
let hasFolder = 1;
}
+//===--===//
+// PowFOp
+//===--===//
+
+def PowFOp : FloatArithmeticOp<"powf"> {
+ let summary = "floating point raised to the power of operation";
+ let description = [{
+Syntax:
+
+```
+operation ::= ssa-id `=` `std.powf` ssa-use `,` ssa-use `:` type
+```
+
+The `powf` operation takes two operands and returns one result, each of
+these is required to be the same type. This type may be a floating point
+scalar type, a vector whose element type is a floating point type, or a
+floating point tensor.
+
+Example:
+
+```mlir
+// Scalar exponentiation.
+%a = powf %b, %c : f64
+
+// SIMD pointwise vector exponentiation
+%f = powf %g, %h : vector<4xf32>
+
+// Tensor pointwise exponentiation.
+%x = powf %y, %z : tensor<4x?xbf16>
+```
+ }];
+}
+
//===--===//
// PrefetchOp
//===--===//
diff --git a/mlir/test/IR/core-ops.mlir b/mlir/test/IR/core-ops.mlir
index 9af0c01bf555..502e7fb358fb 100644
--- a/mlir/test/IR/core-ops.mlir
+++ b/mlir/test/IR/core-ops.mlir
@@ -86,6 +86,9 @@ func @standard_instrs(tensor<4x4x?xf32>, f32, i32, index,
i64, f16) {
// CHECK: %[[I6:.*]] = muli %[[I2]], %[[I2]] : i32
%i6 = muli %i2, %i2 : i32
+ // CHECK: %[[F7:.*]] = powf %[[F2]], %[[F2]] : f32
+ %f7 = powf %f2, %f2 : f32
+
// CHECK: %[[C0:.*]] = create_complex %[[F2]], %[[F2]] : complex
%c0 = "std.create_complex"(%f2, %f2) : (f32, f32) -> complex
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[llvm-branch-commits] [mlir] e04785b - [mlir] Add NVVM lowering for std.pow
Author: Tres Popp
Date: 2020-12-15T18:28:23+01:00
New Revision: e04785b131cda100f1aab38067a36ae60c7d5680
URL:
https://github.com/llvm/llvm-project/commit/e04785b131cda100f1aab38067a36ae60c7d5680
DIFF:
https://github.com/llvm/llvm-project/commit/e04785b131cda100f1aab38067a36ae60c7d5680.diff
LOG: [mlir] Add NVVM lowering for std.pow
Differential Revision: https://reviews.llvm.org/D93303
Added:
Modified:
mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Removed:
diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
index a8b4d074a08e..cea1cdc7e25f 100644
--- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
+++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
@@ -148,7 +148,7 @@ void
mlir::configureGpuToNVVMConversionLegality(ConversionTarget &target) {
target.addIllegalDialect();
target.addIllegalOp();
+ LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>();
// TODO: Remove once we support replacing non-root ops.
target.addLegalOp();
@@ -191,6 +191,8 @@ void mlir::populateGpuToNVVMConversionPatterns(
"__nv_log10");
patterns.insert>(converter, "__nv_log2f",
"__nv_log2");
+ patterns.insert>(converter, "__nv_powf",
+"__nv_pow");
patterns.insert>(converter, "__nv_rsqrtf",
"__nv_rsqrt");
patterns.insert>(converter, "__nv_sinf",
diff --git a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
index d8c4d7e064e5..af6766bba6f4 100644
--- a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
+++ b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
@@ -394,3 +394,17 @@ gpu.module @test_module {
}) : () -> ()
}
+// -
+
+gpu.module @test_module {
+ // CHECK: llvm.func @__nv_powf(!llvm.float) -> !llvm.float
+ // CHECK: llvm.func @__nv_pow(!llvm.double) -> !llvm.double
+ // CHECK-LABEL: func @gpu_pow
+ func @gpu_pow(%arg_f32 : f32, %arg_f64 : f64) -> (f32, f64) {
+%result32 = std.pow %arg_f32, %arg_f32 : f32
+// CHECK: llvm.call @__nv_powf(%{{.*}}, %{{.*}}) : (!llvm.float) ->
!llvm.float
+%result64 = std.pow %arg_f64, %arg_f64 : f64
+// CHECK: llvm.call @__nv_pow(%{{.*}}, %{{.*}}) : (!llvm.double) ->
!llvm.double
+std.return %result32, %result64 : f32, f64
+ }
+}
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[llvm-branch-commits] [mlir] f3e8f27 - [mlir] Fix GPUToNVVM test
Author: Tres Popp
Date: 2020-12-15T18:41:16+01:00
New Revision: f3e8f27ca1170c2d74c4f1df51fa66e95588ef1a
URL:
https://github.com/llvm/llvm-project/commit/f3e8f27ca1170c2d74c4f1df51fa66e95588ef1a
DIFF:
https://github.com/llvm/llvm-project/commit/f3e8f27ca1170c2d74c4f1df51fa66e95588ef1a.diff
LOG: [mlir] Fix GPUToNVVM test
Added:
Modified:
mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Removed:
diff --git a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
index af6766bba6f4..21be3b6297e2 100644
--- a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
+++ b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
@@ -397,14 +397,14 @@ gpu.module @test_module {
// -
gpu.module @test_module {
- // CHECK: llvm.func @__nv_powf(!llvm.float) -> !llvm.float
- // CHECK: llvm.func @__nv_pow(!llvm.double) -> !llvm.double
+ // CHECK: llvm.func @__nv_powf(!llvm.float, !llvm.float) -> !llvm.float
+ // CHECK: llvm.func @__nv_pow(!llvm.double, !llvm.double) -> !llvm.double
// CHECK-LABEL: func @gpu_pow
func @gpu_pow(%arg_f32 : f32, %arg_f64 : f64) -> (f32, f64) {
-%result32 = std.pow %arg_f32, %arg_f32 : f32
-// CHECK: llvm.call @__nv_powf(%{{.*}}, %{{.*}}) : (!llvm.float) ->
!llvm.float
-%result64 = std.pow %arg_f64, %arg_f64 : f64
-// CHECK: llvm.call @__nv_pow(%{{.*}}, %{{.*}}) : (!llvm.double) ->
!llvm.double
+%result32 = std.powf %arg_f32, %arg_f32 : f32
+// CHECK: llvm.call @__nv_powf(%{{.*}}, %{{.*}}) : (!llvm.float,
!llvm.float) -> !llvm.float
+%result64 = std.powf %arg_f64, %arg_f64 : f64
+// CHECK: llvm.call @__nv_pow(%{{.*}}, %{{.*}}) : (!llvm.double,
!llvm.double) -> !llvm.double
std.return %result32, %result64 : f32, f64
}
}
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[llvm-branch-commits] [mlir] 9adc645 - [mlir] Add std.powf to ROCDL lowering.
Author: Tres Popp
Date: 2020-12-15T18:47:49+01:00
New Revision: 9adc64539f97e531b865e4864b9965b0a99fd70f
URL:
https://github.com/llvm/llvm-project/commit/9adc64539f97e531b865e4864b9965b0a99fd70f
DIFF:
https://github.com/llvm/llvm-project/commit/9adc64539f97e531b865e4864b9965b0a99fd70f.diff
LOG: [mlir] Add std.powf to ROCDL lowering.
Differential Revision: https://reviews.llvm.org/D93313
Added:
Modified:
mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
Removed:
diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
index b6f4238a4a5e..e87ca62c9b81 100644
--- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
@@ -84,7 +84,7 @@ void
mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) {
target.addIllegalDialect();
target.addIllegalOp();
+ LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>();
// TODO: Remove once we support replacing non-root ops.
target.addLegalOp();
@@ -123,6 +123,8 @@ void mlir::populateGpuToROCDLConversionPatterns(
"__ocml_log10_f64");
patterns.insert>(converter, "__ocml_log2_f32",
"__ocml_log2_f64");
+ patterns.insert>(converter, "__ocml_pow_f32",
+"__ocml_pow_f64");
patterns.insert>(converter, "__ocml_rsqrt_f32",
"__ocml_rsqrt_f64");
patterns.insert>(converter, "__ocml_sin_f32",
diff --git a/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
b/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
index c57f98571df6..dc23d436cab5 100644
--- a/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
+++ b/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
@@ -310,3 +310,18 @@ gpu.module @test_module {
std.return %result32, %result64 : f32, f64
}
}
+
+// -
+
+gpu.module @test_module {
+ // CHECK: llvm.func @__ocml_pow_f32(!llvm.float, !llvm.float) -> !llvm.float
+ // CHECK: llvm.func @__ocml_pow_f64(!llvm.double, !llvm.double) ->
!llvm.double
+ // CHECK-LABEL: func @gpu_pow
+ func @gpu_pow(%arg_f32 : f32, %arg_f64 : f64) -> (f32, f64) {
+%result32 = std.powf %arg_f32, %arg_f32 : f32
+// CHECK: llvm.call @__ocml_pow_f32(%{{.*}}, %{{.*}}) : (!llvm.float,
!llvm.float) -> !llvm.float
+%result64 = std.powf %arg_f64, %arg_f64 : f64
+// CHECK: llvm.call @__ocml_pow_f64(%{{.*}}, %{{.*}}) : (!llvm.double,
!llvm.double) -> !llvm.double
+std.return %result32, %result64 : f32, f64
+ }
+}
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[llvm-branch-commits] [mlir] c77ea40 - [mlir] Add std.pow lowering to LLVMIR
Author: Tres Popp
Date: 2020-12-15T18:54:29+01:00
New Revision: c77ea40528de7d5bf74b19819b82eeb0e5dab89d
URL:
https://github.com/llvm/llvm-project/commit/c77ea40528de7d5bf74b19819b82eeb0e5dab89d
DIFF:
https://github.com/llvm/llvm-project/commit/c77ea40528de7d5bf74b19819b82eeb0e5dab89d.diff
LOG: [mlir] Add std.pow lowering to LLVMIR
Differential Revision: https://reviews.llvm.org/D93311
Added:
Modified:
mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
mlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
Removed:
diff --git a/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
b/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
index 939bc7d50e27..f30048186a0b 100644
--- a/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
+++ b/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
@@ -1681,6 +1681,7 @@ using MulFOpLowering = VectorConvertToLLVMPattern;
using MulIOpLowering = VectorConvertToLLVMPattern;
using NegFOpLowering = VectorConvertToLLVMPattern;
using OrOpLowering = VectorConvertToLLVMPattern;
+using PowFOpLowering = VectorConvertToLLVMPattern;
using RemFOpLowering = VectorConvertToLLVMPattern;
using SelectOpLowering = OneToOneConvertToLLVMPattern;
using ShiftLeftOpLowering =
@@ -3963,6 +3964,7 @@ void mlir::populateStdToLLVMNonMemoryConversionPatterns(
MulIOpLowering,
NegFOpLowering,
OrOpLowering,
+ PowFOpLowering,
PrefetchOpLowering,
ReOpLowering,
RemFOpLowering,
diff --git a/mlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
b/mlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
index 9c709a653b27..acb894af1f38 100644
--- a/mlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
+++ b/mlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
@@ -213,3 +213,13 @@ func @call_zero_result_func() {
return
}
func private @zero_result_func()
+
+// -
+
+// CHECK-LABEL: func @powf(
+// CHECK-SAME: !llvm.double
+func @powf(%arg0 : f64) {
+ // CHECK: %[[POWF:.*]] = "llvm.intr.pow"(%arg0, %arg0) : (!llvm.double,
!llvm.double) -> !llvm.double
+ %0 = std.powf %arg0, %arg0 : f64
+ std.return
+}
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[llvm-branch-commits] [mlir] 922d3d5 - [mlir] Allow nested regions in inlineRegionAndEmitStore
Author: Tres Popp
Date: 2020-12-15T21:02:57+01:00
New Revision: 922d3d55220dfcfde1f68d17fddca5680aff9545
URL:
https://github.com/llvm/llvm-project/commit/922d3d55220dfcfde1f68d17fddca5680aff9545
DIFF:
https://github.com/llvm/llvm-project/commit/922d3d55220dfcfde1f68d17fddca5680aff9545.diff
LOG: [mlir] Allow nested regions in inlineRegionAndEmitStore
This is useful for scalar code that uses for/while loops.
This has also been confirmed to work for representing std.pow as an
scf.for loop on gpus.
Differential Revision: https://reviews.llvm.org/D93308
Added:
Modified:
mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
Removed:
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
b/mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
index d4529792624c..3a5b79176959 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
@@ -71,7 +71,6 @@ static void inlineRegionAndEmitStore(OpType op,
ArrayRef indexedValues,
BlockAndValueMapping map;
map.map(block.getArguments(), indexedValues);
for (auto &op : block.without_terminator()) {
-assert(op.getNumRegions() == 0 && "expected a non-nested region");
auto *newOp = b.clone(op, map);
map.map(op.getResults(), newOp->getResults());
}
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[llvm-branch-commits] [mlir] f43e67c - [mlir] Allow SymbolTable to update existing symbols
Author: Tres Popp
Date: 2020-12-16T00:44:40+01:00
New Revision: f43e67cc6c6f6e0da925039b28b54e44fc751267
URL:
https://github.com/llvm/llvm-project/commit/f43e67cc6c6f6e0da925039b28b54e44fc751267
DIFF:
https://github.com/llvm/llvm-project/commit/f43e67cc6c6f6e0da925039b28b54e44fc751267.diff
LOG: [mlir] Allow SymbolTable to update existing symbols
Previous behavior would fail if inserting an operation that already
existed. Now SymbolTable::insert can also be used as a way to make a
symbol's name unique even after insertion.
Further TODOs have been left over naming and consistent behavior
considerations.
Differential Revision: https://reviews.llvm.org/D93349
Added:
Modified:
mlir/include/mlir/IR/SymbolTable.h
mlir/lib/IR/SymbolTable.cpp
Removed:
diff --git a/mlir/include/mlir/IR/SymbolTable.h
b/mlir/include/mlir/IR/SymbolTable.h
index 0e3230672568..edeaab21aabe 100644
--- a/mlir/include/mlir/IR/SymbolTable.h
+++ b/mlir/include/mlir/IR/SymbolTable.h
@@ -38,7 +38,8 @@ class SymbolTable {
/// Insert a new symbol into the table, and rename it as necessary to avoid
/// collisions. Also insert at the specified location in the body of the
- /// associated operation.
+ /// associated operation if it is not already there. It is asserted that the
+ /// symbol is not inside another operation.
void insert(Operation *symbol, Block::iterator insertPt = {});
/// Return the name of the attribute used for symbol names.
diff --git a/mlir/lib/IR/SymbolTable.cpp b/mlir/lib/IR/SymbolTable.cpp
index 85c08c3a7e8f..b3bf6e169530 100644
--- a/mlir/lib/IR/SymbolTable.cpp
+++ b/mlir/lib/IR/SymbolTable.cpp
@@ -151,23 +151,35 @@ void SymbolTable::erase(Operation *symbol) {
}
}
-/// Insert a new symbol into the table and associated operation, and rename it
-/// as necessary to avoid collisions.
+// TODO: Consider if this should be renamed to something like insertOrUpdate
+/// Insert a new symbol into the table and associated operation if not already
+/// there and rename it as necessary to avoid collisions.
void SymbolTable::insert(Operation *symbol, Block::iterator insertPt) {
- auto &body = symbolTableOp->getRegion(0).front();
- if (insertPt == Block::iterator() || insertPt == body.end())
-insertPt = Block::iterator(body.getTerminator());
-
- assert(insertPt->getParentOp() == symbolTableOp &&
- "expected insertPt to be in the associated module operation");
-
- body.getOperations().insert(insertPt, symbol);
+ // The symbol cannot be the child of another op and must be the child of the
+ // symbolTableOp after this.
+ //
+ // TODO: consider if SymbolTable's constructor should behave the same.
+ if (!symbol->getParentOp()) {
+auto &body = symbolTableOp->getRegion(0).front();
+if (insertPt == Block::iterator() || insertPt == body.end())
+ insertPt = Block::iterator(body.getTerminator());
+
+assert(insertPt->getParentOp() == symbolTableOp &&
+ "expected insertPt to be in the associated module operation");
+
+body.getOperations().insert(insertPt, symbol);
+ }
+ assert(symbol->getParentOp() == symbolTableOp &&
+ "symbol is already inserted in another op");
// Add this symbol to the symbol table, uniquing the name if a conflict is
// detected.
StringRef name = getSymbolName(symbol);
if (symbolTable.insert({name, symbol}).second)
return;
+ // If the symbol was already in the table, also return.
+ if (symbolTable.lookup(name) == symbol)
+return;
// If a conflict was detected, then the symbol will not have been added to
// the symbol table. Try suffixes until we get to a unique name that works.
SmallString<128> nameBuffer(name);
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[llvm-branch-commits] [mlir] b17a181 - [mlir] Modify linalg loops test to have nested regions
Author: Tres Popp
Date: 2020-12-17T01:19:46+01:00
New Revision: b17a18156368549d090496bfe215b17a3f8a1f93
URL:
https://github.com/llvm/llvm-project/commit/b17a18156368549d090496bfe215b17a3f8a1f93
DIFF:
https://github.com/llvm/llvm-project/commit/b17a18156368549d090496bfe215b17a3f8a1f93.diff
LOG: [mlir] Modify linalg loops test to have nested regions
Differential Revision: https://reviews.llvm.org/D93418
Added:
Modified:
mlir/test/Dialect/Linalg/loops.mlir
Removed:
diff --git a/mlir/test/Dialect/Linalg/loops.mlir
b/mlir/test/Dialect/Linalg/loops.mlir
index 5a9d7330f289..7801bf1dbb56 100644
--- a/mlir/test/Dialect/Linalg/loops.mlir
+++ b/mlir/test/Dialect/Linalg/loops.mlir
@@ -1144,14 +1144,18 @@ func @generic_const_init(%arg0: memref) {
indexing_maps = #scalar_access,
library_call = "some_external_fn"
}
-func @scalar_code(%arg0: memref, %arg1 : memref, %arg2 : memref)
+func @scalar_code(%arg0: memref, %arg1 : memref, %arg2 :
memref, %arg3 : i1)
{
linalg.generic #scalar_trait
ins(%arg0, %arg1 : memref, memref)
outs(%arg2 : memref) {
^bb(%a : f32, %b : f32, %c : f32) :
-%0 = addf %a, %b : f32
-linalg.yield %0 : f32
+%result = scf.if %arg3 -> (f32) {
+ scf.yield %a : f32
+} else {
+ scf.yield %b : f32
+}
+linalg.yield %result : f32
}
return
}
@@ -1162,7 +1166,10 @@ func @scalar_code(%arg0: memref, %arg1 :
memref, %arg2 : memref)
// CHECKLOOP-NOT: scf.for
// CHECKLOOP: load %[[ARG0]][]
// CHECKLOOP: load %[[ARG1]][]
-// CHECKLOOP: addf
+// CHECKLOOP: scf.if
+// CHECKLOOP: scf.yield
+// CHECKLOOP: else
+// CHECKLOOP: scf.yield
// CHECKLOOP: store %{{.*}}, %[[ARG2]][]
// CHECKPARALLEL-LABEL: @scalar_code
@@ -1172,7 +1179,10 @@ func @scalar_code(%arg0: memref, %arg1 :
memref, %arg2 : memref)
// CHECKPARALLEL-NOT: scf.for
// CHECKPARALLEL: load %[[ARG0]][]
// CHECKPARALLEL: load %[[ARG1]][]
-// CHECKPARALLEL: addf
+// CHECKPARALLEL: scf.if
+// CHECKPARALLEL: scf.yield
+// CHECKPARALLEL: else
+// CHECKPARALLEL: scf.yield
// CHECKPARALLEL: store %{{.*}}, %[[ARG2]][]
////
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[llvm-branch-commits] [llvm] d56982b - Remove unused variables.
Author: Michael Forster
Date: 2020-12-21T16:24:43+01:00
New Revision: d56982b6f5fb17fb1fa50b31ab4b67b8d3a76c24
URL:
https://github.com/llvm/llvm-project/commit/d56982b6f5fb17fb1fa50b31ab4b67b8d3a76c24
DIFF:
https://github.com/llvm/llvm-project/commit/d56982b6f5fb17fb1fa50b31ab4b67b8d3a76c24.diff
LOG: Remove unused variables.
Differential Revision: https://reviews.llvm.org/D93635
Added:
Modified:
llvm/lib/Transforms/IPO/IROutliner.cpp
Removed:
diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp
b/llvm/lib/Transforms/IPO/IROutliner.cpp
index 4031eedced7c..c879031faf5a 100644
--- a/llvm/lib/Transforms/IPO/IROutliner.cpp
+++ b/llvm/lib/Transforms/IPO/IROutliner.cpp
@@ -429,8 +429,7 @@ findExtractedInputToOverallInputMapping(OutlinableRegion
&Region,
// It is not a constant, check if it is a sunken alloca. If it is not,
// create the mapping from extracted to overall. If it is, create the
// mapping of the index to the value.
-unsigned Found = ArgInputs.count(Input);
-assert(Found && "Input cannot be found!");
+assert(ArgInputs.count(Input) && "Input cannot be found!");
Region.ExtractedArgToAgg.insert(std::make_pair(OriginalIndex, TypeIndex));
Region.AggArgToExtracted.insert(std::make_pair(TypeIndex, OriginalIndex));
@@ -475,7 +474,6 @@ void IROutliner::findAddInputsOutputs(Module &M,
OutlinableRegion &Region) {
/// \returns a call instruction with the replaced function.
CallInst *replaceCalledFunction(Module &M, OutlinableRegion &Region) {
std::vector NewCallArgs;
- DenseMap::iterator ArgPair;
OutlinableGroup &Group = *Region.Parent;
CallInst *Call = Region.Call;
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[llvm-branch-commits] [mlir] 83274a0 - [mlir] Add SmallVector sizes
Author: Tres Popp
Date: 2020-12-22T00:48:41+01:00
New Revision: 83274a0773f6a20abdc848b448009e0195c42166
URL:
https://github.com/llvm/llvm-project/commit/83274a0773f6a20abdc848b448009e0195c42166
DIFF:
https://github.com/llvm/llvm-project/commit/83274a0773f6a20abdc848b448009e0195c42166.diff
LOG: [mlir] Add SmallVector sizes
This is a temporary fix until figuring out how to correct the forward
declare in mlir/include/mlir/Support/LLVM.h
Differential Revision: https://reviews.llvm.org/D93666
Added:
Modified:
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Removed:
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index 7b1300da1783..09c662c74477 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -198,8 +198,8 @@ void SwitchOp::build(OpBuilder &builder, OperationState
&result, Value value,
ArrayRef caseValues, BlockRange caseDestinations,
ArrayRef caseOperands,
ArrayRef branchWeights) {
- SmallVector flattenedCaseOperands;
- SmallVector caseOperandOffsets;
+ SmallVector flattenedCaseOperands;
+ SmallVector caseOperandOffsets;
int32_t offset = 0;
for (ValueRange operands : caseOperands) {
flattenedCaseOperands.append(operands.begin(), operands.end());
@@ -230,8 +230,8 @@ parseSwitchOpCases(OpAsmParser &parser, ElementsAttr
&caseValues,
SmallVectorImpl &caseOperands,
SmallVectorImpl &caseOperandTypes,
ElementsAttr &caseOperandOffsets) {
- SmallVector values;
- SmallVector offsets;
+ SmallVector values;
+ SmallVector offsets;
int32_t value, offset = 0;
do {
OptionalParseResult integerParseResult =
parser.parseOptionalInteger(value);
@@ -243,7 +243,7 @@ parseSwitchOpCases(OpAsmParser &parser, ElementsAttr
&caseValues,
values.push_back(value);
Block *destination;
-SmallVector operands;
+SmallVector operands;
if (parser.parseColon() || parser.parseSuccessor(destination))
return failure();
if (!parser.parseOptionalLParen()) {
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[llvm-branch-commits] [mlir] 6e2af4d - Revert "[mlir] Add SmallVector sizes"
Author: Tres Popp
Date: 2020-12-22T02:33:14+01:00
New Revision: 6e2af4d6046995abf1003ebacfce95415010d574
URL:
https://github.com/llvm/llvm-project/commit/6e2af4d6046995abf1003ebacfce95415010d574
DIFF:
https://github.com/llvm/llvm-project/commit/6e2af4d6046995abf1003ebacfce95415010d574.diff
LOG: Revert "[mlir] Add SmallVector sizes"
This reverts commit 83274a0773f6a20abdc848b448009e0195c42166.
Fixed in a555ca8b3d67
Added:
Modified:
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Removed:
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index 09c662c74477..7b1300da1783 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -198,8 +198,8 @@ void SwitchOp::build(OpBuilder &builder, OperationState
&result, Value value,
ArrayRef caseValues, BlockRange caseDestinations,
ArrayRef caseOperands,
ArrayRef branchWeights) {
- SmallVector flattenedCaseOperands;
- SmallVector caseOperandOffsets;
+ SmallVector flattenedCaseOperands;
+ SmallVector caseOperandOffsets;
int32_t offset = 0;
for (ValueRange operands : caseOperands) {
flattenedCaseOperands.append(operands.begin(), operands.end());
@@ -230,8 +230,8 @@ parseSwitchOpCases(OpAsmParser &parser, ElementsAttr
&caseValues,
SmallVectorImpl &caseOperands,
SmallVectorImpl &caseOperandTypes,
ElementsAttr &caseOperandOffsets) {
- SmallVector values;
- SmallVector offsets;
+ SmallVector values;
+ SmallVector offsets;
int32_t value, offset = 0;
do {
OptionalParseResult integerParseResult =
parser.parseOptionalInteger(value);
@@ -243,7 +243,7 @@ parseSwitchOpCases(OpAsmParser &parser, ElementsAttr
&caseValues,
values.push_back(value);
Block *destination;
-SmallVector operands;
+SmallVector operands;
if (parser.parseColon() || parser.parseSuccessor(destination))
return failure();
if (!parser.parseOptionalLParen()) {
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[llvm-branch-commits] [mlir] 111ae22 - [mlir] Use rewriting infrastructure in AsyncToLLVM
Author: Tres Popp
Date: 2020-12-08T17:30:01+01:00
New Revision: 111ae220a3bff944e10a0760ce344630f4efc40d
URL:
https://github.com/llvm/llvm-project/commit/111ae220a3bff944e10a0760ce344630f4efc40d
DIFF:
https://github.com/llvm/llvm-project/commit/111ae220a3bff944e10a0760ce344630f4efc40d.diff
LOG: [mlir] Use rewriting infrastructure in AsyncToLLVM
This is needed so a listener hears all changes during the dialect
conversion to allow correct rollbacks upon failure.
Differential Revision: https://reviews.llvm.org/D92685
Added:
Modified:
mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
Removed:
diff --git a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
index c36cde1054ed..361bfa2b6fad 100644
--- a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
+++ b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
@@ -386,8 +386,10 @@ static CoroMachinery setupCoroMachinery(FuncOp func) {
suspendBlock};
}
-// Adds a suspension point before the `op`, and moves `op` and all operations
-// after it into the resume block. Returns a pointer to the resume block.
+// Add a LLVM coroutine suspension point to the end of suspended block, to
+// resume execution in resume block. The caller is responsible for creating the
+// two suspended/resume blocks with the desired ops contained in each block.
+// This function merely provides the required control flow logic.
//
// `coroState` must be a value returned from the call to @llvm.coro.save(...)
// intrinsic (saved coroutine state).
@@ -399,6 +401,8 @@ static CoroMachinery setupCoroMachinery(FuncOp func) {
// "op"(...)
// ^cleanup: ...
// ^suspend: ...
+// ^resume:
+// "op"(...)
//
// After:
//
@@ -411,20 +415,17 @@ static CoroMachinery setupCoroMachinery(FuncOp func) {
// ^cleanup: ...
// ^suspend: ...
//
-static Block *addSuspensionPoint(CoroMachinery coro, Value coroState,
- Operation *op) {
+static void addSuspensionPoint(CoroMachinery coro, Value coroState,
+ Operation *op, Block *suspended, Block *resume,
+ OpBuilder &builder) {
+ Location loc = op->getLoc();
MLIRContext *ctx = op->getContext();
auto i1 = LLVM::LLVMType::getInt1Ty(ctx);
auto i8 = LLVM::LLVMType::getInt8Ty(ctx);
- Location loc = op->getLoc();
- Block *splitBlock = op->getBlock();
-
- // Split the block before `op`, newly added block is the resume block.
- Block *resume = splitBlock->splitBlock(op);
-
// Add a coroutine suspension in place of original `op` in the split block.
- OpBuilder builder = OpBuilder::atBlockEnd(splitBlock);
+ OpBuilder::InsertionGuard guard(builder);
+ builder.setInsertionPointToEnd(suspended);
auto constFalse =
builder.create(loc, i1, builder.getBoolAttr(false));
@@ -445,7 +446,7 @@ static Block *addSuspensionPoint(CoroMachinery coro, Value
coroState,
Block *resumeOrCleanup = builder.createBlock(resume);
// Suspend the coroutine ...?
- builder.setInsertionPointToEnd(splitBlock);
+ builder.setInsertionPointToEnd(suspended);
auto isNegOne = builder.create(
loc, LLVM::ICmpPredicate::eq, coroSuspend.getResult(0), constNegOne);
builder.create(loc, isNegOne, /*trueDest=*/coro.suspend,
@@ -457,12 +458,12 @@ static Block *addSuspensionPoint(CoroMachinery coro,
Value coroState,
loc, LLVM::ICmpPredicate::eq, coroSuspend.getResult(0), constZero);
builder.create(loc, isZero, /*trueDest=*/resume,
/*falseDest=*/coro.cleanup);
-
- return resume;
}
// Outline the body region attached to the `async.execute` op into a standalone
// function.
+//
+// Note that this is not reversible transformation.
static std::pair
outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
ModuleOp module = execute.getParentOfType();
@@ -518,8 +519,11 @@ outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp
execute) {
builder.create(loc, TypeRange(), kExecute, executeArgs);
// Split the entry block before the terminator.
- Block *resume = addSuspensionPoint(coro, coroSave.getResult(0),
- entryBlock->getTerminator());
+ auto *terminatorOp = entryBlock->getTerminator();
+ Block *suspended = terminatorOp->getBlock();
+ Block *resume = suspended->splitBlock(terminatorOp);
+ addSuspensionPoint(coro, coroSave.getResult(0), terminatorOp, suspended,
+ resume, builder);
// Await on all dependencies before starting to execute the body region.
builder.setInsertionPointToStart(resume);
@@ -740,7 +744,7 @@ class AwaitOpLoweringBase : public ConversionPattern {
if (isInCoroutine) {
const CoroMachinery &coro = outlined->getSecond();
- OpBuilder builder(op);
+ OpBuilder builder(op, rewriter.getListener());
MLIRContext *ctx = op->get
[llvm-branch-commits] [mlir] 7ea9492 - [mlir] Allow RegionBranchOps in dependence analysis
Author: Tres Popp
Date: 2020-12-09T22:32:04+01:00
New Revision: 7ea94922fa0d8ac6b041c0dc4cd9f8135f0e60bb
URL:
https://github.com/llvm/llvm-project/commit/7ea94922fa0d8ac6b041c0dc4cd9f8135f0e60bb
DIFF:
https://github.com/llvm/llvm-project/commit/7ea94922fa0d8ac6b041c0dc4cd9f8135f0e60bb.diff
LOG: [mlir] Allow RegionBranchOps in dependence analysis
This is to prevent assertion failures on scf.if and shape.assuming
operations where this is not enough information currently to handle any
aliasing information.
Differential Revision: https://reviews.llvm.org/D92963
Added:
Modified:
mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
Removed:
diff --git a/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
b/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
index 99e2e6ab07f2..ca2d16e8de86 100644
--- a/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
+++ b/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
@@ -43,6 +43,10 @@ Value Aliases::find(Value v) {
if (!defOp)
return v;
+// Treat RegionBranchOpInterfaces like an allocate and don't try to follow
+// the aliasing further.
+if (isa(defOp))
+ return v;
if (isa(defOp))
return v;
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[llvm-branch-commits] [llvm] bbe6764 - Remove unused variable.
Author: Tres Popp
Date: 2020-03-12T08:42:57+01:00
New Revision: bbe6764711b6ca5dff8046ed1aec867d67aafb02
URL:
https://github.com/llvm/llvm-project/commit/bbe6764711b6ca5dff8046ed1aec867d67aafb02
DIFF:
https://github.com/llvm/llvm-project/commit/bbe6764711b6ca5dff8046ed1aec867d67aafb02.diff
LOG: Remove unused variable.
Delete dead code from 8fffa40400e8719222e7f67152c12738521fa9fb.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
index e65b59416085..012cc23ca7e4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
@@ -840,7 +840,6 @@ SelectionDAGBuilder::LowerStatepoint(ImmutableStatepoint
ISP,
for (const GCRelocateInst *Relocate : ISP.getRelocates()) {
SI.GCRelocates.push_back(Relocate);
-SDValue BaseSD = getValue(Relocate->getBasePtr());
SDValue DerivedSD = getValue(Relocate->getDerivedPtr());
if (Seen.insert(DerivedSD).second) {
SI.Bases.push_back(Relocate->getBasePtr());
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