[llvm-branch-commits] [clang] 11802ec - [WebAssembly] Prototype new f64x2 conversions
Author: Thomas Lively
Date: 2021-01-20T11:28:06-08:00
New Revision: 11802eced5d67394c1dcb5acfaef38b0038c6d90
URL:
https://github.com/llvm/llvm-project/commit/11802eced5d67394c1dcb5acfaef38b0038c6d90
DIFF:
https://github.com/llvm/llvm-project/commit/11802eced5d67394c1dcb5acfaef38b0038c6d90.diff
LOG: [WebAssembly] Prototype new f64x2 conversions
As proposed in https://github.com/WebAssembly/simd/pull/383.
Differential Revision: https://reviews.llvm.org/D95012
Added:
Modified:
clang/include/clang/Basic/BuiltinsWebAssembly.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-wasm.c
llvm/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
llvm/test/MC/WebAssembly/simd-encodings.s
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def
b/clang/include/clang/Basic/BuiltinsWebAssembly.def
index 080c6b5c3a40..bb7d6d379e58 100644
--- a/clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -206,6 +206,13 @@ TARGET_BUILTIN(__builtin_wasm_widen_high_s_i32x4_i64x2,
"V2LLiV4i", "nc", "simd1
TARGET_BUILTIN(__builtin_wasm_widen_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc",
"simd128")
TARGET_BUILTIN(__builtin_wasm_widen_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc",
"simd128")
+TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc",
"simd128")
+TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc",
"simd128")
+TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4, "V4iV2d",
"nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4, "V4UiV2d",
"nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc",
"simd128")
+TARGET_BUILTIN(__builtin_wasm_promote_low_f32x4_f64x2, "V2dV4f", "nc",
"simd128")
+
TARGET_BUILTIN(__builtin_wasm_load32_zero, "V4ii*", "n", "simd128")
TARGET_BUILTIN(__builtin_wasm_load64_zero, "V2LLiLLi*", "n", "simd128")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 25ebb67c2ab6..113541bd5024 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -17220,6 +17220,46 @@ Value
*CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(IntNo);
return Builder.CreateCall(Callee, Vec);
}
+ case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
+ case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: {
+Value *Vec = EmitScalarExpr(E->getArg(0));
+unsigned IntNo;
+switch (BuiltinID) {
+case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
+ IntNo = Intrinsic::wasm_convert_low_signed;
+ break;
+case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2:
+ IntNo = Intrinsic::wasm_convert_low_unsigned;
+ break;
+}
+Function *Callee = CGM.getIntrinsic(IntNo);
+return Builder.CreateCall(Callee, Vec);
+ }
+ case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4:
+ case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4: {
+Value *Vec = EmitScalarExpr(E->getArg(0));
+unsigned IntNo;
+switch (BuiltinID) {
+case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4:
+ IntNo = Intrinsic::wasm_trunc_saturate_zero_signed;
+ break;
+case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4:
+ IntNo = Intrinsic::wasm_trunc_saturate_zero_unsigned;
+ break;
+}
+Function *Callee = CGM.getIntrinsic(IntNo);
+return Builder.CreateCall(Callee, Vec);
+ }
+ case WebAssembly::BI__builtin_wasm_demote_zero_f64x2_f32x4: {
+Value *Vec = EmitScalarExpr(E->getArg(0));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_demote_zero);
+return Builder.CreateCall(Callee, Vec);
+ }
+ case WebAssembly::BI__builtin_wasm_promote_low_f32x4_f64x2: {
+Value *Vec = EmitScalarExpr(E->getArg(0));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_promote_low);
+return Builder.CreateCall(Callee, Vec);
+ }
case WebAssembly::BI__builtin_wasm_load32_zero: {
Value *Ptr = EmitScalarExpr(E->getArg(0));
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_load32_zero);
diff --git a/clang/test/CodeGen/builtins-wasm.c
b/clang/test/CodeGen/builtins-wasm.c
index d8b61f5d285e..61fc76cd1873 100644
--- a/clang/test/CodeGen/builtins-wasm.c
+++ b/clang/test/CodeGen/builtins-wasm.c
@@ -976,6 +976,42 @@ u64x2 widen_high_u_i32x4_i64x2(u32x4 x) {
// WEBASSEMBLY: ret
}
+f64x2 convert_low_s_i32x4_f64x2(i32x4 x) {
+ return __builtin_wasm_convert_low_s_i32x4_f64x2(x);
+ // WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x)
+ // WEBASSEMBLY: ret
+}
+
+f64x2 convert_low_u_i32x4_f64x2(u32x4 x) {
+ return __
[llvm-branch-commits] [llvm] 44ee14f - [WebAssembly][NFC] Finish cleaning up SIMD tablegen
Author: Thomas Lively
Date: 2020-12-28T13:59:23-08:00
New Revision: 44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6
URL:
https://github.com/llvm/llvm-project/commit/44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6
DIFF:
https://github.com/llvm/llvm-project/commit/44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6.diff
LOG: [WebAssembly][NFC] Finish cleaning up SIMD tablegen
This commit is a follow-on to c2c2e9119e73, using the `Vec` records introduced
in that commit in the rest of the SIMD instruction definitions. Also removes
unnecessary types in output patterns.
Differential Revision: https://reviews.llvm.org/D93771
Added:
Modified:
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
Removed:
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index df4de49ee4c8..707b7e3998d0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -37,74 +37,98 @@ def ImmI#SIZE : ImmLeaf;
+// Create vector with identical lanes: splat
+def splat2 : PatFrag<(ops node:$x), (build_vector $x, $x)>;
+def splat4 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x)>;
+def splat8 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x,
+ $x, $x, $x, $x)>;
+def splat16 : PatFrag<(ops node:$x),
+ (build_vector $x, $x, $x, $x, $x, $x, $x, $x,
+$x, $x, $x, $x, $x, $x, $x, $x)>;
+
class Vec {
ValueType vt;
+ ValueType int_vt;
ValueType lane_vt;
WebAssemblyRegClass lane_rc;
int lane_bits;
ImmLeaf lane_idx;
+ PatFrag splat;
string prefix;
Vec split;
}
def I8x16 : Vec {
let vt = v16i8;
+ let int_vt = vt;
let lane_vt = i32;
let lane_rc = I32;
let lane_bits = 8;
let lane_idx = LaneIdx16;
+ let splat = splat16;
let prefix = "i8x16";
}
def I16x8 : Vec {
let vt = v8i16;
+ let int_vt = vt;
let lane_vt = i32;
let lane_rc = I32;
let lane_bits = 16;
let lane_idx = LaneIdx8;
+ let splat = splat8;
let prefix = "i16x8";
let split = I8x16;
}
def I32x4 : Vec {
let vt = v4i32;
+ let int_vt = vt;
let lane_vt = i32;
let lane_rc = I32;
let lane_bits = 32;
let lane_idx = LaneIdx4;
+ let splat = splat4;
let prefix = "i32x4";
let split = I16x8;
}
def I64x2 : Vec {
let vt = v2i64;
+ let int_vt = vt;
let lane_vt = i64;
let lane_rc = I64;
let lane_bits = 64;
let lane_idx = LaneIdx2;
+ let splat = splat2;
let prefix = "i64x2";
let split = I32x4;
}
def F32x4 : Vec {
let vt = v4f32;
+ let int_vt = v4i32;
let lane_vt = f32;
let lane_rc = F32;
let lane_bits = 32;
let lane_idx = LaneIdx4;
+ let splat = splat4;
let prefix = "f32x4";
}
def F64x2 : Vec {
let vt = v2f64;
+ let int_vt = v2i64;
let lane_vt = f64;
let lane_rc = F64;
let lane_bits = 64;
let lane_idx = LaneIdx2;
+ let splat = splat2;
let prefix = "f64x2";
}
defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2];
+defvar IntVecs = [I8x16, I16x8, I32x4, I64x2];
//===--===//
// Load and store
@@ -289,11 +313,11 @@ multiclass LoadLanePatNoOffset {
defvar load_lane_a64 = !cast("LOAD_LANE_"#vec#"_A64");
def : Pat<(vec.vt (kind (i32 I32:$addr),
(vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
-(load_lane_a32 0, 0, imm:$idx, I32:$addr, V128:$vec)>,
+(load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr32]>;
def : Pat<(vec.vt (kind (i64 I64:$addr),
(vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
-(load_lane_a64 0, 0, imm:$idx, I64:$addr, V128:$vec)>,
+(load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr64]>;
}
@@ -359,12 +383,10 @@ defm "" : SIMDStoreLane;
// Select stores with no constant offset.
multiclass StoreLanePatNoOffset {
def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32
vec.lane_idx:$idx)),
-(!cast("STORE_LANE_"#vec#"_A32")
- 0, 0, imm:$idx, I32:$addr, vec.vt:$vec)>,
+(!cast("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr32]>;
def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32
vec.lane_idx:$idx)),
-(!cast("STORE_LANE_"#vec#"_A64")
- 0, 0, imm:$idx, I64:$addr, vec.vt:$vec)>,
+(!cast("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr64]>;
}
@@ -381,16 +403,16 @@ defm : StoreLanePatNoOffset;
//===--===//
// Constant: v128.const
-multiclass ConstVec {
+multiclass ConstVec {
let isMoveImm = 1, isReMaterializab
[llvm-branch-commits] [llvm] 5e09e99 - [WebAssembly] Prototype extending pairwise add instructions
Author: Thomas Lively
Date: 2020-12-28T14:11:14-08:00
New Revision: 5e09e9979bc60f0fca0e80e7f72f1260bd1bbca5
URL:
https://github.com/llvm/llvm-project/commit/5e09e9979bc60f0fca0e80e7f72f1260bd1bbca5
DIFF:
https://github.com/llvm/llvm-project/commit/5e09e9979bc60f0fca0e80e7f72f1260bd1bbca5.diff
LOG: [WebAssembly] Prototype extending pairwise add instructions
As proposed in https://github.com/WebAssembly/simd/pull/380. This commit makes
the new instructions available only via clang builtins and LLVM intrinsics to
make their use opt-in while they are still being evaluated for inclusion in the
SIMD proposal.
Depends on D93771.
Differential Revision: https://reviews.llvm.org/D93775
Added:
Modified:
clang/include/clang/Basic/BuiltinsWebAssembly.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-wasm.c
llvm/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
llvm/test/MC/WebAssembly/simd-encodings.s
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def
b/clang/include/clang/Basic/BuiltinsWebAssembly.def
index 023365bec7f8..d6860e0b13be 100644
--- a/clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_wasm_extmul_high_i32x4_s_i64x2,
"V2LLiV4iV4i", "nc", "s
TARGET_BUILTIN(__builtin_wasm_extmul_low_i32x4_u_i64x2, "V2ULLiV4UiV4Ui",
"nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_extmul_high_i32x4_u_i64x2, "V2ULLiV4UiV4Ui",
"nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i8x16_s_i16x8, "V8sV16Sc", "nc",
"simd128")
+TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i8x16_u_i16x8, "V8UsV16Uc",
"nc", "simd128")
+
+TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i16x8_s_i32x4, "V4iV8s", "nc",
"simd128")
+TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i16x8_u_i32x4, "V4UiV8Us", "nc",
"simd128")
+
TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_signselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc",
"simd128")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 60bfa90e22fc..0c02dbfe8469 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16932,6 +16932,28 @@ Value
*CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
return Builder.CreateCall(Callee, {LHS, RHS});
}
+ case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_s_i16x8:
+ case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_u_i16x8:
+ case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_s_i32x4:
+ case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_u_i32x4: {
+Value *Vec = EmitScalarExpr(E->getArg(0));
+unsigned IntNo;
+switch (BuiltinID) {
+case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_s_i16x8:
+case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_s_i32x4:
+ IntNo = Intrinsic::wasm_extadd_pairwise_signed;
+ break;
+case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_u_i16x8:
+case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_u_i32x4:
+ IntNo = Intrinsic::wasm_extadd_pairwise_unsigned;
+ break;
+default:
+ llvm_unreachable("unexptected builtin ID");
+}
+
+Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
+return Builder.CreateCall(Callee, Vec);
+ }
case WebAssembly::BI__builtin_wasm_bitselect: {
Value *V1 = EmitScalarExpr(E->getArg(0));
Value *V2 = EmitScalarExpr(E->getArg(1));
diff --git a/clang/test/CodeGen/builtins-wasm.c
b/clang/test/CodeGen/builtins-wasm.c
index 76dd2622fe2f..a07c278c33af 100644
--- a/clang/test/CodeGen/builtins-wasm.c
+++ b/clang/test/CodeGen/builtins-wasm.c
@@ -603,6 +603,34 @@ u64x2 extmul_high_i32x4_u_i64x2(u32x4 x, u32x4 y) {
// WEBASSEMBLY-NEXT: ret
}
+i16x8 extadd_pairwise_i8x16_s_i16x8(i8x16 v) {
+ return __builtin_wasm_extadd_pairwise_i8x16_s_i16x8(v);
+ // WEBASSEMBLY: call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(
+ // WEBASSEMBLY-SAME: <16 x i8> %v)
+ // WEBASSEMBLY-NEXT: ret
+}
+
+u16x8 extadd_pairwise_i8x16_u_i16x8(u8x16 v) {
+ return __builtin_wasm_extadd_pairwise_i8x16_u_i16x8(v);
+ // WEBASSEMBLY: call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(
+ // WEBASSEMBLY-SAME: <16 x i8> %v)
+ // WEBASSEMBLY-NEXT: ret
+}
+
+i32x4 extadd_pairwise_i16x8_s_i32x4(i16x8 v) {
+ return __builtin_wasm_extadd_pairwise_i16x8_s_i32x4(v);
+ // WEBASSEMBLY: call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(
+ // WEBASSEMBLY-SAME: <8 x i16> %v)
+ // WEBASSEMBLY-NEXT: ret
+}
+
+u32x4 extadd_pairwise_i16x8_u_i32x4(u16x8 v) {
+ return __builtin_wasm_extadd_pairwise_i16x8_u_i32
[llvm-branch-commits] [clang] 497026c - [WebAssembly] Prototype prefetch instructions
Author: Thomas Lively
Date: 2021-01-05T11:32:03-08:00
New Revision: 497026c90233e82ffd3ce2438c5f9567be6dabe7
URL:
https://github.com/llvm/llvm-project/commit/497026c90233e82ffd3ce2438c5f9567be6dabe7
DIFF:
https://github.com/llvm/llvm-project/commit/497026c90233e82ffd3ce2438c5f9567be6dabe7.diff
LOG: [WebAssembly] Prototype prefetch instructions
As proposed in https://github.com/WebAssembly/simd/pull/352 and using the
opcodes used in the V8 prototype:
https://chromium-review.googlesource.com/c/v8/v8/+/2543167. These instructions
are only usable via intrinsics and clang builtins to make them opt-in while they
are being benchmarked.
Differential Revision: https://reviews.llvm.org/D93883
Added:
llvm/test/CodeGen/WebAssembly/simd-prefetch-offset.ll
Modified:
clang/include/clang/Basic/BuiltinsWebAssembly.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-wasm.c
llvm/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/test/MC/WebAssembly/simd-encodings.s
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def
b/clang/include/clang/Basic/BuiltinsWebAssembly.def
index d6860e0b13be..84482082095e 100644
--- a/clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -220,5 +220,8 @@ TARGET_BUILTIN(__builtin_wasm_store64_lane, "vLLi*V2LLiIi",
"n", "simd128")
TARGET_BUILTIN(__builtin_wasm_eq_i64x2, "V2LLiV2LLiV2LLi", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_prefetch_t, "vv*", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_prefetch_nt, "vv*", "n", "simd128")
+
#undef BUILTIN
#undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 6e98af407a9a..1e0337ca7ac3 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -17171,6 +17171,16 @@ Value
*CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_shuffle);
return Builder.CreateCall(Callee, Ops);
}
+ case WebAssembly::BI__builtin_wasm_prefetch_t: {
+Value *Ptr = EmitScalarExpr(E->getArg(0));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_prefetch_t);
+return Builder.CreateCall(Callee, Ptr);
+ }
+ case WebAssembly::BI__builtin_wasm_prefetch_nt: {
+Value *Ptr = EmitScalarExpr(E->getArg(0));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_prefetch_nt);
+return Builder.CreateCall(Callee, Ptr);
+ }
default:
return nullptr;
}
diff --git a/clang/test/CodeGen/builtins-wasm.c
b/clang/test/CodeGen/builtins-wasm.c
index a07c278c33af..83924b48542e 100644
--- a/clang/test/CodeGen/builtins-wasm.c
+++ b/clang/test/CodeGen/builtins-wasm.c
@@ -1002,3 +1002,13 @@ i8x16 shuffle(i8x16 x, i8x16 y) {
// WEBASSEMBLY-SAME: i32 15
// WEBASSEMBLY-NEXT: ret
}
+
+void prefetch_t(void *p) {
+ return __builtin_wasm_prefetch_t(p);
+ // WEBASSEMBLY: call void @llvm.wasm.prefetch.t(i8* %p)
+}
+
+void prefetch_nt(void *p) {
+ return __builtin_wasm_prefetch_nt(p);
+ // WEBASSEMBLY: call void @llvm.wasm.prefetch.nt(i8* %p)
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
index d9a6aa78fdcd..e87700ab0fcb 100644
--- a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -311,6 +311,20 @@ def int_wasm_eq :
[llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem, IntrSpeculatable]>;
+// TODO: Remove this after experiments have been run. Use the target-agnostic
+// int_prefetch if this becomes specified at some point.
+def int_wasm_prefetch_t :
+ Intrinsic<[], [llvm_ptr_ty],
+[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
+ ReadOnly>, NoCapture>],
+"", [SDNPMemOperand]>;
+
+def int_wasm_prefetch_nt :
+ Intrinsic<[], [llvm_ptr_ty],
+[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
+ ReadOnly>, NoCapture>],
+"", [SDNPMemOperand]>;
+
//===--===//
// Thread-local storage intrinsics
//===--===//
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index 18d7b642e044..cd07a142147c 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -427,7 +427,8 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser
{
bool c
[llvm-branch-commits] [llvm] a781a70 - [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
Author: Thomas Lively
Date: 2020-12-22T14:29:06-08:00
New Revision: a781a706b961a348006b604cdff8b555e62a2fcb
URL:
https://github.com/llvm/llvm-project/commit/a781a706b961a348006b604cdff8b555e62a2fcb
DIFF:
https://github.com/llvm/llvm-project/commit/a781a706b961a348006b604cdff8b555e62a2fcb.diff
LOG: [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
These instructions previously used prefixes like v8x16 to signify that they were
agnostic between float and int interpretations. We renamed these instructions to
remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and
https://github.com/WebAssembly/simd/issues/316 and this commit brings the names
in LLVM up to date.
Differential Revision: https://reviews.llvm.org/D93722
Added:
Modified:
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
llvm/test/CodeGen/WebAssembly/simd-offset.ll
llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
llvm/test/CodeGen/WebAssembly/simd.ll
llvm/test/MC/Disassembler/WebAssembly/wasm.txt
llvm/test/MC/WebAssembly/simd-encodings.s
Removed:
diff --git
a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
index fccee4b96ed5..4bc77aa68668 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
@@ -194,7 +194,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
- WASM_LOAD_STORE(LOAD_SPLAT_v8x16)
+ WASM_LOAD_STORE(LOAD8_SPLAT)
WASM_LOAD_STORE(LOAD_LANE_v16i8)
WASM_LOAD_STORE(STORE_LANE_v16i8)
return 0;
@@ -222,7 +222,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
- WASM_LOAD_STORE(LOAD_SPLAT_v16x8)
+ WASM_LOAD_STORE(LOAD16_SPLAT)
WASM_LOAD_STORE(LOAD_LANE_v8i16)
WASM_LOAD_STORE(STORE_LANE_v8i16)
return 1;
@@ -253,7 +253,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
- WASM_LOAD_STORE(LOAD_SPLAT_v32x4)
+ WASM_LOAD_STORE(LOAD32_SPLAT)
WASM_LOAD_STORE(LOAD_ZERO_v4i32)
WASM_LOAD_STORE(LOAD_LANE_v4i32)
WASM_LOAD_STORE(STORE_LANE_v4i32)
@@ -272,7 +272,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
- WASM_LOAD_STORE(LOAD_SPLAT_v64x2)
+ WASM_LOAD_STORE(LOAD64_SPLAT)
WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16)
WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16)
WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 191cdea0c0ae..e48bbaebd47e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -64,55 +64,55 @@ defm : LoadPatOffsetOnly;
defm : LoadPatGlobalAddrOffOnly;
}
-// vNxM.load_splat
-multiclass SIMDLoadSplat simdop> {
+// v128.loadX_splat
+multiclass SIMDLoadSplat simdop> {
let mayLoad = 1, UseNamedOperandTable = 1 in {
- defm LOAD_SPLAT_#vec#_A32 :
+ defm LOAD#size#_SPLAT_A32 :
SIMD_I<(outs V128:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
(outs),
(ins P2Align:$p2align, offset32_op:$off), [],
- vec#".load_splat\t$dst, ${off}(${addr})$p2align",
- vec#".load_splat\t$off$p2align", simdop>;
- defm LOAD_SPLAT_#vec#_A64 :
+ "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
+ "v128.load"#size#"_splat\t$off$p2align", simdop>;
+ defm LOAD#size#_SPLAT_A64 :
SIMD_I<(outs V128:$dst),
(ins P2Align:$p2align, offset64_op:$off, I64:$addr),
(outs),
(ins P2Align:$p2align, offset64_op:$off), [],
- vec#".load_splat\t$dst, ${off}(${addr})$p2align",
- vec#".load_splat\t$off$p2align", simdop>;
+ "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
+ "v128.load"#size#"_splat\t$off$p2align", simdop>;
}
}
-defm "" : SIMDLoadSplat<"v8x16", 7>;
-defm "" : SIM
[llvm-branch-commits] [llvm] efe7f5e - [WebAssembly][NFC] Refactor SIMD load/store tablegen defs
Author: Thomas Lively
Date: 2020-12-22T20:06:12-08:00
New Revision: efe7f5ede0b3276f3f43daca46410bb7978221fb
URL:
https://github.com/llvm/llvm-project/commit/efe7f5ede0b3276f3f43daca46410bb7978221fb
DIFF:
https://github.com/llvm/llvm-project/commit/efe7f5ede0b3276f3f43daca46410bb7978221fb.diff
LOG: [WebAssembly][NFC] Refactor SIMD load/store tablegen defs
Introduce `Vec` records, each bundling all information related to a single SIMD
lane interpretation. This lets TableGen definitions take a single Vec parameter
from which they can extract information rather than taking multiple redundant
parameters. This commit refactors all of the SIMD load and store instruction
definitions to use the new `Vec`s. Subsequent commits will similarly refactor
additional instruction definitions.
Differential Revision: https://reviews.llvm.org/D93660
Added:
Modified:
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Removed:
diff --git
a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
index 4bc77aa68668..6c819f396ddc 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
@@ -195,8 +195,8 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
WASM_LOAD_STORE(LOAD8_SPLAT)
- WASM_LOAD_STORE(LOAD_LANE_v16i8)
- WASM_LOAD_STORE(STORE_LANE_v16i8)
+ WASM_LOAD_STORE(LOAD_LANE_I8x16)
+ WASM_LOAD_STORE(STORE_LANE_I8x16)
return 0;
WASM_LOAD_STORE(LOAD16_S_I32)
WASM_LOAD_STORE(LOAD16_U_I32)
@@ -223,8 +223,8 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
WASM_LOAD_STORE(LOAD16_SPLAT)
- WASM_LOAD_STORE(LOAD_LANE_v8i16)
- WASM_LOAD_STORE(STORE_LANE_v8i16)
+ WASM_LOAD_STORE(LOAD_LANE_I16x8)
+ WASM_LOAD_STORE(STORE_LANE_I16x8)
return 1;
WASM_LOAD_STORE(LOAD_I32)
WASM_LOAD_STORE(LOAD_F32)
@@ -254,9 +254,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
WASM_LOAD_STORE(LOAD32_SPLAT)
- WASM_LOAD_STORE(LOAD_ZERO_v4i32)
- WASM_LOAD_STORE(LOAD_LANE_v4i32)
- WASM_LOAD_STORE(STORE_LANE_v4i32)
+ WASM_LOAD_STORE(LOAD_ZERO_I32x4)
+ WASM_LOAD_STORE(LOAD_LANE_I32x4)
+ WASM_LOAD_STORE(STORE_LANE_I32x4)
return 2;
WASM_LOAD_STORE(LOAD_I64)
WASM_LOAD_STORE(LOAD_F64)
@@ -273,15 +273,15 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
WASM_LOAD_STORE(LOAD64_SPLAT)
- WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16)
- WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16)
- WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32)
- WASM_LOAD_STORE(LOAD_EXTEND_U_v4i32)
- WASM_LOAD_STORE(LOAD_EXTEND_S_v2i64)
- WASM_LOAD_STORE(LOAD_EXTEND_U_v2i64)
- WASM_LOAD_STORE(LOAD_ZERO_v2i64)
- WASM_LOAD_STORE(LOAD_LANE_v2i64)
- WASM_LOAD_STORE(STORE_LANE_v2i64)
+ WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8)
+ WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8)
+ WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4)
+ WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4)
+ WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2)
+ WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2)
+ WASM_LOAD_STORE(LOAD_ZERO_I64x2)
+ WASM_LOAD_STORE(LOAD_LANE_I64x2)
+ WASM_LOAD_STORE(STORE_LANE_I64x2)
return 3;
WASM_LOAD_STORE(LOAD_V128)
WASM_LOAD_STORE(STORE_V128)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index e48bbaebd47e..df4de49ee4c8 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -37,6 +37,75 @@ def ImmI#SIZE : ImmLeaf;
+class Vec {
+ ValueType vt;
+ ValueType lane_vt;
+ WebAssemblyRegClass lane_rc;
+ int lane_bits;
+ ImmLeaf lane_idx;
+ string prefix;
+ Vec split;
+}
+
+def I8x16 : Vec {
+ let vt = v16i8;
+ let lane_vt = i32;
+ let lane_rc = I32;
+ let lane_bits = 8;
+ let lane_idx = LaneIdx16;
+ let prefix = "i8x16";
+}
+
+def I16x8 : Vec {
+ let vt = v8i16;
+ let lane_vt = i32;
+ let lane_rc = I32;
+ let lane_bits = 16;
+ let lane_idx = LaneIdx8;
+ let prefix = "i16x8";
+ let split = I8x16;
+}
+
+def I32x4 : Vec {
+ let vt = v4i32;
+ let lane_vt = i32;
+ let lane_rc = I32;
+ let lane_bits = 32;
+ let lane_idx = LaneIdx4;
+ let prefix = "i32x4";
+ let split = I16x8;
+}
+
+def I64x2 : Vec {
+ let vt = v2i64;
+ let lane_vt = i64;
+ let lane_rc = I64;
+ let lane_bits = 64;
+ let lane_idx = LaneIdx2;
+ let prefix = "i64x2";
+ let split = I32x4;
+}
+
+def F32x4 : Vec {
+ let vt = v4f32;
+ let lane_vt = f32;
+ let lane_rc = F
[llvm-branch-commits] [llvm] release/19.x: [WebAssembly] Fix feature coalescing (#110647) (PR #112431)
https://github.com/tlively approved this pull request. https://github.com/llvm/llvm-project/pull/112431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] WebAssembly: Stop directly using RuntimeLibcalls.def (PR #143054)
@@ -528,23 +528,20 @@ RuntimeLibcallSignatureTable
&getRuntimeLibcallSignatures() {
// constructor for use with a static variable
struct StaticLibcallNameMap {
StringMap Map;
- StaticLibcallNameMap() {
-static const std::pair NameLibcalls[] = {
-#define HANDLE_LIBCALL(code, name) {(const char *)name, RTLIB::code},
-#include "llvm/IR/RuntimeLibcalls.def"
-#undef HANDLE_LIBCALL
-};
-for (const auto &NameLibcall : NameLibcalls) {
- if (NameLibcall.first != nullptr &&
- getRuntimeLibcallSignatures().Table[NameLibcall.second] !=
- unsupported) {
-assert(!Map.contains(NameLibcall.first) &&
+ StaticLibcallNameMap(const Triple &TT) {
+// FIXME: This is broken if there are ever different triples compiled with
+// different libcalls.
+RTLIB::RuntimeLibcallsInfo RTCI(TT);
+for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
+ RTLIB::Libcall LC = static_cast(I);
+ const char *NameLibcall = RTCI.getLibcallName(LC);
+ if (NameLibcall != nullptr &&
+ getRuntimeLibcallSignatures().Table[LC] != unsupported) {
+assert(!Map.contains(NameLibcall) &&
"duplicate libcall names in name map");
-Map[NameLibcall.first] = NameLibcall.second;
+Map[NameLibcall] = LC;
}
}
-
-Map["emscripten_return_address"] = RTLIB::RETURN_ADDRESS;
tlively wrote:
How is this handled in the new version?
https://github.com/llvm/llvm-project/pull/143054
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