[llvm-branch-commits] [llvm] 4dae224 - [RISCV] refactor VPatBinary (NFC)
Author: ShihPo Hung
Date: 2021-01-19T19:09:56-08:00
New Revision: 4dae2247fd62f1319de6297fa5088ab1b0175d88
URL:
https://github.com/llvm/llvm-project/commit/4dae2247fd62f1319de6297fa5088ab1b0175d88
DIFF:
https://github.com/llvm/llvm-project/commit/4dae2247fd62f1319de6297fa5088ab1b0175d88.diff
LOG: [RISCV] refactor VPatBinary (NFC)
Make it easier to reuse for intrinsic vrgatherei16
which needs to encode both LMUL & EMUL in the instruction name,
like PseudoVRGATHEREI16_VV_M1_M1 and PseudoVRGATHEREI16_VV_M1_M2.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D94951
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 85826b26eedf..4e08ab0d563c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1522,32 +1522,28 @@ class VPatUnaryAnyMask :
Pat<(result_type (!cast(intrinsic_name)
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
(XLenVT GPR:$vl))),
- (!cast(inst#"_"#kind#"_"#vlmul.MX)
+ (!cast(inst)
(op1_type op1_reg_class:$rs1),
ToFPR32.ret,
(NoX0 GPR:$vl), sew)>;
class VPatBinaryMask :
@@ -1557,7 +1553,7 @@ class VPatBinaryMask(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
+ (!cast(inst#"_MASK")
(result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1),
ToFPR32.ret,
@@ -1869,21 +1865,19 @@ multiclass VPatNullaryM {
multiclass VPatBinary
{
- def : VPatBinaryNoMask;
- def : VPatBinaryMask;
+ def : VPatBinaryMask;
}
@@ -1951,9 +1945,9 @@ multiclass VPatConversion vtilist> {
foreach vti = vtilist in
-defm : VPatBinary;
}
@@ -1961,46 +1955,47 @@ multiclass VPatBinaryV_VV_INT vtilist> {
foreach vti = vtilist in {
defvar ivti = GetIntVTypeInfo.Vti;
-defm : VPatBinary;
}
}
multiclass VPatBinaryV_VX vtilist> {
- foreach vti = vtilist in
-defm : VPatBinary;
+ }
}
multiclass VPatBinaryV_VX_INT vtilist> {
foreach vti = vtilist in
-defm : VPatBinary;
}
multiclass VPatBinaryV_VI vtilist, Operand imm_type> {
foreach vti = vtilist in
-defm : VPatBinary;
}
multiclass VPatBinaryM_MM {
foreach mti = AllMasks in
-def : VPatBinaryNoMask;
+ mti.SEW, VR, VR>;
}
multiclass VPatBinaryW_VV;
}
}
@@ -2020,10 +2015,10 @@ multiclass VPatBinaryW_VX;
}
}
@@ -2033,9 +2028,9 @@ multiclass VPatBinaryW_WV;
}
}
@@ -2045,10 +2040,10 @@ multiclass VPatBinaryW_WX;
}
}
@@ -2058,9 +2053,9 @@ multiclass VPatBinaryV_WV;
}
}
@@ -2070,10 +2065,10 @@ multiclass VPatBinaryV_WX;
}
}
@@ -2083,9 +2078,9 @@ multiclass VPatBinaryV_WI;
}
}
@@ -2150,28 +2145,29 @@ multiclass VPatBinaryV_I {
multiclass VPatBinaryM_VV vtilist> {
foreach vti = vtilist in
-defm : VPatBinary;
}
multiclass VPatBinaryM_VX vtilist> {
- foreach vti = vtilist in
-defm : VPatBinary;
+ }
}
multiclass VPatBinaryM_VI vtilist> {
foreach vti = vtilist in
-defm : VPatBinary;
}
___
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[llvm-branch-commits] [llvm] bea661d - [RISCV] Add intrinsics for RVV 1.0 vrgatherei16
Author: ShihPo Hung
Date: 2021-01-21T18:38:49-08:00
New Revision: bea661d9a52f9abb4fef7cf195092e912c165d34
URL:
https://github.com/llvm/llvm-project/commit/bea661d9a52f9abb4fef7cf195092e912c165d34
DIFF:
https://github.com/llvm/llvm-project/commit/bea661d9a52f9abb4fef7cf195092e912c165d34.diff
LOG: [RISCV] Add intrinsics for RVV 1.0 vrgatherei16
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D95014
Added:
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 659010399977..cda0c86f0048 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -885,6 +885,7 @@ let TargetPrefix = "riscv" in {
defm vfslide1down : RISCVBinaryAAX;
defm vrgather : RISCVBinaryAAX;
+ defm vrgatherei16 : RISCVBinaryAAX;
def "int_riscv_vcompress" : RISCVBinaryAAAMask;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 4650c75b77fc..fd563f010cae 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1266,11 +1266,40 @@ multiclass VPseudoBinary {
+ let VLMul = lmul.value in {
+def "_" # lmul.MX # "_" # emul.MX : VPseudoBinaryNoMask;
+def "_" # lmul.MX # "_" # emul.MX # "_MASK" : VPseudoBinaryMask;
+ }
+}
+
multiclass VPseudoBinaryV_VV {
foreach m = MxList.m in
defm _VV : VPseudoBinary;
}
+multiclass VPseudoBinaryV_VV_EEW {
+ foreach m = MxList.m in {
+foreach sew = EEWList in {
+ defvar octuple_lmul = octuple_from_str.ret;
+ // emul = lmul * eew / sew
+ defvar octuple_emul = !srl(!mul(octuple_lmul, eew),
shift_amount.val);
+ if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+defvar emulMX = octuple_to_str.ret;
+defvar emul = !cast("V_" # emulMX);
+defm _VV : VPseudoBinaryEmul;
+ }
+}
+ }
+}
+
multiclass VPseudoBinaryV_VX {
foreach m = MxList.m in
defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary vtilist> {
+ foreach vti = vtilist in {
+// emul = lmul * eew / sew
+defvar vlmul = vti.LMul;
+defvar octuple_lmul = octuple_from_str.ret;
+defvar octuple_emul = !srl(!mul(octuple_lmul, eew),
shift_amount.val);
+if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+ defvar emul_str = octuple_to_str.ret;
+ defvar ivti = !cast("VI" # eew # emul_str);
+ defvar inst = instruction # "_VV_" # vti.LMul.MX # "_" # emul_str;
+ defm : VPatBinary;
+}
+ }
+}
+
multiclass VPatBinaryV_VX vtilist> {
foreach vti = vtilist in {
@@ -3403,6 +3451,7 @@ let Predicates = [HasStdExtV, HasStdExtF] in {
// 17.4. Vector Register Gather Instructions
//===--===//
defm PseudoVRGATHER: VPseudoBinaryV_VV_VX_VI;
+defm PseudoVRGATHEREI16 : VPseudoBinaryV_VV_EEW;
//===--===//
// 17.5. Vector Compress Instruction
@@ -4081,11 +4130,15 @@ let Predicates = [HasStdExtV, HasStdExtF] in {
let Predicates = [HasStdExtV] in {
defm "" : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllIntegerVectors, uimm5>;
+ defm "" : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16",
"PseudoVRGATHEREI16",
+ /* eew */ 16, AllIntegerVectors>;
} // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, HasStdExtF] in {
defm "" : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllFloatVectors, uimm5>;
+ defm "" : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16",
"PseudoVRGATHEREI16",
+ /* eew */ 16, AllFloatVectors>;
} // Predicates = [HasStdExtV, HasStdExtF]
//===--===//
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
new file mode 100644
index ..50dcdded0287
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
@@ -0,0 +1,1272 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh
-verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16(
+ ,
+ ,
+ i32);
+
+define
@intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16( %0, %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16:
[llvm-branch-commits] [llvm] 9667750 - [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
Author: ShihPo Hung
Date: 2021-01-21T18:38:49-08:00
New Revision: 96677503315e689fd3c8f5ef164d8fb9725d4bb3
URL:
https://github.com/llvm/llvm-project/commit/96677503315e689fd3c8f5ef164d8fb9725d4bb3
DIFF:
https://github.com/llvm/llvm-project/commit/96677503315e689fd3c8f5ef164d8fb9725d4bb3.diff
LOG: [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
Reviewed By: craig.topper, frasercrmck
Differential Revision: https://reviews.llvm.org/D95113
Added:
llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
llvm/test/CodeGen/RISCV/vfrece7-rv64.ll
llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 4b174b3edc31..407b27744477 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -865,6 +865,8 @@ let TargetPrefix = "riscv" in {
defm vfwnmsac : RISCVTernaryWide;
defm vfsqrt : RISCVUnaryAA;
+ defm vfrsqrte7 : RISCVUnaryAA;
+ defm vfrece7 : RISCVUnaryAA;
defm vfmin : RISCVBinaryAAX;
defm vfmax : RISCVBinaryAAX;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index fb09110acc4c..d1a823be25b6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3212,6 +3212,16 @@ defm PseudoVFWNMSAC:
VPseudoTernaryW_VV_VX;
//===--===//
defm PseudoVFSQRT : VPseudoUnaryV_V;
+//===--===//
+// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+//===--===//
+defm PseudoVFRSQRTE7 : VPseudoUnaryV_V;
+
+//===--===//
+// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
+//===--===//
+defm PseudoVFRECE7 : VPseudoUnaryV_V;
+
//===--===//
// 14.11. Vector Floating-Point Min/Max Instructions
//===--===//
@@ -3871,6 +3881,16 @@ defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac",
"PseudoVFWNMSAC", AllWidenabl
//===--===//
defm "" : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>;
+//===--===//
+// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+//===--===//
+defm "" : VPatUnaryV_V<"int_riscv_vfrsqrte7", "PseudoVFRSQRTE7",
AllFloatVectors>;
+
+//===--===//
+// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
+//===--===//
+defm "" : VPatUnaryV_V<"int_riscv_vfrece7", "PseudoVFRECE7", AllFloatVectors>;
+
//===--===//
// 14.11. Vector Floating-Point Min/Max Instructions
//===--===//
diff --git a/llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
b/llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
new file mode 100644
index ..7a810f10d47d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
@@ -0,0 +1,602 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh
-verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare @llvm.riscv.vfrece7.nxv1f16(
+ ,
+ i32);
+
+define @intrinsic_vfrece7_v_nxv1f16_nxv1f16( %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f16_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:vfrece7.v v8, v8
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vfrece7.nxv1f16(
+ %0,
+i32 %1)
+
+ ret %a
+}
+
+declare @llvm.riscv.vfrece7.mask.nxv1f16(
+ ,
+ ,
+ ,
+ i32);
+
+define @intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:vfrece7.v v8, v9, v0.t
+; CHECK-NEXT:jalr zero, 0(ra)
+entry:
+ %a = call @llvm.riscv.vfrece7.mask.nxv1
[llvm-branch-commits] [llvm] 096b02e - [RISCV] Add intrinsics for vcompress instruction
Author: ShihPo Hung
Date: 2020-12-29T18:38:15-08:00
New Revision: 096b02ebbff72c403379b28a40f14a8c48e640f8
URL:
https://github.com/llvm/llvm-project/commit/096b02ebbff72c403379b28a40f14a8c48e640f8
DIFF:
https://github.com/llvm/llvm-project/commit/096b02ebbff72c403379b28a40f14a8c48e640f8.diff
LOG: [RISCV] Add intrinsics for vcompress instruction
This patch defines vcompress intrinsics and lower to V instructions.
We work with @rogfer01 from BSC to come out this patch.
Authored-by: Roger Ferrer Ibanez
Co-Authored-by: ShihPo Hung
Differential revision: https://reviews.llvm.org/D93809
Added:
llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 8e3d6f2ed675..430687d796ba 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -189,6 +189,13 @@ let TargetPrefix = "riscv" in {
LLVMPointerType>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty],
[NoCapture>, IntrWriteMem]>, RISCVVIntrinsic;
+ // For destination vector type is the same as first source vector (with
mask).
+ // Input: (maskedoff, vector_in, mask, vl)
+ class RISCVUnaryAAMask
+: Intrinsic<[llvm_anyvector_ty],
+[LLVMMatchType<0>, LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty],
+[IntrNoMem]>, RISCVVIntrinsic;
// For destination vector type is the same as first and second source vector.
// Input: (vector_in, vector_in, vl)
class RISCVBinaryAAANoMask
@@ -680,6 +687,8 @@ let TargetPrefix = "riscv" in {
defm vrgather : RISCVBinaryAAX;
+ def "int_riscv_vcompress_mask" : RISCVUnaryAAMask;
+
defm vaaddu : RISCVSaturatingBinaryAAX;
defm vaadd : RISCVSaturatingBinaryAAX;
defm vasubu : RISCVSaturatingBinaryAAX;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index b0e3b455339f..6a89f34f9047 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -669,6 +669,27 @@ class VPseudoUnaryMOutMask:
let BaseInstr = !cast(PseudoToVInst.VInst);
}
+// Mask can be V0~V31
+class VPseudoUnaryAnyMask :
+ Pseudo<(outs RetClass:$rd),
+ (ins RetClass:$merge,
+ Op1Class:$rs2,
+ VR:$vm, GPR:$vl, ixlenimm:$sew),
+ []>,
+ RISCVVPseudo {
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+ let usesCustomInserter = 1;
+ let Constraints = "@earlyclobber $rd, $rd = $merge";
+ let Uses = [VL, VTYPE];
+ let VLIndex = 4;
+ let SEWIndex = 5;
+ let MergeOpIndex = 1;
+ let BaseInstr = !cast(PseudoToVInst.VInst);
+}
+
class VPseudoBinaryNoMask;
+ }
+}
+
multiclass VPseudoBinary;
+class VPatUnaryAnyMask :
+ Pat<(result_type (!cast(intrinsic#"_mask")
+ (result_type result_reg_class:$merge),
+ (op1_type op1_reg_class:$rs1),
+ (mask_type VR:$rs2),
+ (XLenVT GPR:$vl))),
+ (!cast(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
+ (result_type result_reg_class:$merge),
+ (op1_type op1_reg_class:$rs1),
+ (mask_type VR:$rs2),
+ (NoX0 GPR:$vl), sew)>;
+
class VPatBinaryNoMask vtilist> {
+ foreach vti = vtilist in {
+def : VPatUnaryAnyMask;
+ }
+}
+
multiclass VPatUnaryM_M
{
@@ -2645,6 +2704,11 @@ let Predicates = [HasStdExtV, HasStdExtF] in {
//===--===//
defm PseudoVRGATHER: VPseudoBinaryV_VV_VX_VI;
+//===--===//
+// 17.5. Vector Compress Instruction
+//===--===//
+defm PseudoVCOMPRESS : VPseudoUnaryV_V_AnyMask;
+
//===--===//
// Patterns.
//===--===//
@@ -3201,5 +3265,16 @@ let Predicates = [HasStdExtV, HasStdExtF] in {
AllFloatVectors, uimm5>;
} // Predicates = [HasStdExtV, HasStdExtF]
+//===--===//
+// 17.5. Vector Compress Instruction
+//===--===//
+let Predicates = [HasStdExtV] in {
+ defm "" : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS",
AllInteg
