[llvm-branch-commits] [llvm] release/19.x: Revert "[LLVM] Silence compiler-rt warning in runtimes build (#99525)" (PR #102475)
https://github.com/peterwaller-arm edited https://github.com/llvm/llvm-project/pull/102475 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: Revert "[LLVM] Silence compiler-rt warning in runtimes build (#99525)" (PR #102475)
https://github.com/peterwaller-arm edited https://github.com/llvm/llvm-project/pull/102475 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: Revert "[LLVM] Silence compiler-rt warning in runtimes build (#99525)" (PR #102475)
peterwaller-arm wrote:
Bad case:
```
/home/ubuntu/llvm-project/compiler-rt/lib/builtins/CMakeLists.txt(29):
load_llvm_config()
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(289):
if(LLVM_CONFIG_PATH AND NOT LLVM_CMAKE_DIR )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(303):
get_compiler_rt_root_source_dir(COMPILER_RT_ROOT_SRC_PATH )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(245):
if(${ROOT_DIR_VAR} STREQUAL )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(251):
set(PATH_TO_COMPILER_RT_SOURCE_ROOT )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(252):
if(DEFINED CompilerRTBuiltins_SOURCE_DIR )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(255):
set(PATH_TO_COMPILER_RT_SOURCE_ROOT ${CompilerRTBuiltins_SOURCE_DIR}/../../ )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(273):
get_filename_component(ROOT_DIR ${PATH_TO_COMPILER_RT_SOURCE_ROOT} ABSOLUTE )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(274):
if(NOT EXISTS ${ROOT_DIR} )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(280):
set(PATH_TO_CURRENT_FILE ${ROOT_DIR}/cmake/Modules/CompilerRTUtils.cmake )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(281):
if(NOT EXISTS ${PATH_TO_CURRENT_FILE} )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(285):
set(${ROOT_DIR_VAR} ${ROOT_DIR} PARENT_SCOPE )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(304):
get_filename_component(LLVM_MAIN_SRC_DIR_DEFAULT
${COMPILER_RT_ROOT_SRC_PATH}/../llvm ABSOLUTE )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(305):
if(NOT EXISTS ${LLVM_MAIN_SRC_DIR_DEFAULT} )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(312):
find_package(LLVM HINTS ${LLVM_CMAKE_DIR} )
/usr/lib/llvm-14/cmake/LLVMConfigVersion.cmake(1): set(PACKAGE_VERSION 14.0.0 )
/usr/lib/llvm-14/cmake/LLVMConfigVersion.cmake(5): if(14.0 VERSION_EQUAL
${PACKAGE_FIND_VERSION_MAJOR}.${PACKAGE_FIND_VERSION_MINOR} AND NOT 0
VERSION_LESS ${PACKAGE_FIND_VERSION_PATCH} )
```
Good case:
```
/home/ubuntu/llvm-project/compiler-rt/lib/builtins/CMakeLists.txt(28): if(NOT
LLVM_RUNTIMES_BUILD )
/home/ubuntu/llvm-project/compiler-rt/lib/builtins/CMakeLists.txt(29):
load_llvm_config()
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(289):
if(LLVM_CONFIG_PATH AND NOT LLVM_CMAKE_DIR )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(290):
message(WARNING LLVM_CONFIG_PATH is deprecated, please use LLVM_CMAKE_DIR
instead )
CMake Warning at
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake:290
(message):
LLVM_CONFIG_PATH is deprecated, please use LLVM_CMAKE_DIR instead
Call Stack (most recent call first):
CMakeLists.txt:29 (load_llvm_config)
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(296):
get_filename_component(LLVM_CMAKE_DIR ${LLVM_CONFIG_PATH} DIRECTORY )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(297):
get_filename_component(LLVM_CMAKE_DIR ${LLVM_CMAKE_DIR} DIRECTORY )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(303):
get_compiler_rt_root_source_dir(COMPILER_RT_ROOT_SRC_PATH )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(245):
if(${ROOT_DIR_VAR} STREQUAL )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(251):
set(PATH_TO_COMPILER_RT_SOURCE_ROOT )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(252):
if(DEFINED CompilerRTBuiltins_SOURCE_DIR )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(255):
set(PATH_TO_COMPILER_RT_SOURCE_ROOT ${CompilerRTBuiltins_SOURCE_DIR}/../../ )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(273):
get_filename_component(ROOT_DIR ${PATH_TO_COMPILER_RT_SOURCE_ROOT} ABSOLUTE )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(274):
if(NOT EXISTS ${ROOT_DIR} )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(280):
set(PATH_TO_CURRENT_FILE ${ROOT_DIR}/cmake/Modules/CompilerRTUtils.cmake )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(281):
if(NOT EXISTS ${PATH_TO_CURRENT_FILE} )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(285):
set(${ROOT_DIR_VAR} ${ROOT_DIR} PARENT_SCOPE )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(304):
get_filename_component(LLVM_MAIN_SRC_DIR_DEFAULT
${COMPILER_RT_ROOT_SRC_PATH}/../llvm ABSOLUTE )
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(305):
if(NOT EXISTS ${LLVM_MAIN_SRC
[llvm-branch-commits] [llvm] release/19.x: Revert "[LLVM] Silence compiler-rt warning in runtimes build (#99525)" (PR #102475)
peterwaller-arm wrote:
For reasons I don't understand, cmake is not producing debug output for the
find_package call for LLVM if I use `cmake --debug-find`. It does produce
output for other packages.
Resorting to strace -efile:
Good:
```
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(312):
find_package(LLVM HINTS /home/ubuntu/bld4 )
access("/home/ubuntu/bld4/lib/cmake/llvm/LLVMConfig.cmake", R_OK) = 0
```
Bad:
```
/home/ubuntu/llvm-project/compiler-rt/cmake/Modules/CompilerRTUtils.cmake(312):
find_package(LLVM HINTS /home/ubuntu/llvm-project/llvm/cmake/modules )
access("/usr/lib/llvm-14/cmake/LLVMConfig.cmake", R_OK) = 0
```
Not sure why cmake is ignoring the hint. It doesn't appear to test any other
directories.
https://github.com/llvm/llvm-project/pull/102475
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[llvm-branch-commits] [llvm] release/19.x: Revert "[LLVM] Silence compiler-rt warning in runtimes build (#99525)" (PR #102475)
peterwaller-arm wrote: > Do you know what LLVM_CONFIG_PATH is set to in this case? In both good and bad cases they're set to `$BUILD_DIR/bin/llvm-config`, according to what is in `$BUILD_DIR/runtimes/builtins-bins/CMakeCache.txt`, at least. https://github.com/llvm/llvm-project/pull/102475 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: Revert "[LLVM] Silence compiler-rt warning in runtimes build (#99525)" (PR #102475)
peterwaller-arm wrote: I previously wrote: > Not sure why cmake is ignoring the hint. I'm thinking; it wants a `LLVMConfig.cmake`, which is an aspect of the build, not the sources. So it seems `LLVM_CMAKE_DIR` should be set to the build directory in this case, if the compiler-rt cmake code is using this variable correctly. (I haven't made a judgement yet) https://github.com/llvm/llvm-project/pull/102475 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] bc2dad1 - [clang][aarch64][WOA64][docs] Release note for longjmp crash with /guard:cf
Author: Peter Waller Date: 2021-02-04T14:35:14Z New Revision: bc2dad1671598a87423c61c355d03db49ce76907 URL: https://github.com/llvm/llvm-project/commit/bc2dad1671598a87423c61c355d03db49ce76907 DIFF: https://github.com/llvm/llvm-project/commit/bc2dad1671598a87423c61c355d03db49ce76907.diff LOG: [clang][aarch64][WOA64][docs] Release note for longjmp crash with /guard:cf Add a release note workaround for PR47463. Bug: https://bugs.llvm.org/show_bug.cgi?id=47463 Differential Revision: https://reviews.llvm.org/D95435 Added: Modified: clang/docs/ReleaseNotes.rst Removed: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 9efd4c01f053..c17d84de320c 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -153,6 +153,11 @@ Windows Support - Implicitly add ``.exe`` suffix for MinGW targets, even when cross compiling. (This matches a change from GCC 8.) +- Windows on Arm64: programs using the C standard library's setjmp and longjmp + functions may crash with a "Security check failure or stack buffer overrun" + exception. To workaround (with reduced security), compile with + /guard:cf,nolongjmp. + C Language Changes in Clang --- ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 0fa1dda - [NFC][SVE] s/fast/contract/ in test sve-fp-combine.ll
Author: Peter Waller Date: 2021-12-08T16:06:05Z New Revision: 0fa1dda5eb642f678d9aa5f70c5e525583f653e0 URL: https://github.com/llvm/llvm-project/commit/0fa1dda5eb642f678d9aa5f70c5e525583f653e0 DIFF: https://github.com/llvm/llvm-project/commit/0fa1dda5eb642f678d9aa5f70c5e525583f653e0.diff LOG: [NFC][SVE] s/fast/contract/ in test sve-fp-combine.ll These tests doesn't currently make use of any fast math flag other than contract. This will change in D109525 when a dependency on nsz will be introduced where negation is involved. Added: Modified: llvm/test/CodeGen/AArch64/sve-fp-combine.ll Removed: diff --git a/llvm/test/CodeGen/AArch64/sve-fp-combine.ll b/llvm/test/CodeGen/AArch64/sve-fp-combine.ll index 6fcf45d9286c8..d9bf9653097c3 100644 --- a/llvm/test/CodeGen/AArch64/sve-fp-combine.ll +++ b/llvm/test/CodeGen/AArch64/sve-fp-combine.ll @@ -6,8 +6,8 @@ define @fmla_h_sel( %pred, %m1, %m2 - %add = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %add = fadd contract %acc, %mul %res = select %pred, %add, %acc ret %res } @@ -17,8 +17,8 @@ define @fmla_hx4_sel( %pred, %m1, %m2 - %add = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %add = fadd contract %acc, %mul %res = select %pred, %add, %acc ret %res } @@ -28,8 +28,8 @@ define @fmla_hx2_sel( %pred, %m1, %m2 - %add = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %add = fadd contract %acc, %mul %res = select %pred, %add, %acc ret %res } @@ -39,8 +39,8 @@ define @fmla_s_sel( %pred, %m1, %m2 - %add = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %add = fadd contract %acc, %mul %res = select %pred, %add, %acc ret %res } @@ -50,8 +50,8 @@ define @fmla_sx2_sel( %pred, %m1, %m2 - %add = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %add = fadd contract %acc, %mul %res = select %pred, %add, %acc ret %res } @@ -61,8 +61,8 @@ define @fmla_d_sel( %pred, %m1, %m2 - %add = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %add = fadd contract %acc, %mul %res = select %pred, %add, %acc ret %res } @@ -72,8 +72,8 @@ define @fmls_h_sel( %pred, %m1, %m2 - %sub = fsub fast %acc, %mul + %mul = fmul contract %m1, %m2 + %sub = fsub contract %acc, %mul %res = select %pred, %sub, %acc ret %res } @@ -83,8 +83,8 @@ define @fmls_hx4_sel( %pred, %m1, %m2 - %sub = fsub fast %acc, %mul + %mul = fmul contract %m1, %m2 + %sub = fsub contract %acc, %mul %res = select %pred, %sub, %acc ret %res } @@ -94,8 +94,8 @@ define @fmls_hx2_sel( %pred, %m1, %m2 - %sub = fsub fast %acc, %mul + %mul = fmul contract %m1, %m2 + %sub = fsub contract %acc, %mul %res = select %pred, %sub, %acc ret %res } @@ -105,8 +105,8 @@ define @fmls_s_sel( %pred, %m1, %m2 - %sub = fsub fast %acc, %mul + %mul = fmul contract %m1, %m2 + %sub = fsub contract %acc, %mul %res = select %pred, %sub, %acc ret %res } @@ -116,8 +116,8 @@ define @fmls_sx2_sel( %pred, %m1, %m2 - %sub = fsub fast %acc, %mul + %mul = fmul contract %m1, %m2 + %sub = fsub contract %acc, %mul %res = select %pred, %sub, %acc ret %res } @@ -127,8 +127,8 @@ define @fmls_d_sel( %pred, %m1, %m2 - %sub = fsub fast %acc, %mul + %mul = fmul contract %m1, %m2 + %sub = fsub contract %acc, %mul %res = select %pred, %sub, %acc ret %res } @@ -139,8 +139,8 @@ define @fmad_h( %m1, ; CHECK-NEXT:ptrue p0.h ; CHECK-NEXT:fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT:ret - %mul = fmul fast %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -150,8 +150,8 @@ define @fmad_hx4( %m1, %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -161,8 +161,8 @@ define @fmad_hx2( %m1, %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -172,8 +172,8 @@ define @fmad_s( %m1, %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -183,8 +183,8 @@ define @fmad_sx2( %m1, %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -194,8 +194,8 @@ define @fmad_d( %m1, %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -205,8 +205,8 @@ define @fmla_h( %acc, ; CHECK-NEXT:ptrue p0.h ; CHECK-NEXT:fmla z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT:ret - %mul = fmul fast %m1, %m2 - %res = fadd fast %acc, %mul + %mul = fmul contract %m1, %m2 + %res = fadd contract %acc, %mul ret %res } @@ -216,8 +216,8
[llvm-branch-commits] [llvm] dfd3384 - [InstCombine] Update valueCoversEntireFragment to use TypeSize
Author: Francesco Petrogalli
Date: 2021-01-06T17:14:59Z
New Revision: dfd3384feeca334c59b5a32254e425491acd716a
URL:
https://github.com/llvm/llvm-project/commit/dfd3384feeca334c59b5a32254e425491acd716a
DIFF:
https://github.com/llvm/llvm-project/commit/dfd3384feeca334c59b5a32254e425491acd716a.diff
LOG: [InstCombine] Update valueCoversEntireFragment to use TypeSize
* Update valueCoversEntireFragment to use TypeSize.
* Add a regression test.
* Assertions have been added to protect untested codepaths.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D91806
Added:
llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
Modified:
llvm/lib/Transforms/Utils/Local.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/Local.cpp
b/llvm/lib/Transforms/Utils/Local.cpp
index f2bc8a801a75..e3bdfbae9287 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1340,16 +1340,22 @@ static bool PhiHasDebugValue(DILocalVariable *DIVar,
/// least n bits.
static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
const DataLayout &DL = DII->getModule()->getDataLayout();
- uint64_t ValueSize = DL.getTypeAllocSizeInBits(ValTy);
- if (auto FragmentSize = DII->getFragmentSizeInBits())
-return ValueSize >= *FragmentSize;
+ TypeSize ValueSize = DL.getTypeAllocSizeInBits(ValTy);
+ if (Optional FragmentSize = DII->getFragmentSizeInBits()) {
+assert(!ValueSize.isScalable() &&
+ "Fragments don't work on scalable types.");
+return ValueSize.getFixedSize() >= *FragmentSize;
+ }
// We can't always calculate the size of the DI variable (e.g. if it is a
// VLA). Try to use the size of the alloca that the dbg intrinsic describes
// intead.
if (DII->isAddressOfVariable())
if (auto *AI = dyn_cast_or_null(DII->getVariableLocation()))
- if (auto FragmentSize = AI->getAllocationSizeInBits(DL))
-return ValueSize >= *FragmentSize;
+ if (Optional FragmentSize = AI->getAllocationSizeInBits(DL)) {
+assert(ValueSize.isScalable() == FragmentSize->isScalable() &&
+ "Both sizes should agree on the scalable flag.");
+return TypeSize::isKnownGE(ValueSize, *FragmentSize);
+ }
// Could not determine size of variable. Conservatively return false.
return false;
}
diff --git a/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
b/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
new file mode 100644
index ..8b96fccdd9e9
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
@@ -0,0 +1,36 @@
+; RUN: opt -instcombine -S < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; This test is defending against a TypeSize message raised in the method
+; `valueCoversEntireFragment` in Local.cpp because of an implicit cast from
+; `TypeSize` to `uint64_t`. This particular TypeSize message only occurred when
+; debug info was available.
+
+; If this check fails please read
+; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on
+; how to resolve it.
+; This test must not produce any warnings. Prior to this test being introduced,
+; it produced a warning containing the text "TypeSize is not scalable".
+; WARN-NOT: warning:
+
+; CHECK-LABEL: @debug_local_scalable(
+define @debug_local_scalable(
%tostore) {
+ %vx = alloca , align 16
+ call void @llvm.dbg.declare(metadata * %vx, metadata
!3, metadata !DIExpression()), !dbg !5
+ store %tostore, * %vx, align 16
+ %ret = call @f(* %vx)
+ ret %ret
+}
+
+declare @f(*)
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1)
+!1 = !DIFile(filename: "/tmp/test.c", directory: "/tmp/")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !DILocalVariable(scope: !4)
+!4 = distinct !DISubprogram(unit: !0)
+!5 = !DILocation(scope: !4)
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[llvm-branch-commits] [llvm] 3e357ec - [llvm][NFC] Disallow all warnings in TypeSize tests
Author: Peter Waller
Date: 2021-01-06T17:17:07Z
New Revision: 3e357ecd44a610ab39c33c85a15cf6437891655b
URL:
https://github.com/llvm/llvm-project/commit/3e357ecd44a610ab39c33c85a15cf6437891655b
DIFF:
https://github.com/llvm/llvm-project/commit/3e357ecd44a610ab39c33c85a15cf6437891655b.diff
LOG: [llvm][NFC] Disallow all warnings in TypeSize tests
This is a follow-up to a request from a reviewer [0]. The text may change in
the future and these tests should not produce any warning output.
[0] https://reviews.llvm.org/D91806#inline-879243
Reviewed By: sdesmalen, david-arm
Differential Revision: https://reviews.llvm.org/D94161
Added:
Modified:
llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
llvm/test/CodeGen/AArch64/sve-redundant-store.ll
llvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-scalable-load-in-loop.ll
Removed:
diff --git a/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
b/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
index 4bc6889e3fdd..019aa0148365 100644
--- a/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
@@ -6,7 +6,7 @@
; warning when performing cost analysis.
; If this check fails please read test/CodeGen/AArch64/README for instructions
on how to resolve it.
-; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+; WARN-NOT: warning:
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %retval =
getelementptr
define * @gep_scalable_vector(* %ptr) {
diff --git
a/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
b/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
index 7e4e5bacd12b..050b09925b46 100644
---
a/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
+++
b/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
@@ -6,7 +6,7 @@
; warning in the llvm::getGEPInductionOperand function.
; If this check fails please read test/CodeGen/AArch64/README for instructions
on how to resolve it.
-; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+; WARN-NOT: warning:
define void @get_gep_induction_operand_typesize_warning(i64 %n, * %a) {
entry:
diff --git
a/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
b/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
index d1a980f51c37..e8d25883a6cc 100644
---
a/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
+++
b/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
@@ -7,7 +7,7 @@
; this function was previously unaware of scalable types.
; If this check fails please read test/CodeGen/AArch64/README for instructions
on how to resolve it.
-; CHECK-NOT: warning: {{.*}}TypeSize is not scalable
+; CHECK-NOT: warning:
define void @runtime_pointer_checking_insert_typesize(* %a,
* %b) {
diff --git
a/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
b/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
index fd5b85a57de1..ba8d8cb0a0d2 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
@@ -5,7 +5,7 @@
; node linked to a scalable store.
; If this check fails please read test/CodeGen/AArch64/README for instructions
on how to resolve it.
-; CHECK-NOT: warning: {{.*}}TypeSize is not scalable
+; CHECK-NOT: warning:
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
diff --git a/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
b/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
index 65fd1e22de02..0673272c19be 100644
--- a/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
+++ b/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
@@ -3,7 +3,7 @@
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
; If this check fails please read test/CodeGen/AArch64/README for instructions
on how to resolve it.
-; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+; WARN-NOT: warning:
; #include
; #include
diff --git
a/llvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
b/llvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
index c20128d5fe02..68e840bfe251 100644
---
a/llvm/test/Trans
[llvm-branch-commits] [llvm] fef8113 - [SVE] Optimize new cases for lowerConvertToSVBool
Author: Alban Bridonneau
Date: 2022-05-09T10:17:57Z
New Revision: fef81131d92ef71f43640667b6fc88b241aebe50
URL:
https://github.com/llvm/llvm-project/commit/fef81131d92ef71f43640667b6fc88b241aebe50
DIFF:
https://github.com/llvm/llvm-project/commit/fef81131d92ef71f43640667b6fc88b241aebe50.diff
LOG: [SVE] Optimize new cases for lowerConvertToSVBool
Converts to SVBool are already considered as a nop, if they
are converting an operand from a ptrue or a cmp, because
they zero the extra predicate lanes by construction.
This patch adds 2 similar cases:
- The wide cmp, which were not directly recognized by the test
for other forms of cmp
- Splats of 1, which will be generated as ptrue, and as such
will also zero the extra predicate lines.
Reviewed By: paulwalker-arm, peterwaller-arm
Differential Revision: https://reviews.llvm.org/D124908
Added:
llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret-no-streaming.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpge.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpgt.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmphi.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmphs.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmplo.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpls.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmplt.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpne.ll
llvm/test/CodeGen/AArch64/sve-vector-splat.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9d7a8e67374d..dc99ed0b4066 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4181,10 +4181,26 @@ static SDValue lowerConvertToSVBool(SDValue Op,
SelectionDAG &DAG) {
case AArch64ISD::SETCC_MERGE_ZERO:
return Reinterpret;
case ISD::INTRINSIC_WO_CHAIN:
-if (InOp.getConstantOperandVal(0) == Intrinsic::aarch64_sve_ptrue)
+switch (InOp.getConstantOperandVal(0)) {
+case Intrinsic::aarch64_sve_ptrue:
+case Intrinsic::aarch64_sve_cmpeq_wide:
+case Intrinsic::aarch64_sve_cmpne_wide:
+case Intrinsic::aarch64_sve_cmpge_wide:
+case Intrinsic::aarch64_sve_cmpgt_wide:
+case Intrinsic::aarch64_sve_cmplt_wide:
+case Intrinsic::aarch64_sve_cmple_wide:
+case Intrinsic::aarch64_sve_cmphs_wide:
+case Intrinsic::aarch64_sve_cmphi_wide:
+case Intrinsic::aarch64_sve_cmplo_wide:
+case Intrinsic::aarch64_sve_cmpls_wide:
return Reinterpret;
+}
}
+ // Splat vectors of 1 will generate ptrue instructions
+ if (ISD::isConstantSplatVectorAllOnes(InOp.getNode()))
+return Reinterpret;
+
// Otherwise, zero the newly introduced lanes.
SDValue Mask = getPTrue(DAG, DL, InVT, AArch64SVEPredPattern::all);
SDValue MaskReinterpret =
diff --git
a/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret-no-streaming.ll
b/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret-no-streaming.ll
new file mode 100644
index ..bc5cdb48fef6
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret-no-streaming.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+; This test should belong in sve-intrinsics-reinterpret.ll, but uses types
+; that are invalid with sve-streaming
+
+define @reinterpret_bool_from_splat() {
+; CHECK-LABEL: reinterpret_bool_from_splat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ptrue p0.d
+; CHECK-NEXT:ret
+ %ins = insertelement undef, i1 1, i32 0
+ %splat = shufflevector %ins, undef,
zeroinitializer
+ %out = call
@llvm.aarch64.sve.convert.to.svbool.nxv2i1( %splat)
+ ret %out
+}
+
+declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1()
+
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
b/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
index 37b6c80c19a0..3e9a21da0eb7 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
@@ -102,7 +102,22 @@ define @reinterpret_cmpgt( %p, %2
}
+; The first reinterpret should prevent the second one from being simplified as
a nop
+define @chained_reinterpret() {
+; CHECK-LABEL: chained_reinterpret:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ptrue p0.b
+; CHECK-NEXT:ptrue p1.d
+; CHECK-NEXT:and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT:ret
+ %in = tail call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+ %cast2 = call
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( %in)
+ %out = tail call
@llvm.aarch64.sve
[llvm-branch-commits] [llvm] 65e311a - [LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6
Author: Peter Waller
Date: 2022-07-04T14:13:16Z
New Revision: 65e311ac0da02203c188caea9f171f4496ca9178
URL:
https://github.com/llvm/llvm-project/commit/65e311ac0da02203c188caea9f171f4496ca9178
DIFF:
https://github.com/llvm/llvm-project/commit/65e311ac0da02203c188caea9f171f4496ca9178.diff
LOG: [LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6
Fixes #56374.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 25ec712f43dd..c9e9136bbd3c 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5937,10 +5937,11 @@
LoopVectorizationCostModel::calculateRegisterUsage(ArrayRef VFs) {
LLVM_DEBUG(dbgs() << "LV(REG): Calculating max register usage:\n");
- auto GetRegUsage = [&TTI = TTI](Type *Ty, ElementCount VF) -> unsigned {
+ const auto &TTICapture = TTI;
+ auto GetRegUsage = [&TTICapture](Type *Ty, ElementCount VF) -> unsigned {
if (Ty->isTokenTy() || !VectorType::isValidElementType(Ty))
return 0;
-return TTI.getRegUsageForType(VectorType::get(Ty, VF));
+return TTICapture.getRegUsageForType(VectorType::get(Ty, VF));
};
for (unsigned int i = 0, s = IdxToInstr.size(); i < s; ++i) {
___
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[llvm-branch-commits] [llvm] 9a1794f - [gn build] (manually) port 6b3956e123db
Author: Peter Waller
Date: 2022-07-04T14:13:16Z
New Revision: 9a1794f0b9ba25de3a23daac6e4e600a755634cd
URL:
https://github.com/llvm/llvm-project/commit/9a1794f0b9ba25de3a23daac6e4e600a755634cd
DIFF:
https://github.com/llvm/llvm-project/commit/9a1794f0b9ba25de3a23daac6e4e600a755634cd.diff
LOG: [gn build] (manually) port 6b3956e123db
Added:
Modified:
llvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
b/llvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
index 0b9fa454dec65..ad9e6d47b9205 100644
--- a/llvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
@@ -3,6 +3,7 @@ executable("llvm-reduce") {
"//llvm/lib/CodeGen/MIRParser",
"//llvm/lib/IR",
"//llvm/lib/IRReader",
+"//llvm/lib/LTO",
"//llvm/lib/Support",
"//llvm/lib/Target",
"//llvm/lib/Target:TargetsToBuild",
___
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[llvm-branch-commits] [clang] 2fd3147 - [AArch64][Driver][SVE] Push missing SVE feature error from driver to frontend
Author: Peter Waller
Date: 2020-12-10T12:34:26Z
New Revision: 2fd31472992f39eaa57e86b6c10969978ada2c3e
URL:
https://github.com/llvm/llvm-project/commit/2fd31472992f39eaa57e86b6c10969978ada2c3e
DIFF:
https://github.com/llvm/llvm-project/commit/2fd31472992f39eaa57e86b6c10969978ada2c3e.diff
LOG: [AArch64][Driver][SVE] Push missing SVE feature error from driver to
frontend
... and give more guidance to users.
If specifying -msve-vector-bits on a non-SVE target, clang would say:
error: '-msve-vector-bits' is not supported without SVE enabled
1. The driver lacks logic for "implied features".
This would result in this error being raised for -march=...+sve2,
even though +sve2 implies +sve.
2. Feature implication is well modelled in LLVM, so push the error down
the stack.
3. Hint to the user what flag they need to consider setting.
Now clang fails later, when the feature is used, saying:
aarch64-sve-vector-bits.c:42:41: error: 'arm_sve_vector_bits' attribute is
not supported on targets missing 'sve'; specify an appropriate -march= or -mcpu=
typedef svint32_t noflag __attribute__((arm_sve_vector_bits(256)));
Move clang/test/Sema/{neon => arm}-vector-types-support.c and put tests for
this warning together in one place.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92487
Added:
clang/test/Sema/arm-vector-types-support.c
Modified:
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/lib/Sema/SemaType.cpp
clang/test/Driver/aarch64-sve-vector-bits.c
Removed:
clang/test/Sema/neon-vector-types-support.c
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 8ca176d3bb43..0e85be8f058b 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -534,9 +534,6 @@ def err_drv_cannot_mix_options : Error<"cannot specify '%1'
along with '%0'">;
def err_drv_invalid_object_mode : Error<"OBJECT_MODE setting %0 is not
recognized and is not a valid setting.">;
-def err_drv_invalid_sve_vector_bits : Error<
- "'-msve-vector-bits' is not supported without SVE enabled">;
-
def err_aix_default_altivec_abi : Error<
"The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi'
for the extended Altivec ABI">;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 97773d35a694..363bcc1d383d 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -2843,7 +2843,8 @@ def warn_unsupported_target_attribute
"attribute ignored">,
InGroup;
def err_attribute_unsupported
-: Error<"%0 attribute is not supported for this target">;
+: Error<"%0 attribute is not supported on targets missing %1;"
+" specify an appropriate -march= or -mcpu=">;
// The err_*_attribute_argument_not_int are separate because they're used by
// VerifyIntegerConstantExpression.
def err_aligned_attribute_argument_not_int : Error<
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 0fc531b8c3a0..fca6d95d361b 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -381,12 +381,6 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (V8_6Pos != std::end(Features))
V8_6Pos = Features.insert(std::next(V8_6Pos), {"+i8mm", "+bf16"});
- bool HasSve = llvm::is_contained(Features, "+sve");
- // -msve-vector-bits= flag is valid only if SVE is enabled.
- if (Args.hasArg(options::OPT_msve_vector_bits_EQ))
-if (!HasSve)
- D.Diag(diag::err_drv_invalid_sve_vector_bits);
-
if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
options::OPT_munaligned_access)) {
if (A->getOption().matches(options::OPT_mno_unaligned_access))
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index fbdbfbc9f8ec..6485bebc0e8e 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -7799,7 +7799,8 @@ static void HandleNeonVectorTypeAttr(QualType &CurType,
const ParsedAttr &Attr,
// not to need a separate attribute)
if (!S.Context.getTargetInfo().hasFeature("neon") &&
!S.Context.getTargetInfo().hasFeature("mve")) {
-S.Diag(Attr.getLoc(), diag::err_attribute_unsupported) << Attr;
+S.Diag(Attr.getLoc(), diag::err_attribute_unsupported)
+<< Attr << "'neon' or 'mve'";
Attr.setInvalid();
return;
}
@@ -7842,7 +7843,7 @@ static void HandleArmSveVectorBitsTypeAttr(QualType
&CurType, ParsedAttr &Attr,
Sem
[llvm-branch-commits] [clang] 2315e98 - [AArch64][Driver][SVE] Push missing SVE feature error from driver to frontend
Author: Peter Waller
Date: 2020-12-10T12:43:14Z
New Revision: 2315e9874c92bf625ec84a5f45a4fa28bfbc16ce
URL:
https://github.com/llvm/llvm-project/commit/2315e9874c92bf625ec84a5f45a4fa28bfbc16ce
DIFF:
https://github.com/llvm/llvm-project/commit/2315e9874c92bf625ec84a5f45a4fa28bfbc16ce.diff
LOG: [AArch64][Driver][SVE] Push missing SVE feature error from driver to
frontend
... and give more guidance to users.
If specifying -msve-vector-bits on a non-SVE target, clang would say:
error: '-msve-vector-bits' is not supported without SVE enabled
1. The driver lacks logic for "implied features".
This would result in this error being raised for -march=...+sve2,
even though +sve2 implies +sve.
2. Feature implication is well modelled in LLVM, so push the error down
the stack.
3. Hint to the user what flag they need to consider setting.
Now clang fails later, when the feature is used, saying:
aarch64-sve-vector-bits.c:42:41: error: 'arm_sve_vector_bits' attribute is
not supported on targets missing 'sve'; specify an appropriate -march= or -mcpu=
typedef svint32_t noflag __attribute__((arm_sve_vector_bits(256)));
Move clang/test/Sema/{neon => arm}-vector-types-support.c and put tests for
this warning together in one place.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92487
Added:
clang/test/Sema/arm-vector-types-support.c
Modified:
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/lib/Sema/SemaType.cpp
clang/test/Driver/aarch64-sve-vector-bits.c
Removed:
clang/test/Sema/neon-vector-types-support.c
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 8ca176d3bb43..0e85be8f058b 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -534,9 +534,6 @@ def err_drv_cannot_mix_options : Error<"cannot specify '%1'
along with '%0'">;
def err_drv_invalid_object_mode : Error<"OBJECT_MODE setting %0 is not
recognized and is not a valid setting.">;
-def err_drv_invalid_sve_vector_bits : Error<
- "'-msve-vector-bits' is not supported without SVE enabled">;
-
def err_aix_default_altivec_abi : Error<
"The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi'
for the extended Altivec ABI">;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 97773d35a694..363bcc1d383d 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -2843,7 +2843,8 @@ def warn_unsupported_target_attribute
"attribute ignored">,
InGroup;
def err_attribute_unsupported
-: Error<"%0 attribute is not supported for this target">;
+: Error<"%0 attribute is not supported on targets missing %1;"
+" specify an appropriate -march= or -mcpu=">;
// The err_*_attribute_argument_not_int are separate because they're used by
// VerifyIntegerConstantExpression.
def err_aligned_attribute_argument_not_int : Error<
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 0fc531b8c3a0..fca6d95d361b 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -381,12 +381,6 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (V8_6Pos != std::end(Features))
V8_6Pos = Features.insert(std::next(V8_6Pos), {"+i8mm", "+bf16"});
- bool HasSve = llvm::is_contained(Features, "+sve");
- // -msve-vector-bits= flag is valid only if SVE is enabled.
- if (Args.hasArg(options::OPT_msve_vector_bits_EQ))
-if (!HasSve)
- D.Diag(diag::err_drv_invalid_sve_vector_bits);
-
if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
options::OPT_munaligned_access)) {
if (A->getOption().matches(options::OPT_mno_unaligned_access))
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index fbdbfbc9f8ec..6485bebc0e8e 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -7799,7 +7799,8 @@ static void HandleNeonVectorTypeAttr(QualType &CurType,
const ParsedAttr &Attr,
// not to need a separate attribute)
if (!S.Context.getTargetInfo().hasFeature("neon") &&
!S.Context.getTargetInfo().hasFeature("mve")) {
-S.Diag(Attr.getLoc(), diag::err_attribute_unsupported) << Attr;
+S.Diag(Attr.getLoc(), diag::err_attribute_unsupported)
+<< Attr << "'neon' or 'mve'";
Attr.setInvalid();
return;
}
@@ -7842,7 +7843,7 @@ static void HandleArmSveVectorBitsTypeAttr(QualType
&CurType, ParsedAttr &Attr,
Sem
