[llvm-branch-commits] [llvm] 2aeaaf8 - [GlobalISel] Add missing operand update when copy is required
Author: Gabriel Hjort Åkerlund
Date: 2021-01-20T10:32:52+01:00
New Revision: 2aeaaf841b58b2a6721f9271ae897e392fd0b357
URL:
https://github.com/llvm/llvm-project/commit/2aeaaf841b58b2a6721f9271ae897e392fd0b357
DIFF:
https://github.com/llvm/llvm-project/commit/2aeaaf841b58b2a6721f9271ae897e392fd0b357.diff
LOG: [GlobalISel] Add missing operand update when copy is required
When constraining an operand register using constrainOperandRegClass(),
the function may emit a COPY in case the provided register class does
not match the current operand register class. However, the operand
itself is not updated to make use of the COPY, thereby resulting in
incorrect code. This patch fixes that bug by updating the machine
operand accordingly.
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D91244
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/include/llvm/CodeGen/GlobalISel/Utils.h
llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
index bf9991eb08de..5b8243a93e7f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
@@ -527,16 +527,6 @@ class InstructionSelector {
"Subclasses must override this with a tablegen-erated function");
}
- /// Constrain a register operand of an instruction \p I to a specified
- /// register class. This could involve inserting COPYs before (for uses) or
- /// after (for defs) and may replace the operand of \p I.
- /// \returns whether operand regclass constraining succeeded.
- bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
- const TargetRegisterClass &RC,
- const TargetInstrInfo &TII,
- const TargetRegisterInfo &TRI,
- const RegisterBankInfo &RBI) const;
-
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
const MachineRegisterInfo &MRI) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
index bcb84c337f5e..82e26b0bc355 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
@@ -1058,8 +1058,12 @@ bool InstructionSelector::executeMatchTable(
int64_t OpIdx = MatchTable[CurrentIdx++];
int64_t RCEnum = MatchTable[CurrentIdx++];
assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
- constrainOperandRegToRegClass(*OutMIs[InsnID].getInstr(), OpIdx,
-*TRI.getRegClass(RCEnum), TII, TRI, RBI);
+ MachineInstr &I = *OutMIs[InsnID].getInstr();
+ MachineFunction &MF = *I.getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
+ MachineOperand &MO = I.getOperand(OpIdx);
+ constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
dbgs() << CurrentIdx << ":
GIR_ConstrainOperandRC(OutMIs["
<< InsnID << "], " << OpIdx << ", " << RCEnum
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index 9bd5180f7222..ed75cde6f316 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -52,9 +52,10 @@ Register constrainRegToClass(MachineRegisterInfo &MRI,
/// Constrain the Register operand OpIdx, so that it is now constrained to the
/// TargetRegisterClass passed as an argument (RegClass).
-/// If this fails, create a new virtual register in the correct class and
-/// insert a COPY before \p InsertPt if it is a use or after if it is a
-/// definition. The debug location of \p InsertPt is used for the new copy.
+/// If this fails, create a new virtual register in the correct class and
insert
+/// a COPY before \p InsertPt if it is a use or after if it is a definition.
+/// In both cases, the function also updates the register of RegMo. The debug
+/// location of \p InsertPt is used for the new copy.
///
/// \return The virtual register constrained to the right register class.
Register constrainOperandRegClass(const MachineFunction &MF,
@@ -64,12 +65,13 @@ Register constrainOperandRegClass(const MachineFunction &MF,
[llvm-branch-commits] [llvm] 2b4716d - [MC] Use std::make_tuple to make some toolchains happy again
Author: Mikael Holmen
Date: 2021-01-21T14:05:14+01:00
New Revision: 2b4716d6dff1c9a5e64b3487a0b2388e3ff18b30
URL:
https://github.com/llvm/llvm-project/commit/2b4716d6dff1c9a5e64b3487a0b2388e3ff18b30
DIFF:
https://github.com/llvm/llvm-project/commit/2b4716d6dff1c9a5e64b3487a0b2388e3ff18b30.diff
LOG: [MC] Use std::make_tuple to make some toolchains happy again
My toolchain (LLVM 8.0, libstdc++ 5.4.0) complained with:
12:27:43 ../lib/MC/MCDwarf.cpp:814:10: error: chosen constructor is explicit in
copy-initialization
12:27:43 return {Offset, Size, SetDelta};
12:27:43 ^~~~
12:27:43
/proj/flexasic/app/llvm/8.0/bin/../lib/gcc/x86_64-unknown-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19:
note: explicit constructor declared here
12:27:43 constexpr tuple(_UElements&&... __elements)
12:27:43 ^
12:27:43 1 error generated.
This commit adds explicit calls to std::make_tuple to work around
the problem.
Added:
Modified:
llvm/lib/MC/MCDwarf.cpp
Removed:
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index 410ca296eaf2..f86d4266a1eb 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -811,7 +811,7 @@ MCDwarfLineAddr::fixedEncode(MCContext &Context, int64_t
LineDelta,
OS << char(dwarf::DW_LNS_copy);
}
- return {Offset, Size, SetDelta};
+ return std::make_tuple(Offset, Size, SetDelta);
}
// Utility function to write a tuple for .debug_abbrev.
___
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[llvm-branch-commits] [llvm] 3c1d015 - [GlobalISel][TableGen] Fix ConstrainOperandRC bug
Author: Gabriel Hjort Åkerlund
Date: 2021-01-05T09:30:04+01:00
New Revision: 3c1d015edc755e8f3fa9c2a92d0b9bc81ba4d5fd
URL:
https://github.com/llvm/llvm-project/commit/3c1d015edc755e8f3fa9c2a92d0b9bc81ba4d5fd
DIFF:
https://github.com/llvm/llvm-project/commit/3c1d015edc755e8f3fa9c2a92d0b9bc81ba4d5fd.diff
LOG: [GlobalISel][TableGen] Fix ConstrainOperandRC bug
TableGen would pick the largest RC for constraining the operands, which
could potentially be an unallocatable RC. This patch removes selection
of unallocatable RCs.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93945
Added:
Modified:
llvm/test/TableGen/GlobalISelEmitterSubreg.td
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/CodeGenTarget.h
llvm/utils/TableGen/GlobalISelEmitter.cpp
Removed:
diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
index e8dc4a9ac4a0..2865cbc70038 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
@@ -36,6 +36,11 @@ def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>;
def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
def SUBSOME_INSN2 : I<(outs SRegs:$dst), (ins SOP:$src), []>;
+// Adding this enables the tests below to check that we are not using this
class
+// for constraining the operand register classes, since it is unallocatable.
+let isAllocatable = 0 in
+def SuperDRegs : MyClass<32, [i32], (add DRegs, ERegs)>;
+
// We should skip cases where we don't have a given register class for the
// subregister source.
// SKIPPED: def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32
(IMPLICIT_DEF)), i16:$src, sub0)>;
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp
b/llvm/utils/TableGen/CodeGenTarget.cpp
index 37bce3afa05a..2ed29b10fba6 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -344,7 +344,8 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
Optional
CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
CodeGenRegBank &RegBank,
-const CodeGenSubRegIndex *SubIdx) const {
+const CodeGenSubRegIndex *SubIdx,
+bool MustBeAllocatable) const {
std::vector Candidates;
auto &RegClasses = RegBank.getRegClasses();
@@ -360,6 +361,10 @@ CodeGenTarget::getSuperRegForSubReg(const
ValueTypeByHwMode &ValueTy,
if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
continue;
+// If necessary, check that it is allocatable.
+if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
+ continue;
+
// We have a register class which supports both the value type and
// subregister index. Remember it.
Candidates.push_back(SubClassWithSubReg);
diff --git a/llvm/utils/TableGen/CodeGenTarget.h
b/llvm/utils/TableGen/CodeGenTarget.h
index cc5bbe7a8bfe..1852bac15511 100644
--- a/llvm/utils/TableGen/CodeGenTarget.h
+++ b/llvm/utils/TableGen/CodeGenTarget.h
@@ -111,7 +111,8 @@ class CodeGenTarget {
/// covers \p SubIdx if it exists.
Optional
getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
- const CodeGenSubRegIndex *SubIdx) const;
+ const CodeGenSubRegIndex *SubIdx,
+ bool MustBeAllocatable = false) const;
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp
b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 07130e4e0ab7..29ca558580fe 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4998,7 +4998,8 @@ GlobalISelEmitter::inferSuperRegisterClass(const
TypeSetByHwMode &Ty,
// Use the information we found above to find a minimal register class which
// supports the subregister and type we want.
auto RC =
- Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx);
+ Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx,
+ /* MustBeAllocatable */ true);
if (!RC)
return None;
return *RC;
___
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[llvm-branch-commits] [lld] 496fb70 - [MachO] Fix enum-int mismatch warning
Author: Gabriel Hjort Åkerlund
Date: 2020-12-28T17:39:41+01:00
New Revision: 496fb70b141ccbfaba9761294f3b4b97717096a3
URL:
https://github.com/llvm/llvm-project/commit/496fb70b141ccbfaba9761294f3b4b97717096a3
DIFF:
https://github.com/llvm/llvm-project/commit/496fb70b141ccbfaba9761294f3b4b97717096a3.diff
LOG: [MachO] Fix enum-int mismatch warning
Change-Id: Ie637dc7761144e5552b05a9c286f1e736579823d
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D91520
Added:
Modified:
lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
Removed:
diff --git a/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
b/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
index 42ac711bc9dc..ddfd1764f7e1 100644
--- a/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
+++ b/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
@@ -1561,7 +1561,7 @@ void Util::addExportInfo(const lld::File &atomFile,
NormalizedFile &nFile) {
uint32_t Util::fileFlags() {
// FIXME: these need to determined at runtime.
if (_ctx.outputMachOType() == MH_OBJECT) {
-return _subsectionsViaSymbols ? MH_SUBSECTIONS_VIA_SYMBOLS : 0;
+return _subsectionsViaSymbols ? (uint32_t)MH_SUBSECTIONS_VIA_SYMBOLS : 0;
} else {
uint32_t flags = MH_DYLDLINK;
if (!_ctx.useFlatNamespace())
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[llvm-branch-commits] [llvm] b9a7c89 - [MIRPrinter] Fix incorrect output of unnamed stack names
Author: Gabriel Hjort Åkerlund
Date: 2020-12-28T18:01:40+01:00
New Revision: b9a7c89d4322b261b65eb96d678a9d38b776cb60
URL:
https://github.com/llvm/llvm-project/commit/b9a7c89d4322b261b65eb96d678a9d38b776cb60
DIFF:
https://github.com/llvm/llvm-project/commit/b9a7c89d4322b261b65eb96d678a9d38b776cb60.diff
LOG: [MIRPrinter] Fix incorrect output of unnamed stack names
The MIRParser expects unnamed stack entries to have empty names ('').
In case of unnamed alloca instructions, the MIRPrinter would output
'', which caused the MIRParser to reject the generated
code.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93685
Added:
llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
Modified:
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/test/CodeGen/PowerPC/alloca-crspill.ll
Removed:
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 25f785342d04..eae174019b56 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -415,7 +415,7 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction
&YMF,
YamlObject.ID = ID;
if (const auto *Alloca = MFI.getObjectAllocation(I))
YamlObject.Name.Value = std::string(
- Alloca->hasName() ? Alloca->getName() : "");
+ Alloca->hasName() ? Alloca->getName() : "");
YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
? yaml::MachineStackObject::SpillSlot
: MFI.isVariableSizedObjectIndex(I)
diff --git a/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
new file mode 100644
index ..c7e87e3f62a6
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
@@ -0,0 +1,23 @@
+; RUN: llc -O0 -march aarch64 -global-isel -stop-after=irtranslator -o - %s |
llc -x mir -march aarch64 -run-pass=none -o - | FileCheck %s
+
+define i16 @unnamed_stack() {
+entry:
+ ; CHECK-NAME: unnamed_stack
+ ; CHECK: stack:
+ ; CHECK-NEXT: - { id: 0, name: '',
+ ; CHECK: %0:_(p0) = G_FRAME_INDEX %stack.0
+ %0 = alloca i16
+ %1 = load i16, i16* %0
+ ret i16 %1
+}
+
+define i16 @named_stack() {
+entry:
+ ; CHECK-NAME: named_stack
+ ; CHECK: stack:
+ ; CHECK-NEXT: - { id: 0, name: ptr,
+ ; CHECK: %0:_(p0) = G_FRAME_INDEX %stack.0.ptr
+ %ptr = alloca i16
+ %0 = load i16, i16* %ptr
+ ret i16 %0
+}
diff --git a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
index f52e305fb05c..b71a9ff6d49b 100644
--- a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
+++ b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
@@ -49,8 +49,8 @@ declare signext i32 @do_something(double*)
; CHECK64-NEXT: debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
; CHECK64-NEXT: stack:
-; CHECK64-NEXT: - { id: 0, name: '', type: variable-sized,
offset: -8,
-; CHECK64-NEXT: alignment: 1, stack-id: default, callee-saved-register:
'', callee-saved-restored: true,
+; CHECK64-NEXT: - { id: 0, name: '', type: variable-sized, offset: -8,
alignment: 1,
+; CHECK64-NEXT: stack-id: default, callee-saved-register: '',
callee-saved-restored: true,
; CHECK64-NEXT: local-offset: 0, debug-info-variable: '',
debug-info-expression: '',
; CHECK64-NEXT: debug-info-location: '' }
; CHECK64-NEXT: - { id: 1, name: '', type: default, offset: -16, size: 8,
alignment: 8,
@@ -68,8 +68,8 @@ declare signext i32 @do_something(double*)
; CHECK32-NEXT: debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
; CHECK32-NEXT: stack:
-; CHECK32-NEXT: - { id: 0, name: '', type: variable-sized,
offset: -4,
-; CHECK32-NEXT: alignment: 1, stack-id: default, callee-saved-register:
'', callee-saved-restored: true,
+; CHECK32-NEXT: - { id: 0, name: '', type: variable-sized, offset: -4,
alignment: 1,
+; CHECK32-NEXT: stack-id: default, callee-saved-register: '',
callee-saved-restored: true,
; CHECK32-NEXT: local-offset: 0, debug-info-variable: '',
debug-info-expression: '',
; CHECK32-NEXT: debug-info-location: '' }
; CHECK32-NEXT: - { id: 1, name: '', type: default, offset: -8, size: 4,
alignment: 4,
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[llvm-branch-commits] [llvm] faf848a - [Inline] Fix in handling of ptrtoint in InlineCost
Author: Mikael Holmen
Date: 2020-11-23T14:33:06+01:00
New Revision: faf848ac321801ba92b1d3038fccc84988d46ac8
URL:
https://github.com/llvm/llvm-project/commit/faf848ac321801ba92b1d3038fccc84988d46ac8
DIFF:
https://github.com/llvm/llvm-project/commit/faf848ac321801ba92b1d3038fccc84988d46ac8.diff
LOG: [Inline] Fix in handling of ptrtoint in InlineCost
ConstantOffsetPtrs contains mappings from a Value to a base pointer and
an offset. The offset is typed and has a size, and at least when dealing
with ptrtoint, it could happen that we had a mapping from a ptrtoint
with type i32 to an offset with type i16. This could later cause
problems, showing up in PR 47969 and PR 38500.
In PR 47969 we ended up in an assert complaining that trunc i16 to i16
is invalid and in Pr 38500 that a cmp on an i32 and i16 value isn't
valid.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D90610
Added:
llvm/test/Transforms/Inline/inline-ptrtoint-different-sizes.ll
Modified:
llvm/lib/Analysis/InlineCost.cpp
Removed:
diff --git a/llvm/lib/Analysis/InlineCost.cpp
b/llvm/lib/Analysis/InlineCost.cpp
index 8a4b779e5084..80be0040e7b3 100644
--- a/llvm/lib/Analysis/InlineCost.cpp
+++ b/llvm/lib/Analysis/InlineCost.cpp
@@ -1101,7 +1101,7 @@ bool CallAnalyzer::visitPtrToInt(PtrToIntInst &I) {
// integer is large enough to represent the pointer.
unsigned IntegerSize = I.getType()->getScalarSizeInBits();
unsigned AS = I.getOperand(0)->getType()->getPointerAddressSpace();
- if (IntegerSize >= DL.getPointerSizeInBits(AS)) {
+ if (IntegerSize == DL.getPointerSizeInBits(AS)) {
std::pair BaseAndOffset =
ConstantOffsetPtrs.lookup(I.getOperand(0));
if (BaseAndOffset.first)
diff --git a/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll b/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll
new file mode 100644
index ..b412504a800c
--- /dev/null
+++ b/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll
@@ -0,0 +1,40 @@
+; RUN: opt < %s -inline -S | FileCheck %s
+
+; InlineCost used to have problems with the ptrtoint, leading to
+; crashes when visiting the trunc in pr48908_help and the icmp in
+; pr38500_help.
+
+target datalayout = "p:16:16"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @pr48980_help(i16* %p) {
+ %cast = ptrtoint i16* %p to i32
+ %sub = sub i32 %cast, %cast
+ %conv = trunc i32 %sub to i16
+ ret void
+}
+
+define void @pr48980(i16* %x) {
+ call void @pr48980_help(i16* %x)
+ ret void
+}
+
+; CHECK-LABEL: @pr48980(i16* %x)
+; CHECK-NOT: call
+; CHECK: ret void
+
+define void @pr38500_help(i16* %p) {
+ %cast = ptrtoint i16* %p to i32
+ %sub = sub i32 %cast, %cast
+ %cmp = icmp eq i32 %sub, 0
+ ret void
+}
+
+define void @pr38500(i16* %x) {
+ call void @pr38500_help(i16* %x)
+ ret void
+}
+
+; CHECK-LABEL: @pr38500(i16* %x)
+; CHECK-NOT: call
+; CHECK: ret void
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[llvm-branch-commits] [llvm] 410c150 - [test] Update PR reference in testcase [NFC]
Author: Mikael Holmen
Date: 2020-11-23T15:12:50+01:00
New Revision: 410c150abb20b71895ea75749b1393647c7ec79f
URL:
https://github.com/llvm/llvm-project/commit/410c150abb20b71895ea75749b1393647c7ec79f
DIFF:
https://github.com/llvm/llvm-project/commit/410c150abb20b71895ea75749b1393647c7ec79f.diff
LOG: [test] Update PR reference in testcase [NFC]
The testcase was added in faf848ac32 to test the fix of PR 47969, but
it was named pr48980 (which happens to be the TR number in my downstream
issue system).
Added:
Modified:
llvm/test/Transforms/Inline/inline-ptrtoint-different-sizes.ll
Removed:
diff --git a/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll b/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll
index b412504a800c..818792fb55a9 100644
--- a/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll
+++ b/llvm/test/Transforms/Inline/inline-ptrtoint-
diff erent-sizes.ll
@@ -1,25 +1,25 @@
; RUN: opt < %s -inline -S | FileCheck %s
; InlineCost used to have problems with the ptrtoint, leading to
-; crashes when visiting the trunc in pr48908_help and the icmp in
+; crashes when visiting the trunc in pr47969_help and the icmp in
; pr38500_help.
target datalayout = "p:16:16"
target triple = "x86_64-unknown-linux-gnu"
-define void @pr48980_help(i16* %p) {
+define void @pr47969_help(i16* %p) {
%cast = ptrtoint i16* %p to i32
%sub = sub i32 %cast, %cast
%conv = trunc i32 %sub to i16
ret void
}
-define void @pr48980(i16* %x) {
- call void @pr48980_help(i16* %x)
+define void @pr47969(i16* %x) {
+ call void @pr47969_help(i16* %x)
ret void
}
-; CHECK-LABEL: @pr48980(i16* %x)
+; CHECK-LABEL: @pr47969(i16* %x)
; CHECK-NOT: call
; CHECK: ret void
___
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