[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

2025-03-18 Thread Mariusz Sikora via llvm-branch-commits 

https://github.com/mariusz-sikora-at-amd updated 
https://github.com/llvm/llvm-project/pull/130041

>From b62b5fb5137585872f7a10950bc08f28383e3eea Mon Sep 17 00:00:00 2001
From: Ivan Kosarev 
Date: Mon, 3 Mar 2025 05:34:48 -0500
Subject: [PATCH 1/4] [AMDGPU] Support image_bvh8_intersect_ray instruction and
 intrinsic.

---
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  | 11 +++
 .../AMDGPU/AMDGPUInstructionSelector.cpp  |  1 +
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 21 +++--
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h  |  3 +-
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  | 18 ++--
 llvm/lib/Target/AMDGPU/MIMGInstructions.td| 32 ---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 ++--
 llvm/lib/Target/AMDGPU/SIInstructions.td  |  8 ++
 .../AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll  | 87 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vimage.s|  3 +
 llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s  |  3 +
 .../Disassembler/AMDGPU/gfx12_dasm_vimage.txt |  3 +
 12 files changed, 171 insertions(+), 35 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index a1cfcfa8e67d6..33aca93735074 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2812,6 +2812,17 @@ def int_amdgcn_image_bvh_dual_intersect_ray :
  llvm_v3f32_ty, llvm_v2i32_ty, llvm_v4i32_ty],
 [IntrReadMem, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
 
+// , , 
+//   llvm.amdgcn.image.bvh8.intersect.ray , ,
+//, ,
+//, ,
+//
+def int_amdgcn_image_bvh8_intersect_ray :
+  Intrinsic<[llvm_v10i32_ty, llvm_v3f32_ty, llvm_v3f32_ty],
+[llvm_i64_ty, llvm_float_ty, llvm_i8_ty, llvm_v3f32_ty,
+ llvm_v3f32_ty, llvm_i32_ty, llvm_v4i32_ty],
+[IntrReadMem, IntrWillReturn]>;
+
 // llvm.amdgcn.permlane16.var 
 def int_amdgcn_permlane16_var : 
ClangBuiltin<"__builtin_amdgcn_permlane16_var">,
   Intrinsic<[llvm_i32_ty],
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 0f9096d4cec5b..20abe4bc77dd1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4101,6 +4101,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
   }
   case AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY:
   case AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY:
+  case AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY:
 return selectBVHIntersectRayIntrinsic(I);
   case AMDGPU::G_SBFX:
   case AMDGPU::G_UBFX:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 03d75d006c982..761770ebe1c20 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -7183,8 +7183,8 @@ bool 
AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(
   return true;
 }
 
-bool AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
-   MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(
+MachineInstr &MI, MachineIRBuilder &B) const {
   const LLT S32 = LLT::scalar(32);
   const LLT V2S32 = LLT::fixed_vector(2, 32);
 
@@ -7207,17 +7207,21 @@ bool 
AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
 return false;
   }
 
+  bool IsBVH8 = cast(MI).getIntrinsicID() ==
+Intrinsic::amdgcn_image_bvh8_intersect_ray;
   const unsigned NumVDataDwords = 10;
-  const unsigned NumVAddrDwords = 12;
-  int Opcode = AMDGPU::getMIMGOpcode(AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
- AMDGPU::MIMGEncGfx12, NumVDataDwords,
- NumVAddrDwords);
+  const unsigned NumVAddrDwords = IsBVH8 ? 11 : 12;
+  int Opcode = AMDGPU::getMIMGOpcode(
+  IsBVH8 ? AMDGPU::IMAGE_BVH8_INTERSECT_RAY
+ : AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
+  AMDGPU::MIMGEncGfx12, NumVDataDwords, NumVAddrDwords);
   assert(Opcode != -1);
 
   auto RayExtentInstanceMaskVec = B.buildMergeLikeInstr(
   V2S32, {RayExtent, B.buildAnyExt(S32, InstanceMask)});
 
-  B.buildInstr(AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
+  B.buildInstr(IsBVH8 ? AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY
+  : AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
   .addDef(DstReg)
   .addDef(DstOrigin)
   .addDef(DstDir)
@@ -7583,7 +7587,8 @@ bool 
AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
   case Intrinsic::amdgcn_image_bvh_intersect_ray:
 return legalizeBVHIntersectRayIntrinsic(MI, B);
   case Intrinsic::amdgcn_image_bvh_dual_intersect_ray:
-return legalizeBVHDualIntrinsic(MI, B);
+  c

[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

2025-03-16 Thread Mariusz Sikora via llvm-branch-commits 

https://github.com/mariusz-sikora-at-amd updated 
https://github.com/llvm/llvm-project/pull/130041

>From b62b5fb5137585872f7a10950bc08f28383e3eea Mon Sep 17 00:00:00 2001
From: Ivan Kosarev 
Date: Mon, 3 Mar 2025 05:34:48 -0500
Subject: [PATCH 1/3] [AMDGPU] Support image_bvh8_intersect_ray instruction and
 intrinsic.

---
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  | 11 +++
 .../AMDGPU/AMDGPUInstructionSelector.cpp  |  1 +
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 21 +++--
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h  |  3 +-
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  | 18 ++--
 llvm/lib/Target/AMDGPU/MIMGInstructions.td| 32 ---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 ++--
 llvm/lib/Target/AMDGPU/SIInstructions.td  |  8 ++
 .../AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll  | 87 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vimage.s|  3 +
 llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s  |  3 +
 .../Disassembler/AMDGPU/gfx12_dasm_vimage.txt |  3 +
 12 files changed, 171 insertions(+), 35 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index a1cfcfa8e67d6..33aca93735074 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2812,6 +2812,17 @@ def int_amdgcn_image_bvh_dual_intersect_ray :
  llvm_v3f32_ty, llvm_v2i32_ty, llvm_v4i32_ty],
 [IntrReadMem, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
 
+// , , 
+//   llvm.amdgcn.image.bvh8.intersect.ray , ,
+//, ,
+//, ,
+//
+def int_amdgcn_image_bvh8_intersect_ray :
+  Intrinsic<[llvm_v10i32_ty, llvm_v3f32_ty, llvm_v3f32_ty],
+[llvm_i64_ty, llvm_float_ty, llvm_i8_ty, llvm_v3f32_ty,
+ llvm_v3f32_ty, llvm_i32_ty, llvm_v4i32_ty],
+[IntrReadMem, IntrWillReturn]>;
+
 // llvm.amdgcn.permlane16.var 
 def int_amdgcn_permlane16_var : 
ClangBuiltin<"__builtin_amdgcn_permlane16_var">,
   Intrinsic<[llvm_i32_ty],
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 0f9096d4cec5b..20abe4bc77dd1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4101,6 +4101,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
   }
   case AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY:
   case AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY:
+  case AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY:
 return selectBVHIntersectRayIntrinsic(I);
   case AMDGPU::G_SBFX:
   case AMDGPU::G_UBFX:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 03d75d006c982..761770ebe1c20 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -7183,8 +7183,8 @@ bool 
AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(
   return true;
 }
 
-bool AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
-   MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(
+MachineInstr &MI, MachineIRBuilder &B) const {
   const LLT S32 = LLT::scalar(32);
   const LLT V2S32 = LLT::fixed_vector(2, 32);
 
@@ -7207,17 +7207,21 @@ bool 
AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
 return false;
   }
 
+  bool IsBVH8 = cast(MI).getIntrinsicID() ==
+Intrinsic::amdgcn_image_bvh8_intersect_ray;
   const unsigned NumVDataDwords = 10;
-  const unsigned NumVAddrDwords = 12;
-  int Opcode = AMDGPU::getMIMGOpcode(AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
- AMDGPU::MIMGEncGfx12, NumVDataDwords,
- NumVAddrDwords);
+  const unsigned NumVAddrDwords = IsBVH8 ? 11 : 12;
+  int Opcode = AMDGPU::getMIMGOpcode(
+  IsBVH8 ? AMDGPU::IMAGE_BVH8_INTERSECT_RAY
+ : AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
+  AMDGPU::MIMGEncGfx12, NumVDataDwords, NumVAddrDwords);
   assert(Opcode != -1);
 
   auto RayExtentInstanceMaskVec = B.buildMergeLikeInstr(
   V2S32, {RayExtent, B.buildAnyExt(S32, InstanceMask)});
 
-  B.buildInstr(AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
+  B.buildInstr(IsBVH8 ? AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY
+  : AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
   .addDef(DstReg)
   .addDef(DstOrigin)
   .addDef(DstDir)
@@ -7583,7 +7587,8 @@ bool 
AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
   case Intrinsic::amdgcn_image_bvh_intersect_ray:
 return legalizeBVHIntersectRayIntrinsic(MI, B);
   case Intrinsic::amdgcn_image_bvh_dual_intersect_ray:
-return legalizeBVHDualIntrinsic(MI, B);
+  c

[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

2025-03-19 Thread Mariusz Sikora via llvm-branch-commits 


@@ -1509,18 +1509,18 @@ multiclass MIMG_Gather 
 : MIMG_Gather;
 
-class MIMG_IntersectRay_Helper {
-  int num_addrs = !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11));
+class MIMG_IntersectRay_Helper {
+  int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 
11)));
   RegisterClass RegClass = MIMGAddrSize.RegClass;
   int VAddrDwords = !srl(RegClass.Size, 5);
 
   int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
   RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
   list GFX11PlusAddrTypes =
-!if(isDual, [VReg_64, VReg_64, VReg_96, VReg_96, VReg_64],
- !if(IsA16,
-  [node_ptr_type, VGPR_32, VReg_96, VReg_96],
-  [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]));
+ !cond(!eq(isBVH8, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, 
VGPR_32],
+   !eq(isDual, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, 
VReg_64],
+   !eq(IsA16,  0) : [node_ptr_type, VGPR_32, VReg_96, VReg_96, 
VReg_96],
+   !eq(IsA16,  1) : [node_ptr_type, VGPR_32, VReg_96, VReg_96]);

mariusz-sikora-at-amd wrote:

Done, thanks

https://github.com/llvm/llvm-project/pull/130041
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[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

2025-03-08 Thread Mariusz Sikora via llvm-branch-commits 

https://github.com/mariusz-sikora-at-amd created 
https://github.com/llvm/llvm-project/pull/130041

None

>From 2377e74544b379a34b1623df2269c3e173496994 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev 
Date: Mon, 3 Mar 2025 05:34:48 -0500
Subject: [PATCH] [AMDGPU] Support image_bvh8_intersect_ray instruction and
 intrinsic.

---
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  | 11 +++
 .../AMDGPU/AMDGPUInstructionSelector.cpp  |  1 +
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 21 +++--
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h  |  3 +-
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  | 18 ++--
 llvm/lib/Target/AMDGPU/MIMGInstructions.td| 32 ---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 ++--
 llvm/lib/Target/AMDGPU/SIInstructions.td  |  8 ++
 .../AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll  | 87 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vimage.s|  3 +
 llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s  |  3 +
 .../Disassembler/AMDGPU/gfx12_dasm_vimage.txt |  3 +
 12 files changed, 171 insertions(+), 35 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index f93439b30523e..d0ce9f0b8322d 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2812,6 +2812,17 @@ def int_amdgcn_image_bvh_dual_intersect_ray :
  llvm_v3f32_ty, llvm_v2i32_ty, llvm_v4i32_ty],
 [IntrReadMem, IntrWillReturn]>;
 
+// , , 
+//   llvm.amdgcn.image.bvh8.intersect.ray , ,
+//, ,
+//, ,
+//
+def int_amdgcn_image_bvh8_intersect_ray :
+  Intrinsic<[llvm_v10i32_ty, llvm_v3f32_ty, llvm_v3f32_ty],
+[llvm_i64_ty, llvm_float_ty, llvm_i8_ty, llvm_v3f32_ty,
+ llvm_v3f32_ty, llvm_i32_ty, llvm_v4i32_ty],
+[IntrReadMem, IntrWillReturn]>;
+
 // llvm.amdgcn.permlane16.var 
 def int_amdgcn_permlane16_var : 
ClangBuiltin<"__builtin_amdgcn_permlane16_var">,
   Intrinsic<[llvm_i32_ty],
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 9c3bdd74a5cb0..8777a440c613b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4090,6 +4090,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
   }
   case AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY:
   case AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY:
+  case AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY:
 return selectBVHIntersectRayIntrinsic(I);
   case AMDGPU::G_SBFX:
   case AMDGPU::G_UBFX:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index cd0554a5c5b99..3e4c946ee9010 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -7183,8 +7183,8 @@ bool 
AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(
   return true;
 }
 
-bool AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
-   MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(
+MachineInstr &MI, MachineIRBuilder &B) const {
   const LLT S32 = LLT::scalar(32);
   const LLT V2S32 = LLT::fixed_vector(2, 32);
 
@@ -7207,11 +7207,14 @@ bool 
AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
 return false;
   }
 
+  bool IsBVH8 = cast(MI).getIntrinsicID() ==
+Intrinsic::amdgcn_image_bvh8_intersect_ray;
   const unsigned NumVDataDwords = 10;
-  const unsigned NumVAddrDwords = 12;
-  int Opcode = AMDGPU::getMIMGOpcode(AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
- AMDGPU::MIMGEncGfx12, NumVDataDwords,
- NumVAddrDwords);
+  const unsigned NumVAddrDwords = IsBVH8 ? 11 : 12;
+  int Opcode = AMDGPU::getMIMGOpcode(
+  IsBVH8 ? AMDGPU::IMAGE_BVH8_INTERSECT_RAY
+ : AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
+  AMDGPU::MIMGEncGfx12, NumVDataDwords, NumVAddrDwords);
   assert(Opcode != -1);
 
   SmallVector Ops;
@@ -7223,7 +7226,8 @@ bool 
AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
   Ops.push_back(RayDir);
   Ops.push_back(Offsets);
 
-  auto MIB = B.buildInstr(AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
+  auto MIB = B.buildInstr(IsBVH8 ? AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY
+ : AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
  .addDef(DstReg)
  .addDef(DstOrigin)
  .addDef(DstDir)
@@ -7587,7 +7591,8 @@ bool 
AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
   case Intrinsic::amdgcn_image_bvh_intersect_ray:
 return legalizeBVHIntersectRayIntrinsic(MI, B);
   case Intrinsic::a

[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

2025-03-10 Thread Mariusz Sikora via llvm-branch-commits 

mariusz-sikora-at-amd wrote:

ping

https://github.com/llvm/llvm-project/pull/130041
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