from:"Lei Huang via llvm\-branch\-commits"

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 approved this pull request.

Just some nits for spacing.  Otherwise LGTM
Thx

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Lei Huang via llvm-branch-commits



@@ -327,6 +352,12 @@ Changes to the LLVM tools
 
 * llvm-objcopy now supports ``--gap-fill`` and ``--pad-to`` options, for
   ELF input and binary output files only.
+* Supported parsing XCOFF auxiliary symbols in obj2yaml.

lei137 wrote:

nit: should be consistent for this section. Since other entries are all 
separated by empty line, we should follow suite.

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Lei Huang via llvm-branch-commits



@@ -163,6 +163,30 @@ Changes to the MIPS Backend
 
 Changes to the PowerPC Backend
 --
+* LLJIT's JIT linker now defaults to JITLink on 64-bit ELFv2 targets.

lei137 wrote:

nit: Please add an empty line before this line.

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 edited https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Lei Huang via llvm-branch-commits



@@ -163,6 +163,30 @@ Changes to the MIPS Backend
 
 Changes to the PowerPC Backend
 --
+* LLJIT's JIT linker now defaults to JITLink on 64-bit ELFv2 targets.
+* Initial-exec TLS model is supported on AIX.
+* Implemented new resource based scheduling model of POWER7 and POWER8.
+* ``frexp`` libcall now references correct symbol name for ``fp128``.
+* Optimized materialization of 64-bit immediates, code generation of
+  ``vec_promote`` and atomics.
+

lei137 wrote:

nit: don't need this empty line.

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [llvm] dda7ef0 - [PowerPC] Update release notes for changes to PowerPC for V12.0

2021-02-19 Thread Lei Huang via llvm-branch-commits


Author: Lei Huang
Date: 2021-02-19T19:24:05Z
New Revision: dda7ef025bc66ea326f5a8bda8c5b8534d21c2dd

URL: 
https://github.com/llvm/llvm-project/commit/dda7ef025bc66ea326f5a8bda8c5b8534d21c2dd
DIFF: 
https://github.com/llvm/llvm-project/commit/dda7ef025bc66ea326f5a8bda8c5b8534d21c2dd.diff

LOG: [PowerPC] Update release notes for changes to PowerPC for V12.0

Added: 


Modified: 
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c1bda3339a9e..542a505bfd2e 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -129,7 +129,75 @@ During this release ...
 Changes to the PowerPC Target
 -
 
-During this release ...
+Optimization:
+
+* Made improvements to loop unroll-and-jam including fix to respect user
+  provided #pragma unroll-and-jam for loops on targets other than ARM.
+* Improved PartialInliner allowing it to handle code regions in a switch
+  statements.
+* Improved PGO support on AIX by building and linking with compiler-rt profile
+  library.
+* Add support for Epilogue Vectorization and enabled it by default.
+
+CodeGen:
+
+* POWER10 support
+  * Implementation of PC Relative addressing in LLD including the associated
+linker optimizations.
+  * Add support for the new matrix multiplication (MMA) instructions to Clang
+and LLVM.
+  * Implementation of Power10 builtins.
+
+* Scheduling enhancements
+  * Add a new algorithm to cluster more loads/stores if the DAG is not too
+complicated.
+  * Enable the PowerPC scheduling heuristic for Power10.
+
+* Target dependent passes tuning
+  * Enhance LoopStrengthReduce/PPCLoopInstrFormPrep pass for PowerPC,
+especially for P10 intrinsics.
+  * Enhance machine combiner pass to reduce register pressure for PowerPC.
+  * Improve MachineSink to do more sinking based on register pressure and alias
+analysis.
+
+* General improvements
+  * Complete the constrained floating point operations support.
+  * Improve the llvm-exegesis support.
+  * Improve the stack clash protection to probe the gap between stackptr and
+realigned stackptr.
+  * Improve the IEEE long double support for Power8.
+  * Enable MemorySSA for LoopSink.
+  * Enhance LLVM debugging functionality via options such as -print-changed and
+-print-before-changed.
+  * Add builtins for Power9 (i.e. darn, xvtdiv, xvtsqrt etc).
+  * Add options to disable all or part of LoopIdiomRecognizePass.
+  * Add support for printing the DDG in DOT form allowing for visual inspection
+of the Data Dependence Graph.
+  * Remove the QPX support.
+  * Significant number of bug fixes including all the fixes necessary to
+achieve a clean test run for Julia.
+
+AIX Support:
+
+* Compiler-rt support
+  * Add support for building compiler-rt for AIX and 32-bit Power targets.
+  * Made compiler-rt the default rtlib for AIX.
+
+* General Improvements
+  * Enable the AIX extended AltiVec ABI under option -mabi=vec-extabi.
+  * Add partial C99 complex type support.
+  * Implemente traceback table for functions (encodes vector information,
+emits exception handling).
+  * Implemente code generation for C++ dynamic initialization and finalization.
+of non-local variables for use with the -bcdtors option of the AIX linker.
+  * Add new option -mignore-xcoff-visibility.
+  * Enable explicit sections on AIX.
+  * Enable -f[no-]data-sections on AIX and set -fdata-sections to be the 
default
+on AIX.
+  * Enable -f[no-]function-sections.
+  * Add support for relocation generation using the large code model.
+  * Add pragma align natural and sorted out pragma pack stack effect.
+
 
 Changes to the X86 Target
 -



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[llvm-branch-commits] [libcxx] ce1e90f - [docs] Add PowerPC release notes for LLVM 14

2022-03-03 Thread Lei Huang via llvm-branch-commits


Author: Lei Huang
Date: 2022-03-03T12:21:21-06:00
New Revision: ce1e90fc8dbacdaff0310e50090ec3cfdfce4def

URL: 
https://github.com/llvm/llvm-project/commit/ce1e90fc8dbacdaff0310e50090ec3cfdfce4def
DIFF: 
https://github.com/llvm/llvm-project/commit/ce1e90fc8dbacdaff0310e50090ec3cfdfce4def.diff

LOG: [docs] Add PowerPC release notes for LLVM 14

Reviewed By: jsji, #libc, ldionne

Differential Revision: https://reviews.llvm.org/D120907

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
libcxx/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a6cbf25fd48a5..0b723d67ec4ae 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -51,7 +51,19 @@ Major New Features
   For more details refer to :ref:`the SPIR-V support section `.
 - Completed support of OpenCL C 3.0 and C++ for OpenCL 2021 at experimental
   state.
--  ...
+
+- Prebuilt AIX7.2 TL5 SP3+ binary available with following notes and
+  limitations:
+  - C++ driver modes use the system libc++ headers. These headers are included
+in the optional ``libc++.adt.include`` fileset on AIX.
+  - LTO, although not disabled, is not recommended.
+  - Shared libraries builds (``-shared``) must use explicit symbol export
+options and/or export lists (e.g., with ``-bE:``) on the link step. Clang
+currently will not automatically generate symbol export lists as implicit
+linker inputs.
+
+- ``float.h`` now exposes (in hosted mode) extensions made available from the
+  AIX system header.
 
 Improvements to Clang's diagnostics
 ^^^
@@ -79,6 +91,9 @@ Non-comprehensive list of changes in this release
 - The ``-E -P`` preprocessor output now always omits blank lines, matching
   gcc behaviour. Previously, up to 8 consecutive blank lines could appear
   in the output.
+- AIX platform-related predefined macros added:
+  ``_ARCH_PPC64``, ``__HOS_AIX__``, ``__PPC``, ``__THW_BIG_ENDIAN__``,
+  ``__THW_PPC__``, and ``__powerpc``
 
 New Compiler Flags
 --
@@ -103,6 +118,8 @@ New Compiler Flags
   for `ccache `_ and
   `sccache `_ are under review.
 
+- Clang now accepts "allowlist" spelling for ``-objcmt-allowlist-dir-path``.
+
 Deprecated Compiler Flags
 -
 
@@ -169,6 +186,8 @@ Attribute Changes in Clang
   attributes, but will now issue an error due to the expansion of the
   predefined ``__clang__`` macro.
 
+- Improved handling of ``__attribute__((__aligned__))`` on AIX to match GCC.
+
 Windows Support
 ---
 

diff  --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst
index b7e07d17755a0..8a5f7099b82a8 100644
--- a/libcxx/docs/ReleaseNotes.rst
+++ b/libcxx/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@ New Features
 - More C++2b features have been implemented. :doc:`Status/Cxx2b` has the full
   overview of libc++'s C++2b implementation status.
 
+- 16-bit ``wchar_t`` handling added for ``codecvt_utf8``, ``codecvt_utf16`` and
+  ``codecvt_utf8_utf16``.
+
 API Changes
 ---
 

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c6e6e445f709d..4c6b2fac99ca6 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -105,7 +105,31 @@ Changes to the Hexagon Target
 Changes to the PowerPC Target
 -
 
-During this release ...
+Linux improvements:
+* Provided a number of builtins for compatibility with the XL compiler.
+* Allow MMA builtin types in pre-P10 compilation units.
+* Add support for Return Oriented Programming (ROP) protection for 32 bit.
+* Refactored code to use more inclusive language.
+* Switched to LLD as the default linker for pre-built Linux binaries.
+* Enabled IEEE quad long double on Linux via 
``PPC_LINUX_DEFAULT_IEEELONGDOUBLE``
+  in cmake config.
+  * Added ``__ibm128`` type to represent IBM double-double format, also 
available
+as ``__attribute__((mode(IF)))``.
+  * ``-mfloat128`` can now be used in Linux subtargets with VSX enabled.
+* Added quadword atomic load/store support in codegen; not enabled by default.
+* Codegen improvements for splat load, byval parameter, stack lowering, etc.
+* Implemented P10 instruction scheduling model.
+* Implemented P10 instruction fusion pairs.
+* Improved handling of ``#pragma clang loop unroll_and_jam``.
+* Various bug fixes.
+
+AIX Support/improvements:
+* variadic (ellipsis) functions with C complex types are now supported.
+* Added toc-data support for AIX 64-bit.
+* Added toc-data support for read-only globals.
+* Updated default target on AIX from pwr4 to pwr7.
+* AIX 64-bit now use fast-isel for O0.
+* Added DWARF support for 32-bit XCOFF.
 
 Changes to the X86 Target
 -
@@ -224,6 +248,13 @@ Changes to the LLV

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

2025-03-27 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 updated 
https://github.com/llvm/llvm-project/pull/133279

>From a5a5ebdd21229284459349970deac401a1f2945d Mon Sep 17 00:00:00 2001
From: Lei Huang 
Date: Wed, 19 Mar 2025 10:19:57 -0400
Subject: [PATCH 1/2] [PowerPC] Support conversion between f16 and f128
 (#130158)

Enables conversion between f16 and f128.
Expanding on pre-Power9 targets and using HW instructions on Power9.

Fixes https://github.com/llvm/llvm-project/issues/92866
Commandeer of:  https://github.com/llvm/llvm-project/pull/97677

-

Co-authored-by: esmeyi 
(cherry picked from commit ade22fc1d9616c95bd1aa4ea658a21ddb073b73c)
---
 llvm/lib/IR/RuntimeLibcalls.cpp |   1 +
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp |   6 +
 llvm/lib/Target/PowerPC/PPCInstrVSX.td  |   4 +
 llvm/test/CodeGen/PowerPC/f128-conv.ll  | 487 
 llvm/test/CodeGen/PowerPC/fp128-libcalls.ll |  17 +
 5 files changed, 215 insertions(+), 300 deletions(-)

diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index e38fce764b640..085a3bc0586b6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -82,6 +82,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
 setLibcallName(RTLIB::POWI_F128, "__powikf2");
 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
+setLibcallName(RTLIB::FPROUND_F128_F16, "__trunckfhf2");
 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 21ff6f050817a..16491a145a5b9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -223,13 +223,19 @@ PPCTargetLowering::PPCTargetLowering(const 
PPCTargetMachine &TM,
 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
   }
 
+  setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+  setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
   if (Subtarget.isISA3_0()) {
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
   } else {
 // No extending loads from f16 or HW conversions back and forth.
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
+setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td 
b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 8e400bc63b785..a8724ea125140 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3997,6 +3997,8 @@ defm : ScalToVecWPermute<
   (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
 
 // Load/convert and convert/store patterns for f16.
+def : Pat<(f128 (extloadf16 ForceXForm:$src)),
+  (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src>;
 def : Pat<(f64 (extloadf16 ForceXForm:$src)),
   (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
 def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4005,6 +4007,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
   (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), 
VSSRC))>;
 def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
   (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), 
ForceXForm:$dst)>;
+def : Pat<(f128 (f16_to_fp i32:$A)),
+  (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A>;
 def : Pat<(f64 (f16_to_fp i32:$A)),
   (f64 (XSCVHPDP (MTVSRWZ $A)))>;
 def : Pat<(f32 (f16_to_fp i32:$A)),
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll 
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index d8eed1fb4092c..f8b2861156db4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -10,11 +10,11 @@
 @umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
 @swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
 @uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
-@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 
0], align 2
-@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
+@uhwMem = global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
+@ubMem = global [5 x i8] c"\05\02\03\04\00", align 1
 
 ; Function Attrs: norecurse nounwind
-define void @sdwConv2qp(ptr nocapture %a, i64 %b) {
+define void @sdwConv2qp(ptr nocapture %a, i64 %b) nounwind {
 ;

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

2025-03-27 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 created 
https://github.com/llvm/llvm-project/pull/133279

Backport 
https://github.com/llvm/llvm-project/commit/ade22fc1d9616c95bd1aa4ea658a21ddb073b73c

Requested by: @lei137

>From f04efc3eafa9e1397613cbbc33f1370f896202c8 Mon Sep 17 00:00:00 2001
From: Lei Huang 
Date: Wed, 19 Mar 2025 10:19:57 -0400
Subject: [PATCH 1/2] [PowerPC] Support conversion between f16 and f128
 (#130158)

Enables conversion between f16 and f128.
Expanding on pre-Power9 targets and using HW instructions on Power9.

Fixes https://github.com/llvm/llvm-project/issues/92866
Commandeer of:  https://github.com/llvm/llvm-project/pull/97677

-

Co-authored-by: esmeyi 
(cherry picked from commit ade22fc1d9616c95bd1aa4ea658a21ddb073b73c)
---
 llvm/lib/IR/RuntimeLibcalls.cpp |   1 +
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp |   6 +
 llvm/lib/Target/PowerPC/PPCInstrVSX.td  |   4 +
 llvm/test/CodeGen/PowerPC/f128-conv.ll  | 487 
 llvm/test/CodeGen/PowerPC/fp128-libcalls.ll |  17 +
 5 files changed, 215 insertions(+), 300 deletions(-)

diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index e38fce764b640..085a3bc0586b6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -82,6 +82,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
 setLibcallName(RTLIB::POWI_F128, "__powikf2");
 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
+setLibcallName(RTLIB::FPROUND_F128_F16, "__trunckfhf2");
 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 21ff6f050817a..16491a145a5b9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -223,13 +223,19 @@ PPCTargetLowering::PPCTargetLowering(const 
PPCTargetMachine &TM,
 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
   }
 
+  setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+  setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
   if (Subtarget.isISA3_0()) {
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
   } else {
 // No extending loads from f16 or HW conversions back and forth.
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
+setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td 
b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 8e400bc63b785..a8724ea125140 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3997,6 +3997,8 @@ defm : ScalToVecWPermute<
   (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
 
 // Load/convert and convert/store patterns for f16.
+def : Pat<(f128 (extloadf16 ForceXForm:$src)),
+  (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src>;
 def : Pat<(f64 (extloadf16 ForceXForm:$src)),
   (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
 def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4005,6 +4007,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
   (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), 
VSSRC))>;
 def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
   (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), 
ForceXForm:$dst)>;
+def : Pat<(f128 (f16_to_fp i32:$A)),
+  (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A>;
 def : Pat<(f64 (f16_to_fp i32:$A)),
   (f64 (XSCVHPDP (MTVSRWZ $A)))>;
 def : Pat<(f32 (f16_to_fp i32:$A)),
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll 
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index d8eed1fb4092c..f8b2861156db4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -10,11 +10,11 @@
 @umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
 @swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
 @uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
-@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 
0], align 2
-@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
+@uhwMem = global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
+@ubMem = global [5 x i8] c"\05\02\03\04\00", align 1
 
 ; Function Attrs: norecurse nounwin

[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)

2025-03-27 Thread Lei Huang via llvm-branch-commits


lei137 wrote:

New PR to backport to V20.x: https://github.com/llvm/llvm-project/pull/133279

https://github.com/llvm/llvm-project/pull/132049
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[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

2025-03-27 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 milestoned 
https://github.com/llvm/llvm-project/pull/133279
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[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)

2025-03-27 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 closed 
https://github.com/llvm/llvm-project/pull/132049
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[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)

2025-03-27 Thread Lei Huang via llvm-branch-commits


lei137 wrote:

> Seems like the tests are failing because #126880 hasn't been backported. 
> Probably should just adjust the tests accordingly.
> 
> What's standard practice here? Should someone with commit access just push a 
> fix to the PR branch?

I will create a local branch with the fix and open a new PR to get this 
backported.

https://github.com/llvm/llvm-project/pull/132049
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[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

2025-03-31 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 updated 
https://github.com/llvm/llvm-project/pull/133279

>From 9cb7ed36484774b012b8e17c79fccc161c36d116 Mon Sep 17 00:00:00 2001
From: Lei Huang 
Date: Thu, 27 Mar 2025 17:27:45 +
Subject: [PATCH] update test due to
 https://github.com/llvm/llvm-project/pull/126880 not being backported

---
 llvm/test/CodeGen/PowerPC/f128-conv.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll 
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index f8b2861156db4..1a51ca64177a0 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -1365,7 +1365,7 @@ define half @trunc(fp128 %a) nounwind {
 ; CHECK-P8-NEXT:bl __trunckfhf2
 ; CHECK-P8-NEXT:nop
 ; CHECK-P8-NEXT:clrldi r3, r3, 48
-; CHECK-P8-NEXT:bl __extendhfsf2
+; CHECK-P8-NEXT:bl __gnu_h2f_ieee
 ; CHECK-P8-NEXT:nop
 ; CHECK-P8-NEXT:addi r1, r1, 32
 ; CHECK-P8-NEXT:ld r0, 16(r1)

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[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

2025-03-28 Thread Lei Huang via llvm-branch-commits


lei137 wrote:

I am not able to resolve this conflict here.  I don't see this issue in my 
local branch and it doesn't seem to work if I use the web editor to accept the 
incoming change and mark it as resolved.

https://github.com/llvm/llvm-project/pull/133279
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[llvm-branch-commits] [clang] RFC02658:CLANG: DMF VSX Vector float GER 2x (rank-2 update) (PR #147383)

2025-07-07 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 created 
https://github.com/llvm/llvm-project/pull/147383

Add clang builtins for DMF VSX Vector floats:

```
void __builtin_mma_dmxvf16gerx2 (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvf16gerx2nn (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvf16gerx2np (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvf16gerx2pn (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvf16gerx2pp (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_pmdmxvf16gerx2 (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvf16gerx2nn (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvf16gerx2np (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvf16gerx2pn (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvf16gerx2pp (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);

void __builtin_mma_dmxvbf16gerx2 (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvbf16gerx2nn (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvbf16gerx2np (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvbf16gerx2pn (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvbf16gerx2pp (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_pmdmxvbf16gerx2 (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvbf16gerx2nn (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvbf16gerx2np (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvbf16gerx2pn (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
void __builtin_mma_pmdmxvbf16gerx2pp (__dmr1024 *, __vector_pair, vec_t, uint8, 
uint4, uint2);
```

>From cfe934f27abdf6f18f00076c9418ad8943752c9a Mon Sep 17 00:00:00 2001
From: Lei Huang 
Date: Mon, 7 Jul 2025 11:11:23 -0500
Subject: [PATCH 1/3] RFC02658:CLANG: DMF VSX Vector bfloat16 GER 2x (rank-2
 update)

---
 clang/include/clang/Basic/BuiltinsPPC.def |   5 +
 .../PowerPC/builtins-dmf-vsx-vector-float.c   | 161 ++
 .../PowerPC/ppc-future-mma-builtin-err.c  |  22 +++
 3 files changed, 188 insertions(+)
 create mode 100644 clang/test/CodeGen/PowerPC/builtins-dmf-vsx-vector-float.c

diff --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 3fa9961a9602c..35d863d501495 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -1095,6 +1095,11 @@ UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvbf16ger2, "vW512*VV",
  "mma,paired-vector-memops")
 UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3",
  "mma,paired-vector-memops")
+UNALIASED_CUSTOM_MMA_BUILTIN(mma_dmxvbf16gerx2, "vW1024*W256V",
+ "mma,paired-vector-memops")
+UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmdmxvbf16gerx2, "vW1024*W256Vi255i15i15",
+ "mma,paired-vector-memops")
+
 
 // FIXME: Obviously incomplete.
 
diff --git a/clang/test/CodeGen/PowerPC/builtins-dmf-vsx-vector-float.c 
b/clang/test/CodeGen/PowerPC/builtins-dmf-vsx-vector-float.c
new file mode 100644
index 0..953815ecc42b6
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-dmf-vsx-vector-float.c
@@ -0,0 +1,161 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
+//   Update then manual applied to commonize the checks for AIX and LoP.
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN:-emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-ibm-aix -target-cpu future \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: void @test_dmxvbf16gerx2(
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, 
!tbaa [[TBAA2:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = tail call <1024 x i1> 
@llvm.ppc.mma.dmxvbf16gerx2(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]])
+// CHECK-NEXT:store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, 
!tbaa [[TBAA6:![0-9]+]]
+// CHECK-NEXT:ret void
+//
+void test_dmxvbf16gerx2(unsigned char *vdmrp, unsigned char *vpp, vector 
unsigned char vc, unsigned char *resp) {
+  __dmr1024 vdmr = *((__dmr1024 *)vdmrp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_dmxvbf16gerx2(&vdmr, vp, vc);
+  *((__dmr1024 *)resp) = vdmr;
+}
+
+// CHECK-LABEL: void @test_dmxvbf16gerx2nn(
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 
128, !tbaa [[TBAA6]]
+// CHECK-NEXT:[[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, 
!tbaa [[TBAA2]]
+// CHECK-NEXT:[[TMP2:%.*]] = tail call <1024 x i1> 
@llvm.ppc.mma.dmxvbf16gerx2nn(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x 
i8> [[VC:%.*]]

[llvm-branch-commits] [clang] [PowerPC][CLANG] DMF VSX Vector float GER 2x (rank-2 update) (PR #147383)

2025-07-07 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 edited 
https://github.com/llvm/llvm-project/pull/147383
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[llvm-branch-commits] [clang] PowerPC:CLANG: DMF VSX Vector float GER 2x (rank-2 update) (PR #147383)

2025-07-07 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 edited 
https://github.com/llvm/llvm-project/pull/147383
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

[llvm-branch-commits] [llvm] dda7ef0 - [PowerPC] Update release notes for changes to PowerPC for V12.0

[llvm-branch-commits] [libcxx] ce1e90f - [docs] Add PowerPC release notes for LLVM 14

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)

[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)

[llvm-branch-commits] [clang] RFC02658:CLANG: DMF VSX Vector float GER 2x (rank-2 update) (PR #147383)

[llvm-branch-commits] [clang] [PowerPC][CLANG] DMF VSX Vector float GER 2x (rank-2 update) (PR #147383)

[llvm-branch-commits] [clang] PowerPC:CLANG: DMF VSX Vector float GER 2x (rank-2 update) (PR #147383)

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