[llvm-branch-commits] [libunwind] 3cbd476 - [VE] Support VE in libunwind
Author: Kazushi (Jam) Marukawa
Date: 2021-01-17T15:35:02+09:00
New Revision: 3cbd476c54886e8ebac64b4145d4517732a71023
URL:
https://github.com/llvm/llvm-project/commit/3cbd476c54886e8ebac64b4145d4517732a71023
DIFF:
https://github.com/llvm/llvm-project/commit/3cbd476c54886e8ebac64b4145d4517732a71023.diff
LOG: [VE] Support VE in libunwind
Modify libunwind to support SjLj exception handling routines for VE.
In order to do that, we need to implement not only SjLj exception
handling routines but also a Registers_ve class. This implementation
of Registers_ve is incomplete. We will work on it later when we need
backtrace in libunwind.
Reviewed By: #libunwind, compnerd
Differential Revision: https://reviews.llvm.org/D94591
Added:
Modified:
libunwind/include/__libunwind_config.h
libunwind/include/libunwind.h
libunwind/src/Registers.hpp
libunwind/src/Unwind-sjlj.c
libunwind/src/libunwind.cpp
Removed:
diff --git a/libunwind/include/__libunwind_config.h
b/libunwind/include/__libunwind_config.h
index 80be357496c4..34ac6f717d6e 100644
--- a/libunwind/include/__libunwind_config.h
+++ b/libunwind/include/__libunwind_config.h
@@ -25,6 +25,7 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON 34
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE143
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
# if defined(__linux__)
@@ -138,6 +139,11 @@
#error "Unsupported RISC-V ABI"
# endif
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
+# elif defined(__ve__)
+# define _LIBUNWIND_TARGET_VE 1
+# define _LIBUNWIND_CONTEXT_SIZE 67
+# define _LIBUNWIND_CURSOR_SIZE 79
+# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_VE
# else
# error "Unsupported architecture."
# endif
@@ -154,6 +160,7 @@
# define _LIBUNWIND_TARGET_SPARC 1
# define _LIBUNWIND_TARGET_HEXAGON 1
# define _LIBUNWIND_TARGET_RISCV 1
+# define _LIBUNWIND_TARGET_VE 1
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h
index 6ec649a460b8..5bae8d02f799 100644
--- a/libunwind/include/libunwind.h
+++ b/libunwind/include/libunwind.h
@@ -947,4 +947,156 @@ enum {
UNW_RISCV_F31 = 63,
};
+// VE register numbers
+enum {
+ UNW_VE_S0 = 0,
+ UNW_VE_S1 = 1,
+ UNW_VE_S2 = 2,
+ UNW_VE_S3 = 3,
+ UNW_VE_S4 = 4,
+ UNW_VE_S5 = 5,
+ UNW_VE_S6 = 6,
+ UNW_VE_S7 = 7,
+ UNW_VE_S8 = 8,
+ UNW_VE_S9 = 9,
+ UNW_VE_S10 = 10,
+ UNW_VE_S11 = 11,
+ UNW_VE_S12 = 12,
+ UNW_VE_S13 = 13,
+ UNW_VE_S14 = 14,
+ UNW_VE_S15 = 15,
+ UNW_VE_S16 = 16,
+ UNW_VE_S17 = 17,
+ UNW_VE_S18 = 18,
+ UNW_VE_S19 = 19,
+ UNW_VE_S20 = 20,
+ UNW_VE_S21 = 21,
+ UNW_VE_S22 = 22,
+ UNW_VE_S23 = 23,
+ UNW_VE_S24 = 24,
+ UNW_VE_S25 = 25,
+ UNW_VE_S26 = 26,
+ UNW_VE_S27 = 27,
+ UNW_VE_S28 = 28,
+ UNW_VE_S29 = 29,
+ UNW_VE_S30 = 30,
+ UNW_VE_S31 = 31,
+ UNW_VE_S32 = 32,
+ UNW_VE_S33 = 33,
+ UNW_VE_S34 = 34,
+ UNW_VE_S35 = 35,
+ UNW_VE_S36 = 36,
+ UNW_VE_S37 = 37,
+ UNW_VE_S38 = 38,
+ UNW_VE_S39 = 39,
+ UNW_VE_S40 = 40,
+ UNW_VE_S41 = 41,
+ UNW_VE_S42 = 42,
+ UNW_VE_S43 = 43,
+ UNW_VE_S44 = 44,
+ UNW_VE_S45 = 45,
+ UNW_VE_S46 = 46,
+ UNW_VE_S47 = 47,
+ UNW_VE_S48 = 48,
+ UNW_VE_S49 = 49,
+ UNW_VE_S50 = 50,
+ UNW_VE_S51 = 51,
+ UNW_VE_S52 = 52,
+ UNW_VE_S53 = 53,
+ UNW_VE_S54 = 54,
+ UNW_VE_S55 = 55,
+ UNW_VE_S56 = 56,
+ UNW_VE_S57 = 57,
+ UNW_VE_S58 = 58,
+ UNW_VE_S59 = 59,
+ UNW_VE_S60 = 60,
+ UNW_VE_S61 = 61,
+ UNW_VE_S62 = 62,
+ UNW_VE_S63 = 63,
+ UNW_VE_V0 = 64 + 0,
+ UNW_VE_V1 = 64 + 1,
+ UNW_VE_V2 = 64 + 2,
+ UNW_VE_V3 = 64 + 3,
+ UNW_VE_V4 = 64 + 4,
+ UNW_VE_V5 = 64 + 5,
+ UNW_VE_V6 = 64 + 6,
+ UNW_VE_V7 = 64 + 7,
+ UNW_VE_V8 = 64 + 8,
+ UNW_VE_V9 = 64 + 9,
+ UNW_VE_V10 = 64 + 10,
+ UNW_VE_V11 = 64 + 11,
+ UNW_VE_V12 = 64 + 12,
+ UNW_VE_V13 = 64 + 13,
+ UNW_VE_V14 = 64 + 14,
+ UNW_VE_V15 = 64 + 15,
+ UNW_VE_V16 = 64 + 16,
+ UNW_VE_V17 = 64 + 17,
+ UNW_VE_V18 = 64 + 18,
+ UNW_VE_V19 = 64 + 19,
+ UNW_VE_V20 = 64 + 20,
+ UNW_VE_V21 = 64 + 21,
+ UNW_VE_V22 = 64 + 22,
+ UNW_VE_V23 = 64 + 23,
+ UNW_VE_V24 = 64 + 24,
+ UNW_VE_V25 = 64 + 25,
+ UNW_VE_V26 = 64 + 26,
+ UNW_VE_V27 = 64 + 27,
+ UNW_VE_V28 = 64 + 28,
+ UNW_VE_V29 = 64 + 29,
+ UNW_VE_V30 = 64 + 30,
+ UNW_VE_V31 = 64 + 31,
+ UNW_VE_V32 = 64 + 32,
+ UNW_VE_V33 = 64 + 33,
+ UNW_VE_V34 = 64 + 34,
+ UNW_VE_V35 = 64 + 35,
+ UNW_VE_V36 = 64 + 36,
+ UNW_VE_V37 = 64 + 37,
+ UNW_VE_V38 = 64 + 38,
+ UNW_VE_V39 = 64 + 39,
+ UNW_VE_V40 = 64 + 40,
+ UNW_VE_V41 = 64 + 41,
+ UNW_VE_V42 = 64 + 42,
+
[llvm-branch-commits] [llvm] 74e7cb2 - [VE] Remove VA.needsCustom checks
Author: Kazushi (Jam) Marukawa
Date: 2021-01-04T18:19:18+09:00
New Revision: 74e7cb26b9a3ff3f64883cc2418d9916b5e9257d
URL:
https://github.com/llvm/llvm-project/commit/74e7cb26b9a3ff3f64883cc2418d9916b5e9257d
DIFF:
https://github.com/llvm/llvm-project/commit/74e7cb26b9a3ff3f64883cc2418d9916b5e9257d.diff
LOG: [VE] Remove VA.needsCustom checks
Remove VA.needsCustom checks which are copied from Sparc implementation
at the very beginning of VE implementation. Add assert to sanity-check
VA.needsCustom flag, also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93847
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index ea9281a00502..5a3a9f504e30 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -314,6 +314,7 @@ VETargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
+assert(!VA.needsCustom() && "Unexpected custom lowering");
SDValue OutVal = OutVals[i];
// Integer return values must be sign or zero extended by the callee.
@@ -349,8 +350,6 @@ VETargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
llvm_unreachable("Unknown loc info!");
}
-assert(!VA.needsCustom() && "Unexpected custom lowering");
-
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
// Guarantee that all emitted copies are stuck together with flags.
@@ -390,6 +389,7 @@ SDValue VETargetLowering::LowerFormalArguments(
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
+assert(!VA.needsCustom() && "Unexpected custom lowering");
if (VA.isRegLoc()) {
// This argument is passed in a register.
// All integer register arguments are promoted by the caller to i64.
@@ -399,11 +399,6 @@ SDValue VETargetLowering::LowerFormalArguments(
MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));
SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
- // Get the high bits for i32 struct elements.
- if (VA.getValVT() == MVT::i32 && VA.needsCustom())
-Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
- DAG.getConstant(32, DL, MVT::i32));
-
// The caller promoted the argument, so insert an Assert?ext SDNode so we
// won't promote the value again in this function.
switch (VA.getLocInfo()) {
@@ -734,6 +729,7 @@ SDValue
VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
+assert(!VA.needsCustom() && "Unexpected custom lowering");
unsigned Reg = VA.getLocReg();
// When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
@@ -751,11 +747,6 @@ SDValue
VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
InGlue = Chain.getValue(2);
}
-// Get the high bits for i32 struct elements.
-if (VA.getValVT() == MVT::i32 && VA.needsCustom())
- RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
- DAG.getConstant(32, DL, MVT::i32));
-
// The callee promoted the return value, so insert an Assert?ext SDNode so
// we won't promote the value again in this function.
switch (VA.getLocInfo()) {
___
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[llvm-branch-commits] [llvm] c287f90 - [VE] Change default CPU name to "generic"
Author: Kazushi (Jam) Marukawa
Date: 2021-01-04T20:09:57+09:00
New Revision: c287f90ccd33b3aa47488e8f2b3a24aa0717066b
URL:
https://github.com/llvm/llvm-project/commit/c287f90ccd33b3aa47488e8f2b3a24aa0717066b
DIFF:
https://github.com/llvm/llvm-project/commit/c287f90ccd33b3aa47488e8f2b3a24aa0717066b.diff
LOG: [VE] Change default CPU name to "generic"
Change default CPU name of SX-Aurora VE from "ve" to "generic" similar
to other architectures.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93836
Added:
llvm/test/CodeGen/VE/Scalar/cpu.ll
Modified:
llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
llvm/lib/Target/VE/VE.td
llvm/lib/Target/VE/VESubtarget.cpp
Removed:
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
index 239a89812e47..4c480c050274 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
@@ -56,7 +56,7 @@ static MCRegisterInfo *createVEMCRegisterInfo(const Triple
&TT) {
static MCSubtargetInfo *createVEMCSubtargetInfo(const Triple &TT, StringRef
CPU,
StringRef FS) {
if (CPU.empty())
-CPU = "ve";
+CPU = "generic";
return createVEMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS);
}
diff --git a/llvm/lib/Target/VE/VE.td b/llvm/lib/Target/VE/VE.td
index a2c0ba04adaa..9e8adcd42077 100644
--- a/llvm/lib/Target/VE/VE.td
+++ b/llvm/lib/Target/VE/VE.td
@@ -46,7 +46,7 @@ def VEAsmParser : AsmParser {
class Proc Features>
: Processor;
-def : Proc<"ve", []>;
+def : Proc<"generic", []>;
//===--===//
// Declare the target which we are implementing
diff --git a/llvm/lib/Target/VE/VESubtarget.cpp
b/llvm/lib/Target/VE/VESubtarget.cpp
index 3406a613e89d..daa6cfb8aa84 100644
--- a/llvm/lib/Target/VE/VESubtarget.cpp
+++ b/llvm/lib/Target/VE/VESubtarget.cpp
@@ -33,7 +33,7 @@ VESubtarget
&VESubtarget::initializeSubtargetDependencies(StringRef CPU,
// Determine default and user specified characteristics
std::string CPUName = std::string(CPU);
if (CPUName.empty())
-CPUName = "ve";
+CPUName = "generic";
// Parse features string.
ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPU, FS);
diff --git a/llvm/test/CodeGen/VE/Scalar/cpu.ll
b/llvm/test/CodeGen/VE/Scalar/cpu.ll
new file mode 100644
index ..7586a38f9f5a
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/cpu.ll
@@ -0,0 +1,5 @@
+; RUN: llc -mtriple=ve -mcpu=help < %s 2>&1 | FileCheck %s
+
+; CHECK: Available CPUs for this target:
+; CHECK-EMPTY:
+; CHECK-NEXT: generic - Select the generic processor.
___
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[llvm-branch-commits] [llvm] 2654f33 - [VE] Support llvm.eh.sjlj.lsda
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T18:06:14+09:00
New Revision: 2654f33c47f44b05351422e61c94afa5a6d6afe5
URL:
https://github.com/llvm/llvm-project/commit/2654f33c47f44b05351422e61c94afa5a6d6afe5
DIFF:
https://github.com/llvm/llvm-project/commit/2654f33c47f44b05351422e61c94afa5a6d6afe5.diff
LOG: [VE] Support llvm.eh.sjlj.lsda
In order to support SJLJ exception, implement llvm.eh.sjlj.lsda first.
Add regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93811
Added:
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index 5a3a9f504e30..10b99ac031b3 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -275,6 +275,9 @@ void VETargetLowering::initSPUActions() {
}
/// } Atomic isntructions
+
+ // Intrinsic instructions
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
}
void VETargetLowering::initVPUActions() {
@@ -1525,6 +1528,37 @@ static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG
&DAG,
MachinePointerInfo());
}
+SDValue VETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ unsigned IntNo = cast(Op.getOperand(0))->getZExtValue();
+ switch (IntNo) {
+ default: // Don't custom lower most intrinsics.
+return SDValue();
+ case Intrinsic::eh_sjlj_lsda: {
+MachineFunction &MF = DAG.getMachineFunction();
+MVT VT = Op.getSimpleValueType();
+const VETargetMachine *TM =
+static_cast(&DAG.getTarget());
+
+// Create GCC_except_tableXX string. The real symbol for that will be
+// generated in EHStreamer::emitExceptionTable() later. So, we just
+// borrow it's name here.
+TM->getStrList()->push_back(std::string(
+(Twine("GCC_except_table") + Twine(MF.getFunctionNumber())).str()));
+SDValue Addr =
+DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);
+if (isPositionIndependent()) {
+ Addr = makeHiLoPair(Addr, VEMCExpr::VK_VE_GOTOFF_HI32,
+ VEMCExpr::VK_VE_GOTOFF_LO32, DAG);
+ SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, VT);
+ return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);
+}
+return makeHiLoPair(Addr, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG);
+ }
+ }
+}
+
static SDValue getSplatValue(SDNode *N) {
if (auto *BuildVec = dyn_cast(N)) {
return BuildVec->getSplatValue();
@@ -1571,6 +1605,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return lowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress:
return lowerGlobalTLSAddress(Op, DAG);
+ case ISD::INTRINSIC_WO_CHAIN:
+return lowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::JumpTable:
return lowerJumpTable(Op, DAG);
case ISD::LOAD:
diff --git a/llvm/lib/Target/VE/VEISelLowering.h
b/llvm/lib/Target/VE/VEISelLowering.h
index b5e2a72887f4..eec4532ffa3a 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -115,6 +115,7 @@ class VETargetLowering : public TargetLowering {
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
new file mode 100644
index ..d3da4ce971aa
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=ve -exception-model sjlj | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define i8* @test_lsda() {
+; CHECK-LABEL: test_lsda:
+; CHECK: # %bb.0:
+; CHECK-NEXT:lea %s0, GCC_except_table0@lo
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea.sl %s0, GCC_except_table0@hi(, %s0)
+; CHECK-NEXT:b.l.t (, %s10)
+ %ret = call i8* @llvm.eh.sjlj.lsda()
+ ret i8* %ret
+}
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.sjlj.lsda()
___
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[llvm-branch-commits] [llvm] 53a341a - [VE][NFC] Fix typo in comments
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T18:55:28+09:00
New Revision: 53a341a61d1fc2d0c455738a6a4d5f5d54a4e1d3
URL:
https://github.com/llvm/llvm-project/commit/53a341a61d1fc2d0c455738a6a4d5f5d54a4e1d3
DIFF:
https://github.com/llvm/llvm-project/commit/53a341a61d1fc2d0c455738a6a4d5f5d54a4e1d3.diff
LOG: [VE][NFC] Fix typo in comments
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index 10b99ac031b3..e83483dd13fb 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -257,7 +257,7 @@ void VETargetLowering::initSPUActions() {
// Support i8/i16 atomic swap.
setOperationAction(ISD::ATOMIC_SWAP, VT, Custom);
-// FIXME: Support "atmam" isntructions.
+// FIXME: Support "atmam" instructions.
setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Expand);
setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Expand);
setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Expand);
@@ -274,7 +274,7 @@ void VETargetLowering::initSPUActions() {
setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
}
- /// } Atomic isntructions
+ /// } Atomic instructions
// Intrinsic instructions
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
___
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[llvm-branch-commits] [llvm] f784be0 - [VE] Support SJLJ exception related instructions
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T20:19:15+09:00
New Revision: f784be0777f34a5b3bc3da6892ca242de7840fce
URL:
https://github.com/llvm/llvm-project/commit/f784be0777f34a5b3bc3da6892ca242de7840fce
DIFF:
https://github.com/llvm/llvm-project/commit/f784be0777f34a5b3bc3da6892ca242de7840fce.diff
LOG: [VE] Support SJLJ exception related instructions
Support EH_SJLJ_LONGJMP, EH_SJLJ_SETJMP, and EH_SJLJ_SETUP_DISPATCH
for SjLj exception handling. NC++ uses SjLj exception handling, so
implement it first. Add regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94071
Added:
llvm/lib/Target/VE/VEInstrBuilder.h
llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
llvm/test/CodeGen/VE/Scalar/sjlj_except.ll
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index e83483dd13fb..230ce42d46b3 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -13,6 +13,7 @@
#include "VEISelLowering.h"
#include "MCTargetDesc/VEMCExpr.h"
+#include "VEInstrBuilder.h"
#include "VEMachineFunctionInfo.h"
#include "VERegisterInfo.h"
#include "VETargetMachine.h"
@@ -276,6 +277,14 @@ void VETargetLowering::initSPUActions() {
/// } Atomic instructions
+ /// SJLJ instructions {
+ setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
+ setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
+ setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
+ if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
+setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
+ /// } SJLJ instructions
+
// Intrinsic instructions
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
}
@@ -864,6 +873,9 @@ const char *VETargetLowering::getTargetNodeName(unsigned
Opcode) const {
case VEISD::FIRST_NUMBER:
break;
TARGET_NODE_CASE(CALL)
+TARGET_NODE_CASE(EH_SJLJ_LONGJMP)
+TARGET_NODE_CASE(EH_SJLJ_SETJMP)
+TARGET_NODE_CASE(EH_SJLJ_SETUP_DISPATCH)
TARGET_NODE_CASE(GETFUNPLT)
TARGET_NODE_CASE(GETSTACKTOP)
TARGET_NODE_CASE(GETTLSADDR)
@@ -1487,6 +1499,28 @@ SDValue
VETargetLowering::lowerDYNAMIC_STACKALLOC(SDValue Op,
return DAG.getMergeValues(Ops, DL);
}
+SDValue VETargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ return DAG.getNode(VEISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0),
+ Op.getOperand(1));
+}
+
+SDValue VETargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ return DAG.getNode(VEISD::EH_SJLJ_SETJMP, DL,
+ DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
+ Op.getOperand(1));
+}
+
+SDValue VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
+ SelectionDAG &DAG) const
{
+ SDLoc DL(Op);
+ return DAG.getNode(VEISD::EH_SJLJ_SETUP_DISPATCH, DL, MVT::Other,
+ Op.getOperand(0));
+}
+
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
const VETargetLowering &TLI,
const VESubtarget *Subtarget) {
@@ -1599,6 +1633,12 @@ SDValue VETargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return lowerConstantPool(Op, DAG);
case ISD::DYNAMIC_STACKALLOC:
return lowerDYNAMIC_STACKALLOC(Op, DAG);
+ case ISD::EH_SJLJ_LONGJMP:
+return lowerEH_SJLJ_LONGJMP(Op, DAG);
+ case ISD::EH_SJLJ_SETJMP:
+return lowerEH_SJLJ_SETJMP(Op, DAG);
+ case ISD::EH_SJLJ_SETUP_DISPATCH:
+return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
case ISD::FRAMEADDR:
return lowerFRAMEADDR(Op, DAG, *this, Subtarget);
case ISD::GlobalAddress:
@@ -1699,6 +1739,677 @@ SDValue
VETargetLowering::getPICJumpTableRelocBase(SDValue Table,
return DAG.getNode(ISD::ADD, DL, PtrTy, GlobalBase, HiLo);
}
+Register VETargetLowering::prepareMBB(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ MachineBasicBlock *TargetBB,
+ const DebugLoc &DL) const {
+ MachineFunction *MF = MBB.getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const VEInstrInfo *TII = Subtarget->getInstrInfo();
+
+ const TargetRegisterClass *RC = &VE::I64RegClass;
+ Register Tmp1 = MRI.createVirtualRegister(RC);
+ Regi
[llvm-branch-commits] [clang] 489000d - [VE] Change clang to support SjLj Lowering
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T22:19:02+09:00
New Revision: 489000d8516da7eaf6aabaad11cce0ed7e67c61f
URL:
https://github.com/llvm/llvm-project/commit/489000d8516da7eaf6aabaad11cce0ed7e67c61f
DIFF:
https://github.com/llvm/llvm-project/commit/489000d8516da7eaf6aabaad11cce0ed7e67c61f.diff
LOG: [VE] Change clang to support SjLj Lowering
We supports SjLj exception handling in the backend, so changing
clang to allow lowering using SjLj exceptions. Update a regression
test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94076
Added:
Modified:
clang/lib/Basic/Targets/VE.h
clang/test/Sema/builtin-longjmp.c
Removed:
diff --git a/clang/lib/Basic/Targets/VE.h b/clang/lib/Basic/Targets/VE.h
index 2d9c74ac5247..71d6fc08d859 100644
--- a/clang/lib/Basic/Targets/VE.h
+++ b/clang/lib/Basic/Targets/VE.h
@@ -53,10 +53,7 @@ class LLVM_LIBRARY_VISIBILITY VETargetInfo : public
TargetInfo {
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
- bool hasSjLjLowering() const override {
-// TODO
-return false;
- }
+ bool hasSjLjLowering() const override { return true; }
ArrayRef getTargetBuiltins() const override;
diff --git a/clang/test/Sema/builtin-longjmp.c
b/clang/test/Sema/builtin-longjmp.c
index d80208f82c67..3023098a7631 100644
--- a/clang/test/Sema/builtin-longjmp.c
+++ b/clang/test/Sema/builtin-longjmp.c
@@ -4,6 +4,7 @@
// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm < %s| FileCheck
%s
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm < %s|
FileCheck %s
// RUN: %clang_cc1 -triple sparc-eabi-unknown -emit-llvm < %s | FileCheck %s
+// RUN: %clang_cc1 -triple ve-unknown-unknown -emit-llvm < %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -emit-llvm-only -verify %s
// RUN: %clang_cc1 -triple mips-unknown-unknown -emit-llvm-only -verify %s
___
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[llvm-branch-commits] [llvm] 3bfc9bb - [VE][NFC] Update comments to match the generated instructions
Author: Kazushi (Jam) Marukawa Date: 2021-01-07T15:13:24+09:00 New Revision: 3bfc9bb8ef223dd28c885fcb1a5fa553c8be3645 URL: https://github.com/llvm/llvm-project/commit/3bfc9bb8ef223dd28c885fcb1a5fa553c8be3645 DIFF: https://github.com/llvm/llvm-project/commit/3bfc9bb8ef223dd28c885fcb1a5fa553c8be3645.diff LOG: [VE][NFC] Update comments to match the generated instructions Added: Modified: llvm/lib/Target/VE/VEAsmPrinter.cpp Removed: diff --git a/llvm/lib/Target/VE/VEAsmPrinter.cpp b/llvm/lib/Target/VE/VEAsmPrinter.cpp index 0ebf0a87de74..08a75b6b8c55 100644 --- a/llvm/lib/Target/VE/VEAsmPrinter.cpp +++ b/llvm/lib/Target/VE/VEAsmPrinter.cpp @@ -206,7 +206,7 @@ void VEAsmPrinter::lowerGETGOTAndEmitMCInsts(const MachineInstr *MI, // lea %got, _GLOBAL_OFFSET_TABLE_@PC_LO(-24) // and %got, %got, (32)0 // sic %plt - // lea.sl %got, _GLOBAL_OFFSET_TABLE_@PC_HI(%got, %plt) + // lea.sl %got, _GLOBAL_OFFSET_TABLE_@PC_HI(%plt, %got) MCOperand cim24 = MCOperand::createImm(-24); MCOperand loImm = createGOTRelExprOp(VEMCExpr::VK_VE_PC_LO32, GOTLabel, OutContext); @@ -251,10 +251,10 @@ void VEAsmPrinter::lowerGETFunPLTAndEmitMCInsts(const MachineInstr *MI, MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT - // lea %dst, %plt_lo(func)(-24) + // lea %dst, func@plt_lo(-24) // and %dst, %dst, (32)0 // sic %plt; FIXME: is it safe to use %plt here? - // lea.sl %dst, %plt_hi(func)(%dst, %plt) + // lea.sl %dst, func@plt_hi(%plt, %dst) MCOperand cim24 = MCOperand::createImm(-24); MCOperand loImm = createGOTRelExprOp(VEMCExpr::VK_VE_PLT_LO32, AddrSym, OutContext); @@ -298,7 +298,7 @@ void VEAsmPrinter::lowerGETTLSAddrAndEmitMCInsts(const MachineInstr *MI, // lea %s0, sym@tls_gd_lo(-24) // and %s0, %s0, (32)0 // sic %lr - // lea.sl %s0, sym@tls_gd_hi(%s0, %lr) + // lea.sl %s0, sym@tls_gd_hi(%lr, %s0) // lea %s12, __tls_get_addr@plt_lo(8) // and %s12, %s12, (32)0 // lea.sl %s12, __tls_get_addr@plt_hi(%s12, %lr) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 1216763 - [VE] Add SVOB intrinsic instruction
Author: Kazushi (Jam) Marukawa
Date: 2021-01-08T18:49:17+09:00
New Revision: 12167632bc5cafee68da31592dae78a20a3e7e7a
URL:
https://github.com/llvm/llvm-project/commit/12167632bc5cafee68da31592dae78a20a3e7e7a
DIFF:
https://github.com/llvm/llvm-project/commit/12167632bc5cafee68da31592dae78a20a3e7e7a.diff
LOG: [VE] Add SVOB intrinsic instruction
Add SVOB intrinsic instruction and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94279
Added:
llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
Modified:
llvm/include/llvm/IR/IntrinsicsVE.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsVE.td
b/llvm/include/llvm/IR/IntrinsicsVE.td
index 1cb7a2e1eaf4..3a8eec6d4dd5 100644
--- a/llvm/include/llvm/IR/IntrinsicsVE.td
+++ b/llvm/include/llvm/IR/IntrinsicsVE.td
@@ -1,4 +1,10 @@
// Define intrinsics written by hand
+// VEL Intrinsic instructions.
+let TargetPrefix = "ve" in {
+ def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">,
+ Intrinsic<[], [], [IntrHasSideEffects]>;
+}
+
// Define intrinsics automatically generated
include "llvm/IR/IntrinsicsVEVL.gen.td"
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
index 29365b327f27..b64d241cecfd 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -2,6 +2,9 @@
// Define intrinsics written by hand
+// SVOB pattern.
+def : Pat<(int_ve_vl_svob), (SVOB)>;
+
// The lsv and lvs patterns
def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
(LSVrr_v (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32),
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
new file mode 100644
index ..b835faecdc18
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test set vector out-of-order memory access boundary intrinsic instructions
+;;;
+;;; Note:
+;;; We test SVOB instruction.
+
+; Function Attrs: nounwind
+define fastcc void @svob_svob() {
+; CHECK-LABEL: svob_svob:
+; CHECK: # %bb.0:
+; CHECK-NEXT:svob
+; CHECK-NEXT:b.l.t (, %s10)
+ tail call void @llvm.ve.vl.svob()
+ ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.ve.vl.svob()
___
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[llvm-branch-commits] [llvm] 99c84af - [VE][NFC] Clean ISel patterns for LSV and LVS
Author: Kazushi (Jam) Marukawa Date: 2021-01-08T21:47:33+09:00 New Revision: 99c84af1a25a072df4f05d3f269f140a6e5ff18a URL: https://github.com/llvm/llvm-project/commit/99c84af1a25a072df4f05d3f269f140a6e5ff18a DIFF: https://github.com/llvm/llvm-project/commit/99c84af1a25a072df4f05d3f269f140a6e5ff18a.diff LOG: [VE][NFC] Clean ISel patterns for LSV and LVS Clean ISel patterns for LSV and LVS before upstream more hand-written ISel patterns. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94291 Added: Modified: llvm/lib/Target/VE/VEInstrIntrinsicVL.td Removed: diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td index b64d241cecfd..6cec6fece8d8 100644 --- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td +++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td @@ -1,25 +1,21 @@ -// Pattern Matchings for VEL Intrinsics +/// Pattern Matchings for VEL intrinsic instructions. -// Define intrinsics written by hand +/// Intrinsic patterns written by hand. // SVOB pattern. def : Pat<(int_ve_vl_svob), (SVOB)>; -// The lsv and lvs patterns +// LSV patterns. def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz), - (LSVrr_v (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32), - i64:$sz, v256f64:$pt)>; + (LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>; + +// LVS patterns. def : Pat<(int_ve_vl_lvsl_svs v256f64:$vx, i32:$sy), - (LVSvr v256f64:$vx, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32))>; + (LVSvr v256f64:$vx, (i2l i32:$sy))>; def : Pat<(int_ve_vl_lvsd_svs v256f64:$vx, i32:$sy), - (LVSvr v256f64:$vx, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32))>; + (LVSvr v256f64:$vx, (i2l i32:$sy))>; def : Pat<(int_ve_vl_lvss_svs v256f64:$vx, i32:$sy), - (EXTRACT_SUBREG (LVSvr v256f64:$vx, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, -sub_i32)), - sub_f32)>; + (l2f (LVSvr v256f64:$vx, (i2l i32:$sy)))>; -// Define intrinsics automatically generated +/// Intrinsic patterns automatically generated. include "VEInstrIntrinsicVL.gen.td" ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 5ead757 - [VE] Support pack_f32p and pack_f32a intrinsic instructions
Author: Kazushi (Jam) Marukawa
Date: 2021-01-08T22:59:11+09:00
New Revision: 5ead757f1d89898941f0e10f71f382aaf36d174b
URL:
https://github.com/llvm/llvm-project/commit/5ead757f1d89898941f0e10f71f382aaf36d174b
DIFF:
https://github.com/llvm/llvm-project/commit/5ead757f1d89898941f0e10f71f382aaf36d174b.diff
LOG: [VE] Support pack_f32p and pack_f32a intrinsic instructions
Support pack_f32p and pack_f32a intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94296
Added:
llvm/test/CodeGen/VE/VELIntrinsics/pack.ll
Modified:
llvm/include/llvm/IR/IntrinsicsVE.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsVE.td
b/llvm/include/llvm/IR/IntrinsicsVE.td
index 3a8eec6d4dd5..4e682eee7cc2 100644
--- a/llvm/include/llvm/IR/IntrinsicsVE.td
+++ b/llvm/include/llvm/IR/IntrinsicsVE.td
@@ -4,6 +4,13 @@
let TargetPrefix = "ve" in {
def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">,
Intrinsic<[], [], [IntrHasSideEffects]>;
+
+ def int_ve_vl_pack_f32p : GCCBuiltin<"__builtin_ve_vl_pack_f32p">,
+Intrinsic<[llvm_i64_ty], [llvm_ptr_ty,
llvm_ptr_ty],
+ [IntrReadMem]>;
+ def int_ve_vl_pack_f32a : GCCBuiltin<"__builtin_ve_vl_pack_f32a">,
+Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
+ [IntrReadMem]>;
}
// Define intrinsics automatically generated
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
index 6cec6fece8d8..3525484af108 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -5,6 +5,18 @@
// SVOB pattern.
def : Pat<(int_ve_vl_svob), (SVOB)>;
+// Pack patterns.
+def : Pat<(i64 (int_ve_vl_pack_f32p ADDRrii:$addr0, ADDRrii:$addr1)),
+ (ORrr (f2l (LDUrii MEMrii:$addr0)),
+(i2l (LDLZXrii MEMrii:$addr1)))>;
+
+def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
+ (MULULrr
+(i2l (LDLZXrii MEMrii:$addr)),
+(LEASLrii (ANDrm (LEAzii 0, 0, (LO32 (i64 0x00010001))),
+ !add(32, 64)), 0,
+ (HI32 (i64 0x00010001>;
+
// LSV patterns.
def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/pack.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/pack.ll
new file mode 100644
index ..7ad702ace430
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/pack.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test pack intrinsic instructions
+;;;
+;;; Note:
+;;; We test pack_f32p and pack_f32a pseudo instruction.
+
+; Function Attrs: nounwind readonly
+define fastcc i64 @pack_f32p(float* readonly %0, float* readonly %1) {
+; CHECK-LABEL: pack_f32p:
+; CHECK: # %bb.0:
+; CHECK-NEXT:ldu %s0, (, %s0)
+; CHECK-NEXT:ldl.zx %s1, (, %s1)
+; CHECK-NEXT:or %s0, %s0, %s1
+; CHECK-NEXT:b.l.t (, %s10)
+ %3 = bitcast float* %0 to i8*
+ %4 = bitcast float* %1 to i8*
+ %5 = tail call i64 @llvm.ve.vl.pack.f32p(i8* %3, i8* %4)
+ ret i64 %5
+}
+
+; Function Attrs: nounwind readonly
+declare i64 @llvm.ve.vl.pack.f32p(i8*, i8*)
+
+; Function Attrs: nounwind readonly
+define fastcc i64 @pack_f32a(float* readonly %0) {
+; CHECK-LABEL: pack_f32a:
+; CHECK: # %bb.0:
+; CHECK-NEXT:ldl.zx %s0, (, %s0)
+; CHECK-NEXT:lea %s1, 1
+; CHECK-NEXT:and %s1, %s1, (32)0
+; CHECK-NEXT:lea.sl %s1, 1(, %s1)
+; CHECK-NEXT:mulu.l %s0, %s0, %s1
+; CHECK-NEXT:b.l.t (, %s10)
+ %2 = bitcast float* %0 to i8*
+ %3 = tail call i64 @llvm.ve.vl.pack.f32a(i8* %2)
+ ret i64 %3
+}
+
+; Function Attrs: nounwind readonly
+declare i64 @llvm.ve.vl.pack.f32a(i8*)
___
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[llvm-branch-commits] [llvm] b72ca79 - [VE] Support intrinsic to isnert/extract_subreg of v512i1
Author: Kazushi (Jam) Marukawa
Date: 2021-01-11T20:40:10+09:00
New Revision: b72ca799823e97b94ac0144bb87c094fb2db7324
URL:
https://github.com/llvm/llvm-project/commit/b72ca799823e97b94ac0144bb87c094fb2db7324
DIFF:
https://github.com/llvm/llvm-project/commit/b72ca799823e97b94ac0144bb87c094fb2db7324.diff
LOG: [VE] Support intrinsic to isnert/extract_subreg of v512i1
Support insert/extract_subreg intrinsic instructions for v512i1
registers and add regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94298
Added:
llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
llvm/test/CodeGen/VE/VELIntrinsics/insert.ll
Modified:
llvm/include/llvm/IR/IntrinsicsVE.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsVE.td
b/llvm/include/llvm/IR/IntrinsicsVE.td
index 4e682eee7cc2..be4bccef0cc1 100644
--- a/llvm/include/llvm/IR/IntrinsicsVE.td
+++ b/llvm/include/llvm/IR/IntrinsicsVE.td
@@ -11,6 +11,24 @@ let TargetPrefix = "ve" in {
def int_ve_vl_pack_f32a : GCCBuiltin<"__builtin_ve_vl_pack_f32a">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
[IntrReadMem]>;
+
+ def int_ve_vl_extract_vm512u :
+ GCCBuiltin<"__builtin_ve_vl_extract_vm512u">,
+ Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>;
+
+ def int_ve_vl_extract_vm512l :
+ GCCBuiltin<"__builtin_ve_vl_extract_vm512l">,
+ Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>;
+
+ def int_ve_vl_insert_vm512u :
+ GCCBuiltin<"__builtin_ve_vl_insert_vm512u">,
+ Intrinsic<[LLVMType], [LLVMType, LLVMType],
+[IntrNoMem]>;
+
+ def int_ve_vl_insert_vm512l :
+ GCCBuiltin<"__builtin_ve_vl_insert_vm512l">,
+ Intrinsic<[LLVMType], [LLVMType, LLVMType],
+[IntrNoMem]>;
}
// Define intrinsics automatically generated
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
index 3525484af108..9ccfbe1ea42e 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -17,6 +17,19 @@ def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
!add(32, 64)), 0,
(HI32 (i64 0x00010001>;
+// The extract/insert patterns.
+def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)),
+ (EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>;
+
+def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)),
+ (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>;
+
+def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
+ (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>;
+
+def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
+ (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
+
// LSV patterns.
def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
new file mode 100644
index ..0e69448d7421
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test extract intrinsic instructions
+;;;
+;;; Note:
+;;; We test extract_vm512u and extract_vm512l pseudo instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @extract_vm512u(<512 x i1> %0) {
+; CHECK-LABEL: extract_vm512u:
+; CHECK: # %bb.0:
+; CHECK-NEXT:andm %vm1, %vm0, %vm2
+; CHECK-NEXT:b.l.t (, %s10)
+ %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1> %0)
+ ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1>)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @extract_vm512l(<512 x i1> %0) {
+; CHECK-LABEL: extract_vm512l:
+; CHECK: # %bb.0:
+; CHECK-NEXT:andm %vm0, %vm0, %vm2
+; CHECK-NEXT:andm %vm1, %vm0, %vm3
+; CHECK-NEXT:b.l.t (, %s10)
+ %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1> %0)
+ ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1>)
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll
new file mode 100644
index ..faa17be94f6e
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test insert intrinsic instructions
+;;;
+;;; Note:
+;;; We test insert_vm512u and insert_vm512l pseudo instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @insert_vm512u(<512 x i1> %0, <256 x i1> %1) {
+; CHECK-LABEL: insert_vm512u:
+; CHECK: # %bb.0:
+;
[llvm-branch-commits] [llvm] d02de13 - [VE] Support additional VMRGW and VMV intrinsic instructions
Author: Kazushi (Jam) Marukawa
Date: 2021-01-11T20:50:31+09:00
New Revision: d02de13932488841eb104ad2a5665fdf7db4026b
URL:
https://github.com/llvm/llvm-project/commit/d02de13932488841eb104ad2a5665fdf7db4026b
DIFF:
https://github.com/llvm/llvm-project/commit/d02de13932488841eb104ad2a5665fdf7db4026b.diff
LOG: [VE] Support additional VMRGW and VMV intrinsic instructions
Support missing VMRGW and VMV intrinsic instructions and add regression
tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94300
Added:
Modified:
llvm/lib/Target/VE/VEInstrIntrinsicVL.td
llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
Removed:
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
index 9ccfbe1ea42e..69ea133ceed0 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -30,6 +30,24 @@ def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx,
v256i1:$vmy)),
def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
(INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
+// VMRG patterns.
+def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
+ (VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
+ v256f64:$pt, i32:$vl),
+ (VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl,
+ v256f64:$pt)>;
+
+// VMV patterns.
+def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
+ (VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
+ (VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt,
+i32:$vl),
+ (VMVrvml_v (i2l i32:$sy), v256f64:$vz, v256i1:$vm, i32:$vl,
+ v256f64:$pt)>;
+
// LSV patterns.
def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
index 0c81db934607..23b320042c3a 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
@@ -131,3 +131,38 @@ define fastcc <256 x double> @vmrgw_vvvMvl(<256 x double>
%0, <256 x double> %1,
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmrgw.vvvMvl(<256 x double>, <256 x
double>, <512 x i1>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vmrgw_vsvMl(i32 signext %0, <256 x double> %1,
<512 x i1> %2) {
+; CHECK-LABEL: vmrgw_vsvMl:
+; CHECK: # %bb.0:
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea %s1, 256
+; CHECK-NEXT:lvl %s1
+; CHECK-NEXT:vmrg.w %v0, %s0, %v0, %vm2
+; CHECK-NEXT:b.l.t (, %s10)
+ %4 = tail call fast <256 x double> @llvm.ve.vl.vmrgw.vsvMl(i32 %0, <256 x
double> %1, <512 x i1> %2, i32 256)
+ ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vmrgw.vsvMl(i32, <256 x double>, <512 x
i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vmrgw_vsvMvl(i32 signext %0, <256 x double> %1,
<512 x i1> %2, <256 x double> %3) {
+; CHECK-LABEL: vmrgw_vsvMvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea %s1, 128
+; CHECK-NEXT:lvl %s1
+; CHECK-NEXT:vmrg.w %v1, %s0, %v0, %vm2
+; CHECK-NEXT:lea %s16, 256
+; CHECK-NEXT:lvl %s16
+; CHECK-NEXT:vor %v0, (0)1, %v1
+; CHECK-NEXT:b.l.t (, %s10)
+ %5 = tail call fast <256 x double> @llvm.ve.vl.vmrgw.vsvMvl(i32 %0, <256 x
double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
+ ret <256 x double> %5
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vmrgw.vsvMvl(i32, <256 x double>, <512 x
i1>, <256 x double>, i32)
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
index 58dec2417690..c54d3dfe39d2 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
@@ -6,18 +6,19 @@
;;; We test VMVivl and VMVivl_v, and VMVivml_v instructions.
; Function Attrs: nounwind
-define void @vmv_vsvl(i8* %0, i64 %1, i32 signext %2) {
+define void @vmv_vsvl(i8* %0, i32 signext %1) {
; CHECK-LABEL: vmv_vsvl:
; CHECK: # %bb.0:
-; CHECK-NEXT:lea %s1, 256
-; CHECK-NEXT:lvl %s1
+; CHECK-NEXT:lea %s2, 256
+; CHECK-NEXT:lvl %s2
; CHECK-NEXT:vld %v0, 8, %s0
-; CHECK-NEXT:vmv %v0, 31, %v0
+; CHECK-NEXT:and %s1, %s1, (32)0
+; CHECK-NEXT:vmv %v0,
[llvm-branch-commits] [compiler-rt] 70474df - [VE][compiler-rt] Add VE as a target of crt
Author: Kazushi (Jam) Marukawa
Date: 2021-01-12T10:20:21+09:00
New Revision: 70474dfebcd9babf2e3af5fb002b40417fd6cf88
URL:
https://github.com/llvm/llvm-project/commit/70474dfebcd9babf2e3af5fb002b40417fd6cf88
DIFF:
https://github.com/llvm/llvm-project/commit/70474dfebcd9babf2e3af5fb002b40417fd6cf88.diff
LOG: [VE][compiler-rt] Add VE as a target of crt
SX Aurora VE is an experimental target. We upstreamed many part of
ported llvm and clang. In order to continue this move, we need to
support libraries next, then we need to show the ability of llvm for
VE through test cases. As a first step for that, we need to use
crt in compiler-rt. VE has it's own crt but they are a part of
proprietary compiler. So, we want to use crt in compiler-rt as an
alternative.
This patch enables VE as a candidate of crt in compiler-rt.
Reviewed By: phosek, compnerd
Differential Revision: https://reviews.llvm.org/D92748
Added:
Modified:
compiler-rt/cmake/config-ix.cmake
Removed:
diff --git a/compiler-rt/cmake/config-ix.cmake
b/compiler-rt/cmake/config-ix.cmake
index d13e75e41685..f81b8384cbd5 100644
--- a/compiler-rt/cmake/config-ix.cmake
+++ b/compiler-rt/cmake/config-ix.cmake
@@ -287,6 +287,7 @@ set(SPARC sparc)
set(SPARCV9 sparcv9)
set(WASM32 wasm32)
set(WASM64 wasm64)
+set(VE ve)
if(APPLE)
set(ARM64 arm64)
@@ -298,7 +299,7 @@ set(ALL_SANITIZER_COMMON_SUPPORTED_ARCH ${X86} ${X86_64}
${PPC64} ${RISCV64}
${ARM32} ${ARM64} ${MIPS32} ${MIPS64} ${S390X} ${SPARC} ${SPARCV9})
set(ALL_ASAN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${RISCV64}
${MIPS32} ${MIPS64} ${PPC64} ${S390X} ${SPARC} ${SPARCV9})
-set(ALL_CRT_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${RISCV32}
${RISCV64})
+set(ALL_CRT_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${RISCV32}
${RISCV64} ${VE})
set(ALL_DFSAN_SUPPORTED_ARCH ${X86_64} ${MIPS64} ${ARM64})
if(ANDROID)
___
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llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [llvm] 24faa87 - [VE] Update VELIntrinsic tests
Author: Kazushi (Jam) Marukawa
Date: 2021-01-13T00:12:50+09:00
New Revision: 24faa87075ac1b4e4d7f7336271b1ba72ffcc2c0
URL:
https://github.com/llvm/llvm-project/commit/24faa87075ac1b4e4d7f7336271b1ba72ffcc2c0
DIFF:
https://github.com/llvm/llvm-project/commit/24faa87075ac1b4e4d7f7336271b1ba72ffcc2c0.diff
LOG: [VE] Update VELIntrinsic tests
Update comment and style of regression tests for VELIntrinsic
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94490
Added:
Modified:
llvm/test/CodeGen/VE/VELIntrinsics/vand.ll
llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
Removed:
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vand.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/vand.ll
index 17ab5d97b361..749ff16cd49c 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vand.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vand.ll
@@ -4,8 +4,8 @@
;;;
;;; Note:
;;; We test VAND*vvl, VAND*vvl_v, VAND*rvl, VAND*rvl_v, VAND*vvml_v,
-;;; VAND*rvml_v, PVAND*vvl, PVAND*vvl_v, PVAND*rvl, PVAND*rvl_v,
PVAND*vvml_v, and
-;;; PVAND*rvml_v instructions.
+;;; VAND*rvml_v, PVAND*vvl, PVAND*vvl_v, PVAND*rvl, PVAND*rvl_v,
PVAND*vvml_v,
+;;; and PVAND*rvml_v instructions.
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vand_vvvl(<256 x double> %0, <256 x double> %1) {
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
index d92666194edf..6068b816f911 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
@@ -3,7 +3,7 @@
;;; Test vector load intrinsic instructions
;;;
;;; Note:
-;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, VLD*irl_v
+;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, and VLD*irl_v instructions.
; Function Attrs: nounwind
define void @vld_vssl(i8* %0, i64 %1) {
@@ -17,7 +17,7 @@ define void @vld_vssl(i8* %0, i64 %1) {
; CHECK-NEXT:#NO_APP
; CHECK-NEXT:b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32
256)
- tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3,
i64 %1, i8* %0)
+ tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double>
%3, i8* %0, i64 %1)
ret void
}
@@ -38,7 +38,7 @@ define void @vld_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-NEXT:b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32
256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0,
<256 x double> %4, i32 256)
- tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5,
i64 %1, i8* %0)
+ tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double>
%5, i8* %0, i64 %1)
ret void
}
@@ -57,7 +57,7 @@ define void @vld_vssl_imm(i8* %0) {
; CHECK-NEXT:#NO_APP
; CHECK-NEXT:b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32
256)
- tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8*
%0)
+ tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2,
i8* %0)
ret void
}
@@ -75,7 +75,7 @@ define void @vld_vssvl_imm(i8* %0, i8* %1) {
; CHECK-NEXT:b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32
256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256
x double> %3, i32 256)
- tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8*
%0)
+ tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4,
i8* %0)
ret void
}
@@ -91,7 +91,7 @@ define void @vldnc_vssl(i8* %0, i64 %1) {
; CHECK-NEXT:#NO_APP
; CHECK-NEXT:b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0,
i32 256)
- tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3,
i64 %1, i8* %0)
+ tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double>
%3, i8* %0, i64 %1)
ret void
}
@@ -112,7 +112,7 @@ define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-NEXT:b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2,
i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0,
<256 x double> %4, i32 256)
- tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5,
i64 %1, i8* %0)
+ tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double>
%5, i8* %0, i64 %1)
ret void
}
@@ -131,7 +131,7 @@ define void @vldnc_vssl_imm(i8* %0) {
; CHECK-NEXT:#NO_APP
; CHECK-NEXT:b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32
256)
- tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8*
%0)
+ tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2,
i8* %0)
[llvm-branch-commits] [llvm] 2a2268a - [VE][NFC] Sort VEISD operations
Author: Kazushi (Jam) Marukawa
Date: 2020-12-15T23:29:16+09:00
New Revision: 2a2268a6db17cbbef54c1b80f74a04849831c997
URL:
https://github.com/llvm/llvm-project/commit/2a2268a6db17cbbef54c1b80f74a04849831c997
DIFF:
https://github.com/llvm/llvm-project/commit/2a2268a6db17cbbef54c1b80f74a04849831c997.diff
LOG: [VE][NFC] Sort VEISD operations
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93294
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index ca548e056c51..d15158f4f4d2 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -865,17 +865,17 @@ const char *VETargetLowering::getTargetNodeName(unsigned
Opcode) const {
switch ((VEISD::NodeType)Opcode) {
case VEISD::FIRST_NUMBER:
break;
-TARGET_NODE_CASE(Lo)
-TARGET_NODE_CASE(Hi)
+TARGET_NODE_CASE(CALL)
TARGET_NODE_CASE(GETFUNPLT)
TARGET_NODE_CASE(GETSTACKTOP)
TARGET_NODE_CASE(GETTLSADDR)
+TARGET_NODE_CASE(GLOBAL_BASE_REG)
+TARGET_NODE_CASE(Hi)
+TARGET_NODE_CASE(Lo)
TARGET_NODE_CASE(MEMBARRIER)
-TARGET_NODE_CASE(CALL)
+TARGET_NODE_CASE(RET_FLAG)
TARGET_NODE_CASE(TS1AM)
TARGET_NODE_CASE(VEC_BROADCAST)
-TARGET_NODE_CASE(RET_FLAG)
-TARGET_NODE_CASE(GLOBAL_BASE_REG)
// Register the VVP_* SDNodes.
#define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
diff --git a/llvm/lib/Target/VE/VEISelLowering.h
b/llvm/lib/Target/VE/VEISelLowering.h
index 0eea838ff55d..b5e2a72887f4 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -24,22 +24,19 @@ namespace VEISD {
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
- Hi,
- Lo, // Hi/Lo operations, typically on a global address.
-
- GETFUNPLT, // load function address through %plt insturction
- GETTLSADDR, // load address for TLS access
- GETSTACKTOP, // retrieve address of stack top (first address of
- // locals and temporaries)
-
- MEMBARRIER, // Compiler barrier only; generate a no-op.
- TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
-
- VEC_BROADCAST, // 0: scalar value, 1: VL
-
CALL,// A call instruction.
- RET_FLAG,// Return with a flag operand.
+ GETFUNPLT, // Load function address through %plt insturction.
+ GETTLSADDR, // Load address for TLS access.
+ GETSTACKTOP, // Retrieve address of stack top (first address of
+ // locals and temporaries).
GLOBAL_BASE_REG, // Global base reg for PIC.
+ Hi, // Hi/Lo operations, typically on a global address.
+ Lo, // Hi/Lo operations, typically on a global address.
+ MEMBARRIER, // Compiler barrier only; generate a no-op.
+ RET_FLAG,// Return with a flag operand.
+ TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
+ VEC_BROADCAST, // A vector broadcast instruction.
+ // 0: scalar value, 1: VL
// VVP_* nodes.
#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
___
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[llvm-branch-commits] [llvm] 6972265 - [VE] Support FRAMEADDR
Author: Kazushi (Jam) Marukawa
Date: 2020-12-15T23:31:19+09:00
New Revision: 697226550e369e7e736411508d7d2589a2aff764
URL:
https://github.com/llvm/llvm-project/commit/697226550e369e7e736411508d7d2589a2aff764
DIFF:
https://github.com/llvm/llvm-project/commit/697226550e369e7e736411508d7d2589a2aff764.diff
LOG: [VE] Support FRAMEADDR
Implement FRAMEADDR for VE. Add a regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93295
Added:
llvm/test/CodeGen/VE/Scalar/frameaddr.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index d15158f4f4d2..408c28205aa2 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -1489,6 +1489,27 @@ SDValue
VETargetLowering::lowerDYNAMIC_STACKALLOC(SDValue Op,
return DAG.getMergeValues(Ops, DL);
}
+static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
+ const VETargetLowering &TLI,
+ const VESubtarget *Subtarget) {
+ SDLoc DL(Op);
+ MachineFunction &MF = DAG.getMachineFunction();
+ EVT PtrVT = TLI.getPointerTy(MF.getDataLayout());
+
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ MFI.setFrameAddressIsTaken(true);
+
+ unsigned Depth = Op.getConstantOperandVal(0);
+ const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
+ unsigned FrameReg = RegInfo->getFrameRegister(MF);
+ SDValue FrameAddr =
+ DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, PtrVT);
+ while (Depth--)
+FrameAddr = DAG.getLoad(Op.getValueType(), DL, DAG.getEntryNode(),
+FrameAddr, MachinePointerInfo());
+ return FrameAddr;
+}
+
static SDValue getSplatValue(SDNode *N) {
if (auto *BuildVec = dyn_cast(N)) {
return BuildVec->getSplatValue();
@@ -1529,6 +1550,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return lowerConstantPool(Op, DAG);
case ISD::DYNAMIC_STACKALLOC:
return lowerDYNAMIC_STACKALLOC(Op, DAG);
+ case ISD::FRAMEADDR:
+return lowerFRAMEADDR(Op, DAG, *this, Subtarget);
case ISD::GlobalAddress:
return lowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress:
diff --git a/llvm/test/CodeGen/VE/Scalar/frameaddr.ll
b/llvm/test/CodeGen/VE/Scalar/frameaddr.ll
new file mode 100644
index ..117ae90b6ccc
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/frameaddr.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+define i8* @test1() nounwind {
+; CHECK-LABEL: test1:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:or %s0, 0, %s9
+; CHECK-NEXT:or %s11, 0, %s9
+entry:
+ %ret = tail call i8* @llvm.frameaddress(i32 0)
+ ret i8* %ret
+}
+
+define i8* @test2() nounwind {
+; CHECK-LABEL: test2:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:ld %s0, (, %s9)
+; CHECK-NEXT:ld %s0, (, %s0)
+; CHECK-NEXT:or %s11, 0, %s9
+entry:
+ %ret = tail call i8* @llvm.frameaddress(i32 2)
+ ret i8* %ret
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
___
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[llvm-branch-commits] [llvm] af83b74 - [VE] Support copy of vector mask registers
Author: Kazushi (Jam) Marukawa
Date: 2020-12-19T09:16:43+09:00
New Revision: af83b74dc2e563c429dfcf5bd0a21dd2d4b8af7b
URL:
https://github.com/llvm/llvm-project/commit/af83b74dc2e563c429dfcf5bd0a21dd2d4b8af7b
DIFF:
https://github.com/llvm/llvm-project/commit/af83b74dc2e563c429dfcf5bd0a21dd2d4b8af7b.diff
LOG: [VE] Support copy of vector mask registers
Support VM and VMP registers in copyPhysReg() function. Also add
regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93547
Added:
Modified:
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
Removed:
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp
b/llvm/lib/Target/VE/VEInstrInfo.cpp
index 530c5d655931..9770052ff913 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -341,6 +341,11 @@ static void copyPhysSubRegs(MachineBasicBlock &MBB,
MachineInstrBuilder MIB =
BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0);
MovMI = MIB.getInstr();
+} else if (MCID.getOpcode() == VE::ANDMmm) {
+ // generate "ANDM, dest, vm0, src" instruction.
+ MachineInstrBuilder MIB =
+ BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc);
+ MovMI = MIB.getInstr();
} else {
llvm_unreachable("Unexpected reg-to-reg copy instruction");
}
@@ -379,6 +384,16 @@ void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc))
.addReg(SubTmp, getKillRegState(true));
MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true);
+ } else if (VE::VMRegClass.contains(DestReg, SrcReg)) {
+BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg)
+.addReg(VE::VM0)
+.addReg(SrcReg, getKillRegState(KillSrc));
+ } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) {
+// Use two instructions.
+const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};
+unsigned int NumSubRegs = 2;
+copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm),
+NumSubRegs, SubRegIdx, &getRegisterInfo());
} else if (VE::F128RegClass.contains(DestReg, SrcReg)) {
// Use two instructions.
const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
diff --git a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
index fe601b082192..c0ad247d0e74 100644
--- a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
+++ b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
@@ -120,3 +120,20 @@ define fastcc <256 x i32> @vreg_arg_v256i32_r6(<256 x i32>
%p0, <256 x i32> %p1,
; define <256 x i32> @vreg_arg_v256i32_r8(<256 x i32> %p0, <256 x i32> %p1,
<256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32>
%p6, <256 x i32> %p7, <256 x i32> %p8) {
; ret <256 x i32> %p8
; }
+
+define fastcc <256 x i1> @vreg_arg_v256i1_vm7(<256 x i1> %vm1, <256 x i1>
%vm2, <256 x i1> %vm3, <256 x i1> %vm4, <256 x i1> %vm5, <256 x i1> %vm6, <256
x i1> %vm7, <256 x i1> %vm8) {
+; CHECK-LABEL: vreg_arg_v256i1_vm7:
+; CHECK: # %bb.0:
+; CHECK-NEXT:andm %vm1, %vm0, %vm6
+; CHECK-NEXT:b.l.t (, %s10)
+ ret <256 x i1> %vm6
+}
+
+define fastcc <512 x i1> @vreg_arg_v512i1_vmp3(<512 x i1> %vmp1, <512 x i1>
%vmp2, <512 x i1> %vmp3, <512 x i1> %vmp4) {
+; CHECK-LABEL: vreg_arg_v512i1_vmp3:
+; CHECK: # %bb.0:
+; CHECK-NEXT:andm %vm2, %vm0, %vm6
+; CHECK-NEXT:andm %vm3, %vm0, %vm7
+; CHECK-NEXT:b.l.t (, %s10)
+ ret <512 x i1> %vmp3
+}
___
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[llvm-branch-commits] [llvm] d99e4a4 - [VE] Support RETURNADDR
Author: Kazushi (Jam) Marukawa
Date: 2020-12-21T20:06:03+09:00
New Revision: d99e4a4840d833c6e381c2ab76b15451dffb56b2
URL:
https://github.com/llvm/llvm-project/commit/d99e4a4840d833c6e381c2ab76b15451dffb56b2
DIFF:
https://github.com/llvm/llvm-project/commit/d99e4a4840d833c6e381c2ab76b15451dffb56b2.diff
LOG: [VE] Support RETURNADDR
Implement RETURNADDR for VE. Add a regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93545
Added:
llvm/test/CodeGen/VE/Scalar/returnaddr.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index 408c28205aa2..da5b6422f53d 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -1510,6 +1510,26 @@ static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG
&DAG,
return FrameAddr;
}
+static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
+ const VETargetLowering &TLI,
+ const VESubtarget *Subtarget) {
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ MFI.setReturnAddressIsTaken(true);
+
+ if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
+return SDValue();
+
+ SDValue FrameAddr = lowerFRAMEADDR(Op, DAG, TLI, Subtarget);
+
+ SDLoc DL(Op);
+ EVT VT = Op.getValueType();
+ SDValue Offset = DAG.getConstant(8, DL, VT);
+ return DAG.getLoad(VT, DL, DAG.getEntryNode(),
+ DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
+ MachinePointerInfo());
+}
+
static SDValue getSplatValue(SDNode *N) {
if (auto *BuildVec = dyn_cast(N)) {
return BuildVec->getSplatValue();
@@ -1560,6 +1580,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return lowerJumpTable(Op, DAG);
case ISD::LOAD:
return lowerLOAD(Op, DAG);
+ case ISD::RETURNADDR:
+return lowerRETURNADDR(Op, DAG, *this, Subtarget);
case ISD::BUILD_VECTOR:
return lowerBUILD_VECTOR(Op, DAG);
case ISD::STORE:
diff --git a/llvm/test/CodeGen/VE/Scalar/returnaddr.ll
b/llvm/test/CodeGen/VE/Scalar/returnaddr.ll
new file mode 100644
index ..ea1b5f687c9d
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/returnaddr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve-- | FileCheck %s
+
+define i8* @h() nounwind readnone optsize {
+; CHECK-LABEL: h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:st %s9, (, %s11)
+; CHECK-NEXT:st %s10, 8(, %s11)
+; CHECK-NEXT:or %s9, 0, %s11
+; CHECK-NEXT:lea %s11, -176(, %s11)
+; CHECK-NEXT:brge.l.t %s11, %s8, .LBB0_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT:ld %s61, 24(, %s14)
+; CHECK-NEXT:or %s62, 0, %s0
+; CHECK-NEXT:lea %s63, 315
+; CHECK-NEXT:shm.l %s63, (%s61)
+; CHECK-NEXT:shm.l %s8, 8(%s61)
+; CHECK-NEXT:shm.l %s11, 16(%s61)
+; CHECK-NEXT:monc
+; CHECK-NEXT:or %s0, 0, %s62
+; CHECK-NEXT: .LBB0_2: # %entry
+; CHECK-NEXT:ld %s0, (, %s9)
+; CHECK-NEXT:ld %s0, (, %s0)
+; CHECK-NEXT:ld %s0, 8(, %s0)
+; CHECK-NEXT:or %s11, 0, %s9
+; CHECK-NEXT:ld %s10, 8(, %s11)
+; CHECK-NEXT:ld %s9, (, %s11)
+; CHECK-NEXT:b.l.t (, %s10)
+entry:
+ %ret = tail call i8* @llvm.returnaddress(i32 2)
+ ret i8* %ret
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @g() nounwind readnone optsize {
+; CHECK-LABEL: g:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:st %s9, (, %s11)
+; CHECK-NEXT:st %s10, 8(, %s11)
+; CHECK-NEXT:or %s9, 0, %s11
+; CHECK-NEXT:lea %s11, -176(, %s11)
+; CHECK-NEXT:brge.l.t %s11, %s8, .LBB1_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT:ld %s61, 24(, %s14)
+; CHECK-NEXT:or %s62, 0, %s0
+; CHECK-NEXT:lea %s63, 315
+; CHECK-NEXT:shm.l %s63, (%s61)
+; CHECK-NEXT:shm.l %s8, 8(%s61)
+; CHECK-NEXT:shm.l %s11, 16(%s61)
+; CHECK-NEXT:monc
+; CHECK-NEXT:or %s0, 0, %s62
+; CHECK-NEXT: .LBB1_2: # %entry
+; CHECK-NEXT:ld %s0, (, %s9)
+; CHECK-NEXT:ld %s0, 8(, %s0)
+; CHECK-NEXT:or %s11, 0, %s9
+; CHECK-NEXT:ld %s10, 8(, %s11)
+; CHECK-NEXT:ld %s9, (, %s11)
+; CHECK-NEXT:b.l.t (, %s10)
+entry:
+ %ret = tail call i8* @llvm.returnaddress(i32 1)
+ ret i8* %ret
+}
+
+define i8* @f() nounwind readnone optsize {
+; CHECK-LABEL: f:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:st %s9, (, %s11)
+; CHECK-NEXT:st %s10, 8(, %s11)
+; CHECK-NEXT:or %s9, 0, %s11
+; CHECK-NEXT:lea %s11, -176(, %s11)
+; CHECK-NEXT:brge.l.t %s11, %s8, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT:ld %s61, 24(, %s14)
+; CHECK-NEXT:or %s62, 0, %s0
+; CHECK-NEXT:lea %s63, 315
+; CHECK-NEXT:shm.l %s63, (%s61)
[llvm-branch-commits] [llvm] 5e273b8 - [VE] Support STACKSAVE and STACKRESTORE
Author: Kazushi (Jam) Marukawa
Date: 2020-12-21T20:15:50+09:00
New Revision: 5e273b845bc4411c23f5da0ebbf5d4dfd6b91f13
URL:
https://github.com/llvm/llvm-project/commit/5e273b845bc4411c23f5da0ebbf5d4dfd6b91f13
DIFF:
https://github.com/llvm/llvm-project/commit/5e273b845bc4411c23f5da0ebbf5d4dfd6b91f13.diff
LOG: [VE] Support STACKSAVE and STACKRESTORE
Change to use default expanded code. Add regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93539
Added:
llvm/test/CodeGen/VE/Scalar/stacksave.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index da5b6422f53d..ea9281a00502 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -135,6 +135,10 @@ void VETargetLowering::initSPUActions() {
/// Stack {
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
+
+ // Use the default implementation.
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
/// } Stack
/// Branch {
diff --git a/llvm/test/CodeGen/VE/Scalar/stacksave.ll
b/llvm/test/CodeGen/VE/Scalar/stacksave.ll
new file mode 100644
index ..336f9b83455f
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/stacksave.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define i8* @stacksave() {
+; CHECK-LABEL: stacksave:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:or %s0, 0, %s11
+; CHECK-NEXT:or %s11, 0, %s9
+ %ret = call i8* @llvm.stacksave()
+ ret i8* %ret
+}
+
+; Function Attrs: noinline nounwind optnone
+define void @stackrestore(i8* %ptr) {
+; CHECK-LABEL: stackrestore:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:or %s11, 0, %s0
+; CHECK-NEXT:or %s11, 0, %s9
+ call void @llvm.stackrestore(i8* %ptr)
+ ret void
+}
+
+; Function Attrs: nounwind
+declare i8* @llvm.stacksave()
+; Function Attrs: nounwind
+declare void @llvm.stackrestore(i8*)
___
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[llvm-branch-commits] [llvm] a3a896d - [VE] Optimize LEA combinations
Author: Kazushi (Jam) Marukawa
Date: 2020-12-21T22:21:10+09:00
New Revision: a3a896d1cdc0fd2f87de4787120eaac08e69eb5f
URL:
https://github.com/llvm/llvm-project/commit/a3a896d1cdc0fd2f87de4787120eaac08e69eb5f
DIFF:
https://github.com/llvm/llvm-project/commit/a3a896d1cdc0fd2f87de4787120eaac08e69eb5f.diff
LOG: [VE] Optimize LEA combinations
Change to optimize references of elements of aggregate data. Also
add regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93627
Added:
llvm/test/CodeGen/VE/Scalar/lea-opt.ll
Modified:
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td
b/llvm/lib/Target/VE/VEInstrInfo.td
index fce3bf06b9d3..debd00ff6f96 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1608,6 +1608,8 @@ def vehi_only : OutPatFrag<(ops node:$hi),
(LEASLzii 0, 0, $hi)>;
def vehi_lo : OutPatFrag<(ops node:$hi, node:$lo),
(LEASLrii $lo, 0, $hi)>;
+def vehi_lo_imm : OutPatFrag<(ops node:$hi, node:$lo, node:$idx),
+ (LEASLrii $lo, $idx, $hi)>;
def vehi_baselo : OutPatFrag<(ops node:$base, node:$hi, node:$lo),
(LEASLrri $base, $lo, $hi)>;
foreach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr",
@@ -1615,6 +1617,8 @@ foreach type = [ "tblockaddress", "tconstpool",
"texternalsym", "tglobaladdr",
def : Pat<(VElo !cast(type):$lo), (velo_only $lo)>;
def : Pat<(VEhi !cast(type):$hi), (vehi_only $hi)>;
def : Pat<(add (VEhi !cast(type):$hi), I64:$lo), (vehi_lo $hi, $lo)>;
+ def : Pat<(add (add (VEhi !cast(type):$hi), I64:$lo), simm7:$val),
+(vehi_lo_imm $hi, $lo, (LO7 $val))>;
def : Pat<(add I64:$base, (add (VEhi !cast(type):$hi), I64:$lo)),
(vehi_baselo $base, $hi, $lo)>;
}
diff --git a/llvm/test/CodeGen/VE/Scalar/lea-opt.ll
b/llvm/test/CodeGen/VE/Scalar/lea-opt.ll
new file mode 100644
index ..356b27653f4f
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/lea-opt.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+; RUN: llc < %s -mtriple=ve -relocation-model=pic \
+; RUN: | FileCheck %s --check-prefix=PIC
+
+;;; Tests for lea instruction and its optimizations
+
+%struct.buffer = type { i64, [1 x i8] }
+
+@data = internal global i8 0, align 1
+@buf = internal global %struct.buffer zeroinitializer, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define nonnull i8* @lea_basic() {
+; CHECK-LABEL: lea_basic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:lea %s0, data@lo
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea.sl %s0, data@hi(, %s0)
+; CHECK-NEXT:b.l.t (, %s10)
+;
+; PIC-LABEL: lea_basic:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s15, 24(, %s11)
+; PIC-NEXT:st %s16, 32(, %s11)
+; PIC-NEXT:lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
+; PIC-NEXT:and %s15, %s15, (32)0
+; PIC-NEXT:sic %s16
+; PIC-NEXT:lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
+; PIC-NEXT:lea %s0, data@gotoff_lo
+; PIC-NEXT:and %s0, %s0, (32)0
+; PIC-NEXT:lea.sl %s0, data@gotoff_hi(%s0, %s15)
+; PIC-NEXT:ld %s16, 32(, %s11)
+; PIC-NEXT:ld %s15, 24(, %s11)
+; PIC-NEXT:b.l.t (, %s10)
+ ret i8* @data
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i8* @lea_offset() {
+; CHECK-LABEL: lea_offset:
+; CHECK: # %bb.0:
+; CHECK-NEXT:lea %s0, buf@lo
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea.sl %s0, buf@hi(8, %s0)
+; CHECK-NEXT:b.l.t (, %s10)
+;
+; PIC-LABEL: lea_offset:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s15, 24(, %s11)
+; PIC-NEXT:st %s16, 32(, %s11)
+; PIC-NEXT:lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
+; PIC-NEXT:and %s15, %s15, (32)0
+; PIC-NEXT:sic %s16
+; PIC-NEXT:lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
+; PIC-NEXT:lea %s0, buf@gotoff_lo
+; PIC-NEXT:and %s0, %s0, (32)0
+; PIC-NEXT:lea.sl %s0, buf@gotoff_hi(, %s0)
+; PIC-NEXT:lea %s0, 8(%s0, %s15)
+; PIC-NEXT:ld %s16, 32(, %s11)
+; PIC-NEXT:ld %s15, 24(, %s11)
+; PIC-NEXT:b.l.t (, %s10)
+ ret i8* getelementptr inbounds (%struct.buffer, %struct.buffer* @buf, i64 0,
i32 1, i64 0)
+}
___
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[llvm-branch-commits] [llvm] 8c2ad9e - [VE] Correct VMP allocation in calling conv
Author: Kazushi (Jam) Marukawa
Date: 2020-12-21T22:42:24+09:00
New Revision: 8c2ad9e85f677546021880dc88e24f633ccacd93
URL:
https://github.com/llvm/llvm-project/commit/8c2ad9e85f677546021880dc88e24f633ccacd93
DIFF:
https://github.com/llvm/llvm-project/commit/8c2ad9e85f677546021880dc88e24f633ccacd93.diff
LOG: [VE] Correct VMP allocation in calling conv
VE used to allocate VM1, VM2, VMP2 (VM4+VM5), and VM3. This patch
corrects to allocate VM1, VM2, VMP2 (VM4+VM5), and VM6. Also add
a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93570
Added:
Modified:
llvm/lib/Target/VE/VECallingConv.td
llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
Removed:
diff --git a/llvm/lib/Target/VE/VECallingConv.td
b/llvm/lib/Target/VE/VECallingConv.td
index 6741d1cc8eaf..93899c2cae3d 100644
--- a/llvm/lib/Target/VE/VECallingConv.td
+++ b/llvm/lib/Target/VE/VECallingConv.td
@@ -116,7 +116,7 @@ def CC_VE_Fast : CallingConv<[
// pair of vector mask --> generic vector mask registers
CCIfType<[v512i1],
CCAssignToRegWithShadow<[VMP1, VMP2, VMP3],
- [VM1, VM1, VM3]>>,
+ [VM1, VM3, VM5]>>,
// Follow the standard C CC for scalars.
CCDelegateTo
@@ -137,7 +137,7 @@ def RetCC_VE_Fast : CallingConv<[
// pair of vector mask --> generic vector mask registers
CCIfType<[v512i1],
CCAssignToRegWithShadow<[VMP1, VMP2, VMP3],
- [VM1, VM1, VM3]>>,
+ [VM1, VM3, VM5]>>,
// Follow the standard C CC for scalars.
CCDelegateTo
diff --git a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
index c0ad247d0e74..aa7b4944e7e4 100644
--- a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
+++ b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
@@ -137,3 +137,11 @@ define fastcc <512 x i1> @vreg_arg_v512i1_vmp3(<512 x i1>
%vmp1, <512 x i1> %vmp
; CHECK-NEXT:b.l.t (, %s10)
ret <512 x i1> %vmp3
}
+
+define fastcc <256 x i1> @vmp_cc_bug(<256 x i1> %vm1, <256 x i1> %vm2, <512 x
i1> %vmp2, <256 x i1> %vm6) {
+; CHECK-LABEL: vmp_cc_bug:
+; CHECK: # %bb.0:
+; CHECK-NEXT:andm %vm1, %vm0, %vm6
+; CHECK-NEXT:b.l.t (, %s10)
+ ret <256 x i1> %vm6
+}
___
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[llvm-branch-commits] [llvm] 02b2bcd - [VE] Correct types of return/argument values for getAdjustedFrameSize()
Author: Kazushi (Jam) Marukawa
Date: 2020-11-21T16:08:20+09:00
New Revision: 02b2bcd940cc61c90a966679b48d3c1a34e13139
URL:
https://github.com/llvm/llvm-project/commit/02b2bcd940cc61c90a966679b48d3c1a34e13139
DIFF:
https://github.com/llvm/llvm-project/commit/02b2bcd940cc61c90a966679b48d3c1a34e13139.diff
LOG: [VE] Correct types of return/argument values for getAdjustedFrameSize()
A getAdjustedFrameSize function may need to handle larger than 32 bits
integer, so change int to uint64_t.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91862
Added:
llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
Modified:
llvm/lib/Target/VE/VESubtarget.cpp
llvm/lib/Target/VE/VESubtarget.h
Removed:
diff --git a/llvm/lib/Target/VE/VESubtarget.cpp
b/llvm/lib/Target/VE/VESubtarget.cpp
index f9c179e18528..e15969cd6091 100644
--- a/llvm/lib/Target/VE/VESubtarget.cpp
+++ b/llvm/lib/Target/VE/VESubtarget.cpp
@@ -47,7 +47,7 @@ VESubtarget::VESubtarget(const Triple &TT, const std::string
&CPU,
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering(*this) {}
-int VESubtarget::getAdjustedFrameSize(int frameSize) const {
+uint64_t VESubtarget::getAdjustedFrameSize(uint64_t FrameSize) const {
// VE stack frame:
//
@@ -93,10 +93,10 @@ int VESubtarget::getAdjustedFrameSize(int frameSize) const {
// 16(fp) | Thread pointer register (%tp=%s14) |
// +--+
- frameSize += 176; // for RSA, RA, and FP
- frameSize = alignTo(frameSize, 16); // requires 16 bytes alignment
+ FrameSize += 176; // For RSA, RA, and FP.
+ FrameSize = alignTo(FrameSize, 16); // Requires 16 bytes alignment.
- return frameSize;
+ return FrameSize;
}
bool VESubtarget::enableMachineScheduler() const { return true; }
diff --git a/llvm/lib/Target/VE/VESubtarget.h
b/llvm/lib/Target/VE/VESubtarget.h
index 04c133342f2a..9fe2a8f1f825 100644
--- a/llvm/lib/Target/VE/VESubtarget.h
+++ b/llvm/lib/Target/VE/VESubtarget.h
@@ -72,7 +72,7 @@ class VESubtarget : public VEGenSubtargetInfo {
/// Given a actual stack size as determined by FrameInfo, this function
/// returns adjusted framesize which includes space for register window
/// spills and arguments.
- int getAdjustedFrameSize(int stackSize) const;
+ uint64_t getAdjustedFrameSize(uint64_t FrameSize) const;
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
};
diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
b/llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
new file mode 100644
index ..a6305092dc39
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
@@ -0,0 +1,440 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+; RUN: llc < %s -mtriple=ve -relocation-model=pic | FileCheck %s
--check-prefix=PIC
+
+;; Check stack frame allocation of a function which calls other functions
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_frame0(i32 signext %0) {
+; CHECK-LABEL: test_frame0:
+; CHECK: # %bb.0:
+; CHECK-NEXT:adds.w.sx %s0, 3, %s0
+; CHECK-NEXT:adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:b.l.t (, %s10)
+;
+; PIC-LABEL: test_frame0:
+; PIC: # %bb.0:
+; PIC-NEXT:adds.w.sx %s0, 3, %s0
+; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:b.l.t (, %s10)
+ %2 = add nsw i32 %0, 3
+ ret i32 %2
+}
+
+; Function Attrs: nounwind
+define i8* @test_frame32(i8* %0) {
+; CHECK-LABEL: test_frame32:
+; CHECK: # %bb.0:
+; CHECK-NEXT:st %s9, (, %s11)
+; CHECK-NEXT:st %s10, 8(, %s11)
+; CHECK-NEXT:st %s15, 24(, %s11)
+; CHECK-NEXT:st %s16, 32(, %s11)
+; CHECK-NEXT:or %s9, 0, %s11
+; CHECK-NEXT:lea %s13, -272
+; CHECK-NEXT:and %s13, %s13, (32)0
+; CHECK-NEXT:lea.sl %s11, -1(%s13, %s11)
+; CHECK-NEXT:brge.l.t %s11, %s8, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT:ld %s61, 24(, %s14)
+; CHECK-NEXT:or %s62, 0, %s0
+; CHECK-NEXT:lea %s63, 315
+; CHECK-NEXT:shm.l %s63, (%s61)
+; CHECK-NEXT:shm.l %s8, 8(%s61)
+; CHECK-NEXT:shm.l %s11, 16(%s61)
+; CHECK-NEXT:monc
+; CHECK-NEXT:or %s0, 0, %s62
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT:or %s1, 0, %s0
+; CHECK-NEXT:lea %s0, fun@lo
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea.sl %s12, fun@hi(, %s0)
+; CHECK-NEXT:lea %s0, 240(, %s11)
+; CHECK-NEXT:bsic %s10, (, %s12)
+; CHECK-NEXT:or %s11, 0, %s9
+; CHECK-NEXT:ld %s16, 32(, %s11)
+; CHECK-NEXT:ld %s15, 24(, %s11)
+; CHECK-NEXT:ld %s10, 8(, %s11)
+; CHECK-NEXT:ld %s9, (, %s11)
+; CHECK-NEXT:b.l.t (, %s10)
+;
+; PIC-LABEL: test_frame32:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s9, (, %s11)
+;
[llvm-branch-commits] [llvm] 4a1d230 - [VE][NFC] Modify function order and simplify comments
Author: Kazushi (Jam) Marukawa
Date: 2020-11-21T16:09:37+09:00
New Revision: 4a1d230fa6f4cf27e4ce0626afe6c1434eab29b2
URL:
https://github.com/llvm/llvm-project/commit/4a1d230fa6f4cf27e4ce0626afe6c1434eab29b2
DIFF:
https://github.com/llvm/llvm-project/commit/4a1d230fa6f4cf27e4ce0626afe6c1434eab29b2.diff
LOG: [VE][NFC] Modify function order and simplify comments
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index c41d0a416eaa..eb47d01afc77 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -801,30 +801,6 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT
VT,
return true;
}
-bool VETargetLowering::hasAndNot(SDValue Y) const {
- EVT VT = Y.getValueType();
-
- // VE doesn't have vector and not instruction.
- if (VT.isVector())
-return false;
-
- // VE allows
diff erent immediate values for X and Y where ~X & Y.
- // Only simm7 works for X, and only mimm works for Y on VE. However, this
- // function is used to check whether an immediate value is OK for and-not
- // instruction as both X and Y. Generating additional instruction to
- // retrieve an immediate value is no good since the purpose of this
- // function is to convert a series of 3 instructions to another series of
- // 3 instructions with better parallelism. Therefore, we return false
- // for all immediate values now.
- // FIXME: Change hasAndNot function to have two operands to make it work
- //correctly with Aurora VE.
- if (isa(Y))
-return false;
-
- // It's ok for generic registers.
- return true;
-}
-
VETargetLowering::VETargetLowering(const TargetMachine &TM,
const VESubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) {
@@ -1617,7 +1593,7 @@ SDValue VETargetLowering::PerformDAGCombine(SDNode *N,
}
//===--===//
-// VE Inline Assembly Support
+// VE Inline Assembly Support
//===--===//
VETargetLowering::ConstraintType
@@ -1666,3 +1642,27 @@ unsigned VETargetLowering::getMinimumJumpTableEntries()
const {
return TargetLowering::getMinimumJumpTableEntries();
}
+
+bool VETargetLowering::hasAndNot(SDValue Y) const {
+ EVT VT = Y.getValueType();
+
+ // VE doesn't have vector and not instruction.
+ if (VT.isVector())
+return false;
+
+ // VE allows
diff erent immediate values for X and Y where ~X & Y.
+ // Only simm7 works for X, and only mimm works for Y on VE. However, this
+ // function is used to check whether an immediate value is OK for and-not
+ // instruction as both X and Y. Generating additional instruction to
+ // retrieve an immediate value is no good since the purpose of this
+ // function is to convert a series of 3 instructions to another series of
+ // 3 instructions with better parallelism. Therefore, we return false
+ // for all immediate values now.
+ // FIXME: Change hasAndNot function to have two operands to make it work
+ //correctly with Aurora VE.
+ if (isa(Y))
+return false;
+
+ // It's ok for generic registers.
+ return true;
+}
___
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[llvm-branch-commits] [llvm] 3a30234 - [VE][NFC] Clean stack frame description
Author: Kazushi (Jam) Marukawa Date: 2020-11-23T20:59:43+09:00 New Revision: 3a302349ebd11279d0c49fbd03c66ed502968f19 URL: https://github.com/llvm/llvm-project/commit/3a302349ebd11279d0c49fbd03c66ed502968f19 DIFF: https://github.com/llvm/llvm-project/commit/3a302349ebd11279d0c49fbd03c66ed502968f19.diff LOG: [VE][NFC] Clean stack frame description Move stack frame description from VESubtarget.cpp to VEFrameLowering.cpp and add detail. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91946 Added: Modified: llvm/lib/Target/VE/VEFrameLowering.cpp llvm/lib/Target/VE/VESubtarget.cpp Removed: diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp b/llvm/lib/Target/VE/VEFrameLowering.cpp index ec18bee74329..8be298b46f0d 100644 --- a/llvm/lib/Target/VE/VEFrameLowering.cpp +++ b/llvm/lib/Target/VE/VEFrameLowering.cpp @@ -8,6 +8,105 @@ // // This file contains the VE implementation of TargetFrameLowering class. // +// On VE, stack frames are structured as follows: +// +// The stack grows downward. +// +// All of the individual frame areas on the frame below are optional, i.e. it's +// possible to create a function so that the particular area isn't present +// in the frame. +// +// At function entry, the "frame" looks as follows: +// +// | | Higher address +// |--| +// | Parameter area for this function | +// |--| +// | Register save area (RSA) for this function | +// |--| +// | Return address for this function | +// |--| +// | Frame pointer for this function | +// |--| <- sp +// | | Lower address +// +// VE doesn't use on demand stack allocation, so user code generated by LLVM +// needs to call VEOS to allocate stack frame. VE's ABI want to reduce the +// number of VEOS calls, so ABI requires to allocate not only RSA (in general +// CSR, callee saved register) area but also call frame at the prologue of +// caller function. +// +// After the prologue has run, the frame has the following general structure. +// Note that technically the last frame area (VLAs) doesn't get created until +// in the main function body, after the prologue is run. However, it's depicted +// here for completeness. +// +// | | Higher address +// |--| +// | Parameter area for this function | +// |--| +// | Register save area (RSA) for this function | +// |--| +// | Return address for this function | +// |--| +// | Frame pointer for this function | +// |--| <- fp(=old sp) +// |.empty.space.to.make.part.below.aligned.in| +// |.case.it.needs.more.than.the.standard.16-byte.| (size of this area is +// |.alignment| unknown at compile time) +// |--| +// | Local variables of fixed size including spill| +// | slots| +// |--| <- bp(not defined by ABI, +// |.variable-sized.local.variables.(VLAs)| LLVM chooses SX17) +// |..| (size of this area is +// |..| unknown at compile time) +// |--| <- stack top (returned by +// | Parameter area for callee| alloca) +// |--| +// | Register save area (RSA) for callee | +// |--| +// | Return address for callee| +// |--| +// | Frame pointer for callee | +// |--| <- sp +// | | Lower address +// +// To access the data in a frame, at-compile time, a constant offset must be +// computable from one of the pointers (fp, bp, sp) to access it. The size +// of the areas with a dotted background cannot be computed at compile-time +// if they are present, making it required to have all three of fp, bp and +// sp to be set up to be able to access all contents in the frame areas, +// assuming all of the frame areas are non-empty. +// +// For most functions, some of the frame areas are empty. For those functions, +// it may not be necessary to set up
[llvm-branch-commits] [llvm] 677e94c - [VE] Clean canRealignStack implementation
Author: Kazushi (Jam) Marukawa
Date: 2020-11-23T21:09:03+09:00
New Revision: 677e94c0f09bf48d92b57a34ba7cf2e0d94016fb
URL:
https://github.com/llvm/llvm-project/commit/677e94c0f09bf48d92b57a34ba7cf2e0d94016fb
DIFF:
https://github.com/llvm/llvm-project/commit/677e94c0f09bf48d92b57a34ba7cf2e0d94016fb.diff
LOG: [VE] Clean canRealignStack implementation
Old canRealignStack calls TRI::canRealignStack and hasReservedCallFrame.
But, this hasReservedCallFrame return true whenever for VE since VE
allocates call frame all the time. It means this canRealignStack is
identical to TRI::canRealignStack. This patch removes VE's
canRealignStack and let caller call TRI::canRealignStack directly.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91929
Added:
Modified:
llvm/lib/Target/VE/VERegisterInfo.cpp
llvm/lib/Target/VE/VERegisterInfo.h
Removed:
diff --git a/llvm/lib/Target/VE/VERegisterInfo.cpp
b/llvm/lib/Target/VE/VERegisterInfo.cpp
index 0559c330368f..07249616c249 100644
--- a/llvm/lib/Target/VE/VERegisterInfo.cpp
+++ b/llvm/lib/Target/VE/VERegisterInfo.cpp
@@ -174,26 +174,3 @@ void
VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
Register VERegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return VE::SX9;
}
-
-// VE has no architectural need for stack realignment support,
-// except that LLVM unfortunately currently implements overaligned
-// stack objects by depending upon stack realignment support.
-// If that ever changes, this can probably be deleted.
-bool VERegisterInfo::canRealignStack(const MachineFunction &MF) const {
- if (!TargetRegisterInfo::canRealignStack(MF))
-return false;
-
- // VE always has a fixed frame pointer register, so don't need to
- // worry about needing to reserve it. [even if we don't have a frame
- // pointer for our frame, it still cannot be used for other things,
- // or register window traps will be SADNESS.]
-
- // If there's a reserved call frame, we can use VE to access locals.
- if (getFrameLowering(MF)->hasReservedCallFrame(MF))
-return true;
-
- // Otherwise, we'd need a base pointer, but those aren't implemented
- // for VE at the moment.
-
- return false;
-}
diff --git a/llvm/lib/Target/VE/VERegisterInfo.h
b/llvm/lib/Target/VE/VERegisterInfo.h
index 9a32da16bea6..334fb965a986 100644
--- a/llvm/lib/Target/VE/VERegisterInfo.h
+++ b/llvm/lib/Target/VE/VERegisterInfo.h
@@ -40,8 +40,6 @@ struct VERegisterInfo : public VEGenRegisterInfo {
RegScavenger *RS = nullptr) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
-
- bool canRealignStack(const MachineFunction &MF) const override;
};
} // namespace llvm
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[llvm-branch-commits] [llvm] 590aaa5 - [VE] Remove magic numbers 176
Author: Kazushi (Jam) Marukawa
Date: 2020-11-24T00:13:24+09:00
New Revision: 590aaa5077330e97203999f08946cb2c25dd56d1
URL:
https://github.com/llvm/llvm-project/commit/590aaa5077330e97203999f08946cb2c25dd56d1
DIFF:
https://github.com/llvm/llvm-project/commit/590aaa5077330e97203999f08946cb2c25dd56d1.diff
LOG: [VE] Remove magic numbers 176
Remove magic numbers 176 from VE source codes and update comments.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91958
Added:
Modified:
llvm/lib/Target/VE/VEFrameLowering.cpp
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/lib/Target/VE/VESubtarget.cpp
llvm/lib/Target/VE/VESubtarget.h
Removed:
diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp
b/llvm/lib/Target/VE/VEFrameLowering.cpp
index 8be298b46f0d..e15e4130f74b 100644
--- a/llvm/lib/Target/VE/VEFrameLowering.cpp
+++ b/llvm/lib/Target/VE/VEFrameLowering.cpp
@@ -323,8 +323,8 @@ void VEFrameLowering::emitPrologue(MachineFunction &MF,
// Get the number of bytes to allocate from the FrameInfo
uint64_t NumBytes = MFI.getStackSize();
- // The VE ABI requires a reserved 176 bytes area at the top
- // of stack as described in VESubtarget.cpp. So, we adjust it here.
+ // The VE ABI requires a reserved area at the top of stack as described
+ // in VESubtarget.cpp. So, we adjust it here.
NumBytes = STI.getAdjustedFrameSize(NumBytes);
// Finally, ensure that the size is sufficiently aligned for the
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index eb47d01afc77..30b6aa96edec 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -341,7 +341,7 @@ SDValue VETargetLowering::LowerFormalArguments(
MachineFunction &MF = DAG.getMachineFunction();
// Get the base offset of the incoming arguments stack space.
- unsigned ArgsBaseOffset = 176;
+ unsigned ArgsBaseOffset = Subtarget->getRsaSize();
// Get the size of the preserved arguments area
unsigned ArgsPreserved = 64;
@@ -411,7 +411,7 @@ SDValue VETargetLowering::LowerFormalArguments(
// The registers are exhausted. This argument was passed on the stack.
assert(VA.isMemLoc());
// The CC_VE_Full/Half functions compute stack offsets relative to the
-// beginning of the arguments area at %fp+176.
+// beginning of the arguments area at %fp + the size of reserved area.
unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;
unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
@@ -446,7 +446,7 @@ SDValue VETargetLowering::LowerFormalArguments(
// TODO: need to calculate offset correctly once we support f128.
unsigned ArgOffset = ArgLocs.size() * 8;
VEMachineFunctionInfo *FuncInfo = MF.getInfo();
- // Skip the 176 bytes of register save area.
+ // Skip the reserved area at the top of stack.
FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset);
return Chain;
@@ -489,7 +489,7 @@ SDValue
VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
CLI.IsTailCall = false;
// Get the base offset of the outgoing arguments stack space.
- unsigned ArgsBaseOffset = 176;
+ unsigned ArgsBaseOffset = Subtarget->getRsaSize();
// Get the size of the preserved arguments area
unsigned ArgsPreserved = 8 * 8u;
@@ -631,8 +631,7 @@ SDValue
VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Create a store off the stack pointer for this argument.
SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT);
-// The argument area starts at %fp+176 in the callee frame,
-// %sp+176 in ours.
+// The argument area starts at %fp/%sp + the size of reserved area.
SDValue PtrOff =
DAG.getIntPtrConstant(VA.getLocMemOffset() + ArgsBaseOffset, DL);
PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp
b/llvm/lib/Target/VE/VEInstrInfo.cpp
index c6c77aface52..eb375ccca371 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -915,8 +915,8 @@ bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI)
const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const VEFrameLowering &TFL = *STI.getFrameLowering();
- // The VE ABI requires a reserved 176 bytes area at the top
- // of stack as described in VESubtarget.cpp. So, we adjust it here.
+ // The VE ABI requires a reserved area at the top of stack as described
+ // in VEFrameLowering.cpp. So, we adjust it here.
unsigned NumBytes = STI.getAdjustedFrameSize(0);
// Also adds the size of parameter area.
diff --git a/llvm/lib/Target/VE/VESubtarget.cpp
b/llvm/lib/Target/VE/VESubtarget.cpp
index a484e7c2c7aa..3406a613e89d 100644
--- a/llvm/lib/Target/VE/VESubtarget.cpp
+++ b/llvm/lib/Target/VE/VESubtarget.cpp
@@ -50,9 +
[llvm-branch-commits] [llvm] c2b49b2 - [VE] Add comprehensive stackframe tests
Author: Kazushi (Jam) Marukawa
Date: 2020-11-26T22:12:09+09:00
New Revision: c2b49b2fb4bfe62d64902839b39a56851cfabac7
URL:
https://github.com/llvm/llvm-project/commit/c2b49b2fb4bfe62d64902839b39a56851cfabac7
DIFF:
https://github.com/llvm/llvm-project/commit/c2b49b2fb4bfe62d64902839b39a56851cfabac7.diff
LOG: [VE] Add comprehensive stackframe tests
Add comprehensive stackframe regression tests as a preparation of
VEFrameLowering.cpp optimizations.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92170
Added:
llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
llvm/test/CodeGen/VE/Scalar/stackframe_size.ll
Modified:
llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
Removed:
diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
b/llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
new file mode 100644
index ..f180ae531a9d
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
@@ -0,0 +1,582 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+; RUN: llc < %s -mtriple=ve --frame-pointer=all \
+; RUN: | FileCheck %s --check-prefix=CHECKFP
+
+;;; Check stack frame allocation with static and dynamic stack object with
+;;; alignments as a test of getFrameIndexReference().
+
+;; Allocated buffer places from 9 to 15 bytes in 16 bytes local vars area.
+
+; Function Attrs: nounwind
+define i8* @test_frame7(i8* %0) {
+; CHECK-LABEL: test_frame7:
+; CHECK: # %bb.0:
+; CHECK-NEXT:st %s9, (, %s11)
+; CHECK-NEXT:st %s10, 8(, %s11)
+; CHECK-NEXT:st %s15, 24(, %s11)
+; CHECK-NEXT:st %s16, 32(, %s11)
+; CHECK-NEXT:or %s9, 0, %s11
+; CHECK-NEXT:lea %s13, -192
+; CHECK-NEXT:and %s13, %s13, (32)0
+; CHECK-NEXT:lea.sl %s11, -1(%s13, %s11)
+; CHECK-NEXT:brge.l.t %s11, %s8, .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT:ld %s61, 24(, %s14)
+; CHECK-NEXT:or %s62, 0, %s0
+; CHECK-NEXT:lea %s63, 315
+; CHECK-NEXT:shm.l %s63, (%s61)
+; CHECK-NEXT:shm.l %s8, 8(%s61)
+; CHECK-NEXT:shm.l %s11, 16(%s61)
+; CHECK-NEXT:monc
+; CHECK-NEXT:or %s0, 0, %s62
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT:ld1b.zx %s1, (, %s0)
+; CHECK-NEXT:lea %s0, 185(, %s11)
+; CHECK-NEXT:st1b %s1, 185(, %s11)
+; CHECK-NEXT:or %s11, 0, %s9
+; CHECK-NEXT:ld %s16, 32(, %s11)
+; CHECK-NEXT:ld %s15, 24(, %s11)
+; CHECK-NEXT:ld %s10, 8(, %s11)
+; CHECK-NEXT:ld %s9, (, %s11)
+; CHECK-NEXT:b.l.t (, %s10)
+;
+; CHECKFP-LABEL: test_frame7:
+; CHECKFP: # %bb.0:
+; CHECKFP-NEXT:st %s9, (, %s11)
+; CHECKFP-NEXT:st %s10, 8(, %s11)
+; CHECKFP-NEXT:st %s15, 24(, %s11)
+; CHECKFP-NEXT:st %s16, 32(, %s11)
+; CHECKFP-NEXT:or %s9, 0, %s11
+; CHECKFP-NEXT:lea %s13, -192
+; CHECKFP-NEXT:and %s13, %s13, (32)0
+; CHECKFP-NEXT:lea.sl %s11, -1(%s13, %s11)
+; CHECKFP-NEXT:brge.l.t %s11, %s8, .LBB0_2
+; CHECKFP-NEXT: # %bb.1:
+; CHECKFP-NEXT:ld %s61, 24(, %s14)
+; CHECKFP-NEXT:or %s62, 0, %s0
+; CHECKFP-NEXT:lea %s63, 315
+; CHECKFP-NEXT:shm.l %s63, (%s61)
+; CHECKFP-NEXT:shm.l %s8, 8(%s61)
+; CHECKFP-NEXT:shm.l %s11, 16(%s61)
+; CHECKFP-NEXT:monc
+; CHECKFP-NEXT:or %s0, 0, %s62
+; CHECKFP-NEXT: .LBB0_2:
+; CHECKFP-NEXT:ld1b.zx %s1, (, %s0)
+; CHECKFP-NEXT:lea %s0, -7(, %s9)
+; CHECKFP-NEXT:st1b %s1, -7(, %s9)
+; CHECKFP-NEXT:or %s11, 0, %s9
+; CHECKFP-NEXT:ld %s16, 32(, %s11)
+; CHECKFP-NEXT:ld %s15, 24(, %s11)
+; CHECKFP-NEXT:ld %s10, 8(, %s11)
+; CHECKFP-NEXT:ld %s9, (, %s11)
+; CHECKFP-NEXT:b.l.t (, %s10)
+ %2 = alloca [7 x i8], align 1
+ %3 = getelementptr inbounds [7 x i8], [7 x i8]* %2, i64 0, i64 0
+ %4 = load i8, i8* %0, align 1
+ store i8 %4, i8* %3, align 1
+ ret i8* %3
+}
+
+;; Allocated buffer is aligned by 8, so it places from 8 to 14 bytes in 16
+;; bytes local vars area.
+
+; Function Attrs: nounwind
+define i8* @test_frame7_align8(i8* %0) {
+; CHECK-LABEL: test_frame7_align8:
+; CHECK: # %bb.0:
+; CHECK-NEXT:st %s9, (, %s11)
+; CHECK-NEXT:st %s10, 8(, %s11)
+; CHECK-NEXT:st %s15, 24(, %s11)
+; CHECK-NEXT:st %s16, 32(, %s11)
+; CHECK-NEXT:or %s9, 0, %s11
+; CHECK-NEXT:lea %s13, -192
+; CHECK-NEXT:and %s13, %s13, (32)0
+; CHECK-NEXT:lea.sl %s11, -1(%s13, %s11)
+; CHECK-NEXT:brge.l.t %s11, %s8, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT:ld %s61, 24(, %s14)
+; CHECK-NEXT:or %s62, 0, %s0
+; CHECK-NEXT:lea %s63, 315
+; CHECK-NEXT:shm.l %s63, (%s61)
+; CHECK-NEXT:shm.l %s8, 8(%s61)
+; CHECK-NEXT:shm.l %s11, 16(%s61)
+; CHECK-NEXT:monc
+; CHECK-NEXT:or %s0, 0, %s62
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT:ld1b.zx %s1, (, %s0)
+; CHECK-NEXT:lea %s0, 184(, %s11)
+; CHECK-NEXT:st1b %s1, 184(, %s11)
+
[llvm-branch-commits] [llvm] 3bd78b7 - [VE] Optimize emitSPAdjustment function
Author: Kazushi (Jam) Marukawa
Date: 2020-11-28T08:06:31+09:00
New Revision: 3bd78b7cc00d842782226bb9884ebf8d9d1f07bd
URL:
https://github.com/llvm/llvm-project/commit/3bd78b7cc00d842782226bb9884ebf8d9d1f07bd
DIFF:
https://github.com/llvm/llvm-project/commit/3bd78b7cc00d842782226bb9884ebf8d9d1f07bd.diff
LOG: [VE] Optimize emitSPAdjustment function
Optimize emitSPAdjustment function to generate as small as possible
instructions to adjust SP.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92174
Added:
Modified:
llvm/lib/Target/VE/VEFrameLowering.cpp
llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
llvm/test/CodeGen/VE/Scalar/stackframe_size.ll
Removed:
diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp
b/llvm/lib/Target/VE/VEFrameLowering.cpp
index e15e4130f74b..951430be8f61 100644
--- a/llvm/lib/Target/VE/VEFrameLowering.cpp
+++ b/llvm/lib/Target/VE/VEFrameLowering.cpp
@@ -225,33 +225,40 @@ void VEFrameLowering::emitSPAdjustment(MachineFunction
&MF,
int64_t NumBytes,
MaybeAlign MaybeAlign) const {
DebugLoc DL;
- const VEInstrInfo &TII =
- *static_cast(MF.getSubtarget().getInstrInfo());
+ const VEInstrInfo &TII = *STI.getInstrInfo();
- if (NumBytes >= -64 && NumBytes < 63) {
+ if (NumBytes == 0) {
+// Nothing to do here.
+ } else if (isInt<7>(NumBytes)) {
+// adds.l %s11, NumBytes@lo, %s11
BuildMI(MBB, MBBI, DL, TII.get(VE::ADDSLri), VE::SX11)
.addReg(VE::SX11)
.addImm(NumBytes);
-return;
+ } else if (isInt<32>(NumBytes)) {
+// lea %s11, NumBytes@lo(, %s11)
+BuildMI(MBB, MBBI, DL, TII.get(VE::LEArii), VE::SX11)
+.addReg(VE::SX11)
+.addImm(0)
+.addImm(Lo_32(NumBytes));
+ } else {
+// Emit following codes. This clobbers SX13 which we always know is
+// available here.
+// lea %s13, NumBytes@lo
+// and %s13, %s13, (32)0
+// lea.sl %sp, NumBytes@hi(%s13, %sp)
+BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13)
+.addImm(0)
+.addImm(0)
+.addImm(Lo_32(NumBytes));
+BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13)
+.addReg(VE::SX13)
+.addImm(M0(32));
+BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11)
+.addReg(VE::SX11)
+.addReg(VE::SX13)
+.addImm(Hi_32(NumBytes));
}
- // Emit following codes. This clobbers SX13 which we always know is
- // available here.
- // lea %s13,%lo(NumBytes)
- // and %s13,%s13,(32)0
- // lea.sl %sp,%hi(NumBytes)(%sp, %s13)
- BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13)
- .addImm(0)
- .addImm(0)
- .addImm(Lo_32(NumBytes));
- BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13)
- .addReg(VE::SX13)
- .addImm(M0(32));
- BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11)
- .addReg(VE::SX11)
- .addReg(VE::SX13)
- .addImm(Hi_32(NumBytes));
-
if (MaybeAlign) {
// and %sp, %sp, Align-1
BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11)
diff --git a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
index 1d6314a02070..bc3f9d633e95 100644
--- a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
+++ b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
@@ -33,9 +33,7 @@ define i8 @func_gv() {
; PIC-NEXT:st %s15, 24(, %s11)
; PIC-NEXT:st %s16, 32(, %s11)
; PIC-NEXT:or %s9, 0, %s11
-; PIC-NEXT:lea %s13, -176
-; PIC-NEXT:and %s13, %s13, (32)0
-; PIC-NEXT:lea.sl %s11, -1(%s13, %s11)
+; PIC-NEXT:lea %s11, -176(, %s11)
; PIC-NEXT:brge.l.t %s11, %s8, .LBB1_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT:ld %s61, 24(, %s14)
@@ -75,9 +73,7 @@ define i32 @func_alloca(i32 signext %0) {
; CHECK-NEXT:st %s15, 24(, %s11)
; CHECK-NEXT:st %s16, 32(, %s11)
; CHECK-NEXT:or %s9, 0, %s11
-; CHECK-NEXT:lea %s13, -192
-; CHECK-NEXT:and %s13, %s13, (32)0
-; CHECK-NEXT:lea.sl %s11, -1(%s13, %s11)
+; CHECK-NEXT:lea %s11, -192(, %s11)
; CHECK-NEXT:brge.l.t %s11, %s8, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT:ld %s61, 24(, %s14)
@@ -104,9 +100,7 @@ define i32 @func_alloca(i32 signext %0) {
; PIC-NEXT:st %s15, 24(, %s11)
; PIC-NEXT:st %s16, 32(, %s11)
; PIC-NEXT:or %s9, 0, %s11
-; PIC-NEXT:lea %s13, -192
-; PIC-NEXT:and %s13, %s13, (32)0
-; PIC-NEXT:lea.sl %s11, -1(%s13, %s11)
+; PIC-NEXT:lea %s11, -192(, %s11)
; PIC-NEXT:brge.l.t %s11, %s8, .LBB2_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT:ld %s61, 24(, %s14)
diff --git a/llvm/test/CodeGen/VE/Scalar/stackfram
[llvm-branch-commits] [llvm] 33eac0f - [VE] Specify vector alignments
Author: Kazushi (Jam) Marukawa
Date: 2020-11-30T22:09:21+09:00
New Revision: 33eac0f2830ee3f362ec0207a3d0e5f0861de8f1
URL:
https://github.com/llvm/llvm-project/commit/33eac0f2830ee3f362ec0207a3d0e5f0861de8f1
DIFF:
https://github.com/llvm/llvm-project/commit/33eac0f2830ee3f362ec0207a3d0e5f0861de8f1.diff
LOG: [VE] Specify vector alignments
Specify alignments for all vector types. Update a regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92256
Added:
Modified:
clang/lib/Basic/Targets/VE.h
clang/test/CodeGen/target-data.c
llvm/lib/Target/VE/VETargetMachine.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/VE.h b/clang/lib/Basic/Targets/VE.h
index b8143747a38d..2d9c74ac5247 100644
--- a/clang/lib/Basic/Targets/VE.h
+++ b/clang/lib/Basic/Targets/VE.h
@@ -45,7 +45,9 @@ class LLVM_LIBRARY_VISIBILITY VETargetInfo : public
TargetInfo {
WCharType = UnsignedInt;
WIntType = UnsignedInt;
UseZeroLengthBitfieldAlignment = true;
-resetDataLayout("e-m:e-i64:64-n32:64-S128");
+resetDataLayout(
+"e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-"
+"v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64");
}
void getTargetDefines(const LangOptions &Opts,
diff --git a/clang/test/CodeGen/target-data.c
b/clang/test/CodeGen/target-data.c
index 82a0a867526b..1d7ed500340c 100644
--- a/clang/test/CodeGen/target-data.c
+++ b/clang/test/CodeGen/target-data.c
@@ -281,4 +281,4 @@
// RUN: %clang_cc1 -triple ve -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=VE
-// VE: target datalayout = "e-m:e-i64:64-n32:64-S128"
+// VE: target datalayout =
"e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64"
diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp
b/llvm/lib/Target/VE/VETargetMachine.cpp
index 12c4f4628811..1077abc54141 100644
--- a/llvm/lib/Target/VE/VETargetMachine.cpp
+++ b/llvm/lib/Target/VE/VETargetMachine.cpp
@@ -44,6 +44,19 @@ static std::string computeDataLayout(const Triple &T) {
// Stack alignment is 128 bits
Ret += "-S128";
+ // Vector alignments are 64 bits
+ // Need to define all of them. Otherwise, each alignment becomes
+ // the size of each data by default.
+ Ret += "-v64:64:64"; // for v2f32
+ Ret += "-v128:64:64";
+ Ret += "-v256:64:64";
+ Ret += "-v512:64:64";
+ Ret += "-v1024:64:64";
+ Ret += "-v2048:64:64";
+ Ret += "-v4096:64:64";
+ Ret += "-v8192:64:64";
+ Ret += "-v16384:64:64"; // for v256f64
+
return Ret;
}
___
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[llvm-branch-commits] [llvm] 44a679e - [VE] Change the behaviour of truncate
Author: Kazushi (Jam) Marukawa
Date: 2020-11-30T22:12:45+09:00
New Revision: 44a679eaa40cf234c79c241012607ed5f7bada77
URL:
https://github.com/llvm/llvm-project/commit/44a679eaa40cf234c79c241012607ed5f7bada77
DIFF:
https://github.com/llvm/llvm-project/commit/44a679eaa40cf234c79c241012607ed5f7bada77.diff
LOG: [VE] Change the behaviour of truncate
Change the way to truncate i64 to i32 in I64 registers. VE assumed
sext values previously. Change it to zext values this time to make
it match to the LLVM behaviour.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92226
Added:
Modified:
llvm/lib/Target/VE/VEInstrInfo.td
llvm/test/CodeGen/VE/Scalar/br_jt.ll
llvm/test/CodeGen/VE/Scalar/select.ll
llvm/test/CodeGen/VE/Scalar/select_cc.ll
llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
llvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll
llvm/test/CodeGen/VE/Vector/vec_add.ll
llvm/test/CodeGen/VE/Vector/vec_broadcast.ll
Removed:
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td
b/llvm/lib/Target/VE/VEInstrInfo.td
index 86635adf9ef2..5837267aa63b 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1656,7 +1656,7 @@ def : Pat<(i32 (and (trunc i64:$src), 0x)),
// Cast to i32
def : Pat<(i32 (trunc i64:$src)),
- (ADDSWSXrm (EXTRACT_SUBREG $src, sub_i32), 0)>;
+ (EXTRACT_SUBREG (ANDrm $src, !add(32, 64)), sub_i32)>;
def : Pat<(i32 (fp_to_sint f32:$src)), (CVTWSSXr RD_RZ, $src)>;
def : Pat<(i32 (fp_to_sint f64:$src)), (CVTWDSXr RD_RZ, $src)>;
def : Pat<(i32 (fp_to_sint f128:$src)), (CVTWDSXr RD_RZ, (CVTDQr $src))>;
diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
index d84e830299ff..88d5378830a1 100644
--- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
@@ -10,7 +10,7 @@
define signext i32 @br_jt3(i32 signext %0) {
; CHECK-LABEL: br_jt3:
; CHECK: # %bb.0:
-; CHECK-NEXT:adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:and %s0, %s0, (32)0
; CHECK-NEXT:breq.w 1, %s0, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT:breq.w 4, %s0, .LBB{{[0-9]+}}_5
@@ -32,7 +32,7 @@ define signext i32 @br_jt3(i32 signext %0) {
;
; PIC-LABEL: br_jt3:
; PIC: # %bb.0:
-; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:breq.w 1, %s0, .LBB0_1
; PIC-NEXT: # %bb.2:
; PIC-NEXT:breq.w 4, %s0, .LBB0_5
@@ -75,7 +75,7 @@ define signext i32 @br_jt3(i32 signext %0) {
define signext i32 @br_jt4(i32 signext %0) {
; CHECK-LABEL: br_jt4:
; CHECK: # %bb.0:
-; CHECK-NEXT:adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:and %s0, %s0, (32)0
; CHECK-NEXT:adds.w.sx %s1, -1, %s0
; CHECK-NEXT:cmpu.w %s2, 3, %s1
; CHECK-NEXT:brgt.w 0, %s2, .LBB{{[0-9]+}}_2
@@ -93,7 +93,7 @@ define signext i32 @br_jt4(i32 signext %0) {
;
; PIC-LABEL: br_jt4:
; PIC: .LBB{{[0-9]+}}_5:
-; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:adds.w.sx %s1, -1, %s0
; PIC-NEXT:cmpu.w %s2, 3, %s1
; PIC-NEXT:lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
@@ -131,7 +131,7 @@ define signext i32 @br_jt4(i32 signext %0) {
define signext i32 @br_jt7(i32 signext %0) {
; CHECK-LABEL: br_jt7:
; CHECK: # %bb.0:
-; CHECK-NEXT:adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:and %s0, %s0, (32)0
; CHECK-NEXT:adds.w.sx %s1, -1, %s0
; CHECK-NEXT:cmpu.w %s2, 8, %s1
; CHECK-NEXT:brgt.w 0, %s2, .LBB{{[0-9]+}}_3
@@ -156,7 +156,7 @@ define signext i32 @br_jt7(i32 signext %0) {
;
; PIC-LABEL: br_jt7:
; PIC: .LBB{{[0-9]+}}_6:
-; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:adds.w.sx %s1, -1, %s0
; PIC-NEXT:cmpu.w %s2, 8, %s1
; PIC-NEXT:lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
@@ -208,7 +208,7 @@ define signext i32 @br_jt7(i32 signext %0) {
define signext i32 @br_jt8(i32 signext %0) {
; CHECK-LABEL: br_jt8:
; CHECK: # %bb.0:
-; CHECK-NEXT:adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:and %s0, %s0, (32)0
; CHECK-NEXT:adds.w.sx %s1, -1, %s0
; CHECK-NEXT:cmpu.w %s2, 8, %s1
; CHECK-NEXT:brgt.w 0, %s2, .LBB{{[0-9]+}}_3
@@ -233,7 +233,7 @@ define signext i32 @br_jt8(i32 signext %0) {
;
; PIC-LABEL: br_jt8:
; PIC: .LBB{{[0-9]+}}_6:
-; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:adds.w.sx %s1, -1, %s0
; PIC-NEXT:cmpu.w %s2, 8, %s1
; PIC-NEXT:lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
@@ -285,7 +285,7 @@ define signext i32 @br_jt8(i32 signext %0) {
define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_jt3_m:
; CHECK: # %bb.0:
-; CHECK-NEXT:adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:and %s0, %s0, (32)0
; CHECK-NEXT:breq.w 1, %s0,
[llvm-branch-commits] [llvm] 686988a - [VE] Optimize prologue/epilogue instructions
Author: Kazushi (Jam) Marukawa
Date: 2020-11-30T22:22:33+09:00
New Revision: 686988a50f5009df5a7f184b7debfe012b29bbf8
URL:
https://github.com/llvm/llvm-project/commit/686988a50f5009df5a7f184b7debfe012b29bbf8
DIFF:
https://github.com/llvm/llvm-project/commit/686988a50f5009df5a7f184b7debfe012b29bbf8.diff
LOG: [VE] Optimize prologue/epilogue instructions
Optimize eliminate FP mechanism. This time optimize a function which has
no call but fixed stack objects. LLVM eliminates FP on such functions now.
Also, optimize GOT/PLT registers save/restore instructions if a given
function doesn't uses them. In addition, remove generating mechanism of
`.cfi` instructions since those are taken from other architectures and not
inspected yet. Update regression tests, also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92251
Added:
Modified:
llvm/lib/Target/VE/VEFrameLowering.cpp
llvm/lib/Target/VE/VEFrameLowering.h
llvm/test/CodeGen/VE/Scalar/callee.ll
llvm/test/CodeGen/VE/Scalar/fabs.ll
llvm/test/CodeGen/VE/Scalar/fcopysign.ll
llvm/test/CodeGen/VE/Scalar/fp_fneg.ll
llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
llvm/test/CodeGen/VE/Scalar/load-align1.ll
llvm/test/CodeGen/VE/Scalar/load-align2.ll
llvm/test/CodeGen/VE/Scalar/load-align4.ll
llvm/test/CodeGen/VE/Scalar/load-align8.ll
llvm/test/CodeGen/VE/Scalar/load.ll
llvm/test/CodeGen/VE/Scalar/loadrri.ll
llvm/test/CodeGen/VE/Scalar/sext_zext_load.ll
llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
llvm/test/CodeGen/VE/Scalar/stackframe_size.ll
llvm/test/CodeGen/VE/Scalar/store-align1.ll
llvm/test/CodeGen/VE/Scalar/store-align2.ll
llvm/test/CodeGen/VE/Scalar/store-align4.ll
llvm/test/CodeGen/VE/Scalar/store-align8.ll
llvm/test/CodeGen/VE/Scalar/store.ll
llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
Removed:
diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp
b/llvm/lib/Target/VE/VEFrameLowering.cpp
index 951430be8f61..7042068f1154 100644
--- a/llvm/lib/Target/VE/VEFrameLowering.cpp
+++ b/llvm/lib/Target/VE/VEFrameLowering.cpp
@@ -137,45 +137,47 @@ void VEFrameLowering::emitPrologueInsns(MachineFunction
&MF,
MachineBasicBlock::iterator MBBI,
uint64_t NumBytes,
bool RequireFPUpdate) const {
+ const VEMachineFunctionInfo *FuncInfo = MF.getInfo();
DebugLoc DL;
- const VEInstrInfo &TII =
- *static_cast(MF.getSubtarget().getInstrInfo());
+ const VEInstrInfo &TII = *STI.getInstrInfo();
// Insert following codes here as prologue
//
- //st %fp, 0(,%sp)
- //st %lr, 8(,%sp)
- //st %got, 24(,%sp)
- //st %plt, 32(,%sp)
- //st %s17, 40(,%sp) iff this function is using s17 as BP
- //or %fp, 0, %sp
- BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
- .addReg(VE::SX11)
- .addImm(0)
- .addImm(0)
- .addReg(VE::SX9);
- BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
- .addReg(VE::SX11)
- .addImm(0)
- .addImm(8)
- .addReg(VE::SX10);
- BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
- .addReg(VE::SX11)
- .addImm(0)
- .addImm(24)
- .addReg(VE::SX15);
- BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
- .addReg(VE::SX11)
- .addImm(0)
- .addImm(32)
- .addReg(VE::SX16);
+ //st %fp, 0(, %sp) iff !isLeafProc
+ //st %lr, 8(, %sp) iff !isLeafProc
+ //st %got, 24(, %sp) iff hasGOT
+ //st %plt, 32(, %sp) iff hasGOT
+ //st %s17, 40(, %sp) iff hasBP
+ if (!FuncInfo->isLeafProc()) {
+BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
+.addReg(VE::SX11)
+.addImm(0)
+.addImm(0)
+.addReg(VE::SX9);
+BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
+.addReg(VE::SX11)
+.addImm(0)
+.addImm(8)
+.addReg(VE::SX10);
+ }
+ if (hasGOT(MF)) {
+BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
+.addReg(VE::SX11)
+.addImm(0)
+.addImm(24)
+.addReg(VE::SX15);
+BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
+.addReg(VE::SX11)
+.addImm(0)
+.addImm(32)
+.addReg(VE::SX16);
+ }
if (hasBP(MF))
BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
.addReg(VE::SX11)
.addImm(0)
.addImm(40)
.addReg(VE::SX17);
- BuildMI(MBB, MBBI, DL, TII.get(VE::ORri),
VE::SX9).addReg(VE::SX11).addImm(0);
}
void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF,
@@ -183,40 +185,42 @@ void VEFrameLowering::emitEpilogueInsns(MachineFunction
&MF,
MachineBasicBlock::iterator MBBI,
uint64_t NumBytes,
[llvm-branch-commits] [llvm] 6fe6105 - [VE] Clean check routines of branch types
Author: Kazushi (Jam) Marukawa
Date: 2020-12-01T02:19:37+09:00
New Revision: 6fe610535f4e0654766a1ace6acafc22150c951d
URL:
https://github.com/llvm/llvm-project/commit/6fe610535f4e0654766a1ace6acafc22150c951d
DIFF:
https://github.com/llvm/llvm-project/commit/6fe610535f4e0654766a1ace6acafc22150c951d.diff
LOG: [VE] Clean check routines of branch types
Previously, these check routines accepted non-generatble instructions.
This time, I clean them and add assert for those non-generatable
instructions.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92254
Added:
llvm/test/CodeGen/VE/Scalar/br_analyze.ll
Modified:
llvm/lib/Target/VE/VEInstrInfo.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp
b/llvm/lib/Target/VE/VEInstrInfo.cpp
index eb375ccca371..1dfb1d8985c4 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -92,38 +92,46 @@ static VECC::CondCode
GetOppositeBranchCondition(VECC::CondCode CC) {
llvm_unreachable("Invalid cond code");
}
-// Treat br.l [BRCF AT] as unconditional branch
+// Treat a branch relative long always instruction as unconditional branch.
+// For example, br.l.t and br.l.
static bool isUncondBranchOpcode(int Opc) {
- return Opc == VE::BRCFLa|| Opc == VE::BRCFWa||
- Opc == VE::BRCFLa_nt || Opc == VE::BRCFWa_nt ||
- Opc == VE::BRCFLa_t || Opc == VE::BRCFWa_t ||
- Opc == VE::BRCFDa|| Opc == VE::BRCFSa||
- Opc == VE::BRCFDa_nt || Opc == VE::BRCFSa_nt ||
- Opc == VE::BRCFDa_t || Opc == VE::BRCFSa_t;
+ using namespace llvm::VE;
+
+#define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t)
+ // VE has other branch relative always instructions for word/double/float,
+ // but we use only long branches in our lower. So, sanity check it here.
+ assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) &&
+ "Branch relative word/double/float always instructions should not be "
+ "used!");
+ return BRKIND(BRCFL);
+#undef BRKIND
}
+// Treat branch relative conditional as conditional branch instructions.
+// For example, brgt.l.t and brle.s.nt.
static bool isCondBranchOpcode(int Opc) {
- return Opc == VE::BRCFLrr|| Opc == VE::BRCFLir||
- Opc == VE::BRCFLrr_nt || Opc == VE::BRCFLir_nt ||
- Opc == VE::BRCFLrr_t || Opc == VE::BRCFLir_t ||
- Opc == VE::BRCFWrr|| Opc == VE::BRCFWir||
- Opc == VE::BRCFWrr_nt || Opc == VE::BRCFWir_nt ||
- Opc == VE::BRCFWrr_t || Opc == VE::BRCFWir_t ||
- Opc == VE::BRCFDrr|| Opc == VE::BRCFDir||
- Opc == VE::BRCFDrr_nt || Opc == VE::BRCFDir_nt ||
- Opc == VE::BRCFDrr_t || Opc == VE::BRCFDir_t ||
- Opc == VE::BRCFSrr|| Opc == VE::BRCFSir||
- Opc == VE::BRCFSrr_nt || Opc == VE::BRCFSir_nt ||
- Opc == VE::BRCFSrr_t || Opc == VE::BRCFSir_t;
+ using namespace llvm::VE;
+
+#define BRKIND(NAME)
\
+ (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t ||
\
+ Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t)
+ return BRKIND(BRCFL) || BRKIND(BRCFW) || BRKIND(BRCFD) || BRKIND(BRCFS);
+#undef BRKIND
}
+// Treat branch long always instructions as indirect branch.
+// For example, b.l.t and b.l.
static bool isIndirectBranchOpcode(int Opc) {
- return Opc == VE::BCFLari|| Opc == VE::BCFLari||
- Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt ||
- Opc == VE::BCFLari_t || Opc == VE::BCFLari_t ||
- Opc == VE::BCFLari|| Opc == VE::BCFLari||
- Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt ||
- Opc == VE::BCFLari_t || Opc == VE::BCFLari_t;
+ using namespace llvm::VE;
+
+#define BRKIND(NAME)
\
+ (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t)
+ // VE has other branch always instructions for word/double/float, but
+ // we use only long branches in our lower. So, sanity check it here.
+ assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) &&
+ "Branch word/double/float always instructions should not be used!");
+ return BRKIND(BCFL);
+#undef BRKIND
}
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
diff --git a/llvm/test/CodeGen/VE/Scalar/br_analyze.ll
b/llvm/test/CodeGen/VE/Scalar/br_analyze.ll
new file mode 100644
index ..b983fb67c2ee
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/br_analyze.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+declare void @foo() noreturn
+
+;;; Check a case where a separate branch is needed and where the original
+;;; order should be reversed. Copied from Syst
[llvm-branch-commits] [llvm] 6834b3d - [VE] Optimize prologue/epilogue instructions about GOT
Author: Kazushi (Jam) Marukawa
Date: 2020-12-01T02:22:31+09:00
New Revision: 6834b3d6d52a4083113eea52e2afb4d2c915602c
URL:
https://github.com/llvm/llvm-project/commit/6834b3d6d52a4083113eea52e2afb4d2c915602c
DIFF:
https://github.com/llvm/llvm-project/commit/6834b3d6d52a4083113eea52e2afb4d2c915602c.diff
LOG: [VE] Optimize prologue/epilogue instructions about GOT
Optimize prologue/epilogue instructions if a given function use GOT but
do not call other functions by eliminating FP. Previously, we had wrong
implementations taken from other architectures. Update regression tests
also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92313
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/test/CodeGen/VE/Scalar/br_jt.ll
llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
llvm/test/CodeGen/VE/Scalar/pic_access_data.ll
llvm/test/CodeGen/VE/Scalar/pic_access_static_data.ll
llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index cc7f5f6800ec..25a3910a48e4 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -913,10 +913,6 @@ SDValue VETargetLowering::makeAddress(SDValue Op,
SelectionDAG &DAG) const {
// Handle PIC mode first. VE needs a got load for every variable!
if (isPositionIndependent()) {
-// GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
-// function has calls.
-MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
-MFI.setHasCalls(true);
auto GlobalN = dyn_cast(Op);
if (isa(Op) || isa(Op) ||
diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
index 88d5378830a1..3000ff27251a 100644
--- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
@@ -92,7 +92,9 @@ define signext i32 @br_jt4(i32 signext %0) {
; CHECK-NEXT:b.l.t (, %s10)
;
; PIC-LABEL: br_jt4:
-; PIC: .LBB{{[0-9]+}}_5:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s15, 24(, %s11)
+; PIC-NEXT:st %s16, 32(, %s11)
; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:adds.w.sx %s1, -1, %s0
; PIC-NEXT:cmpu.w %s2, 3, %s1
@@ -112,7 +114,9 @@ define signext i32 @br_jt4(i32 signext %0) {
; PIC-NEXT: .LBB1_2:
; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
; PIC-NEXT: .LBB1_3:
-; PIC-NEXT:or %s11, 0, %s9
+; PIC-NEXT:ld %s16, 32(, %s11)
+; PIC-NEXT:ld %s15, 24(, %s11)
+; PIC-NEXT:b.l.t (, %s10)
%2 = add i32 %0, -1
%3 = icmp ult i32 %2, 4
br i1 %3, label %4, label %8
@@ -155,7 +159,9 @@ define signext i32 @br_jt7(i32 signext %0) {
; CHECK-NEXT:b.l.t (, %s10)
;
; PIC-LABEL: br_jt7:
-; PIC: .LBB{{[0-9]+}}_6:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s15, 24(, %s11)
+; PIC-NEXT:st %s16, 32(, %s11)
; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:adds.w.sx %s1, -1, %s0
; PIC-NEXT:cmpu.w %s2, 8, %s1
@@ -182,7 +188,9 @@ define signext i32 @br_jt7(i32 signext %0) {
; PIC-NEXT:lea.sl %s1, .Lswitch.table.br_jt7@gotoff_hi(%s1, %s15)
; PIC-NEXT:ldl.sx %s0, (%s0, %s1)
; PIC-NEXT: .LBB2_4:
-; PIC-NEXT:or %s11, 0, %s9
+; PIC-NEXT:ld %s16, 32(, %s11)
+; PIC-NEXT:ld %s15, 24(, %s11)
+; PIC-NEXT:b.l.t (, %s10)
%2 = add i32 %0, -1
%3 = icmp ult i32 %2, 9
br i1 %3, label %4, label %13
@@ -232,7 +240,9 @@ define signext i32 @br_jt8(i32 signext %0) {
; CHECK-NEXT:b.l.t (, %s10)
;
; PIC-LABEL: br_jt8:
-; PIC: .LBB{{[0-9]+}}_6:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s15, 24(, %s11)
+; PIC-NEXT:st %s16, 32(, %s11)
; PIC-NEXT:and %s0, %s0, (32)0
; PIC-NEXT:adds.w.sx %s1, -1, %s0
; PIC-NEXT:cmpu.w %s2, 8, %s1
@@ -259,7 +269,9 @@ define signext i32 @br_jt8(i32 signext %0) {
; PIC-NEXT:lea.sl %s1, .Lswitch.table.br_jt8@gotoff_hi(%s1, %s15)
; PIC-NEXT:ldl.sx %s0, (%s0, %s1)
; PIC-NEXT: .LBB3_4:
-; PIC-NEXT:or %s11, 0, %s9
+; PIC-NEXT:ld %s16, 32(, %s11)
+; PIC-NEXT:ld %s15, 24(, %s11)
+; PIC-NEXT:b.l.t (, %s10)
%2 = add i32 %0, -1
%3 = icmp ult i32 %2, 9
br i1 %3, label %4, label %13
@@ -625,7 +637,9 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext
%1) {
; CHECK-NEXT:b.l.t (, %s10)
;
; PIC-LABEL: br_jt8_m:
-; PIC: .LBB{{[0-9]+}}_12:
+; PIC: # %bb.0:
+; PIC-NEXT:st %s15, 24(, %s11)
+; PIC-NEXT:st %s16, 32(, %s11)
; PIC-NEXT:and %s2, %s0, (32)0
; PIC-NEXT:adds.w.sx %s0, -1, %s2
; PIC-NEXT:cmpu.w %s3, 8, %s0
@@ -673,7 +687,9 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext
%1) {
; PIC-NEXT:or %s0, 10, (0)1
; PIC-NEXT: .LBB7_10:
; PIC-NEXT:adds.w.sx %s0, %s0, (0)1
-; PIC-NEXT:or %s11, 0, %s9
+; PIC-NEXT:ld %s16, 32(, %s11)
+; PIC-NEXT:ld %s15, 24(, %s11)
+; PIC-NEXT:b.l.t (, %s10)
switch i32 %
[llvm-branch-commits] [llvm] 3d872cb - [VE][NFC] Update comments
Author: Kazushi (Jam) Marukawa
Date: 2020-12-01T02:56:16+09:00
New Revision: 3d872cbc2fd3d7ff43b1058da03a91bea51414c7
URL:
https://github.com/llvm/llvm-project/commit/3d872cbc2fd3d7ff43b1058da03a91bea51414c7
DIFF:
https://github.com/llvm/llvm-project/commit/3d872cbc2fd3d7ff43b1058da03a91bea51414c7.diff
LOG: [VE][NFC] Update comments
Update comments. I forgot to update it previously when I modified code.
Added:
Modified:
llvm/lib/Target/VE/VEFrameLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp
b/llvm/lib/Target/VE/VEFrameLowering.cpp
index 7042068f1154..9e97d0eca833 100644
--- a/llvm/lib/Target/VE/VEFrameLowering.cpp
+++ b/llvm/lib/Target/VE/VEFrameLowering.cpp
@@ -493,8 +493,8 @@ void VEFrameLowering::determineCalleeSaves(MachineFunction
&MF,
RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
- // Functions having BP or stack objects need to emit prologue and epilogue
- // to allocate local buffer on the stack.
+ // Functions having BP need to emit prologue and epilogue to allocate local
+ // buffer on the stack even if the function is a leaf function.
if (isLeafProc(MF) && !hasBP(MF)) {
VEMachineFunctionInfo *FuncInfo = MF.getInfo();
FuncInfo->setLeafProc(true);
___
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[llvm-branch-commits] [llvm] dd0159b - [VE] Add vand, vor, and vxor intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-02T22:52:54+09:00 New Revision: dd0159bd814132473fceaba43b864c6db64c96ab URL: https://github.com/llvm/llvm-project/commit/dd0159bd814132473fceaba43b864c6db64c96ab DIFF: https://github.com/llvm/llvm-project/commit/dd0159bd814132473fceaba43b864c6db64c96ab.diff LOG: [VE] Add vand, vor, and vxor intrinsic instructions Add vand, vor, and vxor intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92454 Added: llvm/test/CodeGen/VE/VELIntrinsics/vand.ll llvm/test/CodeGen/VE/VELIntrinsics/vor.ll llvm/test/CodeGen/VE/VELIntrinsics/vxor.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index 10758eaf483a..7c3b523b16b4 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -359,3 +359,39 @@ let TargetPrefix = "ve" in def int_ve_vl_vminsl_vsvl : GCCBuiltin<"__builtin_ve_ let TargetPrefix = "ve" in def int_ve_vl_vminsl_vsvvl : GCCBuiltin<"__builtin_ve_vl_vminsl_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vminsl_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vminsl_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vminsl_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vminsl_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vand_vvvl : GCCBuiltin<"__builtin_ve_vl_vand_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vand_l : GCCBuiltin<"__builtin_ve_vl_vand_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vand_vsvl : GCCBuiltin<"__builtin_ve_vl_vand_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vand_vsvvl : GCCBuiltin<"__builtin_ve_vl_vand_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vand_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vand_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vand_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vand_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvand_vvvl : GCCBuiltin<"__builtin_ve_vl_pvand_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvand_l : GCCBuiltin<"__builtin_ve_vl_pvand_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvand_vsvl : GCCBuiltin<"__builtin_ve_vl_pvand_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvand_vsvvl : GCCBuiltin<"__builtin_ve_vl_pvand_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvand_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pvand_vvvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvand_vsvMvl : GCCBuiltin<"__builtin_ve_vl_pvand_vsvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vor_vvvl : GCCBuiltin<"__builtin_ve_vl_vor_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vor_l : GCCBuiltin<"__builtin_ve_vl_vor_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vor_vsvl : GCCBuiltin<"__builtin_ve_vl_vor_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vor_vsvvl : GCCBuiltin<"__builtin_ve_vl_vor_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vor_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vor_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vor_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vor_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix
[llvm-branch-commits] [llvm] b912381 - [VE] Add veqv and vseq intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-03T17:39:24+09:00 New Revision: b91238173dd9ef84a78c77c099cc26f934443a05 URL: https://github.com/llvm/llvm-project/commit/b91238173dd9ef84a78c77c099cc26f934443a05 DIFF: https://github.com/llvm/llvm-project/commit/b91238173dd9ef84a78c77c099cc26f934443a05.diff LOG: [VE] Add veqv and vseq intrinsic instructions Add veqv and vseq intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92527 Added: llvm/test/CodeGen/VE/VELIntrinsics/veqv.ll llvm/test/CodeGen/VE/VELIntrinsics/vseq.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index 7c3b523b16b4..116cdc6fcc6a 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -395,3 +395,23 @@ let TargetPrefix = "ve" in def int_ve_vl_pvxor_vsvl : GCCBuiltin<"__builtin_ve_v let TargetPrefix = "ve" in def int_ve_vl_pvxor_vsvvl : GCCBuiltin<"__builtin_ve_vl_pvxor_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvxor_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pvxor_vvvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvxor_vsvMvl : GCCBuiltin<"__builtin_ve_vl_pvxor_vsvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_veqv_vvvl : GCCBuiltin<"__builtin_ve_vl_veqv_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_veqv_l : GCCBuiltin<"__builtin_ve_vl_veqv_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_veqv_vsvl : GCCBuiltin<"__builtin_ve_vl_veqv_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_veqv_vsvvl : GCCBuiltin<"__builtin_ve_vl_veqv_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_veqv_vvvmvl : GCCBuiltin<"__builtin_ve_vl_veqv_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_veqv_vsvmvl : GCCBuiltin<"__builtin_ve_vl_veqv_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pveqv_vvvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pveqv_l : GCCBuiltin<"__builtin_ve_vl_pveqv_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pveqv_vsvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pveqv_vsvvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pveqv_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vvvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pveqv_vsvMvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vsvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vseq_vl : GCCBuiltin<"__builtin_ve_vl_vseq_vl">, Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vseq_vvl : GCCBuiltin<"__builtin_ve_vl_vseq_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvseqlo_vl : GCCBuiltin<"__builtin_ve_vl_pvseqlo_vl">, Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvseqlo_vvl : GCCBuiltin<"__builtin_ve_vl_pvseqlo_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsequp_vl : GCCBuiltin<"__builtin_ve_vl_pvsequp_vl">, Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsequp_vvl : GCCBuiltin<"__builtin_ve_vl_pvsequp_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvseq_vl : GCCBuiltin<"__builtin_ve_vl_pvseq_vl">, Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvseq_vvl : GCCBuiltin<"__builtin_ve_vl_pvse
[llvm-branch-commits] [clang] 7d30df7 - [VE] Add standard include path and library path for C++
Author: Kazushi (Jam) Marukawa
Date: 2020-12-03T22:22:56+09:00
New Revision: 7d30df7b59973a42a93c86cb501bd3d0fbb07404
URL:
https://github.com/llvm/llvm-project/commit/7d30df7b59973a42a93c86cb501bd3d0fbb07404
DIFF:
https://github.com/llvm/llvm-project/commit/7d30df7b59973a42a93c86cb501bd3d0fbb07404.diff
LOG: [VE] Add standard include path and library path for C++
We have a plan to add libcxx and libcxxabi for VE. In order to do so,
we need to compile cxx source code with bootstarapped header files.
This patch adds such expected path to make clang++ work, at least
not crash at the startup. Add regression test for that, also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92386
Added:
clang/test/Driver/ve-toolchain.cpp
Modified:
clang/lib/Driver/ToolChains/VEToolchain.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/VEToolchain.cpp
b/clang/lib/Driver/ToolChains/VEToolchain.cpp
index 6ea405c0269c..e28f340f9aad 100644
--- a/clang/lib/Driver/ToolChains/VEToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/VEToolchain.cpp
@@ -102,14 +102,37 @@ void VEToolChain::addClangTargetOptions(const ArgList
&DriverArgs,
void VEToolChain::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
ArgStringList &CC1Args) const {
- // TODO upstream VE libc++ patches
- llvm_unreachable("The VE target has no C++ stdlib for Clang yet");
+ if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) ||
+ DriverArgs.hasArg(options::OPT_nostdlibinc) ||
+ DriverArgs.hasArg(options::OPT_nostdincxx))
+return;
+ if (const char *cl_include_dir = getenv("NCC_CPLUS_INCLUDE_PATH")) {
+SmallVector Dirs;
+const char EnvPathSeparatorStr[] = {llvm::sys::EnvPathSeparator, '\0'};
+StringRef(cl_include_dir).split(Dirs, StringRef(EnvPathSeparatorStr));
+ArrayRef DirVec(Dirs);
+addSystemIncludes(DriverArgs, CC1Args, DirVec);
+ } else {
+SmallString<128> P(getDriver().ResourceDir);
+llvm::sys::path::append(P, "include/c++/v1");
+addSystemInclude(DriverArgs, CC1Args, P);
+ }
}
void VEToolChain::AddCXXStdlibLibArgs(const ArgList &Args,
ArgStringList &CmdArgs) const {
- // TODO upstream VE libc++ patches
- llvm_unreachable("The VE target has no C++ stdlib for Clang yet");
+ assert((GetCXXStdlibType(Args) == ToolChain::CST_Libcxx) &&
+ "Only -lc++ (aka libxx) is supported in this toolchain.");
+
+ tools::addArchSpecificRPath(*this, Args, CmdArgs);
+
+ CmdArgs.push_back("-lc++");
+ CmdArgs.push_back("-lc++abi");
+ CmdArgs.push_back("-lunwind");
+ // libc++ requires -lpthread under glibc environment
+ CmdArgs.push_back("-lpthread");
+ // libunwind requires -ldl under glibc environment
+ CmdArgs.push_back("-ldl");
}
llvm::ExceptionHandling
diff --git a/clang/test/Driver/ve-toolchain.cpp
b/clang/test/Driver/ve-toolchain.cpp
new file mode 100644
index ..e056c04456ae
--- /dev/null
+++ b/clang/test/Driver/ve-toolchain.cpp
@@ -0,0 +1,132 @@
+/// Check the behavior of toolchain for NEC Aurora VE
+/// REQUIRES: ve-registered-target
+
+///-
+/// Checking dwarf-version
+
+// RUN: %clangxx -### -g -target ve %s 2>&1 | FileCheck
-check-prefix=DWARF_VER %s
+// DWARF_VER: "-dwarf-version=4"
+
+///-
+/// Checking dynamic-linker
+
+// RUN: %clangxx -### -target ve %s 2>&1 | FileCheck -check-prefix=DYNLINKER %s
+// DYNLINKER: nld{{.*}} "-dynamic-linker" "/opt/nec/ve/lib/ld-linux-ve.so.1"
+
+///-
+/// Checking VE specific option
+
+// RUN: %clangxx -### -target ve %s 2>&1 | FileCheck -check-prefix=VENLDOPT %s
+// VENLDOPT: nld{{.*}} "-z" "max-page-size=0x400"
+
+///-
+/// Checking include-path
+
+// RUN: %clangxx -### -target ve %s 2>&1 | FileCheck -check-prefix=DEFINC %s
+// DEFINC: clang{{.*}} "-cc1"
+// DEFINC: "-nostdsysteminc"
+// DEFINC: "-internal-isystem" "{{.*}}/lib/clang/{{[0-9.]*}}/include/c++/v1"
+// DEFINC: "-internal-isystem" "{{.*}}/lib/clang/{{[0-9.]*}}/include"
+// DEFINC: "-internal-isystem" "/opt/nec/ve/include"
+
+// RUN: %clangxx -### -target ve %s -nostdlibinc 2>&1 | \
+// RUN:FileCheck -check-prefix=NOSTDLIBINC %s
+// NOSTDLIBINC: clang{{.*}} "-cc1"
+// NOSTDLIBINC-NOT: "-internal-isystem"
"{{.*}}/lib/clang/{{[0-9.]*}}/include/c++/v1"
+// NOSTDLIBINC: "-internal-isystem" "{{.*}}/lib/clang/{{[0-9.]*}}/include"
+// NOSTDLIBINC-NOT: "-internal-isystem" "/opt/nec/ve/include"
+
+// RUN: %clangxx -### -target ve %s -nobuiltininc 2>&1 | \
+// RUN:FileCheck -check-prefix=NOBUILTININC %s
+// NOBUILTININC: clang{{.*}} "-cc1"
+// NOBUILTI
[llvm-branch-commits] [llvm] 1365718 - [VE] Add vsll, vsrl, vsla, vsra, and vsfa intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-03T23:19:58+09:00 New Revision: 1365718778b4ce05587afa22835282c5d3f835b7 URL: https://github.com/llvm/llvm-project/commit/1365718778b4ce05587afa22835282c5d3f835b7 DIFF: https://github.com/llvm/llvm-project/commit/1365718778b4ce05587afa22835282c5d3f835b7.diff LOG: [VE] Add vsll, vsrl, vsla, vsra, and vsfa intrinsic instructions Add vsll, vsrl, vsla, vsra, and vsfa intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92550 Added: llvm/test/CodeGen/VE/VELIntrinsics/vsfa.ll llvm/test/CodeGen/VE/VELIntrinsics/vsla.ll llvm/test/CodeGen/VE/VELIntrinsics/vsll.ll llvm/test/CodeGen/VE/VELIntrinsics/vsra.ll llvm/test/CodeGen/VE/VELIntrinsics/vsrl.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index 116cdc6fcc6a..e1f87122237a 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -415,3 +415,78 @@ let TargetPrefix = "ve" in def int_ve_vl_pvsequp_vl : GCCBuiltin<"__builtin_ve_v let TargetPrefix = "ve" in def int_ve_vl_pvsequp_vvl : GCCBuiltin<"__builtin_ve_vl_pvsequp_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvseq_vl : GCCBuiltin<"__builtin_ve_vl_pvseq_vl">, Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvseq_vvl : GCCBuiltin<"__builtin_ve_vl_pvseq_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsll_vvvl : GCCBuiltin<"__builtin_ve_vl_vsll_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsll_l : GCCBuiltin<"__builtin_ve_vl_vsll_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsll_vvsl : GCCBuiltin<"__builtin_ve_vl_vsll_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsll_vvsvl : GCCBuiltin<"__builtin_ve_vl_vsll_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsll_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vsll_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsll_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vsll_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsll_vvvl : GCCBuiltin<"__builtin_ve_vl_pvsll_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsll_l : GCCBuiltin<"__builtin_ve_vl_pvsll_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsll_vvsl : GCCBuiltin<"__builtin_ve_vl_pvsll_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsll_vvsvl : GCCBuiltin<"__builtin_ve_vl_pvsll_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsll_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pvsll_vvvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvsll_vvsMvl : GCCBuiltin<"__builtin_ve_vl_pvsll_vvsMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrl_vvvl : GCCBuiltin<"__builtin_ve_vl_vsrl_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrl_l : GCCBuiltin<"__builtin_ve_vl_vsrl_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrl_vvsl : GCCBuiltin<"__builtin_ve_vl_vsrl_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrl_vvsvl : GCCBuiltin<"__builtin_ve_vl_vsrl_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrl_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vsrl_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrl_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vsrl_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>
[llvm-branch-commits] [llvm] e936d1e - [VE] Add vfadd, vfsub, vfmul, and vfdiv intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-04T21:58:51+09:00 New Revision: e936d1e11345db5d2de3d1a73bd705d8fcf99fbc URL: https://github.com/llvm/llvm-project/commit/e936d1e11345db5d2de3d1a73bd705d8fcf99fbc DIFF: https://github.com/llvm/llvm-project/commit/e936d1e11345db5d2de3d1a73bd705d8fcf99fbc.diff LOG: [VE] Add vfadd, vfsub, vfmul, and vfdiv intrinsic instructions Add vfadd, vfsub, vfmul, and vfdiv intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92649 Added: llvm/test/CodeGen/VE/VELIntrinsics/vfadd.ll llvm/test/CodeGen/VE/VELIntrinsics/vfdiv.ll llvm/test/CodeGen/VE/VELIntrinsics/vfmul.ll llvm/test/CodeGen/VE/VELIntrinsics/vfsub.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index e1f87122237a..711fc8cddfb3 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -490,3 +490,69 @@ let TargetPrefix = "ve" in def int_ve_vl_vsral_vvsmvl : GCCBuiltin<"__builtin_ve let TargetPrefix = "ve" in def int_ve_vl_vsfa_vvssl : GCCBuiltin<"__builtin_ve_vl_vsfa_vvssl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsfa_vvssvl : GCCBuiltin<"__builtin_ve_vl_vsfa_vvssvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsfa_vvssmvl : GCCBuiltin<"__builtin_ve_vl_vsfa_vvssmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfaddd_vvvl : GCCBuiltin<"__builtin_ve_vl_vfaddd_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfaddd_l : GCCBuiltin<"__builtin_ve_vl_vfaddd_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfaddd_vsvl : GCCBuiltin<"__builtin_ve_vl_vfaddd_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfaddd_vsvvl : GCCBuiltin<"__builtin_ve_vl_vfaddd_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfaddd_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vfaddd_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfaddd_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vfaddd_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfadds_vvvl : GCCBuiltin<"__builtin_ve_vl_vfadds_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfadds_l : GCCBuiltin<"__builtin_ve_vl_vfadds_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfadds_vsvl : GCCBuiltin<"__builtin_ve_vl_vfadds_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfadds_vsvvl : GCCBuiltin<"__builtin_ve_vl_vfadds_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfadds_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vfadds_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfadds_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vfadds_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfadd_vvvl : GCCBuiltin<"__builtin_ve_vl_pvfadd_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfadd_l : GCCBuiltin<"__builtin_ve_vl_pvfadd_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfadd_vsvl : GCCBuiltin<"__builtin_ve_vl_pvfadd_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfadd_vsvvl : GCCBuiltin<"__builtin_ve_vl_pvfadd_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfadd_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pvfadd_vvvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfadd_vsvMvl : GCCBuilt
[llvm-branch-commits] [llvm] 23034a4 - [VE] Add vfsqrt, vfcmp, vfmax, and vfmin intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-05T07:52:14+09:00 New Revision: 23034a4a63e18672be33405f7951d60a0658e67b URL: https://github.com/llvm/llvm-project/commit/23034a4a63e18672be33405f7951d60a0658e67b DIFF: https://github.com/llvm/llvm-project/commit/23034a4a63e18672be33405f7951d60a0658e67b.diff LOG: [VE] Add vfsqrt, vfcmp, vfmax, and vfmin intrinsic instructions Add vfsqrt, vfcmp, vfmax, and vfmin intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92651 Added: llvm/test/CodeGen/VE/VELIntrinsics/vfcmp.ll llvm/test/CodeGen/VE/VELIntrinsics/vfmax.ll llvm/test/CodeGen/VE/VELIntrinsics/vfmin.ll llvm/test/CodeGen/VE/VELIntrinsics/vfsqrt.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index 711fc8cddfb3..aaf8ae6e23b5 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -556,3 +556,61 @@ let TargetPrefix = "ve" in def int_ve_vl_vfdivs_vsvl : GCCBuiltin<"__builtin_ve_ let TargetPrefix = "ve" in def int_ve_vl_vfdivs_vsvvl : GCCBuiltin<"__builtin_ve_vl_vfdivs_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vfdivs_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vfdivs_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vfdivs_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vfdivs_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsqrtd_vvl : GCCBuiltin<"__builtin_ve_vl_vfsqrtd_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsqrtd_vvvl : GCCBuiltin<"__builtin_ve_vl_vfsqrtd_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsqrts_vvl : GCCBuiltin<"__builtin_ve_vl_vfsqrts_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsqrts_vvvl : GCCBuiltin<"__builtin_ve_vl_vfsqrts_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmpd_vvvl : GCCBuiltin<"__builtin_ve_vl_vfcmpd_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmpd_l : GCCBuiltin<"__builtin_ve_vl_vfcmpd_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmpd_vsvl : GCCBuiltin<"__builtin_ve_vl_vfcmpd_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmpd_vsvvl : GCCBuiltin<"__builtin_ve_vl_vfcmpd_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmpd_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vfcmpd_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmpd_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vfcmpd_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmps_vvvl : GCCBuiltin<"__builtin_ve_vl_vfcmps_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmps_l : GCCBuiltin<"__builtin_ve_vl_vfcmps_l">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmps_vsvl : GCCBuiltin<"__builtin_ve_vl_vfcmps_vsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmps_vsvvl : GCCBuiltin<"__builtin_ve_vl_vfcmps_vsvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmps_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vfcmps_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfcmps_vsvmvl : GCCBuiltin<"__builtin_ve_vl_vfcmps_vsvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfcmp_vvvl : GCCBuiltin<"__builtin_ve_vl_pvfcmp_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvfcmp_l : GCCBuiltin<"__builtin_ve_vl_pvfcmp_l">, Intrinsic<[LLVMType], [LLVM
[llvm-branch-commits] [compiler-rt] 414d3dc - [VE][compiler-rt] Support VE in clear_cache.c
Author: Kazushi (Jam) Marukawa
Date: 2020-12-07T17:38:23+09:00
New Revision: 414d3dc62c706f41226b0d552210c79f5080df43
URL:
https://github.com/llvm/llvm-project/commit/414d3dc62c706f41226b0d552210c79f5080df43
DIFF:
https://github.com/llvm/llvm-project/commit/414d3dc62c706f41226b0d552210c79f5080df43.diff
LOG: [VE][compiler-rt] Support VE in clear_cache.c
Support SX Aurora VE by __clear_cache() function. This modification
allows VE to run written data, e.g. clear_cache_test.c under compiler-rt
test. We still have code alignment problem in enable_execute_stack_test.c,
though.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92703
Added:
Modified:
compiler-rt/lib/builtins/clear_cache.c
Removed:
diff --git a/compiler-rt/lib/builtins/clear_cache.c
b/compiler-rt/lib/builtins/clear_cache.c
index e9e291467bd9..5a443ddd4b03 100644
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -167,6 +167,8 @@ void __clear_cache(void *start, void *end) {
#if __APPLE__
// On Darwin, sys_icache_invalidate() provides this functionality
sys_icache_invalidate(start, end - start);
+#elif defined(__ve__)
+ __asm__ volatile("fencec 2");
#else
compilerrt_abort();
#endif
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[llvm-branch-commits] [llvm] 03898b7 - [VE] Add vrcp, vrsqrt, vcvt, vmrg, and vshf intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-07T20:30:12+09:00 New Revision: 03898b79fb76e0a4dabf9f35d7dc51b4c497adb0 URL: https://github.com/llvm/llvm-project/commit/03898b79fb76e0a4dabf9f35d7dc51b4c497adb0 DIFF: https://github.com/llvm/llvm-project/commit/03898b79fb76e0a4dabf9f35d7dc51b4c497adb0.diff LOG: [VE] Add vrcp, vrsqrt, vcvt, vmrg, and vshf intrinsic instructions Add vrcp, vrsqrt, vcvt, vmrg, and vshf intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92750 Added: llvm/test/CodeGen/VE/VELIntrinsics/vcvt.ll llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll llvm/test/CodeGen/VE/VELIntrinsics/vrcp.ll llvm/test/CodeGen/VE/VELIntrinsics/vrsqrt.ll llvm/test/CodeGen/VE/VELIntrinsics/vshf.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index f8f422f4ef2b..f62d7cdafdd0 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -722,3 +722,79 @@ let TargetPrefix = "ve" in def int_ve_vl_pvfnmsb_vvsvvl : GCCBuiltin<"__builtin_ let TargetPrefix = "ve" in def int_ve_vl_pvfnmsb_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfnmsb_Mvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvfnmsb_vsvvMvl : GCCBuiltin<"__builtin_ve_vl_pvfnmsb_vsvvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvfnmsb_vvsvMvl : GCCBuiltin<"__builtin_ve_vl_pvfnmsb_vvsvMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrcpd_vvl : GCCBuiltin<"__builtin_ve_vl_vrcpd_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrcpd_vvvl : GCCBuiltin<"__builtin_ve_vl_vrcpd_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrcps_vvl : GCCBuiltin<"__builtin_ve_vl_vrcps_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrcps_vvvl : GCCBuiltin<"__builtin_ve_vl_vrcps_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvrcp_vvl : GCCBuiltin<"__builtin_ve_vl_pvrcp_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvrcp_vvvl : GCCBuiltin<"__builtin_ve_vl_pvrcp_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrtd_vvl : GCCBuiltin<"__builtin_ve_vl_vrsqrtd_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrtd_vvvl : GCCBuiltin<"__builtin_ve_vl_vrsqrtd_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrts_vvl : GCCBuiltin<"__builtin_ve_vl_vrsqrts_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrts_vvvl : GCCBuiltin<"__builtin_ve_vl_vrsqrts_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvrsqrt_vvl : GCCBuiltin<"__builtin_ve_vl_pvrsqrt_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvrsqrt_vvvl : GCCBuiltin<"__builtin_ve_vl_pvrsqrt_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrtdnex_vvl : GCCBuiltin<"__builtin_ve_vl_vrsqrtdnex_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrtdnex_vvvl : GCCBuiltin<"__builtin_ve_vl_vrsqrtdnex_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrtsnex_vvl : GCCBuiltin<"__builtin_ve_vl_vrsqrtsnex_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrsqrtsnex_vvvl : GCCBuiltin<"__builtin_ve_vl_vrsqrtsnex_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvrsqrtnex_vvl : GCCBuiltin<"__builtin_ve_vl_pvrsqrtnex_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_pvrsqrtnex_vvvl : GCCBuiltin<"__builtin_ve_vl_pvrsqrtnex_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vcvtwdsx_vv
[llvm-branch-commits] [llvm] 9d4501e - [VE] Add vcp and vex intrinsic instructions
Author: Kazushi (Jam) Marukawa
Date: 2020-12-07T22:56:55+09:00
New Revision: 9d4501e2b42a2f413000661155a637e495597026
URL:
https://github.com/llvm/llvm-project/commit/9d4501e2b42a2f413000661155a637e495597026
DIFF:
https://github.com/llvm/llvm-project/commit/9d4501e2b42a2f413000661155a637e495597026.diff
LOG: [VE] Add vcp and vex intrinsic instructions
Add vcp and vex intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92752
Added:
llvm/test/CodeGen/VE/VELIntrinsics/vcp.ll
llvm/test/CodeGen/VE/VELIntrinsics/vex.ll
Modified:
llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
index f62d7cdafdd0..c7ddbbc4ffbd 100644
--- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
+++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
@@ -798,3 +798,5 @@ let TargetPrefix = "ve" in def int_ve_vl_vmrgw_vsvMl :
GCCBuiltin<"__builtin_ve_
let TargetPrefix = "ve" in def int_ve_vl_vmrgw_vsvMvl :
GCCBuiltin<"__builtin_ve_vl_vmrgw_vsvMvl">, Intrinsic<[LLVMType],
[LLVMType, LLVMType, LLVMType, LLVMType,
LLVMType], [IntrNoMem]>;
let TargetPrefix = "ve" in def int_ve_vl_vshf_vvvsl :
GCCBuiltin<"__builtin_ve_vl_vshf_vvvsl">, Intrinsic<[LLVMType],
[LLVMType, LLVMType, LLVMType, LLVMType],
[IntrNoMem]>;
let TargetPrefix = "ve" in def int_ve_vl_vshf_vvvsvl :
GCCBuiltin<"__builtin_ve_vl_vshf_vvvsvl">, Intrinsic<[LLVMType],
[LLVMType, LLVMType, LLVMType, LLVMType,
LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vcp_vvmvl :
GCCBuiltin<"__builtin_ve_vl_vcp_vvmvl">, Intrinsic<[LLVMType],
[LLVMType, LLVMType, LLVMType, LLVMType],
[IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vex_vvmvl :
GCCBuiltin<"__builtin_ve_vl_vex_vvmvl">, Intrinsic<[LLVMType],
[LLVMType, LLVMType, LLVMType, LLVMType],
[IntrNoMem]>;
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
index 651ea2fb9015..2854ecd69872 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
@@ -1021,3 +1021,5 @@ def : Pat<(int_ve_vl_vshf_vvvsl v256f64:$vy, v256f64:$vz,
i64:$sy, i32:$vl), (VS
def : Pat<(int_ve_vl_vshf_vvvsvl v256f64:$vy, v256f64:$vz, i64:$sy,
v256f64:$pt, i32:$vl), (VSHFvvrl_v v256f64:$vy, v256f64:$vz, i64:$sy, i32:$vl,
v256f64:$pt)>;
def : Pat<(int_ve_vl_vshf_vvvsl v256f64:$vy, v256f64:$vz, uimm6:$N, i32:$vl),
(VSHFvvil v256f64:$vy, v256f64:$vz, (ULO7 $N), i32:$vl)>;
def : Pat<(int_ve_vl_vshf_vvvsvl v256f64:$vy, v256f64:$vz, uimm6:$N,
v256f64:$pt, i32:$vl), (VSHFvvil_v v256f64:$vy, v256f64:$vz, (ULO7 $N),
i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_vcp_vvmvl v256f64:$vz, v256i1:$vm, v256f64:$pt, i32:$vl),
(VCPvml_v v256f64:$vz, v256i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_vex_vvmvl v256f64:$vz, v256i1:$vm, v256f64:$pt, i32:$vl),
(VEXvml_v v256f64:$vz, v256i1:$vm, i32:$vl, v256f64:$pt)>;
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vcp.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/vcp.ll
new file mode 100644
index ..608a6bd2d8f4
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vcp.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test vector compress intrinsic instructions
+;;;
+;;; Note:
+;;; We test VCP*vml_v instruction.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vcp_vvmvl(<256 x double> %0, <256 x i1> %1, <256
x double> %2) {
+; CHECK-LABEL: vcp_vvmvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT:lea %s0, 128
+; CHECK-NEXT:lvl %s0
+; CHECK-NEXT:vcp %v1, %v0, %vm1
+; CHECK-NEXT:lea %s16, 256
+; CHECK-NEXT:lvl %s16
+; CHECK-NEXT:vor %v0, (0)1, %v1
+; CHECK-NEXT:b.l.t (, %s10)
+ %4 = tail call fast <256 x double> @llvm.ve.vl.vcp.vvmvl(<256 x double> %0,
<256 x i1> %1, <256 x double> %2, i32 128)
+ ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vcp.vvmvl(<256 x double>, <256 x i1>, <256
x double>, i32)
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vex.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/vex.ll
new file mode 100644
index ..c33f941d48ae
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vex.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test vector expand intrinsic instructions
+;;;
+;;; Note:
+;;; We test VEX*vml_v instruction.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vex_vvmvl(<256 x double> %0, <256 x i1> %1, <256
x double> %2) {
+; CHECK-LABEL: vex_vvmvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT:lea %s0, 128
+; CHECK-NEXT:lvl %s0
+; CHECK-NEXT:vex %v1, %v0, %vm1
+; CHECK-NEXT:lea %s16, 256
+; CHECK-NEXT:lvl %s16
+; CHE
[llvm-branch-commits] [llvm] 95ea50e - [VE] Correct LVLGen (LVL instruction insert pass)
Author: Kazushi (Jam) Marukawa
Date: 2020-12-09T06:33:53+09:00
New Revision: 95ea50e4adf76b75fcc0ad29cacd10642db091a6
URL:
https://github.com/llvm/llvm-project/commit/95ea50e4adf76b75fcc0ad29cacd10642db091a6
DIFF:
https://github.com/llvm/llvm-project/commit/95ea50e4adf76b75fcc0ad29cacd10642db091a6.diff
LOG: [VE] Correct LVLGen (LVL instruction insert pass)
SX Aurora VE uses an intermediate representation similar to VP as its MIR.
VE itself uses invidiual VL register as its own vector length register at
the hardware level. So, LLVM needs to insert load VL (LVL) instruction just
before vector instructions if the value of VL is changed. This LVLGen pass
generates LVL instructions for such purpose. Previously, a bug is pointed
out in D91416. This patch correct this bug and add a regression test.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D92716
Added:
Modified:
llvm/lib/Target/VE/LVLGen.cpp
llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
Removed:
diff --git a/llvm/lib/Target/VE/LVLGen.cpp b/llvm/lib/Target/VE/LVLGen.cpp
index 08b350a581dc..c4588926af9e 100644
--- a/llvm/lib/Target/VE/LVLGen.cpp
+++ b/llvm/lib/Target/VE/LVLGen.cpp
@@ -68,6 +68,12 @@ bool LVLGen::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end();) {
MachineBasicBlock::iterator MI = I;
+// Check whether MI uses a vector length operand. If so, we prepare for VL
+// register. We would like to reuse VL register as much as possible. We
+// also would like to keep the number of LEA instructions as fewer as
+// possible. Therefore, we use a regular scalar register to hold immediate
+// values to load VL register. And try to reuse identical scalar registers
+// to avoid new LVLr instructions as much as possible.
unsigned Reg = getVL(*MI);
if (Reg != VE::NoRegister) {
LLVM_DEBUG(dbgs() << "Vector instruction found: ");
@@ -78,6 +84,8 @@ bool LVLGen::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
<< ". ");
if (!HasRegForVL || RegForVL != Reg) {
+// Use VL, but a
diff erent value in a
diff erent scalar register.
+// So, generate new LVL instruction just before the current
instruction.
LLVM_DEBUG(dbgs() << "Generate a LVL instruction to load "
<< RegName(Reg) << ".\n");
BuildMI(MBB, I, MI->getDebugLoc(), TII->get(VE::LVLr)).addReg(Reg);
@@ -87,18 +95,15 @@ bool LVLGen::runOnMachineBasicBlock(MachineBasicBlock &MBB)
{
} else {
LLVM_DEBUG(dbgs() << "Reuse current VL.\n");
}
-} else if (HasRegForVL) {
- // Old VL is overwritten, so disable HasRegForVL.
- if (MI->findRegisterDefOperandIdx(RegForVL, false, false, TRI) != -1) {
-LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
-LLVM_DEBUG(MI->dump());
-HasRegForVL = false;
- }
}
+// Check the update of a given scalar register holding an immediate value
+// for VL register. Also, a call doesn't preserve VL register.
if (HasRegForVL) {
- // The latest VL is killed, so disable HasRegForVL.
- if (MI->killsRegister(RegForVL, TRI)) {
-LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
+ if (MI->definesRegister(RegForVL, TRI) ||
+ MI->modifiesRegister(RegForVL, TRI) ||
+ MI->killsRegister(RegForVL, TRI) || MI->isCall()) {
+// The latest VL is needed to be updated, so disable HasRegForVL.
+LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is needed to be updated:
");
LLVM_DEBUG(MI->dump());
HasRegForVL = false;
}
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
b/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
index ac889e7b60ca..c4db62442451 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
@@ -42,7 +42,6 @@ define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8*
%Q) {
; Check that no redundant 'lvl' is inserted when vector length does not change
; in a basic block.
-
; Function Attrs: nounwind
define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
; CHECK-LABEL: stable_vl:
@@ -64,3 +63,43 @@ define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32
%evl)
ret void
}
+
+;;; Check the case we have a call in the middle of vector instructions.
+
+; Function Attrs: nounwind
+define void @call_invl(i32 %evl, i8* %P, i8* %Q) {
+; CHECK-LABEL: call_invl:
+; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:st %s18, 288(, %s11) # 8-byte Folded Spill
+; CHECK-NEXT:st %s19, 296(, %s11) # 8-byte Folded Spill
+; CHECK-NEXT:st %s20, 304(, %s11) # 8-byte Folded Spill
+; CHECK-NEXT:or %s18, 0, %s1
+; CHECK-NEXT:and %s20, %s0, (32)0
+
[llvm-branch-commits] [llvm] 1a2147f - [VE] Add vsum and vfsum intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-10T01:11:53+09:00 New Revision: 1a2147feadb80f3b0d4c4cb6892498b0bae549fe URL: https://github.com/llvm/llvm-project/commit/1a2147feadb80f3b0d4c4cb6892498b0bae549fe DIFF: https://github.com/llvm/llvm-project/commit/1a2147feadb80f3b0d4c4cb6892498b0bae549fe.diff LOG: [VE] Add vsum and vfsum intrinsic instructions Add vsum and vfsum intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92938 Added: llvm/test/CodeGen/VE/VELIntrinsics/vfsum.ll llvm/test/CodeGen/VE/VELIntrinsics/vsum.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index 5e86a1b9a372..d2d965085526 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -1084,3 +1084,13 @@ let TargetPrefix = "ve" in def int_ve_vl_pvfmksgenan_Mvl : GCCBuiltin<"__builtin let TargetPrefix = "ve" in def int_ve_vl_pvfmksgenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksgenan_MvMl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvfmkslenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslenan_Mvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvfmkslenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkslenan_MvMl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsumwsx_vvl : GCCBuiltin<"__builtin_ve_vl_vsumwsx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsumwsx_vvml : GCCBuiltin<"__builtin_ve_vl_vsumwsx_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsumwzx_vvl : GCCBuiltin<"__builtin_ve_vl_vsumwzx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsumwzx_vvml : GCCBuiltin<"__builtin_ve_vl_vsumwzx_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsuml_vvl : GCCBuiltin<"__builtin_ve_vl_vsuml_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsuml_vvml : GCCBuiltin<"__builtin_ve_vl_vsuml_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsumd_vvl : GCCBuiltin<"__builtin_ve_vl_vfsumd_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsumd_vvml : GCCBuiltin<"__builtin_ve_vl_vfsumd_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsums_vvl : GCCBuiltin<"__builtin_ve_vl_vfsums_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vfsums_vvml : GCCBuiltin<"__builtin_ve_vl_vfsums_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td index 8c1518edcfed..623eadce3d0a 100644 --- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td +++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td @@ -1307,3 +1307,13 @@ def : Pat<(int_ve_vl_pvfmksgenan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_GENAN, def : Pat<(int_ve_vl_pvfmksgenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_GENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>; def : Pat<(int_ve_vl_pvfmkslenan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_LENAN, v256f64:$vz, i32:$vl)>; def : Pat<(int_ve_vl_pvfmkslenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_LENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>; +def : Pat<(int_ve_vl_vsumwsx_vvl v256f64:$vy, i32:$vl), (VSUMWSXvl v256f64:$vy, i32:$vl)>; +def : Pat<(int_ve_vl_vsumwsx_vvml v256f64:$vy, v256i1:$vm, i32:$vl), (VSUMWSXvml v256f64:$vy, v256i1:$vm, i32:$vl)>; +def : Pat<(int_ve_vl_vsumwzx_vvl v256f64:$vy, i32:$vl), (VSUMWZXvl v256f64:$vy, i32:$vl)>; +def : Pat<(int_ve_vl_vsumwzx_vvml v256f64:$vy, v256i1:$vm, i32:$vl), (VSUMWZXvml v256f64:$vy, v256i1:$vm, i32:$vl)>; +def : Pat<(int_ve_vl_vsuml_vvl v256f64:$vy, i32:$vl), (VSUMLvl v256f64:$vy, i32:$vl)>; +def : Pat<(int_ve_vl_vsuml_vvml v256f64:$vy, v256i1:$vm, i32:$vl), (VSUMLvml v256f64:$vy, v256i1:$vm, i32:$vl)>; +def : Pat<(int_ve_vl_vfsumd_vvl v256f64:$vy, i32:$vl), (VFSUMDvl v256f64:$vy, i32:$vl)>; +def : Pat<(int_ve_vl_vfsumd_vvml v256f64:$vy, v256i1:$vm, i32:$vl), (VFSUMDvml v256f64:$vy, v256i1:$vm, i32:$vl)>; +def : Pat<(int_ve_vl_vfsums_vvl v256f64:$vy, i32:$vl), (VFSUMSvl v256f64:$vy, i32:$vl)>; +def : Pat<(int_ve_vl_vfsums_
[llvm-branch-commits] [llvm] e954ba2 - [VE][NFC] Disable VP tests
Author: Kazushi (Jam) Marukawa
Date: 2020-12-10T15:13:05+09:00
New Revision: e954ba28bcac9dc8d0ffc57d56ffa06ea2cd2f69
URL:
https://github.com/llvm/llvm-project/commit/e954ba28bcac9dc8d0ffc57d56ffa06ea2cd2f69
DIFF:
https://github.com/llvm/llvm-project/commit/e954ba28bcac9dc8d0ffc57d56ffa06ea2cd2f69.diff
LOG: [VE][NFC] Disable VP tests
VP tests recently added don't work on Release mode. They work on
Debug mode, so I disable them on Release mode to make tests work.
Added:
Modified:
llvm/test/CodeGen/VE/Vector/vp_add.ll
llvm/test/CodeGen/VE/Vector/vp_and.ll
llvm/test/CodeGen/VE/Vector/vp_ashr.ll
llvm/test/CodeGen/VE/Vector/vp_lshr.ll
llvm/test/CodeGen/VE/Vector/vp_mul.ll
llvm/test/CodeGen/VE/Vector/vp_or.ll
llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
llvm/test/CodeGen/VE/Vector/vp_shl.ll
llvm/test/CodeGen/VE/Vector/vp_srem.ll
llvm/test/CodeGen/VE/Vector/vp_sub.ll
llvm/test/CodeGen/VE/Vector/vp_udiv.ll
llvm/test/CodeGen/VE/Vector/vp_urem.ll
llvm/test/CodeGen/VE/Vector/vp_xor.ll
Removed:
diff --git a/llvm/test/CodeGen/VE/Vector/vp_add.ll
b/llvm/test/CodeGen/VE/Vector/vp_add.ll
index b69a1a1bd59f..52808a56fbb3 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_add.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_add [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_and.ll
b/llvm/test/CodeGen/VE/Vector/vp_and.ll
index 7507a1a34092..5f7333ffbba2 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_and.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_and [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
b/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
index c4c1def0b56b..cdce387d0d6d 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_ashr [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
b/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
index 79e38e0c128e..e42a3b62c891 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_lshr [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_mul.ll
b/llvm/test/CodeGen/VE/Vector/vp_mul.ll
index 454000e10d0e..c7f8c00b64f0 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_mul.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_mul.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_mul [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_or.ll
b/llvm/test/CodeGen/VE/Vector/vp_or.ll
index 71cef7d1b8c1..684ac1e5b3d8 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_or.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_or [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
b/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
index 4fa7ae516d88..2f99c09a1780 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_sdiv [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_shl.ll
b/llvm/test/CodeGen/VE/Vector/vp_shl.ll
index 84675b640ded..2cb526bd8456 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_shl.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_shl.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_shl [[A:t[0-9]+]], [[B:t[0-9]+]],
[[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
diff --git a/llvm/test/CodeGen/VE/Vector/vp_srem.ll
b/llvm/test/CodeGen/VE/Vector/vp_srem.ll
index 952752498007..b52d5edfe759 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_srem.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_srem.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: n
[llvm-branch-commits] [llvm] 4b1e329 - [VE] Add vector reduce intrinsic instructions
Author: Kazushi (Jam) Marukawa Date: 2020-12-10T22:21:17+09:00 New Revision: 4b1e32925528b546de445ca81999f270acd54618 URL: https://github.com/llvm/llvm-project/commit/4b1e32925528b546de445ca81999f270acd54618 DIFF: https://github.com/llvm/llvm-project/commit/4b1e32925528b546de445ca81999f270acd54618.diff LOG: [VE] Add vector reduce intrinsic instructions Add vrmax, vrmin, vfrmax, vfrmin, vrand, vror, and vrxor intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92941 Added: llvm/test/CodeGen/VE/VELIntrinsics/vfrmax.ll llvm/test/CodeGen/VE/VELIntrinsics/vfrmin.ll llvm/test/CodeGen/VE/VELIntrinsics/vrand.ll llvm/test/CodeGen/VE/VELIntrinsics/vrmax.ll llvm/test/CodeGen/VE/VELIntrinsics/vrmin.ll llvm/test/CodeGen/VE/VELIntrinsics/vror.ll llvm/test/CodeGen/VE/VELIntrinsics/vrxor.ll Modified: llvm/include/llvm/IR/IntrinsicsVEVL.gen.td llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td Removed: diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index d2d965085526..1db7003f0ffd 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -1094,3 +1094,49 @@ let TargetPrefix = "ve" in def int_ve_vl_vfsumd_vvl : GCCBuiltin<"__builtin_ve_v let TargetPrefix = "ve" in def int_ve_vl_vfsumd_vvml : GCCBuiltin<"__builtin_ve_vl_vfsumd_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vfsums_vvl : GCCBuiltin<"__builtin_ve_vl_vfsums_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vfsums_vvml : GCCBuiltin<"__builtin_ve_vl_vfsums_vvml">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswfstsx_vvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswfstsx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswfstsx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswfstsx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswlstsx_vvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswlstsx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswlstsx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswlstsx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswfstzx_vvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswfstzx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswfstzx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswfstzx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswlstzx_vvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswlstzx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxswlstzx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrmaxswlstzx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswfstsx_vvl : GCCBuiltin<"__builtin_ve_vl_vrminswfstsx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswfstsx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrminswfstsx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswlstsx_vvl : GCCBuiltin<"__builtin_ve_vl_vrminswlstsx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswlstsx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrminswlstsx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswfstzx_vvl : GCCBuiltin<"__builtin_ve_vl_vrminswfstzx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswfstzx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrminswfstzx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswlstzx_vvl : GCCBuiltin<"__builtin_ve_vl_vrminswlstzx_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrminswlstzx_vvvl : GCCBuiltin<"__builtin_ve_vl_vrminswlstzx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxslfst_vvl : GCCBuiltin<"__builtin_ve_vl_vrmaxslfst_vvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vrmaxslfst_vvvl : GCCBuiltin<"__builtin_ve_vl_vrmaxslfst_
[llvm-branch-commits] [clang] cd5855a - [VE] Remove -faddrsig and -fnoaddrsig tests
Author: Kazushi (Jam) Marukawa
Date: 2020-12-11T08:25:38+09:00
New Revision: cd5855ac3ba7a91b2a4a7c97b2723c95038dacbe
URL:
https://github.com/llvm/llvm-project/commit/cd5855ac3ba7a91b2a4a7c97b2723c95038dacbe
DIFF:
https://github.com/llvm/llvm-project/commit/cd5855ac3ba7a91b2a4a7c97b2723c95038dacbe.diff
LOG: [VE] Remove -faddrsig and -fnoaddrsig tests
Remove explicitly declared -faddrsig and -fnoaddrsig option tests
since those are already tested in addrsig.c. We test only the implicit
behavior of VE driver.
This is suggested in https://reviews.llvm.org/D92386. Thanks.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D92996
Added:
Modified:
clang/test/Driver/ve-toolchain.c
clang/test/Driver/ve-toolchain.cpp
Removed:
diff --git a/clang/test/Driver/ve-toolchain.c
b/clang/test/Driver/ve-toolchain.c
index 261b3efcc4f0..0ca3c84373f3 100644
--- a/clang/test/Driver/ve-toolchain.c
+++ b/clang/test/Driver/ve-toolchain.c
@@ -67,16 +67,6 @@
// DEFADDESIG: clang{{.*}} "-cc1"
// DEFADDESIG-NOT: "-faddrsig"
-// RUN: %clang -### -target ve %s -faddrsig 2>&1 | \
-// RUN: FileCheck -check-prefix=ADDRSIG %s
-// ADDRSIG: clang{{.*}} "-cc1"
-// ADDRSIG: "-faddrsig"
-
-// RUN: %clang -### -target ve %s -fno-addrsig 2>&1 | \
-// RUN: FileCheck -check-prefix=NOADDRSIG %s
-// NOADDRSIG: clang{{.*}} "-cc1"
-// NOADDRSIG-NOT: "-faddrsig"
-
///-
/// Checking exceptions
diff --git a/clang/test/Driver/ve-toolchain.cpp
b/clang/test/Driver/ve-toolchain.cpp
index 6243b4c3f386..36a23aa87f98 100644
--- a/clang/test/Driver/ve-toolchain.cpp
+++ b/clang/test/Driver/ve-toolchain.cpp
@@ -85,16 +85,6 @@
// DEFADDESIG: clang{{.*}} "-cc1"
// DEFADDESIG-NOT: "-faddrsig"
-// RUN: %clangxx -### -target ve %s -faddrsig 2>&1 | \
-// RUN: FileCheck -check-prefix=ADDRSIG %s
-// ADDRSIG: clang{{.*}} "-cc1"
-// ADDRSIG: "-faddrsig"
-
-// RUN: %clangxx -### -target ve %s -fno-addrsig 2>&1 | \
-// RUN: FileCheck -check-prefix=NOADDRSIG %s
-// NOADDRSIG: clang{{.*}} "-cc1"
-// NOADDRSIG-NOT: "-faddrsig"
-
///-
/// Checking exceptions
___
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[llvm-branch-commits] [clang] 05d1729 - [VE] Optimize toolchain regression test
Author: Kazushi (Jam) Marukawa
Date: 2020-12-13T20:26:05+09:00
New Revision: 05d1729232cdff323cafd469532504aa85740967
URL:
https://github.com/llvm/llvm-project/commit/05d1729232cdff323cafd469532504aa85740967
DIFF:
https://github.com/llvm/llvm-project/commit/05d1729232cdff323cafd469532504aa85740967.diff
LOG: [VE] Optimize toolchain regression test
Optimize toolchain regression test for VE by removing not a useful test
(-fuse-init-array test) and merge several tests to one test which checks
default behavior of driver. Also add sysroot to reduce conflicts.
These are suggested in https://reviews.llvm.org/D92996.
Thank you so much.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D93084
Added:
clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crt1.o
clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crti.o
clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crtn.o
clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/clang_rt.crtbegin-ve.o
clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/clang_rt.crtend-ve.o
clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/libclang_rt.builtins-ve.a
Modified:
clang/test/Driver/ve-toolchain.c
clang/test/Driver/ve-toolchain.cpp
Removed:
diff --git a/clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crt1.o
b/clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crt1.o
new file mode 100644
index ..e69de29bb2d1
diff --git a/clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crti.o
b/clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crti.o
new file mode 100644
index ..e69de29bb2d1
diff --git a/clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crtn.o
b/clang/test/Driver/Inputs/basic_ve_tree/opt/nec/ve/lib/crtn.o
new file mode 100644
index ..e69de29bb2d1
diff --git
a/clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/clang_rt.crtbegin-ve.o
b/clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/clang_rt.crtbegin-ve.o
new file mode 100644
index ..e69de29bb2d1
diff --git
a/clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/clang_rt.crtend-ve.o
b/clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/clang_rt.crtend-ve.o
new file mode 100644
index ..e69de29bb2d1
diff --git
a/clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/libclang_rt.builtins-ve.a
b/clang/test/Driver/Inputs/basic_ve_tree/resource_dir/lib/linux/libclang_rt.builtins-ve.a
new file mode 100644
index ..e69de29bb2d1
diff --git a/clang/test/Driver/ve-toolchain.c
b/clang/test/Driver/ve-toolchain.c
index 0ca3c84373f3..ac925e470770 100644
--- a/clang/test/Driver/ve-toolchain.c
+++ b/clang/test/Driver/ve-toolchain.c
@@ -7,83 +7,93 @@
// RUN: %clang -### -g -target ve %s 2>&1 | FileCheck -check-prefix=DWARF_VER
%s
// DWARF_VER: "-dwarf-version=4"
-///-
-/// Checking dynamic-linker
-
-// RUN: %clang -### -target ve %s 2>&1 | FileCheck -check-prefix=DYNLINKER %s
-// DYNLINKER: nld{{.*}} "-dynamic-linker" "/opt/nec/ve/lib/ld-linux-ve.so.1"
-
-///-
-/// Checking VE specific option
-
-// RUN: %clang -### -target ve %s 2>&1 | FileCheck -check-prefix=VENLDOPT %s
-// VENLDOPT: nld{{.*}} "-z" "max-page-size=0x400"
-
///-
/// Checking include-path
-// RUN: %clang -### -target ve %s 2>&1 | FileCheck -check-prefix=DEFINC %s
+// RUN: %clang -### -target ve --sysroot %S/Inputs/basic_ve_tree %s \
+// RUN: -resource-dir=%S/Input/basic_ve_tree/resource_dir \
+// RUN: 2>&1 | FileCheck -check-prefix=DEFINC %s
// DEFINC: clang{{.*}} "-cc1"
-// DEFINC: "-nostdsysteminc"
-// DEFINC: "-internal-isystem" "{{.*}}/lib/clang/{{[0-9.]*}}/include"
-// DEFINC: "-internal-isystem" "/opt/nec/ve/include"
-
-// RUN: %clang -### -target ve %s -nostdlibinc 2>&1 | \
-// RUN:FileCheck -check-prefix=NOSTDLIBINC %s
+// DEFINC-SAME: "-nostdsysteminc"
+// DEFINC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
+// DEFINC-SAME: "-isysroot" "[[SYSROOT:[^"]+]]"
+// DEFINC-SAME: "-internal-isystem" "[[RESOURCE_DIR]]/include"
+// DEFINC-SAME: "-internal-isystem" "[[SYSROOT]]/opt/nec/ve/include"
+
+// RUN: %clang -### -target ve --sysroot %S/Inputs/basic_ve_tree %s \
+// RUN: -resource-dir=%S/Input/basic_ve_tree/resource_dir \
+// RUN: -nostdlibinc 2>&1 | FileCheck -check-prefix=NOSTDLIBINC %s
// NOSTDLIBINC: clang{{.*}} "-cc1"
-// NOSTDLIBINC: "-internal-isystem" "{{.*}}/lib/clang/{{[0-9.]*}}/include"
-// NOSTDLIBINC-NOT: "-internal-isystem" "/opt/nec/ve/include"
-
-// RUN: %clang -### -target ve %s -nobuiltininc 2>&1 | \
-// RUN:FileCheck -check-prefix=NOBUILT
[llvm-branch-commits] [llvm] c9213e1 - [VE] Correct addRegisterClass calls
Author: Kazushi (Jam) Marukawa
Date: 2020-12-15T01:16:56+09:00
New Revision: c9213e1b299579b37ad4a8c5d5516a10ddfb09b2
URL:
https://github.com/llvm/llvm-project/commit/c9213e1b299579b37ad4a8c5d5516a10ddfb09b2
DIFF:
https://github.com/llvm/llvm-project/commit/c9213e1b299579b37ad4a8c5d5516a10ddfb09b2.diff
LOG: [VE] Correct addRegisterClass calls
Correct addRegisterClass calls for vector mask registers.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93212
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index 25a3910a48e4..f8235bb16622 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -73,8 +73,6 @@ bool VETargetLowering::CanLowerReturn(
static const MVT AllVectorVTs[] = {MVT::v256i32, MVT::v512i32, MVT::v256i64,
MVT::v256f32, MVT::v512f32, MVT::v256f64};
-static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};
-
void VETargetLowering::initRegisterClasses() {
// Set up the register classes.
addRegisterClass(MVT::i32, &VE::I32RegClass);
@@ -86,8 +84,8 @@ void VETargetLowering::initRegisterClasses() {
if (Subtarget->enableVPU()) {
for (MVT VecVT : AllVectorVTs)
addRegisterClass(VecVT, &VE::V64RegClass);
-for (MVT MaskVT : AllMaskVTs)
- addRegisterClass(MaskVT, &VE::VMRegClass);
+addRegisterClass(MVT::v256i1, &VE::VMRegClass);
+addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
}
}
___
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[llvm-branch-commits] [llvm] aefedb1 - [VE] Add logical mask intrinsic instructions
Author: Kazushi (Jam) Marukawa
Date: 2020-12-15T01:34:31+09:00
New Revision: aefedb170734d680516c3875873c80fc29498b43
URL:
https://github.com/llvm/llvm-project/commit/aefedb170734d680516c3875873c80fc29498b43
DIFF:
https://github.com/llvm/llvm-project/commit/aefedb170734d680516c3875873c80fc29498b43.diff
LOG: [VE] Add logical mask intrinsic instructions
Add andm, orm, xorm, eqvm, nndm, negm, pcvm, lzvm, and tovm intrinsic
instructions, a few pseudo instructions to expand logical intrinsic
using VM512, a mechnism to expand such pseudo instructions, and
regression tests. Also, assign vector mask types and vector mask
register classes correctly. This is required to use VM512 registers
as function arguments.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93093
Added:
llvm/test/CodeGen/VE/VELIntrinsics/andm.ll
llvm/test/CodeGen/VE/VELIntrinsics/eqvm.ll
llvm/test/CodeGen/VE/VELIntrinsics/lzvm.ll
llvm/test/CodeGen/VE/VELIntrinsics/negm.ll
llvm/test/CodeGen/VE/VELIntrinsics/nndm.ll
llvm/test/CodeGen/VE/VELIntrinsics/orm.ll
llvm/test/CodeGen/VE/VELIntrinsics/pcvm.ll
llvm/test/CodeGen/VE/VELIntrinsics/tovm.ll
llvm/test/CodeGen/VE/VELIntrinsics/xorm.ll
Modified:
llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
llvm/lib/Target/VE/VEInstrVec.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
index c22fecafb39d..67cbd307903d 100644
--- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
+++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
@@ -1196,3 +1196,18 @@ let TargetPrefix = "ve" in def int_ve_vl_vsclot_vvssl :
GCCBuiltin<"__builtin_ve
let TargetPrefix = "ve" in def int_ve_vl_vsclot_vvssml :
GCCBuiltin<"__builtin_ve_vl_vsclot_vvssml">, Intrinsic<[], [LLVMType,
LLVMType, LLVMType, LLVMType, LLVMType,
LLVMType], [IntrWriteMem]>;
let TargetPrefix = "ve" in def int_ve_vl_vsclncot_vvssl :
GCCBuiltin<"__builtin_ve_vl_vsclncot_vvssl">, Intrinsic<[], [LLVMType,
LLVMType, LLVMType, LLVMType, LLVMType],
[IntrWriteMem]>;
let TargetPrefix = "ve" in def int_ve_vl_vsclncot_vvssml :
GCCBuiltin<"__builtin_ve_vl_vsclncot_vvssml">, Intrinsic<[],
[LLVMType, LLVMType, LLVMType, LLVMType,
LLVMType, LLVMType], [IntrWriteMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_andm_mmm :
GCCBuiltin<"__builtin_ve_vl_andm_mmm">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_andm_MMM :
GCCBuiltin<"__builtin_ve_vl_andm_MMM">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_orm_mmm :
GCCBuiltin<"__builtin_ve_vl_orm_mmm">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_orm_MMM :
GCCBuiltin<"__builtin_ve_vl_orm_MMM">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_xorm_mmm :
GCCBuiltin<"__builtin_ve_vl_xorm_mmm">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_xorm_MMM :
GCCBuiltin<"__builtin_ve_vl_xorm_MMM">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_eqvm_mmm :
GCCBuiltin<"__builtin_ve_vl_eqvm_mmm">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_eqvm_MMM :
GCCBuiltin<"__builtin_ve_vl_eqvm_MMM">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_nndm_mmm :
GCCBuiltin<"__builtin_ve_vl_nndm_mmm">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_nndm_MMM :
GCCBuiltin<"__builtin_ve_vl_nndm_MMM">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_negm_mm :
GCCBuiltin<"__builtin_ve_vl_negm_mm">, Intrinsic<[LLVMType],
[LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_negm_MM :
GCCBuiltin<"__builtin_ve_vl_negm_MM">, Intrinsic<[LLVMType],
[LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pcvm_sml :
GCCBuiltin<"__builtin_ve_vl_pcvm_sml">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_lzvm_sml :
GCCBuiltin<"__builtin_ve_vl_lzvm_sml">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_tovm_sml :
GCCBuiltin<"__builtin_ve_vl_tovm_sml">, Intrinsic<[LLVMType],
[LLVMType, LLVMType], [IntrNoMem]>;
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp
b/llvm/lib/Target/VE/VEInstrInfo.cpp
index 8b56336008a6..530c5d655931 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -731,6 +731,32 @@ static Register getVM512Upper(Register reg) {
st
