[llvm-branch-commits] [llvm] 93b54b7 - [PowerPC][NFCI] PassSubtarget to ASMWriter

2021-01-12 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2021-01-12T16:25:35Z
New Revision: 93b54b7c6733fcb11fd6536499e73872d7452ffb

URL: 
https://github.com/llvm/llvm-project/commit/93b54b7c6733fcb11fd6536499e73872d7452ffb
DIFF: 
https://github.com/llvm/llvm-project/commit/93b54b7c6733fcb11fd6536499e73872d7452ffb.diff

LOG: [PowerPC][NFCI] PassSubtarget to ASMWriter

Subtarget feature bits are needed to change instprinter's behavior based
on feature bits.

Most of the other popular targets were updated back in 2015,
in https://reviews.llvm.org/rGb46d0234a6969
we should update it too.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94449

Added: 


Modified: 
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
llvm/lib/Target/PowerPC/PPC.td

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp 
b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index 2eff1d94ce20..a291a34d4c52 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -71,11 +71,11 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t 
Address,
"reference expression if it is an expression at all.");
 
 O << "\taddis ";
-printOperand(MI, 0, O);
+printOperand(MI, 0, STI, O);
 O << ", ";
-printOperand(MI, 2, O);
+printOperand(MI, 2, STI, O);
 O << "(";
-printOperand(MI, 1, O);
+printOperand(MI, 1, STI, O);
 O << ")";
 return;
   }
@@ -94,7 +94,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t 
Address,
   if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
 const MCSymbol &Symbol = SymExpr->getSymbol();
 if (MI->getOpcode() == PPC::PLDpc) {
-  printInstruction(MI, Address, O);
+  printInstruction(MI, Address, STI, O);
   O << "\n";
   Symbol.print(O, &MAI);
   O << ":";
@@ -124,9 +124,9 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t 
Address,
   SH = 32-SH;
 }
 if (useSubstituteMnemonic) {
-  printOperand(MI, 0, O);
+  printOperand(MI, 0, STI, O);
   O << ", ";
-  printOperand(MI, 1, O);
+  printOperand(MI, 1, STI, O);
   O << ", " << (unsigned int)SH;
 
   printAnnotation(O, Annot);
@@ -141,9 +141,9 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t 
Address,
 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
 if (63-SH == ME) {
   O << "\tsldi ";
-  printOperand(MI, 0, O);
+  printOperand(MI, 0, STI, O);
   O << ", ";
-  printOperand(MI, 1, O);
+  printOperand(MI, 1, STI, O);
   O << ", " << (unsigned int)SH;
   printAnnotation(O, Annot);
   return;
@@ -171,9 +171,9 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t 
Address,
 if (IsBookE && TH != 0 && TH != 16)
   O << (unsigned int) TH << ", ";
 
-printOperand(MI, 1, O);
+printOperand(MI, 1, STI, O);
 O << ", ";
-printOperand(MI, 2, O);
+printOperand(MI, 2, STI, O);
 
 if (!IsBookE && TH != 0 && TH != 16)
   O << ", " << (unsigned int) TH;
@@ -198,21 +198,22 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t 
Address,
 O << "stps";
   O << " ";
 
-  printOperand(MI, 1, O);
+  printOperand(MI, 1, STI, O);
   O << ", ";
-  printOperand(MI, 2, O);
+  printOperand(MI, 2, STI, O);
 
   printAnnotation(O, Annot);
   return;
 }
   }
 
-  if (!printAliasInstr(MI, Address, O))
-printInstruction(MI, Address, O);
+  if (!printAliasInstr(MI, Address, STI, O))
+printInstruction(MI, Address, STI, O);
   printAnnotation(O, Annot);
 }
 
 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
+   const MCSubtargetInfo &STI,
raw_ostream &O,
const char *Modifier) {
   unsigned Code = MI->getOperand(OpNo).getImm();
@@ -306,10 +307,11 @@ void PPCInstPrinter::printPredicateOperand(const MCInst 
*MI, unsigned OpNo,
 
   assert(StringRef(Modifier) == "reg" &&
  "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
-  printOperand(MI, OpNo+1, O);
+  printOperand(MI, OpNo + 1, STI, O);
 }
 
 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
+   const MCSubtargetInfo &STI,
raw_ostream &O) {
   unsigned Code = MI->getOperand(OpNo).getImm();
   if (Code == 2)
@@ -319,6 +321,7 @@ void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, 
unsigned OpNo,
 }
 
 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
+   const MCSubtargetInfo &STI,

[llvm-branch-commits] [llvm] 0f588ac - [PowerPC] Only use some extend mne if assembler is modern enough

2021-01-14 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2021-01-14T20:36:10Z
New Revision: 0f588ac03e15a204b68f0214dda2b9f67410ff62

URL: 
https://github.com/llvm/llvm-project/commit/0f588ac03e15a204b68f0214dda2b9f67410ff62
DIFF: 
https://github.com/llvm/llvm-project/commit/0f588ac03e15a204b68f0214dda2b9f67410ff62.diff

LOG: [PowerPC] Only use some extend mne if assembler is modern enough

Legacy AIX assembly might not support all extended mnes,
add one feature bit to control the generation in MC,
and avoid generating them by default on AIX.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94458

Added: 
llvm/test/MC/PowerPC/modern-aix-as.s

Modified: 
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp 
b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
index 7629fe565bfd..bf9c6feb541e 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
@@ -78,7 +78,17 @@ static MCRegisterInfo *createPPCMCRegisterInfo(const Triple 
&TT) {
 
 static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
  StringRef CPU, StringRef FS) {
-  return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+  // Set some default feature to MC layer.
+  std::string FullFS = std::string(FS);
+
+  if (TT.isOSAIX()) {
+if (!FullFS.empty())
+  FullFS = "+aix," + FullFS;
+else
+  FullFS = "+aix";
+  }
+
+  return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS);
 }
 
 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,

diff  --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index f60adecf65ee..1e6ded231585 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -57,6 +57,10 @@ def DirectivePwrFuture
 
 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
 "Enable 64-bit instructions">;
+def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
+def FeatureModernAIXAs
+: SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
+   "AIX system assembler is modern enough to support new 
mnes">;
 def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
   "Enable floating-point instructions">;
 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index e19ea6a07a0d..03e9d6970a30 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -987,8 +987,11 @@ def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, 
g8rc:$rS)>;
 def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>;
 def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>;
 
-def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>;
-def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>;
+//Disable this alias on AIX for now because as does not support them.
+let Predicates = [ModernAs] in {
+  def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>;
+  def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>;
+}
 
 def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>;
 def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>;

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 018fb8ffe16c..724af23542d7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1120,6 +1120,10 @@ def HasFPU : Predicate<"Subtarget->hasFPU()">;
 def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
 def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
 
+// AIX assembler may not be modern enough to support some extended mne.
+def ModernAs: Predicate<"!Subtarget->isAIXABI() || 
Subtarget->HasModernAIXAs">, 
+ AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
+
 
//===--===//
 // PowerPC Multiclass Definitions.
 
@@ -4649,8 +4653,11 @@ def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
 
+//Disable this alias on AIX for now because as does not support them.
+let Predicates = [ModernAs] in {
 def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>;
 def : InstAlias<"mfudscr $Rx", (MFSPR gp

[llvm-branch-commits] [llvm] f26bc0d - [RegisterClassInfo] Return non-zero for RC without allocatable reg

2021-01-05 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2021-01-05T16:18:34Z
New Revision: f26bc0ddd508edad7e3838850dfcb6b960d6e681

URL: 
https://github.com/llvm/llvm-project/commit/f26bc0ddd508edad7e3838850dfcb6b960d6e681
DIFF: 
https://github.com/llvm/llvm-project/commit/f26bc0ddd508edad7e3838850dfcb6b960d6e681.diff

LOG: [RegisterClassInfo] Return non-zero for RC without allocatable reg

In some case, the RC may have 0 allocatable reg.
eg: VRSAVERC in PowerPC, which has only 1 reg, but it is also reserved.

The curreent implementation will keep calling the computePSetLimit because
getRegPressureSetLimit assume computePSetLimit will return a non-zero value.

The fix simply early return the value from TableGen for such special case.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D92907

Added: 


Modified: 
llvm/lib/CodeGen/RegisterClassInfo.cpp
llvm/test/CodeGen/PowerPC/compute-regpressure.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp 
b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 1523bd4d1649..0488db3d09cb 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -188,7 +188,14 @@ unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) 
const {
   }
   assert(RC && "Failed to find register class");
   compute(RC);
-  unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
-  return TRI->getRegPressureSetLimit(*MF, Idx) -
- TRI->getRegClassWeight(RC).RegWeight * NReserved;
+  unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
+  unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
+  // If all the regs are reserved, return raw RegPressureSetLimit.
+  // One example is VRSAVERC in PowerPC.
+  // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
+  // return non-zero value.
+  if (NAllocatableRegs == 0)
+return RegPressureSetLimit;
+  unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
+  return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * 
NReserved;
 }

diff  --git a/llvm/test/CodeGen/PowerPC/compute-regpressure.ll 
b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
index 7a15e4677267..4ef7fa289381 100644
--- a/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
+++ b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
@@ -1,7 +1,7 @@
 ; REQUIRES: asserts
 ; RUN: llc -debug-only=regalloc < %s 2>&1 |FileCheck %s --check-prefix=DEBUG
 
-; DEBUG-COUNT-3: AllocationOrder(VRSAVERC) = [ ]
+; DEBUG-COUNT-1: AllocationOrder(VRSAVERC) = [ ]
 
 target triple = "powerpc64le-unknown-linux-gnu"
 



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[llvm-branch-commits] [llvm] ab6cb31 - [PowerPC][NFC] Cleanup PPCCTRLoopsVerify pass

2020-12-17 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-17T11:16:33-05:00
New Revision: ab6cb31642fdc84301b7749fdeabba324e3dbc4a

URL: 
https://github.com/llvm/llvm-project/commit/ab6cb31642fdc84301b7749fdeabba324e3dbc4a
DIFF: 
https://github.com/llvm/llvm-project/commit/ab6cb31642fdc84301b7749fdeabba324e3dbc4a.diff

LOG: [PowerPC][NFC] Cleanup PPCCTRLoopsVerify pass

The PPCCTRLoop pass has been moved to HardwareLoops,
so the comments and some useless code are deprecated now.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D93336

Added: 


Modified: 
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp 
b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
index bb12e05173a6..77ea232b0662 100644
--- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -1,4 +1,4 @@
-//===-- PPCCTRLoops.cpp - Identify and generate CTR loops 
-===//
+//===-- PPCCTRLoops.cpp - Verify CTR loops -===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,74 +6,48 @@
 //
 
//===--===//
 //
-// This pass identifies loops where we can generate the PPC branch instructions
-// that decrement and test the count register (CTR) (bdnz and friends).
-//
-// The pattern that defines the induction variable can changed depending on
-// prior optimizations.  For example, the IndVarSimplify phase run by 'opt'
-// normalizes induction variables, and the Loop Strength Reduction pass
-// run by 'llc' may also make changes to the induction variable.
-//
-// Criteria for CTR loops:
-//  - Countable loops (w/ ind. var for a trip count)
-//  - Try inner-most loops first
-//  - No nested CTR loops.
-//  - No function calls in loops.
+// This pass verifies that all bdnz/bdz instructions are dominated by a loop
+// mtctr before any other instructions that might clobber the ctr register.
 //
 
//===--===//
 
+// CTR loops are produced by the HardwareLoops pass and this pass is simply a
+// verification that no invalid CTR loops are produced. As such, it isn't
+// something that needs to be run (or even defined) for Release builds so the
+// entire file is guarded by NDEBUG.
+#ifndef NDEBUG
+#include 
+
+#include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "PPC.h"
-#include "PPCSubtarget.h"
-#include "PPCTargetMachine.h"
-#include "PPCTargetTransformInfo.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Analysis/AssumptionCache.h"
-#include "llvm/Analysis/CFG.h"
-#include "llvm/Analysis/CodeMetrics.h"
-#include "llvm/Analysis/LoopInfo.h"
-#include "llvm/Analysis/LoopIterator.h"
-#include "llvm/Analysis/TargetLibraryInfo.h"
-#include "llvm/Analysis/TargetTransformInfo.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/IR/Constants.h"
-#include "llvm/IR/DerivedTypes.h"
-#include "llvm/IR/Dominators.h"
-#include "llvm/IR/InlineAsm.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/IR/IntrinsicInst.h"
-#include "llvm/IR/Module.h"
-#include "llvm/IR/ValueHandle.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/ilist_iterator.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBundleIterator.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/Register.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/PassRegistry.h"
+#include "llvm/Support/CodeGen.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/GenericDomTreeConstruction.h"
+#include "llvm/Support/Printable.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Transforms/Utils.h"
-#include "llvm/Transforms/Utils/BasicBlockUtils.h"
-#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Transforms/Utils/LoopUtils.h"
-
-#ifndef NDEBUG
-#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#endif
 
 using namespace llvm;
 
-#define DEBUG_TYPE "ctrloops"
-
-#ifndef NDEBUG
-static cl::opt CTRLoopLimit("ppc-max-ctrloop", cl::Hidden, cl::init(-1));
-#endif
+#define DEBUG_TYPE "ppc-ctrloops-verify"
 
 namespace {
 
-#ifndef NDEBUG
   struct PPCCTRLoopsVerify : public MachineFunctionPass {
   public:

[llvm-branch-commits] [llvm] 297be78 - [docs] Add Deprecated section to ReleaseNotes

2020-07-17 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-07-17T15:48:55Z
New Revision: 297be788a797c0ab98d9677f50e3dc57faab363b

URL: 
https://github.com/llvm/llvm-project/commit/297be788a797c0ab98d9677f50e3dc57faab363b
DIFF: 
https://github.com/llvm/llvm-project/commit/297be788a797c0ab98d9677f50e3dc57faab363b.diff

LOG: [docs] Add Deprecated section to ReleaseNotes

This is brought up in https://reviews.llvm.org/D83915.
We would like to remove some feature in PowerPC.

We did send RFC before, but we think it might be a better idea that
we indicate planned removal in the Release Notes for version 11
and actual removal in those for version 12..

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D83968

Added: 


Modified: 
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 2f93afd8374c..ed1718a95054 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -31,6 +31,10 @@ LLVM web page, this document applies to the *next* release, 
not the current
 one.  To see the release notes for a specific release, please see the `releases
 page `_.
 
+Deprecated and Removed Features/APIs
+=
+* BG/Q support, including QPX, will be removed in the 12.0.0 release.
+
 Non-comprehensive list of changes in this release
 =
 .. NOTE



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[llvm-branch-commits] [llvm] c8ec685 - [llvm-exegesis][PowerPC] Add more register classes

2020-12-04 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-04T15:02:12Z
New Revision: c8ec685ca555459051125f9c0194ceee19e959d7

URL: 
https://github.com/llvm/llvm-project/commit/c8ec685ca555459051125f9c0194ceee19e959d7
DIFF: 
https://github.com/llvm/llvm-project/commit/c8ec685ca555459051125f9c0194ceee19e959d7.diff

LOG: [llvm-exegesis][PowerPC] Add more register classes

This PR adds more register class support in PowerPC,
mark OperandType for imm and memory operands.

Also added more unit tests for SnippetGenerator.

Reviewed By: #powerpc, steven.zhang

Differential Revision: https://reviews.llvm.org/D88044

Added: 
llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp
llvm/unittests/tools/llvm-exegesis/PowerPC/TestBase.h

Modified: 
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index eaf20fdc0173..931109e2cbc4 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -19,12 +19,14 @@ def s16imm64 : Operand {
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS16ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def u16imm64 : Operand {
   let PrintMethod = "printU16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCU16ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def s17imm64 : Operand {
   // This operand type is used for addis/lis to allow the assembler parser
@@ -34,6 +36,7 @@ def s17imm64 : Operand {
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS17ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def tocentry : Operand {
   let MIOperandInfo = (ops i64imm:$imm);

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 1496accf83d8..2dc575923da7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -666,6 +666,7 @@ def PPCU1ImmAsmOperand : AsmOperandClass {
 def u1imm   : Operand {
   let PrintMethod = "printU1ImmOperand";
   let ParserMatchClass = PPCU1ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCU2ImmAsmOperand : AsmOperandClass {
@@ -675,6 +676,7 @@ def PPCU2ImmAsmOperand : AsmOperandClass {
 def u2imm   : Operand {
   let PrintMethod = "printU2ImmOperand";
   let ParserMatchClass = PPCU2ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCATBitsAsHintAsmOperand : AsmOperandClass {
@@ -684,6 +686,7 @@ def PPCATBitsAsHintAsmOperand : AsmOperandClass {
 def atimm   : Operand {
   let PrintMethod = "printATBitsAsHint";
   let ParserMatchClass = PPCATBitsAsHintAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCU3ImmAsmOperand : AsmOperandClass {
@@ -693,6 +696,7 @@ def PPCU3ImmAsmOperand : AsmOperandClass {
 def u3imm   : Operand {
   let PrintMethod = "printU3ImmOperand";
   let ParserMatchClass = PPCU3ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCU4ImmAsmOperand : AsmOperandClass {
@@ -702,6 +706,7 @@ def PPCU4ImmAsmOperand : AsmOperandClass {
 def u4imm   : Operand {
   let PrintMethod = "printU4ImmOperand";
   let ParserMatchClass = PPCU4ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS5ImmAsmOperand : AsmOperandClass {
   let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
@@ -711,6 +716,7 @@ def s5imm   : Operand {
   let PrintMethod = "printS5ImmOperand";
   let ParserMatchClass = PPCS5ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<5>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU5ImmAsmOperand : AsmOperandClass {
   let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
@@ -720,6 +726,7 @@ def u5imm   : Operand {
   let PrintMethod = "printU5ImmOperand";
   let ParserMatchClass = PPCU5ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU6ImmAsmOperand : AsmOperandClass {
   let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
@@ -729,6 +736,7 @@ def u6imm   : Operand {
   let PrintMethod = "printU6ImmOperand";
   let ParserMatchClass = PPCU6ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU7ImmAsmOperand : AsmOperandClass {
   let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
@@ -738,6 +746,7 @@ def u7imm   : Operand {
   let PrintMethod = "printU7ImmOperand";
   let ParserMatchClass = PPCU7ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<7>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU8

[llvm-branch-commits] [clang] b49b8f0 - [PowerPC][Clang] Remove QPX support

2020-12-07 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-07T10:15:39-05:00
New Revision: b49b8f096c0382da17d3203dfaa3f54d04a47d27

URL: 
https://github.com/llvm/llvm-project/commit/b49b8f096c0382da17d3203dfaa3f54d04a47d27
DIFF: 
https://github.com/llvm/llvm-project/commit/b49b8f096c0382da17d3203dfaa3f54d04a47d27.diff

LOG: [PowerPC][Clang] Remove QPX support

Clean up QPX code in clang missed in https://reviews.llvm.org/D83915

Reviewed By: #powerpc, steven.zhang

Differential Revision: https://reviews.llvm.org/D92329

Added: 


Modified: 
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Driver/Options.td
clang/lib/AST/ASTContext.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/ppc64-elf-abi.c
clang/test/Driver/linux-ld.c
clang/test/Driver/ppc-features.cpp
clang/test/OpenMP/simd_metadata.c
llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-only-for-real.ll

Removed: 
clang/test/CodeGen/ppc64-qpx-vector.c



diff  --git a/clang/docs/ClangCommandLineReference.rst 
b/clang/docs/ClangCommandLineReference.rst
index 3674f3a62695..ce510f335bd4 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -3169,8 +3169,6 @@ PowerPC
 
 .. option:: -mpower9-vector, -mno-power9-vector
 
-.. option:: -mqpx, -mno-qpx
-
 .. option:: -msecure-plt
 
 .. option:: -mspe, -mno-spe

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index b58f5cbc63d0..6480d6e80293 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2639,8 +2639,6 @@ def mno_mfocrf : Flag<["-"], "mno-mfocrf">, 
Group;
 def mno_mfcrf : Flag<["-"], "mno-mfcrf">, Alias;
 def mpopcntd : Flag<["-"], "mpopcntd">, Group;
 def mno_popcntd : Flag<["-"], "mno-popcntd">, Group;
-def mqpx : Flag<["-"], "mqpx">, Group;
-def mno_qpx : Flag<["-"], "mno-qpx">, Group;
 def mcrbits : Flag<["-"], "mcrbits">, Group;
 def mno_crbits : Flag<["-"], "mno-crbits">, Group;
 def minvariant_function_descriptors :

diff  --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index dacb9679c493..c52369cd8a02 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -2360,12 +2360,6 @@ unsigned ASTContext::getTypeUnadjustedAlign(const Type 
*T) const {
 
 unsigned ASTContext::getOpenMPDefaultSimdAlign(QualType T) const {
   unsigned SimdAlign = getTargetInfo().getSimdDefaultAlign();
-  // Target ppc64 with QPX: simd default alignment for pointer to double is 32.
-  if ((getTargetInfo().getTriple().getArch() == llvm::Triple::ppc64 ||
-   getTargetInfo().getTriple().getArch() == llvm::Triple::ppc64le) &&
-  getTargetInfo().getABI() == "elfv1-qpx" &&
-  T->isSpecificBuiltinType(BuiltinType::Double))
-SimdAlign = 256;
   return SimdAlign;
 }
 

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ad754462370f..a4677cd067f7 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -438,7 +438,7 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public 
PPCTargetInfo {
 
   // PPC64 Linux-specific ABI options.
   bool setABI(const std::string &Name) override {
-if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
+if (Name == "elfv1" || Name == "elfv2") {
   ABI = Name;
   return true;
 }

diff  --git a/clang/lib/CodeGen/TargetInfo.cpp 
b/clang/lib/CodeGen/TargetInfo.cpp
index 4815266371bc..7213f7864d43 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -4885,42 +4885,12 @@ class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
 private:
   static const unsigned GPRBits = 64;
   ABIKind Kind;
-  bool HasQPX;
   bool IsSoftFloatABI;
 
-  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
-  // will be passed in a QPX register.
-  bool IsQPXVectorTy(const Type *Ty) const {
-if (!HasQPX)
-  return false;
-
-if (const VectorType *VT = Ty->getAs()) {
-  unsigned NumElements = VT->getNumElements();
-  if (NumElements == 1)
-return false;
-
-  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
-if (getContext().getTypeSize(Ty) <= 256)
-  return true;
-  } else if (VT->getElementType()->
-   isSpecificBuiltinType(BuiltinType::Float)) {
-if (getContext().getTypeSize(Ty) <= 128)
-  return true;
-  }
-}
-
-return false;
-  }
-
-  bool IsQPXVectorTy(QualType Ty) const {
-return IsQPXVectorTy(Ty.getTypePtr());
-  }
-
 public:
-  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
+  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind,
  bool SoftFloatABI)
-  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
-IsSoftFloatABI(SoftFloatABI) {}
+  : SwiftABII

[llvm-branch-commits] [llvm] 02b2c02 - [PowerPC] Precommit testcases for regpressure compute fix

2020-12-08 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-09T03:37:00Z
New Revision: 02b2c024193b1985d85855a7f85b98aef9ebbcdb

URL: 
https://github.com/llvm/llvm-project/commit/02b2c024193b1985d85855a7f85b98aef9ebbcdb
DIFF: 
https://github.com/llvm/llvm-project/commit/02b2c024193b1985d85855a7f85b98aef9ebbcdb.diff

LOG: [PowerPC] Precommit testcases for regpressure compute fix

Added: 
llvm/test/CodeGen/PowerPC/compute-regpressure.ll

Modified: 


Removed: 




diff  --git a/llvm/test/CodeGen/PowerPC/compute-regpressure.ll 
b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
new file mode 100644
index ..7a15e4677267
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
@@ -0,0 +1,30 @@
+; REQUIRES: asserts
+; RUN: llc -debug-only=regalloc < %s 2>&1 |FileCheck %s --check-prefix=DEBUG
+
+; DEBUG-COUNT-3: AllocationOrder(VRSAVERC) = [ ]
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+define hidden fastcc void @test() {
+freescalar:
+  %0 = load i32, i32* undef, align 4
+  br label %if.end420
+
+if.end420:; preds = %freescalar
+  br label %free_rv
+
+free_rv:  ; preds = %if.end420
+  %and427 = and i32 %0, -2147481600
+  %cmp428 = icmp eq i32 %and427, -2147481600
+  br i1 %cmp428, label %if.then430, label %free_body
+
+if.then430:   ; preds = %free_rv
+  call fastcc void undef()
+  br label %free_body
+
+free_body:; preds = %if.then430, 
%free_rv
+  %or502 = or i32 undef, 255
+  store i32 %or502, i32* undef, align 4
+  ret void
+}
+



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[llvm-branch-commits] [llvm] 45b08c4 - [PowerPC] Set SubRegIndex offset for sub_vsx1/sub_pair1

2020-12-08 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-08T22:56:44-05:00
New Revision: 45b08c41bfb04684abfbd846e2924177dbcddd04

URL: 
https://github.com/llvm/llvm-project/commit/45b08c41bfb04684abfbd846e2924177dbcddd04
DIFF: 
https://github.com/llvm/llvm-project/commit/45b08c41bfb04684abfbd846e2924177dbcddd04.diff

LOG: [PowerPC] Set SubRegIndex offset for sub_vsx1/sub_pair1

We defined SubRegIndex for 256/512 regs,
but we did not set the offset for higher part,
so the offset of lower and higher part are the same.
This may cause problem in assessing ranges of SubReg,
it is great that this haven't affected any testcases,
but I think we should fix it to avoid hidden bugs in the future.

Reviewed By: bsaleil, #powerpc

Differential Revision: https://reviews.llvm.org/D92864

Added: 


Modified: 
llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 38ee19c72712..e03617aa75ff 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -17,9 +17,9 @@ def sub_un : SubRegIndex<1, 3>;
 def sub_32 : SubRegIndex<32>;
 def sub_64 : SubRegIndex<64>;
 def sub_vsx0 : SubRegIndex<128>;
-def sub_vsx1 : SubRegIndex<128>;
+def sub_vsx1 : SubRegIndex<128, 128>;
 def sub_pair0 : SubRegIndex<256>;
-def sub_pair1 : SubRegIndex<256>;
+def sub_pair1 : SubRegIndex<256, 256>;
 }
 
 



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[llvm-branch-commits] [llvm] cf638f8 - [PowerPC] Remove duplicate layout

2020-12-11 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-11T15:52:29Z
New Revision: cf638f84a4ba1b0a1ba229b12c89bd6c96912fb5

URL: 
https://github.com/llvm/llvm-project/commit/cf638f84a4ba1b0a1ba229b12c89bd6c96912fb5
DIFF: 
https://github.com/llvm/llvm-project/commit/cf638f84a4ba1b0a1ba229b12c89bd6c96912fb5.diff

LOG: [PowerPC] Remove duplicate layout

Added: 


Modified: 
llvm/test/CodeGen/PowerPC/unaligned.ll

Removed: 




diff  --git a/llvm/test/CodeGen/PowerPC/unaligned.ll 
b/llvm/test/CodeGen/PowerPC/unaligned.ll
index 977c470e668e..f6e666d6331d 100644
--- a/llvm/test/CodeGen/PowerPC/unaligned.ll
+++ b/llvm/test/CodeGen/PowerPC/unaligned.ll
@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 
-mcpu=pwr7 -mattr=-vsx | FileCheck %s
-target datalayout = 
"E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 
-mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = 
"E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 



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[llvm-branch-commits] [lld] 9b05f18 - [lld][PowerPC][test] Avoid flaky failures

2020-12-11 Thread Jinsong Ji via llvm-branch-commits 

Author: Jinsong Ji
Date: 2020-12-11T19:46:51Z
New Revision: 9b05f1889aa8ca0693b17ce7dd84da3f6fab90da

URL: 
https://github.com/llvm/llvm-project/commit/9b05f1889aa8ca0693b17ce7dd84da3f6fab90da
DIFF: 
https://github.com/llvm/llvm-project/commit/9b05f1889aa8ca0693b17ce7dd84da3f6fab90da.diff

LOG: [lld][PowerPC][test] Avoid flaky failures

This test may fail if there is a new changes to this tests.

The archives are not deleted so the contents from the previous test run
may affect the contents for the current run,
so this will require cleaning up the Output dir or force build of buildbot.

The fix is to put all the objects in the temporary dir that we cleanup every 
run,
 to avoid run-2-run flaky failures.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D93128

Added: 


Modified: 
lld/test/ELF/common-archive-lookup.s

Removed: 




diff  --git a/lld/test/ELF/common-archive-lookup.s 
b/lld/test/ELF/common-archive-lookup.s
index c33ff86973ef..e219f15b6015 100644
--- a/lld/test/ELF/common-archive-lookup.s
+++ b/lld/test/ELF/common-archive-lookup.s
@@ -5,62 +5,62 @@
 # RUN: cd %t.dir
 
 ## Object files.
-# RUN: llvm-mc -triple=powerpc64le -filetype=obj ref.s -o %t1.o
-# RUN: llvm-mc -triple=powerpc64le -filetype=obj refanddef.s -o %t2.o
-# RUN: llvm-mc -triple=powerpc64le -filetype=obj def.s -o %tstrong_data_only.o
-# RUN: llvm-mc -triple=powerpc64le -filetype=obj weak.s -o %tweak_data_only.o
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj ref.s -o 1.o
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj refanddef.s -o 2.o
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj def.s -o strong_data_only.o
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj weak.s -o weak_data_only.o
 
-# RUN: llvm-mc -triple=powerpc64le -filetype=obj main.s -o %tmain.o
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj main.s -o main.o
 
 ## Object file archives.
-# RUN: llvm-ar crs %t1.a %t1.o %tstrong_data_only.o
-# RUN: llvm-ar crs %t2.a %t1.o %tweak_data_only.o
-# RUN: llvm-ar crs %t3.a %t2.o %tstrong_data_only.o
+# RUN: llvm-ar crs 1.a 1.o strong_data_only.o
+# RUN: llvm-ar crs 2.a 1.o weak_data_only.o
+# RUN: llvm-ar crs 3.a 2.o strong_data_only.o
 
 ## Bitcode files.
-# RUN: llvm-as -o %t1.bc commonblock.ll
-# RUN: llvm-as -o %t2.bc blockdata.ll
+# RUN: llvm-as -o 1.bc commonblock.ll
+# RUN: llvm-as -o 2.bc blockdata.ll
 
 ## Bitcode archive.
-# RUN: llvm-ar crs %t4.a %t1.bc %t2.bc
+# RUN: llvm-ar crs 4.a 1.bc 2.bc
 
-# RUN: ld.lld -o %t1 %tmain.o %t1.a
-# RUN: llvm-objdump -D -j .data %t1 | FileCheck --check-prefix=TEST1 %s
+# RUN: ld.lld -o 1 main.o 1.a
+# RUN: llvm-objdump -D -j .data 1 | FileCheck --check-prefix=TEST1 %s
 
-# RUN: ld.lld -o %t2 %tmain.o --start-lib %t1.o %tstrong_data_only.o --end-lib
-# RUN: llvm-objdump -D -j .data %t2 | FileCheck --check-prefix=TEST1 %s
+# RUN: ld.lld -o 2 main.o --start-lib 1.o strong_data_only.o --end-lib
+# RUN: llvm-objdump -D -j .data 2 | FileCheck --check-prefix=TEST1 %s
 
-# RUN: ld.lld -o %t3 %tmain.o %t2.a
-# RUN: llvm-objdump -D -j .data %t3 | FileCheck --check-prefix=TEST1 %s
+# RUN: ld.lld -o 3 main.o 2.a
+# RUN: llvm-objdump -D -j .data 3 | FileCheck --check-prefix=TEST1 %s
 
-# RUN: ld.lld -o %t4 %tmain.o --start-lib %t1.o %tweak_data_only.o --end-lib
-# RUN: llvm-objdump -D -j .data %t4 | FileCheck --check-prefix=TEST1 %s
+# RUN: ld.lld -o 4 main.o --start-lib 1.o weak_data_only.o --end-lib
+# RUN: llvm-objdump -D -j .data 4 | FileCheck --check-prefix=TEST1 %s
 
-# RUN: ld.lld -o %t5 %tmain.o %t3.a --print-map | FileCheck --check-prefix=MAP 
%s
+# RUN: ld.lld -o 5 main.o 3.a --print-map | FileCheck --check-prefix=MAP %s
 
-# RUN: ld.lld -o %t6 %tmain.o %t2.o %t1.a
-# RUN: llvm-objdump -D -j .data %t6 | FileCheck --check-prefix=TEST2 %s
+# RUN: ld.lld -o 6 main.o 2.o 1.a
+# RUN: llvm-objdump -D -j .data 6 | FileCheck --check-prefix=TEST2 %s
 
-# RUN: ld.lld -o %t7 %tmain.o %t2.o --start-lib %t1.o %tstrong_data_only.o 
--end-lib
-# RUN: llvm-objdump -D -j .data %t7 | FileCheck --check-prefix=TEST2 %s
+# RUN: ld.lld -o 7 main.o 2.o --start-lib 1.o strong_data_only.o --end-lib
+# RUN: llvm-objdump -D -j .data 7 | FileCheck --check-prefix=TEST2 %s
 
-# RUN: not ld.lld -o %t8 %tmain.o %t1.a %tstrong_data_only.o 2>&1 | \
+# RUN: not ld.lld -o 8 main.o 1.a strong_data_only.o 2>&1 | \
 # RUN:   FileCheck --check-prefix=ERR %s
 
-# RUN: not ld.lld -o %t9 %tmain.o --start-lib %t1.o %t2.o --end-lib  
%tstrong_data_only.o 2>&1 | \
+# RUN: not ld.lld -o 9 main.o --start-lib 1.o 2.o --end-lib  
strong_data_only.o 2>&1 | \
 # RUN:   FileCheck --check-prefix=ERR %s
 
 # ERR: ld.lld: error: duplicate symbol: block
 
-# RUN: ld.lld --no-fortran-common -o %t10 %tmain.o %t1.a
-# RUN: llvm-readobj --syms %t10 | FileCheck --check-prefix=NFC %s
+# RUN: ld.lld --no-fortran-common -o 10 main.o 1.a
+# RUN: llvm-readobj --syms 10 | FileCheck --check-prefix=NFC %s
 
-# RUN: ld.lld --no-fortr