[llvm-branch-commits] [llvm] 7e6bf0b - [release][docs] Update contributions to LLVM 11 for SVE.

2020-08-18 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-08-18T21:13:21Z
New Revision: 7e6bf0bfe6de9e0d0e58764a66f93210f296bbfa

URL: 
https://github.com/llvm/llvm-project/commit/7e6bf0bfe6de9e0d0e58764a66f93210f296bbfa
DIFF: 
https://github.com/llvm/llvm-project/commit/7e6bf0bfe6de9e0d0e58764a66f93210f296bbfa.diff

LOG: [release][docs] Update contributions to LLVM 11 for SVE.

Differential Revision: https://reviews.llvm.org/D85977

Added: 


Modified: 
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c9ac61d29676..612a5417df95 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -66,7 +66,9 @@ Changes to the LLVM IR
   added to describe the mapping between scalar functions and vector
   functions, to enable vectorization of call sites. The information
   provided by the attribute is interfaced via the API provided by the
-  ``VFDatabase`` class.
+  ``VFDatabase`` class. When scanning through the set of vector
+  functions associated with a scalar call, the loop vectorizer now
+  relies on ``VFDatabase``, instead of ``TargetLibraryInfo``.
 
 * `dereferenceable` attributes and metadata on pointers no longer imply
   anything about the alignment of the pointer in question. Previously, some
@@ -78,6 +80,17 @@ Changes to the LLVM IR
   information. This information is used to represent Fortran modules debug
   info at IR level.
 
+* LLVM IR now supports two distinct ``llvm::FixedVectorType`` and
+  ``llvm::ScalableVectorType`` vector types, both derived from the
+  base class ``llvm::VectorType``. A number of algorithms dealing with
+  IR vector types have been updated to make sure they work for both
+  scalable and fixed vector types. Where possible, the code has been
+  made generic to cover both cases using the base class. Specifically,
+  places that were using the type ``unsigned`` to count the number of
+  lanes of a vector are now using ``llvm::ElementCount``. In places
+  where ``uint64_t`` was used to denote the size in bits of a IR type
+  we have partially migrated the codebase to using ``llvm::TypeSize``.
+
 Changes to building LLVM
 
 
@@ -110,6 +123,55 @@ During this release ...
   default may wish to specify ``-fno-omit-frame-pointer`` to get the old
   behavior. This improves compatibility with GCC.
 
+* Clang adds support for the following macros that enable the
+  C-intrinsics from the `Arm C language extensions for SVE
+  `_ (version
+  ``00bet5``, see section 2.1 for the list of intrinsics associated to
+  each macro):
+
+
+  =  =
+  Preprocessor macro Target feature
+  =  =
+  ``__ARM_FEATURE_SVE``  ``+sve``
+  ``__ARM_FEATURE_SVE_BF16`` ``+sve+bf16``
+  ``__ARM_FEATURE_SVE_MATMUL_FP32``  ``+sve+f32mm``
+  ``__ARM_FEATURE_SVE_MATMUL_FP64``  ``+sve+f64mm``
+  ``__ARM_FEATURE_SVE_MATMUL_INT8``  ``+sve+i8mm``
+  ``__ARM_FEATURE_SVE2`` ``+sve2``
+  ``__ARM_FEATURE_SVE2_AES`` ``+sve2-aes``
+  ``__ARM_FEATURE_SVE2_BITPERM`` ``+sve2-bitperm``
+  ``__ARM_FEATURE_SVE2_SHA3````+sve2-sha3``
+  ``__ARM_FEATURE_SVE2_SM4`` ``+sve2-sm4``
+  =  =
+
+  The macros enable users to write C/C++ `Vector Length Agnostic
+  (VLA)` loops, that can be executed on any CPU that implements the
+  underlying instructions supported by the C intrinsics, independently
+  of the hardware vector register size.
+
+  For example, the ``__ARM_FEATURE_SVE`` macro is enabled when
+  targeting AArch64 code generation by setting ``-march=armv8-a+sve``
+  on the command line.
+
+  .. code-block:: c
+ :caption: Example of VLA addition of two arrays with SVE ACLE.
+
+ // Compile with:
+ // `clang++ -march=armv8a+sve ...` (for c++)
+ // `clang -stc=c11 -march=armv8a+sve ...` (for c)
+ #include 
+
+ void VLA_add_arrays(double *x, double *y, double *out, unsigned N) {
+   for (unsigned i = 0; i < N; i += svcntd()) {
+ svbool_t Pg = svwhilelt_b64(i, N);
+ svfloat64_t vx = svld1(Pg, &x[i]);
+ svfloat64_t vy = svld1(Pg, &y[i]);
+ svfloat64_t vout = svadd_x(Pg, vx, vy);
+ svst1(Pg, &out[i], vout);
+   }
+ }
+
 Changes to the MIPS Target
 --
 



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[llvm-branch-commits] [llvm] c7c68c7 - [release][docs] Note on lazy binding and SVE.

2020-08-20 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-08-20T15:33:30Z
New Revision: c7c68c7965190393ffa594d0c8bec79c4ca7dbfb

URL: 
https://github.com/llvm/llvm-project/commit/c7c68c7965190393ffa594d0c8bec79c4ca7dbfb
DIFF: 
https://github.com/llvm/llvm-project/commit/c7c68c7965190393ffa594d0c8bec79c4ca7dbfb.diff

LOG: [release][docs] Note on lazy binding and SVE.

Added: 


Modified: 
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 612a5417df95..116898aeb75a 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -172,6 +172,11 @@ During this release ...
}
  }
 
+  Please note that support for lazy binding of SVE function calls is
+  incomplete. When you interface user code with SVE functions that are
+  provided through shared libraries, avoid using lazy binding. If you
+  use lazy binding, the results could be corrupted.
+
 Changes to the MIPS Target
 --
 



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[llvm-branch-commits] [llvm] 414f32a - [release][docs] Move SVE release notes to AArch64 section.

2020-08-20 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-08-20T16:24:59Z
New Revision: 414f32a9e862b11f51063b75729278f8d81b12e9

URL: 
https://github.com/llvm/llvm-project/commit/414f32a9e862b11f51063b75729278f8d81b12e9
DIFF: 
https://github.com/llvm/llvm-project/commit/414f32a9e862b11f51063b75729278f8d81b12e9.diff

LOG: [release][docs] Move SVE release notes to AArch64 section.

Added: 


Modified: 
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 116898aeb75a..aea1550960e8 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -103,26 +103,6 @@ Changes to the AArch64 Backend
 * Clearly error out on unsupported relocations when targeting COFF, instead
   of silently accepting some (without being able to do what was requested).
 
-Changes to the ARM Backend
---
-
-During this release ...
-
-* Implemented C-language intrinsics for the full Arm v8.1-M MVE instruction
-  set.  now supports the complete API defined in the Arm C
-  Language Extensions.
-
-* Added support for assembly for the optional Custom Datapath Extension (CDE)
-  for Arm M-profile targets.
-
-* Implemented C-language intrinsics  for the CDE instruction 
set.
-
-* Clang now defaults to ``-fomit-frame-pointer`` when targeting non-Android
-  Linux for arm and thumb when optimizations are enabled. Users that were
-  previously not specifying a value and relying on the implicit compiler
-  default may wish to specify ``-fno-omit-frame-pointer`` to get the old
-  behavior. This improves compatibility with GCC.
-
 * Clang adds support for the following macros that enable the
   C-intrinsics from the `Arm C language extensions for SVE
   `_ (version
@@ -177,6 +157,26 @@ During this release ...
   provided through shared libraries, avoid using lazy binding. If you
   use lazy binding, the results could be corrupted.
 
+Changes to the ARM Backend
+--
+
+During this release ...
+
+* Implemented C-language intrinsics for the full Arm v8.1-M MVE instruction
+  set.  now supports the complete API defined in the Arm C
+  Language Extensions.
+
+* Added support for assembly for the optional Custom Datapath Extension (CDE)
+  for Arm M-profile targets.
+
+* Implemented C-language intrinsics  for the CDE instruction 
set.
+
+* Clang now defaults to ``-fomit-frame-pointer`` when targeting non-Android
+  Linux for arm and thumb when optimizations are enabled. Users that were
+  previously not specifying a value and relying on the implicit compiler
+  default may wish to specify ``-fno-omit-frame-pointer`` to get the old
+  behavior. This improves compatibility with GCC.
+
 Changes to the MIPS Target
 --
 



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[llvm-branch-commits] [clang] 6f2ba83 - [release][SVE] Move notes for SVE ACLE to the release notes of clang.

2020-08-26 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-08-26T15:41:59+01:00
New Revision: 6f2ba83779c8055a58f1cc9ee33686a8109ff33a

URL: 
https://github.com/llvm/llvm-project/commit/6f2ba83779c8055a58f1cc9ee33686a8109ff33a
DIFF: 
https://github.com/llvm/llvm-project/commit/6f2ba83779c8055a58f1cc9ee33686a8109ff33a.diff

LOG: [release][SVE] Move notes for SVE ACLE to the release notes of clang.

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 6f336088750f..a8fde6b452d0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -90,6 +90,60 @@ Non-comprehensive list of changes in this release
   a fixed hashing algorithm that prevents some collision when loading
   out-of-date profile informations. Clang can still read old profile files.
 
+- Clang adds support for the following macros that enable the
+  C-intrinsics from the `Arm C language extensions for SVE
+  `_ (version
+  ``00bet5``, see section 2.1 for the list of intrinsics associated to
+  each macro):
+
+
+  =  =
+  Preprocessor macro Target feature
+  =  =
+  ``__ARM_FEATURE_SVE``  ``+sve``
+  ``__ARM_FEATURE_SVE_BF16`` ``+sve+bf16``
+  ``__ARM_FEATURE_SVE_MATMUL_FP32``  ``+sve+f32mm``
+  ``__ARM_FEATURE_SVE_MATMUL_FP64``  ``+sve+f64mm``
+  ``__ARM_FEATURE_SVE_MATMUL_INT8``  ``+sve+i8mm``
+  ``__ARM_FEATURE_SVE2`` ``+sve2``
+  ``__ARM_FEATURE_SVE2_AES`` ``+sve2-aes``
+  ``__ARM_FEATURE_SVE2_BITPERM`` ``+sve2-bitperm``
+  ``__ARM_FEATURE_SVE2_SHA3````+sve2-sha3``
+  ``__ARM_FEATURE_SVE2_SM4`` ``+sve2-sm4``
+  =  =
+
+  The macros enable users to write C/C++ `Vector Length Agnostic
+  (VLA)` loops, that can be executed on any CPU that implements the
+  underlying instructions supported by the C intrinsics, independently
+  of the hardware vector register size.
+
+  For example, the ``__ARM_FEATURE_SVE`` macro is enabled when
+  targeting AArch64 code generation by setting ``-march=armv8-a+sve``
+  on the command line.
+
+  .. code-block:: c
+ :caption: Example of VLA addition of two arrays with SVE ACLE.
+
+ // Compile with:
+ // `clang++ -march=armv8a+sve ...` (for c++)
+ // `clang -stc=c11 -march=armv8a+sve ...` (for c)
+ #include 
+
+ void VLA_add_arrays(double *x, double *y, double *out, unsigned N) {
+   for (unsigned i = 0; i < N; i += svcntd()) {
+ svbool_t Pg = svwhilelt_b64(i, N);
+ svfloat64_t vx = svld1(Pg, &x[i]);
+ svfloat64_t vy = svld1(Pg, &y[i]);
+ svfloat64_t vout = svadd_x(Pg, vx, vy);
+ svst1(Pg, &out[i], vout);
+   }
+ }
+
+  Please note that support for lazy binding of SVE function calls is
+  incomplete. When you interface user code with SVE functions that are
+  provided through shared libraries, avoid using lazy binding. If you
+  use lazy binding, the results could be corrupted.
+
 New Compiler Flags
 --
 

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6c92c1224238..5bbdea65c3e7 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -106,59 +106,11 @@ Changes to the AArch64 Backend
 * Clearly error out on unsupported relocations when targeting COFF, instead
   of silently accepting some (without being able to do what was requested).
 
-* Clang adds support for the following macros that enable the
-  C-intrinsics from the `Arm C language extensions for SVE
+* Implemented codegen support for the SVE C-language intrinsics
+  documented in `Arm C Language Extensions (ACLE) for SVE
   `_ (version
-  ``00bet5``, see section 2.1 for the list of intrinsics associated to
-  each macro):
-
-
-  =  =
-  Preprocessor macro Target feature
-  =  =
-  ``__ARM_FEATURE_SVE``  ``+sve``
-  ``__ARM_FEATURE_SVE_BF16`` ``+sve+bf16``
-  ``__ARM_FEATURE_SVE_MATMUL_FP32``  ``+sve+f32mm``
-  ``__ARM_FEATURE_SVE_MATMUL_FP64``  ``+sve+f64mm``
-  ``__ARM_FEATURE_SVE_MATMUL_INT8``  ``+sve+i8mm``
-  ``__ARM_FEATURE_SVE2`` ``+sve2``
-  ``__ARM_FEATURE_SVE2_AES`` ``+sve2-aes``
-  ``__ARM_FEATURE_SVE2_BITPERM`` ``+sve2-bitperm``
-  ``__ARM_FEATURE_SVE2_SHA3````+sve2-sha3``
-  ``__ARM_FEATURE_SVE2_SM4`` ``+sve2-sm4``
-  =  =
-
-  The macros enable users to write C/

[llvm-branch-commits] [llvm] 29e94dd - [MC][SVE] Fix data operand for instruction alias of `st1d`.

2020-08-26 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-08-26T20:12:13Z
New Revision: 29e94ddb3930e3d7b54afb3753a6a40d6ef57898

URL: 
https://github.com/llvm/llvm-project/commit/29e94ddb3930e3d7b54afb3753a6a40d6ef57898
DIFF: 
https://github.com/llvm/llvm-project/commit/29e94ddb3930e3d7b54afb3753a6a40d6ef57898.diff

LOG: [MC][SVE] Fix data operand for instruction alias of `st1d`.

The version of `st1d` that operates with vector plus immediate
addressing mode uses the alias `st1d { .d }, , [.d]` for
rendering `st1d { .d }, , [.d, #0]`. The disassembler was
generating `.s` instead of `.d>`.

Differential Revision: https://reviews.llvm.org/D86633

Added: 


Modified: 
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/MC/AArch64/SVE/st1b.s
llvm/test/MC/AArch64/SVE/st1d.s
llvm/test/MC/AArch64/SVE/st1h.s
llvm/test/MC/AArch64/SVE/st1w.s

Removed: 




diff  --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td 
b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index c56a65b9e212..e86f2a6ebde4 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -5416,7 +5416,7 @@ multiclass sve_mem_64b_sst_vi_ptrs opc, string 
asm,
   def : InstAlias(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, 
ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, 
ZPR64:$Zn, 0), 1>;
+  (!cast(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, 
ZPR64:$Zn, 0), 1>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), 
imm_ty:$index, vt),
 (!cast(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, 
imm_ty:$index)>;

diff  --git a/llvm/test/MC/AArch64/SVE/st1b.s b/llvm/test/MC/AArch64/SVE/st1b.s
index a6f766bdfd7c..40b830709ead 100644
--- a/llvm/test/MC/AArch64/SVE/st1b.s
+++ b/llvm/test/MC/AArch64/SVE/st1b.s
@@ -168,3 +168,27 @@ st1b{ z31.d }, p7, [z31.d, #31]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 5f e4 
+
+st1b{ z0.s }, p7, [z0.s, #0]
+// CHECK-INST: st1b{ z0.s }, p7, [z0.s]
+// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc 60 e4 
+
+st1b{ z0.s }, p7, [z0.s]
+// CHECK-INST: st1b{ z0.s }, p7, [z0.s]
+// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc 60 e4 
+
+st1b{ z0.d }, p7, [z0.d, #0]
+// CHECK-INST: st1b{ z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc 40 e4 
+
+st1b{ z0.d }, p7, [z0.d]
+// CHECK-INST: st1b{ z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc 40 e4 

diff  --git a/llvm/test/MC/AArch64/SVE/st1d.s b/llvm/test/MC/AArch64/SVE/st1d.s
index ba4a0e5be114..a5a19e772b52 100644
--- a/llvm/test/MC/AArch64/SVE/st1d.s
+++ b/llvm/test/MC/AArch64/SVE/st1d.s
@@ -78,3 +78,15 @@ st1d{ z31.d }, p7, [z31.d, #248]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf df e5 
+
+st1d{ z0.d }, p7, [z0.d, #0]
+// CHECK-INST: st1d{ z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc c0 e5 
+
+st1d{ z0.d }, p7, [z0.d]
+// CHECK-INST: st1d{ z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc c0 e5 

diff  --git a/llvm/test/MC/AArch64/SVE/st1h.s b/llvm/test/MC/AArch64/SVE/st1h.s
index cd6c20d83482..fe22c52bb9be 100644
--- a/llvm/test/MC/AArch64/SVE/st1h.s
+++ b/llvm/test/MC/AArch64/SVE/st1h.s
@@ -168,3 +168,27 @@ st1h{ z31.d }, p7, [z31.d, #62]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf df e4 
+
+st1h{ z0.s }, p7, [z0.s, #0]
+// CHECK-INST: st1h{ z0.s }, p7, [z0.s]
+// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc e0 e4 
+
+st1h{ z0.s }, p7, [z0.s]
+// CHECK-INST: st1h{ z0.s }, p7, [z0.s]
+// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc e0 e4 
+
+st1h{ z0.d }, p7, [z0.d, #0]
+// CHECK-INST: st1h{ z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc c0 e4 
+
+st1h{ z0.d }, p7, [z0.d]
+// CHECK-INST: st1h{ z0.d }, p7, [z0.d]
+// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 bc c0 e4 

diff  --git a/llvm/test/MC/AArch64/SVE/st1w.s b/llvm/test/MC/AArch64/SVE/st1w.s
index e20194f5747e..5bbcd2e1ea0f 100644
--- a/llvm/test/MC/AArch64/SVE/st1w.s
+++ b/llvm/test/MC/AArch64/SVE/st1w.s
@@ -138,3 +138,27 @@ st1w{ z31.

[llvm-branch-commits] [clang] e592dde - [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`.

2020-11-25 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-11-25T10:16:43Z
New Revision: e592dde6889b5119eb2794a30aca57c3760cab67

URL: 
https://github.com/llvm/llvm-project/commit/e592dde6889b5119eb2794a30aca57c3760cab67
DIFF: 
https://github.com/llvm/llvm-project/commit/e592dde6889b5119eb2794a30aca57c3760cab67.diff

LOG: [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`.

The macro is emitted when wargeting SVE code generation with the additional 
command line option `-msve-vector-bits=`.

The behavior implied by the macro is described in sections "3.7.3.3. Behavior 
specific to SVE vectors" of the SVE ACLE (Version 00bet6) that can be found at 
https://developer.arm.com/documentation/100987/latest

Reviewed By: rengolin, rsandifo-arm

Differential Revision: https://reviews.llvm.org/D90956

Added: 
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp

Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/test/Preprocessor/aarch64-target-features.c

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index 8e0fc5fa621e..37f0212b7001 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -377,8 +377,10 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions 
&Opts,
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
 
-  if (Opts.ArmSveVectorBits)
+  if (Opts.ArmSveVectorBits) {
 Builder.defineMacro("__ARM_FEATURE_SVE_BITS", 
Twine(Opts.ArmSveVectorBits));
+Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS");
+  }
 }
 
 ArrayRef AArch64TargetInfo::getTargetBuiltins() const {

diff  --git 
a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c 
b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
new file mode 100644
index ..fed7708c6893
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
@@ -0,0 +1,117 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s 
-msve-vector-bits=128  | FileCheck %s -D#VBITS=128  --check-prefixes=CHECK128
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s 
-msve-vector-bits=256  | FileCheck %s -D#VBITS=256  
--check-prefixes=CHECK,CHECK256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s 
-msve-vector-bits=512  | FileCheck %s -D#VBITS=512  
--check-prefixes=CHECK,CHECK512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s 
-msve-vector-bits=1024 | FileCheck %s -D#VBITS=1024 
--check-prefixes=CHECK,CHECK1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s 
-msve-vector-bits=2048 | FileCheck %s -D#VBITS=2048 
--check-prefixes=CHECK,CHECK2048
+// REQUIRES: aarch64-registered-target
+
+// Examples taken from section "3.7.3.3 Behavior specific to SVE
+// vectors" of the SVE ACLE (Version 00bet6) that can be found at
+// https://developer.arm.com/documentation/100987/latest
+//
+// Example has been expanded to work with mutiple values of
+// -msve-vector-bits.
+
+#include 
+
+// Page 27, item 1
+#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS
+// CHECK256-LABEL: @x256 = local_unnamed_addr global <4 x i64> , align 16
+typedef svint64_t vec256 __attribute__((arm_sve_vector_bits(256)));
+vec256 x256 = {0, 1, 2, 3};
+#endif
+
+#if __ARM_FEATURE_SVE_BITS == 512 && __ARM_FEATURE_SVE_VECTOR_OPERATORS
+// CHECK512-LABEL: @x512 = local_unnamed_addr global <8 x i64> , align 16
+typedef svint64_t vec512 __attribute__((arm_sve_vector_bits(512)));
+vec512 x512 = {0, 1, 2, 3, 3 , 2 , 1, 0};
+#endif
+
+#if __ARM_FEATURE_SVE_BITS == 1024 && __ARM_FEATURE_SVE_VECTOR_OPERATORS
+// CHECK1024-LABEL: @x1024 = local_unnamed_addr global <16 x i64> , align 16
+typedef svint64_t vec1024 __attribute__((arm_sve_vector_bits(1024)));
+vec1024 x1024 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0};
+#endif
+
+#if __ARM_FEATURE_SVE_BITS == 2048 && __ARM_FEATURE_SVE_VECTOR_OPERATORS
+// CHECK2048-LABEL: @x2048 = local_unnamed_addr global <32 x i64> , align 16
+typedef svint64_t vec2048 __attribute__((arm_sve_vector_bits(2048)));
+vec2048 x2048 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0,
+ 0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0};
+#endif
+
+// Page 27, item 2. We can not change the ABI of existing vector
+// t

[llvm-branch-commits] [llvm] 8e0148d - [AllocaInst] Update `getAllocationSizeInBits` to return `TypeSize`.

2020-11-27 Thread Francesco Petrogalli via llvm-branch-commits 

Author: Francesco Petrogalli
Date: 2020-11-27T16:39:10Z
New Revision: 8e0148dff703dd1ff12cc143482274233a8dacf3

URL: 
https://github.com/llvm/llvm-project/commit/8e0148dff703dd1ff12cc143482274233a8dacf3
DIFF: 
https://github.com/llvm/llvm-project/commit/8e0148dff703dd1ff12cc143482274233a8dacf3.diff

LOG: [AllocaInst] Update `getAllocationSizeInBits` to return `TypeSize`.

Reviewed By: peterwaller-arm, sdesmalen

Differential Revision: https://reviews.llvm.org/D92020

Added: 


Modified: 
llvm/include/llvm/IR/Instructions.h
llvm/lib/IR/Instructions.cpp
llvm/lib/Transforms/Coroutines/CoroFrame.cpp
llvm/unittests/IR/InstructionsTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/IR/Instructions.h 
b/llvm/include/llvm/IR/Instructions.h
index ea1a60d52c87..eb855972256b 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -106,7 +106,7 @@ class AllocaInst : public UnaryInstruction {
 
   /// Get allocation size in bits. Returns None if size can't be determined,
   /// e.g. in case of a VLA.
-  Optional getAllocationSizeInBits(const DataLayout &DL) const;
+  Optional getAllocationSizeInBits(const DataLayout &DL) const;
 
   /// Return the type that is being allocated by the instruction.
   Type *getAllocatedType() const { return AllocatedType; }

diff  --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index ee667cfc42e8..10427b22d5d7 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -49,13 +49,14 @@ using namespace llvm;
 //AllocaInst Class
 
//===--===//
 
-Optional
+Optional
 AllocaInst::getAllocationSizeInBits(const DataLayout &DL) const {
-  uint64_t Size = DL.getTypeAllocSizeInBits(getAllocatedType());
+  TypeSize Size = DL.getTypeAllocSizeInBits(getAllocatedType());
   if (isArrayAllocation()) {
 auto *C = dyn_cast(getArraySize());
 if (!C)
   return None;
+assert(!Size.isScalable() && "Array elements cannot have a scalable size");
 Size *= C->getZExtValue();
   }
   return Size;

diff  --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp 
b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 204fb5d8f4c7..1a000c1913c6 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -576,9 +576,10 @@ void FrameTypeBuilder::addFieldForAllocas(const Function 
&F,
 StackLifetimeAnalyzer.getLiveRange(AI2));
   };
   auto GetAllocaSize = [&](const AllocaInfo &A) {
-Optional RetSize = A.Alloca->getAllocationSizeInBits(DL);
-assert(RetSize && "We can't handle scalable type now.\n");
-return RetSize.getValue();
+Optional RetSize = A.Alloca->getAllocationSizeInBits(DL);
+assert(RetSize && "Variable Length Arrays (VLA) are not supported.\n");
+assert(!RetSize->isScalable() && "Scalable vectors are not yet supported");
+return RetSize->getFixedSize();
   };
   // Put larger allocas in the front. So the larger allocas have higher
   // priority to merge, which can save more space potentially. Also each

diff  --git a/llvm/unittests/IR/InstructionsTest.cpp 
b/llvm/unittests/IR/InstructionsTest.cpp
index 93801b84e73f..dfd292ff60bb 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -1400,5 +1400,45 @@ TEST(InstructionsTest, BranchWeightOverflow) {
   ASSERT_EQ(ProfWeight, UINT32_MAX);
 }
 
+TEST(InstructionsTest, AllocaInst) {
+  LLVMContext Ctx;
+  std::unique_ptr M = parseIR(Ctx, R"(
+  %T = type { i64, [3 x i32]}
+  define void @f(i32 %n) {
+  entry:
+%A = alloca i32, i32 1
+%B = alloca i32, i32 4
+%C = alloca i32, i32 %n
+%D = alloca <8 x double>
+%E = alloca 
+%F = alloca [2 x half]
+%G = alloca [2 x [3 x i128]]
+%H = alloca %T
+ret void
+  }
+)");
+  const DataLayout &DL = M->getDataLayout();
+  ASSERT_TRUE(M);
+  Function *Fun = cast(M->getNamedValue("f"));
+  BasicBlock &BB = Fun->front();
+  auto It = BB.begin();
+  AllocaInst &A = cast(*It++);
+  AllocaInst &B = cast(*It++);
+  AllocaInst &C = cast(*It++);
+  AllocaInst &D = cast(*It++);
+  AllocaInst &E = cast(*It++);
+  AllocaInst &F = cast(*It++);
+  AllocaInst &G = cast(*It++);
+  AllocaInst &H = cast(*It++);
+  EXPECT_EQ(A.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
+  EXPECT_EQ(B.getAllocationSizeInBits(DL), TypeSize::getFixed(128));
+  EXPECT_FALSE(C.getAllocationSizeInBits(DL));
+  EXPECT_EQ(D.getAllocationSizeInBits(DL), TypeSize::getFixed(512));
+  EXPECT_EQ(E.getAllocationSizeInBits(DL), TypeSize::getScalable(512));
+  EXPECT_EQ(F.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
+  EXPECT_EQ(G.getAllocationSizeInBits(DL), TypeSize::getFixed(768));
+  EXPECT_EQ(H.getAllocationSizeInBits(DL), TypeSize::getFixed(