[llvm-branch-commits] [llvm] d8f22c7 - [SchedModels] Return earlier removed checks
Author: Evgeny Leviant
Date: 2020-11-25T12:07:35+03:00
New Revision: d8f22c77699fe8483cdd80e0936d68875ead5838
URL:
https://github.com/llvm/llvm-project/commit/d8f22c77699fe8483cdd80e0936d68875ead5838
DIFF:
https://github.com/llvm/llvm-project/commit/d8f22c77699fe8483cdd80e0936d68875ead5838.diff
LOG: [SchedModels] Return earlier removed checks
It is possible that some write resource is variant in model A
and sequence in model B. Such case will trigger assertion in
getAllPredicates function.
Added:
Modified:
llvm/utils/TableGen/CodeGenSchedule.cpp
Removed:
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp
b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 030e16b744a88..abb2420188116 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1456,7 +1456,9 @@ static std::vector
getAllPredicates(ArrayRef Variants,
ArrayRef ProcIndices) {
std::vector Preds;
for (auto &Variant : Variants) {
-assert(Variant.VarOrSeqDef->isSubClassOf("SchedVar"));
+if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar"))
+ continue;
+
if (ProcIndices[0] && Variant.ProcIdx)
if (!llvm::count(ProcIndices, Variant.ProcIdx))
continue;
@@ -1532,9 +1534,11 @@ void PredTransitions::getIntersectingVariants(
" Ensure only one SchedAlias exists per RW.");
}
}
-Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
-if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
- continue;
+if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
+ Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
+ if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
+continue;
+}
if (IntersectingVariants.empty()) {
// The first variant builds on the existing transition.
___
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[llvm-branch-commits] [llvm] 4c419c4 - [TableGen][SchedModels] Get rid of hasVariant. NFC
Author: Evgeny Leviant
Date: 2020-11-27T18:00:02+03:00
New Revision: 4c419c454ad255437331987dbd3ada6070432999
URL:
https://github.com/llvm/llvm-project/commit/4c419c454ad255437331987dbd3ada6070432999
DIFF:
https://github.com/llvm/llvm-project/commit/4c419c454ad255437331987dbd3ada6070432999.diff
LOG: [TableGen][SchedModels] Get rid of hasVariant. NFC
Differential revision: https://reviews.llvm.org/D92026
Added:
Modified:
llvm/utils/TableGen/CodeGenSchedule.cpp
Removed:
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp
b/llvm/utils/TableGen/CodeGenSchedule.cpp
index abb242018811..0851c0f321b8 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1337,11 +1337,11 @@ class PredTransitions {
PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
- void substituteVariantOperand(const SmallVectorImpl &RWSeq,
+ bool substituteVariantOperand(const SmallVectorImpl &RWSeq,
bool IsRead, bool IsForAnyCPU,
unsigned StartIdx);
- void substituteVariants(const PredTransition &Trans);
+ bool substituteVariants(const PredTransition &Trans);
#ifndef NDEBUG
void dump() const;
@@ -1436,22 +1436,6 @@ static bool hasAliasedVariants(const CodeGenSchedRW &RW,
return false;
}
-static bool hasVariant(ArrayRef Transitions,
- CodeGenSchedModels &SchedModels) {
- for (const PredTransition &PTI : Transitions) {
-for (const SmallVectorImpl &WSI : PTI.WriteSequences)
- for (unsigned WI : WSI)
-if (hasAliasedVariants(SchedModels.getSchedWrite(WI), SchedModels))
- return true;
-
-for (const SmallVectorImpl &RSI : PTI.ReadSequences)
- for (unsigned RI : RSI)
-if (hasAliasedVariants(SchedModels.getSchedRead(RI), SchedModels))
- return true;
- }
- return false;
-}
-
static std::vector getAllPredicates(ArrayRef Variants,
ArrayRef ProcIndices) {
std::vector Preds;
@@ -1628,7 +1612,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
// operand. StartIdx is an index into TransVec where partial results
// starts. RWSeq must be applied to all transitions between StartIdx and the
end
// of TransVec.
-void PredTransitions::substituteVariantOperand(
+bool PredTransitions::substituteVariantOperand(
const SmallVectorImpl &RWSeq, bool IsRead, bool IsForAnyCPU,
unsigned StartIdx) {
@@ -1644,6 +1628,7 @@ void PredTransitions::substituteVariantOperand(
return !IntersectingVariants.empty();
};
+ bool Subst = false;
// Visit each original RW within the current sequence.
for (SmallVectorImpl::const_iterator
RWI = RWSeq.begin(), RWE = RWSeq.end(); RWI != RWE; ++RWI) {
@@ -1664,6 +1649,7 @@ void PredTransitions::substituteVariantOperand(
}
HasAliases = true;
WasPushed |= CollectAndAddVariants(TransIdx, SchedRW);
+ Subst |= WasPushed;
}
if (IsRead && IsForAnyCPU && HasAliases && !WasPushed) {
// If we're here this means that in some sched class:
@@ -1678,9 +1664,10 @@ void PredTransitions::substituteVariantOperand(
TransVec.reserve(TransVec.size() + 1);
TransVec.emplace_back(TransVec[StartIdx].PredTerm);
TransVec.back().ReadSequences.emplace_back();
- CollectAndAddVariants(TransVec.size() - 1, SchedRW);
+ Subst |= CollectAndAddVariants(TransVec.size() - 1, SchedRW);
}
}
+ return Subst;
}
// For each variant of a Read/Write in Trans, substitute the sequence of
@@ -1689,10 +1676,11 @@ void PredTransitions::substituteVariantOperand(
// predicates should result in linear growth in the total number variants.
//
// This is one step in a breadth-first search of nested variants.
-void PredTransitions::substituteVariants(const PredTransition &Trans) {
+bool PredTransitions::substituteVariants(const PredTransition &Trans) {
// Build up a set of partial results starting at the back of
// PredTransitions. Remember the first new transition.
unsigned StartIdx = TransVec.size();
+ bool Subst = false;
TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndices);
bool IsForAnyCPU = llvm::count(Trans.ProcIndices, 0);
@@ -1705,7 +1693,8 @@ void PredTransitions::substituteVariants(const
PredTransition &Trans) {
TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
I->WriteSequences.emplace_back();
}
-substituteVariantOperand(*WSI, /*IsRead=*/false, IsForAnyCPU, StartIdx);
+Subst |=
+substituteVariantOperand(*WSI, /*IsRead=*/false, IsForAnyCPU,
StartIdx);
}
// Visit each original read sequence.
for (SmallVectorImpl>::const_iterator
@@ -1716,8 +1705,10 @@ void PredTransitions::substituteVariants(const
PredTransition &Trans) {
TransVec.begin() + StartIdx, E = TransVec.end(); I != E; +
[llvm-branch-commits] [llvm] 112b3cb - [TableGen][SchedModels] Fix read/write variant substitution
Author: Evgeny Leviant
Date: 2020-11-30T11:55:55+03:00
New Revision: 112b3cb6ba49aacd821440d0913f15b32131480e
URL:
https://github.com/llvm/llvm-project/commit/112b3cb6ba49aacd821440d0913f15b32131480e
DIFF:
https://github.com/llvm/llvm-project/commit/112b3cb6ba49aacd821440d0913f15b32131480e.diff
LOG: [TableGen][SchedModels] Fix read/write variant substitution
Patch fixes multiple issues related to expansion of variant sched reads and
writes.
Differential revision: https://reviews.llvm.org/D90844
Added:
llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
Modified:
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/utils/TableGen/CodeGenSchedule.cpp
llvm/utils/TableGen/CodeGenSchedule.h
Removed:
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td
b/llvm/lib/Target/ARM/ARMScheduleA57.td
index be8591935810..0c610a4839f8 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -183,11 +183,6 @@ class A57BranchForm :
// TODO: according to the doc, conditional uses I0/I1, unconditional uses M
// Why more complex instruction uses more simple pipeline?
// May be an error in doc.
-def A57WriteALUsi : SchedWriteVariant<[
- // lsl #2, lsl #1, or lsr #1.
- SchedVar>]>,
- SchedVar>]>
-]>;
def A57WriteALUsr : SchedWriteVariant<[
SchedVar>]>,
SchedVar>]>
@@ -200,7 +195,7 @@ def A57ReadALUsr : SchedReadVariant<[
SchedVar,
SchedVar
]>;
-def : SchedAlias;
+def : SchedAlias>>;
def : SchedAlias;
def : SchedAlias;
def : SchedAlias;
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
new file mode 100644
index ..da8df20e54d7
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
@@ -0,0 +1,34 @@
+# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched
-run-pass=machine-scheduler -debug-only=machine-scheduler %s 2>&1 | FileCheck %s
+
+# CHECK-LABEL: ** MI Scheduling **
+# CHECK: %[[RES:[0-9]+]]:rgpr = t2MLA
+# CHECK-NEXT: # preds left
+# CHECK-NEXT: # succs left
+# CHECK-NEXT: # rdefs left
+# CHECK-NEXT: Latency : 3
+# CHECK-NEXT: Depth
+# CHECK-NEXT: Height
+# CHECK-NEXT: Predecessors:
+# CHECK-NEXT:SU({{.*}}): Data Latency=1 Reg=
+# CHECK-NEXT:SU({{.*}}): Out Latency=
+# CHECK-NEXT:SU({{.*}}): Data Latency=1 Reg=
+# CHECK-NEXT: Successors:
+# CHECK-NEXT:SU([[SMLA_SU:[0-9]+]]): Data Latency=1 Reg=%[[RES]]
+# CHECK-NEXT: Pressure Diff
+# CHECK-NEXT: Single Issue : false;
+# CHECK-NEXT: SU([[SMLA_SU]]): {{.*}} = t2SMLAL %{{[0-9]+}}:rgpr,
%{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr(tied-def 0), %[[RES]]:rgpr(tied-def 1), 14,
$noreg
+
+name:test_smlal_forwarding
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $r1, $r3, $r4, $r5, $r6
+%1:rgpr = COPY $r1
+%3:rgpr = COPY $r3
+%4:rgpr = COPY $r4
+%5:rgpr = COPY $r5
+%6:rgpr = COPY $r6
+%3:rgpr = t2MLA %4:rgpr, %1:rgpr, %4:rgpr, 14, $noreg
+%6:rgpr, %5:rgpr = t2SMLAL %5:rgpr, %6:rgpr, %4:rgpr, %3:rgpr, 14, $noreg
+$r0 = COPY %6:rgpr
+BX_RET 14, $noreg, implicit $r0
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp
b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 0851c0f321b8..fa84199974ff 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1338,8 +1338,7 @@ class PredTransitions {
PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
bool substituteVariantOperand(const SmallVectorImpl &RWSeq,
-bool IsRead, bool IsForAnyCPU,
-unsigned StartIdx);
+bool IsRead, unsigned StartIdx);
bool substituteVariants(const PredTransition &Trans);
@@ -1413,29 +1412,6 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,
return false;
}
-static bool hasAliasedVariants(const CodeGenSchedRW &RW,
- CodeGenSchedModels &SchedModels) {
- if (RW.HasVariants)
-return true;
-
- for (Record *Alias : RW.Aliases) {
-const CodeGenSchedRW &AliasRW =
- SchedModels.getSchedRW(Alias->getValueAsDef("AliasRW"));
-if (AliasRW.HasVariants)
- return true;
-if (AliasRW.IsSequence) {
- IdxVec ExpandedRWs;
- SchedModels.expandRWSequence(AliasRW.Index, ExpandedRWs, AliasRW.IsRead);
- for (unsigned SI : ExpandedRWs) {
-if (hasAliasedVariants(SchedModels.getSchedRW(SI, AliasRW.IsRead),
- SchedModels))
- return true;
- }
-}
- }
- return false;
-}
-
static std::vector getAllPredicates(ArrayRef Variants,
ArrayRef ProcIndices) {
std::vector Preds;
@@ -1613,21 +1589,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
// starts. RWSeq must be applied to all transitions between StartIdx and the
end
// of TransVec
[llvm-branch-commits] [llvm] 1295235 - Fix test case
Author: Evgeny Leviant Date: 2020-11-30T12:35:28+03:00 New Revision: 129523588f2715cb5d2f8852c949b3669a3c1b6b URL: https://github.com/llvm/llvm-project/commit/129523588f2715cb5d2f8852c949b3669a3c1b6b DIFF: https://github.com/llvm/llvm-project/commit/129523588f2715cb5d2f8852c949b3669a3c1b6b.diff LOG: Fix test case Added: Modified: llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir Removed: diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir index da8df20e54d7..03241c48045d 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir @@ -1,4 +1,4 @@ -# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s 2>&1 | FileCheck %s +# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s # CHECK-LABEL: ** MI Scheduling ** # CHECK: %[[RES:[0-9]+]]:rgpr = t2MLA ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 993eaf2 - Recommit [TableGen][SchedModels] Fix read/write variant substitution
Author: Evgeny Leviant
Date: 2020-12-04T21:50:34+03:00
New Revision: 993eaf2d69d8beb97e4695cbd919b927ed1cfe86
URL:
https://github.com/llvm/llvm-project/commit/993eaf2d69d8beb97e4695cbd919b927ed1cfe86
DIFF:
https://github.com/llvm/llvm-project/commit/993eaf2d69d8beb97e4695cbd919b927ed1cfe86.diff
LOG: Recommit [TableGen][SchedModels] Fix read/write variant substitution
Original commit rG112b3cb6ba49 introduced non-determinism in subtarget
generator due to iteration over DenseMap. New patch fixes this changing
ProcModelMapTy from DenseMap to std::map.
Added:
llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
Modified:
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/utils/TableGen/CodeGenSchedule.cpp
llvm/utils/TableGen/CodeGenSchedule.h
Removed:
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td
b/llvm/lib/Target/ARM/ARMScheduleA57.td
index be8591935810..0c610a4839f8 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -183,11 +183,6 @@ class A57BranchForm :
// TODO: according to the doc, conditional uses I0/I1, unconditional uses M
// Why more complex instruction uses more simple pipeline?
// May be an error in doc.
-def A57WriteALUsi : SchedWriteVariant<[
- // lsl #2, lsl #1, or lsr #1.
- SchedVar>]>,
- SchedVar>]>
-]>;
def A57WriteALUsr : SchedWriteVariant<[
SchedVar>]>,
SchedVar>]>
@@ -200,7 +195,7 @@ def A57ReadALUsr : SchedReadVariant<[
SchedVar,
SchedVar
]>;
-def : SchedAlias;
+def : SchedAlias>>;
def : SchedAlias;
def : SchedAlias;
def : SchedAlias;
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
new file mode 100644
index ..03241c48045d
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
@@ -0,0 +1,34 @@
+# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched
-run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 |
FileCheck %s
+
+# CHECK-LABEL: ** MI Scheduling **
+# CHECK: %[[RES:[0-9]+]]:rgpr = t2MLA
+# CHECK-NEXT: # preds left
+# CHECK-NEXT: # succs left
+# CHECK-NEXT: # rdefs left
+# CHECK-NEXT: Latency : 3
+# CHECK-NEXT: Depth
+# CHECK-NEXT: Height
+# CHECK-NEXT: Predecessors:
+# CHECK-NEXT:SU({{.*}}): Data Latency=1 Reg=
+# CHECK-NEXT:SU({{.*}}): Out Latency=
+# CHECK-NEXT:SU({{.*}}): Data Latency=1 Reg=
+# CHECK-NEXT: Successors:
+# CHECK-NEXT:SU([[SMLA_SU:[0-9]+]]): Data Latency=1 Reg=%[[RES]]
+# CHECK-NEXT: Pressure Diff
+# CHECK-NEXT: Single Issue : false;
+# CHECK-NEXT: SU([[SMLA_SU]]): {{.*}} = t2SMLAL %{{[0-9]+}}:rgpr,
%{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr(tied-def 0), %[[RES]]:rgpr(tied-def 1), 14,
$noreg
+
+name:test_smlal_forwarding
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $r1, $r3, $r4, $r5, $r6
+%1:rgpr = COPY $r1
+%3:rgpr = COPY $r3
+%4:rgpr = COPY $r4
+%5:rgpr = COPY $r5
+%6:rgpr = COPY $r6
+%3:rgpr = t2MLA %4:rgpr, %1:rgpr, %4:rgpr, 14, $noreg
+%6:rgpr, %5:rgpr = t2SMLAL %5:rgpr, %6:rgpr, %4:rgpr, %3:rgpr, 14, $noreg
+$r0 = COPY %6:rgpr
+BX_RET 14, $noreg, implicit $r0
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp
b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 82ca35f37e8b..50ee9462d1d1 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -283,7 +283,7 @@ static APInt constructOperandMask(ArrayRef
Indices) {
static void
processSTIPredicate(STIPredicateFunction &Fn,
-const DenseMap &ProcModelMap) {
+const ProcModelMapTy &ProcModelMap) {
DenseMap Opcode2Index;
using OpcodeMapPair = std::pair;
std::vector OpcodeMappings;
@@ -1338,8 +1338,7 @@ class PredTransitions {
PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
bool substituteVariantOperand(const SmallVectorImpl &RWSeq,
-bool IsRead, bool IsForAnyCPU,
-unsigned StartIdx);
+bool IsRead, unsigned StartIdx);
bool substituteVariants(const PredTransition &Trans);
@@ -1413,29 +1412,6 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,
return false;
}
-static bool hasAliasedVariants(const CodeGenSchedRW &RW,
- CodeGenSchedModels &SchedModels) {
- if (RW.HasVariants)
-return true;
-
- for (Record *Alias : RW.Aliases) {
-const CodeGenSchedRW &AliasRW =
-SchedModels.getSchedRW(Alias->getValueAsDef("AliasRW"));
-if (AliasRW.HasVariants)
- return true;
-if (AliasRW.IsSequence) {
- IdxVec ExpandedRWs;
- SchedModels.expandRWSequence(AliasRW.Index, ExpandedRWs, AliasRW.IsRead);
- for (unsigned SI : ExpandedRWs) {
-if (hasAliasedVariants(SchedModels.getSchedRW(SI, AliasRW.IsRead),
- S
[llvm-branch-commits] [llvm] f69936f - Attempt to fix buildbot after rG993eaf2d69d8
Author: Evgeny Leviant Date: 2020-12-04T22:10:36+03:00 New Revision: f69936f52973750d4746624abf9b6607827b08b1 URL: https://github.com/llvm/llvm-project/commit/f69936f52973750d4746624abf9b6607827b08b1 DIFF: https://github.com/llvm/llvm-project/commit/f69936f52973750d4746624abf9b6607827b08b1.diff LOG: Attempt to fix buildbot after rG993eaf2d69d8 Added: Modified: llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir Removed: diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir index 03241c48045d..1b40a0b8effb 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir @@ -1,3 +1,4 @@ +# REQUIRES: asserts # RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s # CHECK-LABEL: ** MI Scheduling ** ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 53401e8 - [TableGen][SchedModels] Simplify the code. NFC
Author: Evgeny Leviant
Date: 2020-12-07T11:53:33+03:00
New Revision: 53401e8e88641941fee0876d234f9a9fc70ef6ce
URL:
https://github.com/llvm/llvm-project/commit/53401e8e88641941fee0876d234f9a9fc70ef6ce
DIFF:
https://github.com/llvm/llvm-project/commit/53401e8e88641941fee0876d234f9a9fc70ef6ce.diff
LOG: [TableGen][SchedModels] Simplify the code. NFC
Differential revision: https://reviews.llvm.org/D92304
Added:
Modified:
llvm/utils/TableGen/CodeGenSchedule.cpp
llvm/utils/TableGen/CodeGenSchedule.h
llvm/utils/TableGen/SubtargetEmitter.cpp
Removed:
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp
b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 50ee9462d1d1..49a7575dce95 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1314,16 +1314,12 @@ struct PredTransition {
SmallVector PredTerm;
SmallVector, 16> WriteSequences;
SmallVector, 16> ReadSequences;
- SmallVector ProcIndices;
+ unsigned ProcIndex = 0;
PredTransition() = default;
- PredTransition(ArrayRef PT) {
+ PredTransition(ArrayRef PT, unsigned ProcId) {
PredTerm.assign(PT.begin(), PT.end());
-ProcIndices.assign(1, 0);
- }
- PredTransition(ArrayRef PT, ArrayRef PIds) {
-PredTerm.assign(PT.begin(), PT.end());
-ProcIndices.assign(PIds.begin(), PIds.end());
+ProcIndex = ProcId;
}
};
@@ -1413,16 +1409,11 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,
}
static std::vector getAllPredicates(ArrayRef Variants,
- ArrayRef ProcIndices) {
+ unsigned ProcId) {
std::vector Preds;
for (auto &Variant : Variants) {
if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar"))
continue;
-
-if (ProcIndices[0] && Variant.ProcIdx)
- if (!llvm::count(ProcIndices, Variant.ProcIdx))
-continue;
-
Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate"));
}
return Preds;
@@ -1444,12 +1435,14 @@ void PredTransitions::getIntersectingVariants(
Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
}
-// Push each variant. Assign TransVecIdx later.
-const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
-for (Record *VarDef : VarDefs)
- Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
-if (VarProcIdx == 0)
- GenericRW = true;
+if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) {
+ // Push each variant. Assign TransVecIdx later.
+ const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
+ for (Record *VarDef : VarDefs)
+Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
+ if (VarProcIdx == 0)
+GenericRW = true;
+}
}
for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
AI != AE; ++AI) {
@@ -1461,6 +1454,17 @@ void PredTransitions::getIntersectingVariants(
Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
}
+if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
+ continue;
+if (!Variants.empty()) {
+ const CodeGenProcModel &PM =
+ *(SchedModels.procModelBegin() + AliasProcIdx);
+ PrintFatalError((*AI)->getLoc(),
+ "Multiple variants defined for processor " +
+ PM.ModelName +
+ " Ensure only one SchedAlias exists per RW.");
+}
+
const CodeGenSchedRW &AliasRW =
SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
@@ -1475,25 +1479,10 @@ void PredTransitions::getIntersectingVariants(
GenericRW = true;
}
std::vector AllPreds =
- getAllPredicates(Variants, TransVec[TransIdx].ProcIndices);
+ getAllPredicates(Variants, TransVec[TransIdx].ProcIndex);
for (TransVariant &Variant : Variants) {
// Don't expand variants if the processor models don't intersect.
// A zero processor index means any processor.
-SmallVectorImpl &ProcIndices = TransVec[TransIdx].ProcIndices;
-if (ProcIndices[0] && Variant.ProcIdx) {
- unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
-Variant.ProcIdx);
- if (!Cnt)
-continue;
- if (Cnt > 1) {
-const CodeGenProcModel &PM =
- *(SchedModels.procModelBegin() + Variant.ProcIdx);
-PrintFatalError(Variant.VarOrSeqDef->getLoc(),
-"Multiple variants defined for processor " +
-PM.ModelName +
-" Ensure only one SchedAlias exists per RW.");
- }
-}
if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = Variant.VarOr
