[llvm-branch-commits] [llvm] 558b3bb - [AMDGPU][MC] Improved errors handling for SDWA operands
Author: Dmitry Preobrazhensky
Date: 2021-01-25T19:02:53+03:00
New Revision: 558b3bbb5b67387c5a29c1eb6548be81c1588adc
URL:
https://github.com/llvm/llvm-project/commit/558b3bbb5b67387c5a29c1eb6548be81c1588adc
DIFF:
https://github.com/llvm/llvm-project/commit/558b3bbb5b67387c5a29c1eb6548be81c1588adc.diff
LOG: [AMDGPU][MC] Improved errors handling for SDWA operands
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D95212
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 5146271befff..035278135cef 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1297,7 +1297,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
parseNamedBit(const char *Name, OperandVector &Operands,
AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
OperandMatchResultTy parseStringWithPrefix(StringRef Prefix,
- StringRef &Value);
+ StringRef &Value,
+ SMLoc &StringLoc);
bool isModifier();
bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken)
const;
@@ -5099,11 +5100,15 @@ static void addOptionalImmOperand(
}
OperandMatchResultTy
-AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) {
+AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,
+ StringRef &Value,
+ SMLoc &StringLoc) {
if (!trySkipId(Prefix, AsmToken::Colon))
return MatchOperand_NoMatch;
- return parseId(Value) ? MatchOperand_Success : MatchOperand_ParseFail;
+ StringLoc = getLoc();
+ return parseId(Value, "expected an identifier") ? MatchOperand_Success
+ : MatchOperand_ParseFail;
}
//===--===//
@@ -7523,7 +7528,8 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
StringRef Prefix,
StringRef Value;
OperandMatchResultTy res;
- res = parseStringWithPrefix(Prefix, Value);
+ SMLoc StringLoc;
+ res = parseStringWithPrefix(Prefix, Value, StringLoc);
if (res != MatchOperand_Success) {
return res;
}
@@ -7540,6 +7546,7 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
StringRef Prefix,
.Default(0x);
if (Int == 0x) {
+Error(StringLoc, "invalid " + Twine(Prefix) + " value");
return MatchOperand_ParseFail;
}
@@ -7555,7 +7562,8 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector
&Operands) {
StringRef Value;
OperandMatchResultTy res;
- res = parseStringWithPrefix("dst_unused", Value);
+ SMLoc StringLoc;
+ res = parseStringWithPrefix("dst_unused", Value, StringLoc);
if (res != MatchOperand_Success) {
return res;
}
@@ -7568,6 +7576,7 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector
&Operands) {
.Default(0x);
if (Int == 0x) {
+Error(StringLoc, "invalid dst_unused value");
return MatchOperand_ParseFail;
}
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index cb4f9ae91153..b0cf97921daa 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -483,6 +483,24 @@ v_mov_b32_sdwa v1, sext(u)
// CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u)
// CHECK-NEXT:{{^}}^
+//==
+// expected an identifier
+
+v_mov_b32_sdwa v5, v1 dst_sel:
+// CHECK: error: expected an identifier
+// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:
+// CHECK-NEXT:{{^}} ^
+
+v_mov_b32_sdwa v5, v1 dst_sel:0
+// CHECK: error: expected an identifier
+// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:0
+// CHECK-NEXT:{{^}} ^
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
+// CHECK: error: expected an identifier
+// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
+// CHECK-NEXT:{{^}} ^
+
//==
// expected an opening square bracket
@@ -623,6 +641,22 @@ s_waitcnt vmcnt(0) & expcnt(0) x(0)
// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0)
// CHECK-NEXT:{{^}} ^
+//==
+// invalid dst_sel value
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD
+// CHECK: error: invalid dst_sel
[llvm-branch-commits] [llvm] 911961c - [AMDGPU][MC][GFX10] Improved dpp8 errors handling
Author: Dmitry Preobrazhensky
Date: 2021-01-18T15:02:31+03:00
New Revision: 911961c9c1320ba985ac06c1866b33a5a247a94e
URL:
https://github.com/llvm/llvm-project/commit/911961c9c1320ba985ac06c1866b33a5a247a94e
DIFF:
https://github.com/llvm/llvm-project/commit/911961c9c1320ba985ac06c1866b33a5a247a94e.diff
LOG: [AMDGPU][MC][GFX10] Improved dpp8 errors handling
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D94756
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index e73cf2f55ef2..99e7c0e2d6b8 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7260,25 +7260,23 @@ OperandMatchResultTy
AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
int64_t Sels[8];
- if (!trySkipToken(AsmToken::LBrac))
+ if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))
return MatchOperand_ParseFail;
- if (getParser().parseAbsoluteExpression(Sels[0]))
-return MatchOperand_ParseFail;
- if (0 > Sels[0] || 7 < Sels[0])
-return MatchOperand_ParseFail;
-
- for (size_t i = 1; i < 8; ++i) {
-if (!trySkipToken(AsmToken::Comma))
+ for (size_t i = 0; i < 8; ++i) {
+if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))
return MatchOperand_ParseFail;
+SMLoc Loc = getLoc();
if (getParser().parseAbsoluteExpression(Sels[i]))
return MatchOperand_ParseFail;
-if (0 > Sels[i] || 7 < Sels[i])
+if (0 > Sels[i] || 7 < Sels[i]) {
+ Error(Loc, "expected a 3-bit value");
return MatchOperand_ParseFail;
+}
}
- if (!trySkipToken(AsmToken::RBrac))
+ if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
return MatchOperand_ParseFail;
unsigned DPP8 = 0;
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index 7f77a0da2a78..ae8e95105c33 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -115,6 +115,19 @@ s_atomic_swap s5, s[2:3], 0x1F
// CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1F
// CHECK-NEXT:{{^}} ^
+//==
+// expected a 3-bit value
+
+v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
+// CHECK: error: expected a 3-bit value
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
+// CHECK-NEXT:{{^}} ^
+
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
+// CHECK: error: expected a 3-bit value
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
+// CHECK-NEXT:{{^}} ^
+
//==
// expected a 5-character mask
@@ -192,6 +205,11 @@ v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
// CHECK-NEXT:{{^}} ^
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
+// CHECK: error: expected a closing square bracket
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
+// CHECK-NEXT:{{^}} ^
+
//==
// expected a colon
@@ -228,6 +246,11 @@ v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
// CHECK-NEXT:{{^}} ^
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
+// CHECK: error: expected a comma
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
+// CHECK-NEXT:{{^}}^
+
//==
// expected a comma or a closing parenthesis
@@ -351,6 +374,11 @@ tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0
format:BUF_NUM_FORMAT_UINT]
// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0
format:BUF_NUM_FORMAT_UINT]
// CHECK-NEXT:{{^}}
^
+v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
+// CHECK: error: expected absolute expression
+// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
+// CHECK-NEXT:{{^}} ^
+
//==
// expected a message name or an absolute expression
@@ -383,6 +411,14 @@ ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
// CHECK-NEXT:{{^}} ^
+//===
[llvm-branch-commits] [llvm] 55c557a - [AMDGPU][MC] Refactored parsing of dpp ctrl
Author: Dmitry Preobrazhensky
Date: 2021-01-18T18:14:19+03:00
New Revision: 55c557a5d25fd0f4db55fc4a406a1ea74594cfad
URL:
https://github.com/llvm/llvm-project/commit/55c557a5d25fd0f4db55fc4a406a1ea74594cfad
DIFF:
https://github.com/llvm/llvm-project/commit/55c557a5d25fd0f4db55fc4a406a1ea74594cfad.diff
LOG: [AMDGPU][MC] Refactored parsing of dpp ctrl
Summary of changes:
- simplified code to improve maintainability;
- replaced lex() with higher level parser functions;
- improved errors handling.
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D94777
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
llvm/test/MC/AMDGPU/regression/bug28538.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 99e7c0e2d6b8..b10ea9ae99b7 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1485,6 +1485,9 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseDim(OperandVector &Operands);
OperandMatchResultTy parseDPP8(OperandVector &Operands);
OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
+ bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
+ int64_t parseDPPCtrlSel(StringRef Ctrl);
+ int64_t parseDPPCtrlPerm();
AMDGPUOperand::Ptr defaultRowMask() const;
AMDGPUOperand::Ptr defaultBankMask() const;
AMDGPUOperand::Ptr defaultBoundCtrl() const;
@@ -4952,7 +4955,7 @@ bool
AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
Error(getLoc(), Msg);
}
while (!trySkipToken(AsmToken::EndOfStatement)) {
-Parser.Lex();
+lex();
}
return true;
}
@@ -7227,7 +7230,7 @@ OperandMatchResultTy
AMDGPUAsmParser::parseDim(OperandVector &Operands) {
if (isToken(AsmToken::Integer)) {
SMLoc Loc = getToken().getEndLoc();
Token = std::string(getTokenStr());
-Parser.Lex();
+lex();
if (getLoc() != Loc)
return MatchOperand_ParseFail;
}
@@ -7243,7 +7246,7 @@ OperandMatchResultTy
AMDGPUAsmParser::parseDim(OperandVector &Operands) {
if (!DimInfo)
return MatchOperand_ParseFail;
- Parser.Lex();
+ lex();
Operands.push_back(AMDGPUOperand::CreateImm(this, DimInfo->Encoding, S,
AMDGPUOperand::ImmTyDim));
@@ -7287,116 +7290,138 @@ OperandMatchResultTy
AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
return MatchOperand_Success;
}
-OperandMatchResultTy
-AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
+bool
+AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,
+const OperandVector &Operands) {
+ if (Ctrl == "row_share" ||
+ Ctrl == "row_xmask")
+return isGFX10Plus();
+
+ if (Ctrl == "wave_shl" ||
+ Ctrl == "wave_shr" ||
+ Ctrl == "wave_rol" ||
+ Ctrl == "wave_ror" ||
+ Ctrl == "row_bcast")
+return isVI() || isGFX9();
+
+ return Ctrl == "row_mirror" ||
+ Ctrl == "row_half_mirror" ||
+ Ctrl == "quad_perm" ||
+ Ctrl == "row_shl" ||
+ Ctrl == "row_shr" ||
+ Ctrl == "row_ror";
+}
+
+int64_t
+AMDGPUAsmParser::parseDPPCtrlPerm() {
+ // quad_perm:[%d,%d,%d,%d]
+
+ if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))
+return -1;
+
+ int64_t Val = 0;
+ for (int i = 0; i < 4; ++i) {
+if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))
+ return -1;
+
+int64_t Temp;
+SMLoc Loc = getLoc();
+if (getParser().parseAbsoluteExpression(Temp))
+ return -1;
+if (Temp < 0 || Temp > 3) {
+ Error(Loc, "expected a 2-bit value");
+ return -1;
+}
+
+Val += (Temp << i * 2);
+ }
+
+ if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
+return -1;
+
+ return Val;
+}
+
+int64_t
+AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {
using namespace AMDGPU::DPP;
- SMLoc S = getLoc();
- StringRef Prefix;
- int64_t Int;
+ // sel:%d
- if (isToken(AsmToken::Identifier)) {
-Prefix = getTokenStr();
+ int64_t Val;
+ SMLoc Loc = getLoc();
+
+ if (getParser().parseAbsoluteExpression(Val))
+return -1;
+
+ struct DppCtrlCheck {
+int64_t Ctrl;
+int Lo;
+int Hi;
+ };
+
+ DppCtrlCheck Check = StringSwitch(Ctrl)
+.Case("wave_shl", {DppCtrl::WAVE_SHL1, 1, 1})
+.Case("wave_rol", {DppCtrl::WAVE_ROL1, 1, 1})
+.Case("wave_shr", {DppCtrl::WAVE_SHR1, 1, 1})
+.Case("wave_ror", {DppCtrl::WAVE_ROR1, 1, 1})
+.Case("row_shl", {DppCtrl::ROW_SHL0,1, 15})
+.Case("row_shr", {DppCtrl::ROW_SHR0,1, 15})
+.Case("row_ror", {DppCtrl::ROW_ROR0,1, 15})
+.Case("row_share", {DppCtrl::RO
[llvm-branch-commits] [llvm] 30b8f55 - Fix for sanitizer issue in 55c557a
Author: Dmitry Preobrazhensky
Date: 2021-01-18T18:39:55+03:00
New Revision: 30b8f55378cc57f7589694ca9bc4212ce7c2f4ec
URL:
https://github.com/llvm/llvm-project/commit/30b8f55378cc57f7589694ca9bc4212ce7c2f4ec
DIFF:
https://github.com/llvm/llvm-project/commit/30b8f55378cc57f7589694ca9bc4212ce7c2f4ec.diff
LOG: Fix for sanitizer issue in 55c557a
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index b10ea9ae99b7..5146271befff 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7370,7 +7370,7 @@ AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {
.Case("row_ror", {DppCtrl::ROW_ROR0,1, 15})
.Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})
.Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})
-.Default({-1});
+.Default({-1, 0, 0});
bool Valid;
if (Check.Ctrl == -1) {
___
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[llvm-branch-commits] [llvm] 6d02d12 - [AMDGPU][MC][NFC] Added more tests for flat_global
Author: Dmitry Preobrazhensky Date: 2020-12-28T23:00:56+03:00 New Revision: 6d02d12e172ac85d750e1abe48a0c24559c63158 URL: https://github.com/llvm/llvm-project/commit/6d02d12e172ac85d750e1abe48a0c24559c63158 DIFF: https://github.com/llvm/llvm-project/commit/6d02d12e172ac85d750e1abe48a0c24559c63158.diff LOG: [AMDGPU][MC][NFC] Added more tests for flat_global Restored tests from 7898803c638497ad32e2d4a189d5597d4eb4506e Added: Modified: llvm/test/MC/AMDGPU/flat-global.s Removed: diff --git a/llvm/test/MC/AMDGPU/flat-global.s b/llvm/test/MC/AMDGPU/flat-global.s index 77092e0b3493..10f152cc2f85 100644 --- a/llvm/test/MC/AMDGPU/flat-global.s +++ b/llvm/test/MC/AMDGPU/flat-global.s @@ -241,6 +241,26 @@ global_atomic_cmpswap v1, v3, v[5:6], s[2:3] glc // GFX9: global_atomic_cmpswap v1, v3, v[5:6], s[2:3] glc ; encoding: [0x00,0x80,0x05,0xdd,0x03,0x05,0x02,0x01] // VI-ERR: error: instruction not supported on this GPU +global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc +// GCN: global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc ; encoding: [0xff,0x9f,0x05,0xdd,0x02,0x04,0x7f,0x01] +// GFX10: global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc ; encoding: [0xff,0x8f,0xc5,0xdc,0x02,0x04,0x7d,0x01] +// VI-ERR: error: instruction not supported on this GPU + +global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc +// GCN: global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc ; encoding: [0xff,0x9f,0x05,0xdd,0x02,0xfe,0x7f,0x01] +// GFX10: global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc ; encoding: [0xff,0x8f,0xc5,0xdc,0x02,0xfe,0x7d,0x01] +// VI-ERR: error: instruction not supported on this GPU + +global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc +// GCN: global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc ; encoding: [0xff,0x9f,0x05,0xdd,0x02,0x04,0x02,0x01] +// GFX10: global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc ; encoding: [0xff,0x8f,0xc5,0xdc,0x02,0x04,0x02,0x01] +// VI-ERR: error: instruction not supported on this GPU + +global_atomic_cmpswap v1, v[2:3], v[4:5], off glc +// GCN: global_atomic_cmpswap v1, v[2:3], v[4:5], off glc ; encoding: [0x00,0x80,0x05,0xdd,0x02,0x04,0x7f,0x01] +// GFX10: global_atomic_cmpswap v1, v[2:3], v[4:5], off glc ; encoding: [0x00,0x80,0xc5,0xdc,0x02,0x04,0x7d,0x01] +// VI-ERR: error: instruction not supported on this GPU + global_atomic_cmpswap_x2 v[5:6], v[7:10], off // GFX10: encoding: [0x00,0x80,0x44,0xdd,0x05,0x07,0x7d,0x00] // GFX9: global_atomic_cmpswap_x2 v[5:6], v[7:10], off ; encoding: [0x00,0x80,0x84,0xdd,0x05,0x07,0x7f,0x00] @@ -256,6 +276,26 @@ global_atomic_cmpswap_x2 v[1:2], v5, v[7:10], s[2:3] glc // GFX9: global_atomic_cmpswap_x2 v[1:2], v5, v[7:10], s[2:3] glc ; encoding: [0x00,0x80,0x85,0xdd,0x05,0x07,0x02,0x01] // VI-ERR: error: instruction not supported on this GPU +global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc +// GCN: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc ; encoding: [0xff,0x9f,0x85,0xdd,0x05,0x07,0x7f,0x01] +// GFX10: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc ; encoding: [0xff,0x8f,0x45,0xdd,0x05,0x07,0x7d,0x01] +// VI-ERR: error: instruction not supported on this GPU + +global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc +// GCN: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc ; encoding: [0xff,0x9f,0x85,0xdd,0x05,0xfc,0x7f,0x01] +// GFX10: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc ; encoding: [0xff,0x8f,0x45,0xdd,0x05,0xfc,0x7d,0x01] +// VI-ERR: error: instruction not supported on this GPU + +global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc +// GCN: global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc ; encoding: [0xff,0x9f,0x85,0xdd,0x05,0xfc,0x02,0x01] +// GFX10: global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc ; encoding: [0xff,0x8f,0x45,0xdd,0x05,0xfc,0x02,0x01] +// VI-ERR: error: instruction not supported on this GPU + +global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc +// GCN: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc ; encoding: [0x00,0x80,0x85,0xdd,0x05,0x07,0x7f,0x01] +// GFX10: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc ; encoding: [0x00,0x80,0x45,0xdd,0x05,0x07,0x7d,0x01] +// VI-ERR: error: instruction not supported on this GPU + global_atomic_swap v[3:4], v5, off // GFX10: encoding: [0x00,0x80,0xc0,0xdc,0x03,0x05,0x7d,0x00] // GFX9: global_atomic_swap v[3:4], v5, off ; encoding: [0x00,0x80,0x00,0xdd,0x03,0x05,0x7f,0x00] ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] a323682 - [AMDGPU][MC][NFC] Lit tests cleanup
Author: Dmitry Preobrazhensky Date: 2020-12-21T20:04:02+03:00 New Revision: a323682dcbfdce5860fa5f0fd87adf04360a URL: https://github.com/llvm/llvm-project/commit/a323682dcbfdce5860fa5f0fd87adf04360a DIFF: https://github.com/llvm/llvm-project/commit/a323682dcbfdce5860fa5f0fd87adf04360a.diff LOG: [AMDGPU][MC][NFC] Lit tests cleanup See bug 48513 Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D93550 Added: Modified: llvm/test/MC/AMDGPU/flat-gfx9.s llvm/test/MC/AMDGPU/flat-global.s llvm/test/MC/AMDGPU/flat.s llvm/test/MC/AMDGPU/fma-mix.s llvm/test/MC/AMDGPU/literal16.s llvm/test/MC/AMDGPU/mad-mix.s llvm/test/MC/AMDGPU/smem.s llvm/test/MC/AMDGPU/vop1-gfx9-err.s llvm/test/MC/AMDGPU/vop1.s llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt Removed: diff --git a/llvm/test/MC/AMDGPU/flat-gfx9.s b/llvm/test/MC/AMDGPU/flat-gfx9.s index 858907ce436e..da1ec062dece 100644 --- a/llvm/test/MC/AMDGPU/flat-gfx9.s +++ b/llvm/test/MC/AMDGPU/flat-gfx9.s @@ -12,7 +12,6 @@ flat_load_dword v1, v[3:4] offset:-1 // VI-ERR: :28: error: flat offset modifier is not supported on this GPU // GFX9-ERR: :28: error: expected a 12-bit unsigned offset -// FIXME: Error on VI in wrong column flat_load_dword v1, v[3:4] offset:4095 // GFX9: flat_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x03,0x00,0x00,0x01] // VI-ERR: :28: error: flat offset modifier is not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/flat-global.s b/llvm/test/MC/AMDGPU/flat-global.s index 91c10ae13723..77092e0b3493 100644 --- a/llvm/test/MC/AMDGPU/flat-global.s +++ b/llvm/test/MC/AMDGPU/flat-global.s @@ -85,7 +85,6 @@ global_load_dwordx4 v[1:4], v[3:4], off dlc // GFX9-ERR: error: failed parsing operand // VI-ERR: error: instruction not supported on this GPU -// FIXME: VI error should be instruction nto supported global_load_dword v1, v[3:4], off offset:0 // GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x7d,0x01] // GFX9: global_load_dword v1, v[3:4], off; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01] diff --git a/llvm/test/MC/AMDGPU/flat.s b/llvm/test/MC/AMDGPU/flat.s index 31dd4f0500f1..f307ae30a759 100644 --- a/llvm/test/MC/AMDGPU/flat.s +++ b/llvm/test/MC/AMDGPU/flat.s @@ -1,12 +1,6 @@ // RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=VI -// FIXME: For missing instruction the error message is: -// error: too few operands for instruction -// It should be: -// error: instruction not supported on this GPU -// - // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error: // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error: // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error: diff --git a/llvm/test/MC/AMDGPU/fma-mix.s b/llvm/test/MC/AMDGPU/fma-mix.s index 6bd293e467f9..f062664bf8c1 100644 --- a/llvm/test/MC/AMDGPU/fma-mix.s +++ b/llvm/test/MC/AMDGPU/fma-mix.s @@ -22,8 +22,6 @@ v_fma_mix_f32 v0, abs(v1), v2, v3 // GFX9-FMAMIX: v_fma_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04] // GFX9-MADMIX-ERR: error: instruction not supported on this GPU -// FIXME: Improve error messages - v_fma_mix_f32 v0, v1, abs(v2), v3 // GFX9-FMAMIX: v_fma_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04] // GFX9-MADMIX-ERR: error: instruction not supported on this GPU @@ -80,8 +78,6 @@ v_fma_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0] // GFX9-FMAMIX: v_fma_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04] // GFX9-MADMIX-ERR: error: instruction not supported on this GPU -// FIXME: Improve error messages - v_fma_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] // GFX9-FMAMIX: v_fma_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04] // GFX9-MADMIX-ERR: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/literal16.s b/llvm/test/MC/AMDGPU/literal16.s index 97d16c374285..2a641d53a9b6 100644 --- a/llvm/test/MC/AMDGPU/literal16.s +++ b/llvm/test/MC/AMDGPU/literal16.s @@ -146,3 +146,4 @@ v_madmk_f16 v1, v2, 64.0, v3 v_add_f16_e32 v1, 64.0, v2 +// VI: v_add_f16_e32 v1, 0x5400, v2 ; encoding: [0xff,0x04,0x02,0x3e,0x00,0x54,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/mad-mix.s b/llvm/test/MC/AMDGPU/mad-mix.s index f1de62b5a548..4b28d03bb828 100644 --- a/llvm/test/MC/AMDGPU/mad-mix.s +++ b/llvm/test/MC/AMDGPU/mad-mix.s @@ -22,8 +22,6 @@ v_mad_mix_f32 v0, abs(v1), v2, v3 // GFX9-MADMIX: v_mad_mix_f32 v0, |
[llvm-branch-commits] [llvm] 8ab5770 - [AMDGPU][MC][NFC] Parser refactoring
Author: Dmitry Preobrazhensky
Date: 2020-12-21T20:21:07+03:00
New Revision: 8ab5770a17fee4c39e23fc52a30057eb689fa578
URL:
https://github.com/llvm/llvm-project/commit/8ab5770a17fee4c39e23fc52a30057eb689fa578
DIFF:
https://github.com/llvm/llvm-project/commit/8ab5770a17fee4c39e23fc52a30057eb689fa578.diff
LOG: [AMDGPU][MC][NFC] Parser refactoring
See bug 48515 (https://bugs.llvm.org/show_bug.cgi?id=48515)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D93548
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 6597b627f0ef..f472e4d7eace 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1434,7 +1434,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool trySkipToken(const AsmToken::TokenKind Kind);
bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);
bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a
string");
- bool parseId(StringRef &Val, const StringRef ErrMsg);
+ bool parseId(StringRef &Val, const StringRef ErrMsg = "");
void peekTokens(MutableArrayRef Tokens);
AsmToken::TokenKind getTokenKind() const;
@@ -4073,9 +4073,8 @@ bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t
&Major,
if (ParseAsAbsoluteExpression(Major))
return TokError("invalid major version");
- if (getLexer().isNot(AsmToken::Comma))
+ if (!trySkipToken(AsmToken::Comma))
return TokError("minor version number required, comma expected");
- Lex();
if (ParseAsAbsoluteExpression(Minor))
return TokError("invalid minor version");
@@ -4178,15 +4177,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
Optional EnableWavefrontSize32;
while (true) {
-while (getLexer().is(AsmToken::EndOfStatement))
- Lex();
-
-if (getLexer().isNot(AsmToken::Identifier))
- return TokError("expected .amdhsa_ directive or .end_amdhsa_kernel");
+while (trySkipToken(AsmToken::EndOfStatement));
-StringRef ID = getTok().getIdentifier();
+StringRef ID;
SMRange IDRange = getTok().getLocRange();
-Lex();
+if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))
+ return true;
if (ID == ".end_amdhsa_kernel")
break;
@@ -4469,32 +4465,23 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
if (ParseDirectiveMajorMinor(Major, Minor))
return true;
- if (getLexer().isNot(AsmToken::Comma))
+ if (!trySkipToken(AsmToken::Comma))
return TokError("stepping version number required, comma expected");
- Lex();
if (ParseAsAbsoluteExpression(Stepping))
return TokError("invalid stepping version");
- if (getLexer().isNot(AsmToken::Comma))
+ if (!trySkipToken(AsmToken::Comma))
return TokError("vendor name required, comma expected");
- Lex();
-
- if (getLexer().isNot(AsmToken::String))
-return TokError("invalid vendor name");
- VendorName = getLexer().getTok().getStringContents();
- Lex();
+ if (!parseString(VendorName, "invalid vendor name"))
+return true;
- if (getLexer().isNot(AsmToken::Comma))
+ if (!trySkipToken(AsmToken::Comma))
return TokError("arch name required, comma expected");
- Lex();
-
- if (getLexer().isNot(AsmToken::String))
-return TokError("invalid arch name");
- ArchName = getLexer().getTok().getStringContents();
- Lex();
+ if (!parseString(ArchName, "invalid arch name"))
+return true;
getTargetStreamer().EmitDirectiveHSACodeObjectISA(Major, Minor, Stepping,
VendorName, ArchName);
@@ -4569,14 +4556,11 @@ bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
while (true) {
// Lex EndOfStatement. This is in a while loop, because lexing a comment
// will set the current token to EndOfStatement.
-while(getLexer().is(AsmToken::EndOfStatement))
- Lex();
-
-if (getLexer().isNot(AsmToken::Identifier))
- return TokError("expected value identifier or .end_amd_kernel_code_t");
+while(trySkipToken(AsmToken::EndOfStatement));
-StringRef ID = getLexer().getTok().getIdentifier();
-Lex();
+StringRef ID;
+if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))
+ return true;
if (ID == ".end_amd_kernel_code_t")
break;
@@ -4678,13 +4662,9 @@ bool AMDGPUAsmParser::ParseToEndDirective(const char
*AssemblerDirectiveBegin,
Lex();
}
-if (getLexer().is(AsmToken::Identifier)) {
- StringRef ID = getLexer().getTok().getIdentifier();
- if (ID == AssemblerDirectiveEnd) {
-Lex();
-FoundEnd = true;
-break;
- }
+if (trySkipId(AssemblerDirectiveEnd)) {
+ FoundEnd = true;
+
[llvm-branch-commits] [llvm] f4f49d9 - [AMDGPU][MC][NFC] Fix for sanitizer error in 8ab5770
Author: Dmitry Preobrazhensky
Date: 2020-12-21T20:42:35+03:00
New Revision: f4f49d9d0d699f3ac32c1037516c9ab17551991e
URL:
https://github.com/llvm/llvm-project/commit/f4f49d9d0d699f3ac32c1037516c9ab17551991e
DIFF:
https://github.com/llvm/llvm-project/commit/f4f49d9d0d699f3ac32c1037516c9ab17551991e.diff
LOG: [AMDGPU][MC][NFC] Fix for sanitizer error in 8ab5770
Corrected to fix sanitizer error introduced by 8ab5770
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index f472e4d7eace..f6b204f2415f 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7285,7 +7285,6 @@ OperandMatchResultTy
AMDGPUAsmParser::parseDim(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
SMLoc S = Parser.getTok().getLoc();
- StringRef Prefix;
if (!isGFX10Plus() || !trySkipId("dpp8", AsmToken::Colon))
return MatchOperand_NoMatch;
___
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[llvm-branch-commits] [llvm] 5b17263 - [AMDGPU][MC][NFC] Parser refactoring
Author: Dmitry Preobrazhensky
Date: 2020-12-28T14:59:49+03:00
New Revision: 5b17263b6b9d25d02581c2e44efa0c4dcad5ecf4
URL:
https://github.com/llvm/llvm-project/commit/5b17263b6b9d25d02581c2e44efa0c4dcad5ecf4
DIFF:
https://github.com/llvm/llvm-project/commit/5b17263b6b9d25d02581c2e44efa0c4dcad5ecf4.diff
LOG: [AMDGPU][MC][NFC] Parser refactoring
See bug 48515 (https://bugs.llvm.org/show_bug.cgi?id=48515)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D93756
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index f6b204f2415f..c04ea4c81032 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2529,11 +2529,11 @@ bool
AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
int64_t OldCount;
if (!Sym->isVariable())
-return !Error(getParser().getTok().getLoc(),
+return !Error(getLoc(),
".amdgcn.next_free_{v,s}gpr symbols must be variable");
if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))
return !Error(
-getParser().getTok().getLoc(),
+getLoc(),
".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");
if (OldCount <= NewMax)
@@ -2544,7 +2544,7 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind
RegKind,
std::unique_ptr
AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
- const auto &Tok = Parser.getTok();
+ const auto &Tok = getToken();
SMLoc StartLoc = Tok.getLoc();
SMLoc EndLoc = Tok.getEndLoc();
RegisterKind RegKind;
@@ -4058,7 +4058,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc
IDLoc, unsigned &Opcode,
bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
int64_t Tmp = -1;
- if (getLexer().isNot(AsmToken::Integer) &&
getLexer().isNot(AsmToken::Identifier)) {
+ if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {
return true;
}
if (getParser().parseAbsoluteExpression(Tmp)) {
@@ -4088,25 +4088,24 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
std::string Target;
- SMLoc TargetStart = getTok().getLoc();
+ SMLoc TargetStart = getLoc();
if (getParser().parseEscapedString(Target))
return true;
- SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
+ SMRange TargetRange = SMRange(TargetStart, getLoc());
std::string ExpectedTarget;
raw_string_ostream ExpectedTargetOS(ExpectedTarget);
IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS);
if (Target != ExpectedTargetOS.str())
-return getParser().Error(TargetRange.Start, "target must match options",
- TargetRange);
+return Error(TargetRange.Start, "target must match options", TargetRange);
getTargetStreamer().EmitDirectiveAMDGCNTarget(Target);
return false;
}
bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
- return getParser().Error(Range.Start, "value out of range", Range);
+ return Error(Range.Start, "value out of range", Range);
}
bool AMDGPUAsmParser::calculateGPRBlocks(
@@ -4191,11 +4190,11 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
return TokError(".amdhsa_ directives cannot be repeated");
Seen.insert(ID);
-SMLoc ValStart = getTok().getLoc();
+SMLoc ValStart = getLoc();
int64_t IVal;
if (getParser().parseAbsoluteExpression(IVal))
return true;
-SMLoc ValEnd = getTok().getLoc();
+SMLoc ValEnd = getLoc();
SMRange ValRange = SMRange(ValStart, ValEnd);
if (IVal < 0)
@@ -4260,8 +4259,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
UserSGPRCount += 1;
} else if (ID == ".amdhsa_wavefront_size32") {
if (IVersion.Major < 10)
-return getParser().Error(IDRange.Start, "directive requires gfx10+",
- IDRange);
+return Error(IDRange.Start, "directive requires gfx10+", IDRange);
EnableWavefrontSize32 = Val;
PARSE_BITS_ENTRY(KD.kernel_code_properties,
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
@@ -4303,15 +4301,13 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
ReserveVCC = Val;
} else if (ID == ".amdhsa_reserve_flat_scratch") {
if (IVersion.Major < 7)
-return getParser().Error(IDRange.Start, "directive requires gfx7+",
- IDRange);
+return Error(IDRange.Start, "directive requires gfx7+", IDRange);
if (!isUInt<1>(Val))
return OutOfRangeError(ValRange);
ReserveFlatScr = Val;
} else if (ID == ".amdhsa_reserve_xnack_mask") {
if (IVersion.Major < 8)
-return getParser().Error(IDRange.Start, "directive requires gfx8+",
-
[llvm-branch-commits] [llvm] 8c25bb3 - [AMDGPU][MC] Improved errors handling for v_interp* operands
Author: Dmitry Preobrazhensky
Date: 2020-12-28T16:15:48+03:00
New Revision: 8c25bb3d0d5e956a3dc3a8d26b2e7ab509d0b72c
URL:
https://github.com/llvm/llvm-project/commit/8c25bb3d0d5e956a3dc3a8d26b2e7ab509d0b72c
DIFF:
https://github.com/llvm/llvm-project/commit/8c25bb3d0d5e956a3dc3a8d26b2e7ab509d0b72c.diff
LOG: [AMDGPU][MC] Improved errors handling for v_interp* operands
See bug 48596 (https://bugs.llvm.org/show_bug.cgi?id=48596)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D93757
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
llvm/test/MC/AMDGPU/vintrp-err.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index c04ea4c81032..ae10b47d2e9b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5831,34 +5831,40 @@ bool AMDGPUOperand::isSendMsg() const {
//===--===//
OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands)
{
- if (!isToken(AsmToken::Identifier))
+ StringRef Str;
+ SMLoc S = getLoc();
+
+ if (!parseId(Str))
return MatchOperand_NoMatch;
- StringRef Str = getTokenStr();
int Slot = StringSwitch(Str)
.Case("p10", 0)
.Case("p20", 1)
.Case("p0", 2)
.Default(-1);
- SMLoc S = getLoc();
- if (Slot == -1)
+ if (Slot == -1) {
+Error(S, "invalid interpolation slot");
return MatchOperand_ParseFail;
+ }
- Parser.Lex();
Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,
AMDGPUOperand::ImmTyInterpSlot));
return MatchOperand_Success;
}
OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands)
{
- if (!isToken(AsmToken::Identifier))
-return MatchOperand_NoMatch;
+ StringRef Str;
+ SMLoc S = getLoc();
- StringRef Str = getTokenStr();
- if (!Str.startswith("attr"))
+ if (!parseId(Str))
return MatchOperand_NoMatch;
+ if (!Str.startswith("attr")) {
+Error(S, "invalid interpolation attribute");
+return MatchOperand_ParseFail;
+ }
+
StringRef Chan = Str.take_back(2);
int AttrChan = StringSwitch(Chan)
.Case(".x", 0)
@@ -5866,19 +5872,21 @@ OperandMatchResultTy
AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
.Case(".z", 2)
.Case(".w", 3)
.Default(-1);
- if (AttrChan == -1)
+ if (AttrChan == -1) {
+Error(S, "invalid or missing interpolation attribute channel");
return MatchOperand_ParseFail;
+ }
Str = Str.drop_back(2).drop_front(4);
uint8_t Attr;
- if (Str.getAsInteger(10, Attr))
+ if (Str.getAsInteger(10, Attr)) {
+Error(S, "invalid or missing interpolation attribute number");
return MatchOperand_ParseFail;
+ }
- SMLoc S = getLoc();
- Parser.Lex();
if (Attr > 63) {
-Error(S, "out of bounds attr");
+Error(S, "out of bounds interpolation attribute number");
return MatchOperand_ParseFail;
}
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index 013dba641001..7f77a0da2a78 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -443,21 +443,6 @@ v_ceil_f16 v0, abs(neg(1))
// CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))
// CHECK-NEXT:{{^}} ^
-v_interp_mov_f32 v11, invalid_param_3, attr0.y
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}v_interp_mov_f32 v11, invalid_param_3, attr0.y
-// CHECK-NEXT:{{^}} ^
-
-v_interp_mov_f32 v8, foo, attr0.x
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, foo, attr0.x
-// CHECK-NEXT:{{^}} ^
-
-v_interp_p2_f32 v0, v1, attr
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr
-// CHECK-NEXT:{{^}}^
-
//==
// first register index should not exceed second index
@@ -588,6 +573,22 @@ v_dot_f32_f16 v0, v1, v2
// CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2
// CHECK-NEXT:{{^}}^
+//==
+// invalid interpolation attribute
+
+v_interp_p2_f32 v0, v1, att
+// CHECK: error: invalid interpolation attribute
+// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att
+// CHECK-NEXT:{{^}}^
+
+//==
+// invalid interpolation slot
+
+v_interp_mov_f32 v8, p1, attr0.x
+// CHECK: error: invalid interpolation slot
+// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x
+// CHECK-NEXT:{{^}} ^
+
//===
[llvm-branch-commits] [llvm] ce44bf2 - [AMDGPU][MC] Improved diagnostic messages
Author: Dmitry Preobrazhensky
Date: 2020-11-23T16:15:05+03:00
New Revision: ce44bf2cf229c179948b97639587c92c3f2e8b19
URL:
https://github.com/llvm/llvm-project/commit/ce44bf2cf229c179948b97639587c92c3f2e8b19
DIFF:
https://github.com/llvm/llvm-project/commit/ce44bf2cf229c179948b97639587c92c3f2e8b19.diff
LOG: [AMDGPU][MC] Improved diagnostic messages
See bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D91794
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/gfx10_err_pos.s
llvm/test/MC/AMDGPU/gfx908_err_pos.s
llvm/test/MC/AMDGPU/gfx9_err_pos.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index fa5e05ae8801..4f05ba5ab576 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1396,8 +1396,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSOPLiteral(const MCInst &Inst) const;
- bool validateConstantBusLimitations(const MCInst &Inst);
- bool validateEarlyClobberLimitations(const MCInst &Inst);
+ bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector
&Operands);
+ bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector
&Operands);
bool validateIntClampSupported(const MCInst &Inst);
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
@@ -1410,7 +1410,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateOpSel(const MCInst &Inst);
bool validateVccOperand(unsigned Reg) const;
bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands);
- bool validateMAIAccWrite(const MCInst &Inst);
+ bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
bool validateDivScale(const MCInst &Inst);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
const SMLoc &IDLoc);
@@ -3062,9 +3062,12 @@ bool AMDGPUAsmParser::usesConstantBus(const MCInst
&Inst, unsigned OpIdx) {
}
}
-bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) {
+bool
+AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst,
+const OperandVector &Operands)
{
const unsigned Opcode = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opcode);
+ unsigned LastSGPR = AMDGPU::NoRegister;
unsigned ConstantBusUseCount = 0;
unsigned NumLiterals = 0;
unsigned LiteralSize;
@@ -3098,15 +3101,15 @@ bool
AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) {
const MCOperand &MO = Inst.getOperand(OpIdx);
if (usesConstantBus(Inst, OpIdx)) {
if (MO.isReg()) {
- const unsigned Reg = mc2PseudoReg(MO.getReg());
+ LastSGPR = mc2PseudoReg(MO.getReg());
// Pairs of registers with a partial intersections like these
// s0, s[0:1]
// flat_scratch_lo, flat_scratch
// flat_scratch_lo, flat_scratch_hi
// are theoretically valid but they are disabled anyway.
// Note that this code mimics SIInstrInfo::verifyInstruction
- if (!SGPRsUsed.count(Reg)) {
-SGPRsUsed.insert(Reg);
+ if (!SGPRsUsed.count(LastSGPR)) {
+SGPRsUsed.insert(LastSGPR);
++ConstantBusUseCount;
}
} else { // Expression or a literal
@@ -3138,10 +3141,19 @@ bool
AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) {
}
ConstantBusUseCount += NumLiterals;
- return ConstantBusUseCount <= getConstantBusLimit(Opcode);
+ if (ConstantBusUseCount <= getConstantBusLimit(Opcode))
+return true;
+
+ SMLoc LitLoc = getLitLoc(Operands);
+ SMLoc RegLoc = getRegLoc(LastSGPR, Operands);
+ SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;
+ Error(Loc, "invalid operand (violates constant bus restrictions)");
+ return false;
}
-bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) {
+bool
+AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst,
+ const OperandVector
&Operands) {
const unsigned Opcode = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opcode);
@@ -3170,6 +3182,8 @@ bool
AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) {
if (Src.isReg()) {
const unsigned SrcReg = mc2PseudoReg(Src.getReg());
if (isRegIntersect(DstReg, SrcReg, TRI)) {
+Error(getReg
[llvm-branch-commits] [llvm] e97dd11 - [AMDGPU][MC] Corrected error position for invalid MOVREL src
Author: Dmitry Preobrazhensky
Date: 2020-12-05T13:23:14+03:00
New Revision: e97dd119776129e888ab3c02e1394b58b709fd1f
URL:
https://github.com/llvm/llvm-project/commit/e97dd119776129e888ab3c02e1394b58b709fd1f
DIFF:
https://github.com/llvm/llvm-project/commit/e97dd119776129e888ab3c02e1394b58b709fd1f.diff
LOG: [AMDGPU][MC] Corrected error position for invalid MOVREL src
See bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D92084
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/exp-err.s
llvm/test/MC/AMDGPU/gfx10_err_pos.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index d1e5fe59e910..8128bbcaa65d 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1401,7 +1401,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateIntClampSupported(const MCInst &Inst);
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
- bool validateMovrels(const MCInst &Inst);
+ bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
bool validateMIMGDataSize(const MCInst &Inst);
bool validateMIMGAddrSize(const MCInst &Inst);
bool validateMIMGD16(const MCInst &Inst);
@@ -3337,7 +3337,8 @@ static bool IsMovrelsSDWAOpcode(const unsigned Opcode)
// movrels* opcodes should only allow VGPRS as src0.
// This is specified in .td description for vop1/vop3,
// but sdwa is handled
diff erently. See isSDWAOperand.
-bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) {
+bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,
+ const OperandVector &Operands) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -3348,13 +3349,20 @@ bool AMDGPUAsmParser::validateMovrels(const MCInst
&Inst) {
const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
assert(Src0Idx != -1);
+ SMLoc ErrLoc;
const MCOperand &Src0 = Inst.getOperand(Src0Idx);
- if (!Src0.isReg())
-return false;
+ if (Src0.isReg()) {
+auto Reg = mc2PseudoReg(Src0.getReg());
+const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+if (!isSGPR(Reg, TRI))
+ return true;
+ErrLoc = getRegLoc(Reg, Operands);
+ } else {
+ErrLoc = getConstLoc(Operands);
+ }
- auto Reg = Src0.getReg();
- const MCRegisterInfo *TRI = getContext().getRegisterInfo();
- return !isSGPR(mc2PseudoReg(Reg), TRI);
+ Error(ErrLoc, "source operand must be a VGPR");
+ return false;
}
bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
@@ -3899,8 +3907,7 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst
&Inst,
"invalid image_gather dmask: only one bit must be set");
return false;
}
- if (!validateMovrels(Inst)) {
-Error(IDLoc, "source operand must be a VGPR");
+ if (!validateMovrels(Inst, Operands)) {
return false;
}
if (!validateFlatOffset(Inst, Operands)) {
@@ -4033,7 +4040,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc
IDLoc, unsigned &Opcode,
SMLoc ErrorLoc = IDLoc;
if (ErrorInfo != ~0ULL) {
if (ErrorInfo >= Operands.size()) {
-return Error(IDLoc, "too few operands for instruction");
+return Error(getLoc(), "too few operands for instruction");
}
ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
if (ErrorLoc == SMLoc())
diff --git a/llvm/test/MC/AMDGPU/exp-err.s b/llvm/test/MC/AMDGPU/exp-err.s
index ee83bef0c50b..b650a78627db 100644
--- a/llvm/test/MC/AMDGPU/exp-err.s
+++ b/llvm/test/MC/AMDGPU/exp-err.s
@@ -53,7 +53,7 @@ exp , v3, v2, v1, v0
// GCN: :5: error: unknown token in expression
exp
-// GCN: :1: error: too few operands for instruction
+// GCN: :4: error: too few operands for instruction
exp mrt0 s0, v0, v0, v0
// GCN: 10: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index c1aa9f860b5c..f7c9bd914f46 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -938,7 +938,17 @@ s_mov_b64 s[10:11], [s2,s1]
v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
// CHECK: error: source operand must be a VGPR
// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}} ^
+
+v_movrels_b32_sdwa v0, s0
+// CHECK: error: source operand must be a VGPR
+// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s0
+// CHECK-NEXT:{{^}} ^
+
+v_movrels_b32_sdwa v0, shared_base
+// CHECK: error: source op
[llvm-branch-commits] [llvm] a0b3a93 - [AMDGPU][MC] Improved diagnostics message for sym/expr operands
Author: Dmitry Preobrazhensky
Date: 2020-12-05T14:05:53+03:00
New Revision: a0b3a9391cd8cfff2ad1741f12e5ed10acc97869
URL:
https://github.com/llvm/llvm-project/commit/a0b3a9391cd8cfff2ad1741f12e5ed10acc97869
DIFF:
https://github.com/llvm/llvm-project/commit/a0b3a9391cd8cfff2ad1741f12e5ed10acc97869.diff
LOG: [AMDGPU][MC] Improved diagnostics message for sym/expr operands
See bug 48295 (https://bugs.llvm.org/show_bug.cgi?id=48295)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D92088
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/ds-err.s
llvm/test/MC/AMDGPU/gfx10_err_pos.s
llvm/test/MC/AMDGPU/sopk-err.s
llvm/test/MC/AMDGPU/sopp-err.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 8128bbcaa65d..45774935287b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1438,7 +1438,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
void peekTokens(MutableArrayRef Tokens);
AsmToken::TokenKind getTokenKind() const;
- bool parseExpr(int64_t &Imm);
+ bool parseExpr(int64_t &Imm, StringRef Expected = "");
bool parseExpr(OperandVector &Operands);
StringRef getTokenStr() const;
AsmToken peekToken();
@@ -5683,8 +5683,8 @@ AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,
if (isToken(AsmToken::Identifier) &&
(HwReg.Id = getHwregId(getTokenStr())) >= 0) {
HwReg.IsSymbolic = true;
-lex(); // skip message name
- } else if (!parseExpr(HwReg.Id)) {
+lex(); // skip register name
+ } else if (!parseExpr(HwReg.Id, "a register name")) {
return false;
}
@@ -5753,7 +5753,7 @@ AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
} else {
return MatchOperand_ParseFail;
}
- } else if (parseExpr(ImmVal)) {
+ } else if (parseExpr(ImmVal, "a hwreg macro")) {
if (ImmVal < 0 || !isUInt<16>(ImmVal)) {
Error(Loc, "invalid immediate: only 16-bit values are legal");
return MatchOperand_ParseFail;
@@ -5784,7 +5784,7 @@ AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,
if (isToken(AsmToken::Identifier) && (Msg.Id = getMsgId(getTokenStr())) >=
0) {
Msg.IsSymbolic = true;
lex(); // skip message name
- } else if (!parseExpr(Msg.Id)) {
+ } else if (!parseExpr(Msg.Id, "a message name")) {
return false;
}
@@ -5794,7 +5794,7 @@ AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,
if (isToken(AsmToken::Identifier) &&
(Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {
lex(); // skip operation name
-} else if (!parseExpr(Op.Id)) {
+} else if (!parseExpr(Op.Id, "an operation name")) {
return false;
}
@@ -5864,7 +5864,7 @@ AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
} else {
return MatchOperand_ParseFail;
}
- } else if (parseExpr(ImmVal)) {
+ } else if (parseExpr(ImmVal, "a sendmsg macro")) {
if (ImmVal < 0 || !isUInt<16>(ImmVal)) {
Error(Loc, "invalid immediate: only 16-bit values are legal");
return MatchOperand_ParseFail;
@@ -6082,8 +6082,23 @@ AMDGPUAsmParser::skipToken(const AsmToken::TokenKind
Kind,
}
bool
-AMDGPUAsmParser::parseExpr(int64_t &Imm) {
- return !getParser().parseAbsoluteExpression(Imm);
+AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {
+ SMLoc S = getLoc();
+
+ const MCExpr *Expr;
+ if (Parser.parseExpression(Expr))
+return false;
+
+ if (Expr->evaluateAsAbsolute(Imm))
+return true;
+
+ if (Expected.empty()) {
+Error(S, "expected absolute expression");
+ } else {
+Error(S, Twine("expected ", Expected) +
+ Twine(" or an absolute expression"));
+ }
+ return false;
}
bool
@@ -6400,7 +6415,7 @@ AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
SMLoc OffsetLoc = Parser.getTok().getLoc();
- if (!parseExpr(Imm)) {
+ if (!parseExpr(Imm, "a swizzle macro")) {
return false;
}
if (!isUInt<16>(Imm)) {
diff --git a/llvm/test/MC/AMDGPU/ds-err.s b/llvm/test/MC/AMDGPU/ds-err.s
index 507bcbc1c4da..5d0a7463544a 100644
--- a/llvm/test/MC/AMDGPU/ds-err.s
+++ b/llvm/test/MC/AMDGPU/ds-err.s
@@ -46,7 +46,7 @@ ds_swizzle_b32 v8, v2 offset:
// CHECK: error: expected a colon
ds_swizzle_b32 v8, v2 offset-
-// CHECK: error: expected absolute expression
+// CHECK: error: expected a swizzle macro or an absolute expression
ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3)
// CHECK: error: expected a swizzle mode
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index f7c9bd914f46..8d0c3694b285 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -331,26 +331,6 @@ ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
//===
