[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Reduce TOC usage by merging internal and private global data (PR #101224)
@@ -28,6 +28,10 @@ struct GlobalMergeOptions {
bool MergeConst = false;
/// Whether we should merge global variables that have external linkage.
bool MergeExternal = true;
+ /// Whether we should merge global variables that have private linkage.
+ bool MergePrivateGlobals = false;
chenzheng1030 wrote:
+1
Like the internal global variables, private global variables should always be
merged and should not be guarded under an option. You've already done this in
https://github.com/llvm/llvm-project/pull/101222 :)
https://github.com/llvm/llvm-project/pull/101224
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[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)
https://github.com/chenzheng1030 approved this pull request. LGTM once the formatting comment from Kai is resolved https://github.com/llvm/llvm-project/pull/101226 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628) (PR #101498)
https://github.com/chenzheng1030 approved this pull request. LGTM. Thanks for making the fix. https://github.com/llvm/llvm-project/pull/101498 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)
@@ -500,7 +500,10 @@ void PPCPassConfig::addIRPasses() {
}
bool PPCPassConfig::addPreISel() {
- if (EnableGlobalMerge)
+ if ((EnableGlobalMerge.getNumOccurrences() > 0)
+ ? EnableGlobalMerge
+ : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))
chenzheng1030 wrote:
Keep the check for `EnableGlobalMerge.getNumOccurrences()` looks correct to me
: )
https://github.com/llvm/llvm-project/pull/101226
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[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Reduce TOC usage by merging internal and private global data (PR #101224)
https://github.com/chenzheng1030 approved this pull request. LGTM. Thanks very much for enabling this pass on PPC. https://github.com/llvm/llvm-project/pull/101224 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098) (PR #86375)
https://github.com/chenzheng1030 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/86375 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [PPCMergeStringPool] Avoid replacing constant with instruction (#88846) (PR #91557)
https://github.com/chenzheng1030 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [PPCMergeStringPool] Only replace constant once (#92996) (PR #93442)
https://github.com/chenzheng1030 approved this pull request. cherry-pick LGTM https://github.com/llvm/llvm-project/pull/93442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [PowerPC] Respect endianness when bitcasting to fp128 (#95931) (PR #105623)
https://github.com/chenzheng1030 approved this pull request. LGTM. ( cherry pick is requested by myself :) ) https://github.com/llvm/llvm-project/pull/105623 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [PowerPC] Fix mask for __st[d/w/h/b]cx builtins (#104453) (PR #106085)
https://github.com/chenzheng1030 approved this pull request. Thanks very much again for fixing the bug. LGTM https://github.com/llvm/llvm-project/pull/106085 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 0ed4cf4 - [PowerPC] support register pressure reduction in machine combiner.
Author: Chen Zheng
Date: 2021-01-24T21:28:21-05:00
New Revision: 0ed4cf4bf3b65e54d3ccb9a3bf1505efbd1b864c
URL:
https://github.com/llvm/llvm-project/commit/0ed4cf4bf3b65e54d3ccb9a3bf1505efbd1b864c
DIFF:
https://github.com/llvm/llvm-project/commit/0ed4cf4bf3b65e54d3ccb9a3bf1505efbd1b864c.diff
LOG: [PowerPC] support register pressure reduction in machine combiner.
Reassociating some patterns to generate more fma instructions to
reduce register pressure.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D92071
Added:
llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
Modified:
llvm/include/llvm/CodeGen/MachineCombinerPattern.h
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
Removed:
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index e9f52fb064e1..ac0cc70744d1 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -29,6 +29,11 @@ enum class MachineCombinerPattern {
REASSOC_XY_AMM_BMM,
REASSOC_XMM_AMM_BMM,
+ // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
+ // reduce register pressure.
+ REASSOC_XY_BCA,
+ REASSOC_XY_BAC,
+
// These are multiply-add patterns matched by the AArch64 machine combiner.
MULADDW_OP1,
MULADDW_OP2,
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp
b/llvm/lib/CodeGen/MachineCombiner.cpp
index 878912a6032b..e2b6cfe55c16 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -279,6 +279,9 @@ static CombinerObjective
getCombinerObjective(MachineCombinerPattern P) {
case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
return CombinerObjective::MustReduceDepth;
+ case MachineCombinerPattern::REASSOC_XY_BCA:
+ case MachineCombinerPattern::REASSOC_XY_BAC:
+return CombinerObjective::MustReduceRegisterPressure;
default:
return CombinerObjective::Default;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 75a498b807cd..9e3c6c569bd7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -21,12 +21,15 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
@@ -73,6 +76,14 @@ static cl::opt
UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
cl::desc("Use the old (incorrect) instruction latency calculation"));
+static cl::opt
+FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
+cl::desc("register pressure factor for the transformations."));
+
+static cl::opt EnableFMARegPressureReduction(
+"ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
+cl::desc("enable register pressure reduce in machine combiner pass."));
+
// Pin the vtable to this file.
void PPCInstrInfo::anchor() {}
@@ -278,21 +289,23 @@ bool PPCInstrInfo::isAssociativeAndCommutative(const
MachineInstr &Inst) const {
#define InfoArrayIdxFMULInst 2
#define InfoArrayIdxAddOpIdx 3
#define InfoArrayIdxMULOpIdx 4
+#define InfoArrayIdxFSubInst 5
// Array keeps info for FMA instructions:
// Index 0(InfoArrayIdxFMAInst): FMA instruction;
-// Index 1(InfoArrayIdxFAddInst): ADD instruction assoaicted with FMA;
-// Index 2(InfoArrayIdxFMULInst): MUL instruction assoaicted with FMA;
+// Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA;
+// Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA;
// Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands;
// Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands;
-//second MUL operand index is plus 1.
-static const uint16_t FMAOpIdxInfo[][5] = {
+//second MUL operand index is plus 1;
+// Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA.
+static const uint16_t FMAOpIdxInfo[][6] = {
// FIXME: Add more FMA instructions like XSNMADDADP and so on.
-{PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2},
-{PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2},
-{PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2},
-
[llvm-branch-commits] [llvm] de6cd53 - [DebugInfo][NFC] add a new DIE type to represent label + offset.
Author: Chen Zheng
Date: 2021-01-14T07:03:38-05:00
New Revision: de6cd53343c4ed37926c18edbad04aeec06f6ec1
URL:
https://github.com/llvm/llvm-project/commit/de6cd53343c4ed37926c18edbad04aeec06f6ec1
DIFF:
https://github.com/llvm/llvm-project/commit/de6cd53343c4ed37926c18edbad04aeec06f6ec1.diff
LOG: [DebugInfo][NFC] add a new DIE type to represent label + offset.
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/include/llvm/CodeGen/DIE.h
llvm/include/llvm/CodeGen/DIEValue.def
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/AsmPrinter/DIE.cpp
llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 76486b0b48ce..a8a31b83d01c 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -580,7 +580,7 @@ class AsmPrinter : public MachineFunctionPass {
/// Emit something like ".long Label+Offset" where the size in bytes of the
/// directive is specified by Size and Label specifies the label. This
/// implicitly uses .set if it is available.
- void emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
+ void emitLabelPlusOffset(const MCSymbol *Label, int64_t Offset,
unsigned Size, bool IsSectionRelative = false)
const;
/// Emit something like ".long Label" where the size in bytes of the
directive
diff --git a/llvm/include/llvm/CodeGen/DIE.h b/llvm/include/llvm/CodeGen/DIE.h
index 3efef6ec0acd..634ac2815926 100644
--- a/llvm/include/llvm/CodeGen/DIE.h
+++ b/llvm/include/llvm/CodeGen/DIE.h
@@ -266,6 +266,22 @@ class DIEDelta {
void print(raw_ostream &O) const;
};
+//======//
+/// A simple label plus offset DIE.
+///
+class DIELabelPlusOffset {
+ const MCSymbol *Label;
+ int64_t Offset;
+
+public:
+ DIELabelPlusOffset(const MCSymbol *L, int64_t O) : Label(L), Offset(O) {}
+
+ void emitValue(const AsmPrinter *AP, dwarf::Form Form) const;
+ unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
+
+ void print(raw_ostream &O) const;
+};
+
//======//
/// A container for string pool string values.
///
@@ -370,7 +386,8 @@ class DIEValue {
/// should be stored by reference instead of by value.
using ValTy = AlignedCharArrayUnion;
+ DIELoc *, DIELocList, DIEBaseTypeRef *,
+ DIELabelPlusOffset *>;
static_assert(sizeof(ValTy) <= sizeof(uint64_t) ||
sizeof(ValTy) <= sizeof(void *),
diff --git a/llvm/include/llvm/CodeGen/DIEValue.def
b/llvm/include/llvm/CodeGen/DIEValue.def
index 92afeb3868b4..9091f8d06c3b 100644
--- a/llvm/include/llvm/CodeGen/DIEValue.def
+++ b/llvm/include/llvm/CodeGen/DIEValue.def
@@ -41,6 +41,7 @@ HANDLE_DIEVALUE_LARGE(Block)
HANDLE_DIEVALUE_LARGE(Loc)
HANDLE_DIEVALUE_SMALL(LocList)
HANDLE_DIEVALUE_LARGE(InlineString)
+HANDLE_DIEVALUE_LARGE(LabelPlusOffset)
#undef HANDLE_DIEVALUE
#undef HANDLE_DIEVALUE_SMALL
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 85754bf29d0c..89a01e4e1a57 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2319,7 +2319,7 @@ void AsmPrinter::emitLabelDifference(const MCSymbol *Hi,
const MCSymbol *Lo,
/// EmitLabelPlusOffset - Emit something like ".long Label+Offset"
/// where the size in bytes of the directive is specified by Size and Label
/// specifies the label. This implicitly uses .set if it is available.
-void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
+void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, int64_t Offset,
unsigned Size,
bool IsSectionRelative) const {
if (MAI->needsDwarfSectionOffsetDirective() && IsSectionRelative) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
index 39b0b027c765..2ca586c713ab 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
@@ -564,6 +564,36 @@ void DIEDelta::print(raw_ostream &O) const {
O << "Del: " << LabelHi->getName() << "-" << LabelLo->getName();
}
+//===--===//
+// DIELabelPlusOffset Implementation
+//===--===//
+
+/// EmitValue - Emit lable plus offset value.
+///
+void DIELabelPlusOffset::emitValue(const AsmPrinter *AP, dwarf::Form Form)
const {
+ AP->emitLabelPlusOffset(Label, Offse
[llvm-branch-commits] [llvm] 6744490 - [debug-info] NFC - add isa<> support for MCStreamer
Author: Chen Zheng
Date: 2021-01-25T02:55:35-05:00
New Revision: 67444901ed2ae692dcf9971708362df2463be975
URL:
https://github.com/llvm/llvm-project/commit/67444901ed2ae692dcf9971708362df2463be975
DIFF:
https://github.com/llvm/llvm-project/commit/67444901ed2ae692dcf9971708362df2463be975.diff
LOG: [debug-info] NFC - add isa<> support for MCStreamer
Added:
llvm/include/llvm/MC/MCAsmStreamer.h
Modified:
llvm/include/llvm/MC/MCObjectStreamer.h
llvm/include/llvm/MC/MCStreamer.h
llvm/lib/MC/MCAsmStreamer.cpp
llvm/lib/MC/MCNullStreamer.cpp
llvm/lib/Object/RecordStreamer.h
Removed:
diff --git a/llvm/include/llvm/MC/MCAsmStreamer.h
b/llvm/include/llvm/MC/MCAsmStreamer.h
new file mode 100644
index ..5b2f407841e5
--- /dev/null
+++ b/llvm/include/llvm/MC/MCAsmStreamer.h
@@ -0,0 +1,374 @@
+//===- MCObjectStreamer.h - MCStreamer Object File Interface *- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_MC_MCASMSTREAMER_H
+#define LLVM_MC_MCASMSTREAMER_H
+
+#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCRegister.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/Format.h"
+#include "llvm/Support/FormattedStream.h"
+
+using namespace llvm;
+
+namespace llvm {
+
+class MCAsmStreamer final : public MCStreamer {
+ std::unique_ptr OSOwner;
+ formatted_raw_ostream &OS;
+ const MCAsmInfo *MAI;
+ std::unique_ptr InstPrinter;
+ std::unique_ptr Assembler;
+
+ SmallString<128> ExplicitCommentToEmit;
+ SmallString<128> CommentToEmit;
+ raw_svector_ostream CommentStream;
+ raw_null_ostream NullStream;
+
+ unsigned IsVerboseAsm : 1;
+ unsigned ShowInst : 1;
+ unsigned UseDwarfDirectory : 1;
+
+ void EmitRegisterName(int64_t Register);
+ void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
+ void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;
+
+public:
+ MCAsmStreamer(MCContext &Context, std::unique_ptr os,
+bool isVerboseAsm, bool useDwarfDirectory,
+MCInstPrinter *printer, std::unique_ptr emitter,
+std::unique_ptr asmbackend, bool showInst)
+ : MCStreamer(Context), OSOwner(std::move(os)), OS(*OSOwner),
+MAI(Context.getAsmInfo()), InstPrinter(printer),
+Assembler(std::make_unique(
+Context, std::move(asmbackend), std::move(emitter),
+(asmbackend) ? asmbackend->createObjectWriter(NullStream)
+ : nullptr)),
+CommentStream(CommentToEmit), IsVerboseAsm(isVerboseAsm),
+ShowInst(showInst), UseDwarfDirectory(useDwarfDirectory) {
+assert(InstPrinter);
+if (IsVerboseAsm)
+InstPrinter->setCommentStream(CommentStream);
+if (Assembler->getBackendPtr())
+ setAllowAutoPadding(Assembler->getBackend().allowAutoPadding());
+
+Context.setUseNamesOnTempLabels(true);
+ }
+
+ MCAssembler &getAssembler() { return *Assembler; }
+ MCAssembler *getAssemblerPtr() override { return nullptr; }
+
+ inline void EmitEOL() {
+// Dump Explicit Comments here.
+emitExplicitComments();
+// If we don't have any comments, just emit a \n.
+if (!IsVerboseAsm) {
+ OS << '\n';
+ return;
+}
+EmitCommentsAndEOL();
+ }
+
+ uint32_t getStreamerKind() const override { return StreamerKindAsm; }
+ static bool classof(const MCStreamer *S) {
+return S->getStreamerKind() == StreamerKindAsm;
+ }
+
+ void emitSyntaxDirective() override;
+
+ void EmitCommentsAndEOL();
+
+ /// Return true if this streamer supports verbose assembly at all.
+ bool isVerboseAsm() const override { return IsVerboseAsm; }
+
+ /// Do we support EmitRawText?
+ bool hasRawTextSupport() const override { return true; }
+
+ /// Add a comment that can be emitted to the generated .s file to make the
+ /// output of the compiler more readable. This only affects the MCAsmStreamer
+ /// and only when verbose assembly output is enabled.
+ void AddComment(const Twine &T, bool EOL = true) override;
+
+ /// Add a comment showing the encoding of an instruction.
+ void AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &);
+
+ /// Return a raw_ostream that comments can be written to.
+
[llvm-branch-commits] [llvm] 4fda9ab - [AIX DWARF] support aix dwarf for 32-bit assembly.
Author: Chen Zheng
Date: 2021-01-25T07:01:54-05:00
New Revision: 4fda9ab7444d93fa12e830975230fc4a1fdfe094
URL:
https://github.com/llvm/llvm-project/commit/4fda9ab7444d93fa12e830975230fc4a1fdfe094
DIFF:
https://github.com/llvm/llvm-project/commit/4fda9ab7444d93fa12e830975230fc4a1fdfe094.diff
LOG: [AIX DWARF] support aix dwarf for 32-bit assembly.
Added:
Modified:
llvm/include/llvm/MC/MCAsmInfo.h
llvm/include/llvm/MC/MCAsmStreamer.h
llvm/include/llvm/MC/MCContext.h
llvm/include/llvm/MC/MCDwarf.h
llvm/include/llvm/MC/MCSectionXCOFF.h
llvm/include/llvm/MC/MCStreamer.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/lib/MC/MCAsmInfoXCOFF.cpp
llvm/lib/MC/MCAsmStreamer.cpp
llvm/lib/MC/MCContext.cpp
llvm/lib/MC/MCDwarf.cpp
llvm/lib/MC/MCObjectFileInfo.cpp
llvm/lib/MC/MCSectionXCOFF.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
Removed:
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h
b/llvm/include/llvm/MC/MCAsmInfo.h
index 98e9c2fd3607..3c7d9420d963 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -388,6 +388,14 @@ class MCAsmInfo {
/// absolute
diff erence.
bool DwarfFDESymbolsUseAbsDiff = false;
+ /// True if the target supports generating the DWARF line table through using
+ /// of the .loc/.file directives. Defaults to true.
+ bool UsesDwarfFileAndLocDirectives = true;
+
+ /// True if the target needs dwarf section size in the header of dwarf
section
+ /// (if any) in assembly file. Defaults to true.
+ bool DwarfSectionSizeRequired = true;
+
/// True if dwarf register numbers are printed instead of symbolic register
/// names in .cfi_* directives. Defaults to false.
bool DwarfRegNumForCFI = false;
@@ -667,6 +675,14 @@ class MCAsmInfo {
return SupportsExtendedDwarfLocDirective;
}
+ bool usesDwarfFileAndLocDirectives() const {
+return UsesDwarfFileAndLocDirectives;
+ }
+
+ bool requiredDwarfSectionSize() const {
+return DwarfSectionSizeRequired;
+ }
+
void addInitialFrameState(const MCCFIInstruction &Inst);
const std::vector &getInitialFrameState() const {
diff --git a/llvm/include/llvm/MC/MCAsmStreamer.h
b/llvm/include/llvm/MC/MCAsmStreamer.h
index 5b2f407841e5..3bb845c40b43 100644
--- a/llvm/include/llvm/MC/MCAsmStreamer.h
+++ b/llvm/include/llvm/MC/MCAsmStreamer.h
@@ -367,6 +367,9 @@ class MCAsmStreamer final : public MCStreamer {
void emitRawTextImpl(StringRef String) override;
void finishImpl() override;
+ void emitDwarfAdvanceLineAddr(int64_t LineDelta, const MCSymbol *LastLabel,
+const MCSymbol *Label,
+unsigned PointerSize) override;
};
} // end anonymous namespace.
diff --git a/llvm/include/llvm/MC/MCContext.h
b/llvm/include/llvm/MC/MCContext.h
index 49ab0ce8d6fd..1c31fdfc4165 100644
--- a/llvm/include/llvm/MC/MCContext.h
+++ b/llvm/include/llvm/MC/MCContext.h
@@ -574,7 +574,8 @@ namespace llvm {
XCOFF::StorageMappingClass MappingClass,
XCOFF::SymbolType CSectType, SectionKind K,
bool MultiSymbolsAllowed = false,
-const char *BeginSymName = nullptr);
+const char *BeginSymName = nullptr,
+unsigned SecFlags = 0);
// Create and save a copy of STI and return a reference to the copy.
MCSubtargetInfo &getSubtargetCopy(const MCSubtargetInfo &STI);
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index 70da5f76e766..715035203cbc 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -172,7 +172,7 @@ class MCDwarfLineEntry : public MCDwarfLoc {
// This is called when an instruction is assembled into the specified
// section and if there is information from the last .loc directive that
// has yet to have a line entry made for it is made.
- static void Make(MCObjectStreamer *MCOS, MCSection *Section);
+ static void Make(MCStreamer *MCOS, MCSection *Section);
};
/// Instances of this class represent the line information for a compile
@@ -310,10 +310,10 @@ class MCDwarfLineTable {
public:
// This emits the Dwarf file and the line tables for all Compile Units.
- static void Emit(MCObjectStreamer *MCOS, MCDwarfLineTableParams Params);
+ static void Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params);
// This emits the Dwarf file and the line tables for a given Compile Unit.
- void EmitCU(MCObjectStreamer *MCOS, MCDwarfLineTableParams Params,
+ void EmitCU(MCStreamer *MCOS, MCDwarfLineTableParams Params,
Optional &LineStr) const;
Expected tryGetFile(StringRef &Directory, StringRef &F
[llvm-branch-commits] [llvm] de6cd53 - [DebugInfo][NFC] add a new DIE type to represent label + offset.
Author: Chen Zheng
Date: 2021-01-14T07:03:38-05:00
New Revision: de6cd53343c4ed37926c18edbad04aeec06f6ec1
URL:
https://github.com/llvm/llvm-project/commit/de6cd53343c4ed37926c18edbad04aeec06f6ec1
DIFF:
https://github.com/llvm/llvm-project/commit/de6cd53343c4ed37926c18edbad04aeec06f6ec1.diff
LOG: [DebugInfo][NFC] add a new DIE type to represent label + offset.
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/include/llvm/CodeGen/DIE.h
llvm/include/llvm/CodeGen/DIEValue.def
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/AsmPrinter/DIE.cpp
llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 76486b0b48ce..a8a31b83d01c 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -580,7 +580,7 @@ class AsmPrinter : public MachineFunctionPass {
/// Emit something like ".long Label+Offset" where the size in bytes of the
/// directive is specified by Size and Label specifies the label. This
/// implicitly uses .set if it is available.
- void emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
+ void emitLabelPlusOffset(const MCSymbol *Label, int64_t Offset,
unsigned Size, bool IsSectionRelative = false)
const;
/// Emit something like ".long Label" where the size in bytes of the
directive
diff --git a/llvm/include/llvm/CodeGen/DIE.h b/llvm/include/llvm/CodeGen/DIE.h
index 3efef6ec0acd..634ac2815926 100644
--- a/llvm/include/llvm/CodeGen/DIE.h
+++ b/llvm/include/llvm/CodeGen/DIE.h
@@ -266,6 +266,22 @@ class DIEDelta {
void print(raw_ostream &O) const;
};
+//======//
+/// A simple label plus offset DIE.
+///
+class DIELabelPlusOffset {
+ const MCSymbol *Label;
+ int64_t Offset;
+
+public:
+ DIELabelPlusOffset(const MCSymbol *L, int64_t O) : Label(L), Offset(O) {}
+
+ void emitValue(const AsmPrinter *AP, dwarf::Form Form) const;
+ unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
+
+ void print(raw_ostream &O) const;
+};
+
//======//
/// A container for string pool string values.
///
@@ -370,7 +386,8 @@ class DIEValue {
/// should be stored by reference instead of by value.
using ValTy = AlignedCharArrayUnion;
+ DIELoc *, DIELocList, DIEBaseTypeRef *,
+ DIELabelPlusOffset *>;
static_assert(sizeof(ValTy) <= sizeof(uint64_t) ||
sizeof(ValTy) <= sizeof(void *),
diff --git a/llvm/include/llvm/CodeGen/DIEValue.def
b/llvm/include/llvm/CodeGen/DIEValue.def
index 92afeb3868b4..9091f8d06c3b 100644
--- a/llvm/include/llvm/CodeGen/DIEValue.def
+++ b/llvm/include/llvm/CodeGen/DIEValue.def
@@ -41,6 +41,7 @@ HANDLE_DIEVALUE_LARGE(Block)
HANDLE_DIEVALUE_LARGE(Loc)
HANDLE_DIEVALUE_SMALL(LocList)
HANDLE_DIEVALUE_LARGE(InlineString)
+HANDLE_DIEVALUE_LARGE(LabelPlusOffset)
#undef HANDLE_DIEVALUE
#undef HANDLE_DIEVALUE_SMALL
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 85754bf29d0c..89a01e4e1a57 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2319,7 +2319,7 @@ void AsmPrinter::emitLabelDifference(const MCSymbol *Hi,
const MCSymbol *Lo,
/// EmitLabelPlusOffset - Emit something like ".long Label+Offset"
/// where the size in bytes of the directive is specified by Size and Label
/// specifies the label. This implicitly uses .set if it is available.
-void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
+void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, int64_t Offset,
unsigned Size,
bool IsSectionRelative) const {
if (MAI->needsDwarfSectionOffsetDirective() && IsSectionRelative) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
index 39b0b027c765..2ca586c713ab 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
@@ -564,6 +564,36 @@ void DIEDelta::print(raw_ostream &O) const {
O << "Del: " << LabelHi->getName() << "-" << LabelLo->getName();
}
+//===--===//
+// DIELabelPlusOffset Implementation
+//===--===//
+
+/// EmitValue - Emit lable plus offset value.
+///
+void DIELabelPlusOffset::emitValue(const AsmPrinter *AP, dwarf::Form Form)
const {
+ AP->emitLabelPlusOffset(Label, Offse
[llvm-branch-commits] [llvm] 4fda9ab - [AIX DWARF] support aix dwarf for 32-bit assembly.
Author: Chen Zheng
Date: 2021-01-25T07:01:54-05:00
New Revision: 4fda9ab7444d93fa12e830975230fc4a1fdfe094
URL:
https://github.com/llvm/llvm-project/commit/4fda9ab7444d93fa12e830975230fc4a1fdfe094
DIFF:
https://github.com/llvm/llvm-project/commit/4fda9ab7444d93fa12e830975230fc4a1fdfe094.diff
LOG: [AIX DWARF] support aix dwarf for 32-bit assembly.
Added:
Modified:
llvm/include/llvm/MC/MCAsmInfo.h
llvm/include/llvm/MC/MCAsmStreamer.h
llvm/include/llvm/MC/MCContext.h
llvm/include/llvm/MC/MCDwarf.h
llvm/include/llvm/MC/MCSectionXCOFF.h
llvm/include/llvm/MC/MCStreamer.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/lib/MC/MCAsmInfoXCOFF.cpp
llvm/lib/MC/MCAsmStreamer.cpp
llvm/lib/MC/MCContext.cpp
llvm/lib/MC/MCDwarf.cpp
llvm/lib/MC/MCObjectFileInfo.cpp
llvm/lib/MC/MCSectionXCOFF.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
Removed:
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h
b/llvm/include/llvm/MC/MCAsmInfo.h
index 98e9c2fd3607..3c7d9420d963 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -388,6 +388,14 @@ class MCAsmInfo {
/// absolute
diff erence.
bool DwarfFDESymbolsUseAbsDiff = false;
+ /// True if the target supports generating the DWARF line table through using
+ /// of the .loc/.file directives. Defaults to true.
+ bool UsesDwarfFileAndLocDirectives = true;
+
+ /// True if the target needs dwarf section size in the header of dwarf
section
+ /// (if any) in assembly file. Defaults to true.
+ bool DwarfSectionSizeRequired = true;
+
/// True if dwarf register numbers are printed instead of symbolic register
/// names in .cfi_* directives. Defaults to false.
bool DwarfRegNumForCFI = false;
@@ -667,6 +675,14 @@ class MCAsmInfo {
return SupportsExtendedDwarfLocDirective;
}
+ bool usesDwarfFileAndLocDirectives() const {
+return UsesDwarfFileAndLocDirectives;
+ }
+
+ bool requiredDwarfSectionSize() const {
+return DwarfSectionSizeRequired;
+ }
+
void addInitialFrameState(const MCCFIInstruction &Inst);
const std::vector &getInitialFrameState() const {
diff --git a/llvm/include/llvm/MC/MCAsmStreamer.h
b/llvm/include/llvm/MC/MCAsmStreamer.h
index 5b2f407841e5..3bb845c40b43 100644
--- a/llvm/include/llvm/MC/MCAsmStreamer.h
+++ b/llvm/include/llvm/MC/MCAsmStreamer.h
@@ -367,6 +367,9 @@ class MCAsmStreamer final : public MCStreamer {
void emitRawTextImpl(StringRef String) override;
void finishImpl() override;
+ void emitDwarfAdvanceLineAddr(int64_t LineDelta, const MCSymbol *LastLabel,
+const MCSymbol *Label,
+unsigned PointerSize) override;
};
} // end anonymous namespace.
diff --git a/llvm/include/llvm/MC/MCContext.h
b/llvm/include/llvm/MC/MCContext.h
index 49ab0ce8d6fd..1c31fdfc4165 100644
--- a/llvm/include/llvm/MC/MCContext.h
+++ b/llvm/include/llvm/MC/MCContext.h
@@ -574,7 +574,8 @@ namespace llvm {
XCOFF::StorageMappingClass MappingClass,
XCOFF::SymbolType CSectType, SectionKind K,
bool MultiSymbolsAllowed = false,
-const char *BeginSymName = nullptr);
+const char *BeginSymName = nullptr,
+unsigned SecFlags = 0);
// Create and save a copy of STI and return a reference to the copy.
MCSubtargetInfo &getSubtargetCopy(const MCSubtargetInfo &STI);
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index 70da5f76e766..715035203cbc 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -172,7 +172,7 @@ class MCDwarfLineEntry : public MCDwarfLoc {
// This is called when an instruction is assembled into the specified
// section and if there is information from the last .loc directive that
// has yet to have a line entry made for it is made.
- static void Make(MCObjectStreamer *MCOS, MCSection *Section);
+ static void Make(MCStreamer *MCOS, MCSection *Section);
};
/// Instances of this class represent the line information for a compile
@@ -310,10 +310,10 @@ class MCDwarfLineTable {
public:
// This emits the Dwarf file and the line tables for all Compile Units.
- static void Emit(MCObjectStreamer *MCOS, MCDwarfLineTableParams Params);
+ static void Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params);
// This emits the Dwarf file and the line tables for a given Compile Unit.
- void EmitCU(MCObjectStreamer *MCOS, MCDwarfLineTableParams Params,
+ void EmitCU(MCStreamer *MCOS, MCDwarfLineTableParams Params,
Optional &LineStr) const;
Expected tryGetFile(StringRef &Directory, StringRef &F
[llvm-branch-commits] [llvm] 6744490 - [debug-info] NFC - add isa<> support for MCStreamer
Author: Chen Zheng
Date: 2021-01-25T02:55:35-05:00
New Revision: 67444901ed2ae692dcf9971708362df2463be975
URL:
https://github.com/llvm/llvm-project/commit/67444901ed2ae692dcf9971708362df2463be975
DIFF:
https://github.com/llvm/llvm-project/commit/67444901ed2ae692dcf9971708362df2463be975.diff
LOG: [debug-info] NFC - add isa<> support for MCStreamer
Added:
llvm/include/llvm/MC/MCAsmStreamer.h
Modified:
llvm/include/llvm/MC/MCObjectStreamer.h
llvm/include/llvm/MC/MCStreamer.h
llvm/lib/MC/MCAsmStreamer.cpp
llvm/lib/MC/MCNullStreamer.cpp
llvm/lib/Object/RecordStreamer.h
Removed:
diff --git a/llvm/include/llvm/MC/MCAsmStreamer.h
b/llvm/include/llvm/MC/MCAsmStreamer.h
new file mode 100644
index ..5b2f407841e5
--- /dev/null
+++ b/llvm/include/llvm/MC/MCAsmStreamer.h
@@ -0,0 +1,374 @@
+//===- MCObjectStreamer.h - MCStreamer Object File Interface *- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_MC_MCASMSTREAMER_H
+#define LLVM_MC_MCASMSTREAMER_H
+
+#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCRegister.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/Format.h"
+#include "llvm/Support/FormattedStream.h"
+
+using namespace llvm;
+
+namespace llvm {
+
+class MCAsmStreamer final : public MCStreamer {
+ std::unique_ptr OSOwner;
+ formatted_raw_ostream &OS;
+ const MCAsmInfo *MAI;
+ std::unique_ptr InstPrinter;
+ std::unique_ptr Assembler;
+
+ SmallString<128> ExplicitCommentToEmit;
+ SmallString<128> CommentToEmit;
+ raw_svector_ostream CommentStream;
+ raw_null_ostream NullStream;
+
+ unsigned IsVerboseAsm : 1;
+ unsigned ShowInst : 1;
+ unsigned UseDwarfDirectory : 1;
+
+ void EmitRegisterName(int64_t Register);
+ void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
+ void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;
+
+public:
+ MCAsmStreamer(MCContext &Context, std::unique_ptr os,
+bool isVerboseAsm, bool useDwarfDirectory,
+MCInstPrinter *printer, std::unique_ptr emitter,
+std::unique_ptr asmbackend, bool showInst)
+ : MCStreamer(Context), OSOwner(std::move(os)), OS(*OSOwner),
+MAI(Context.getAsmInfo()), InstPrinter(printer),
+Assembler(std::make_unique(
+Context, std::move(asmbackend), std::move(emitter),
+(asmbackend) ? asmbackend->createObjectWriter(NullStream)
+ : nullptr)),
+CommentStream(CommentToEmit), IsVerboseAsm(isVerboseAsm),
+ShowInst(showInst), UseDwarfDirectory(useDwarfDirectory) {
+assert(InstPrinter);
+if (IsVerboseAsm)
+InstPrinter->setCommentStream(CommentStream);
+if (Assembler->getBackendPtr())
+ setAllowAutoPadding(Assembler->getBackend().allowAutoPadding());
+
+Context.setUseNamesOnTempLabels(true);
+ }
+
+ MCAssembler &getAssembler() { return *Assembler; }
+ MCAssembler *getAssemblerPtr() override { return nullptr; }
+
+ inline void EmitEOL() {
+// Dump Explicit Comments here.
+emitExplicitComments();
+// If we don't have any comments, just emit a \n.
+if (!IsVerboseAsm) {
+ OS << '\n';
+ return;
+}
+EmitCommentsAndEOL();
+ }
+
+ uint32_t getStreamerKind() const override { return StreamerKindAsm; }
+ static bool classof(const MCStreamer *S) {
+return S->getStreamerKind() == StreamerKindAsm;
+ }
+
+ void emitSyntaxDirective() override;
+
+ void EmitCommentsAndEOL();
+
+ /// Return true if this streamer supports verbose assembly at all.
+ bool isVerboseAsm() const override { return IsVerboseAsm; }
+
+ /// Do we support EmitRawText?
+ bool hasRawTextSupport() const override { return true; }
+
+ /// Add a comment that can be emitted to the generated .s file to make the
+ /// output of the compiler more readable. This only affects the MCAsmStreamer
+ /// and only when verbose assembly output is enabled.
+ void AddComment(const Twine &T, bool EOL = true) override;
+
+ /// Add a comment showing the encoding of an instruction.
+ void AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &);
+
+ /// Return a raw_ostream that comments can be written to.
+
[llvm-branch-commits] [clang] 082b2fc - strict-dwarf in backend
Author: Chen Zheng
Date: 2021-04-22T21:28:07-04:00
New Revision: 082b2fc0e5a78bd45840c1faa392354ff856de11
URL:
https://github.com/llvm/llvm-project/commit/082b2fc0e5a78bd45840c1faa392354ff856de11
DIFF:
https://github.com/llvm/llvm-project/commit/082b2fc0e5a78bd45840c1faa392354ff856de11.diff
LOG: strict-dwarf in backend
Added:
llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
Modified:
clang/lib/CodeGen/BackendUtil.cpp
llvm/include/llvm/CodeGen/CommandFlags.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/CommandFlags.cpp
Removed:
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index 7edca6fb30730..a499877bb2a98 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -598,6 +598,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Entry.IgnoreSysRoot ? Entry.Path : HSOpts.Sysroot + Entry.Path);
Options.MCOptions.Argv0 = CodeGenOpts.Argv0;
Options.MCOptions.CommandLineArgs = CodeGenOpts.CommandLineArgs;
+ Options.DebugStrictDwarf = CodeGenOpts.DebugStrictDwarf;
return true;
}
diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h
b/llvm/include/llvm/CodeGen/CommandFlags.h
index e18ee36445363..072df9dce1ee2 100644
--- a/llvm/include/llvm/CodeGen/CommandFlags.h
+++ b/llvm/include/llvm/CodeGen/CommandFlags.h
@@ -140,6 +140,8 @@ bool getForceDwarfFrameSection();
bool getXRayOmitFunctionIndex();
+bool getDebugStrictDwarf();
+
/// Create this object with static storage to register codegen-related command
/// line options.
struct RegisterCodeGenFlags {
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 651dbe163a811..fd82afed14b38 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -141,6 +141,7 @@ namespace llvm {
SupportsDebugEntryValues(false), EnableDebugEntryValues(false),
PseudoProbeForProfiling(false),
ValueTrackingVariableLocations(false),
ForceDwarfFrameSection(false), XRayOmitFunctionIndex(false),
+ DebugStrictDwarf(false),
FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
/// DisableFramePointerElim - This returns true if frame pointer
elimination
@@ -331,6 +332,10 @@ namespace llvm {
/// Emit XRay Function Index section
unsigned XRayOmitFunctionIndex : 1;
+/// When set to true, don't use DWARF extensions in later DWARF versions.
+/// By default, it is set to false.
+unsigned DebugStrictDwarf : 1;
+
/// Stack protector guard offset to use.
unsigned StackProtectorGuardOffset = -1U;
diff --git a/llvm/lib/CodeGen/CommandFlags.cpp
b/llvm/lib/CodeGen/CommandFlags.cpp
index de560559b6fe0..a0c748fdf2de7 100644
--- a/llvm/lib/CodeGen/CommandFlags.cpp
+++ b/llvm/lib/CodeGen/CommandFlags.cpp
@@ -97,6 +97,7 @@ CGOPT(bool, PseudoProbeForProfiling)
CGOPT(bool, ValueTrackingVariableLocations)
CGOPT(bool, ForceDwarfFrameSection)
CGOPT(bool, XRayOmitFunctionIndex)
+CGOPT(bool, DebugStrictDwarf)
codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
#define CGBINDOPT(NAME)
\
@@ -471,6 +472,10 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
cl::init(false));
CGBINDOPT(XRayOmitFunctionIndex);
+ static cl::opt DebugStrictDwarf(
+ "strict-dwarf", cl::desc("use strict dwarf"), cl::init(false));
+ CGBINDOPT(DebugStrictDwarf);
+
#undef CGBINDOPT
mc::RegisterMCTargetOptionsFlags();
@@ -567,6 +572,7 @@ codegen::InitTargetOptionsFromCodeGenFlags(const Triple
&TheTriple) {
Options.ValueTrackingVariableLocations = getValueTrackingVariableLocations();
Options.ForceDwarfFrameSection = getForceDwarfFrameSection();
Options.XRayOmitFunctionIndex = getXRayOmitFunctionIndex();
+ Options.DebugStrictDwarf = getDebugStrictDwarf();
Options.MCOptions = mc::InitMCTargetOptionsFromFlags();
diff --git a/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
b/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
new file mode 100644
index 0..b64fd426e8eab
--- /dev/null
+++ b/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
@@ -0,0 +1,60 @@
+; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN: llvm-dwarfdump -debug-info - | FileCheck %s
+; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -strict-dwarf=true < %s | llvm-dwarfdump -debug-info - | \
+; RUN: FileCheck %s
+
+; FIXME: when -strict-dwarf=true is specified, we should check "STRICT" to tell
+; that with DWARF 4, we should not generate DWARF 5 attribute DW_AT_noreturn
and
+; DW_AT_alignment.
+
+; CHECK: DW_AT_alignment
+; CHECK: DW_AT_noreturn
+; STRICT-NOT: DW_AT_noreturn
+; STRICT-NOT: DW_AT_alignment
+
+@_ZL3var = internal global i32 0, align 16, !dbg !0
+
+; Function Attrs: noinline
[llvm-branch-commits] [llvm] 681d9ec - [Debug-Info] change return type to void for attribute adding functions.
Author: Chen Zheng
Date: 2021-04-22T21:30:22-04:00
New Revision: 681d9ecd727bf5835098a4e5d5a49f823670a6b5
URL:
https://github.com/llvm/llvm-project/commit/681d9ecd727bf5835098a4e5d5a49f823670a6b5
DIFF:
https://github.com/llvm/llvm-project/commit/681d9ecd727bf5835098a4e5d5a49f823670a6b5.diff
LOG: [Debug-Info] change return type to void for attribute adding functions.
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Removed:
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
index 7a28bcb08ba42..40d290ebe47fa 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
@@ -286,11 +286,9 @@ void DwarfUnit::addString(DIE &Die, dwarf::Attribute
Attribute,
DIEString(StringPoolEntry));
}
-DIEValueList::value_iterator DwarfUnit::addLabel(DIEValueList &Die,
- dwarf::Attribute Attribute,
- dwarf::Form Form,
- const MCSymbol *Label) {
- return Die.addValue(DIEValueAllocator, Attribute, Form, DIELabel(Label));
+void DwarfUnit::addLabel(DIEValueList &Die, dwarf::Attribute Attribute,
+ dwarf::Form Form, const MCSymbol *Label) {
+ Die.addValue(DIEValueAllocator, Attribute, Form, DIELabel(Label));
}
void DwarfUnit::addLabel(DIELoc &Die, dwarf::Form Form, const MCSymbol *Label)
{
@@ -1746,20 +1744,18 @@ void DwarfTypeUnit::emitHeader(bool UseOffsets) {
Asm->emitDwarfLengthOrOffset(Ty ? Ty->getOffset() : 0);
}
-DIE::value_iterator
-DwarfUnit::addSectionDelta(DIE &Die, dwarf::Attribute Attribute,
- const MCSymbol *Hi, const MCSymbol *Lo) {
- return Die.addValue(DIEValueAllocator, Attribute,
- DD->getDwarfSectionOffsetForm(),
- new (DIEValueAllocator) DIEDelta(Hi, Lo));
+void DwarfUnit::addSectionDelta(DIE &Die, dwarf::Attribute Attribute,
+const MCSymbol *Hi, const MCSymbol *Lo) {
+ Die.addValue(DIEValueAllocator, Attribute, DD->getDwarfSectionOffsetForm(),
+ new (DIEValueAllocator) DIEDelta(Hi, Lo));
}
-DIE::value_iterator
-DwarfUnit::addSectionLabel(DIE &Die, dwarf::Attribute Attribute,
- const MCSymbol *Label, const MCSymbol *Sec) {
+void DwarfUnit::addSectionLabel(DIE &Die, dwarf::Attribute Attribute,
+const MCSymbol *Label, const MCSymbol *Sec) {
if (Asm->MAI->doesDwarfUseRelocationsAcrossSections())
-return addLabel(Die, Attribute, DD->getDwarfSectionOffsetForm(), Label);
- return addSectionDelta(Die, Attribute, Label, Sec);
+addLabel(Die, Attribute, DD->getDwarfSectionOffsetForm(), Label);
+ else
+addSectionDelta(Die, Attribute, Label, Sec);
}
bool DwarfTypeUnit::isDwoUnit() const {
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
index a1d6008251796..10fd725cb8ae7 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
@@ -147,10 +147,8 @@ class DwarfUnit : public DIEUnit {
void addString(DIE &Die, dwarf::Attribute Attribute, StringRef Str);
/// Add a Dwarf label attribute data and value.
- DIEValueList::value_iterator addLabel(DIEValueList &Die,
-dwarf::Attribute Attribute,
-dwarf::Form Form,
-const MCSymbol *Label);
+ void addLabel(DIEValueList &Die, dwarf::Attribute Attribute, dwarf::Form
Form,
+const MCSymbol *Label);
void addLabel(DIELoc &Die, dwarf::Form Form, const MCSymbol *Label);
@@ -272,13 +270,12 @@ class DwarfUnit : public DIEUnit {
void constructTypeDIE(DIE &Buffer, const DICompositeType *CTy);
/// addSectionDelta - Add a label delta attribute data and value.
- DIE::value_iterator addSectionDelta(DIE &Die, dwarf::Attribute Attribute,
- const MCSymbol *Hi, const MCSymbol *Lo);
+ void addSectionDelta(DIE &Die, dwarf::Attribute Attribute, const MCSymbol
*Hi,
+ const MCSymbol *Lo);
/// Add a Dwarf section label attribute data and value.
- DIE::value_iterator addSectionLabel(DIE &Die, dwarf::Attribute Attribute,
- const MCSymbol *Label,
- const MCSymbol *Sec);
+ void addSectionLabel(DIE &Die, dwarf::Attribute Attribute,
+ const MCSymbol *Label, const MCSymbol *Sec);
/// Get context owner's DIE.
DIE *createTypeDIE(const DICompositeType *Ty);
___
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[llvm-branch-commits] [llvm] b12067b - [Debug-Info] add a wrapper addAttribute for addValue()
Author: Chen Zheng
Date: 2021-04-22T22:55:30-04:00
New Revision: b12067bad7c30c33caf2dd168c126be3303be634
URL:
https://github.com/llvm/llvm-project/commit/b12067bad7c30c33caf2dd168c126be3303be634
DIFF:
https://github.com/llvm/llvm-project/commit/b12067bad7c30c33caf2dd168c126be3303be634.diff
LOG: [Debug-Info] add a wrapper addAttribute for addValue()
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Removed:
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
index ac7a316398441..faa14dca1c3f1 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -83,7 +83,7 @@ void DwarfCompileUnit::addLabelAddress(DIE &Die,
dwarf::Attribute Attribute,
if (!Base || Base == Label) {
unsigned idx = DD->getAddressPool().getIndex(Label);
-Die.addValue(DIEValueAllocator, Attribute,
+addAttribute(Die, Attribute,
DD->getDwarfVersion() >= 5 ? dwarf::DW_FORM_addrx
: dwarf::DW_FORM_GNU_addr_index,
DIEInteger(idx));
@@ -100,7 +100,7 @@ void DwarfCompileUnit::addLabelAddress(DIE &Die,
dwarf::Attribute Attribute,
addPoolOpAddress(*Loc, Label);
addBlock(Die, Attribute, dwarf::DW_FORM_exprloc, Loc);
} else
-Die.addValue(DIEValueAllocator, Attribute,
dwarf::DW_FORM_LLVM_addrx_offset,
+addAttribute(Die, Attribute, dwarf::DW_FORM_LLVM_addrx_offset,
new (DIEValueAllocator) DIEAddrOffset(
DD->getAddressPool().getIndex(Base), Label, Base));
}
@@ -112,11 +112,9 @@ void DwarfCompileUnit::addLocalLabelAddress(DIE &Die,
DD->addArangeLabel(SymbolCU(this, Label));
if (Label)
-Die.addValue(DIEValueAllocator, Attribute, dwarf::DW_FORM_addr,
- DIELabel(Label));
+addAttribute(Die, Attribute, dwarf::DW_FORM_addr, DIELabel(Label));
else
-Die.addValue(DIEValueAllocator, Attribute, dwarf::DW_FORM_addr,
- DIEInteger(0));
+addAttribute(Die, Attribute, dwarf::DW_FORM_addr, DIEInteger(0));
}
unsigned DwarfCompileUnit::getOrCreateSourceID(const DIFile *File) {
@@ -1472,7 +1470,7 @@ void DwarfCompileUnit::addLocationList(DIE &Die,
dwarf::Attribute Attribute,
dwarf::Form Form = (DD->getDwarfVersion() >= 5)
? dwarf::DW_FORM_loclistx
: DD->getDwarfSectionOffsetForm();
- Die.addValue(DIEValueAllocator, Attribute, Form, DIELocList(Index));
+ addAttribute(Die, Attribute, Form, DIELocList(Index));
}
void DwarfCompileUnit::applyVariableAttributes(const DbgVariable &Var,
@@ -1504,7 +1502,7 @@ void DwarfCompileUnit::applyLabelAttributes(const
DbgLabel &Label,
/// Add a Dwarf expression attribute data and value.
void DwarfCompileUnit::addExpr(DIELoc &Die, dwarf::Form Form,
const MCExpr *Expr) {
- Die.addValue(DIEValueAllocator, (dwarf::Attribute)0, Form, DIEExpr(Expr));
+ addAttribute(Die, (dwarf::Attribute)0, Form, DIEExpr(Expr));
}
void DwarfCompileUnit::applySubprogramAttributesToDefinition(
@@ -1538,7 +1536,7 @@ void DwarfCompileUnit::addAddrTableBase() {
}
void DwarfCompileUnit::addBaseTypeRef(DIEValueList &Die, int64_t Idx) {
- Die.addValue(DIEValueAllocator, (dwarf::Attribute)0, dwarf::DW_FORM_udata,
+ addAttribute(Die, (dwarf::Attribute)0, dwarf::DW_FORM_udata,
new (DIEValueAllocator) DIEBaseTypeRef(this, Idx));
}
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
index 40d290ebe47fa..2b171ae3b6e84 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
@@ -219,11 +219,9 @@ void DwarfUnit::insertDIE(DIE *D) {
void DwarfUnit::addFlag(DIE &Die, dwarf::Attribute Attribute) {
if (DD->getDwarfVersion() >= 4)
-Die.addValue(DIEValueAllocator, Attribute, dwarf::DW_FORM_flag_present,
- DIEInteger(1));
+addAttribute(Die, Attribute, dwarf::DW_FORM_flag_present, DIEInteger(1));
else
-Die.addValue(DIEValueAllocator, Attribute, dwarf::DW_FORM_flag,
- DIEInteger(1));
+addAttribute(Die, Attribute, dwarf::DW_FORM_flag, DIEInteger(1));
}
void DwarfUnit::addUInt(DIEValueList &Die, dwarf::Attribute Attribute,
@@ -232,7 +230,7 @@ void DwarfUnit::addUInt(DIEValueList &Die, dwarf::Attribute
Attribute,
Form = DIEInteger::BestForm(false, Integer);
assert(Form != dwarf::DW_FORM_implicit_const &&
"DW_FORM_implicit_const is used only for signed integers");
- Die.addValue(DIEValueAllocator, Attribute, *Form, DIEInteger(Integer));
+ addAttribute(Die, Attribute, *Form, DIEInteger(Integer));
}
void DwarfUnit::addUInt(DIEValueList
[llvm-branch-commits] [llvm] e91eb89 - [Debug-Info] guard attribute generating under strict dwarf.
Author: Chen Zheng
Date: 2021-04-24T21:34:42-04:00
New Revision: e91eb89cc97d077c8bbae2c28749304d005511cd
URL:
https://github.com/llvm/llvm-project/commit/e91eb89cc97d077c8bbae2c28749304d005511cd
DIFF:
https://github.com/llvm/llvm-project/commit/e91eb89cc97d077c8bbae2c28749304d005511cd.diff
LOG: [Debug-Info] guard attribute generating under strict dwarf.
Conflicts:
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
Removed:
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
index aca831a535a19..3a961ab47f6df 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/DIE.h"
+#include "llvm/Target/TargetMachine.h"
#include
namespace llvm {
@@ -79,6 +80,12 @@ class DwarfUnit : public DIEUnit {
template
void addAttribute(DIEValueList &Die, dwarf::Attribute Attribute,
dwarf::Form Form, T &&Value) {
+// For strict DWARF mode, only generate attributes available to current
+// DWARF version.
+if (Attribute != 0 && Asm->TM.Options.DebugStrictDwarf &&
+DD->getDwarfVersion() < dwarf::AttributeVersion(Attribute))
+ return;
+
Die.addValue(DIEValueAllocator,
DIEValue(Attribute, Form, std::forward(Value)));
}
diff --git a/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
b/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
index b64fd426e8eab..27fbfdbcedf42 100644
--- a/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
+++ b/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
@@ -2,16 +2,25 @@
; RUN: llvm-dwarfdump -debug-info - | FileCheck %s
; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -strict-dwarf=true < %s | llvm-dwarfdump -debug-info - | \
-; RUN: FileCheck %s
+; RUN: FileCheck %s -check-prefix=STRICT
-; FIXME: when -strict-dwarf=true is specified, we should check "STRICT" to tell
-; that with DWARF 4, we should not generate DWARF 5 attribute DW_AT_noreturn
and
-; DW_AT_alignment.
+; We also check that with/without -strict-dwarf=true, the location attribute
+; is not changed. The location attribute adding will call DwarfUnit::addUInt()
+; which contains a attribute 0, we want to make sure the strict-dwarf handling
+; is also right for attribute 0.
+; For this case, the location attribute adding is for global variable @_ZL3var
+; and the call chain to addUInt() is:
+; 1: DwarfCompileUnit::addLocationAttribute()
+; 2: DwarfUnit::addOpAddress()
+; 3: DwarfUnit::addUInt()
+; 4: addUInt(Block, (dwarf::Attribute)0, Form, Integer);
; CHECK: DW_AT_alignment
+; CHECK: DW_AT_location (DW_OP_addr 0x0)
; CHECK: DW_AT_noreturn
; STRICT-NOT: DW_AT_noreturn
; STRICT-NOT: DW_AT_alignment
+; STRICT: DW_AT_location (DW_OP_addr 0x0)
@_ZL3var = internal global i32 0, align 16, !dbg !0
___
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[llvm-branch-commits] [clang] 72cc3f7 - DW_TAG_Rvalue_reference
Author: Chen Zheng
Date: 2021-04-24T21:41:22-04:00
New Revision: 72cc3f7159b695f1928b82a4f29935db6eb62b42
URL:
https://github.com/llvm/llvm-project/commit/72cc3f7159b695f1928b82a4f29935db6eb62b42
DIFF:
https://github.com/llvm/llvm-project/commit/72cc3f7159b695f1928b82a4f29935db6eb62b42.diff
LOG: DW_TAG_Rvalue_reference
Added:
Modified:
clang/lib/CodeGen/CGDebugInfo.cpp
clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 290cdbf8c4e34..1aa48034da69f 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -2989,8 +2989,14 @@ llvm::DIType *CGDebugInfo::CreateType(const
LValueReferenceType *Ty,
llvm::DIType *CGDebugInfo::CreateType(const RValueReferenceType *Ty,
llvm::DIFile *Unit) {
- return CreatePointerLikeType(llvm::dwarf::DW_TAG_rvalue_reference_type, Ty,
- Ty->getPointeeType(), Unit);
+ llvm::dwarf::Tag Tag = llvm::dwarf::DW_TAG_rvalue_reference_type;
+ // DW_TAG_rvalue_reference_type was introduced in DWARF 4, in strict DWARF
+ // mode, only generate it when DWARF version is no smaller than 4.
+ if (CGM.getCodeGenOpts().DebugStrictDwarf &&
+ CGM.getCodeGenOpts().DwarfVersion < 4)
+Tag = llvm::dwarf::DW_TAG_reference_type;
+
+ return CreatePointerLikeType(Tag, Ty, Ty->getPointeeType(), Unit);
}
llvm::DIType *CGDebugInfo::CreateType(const MemberPointerType *Ty,
diff --git a/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
b/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
index de0f65ad9a029..45b19705fae2f 100644
--- a/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
+++ b/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
@@ -1,4 +1,8 @@
// RUN: %clang_cc1 -std=c++11 -emit-llvm -debug-info-kind=limited -triple
x86_64-apple-darwin %s -o - | FileCheck %s
+// RUN: %clang_cc1 -std=c++11 -gstrict-dwarf -dwarf-version=4 -emit-llvm
-debug-info-kind=limited \
+// RUN: -triple x86_64-apple-darwin %s -o - | FileCheck %s
+// RUN: %clang_cc1 -std=c++11 -gstrict-dwarf -dwarf-version=3 -emit-llvm
-debug-info-kind=limited \
+// RUN: -triple x86_64-apple-darwin %s -o - | FileCheck %s
--check-prefix=NORVALUE
extern "C" {
extern int printf(const char * format, ...);
@@ -10,3 +14,4 @@ void foo (int &&i)
// CHECK: !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType:
![[INT:[0-9]+]], size: 64)
// CHECK: ![[INT]] = !DIBasicType(name: "int"
+// NORVALUE: !DIDerivedType(tag: DW_TAG_reference_type, baseType:
![[INT:[0-9]+]], size: 64)
___
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[llvm-branch-commits] [llvm] b92a912 - DW_OP_stack_value
Author: Chen Zheng
Date: 2021-04-25T02:59:49-04:00
New Revision: b92a9126259f0e9adeb589d54358d095477e9a35
URL:
https://github.com/llvm/llvm-project/commit/b92a9126259f0e9adeb589d54358d095477e9a35
DIFF:
https://github.com/llvm/llvm-project/commit/b92a9126259f0e9adeb589d54358d095477e9a35.diff
LOG: DW_OP_stack_value
Added:
llvm/test/DebugInfo/PowerPC/strict-dwarf-op-stack-value.ll
Modified:
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
Removed:
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
index 2b171ae3b6e84..99722e7921284 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
@@ -1020,6 +1020,11 @@ void DwarfUnit::constructTemplateValueParameterDIE(
if (ConstantInt *CI = mdconst::dyn_extract(Val))
addConstantValue(ParamDIE, CI, VP->getType());
else if (GlobalValue *GV = mdconst::dyn_extract(Val)) {
+ // We need DW_OP_stack_value to represent the value of the global value.
+ // DW_OP_stack_value was introduced in DWARF 4, in strict dwarf mode, we
+ // should not use this expression if DWARF version is smaller than 4.
+ if (Asm->TM.Options.DebugStrictDwarf && DD->getDwarfVersion() < 4)
+return;
// We cannot describe the location of dllimport'd entities: the
// computation of their address requires loads from the IAT.
if (!GV->hasDLLImportStorageClass()) {
diff --git a/llvm/test/DebugInfo/PowerPC/strict-dwarf-op-stack-value.ll
b/llvm/test/DebugInfo/PowerPC/strict-dwarf-op-stack-value.ll
new file mode 100644
index 0..e60efde6cf458
--- /dev/null
+++ b/llvm/test/DebugInfo/PowerPC/strict-dwarf-op-stack-value.ll
@@ -0,0 +1,100 @@
+; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN: llvm-dwarfdump -debug-info - | FileCheck %s
+; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -strict-dwarf=true < %s | llvm-dwarfdump -debug-info - | \
+; RUN: FileCheck %s -check-prefix=STRICT
+
+; check that DWARF 4 location expression DW_OP_stack_value is not emitted in
+; DWARF 3 at strict dwarf mode.
+
+; CHECK: DW_AT_location (DW_OP_addr 0x0, DW_OP_stack_value)
+; STRICT-NOT: DW_OP_stack_value
+
+; $ cat 1.cpp
+; extern bool cmp();
+;
+; typedef bool comparator_function();
+; template
+; void quicksort(Iterator begin, Iterator end)
+; {
+; }
+; void foo(void)
+; {
+; double a[100];
+; quicksort(a, a + 100);
+; }
+
+
+$_Z9quicksortIPdXadL_Z3cmpvEEEvT_S1_ = comdat any
+
+; Function Attrs: noinline optnone uwtable mustprogress
+define dso_local void @_Z3foov() #0 !dbg !8 {
+entry:
+ %a = alloca [100 x double], align 8
+ call void @llvm.dbg.declare(metadata [100 x double]* %a, metadata !11,
metadata !DIExpression()), !dbg !16
+ %arraydecay = getelementptr inbounds [100 x double], [100 x double]* %a, i64
0, i64 0, !dbg !17
+ %arraydecay1 = getelementptr inbounds [100 x double], [100 x double]* %a,
i64 0, i64 0, !dbg !18
+ %add.ptr = getelementptr inbounds double, double* %arraydecay1, i64 100,
!dbg !19
+ call void @_Z9quicksortIPdXadL_Z3cmpvEEEvT_S1_(double* %arraydecay, double*
%add.ptr), !dbg !20
+ ret void, !dbg !21
+}
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: noinline nounwind optnone uwtable mustprogress
+define linkonce_odr dso_local void
@_Z9quicksortIPdXadL_Z3cmpvEEEvT_S1_(double* %begin, double* %end) #2 comdat
!dbg !22 {
+entry:
+ %begin.addr = alloca double*, align 8
+ %end.addr = alloca double*, align 8
+ store double* %begin, double** %begin.addr, align 8
+ call void @llvm.dbg.declare(metadata double** %begin.addr, metadata !33,
metadata !DIExpression()), !dbg !34
+ store double* %end, double** %end.addr, align 8
+ call void @llvm.dbg.declare(metadata double** %end.addr, metadata !35,
metadata !DIExpression()), !dbg !36
+ ret void, !dbg !37
+}
+
+declare zeroext i1 @_Z3cmpv() #3
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5, !6}
+!llvm.ident = !{!7}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1,
producer: "clang version 13.0.0", isOptimized: false, runtimeVersion: 0,
emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind:
None)
+!1 = !DIFile(filename: "1.cpp", directory: "./")
+!2 = !{}
+!3 = !{i32 7, !"Dwarf Version", i32 3}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !{i32 7, !"uwtable", i32 1}
+!7 = !{!"clang version 13.0.0"}
+!8 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", scope: !1,
file: !1, line: 9, type: !9, scopeLine: 10, flags: DIFlagPrototyped, spFlags:
DISPFlagDefinition, unit: !0, retainedNodes: !2)
+!9 = !DISubroutineType(types: !10)
+!10 = !{null}
+!11 = !DILocalVariable(name: "a", scope: !8, file:
[llvm-branch-commits] [llvm] 93a3592 - file name - directory info
Author: Chen Zheng
Date: 2021-04-26T01:31:23-04:00
New Revision: 93a3592728ac1b55a7dd2a1d6abeeb8f9a54e2b6
URL:
https://github.com/llvm/llvm-project/commit/93a3592728ac1b55a7dd2a1d6abeeb8f9a54e2b6
DIFF:
https://github.com/llvm/llvm-project/commit/93a3592728ac1b55a7dd2a1d6abeeb8f9a54e2b6.diff
LOG: file name - directory info
Added:
llvm/test/CodeGen/PowerPC/aix-filename-absolute-path.ll
llvm/test/CodeGen/PowerPC/aix-filename-relative-path.ll
Modified:
llvm/include/llvm/MC/MCAsmInfo.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/MC/MCAsmInfoXCOFF.cpp
Removed:
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h
b/llvm/include/llvm/MC/MCAsmInfo.h
index 250d219d100e4..b674af072ed55 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -341,6 +341,10 @@ class MCAsmInfo {
/// argument and how it is interpreted. Defaults to NoAlignment.
LCOMM::LCOMMType LCOMMDirectiveAlignmentType = LCOMM::NoAlignment;
+ /// True if the target only has basename for .file directive. False if the
+ /// target also needs the directory along with the basename. Default to true.
+ bool HasBasenameOnlyForFileDirective = true;
+
// True if the target allows .align directives on functions. This is true for
// most targets, so defaults to true.
bool HasFunctionAlignment = true;
@@ -666,6 +670,9 @@ class MCAsmInfo {
return LCOMMDirectiveAlignmentType;
}
+ bool hasBasenameOnlyForFileDirective() const {
+return HasBasenameOnlyForFileDirective;
+ }
bool hasFunctionAlignment() const { return HasFunctionAlignment; }
bool hasDotTypeDotSizeDirective() const { return HasDotTypeDotSizeDirective;
}
bool hasSingleParameterDotFile() const { return HasSingleParameterDotFile; }
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index eb7c7e2797d4e..869d83abd47dc 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -297,8 +297,11 @@ bool AsmPrinter::doInitialization(Module &M) {
// don't, this at least helps the user find where a global came from.
if (MAI->hasSingleParameterDotFile()) {
// .file "foo.c"
-OutStreamer->emitFileDirective(
-llvm::sys::path::filename(M.getSourceFileName()));
+if (MAI->hasBasenameOnlyForFileDirective())
+ OutStreamer->emitFileDirective(
+ llvm::sys::path::filename(M.getSourceFileName()));
+else
+ OutStreamer->emitFileDirective(M.getSourceFileName());
}
GCModuleInfo *MI = getAnalysisIfAvailable();
diff --git a/llvm/lib/MC/MCAsmInfoXCOFF.cpp b/llvm/lib/MC/MCAsmInfoXCOFF.cpp
index a23a71b865b43..f90fc5a8f4983 100644
--- a/llvm/lib/MC/MCAsmInfoXCOFF.cpp
+++ b/llvm/lib/MC/MCAsmInfoXCOFF.cpp
@@ -19,6 +19,7 @@ void MCAsmInfoXCOFF::anchor() {}
MCAsmInfoXCOFF::MCAsmInfoXCOFF() {
IsLittleEndian = false;
HasVisibilityOnlyWithLinkage = true;
+ HasBasenameOnlyForFileDirective = false;
PrivateGlobalPrefix = "L..";
PrivateLabelPrefix = "L..";
SupportsQuotedNames = false;
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-absolute-path.ll
b/llvm/test/CodeGen/PowerPC/aix-filename-absolute-path.ll
new file mode 100644
index 0..d5b6886ebcefe
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-absolute-path.ll
@@ -0,0 +1,8 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff < %s \
+; RUN: | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s \
+; RUN: | FileCheck %s
+
+; CHECK: .file "/absolute/path/to/file"
+
+source_filename = "/absolute/path/to/file"
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-relative-path.ll
b/llvm/test/CodeGen/PowerPC/aix-filename-relative-path.ll
new file mode 100644
index 0..6df85c84d2678
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-relative-path.ll
@@ -0,0 +1,8 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff < %s \
+; RUN: | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s \
+; RUN: | FileCheck %s
+
+; CHECK: .file "../relative/path/to/file"
+
+source_filename = "../relative/path/to/file"
___
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[llvm-branch-commits] [llvm] d8dc1f2 - file name - special characters.
Author: Chen Zheng
Date: 2021-04-26T05:13:10-04:00
New Revision: d8dc1f20c9a86adfe31ae8df2a763e89ee5068bb
URL:
https://github.com/llvm/llvm-project/commit/d8dc1f20c9a86adfe31ae8df2a763e89ee5068bb
DIFF:
https://github.com/llvm/llvm-project/commit/d8dc1f20c9a86adfe31ae8df2a763e89ee5068bb.diff
LOG: file name - special characters.
Added:
llvm/test/CodeGen/PowerPC/aix-filename-special-character-double-quotation.ll
llvm/test/CodeGen/PowerPC/aix-filename-special-character-single-quotation.ll
Modified:
llvm/include/llvm/MC/MCAsmInfo.h
llvm/lib/MC/MCAsmInfoXCOFF.cpp
llvm/lib/MC/MCAsmStreamer.cpp
Removed:
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h
b/llvm/include/llvm/MC/MCAsmInfo.h
index b674af072ed55..e48d1edd05068 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -345,6 +345,10 @@ class MCAsmInfo {
/// target also needs the directory along with the basename. Default to true.
bool HasBasenameOnlyForFileDirective = true;
+ /// Tue if the target represents string constant as mostly raw characters in
+ /// paired double quotation. Default to false.
+ bool HasPairedDoubleQuoteStringConstants = false;
+
// True if the target allows .align directives on functions. This is true for
// most targets, so defaults to true.
bool HasFunctionAlignment = true;
@@ -673,6 +677,9 @@ class MCAsmInfo {
bool hasBasenameOnlyForFileDirective() const {
return HasBasenameOnlyForFileDirective;
}
+ bool hasPairedDoubleQuoteStringConstants() const {
+return HasPairedDoubleQuoteStringConstants;
+ }
bool hasFunctionAlignment() const { return HasFunctionAlignment; }
bool hasDotTypeDotSizeDirective() const { return HasDotTypeDotSizeDirective;
}
bool hasSingleParameterDotFile() const { return HasSingleParameterDotFile; }
diff --git a/llvm/lib/MC/MCAsmInfoXCOFF.cpp b/llvm/lib/MC/MCAsmInfoXCOFF.cpp
index f90fc5a8f4983..670ab30821638 100644
--- a/llvm/lib/MC/MCAsmInfoXCOFF.cpp
+++ b/llvm/lib/MC/MCAsmInfoXCOFF.cpp
@@ -20,6 +20,11 @@ MCAsmInfoXCOFF::MCAsmInfoXCOFF() {
IsLittleEndian = false;
HasVisibilityOnlyWithLinkage = true;
HasBasenameOnlyForFileDirective = false;
+
+ // For XCOFF, string constant consists of any number of characters enclosed
in
+ // "" (double quotation marks)
+ HasPairedDoubleQuoteStringConstants = true;
+
PrivateGlobalPrefix = "L..";
PrivateLabelPrefix = "L..";
SupportsQuotedNames = false;
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 0012c10bf83b4..432c7bb3971bd 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -60,6 +60,12 @@ class MCAsmStreamer final : public MCStreamer {
unsigned UseDwarfDirectory : 1;
void EmitRegisterName(int64_t Register);
+ void PrintQuotedString(StringRef Data, raw_ostream &OS);
+ void printDwarfFileDirective(unsigned FileNo, StringRef Directory,
+ StringRef Filename,
+ Optional Checksum,
+ Optional Source,
+ bool UseDwarfDirectory, raw_svector_ostream
&OS);
void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;
@@ -1040,33 +1046,53 @@ static void PrintByteList(StringRef Data, raw_ostream
&OS,
llvm_unreachable("Invalid AsmCharLiteralSyntax value!");
}
-static void PrintQuotedString(StringRef Data, raw_ostream &OS) {
+void MCAsmStreamer::PrintQuotedString(StringRef Data, raw_ostream &OS) {
OS << '"';
- for (unsigned i = 0, e = Data.size(); i != e; ++i) {
-unsigned char C = Data[i];
-if (C == '"' || C == '\\') {
- OS << '\\' << (char)C;
- continue;
+ if (MAI->hasPairedDoubleQuoteStringConstants()) {
+for (unsigned i = 0, e = Data.size(); i != e; ++i) {
+ unsigned char C = Data[i];
+ if (C == '"')
+OS << "\"\"";
+ else
+OS << (char)C;
}
+ } else {
+for (unsigned i = 0, e = Data.size(); i != e; ++i) {
+ unsigned char C = Data[i];
+ if (C == '"' || C == '\\') {
+OS << '\\' << (char)C;
+continue;
+ }
-if (isPrint((unsigned char)C)) {
- OS << (char)C;
- continue;
-}
+ if (isPrint((unsigned char)C)) {
+OS << (char)C;
+continue;
+ }
-switch (C) {
- case '\b': OS << "\\b"; break;
- case '\f': OS << "\\f"; break;
- case '\n': OS << "\\n"; break;
- case '\r': OS << "\\r"; break;
- case '\t': OS << "\\t"; break;
+ switch (C) {
+ case '\b':
+OS << "\\b";
+break;
+ case '\f':
+OS << "\\f";
+break;
+ case '\n':
+OS << "\\n";
+break;
+ case '\r':
+OS << "\\r";
+break;
+ case '\t':
+OS << "\\t";
+break;
default:
OS << '
[llvm-branch-commits] [llvm] 5a87328 - more ds/dq preparation
Author: Chen Zheng
Date: 2021-07-15T07:54:49Z
New Revision: 5a8732852b4d7225acaa347f705798fe7d61e92c
URL:
https://github.com/llvm/llvm-project/commit/5a8732852b4d7225acaa347f705798fe7d61e92c
DIFF:
https://github.com/llvm/llvm-project/commit/5a8732852b4d7225acaa347f705798fe7d61e92c.diff
LOG: more ds/dq preparation
Added:
Modified:
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
index 1d2b1ed3f6269..5f08268277a0e 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -169,7 +169,7 @@ namespace {
private:
PPCTargetMachine *TM = nullptr;
-const PPCSubtarget *ST;
+const PPCSubtarget *ST;
DominatorTree *DT;
LoopInfo *LI;
ScalarEvolution *SE;
@@ -184,10 +184,13 @@ namespace {
bool runOnLoop(Loop *L);
/// Check if required PHI node is already exist in Loop \p L.
-bool alreadyPrepared(Loop *L, Instruction* MemI,
+bool alreadyPrepared(Loop *L, Instruction *MemI,
const SCEV *BasePtrStartSCEV,
- const SCEVConstant *BasePtrIncSCEV,
- InstrForm Form);
+ const SCEV *BasePtrIncSCEV, InstrForm Form);
+
+/// Get the value which defines the increment SCEV \p BasePtrIncSCEV.
+Value *getPreparedIncNode(Loop *L, Instruction *MemI,
+ const SCEV *BasePtrIncSCEV);
/// Collect condition matched(\p isValidCandidate() returns true)
/// candidates in Loop \p L.
@@ -266,7 +269,7 @@ static std::string getInstrName(const Value *I, StringRef
Suffix) {
if (I->hasName())
return (I->getName() + Suffix).str();
else
-return "";
+return "";
}
static Value *GetPointerOperand(Value *MemI) {
@@ -404,13 +407,13 @@ bool
PPCLoopInstrFormPrep::prepareBaseForDispFormChain(Bucket &BucketChain,
// contains following load/stores with
diff erent remainders:
// 1: 10 load/store whose remainder is 1;
// 2: 9 load/store whose remainder is 2;
- // 3: 1 for remainder 3 and 0 for remainder 0;
+ // 3: 1 for remainder 3 and 0 for remainder 0;
// Now we will choose the first load/store whose remainder is 1 as base and
// adjust all other load/stores according to new base, so we will get 10 DS
// form and 10 X form.
// But we should be more clever, for this case we could use two bases, one
for
- // remainder 1 and the other for remainder 2, thus we could get 19 DS form
and 1
- // X form.
+ // remainder 1 and the other for remainder 2, thus we could get 19 DS form
and
+ // 1 X form.
unsigned MaxCountRemainder = 0;
for (unsigned j = 0; j < (unsigned)Form; j++)
if ((RemainderOffsetInfo.find(j) != RemainderOffsetInfo.end()) &&
@@ -515,28 +518,48 @@ bool PPCLoopInstrFormPrep::rewriteLoadStores(Loop *L,
Bucket &BucketChain,
if (!SE->isLoopInvariant(BasePtrSCEV->getStart(), L))
return MadeChange;
- const SCEVConstant *BasePtrIncSCEV =
-dyn_cast(BasePtrSCEV->getStepRecurrence(*SE));
- if (!BasePtrIncSCEV)
+ bool IsConstantInc = false;
+ const SCEV *BasePtrIncSCEV = BasePtrSCEV->getStepRecurrence(*SE);
+ Value *IncNode = getPreparedIncNode(L, MemI, BasePtrIncSCEV);
+
+ const SCEVConstant *BasePtrIncConstantSCEV =
+ dyn_cast(BasePtrIncSCEV);
+ if (BasePtrIncConstantSCEV)
+IsConstantInc = true;
+
+ // No valid representation for the increment.
+ if (!IncNode) {
+LLVM_DEBUG(dbgs() << "Loop Increasement can not be represented!\n");
return MadeChange;
+ }
+
+ // Now we only handle update form for constant increment.
+ // FIXME: add support for non-constant increment UpdateForm.
+ if (!IsConstantInc && Form == UpdateForm) {
+LLVM_DEBUG(dbgs() << "not a constant incresement for update form!\n");
+return MadeChange;
+ }
// For some DS form load/store instructions, it can also be an update form,
// if the stride is a multipler of 4. Use update form if prefer it.
- bool CanPreInc = (Form == UpdateForm ||
-((Form == DSForm) && !BasePtrIncSCEV->getAPInt().urem(4) &&
- PreferUpdateForm));
+ bool CanPreInc =
+ (Form == UpdateForm ||
+ ((Form == DSForm) && IsConstantInc &&
+!BasePtrIncConstantSCEV->getAPInt().urem(4) && PreferUpdateForm));
const SCEV *BasePtrStartSCEV = nullptr;
if (CanPreInc)
BasePtrStartSCEV =
-SE->getMinusSCEV(BasePtrSCEV->getStart(), BasePtrIncSCEV);
+SE->getMinusSCEV(BasePtrSCEV->getStart(), BasePtrIncConstantSCEV);
else
BasePtrStartSCEV = BasePtrSCEV->getStart();
if (!isSafeToExpand(BasePtrStartSCEV, *SE))
return MadeCha
[llvm-branch-commits] [llvm] ee7e6c4 - common chains
Author: Chen Zheng
Date: 2021-08-18T03:20:39Z
New Revision: ee7e6c4e05af743c1ba2db57abd33fb828d49025
URL:
https://github.com/llvm/llvm-project/commit/ee7e6c4e05af743c1ba2db57abd33fb828d49025
DIFF:
https://github.com/llvm/llvm-project/commit/ee7e6c4e05af743c1ba2db57abd33fb828d49025.diff
LOG: common chains
Added:
Modified:
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
index 010f49c8d3ebc..c3d3f1504fd4d 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -140,6 +140,38 @@ namespace {
SmallVector Elements;
};
+ struct ChainBucketElement {
+ChainBucketElement(const SCEV *O, Instruction *I) : Offset(O), Instr(I) {}
+ChainBucketElement(Instruction *I) : Offset(nullptr), Instr(I) {}
+
+const SCEV *Offset;
+Instruction *Instr;
+ };
+
+ struct ChainBucket {
+ChainBucket(const SCEV *B, Instruction *I) : BaseSCEV(B),
+Elements(1, ChainBucketElement(I))
{ ChainSize = 0; }
+
+const SCEV *BaseSCEV;
+ // Value *Ptr;
+SmallVector Elements;
+unsigned ChainSize;
+SmallVector ChainBases;
+//SmallVector RewriteBuckets;
+void dump() {
+ LLVM_DEBUG(dbgs() << "Chain base scev is "; BaseSCEV->dump());
+ LLVM_DEBUG(dbgs() << "Chain element size is "<< Elements.size() << "\n");
+ for (auto E : Elements) {
+if (!E.Offset)
+LLVM_DEBUG(dbgs() << "base Element Instruction is "; E.Instr->dump());
+else {
+ LLVM_DEBUG(dbgs() << "Element offset is "; E.Offset->dump());
+ LLVM_DEBUG(dbgs() << "Element instruction is "; E.Instr->dump());
+}
+ }
+}
+ };
+
// "UpdateForm" is not a real PPC instruction form, it stands for dform
// load/store with update like ldu/stdu, or Prefetch intrinsic.
// For DS form instructions, their displacements must be multiple of 4.
@@ -192,6 +224,21 @@ namespace {
Value *getPreparedIncNode(Loop *L, Instruction *MemI,
const SCEV *BasePtrIncSCEV);
+/// Collect chain load/store candidates in Loop \p L.
+SmallVector collectCandidatesForChain(Loop *L);
+
+/// Add a candidate to candidates \p Buckets for chain.
+void addOneCandidateForChain(Instruction *MemI, const SCEV *LSCEV,
SmallVector &Buckets);
+
+/// Common chains to reuse offsets for a loop to reduce register pressure.
+bool chainCommoning(Loop *L, SmallVector &ChainBuckets);
+
+bool prepareBasesForChains(ChainBucket &BucketChain);
+
+bool rewriteLoadStoresForChains(Loop *L, ChainBucket &Bucket,
+ SmallSet &BBChanged,
+DenseMap &ExpandedOffsets);
+
/// Collect condition matched(\p isValidCandidate() returns true)
/// candidates in Loop \p L.
SmallVector collectCandidates(
@@ -272,7 +319,7 @@ static std::string getInstrName(const Value *I, StringRef
Suffix) {
return "";
}
-static Value *GetPointerOperand(Value *MemI) {
+static Value *getPtrOperand(Value *MemI) {
if (LoadInst *LMemI = dyn_cast(MemI)) {
return LMemI->getPointerOperand();
} else if (StoreInst *SMemI = dyn_cast(MemI)) {
@@ -309,10 +356,448 @@ bool PPCLoopInstrFormPrep::runOnFunction(Function &F) {
return MadeChange;
}
+// check if the SCEV is only with one ptr operand in its start, so that we can
+// use that start as a chain separator.
+static bool isValidChainCandidate(const SCEV *LSCEV)
+{
+ const SCEVAddRecExpr *ARSCEV = cast(LSCEV);
+ if (!ARSCEV)
+return false;
+
+ if (!ARSCEV->isAffine())
+return false;
+
+ const SCEV *Start = ARSCEV->getStart();
+ LLVM_DEBUG(dbgs() << "Start SCEV is "; Start->dump());
+ LLVM_DEBUG(dbgs() << "Start SCEV type is "; Start->getType()->dump());
+
+ LLVM_DEBUG(dbgs() << "start is unknown is " << isa(Start) <<
"\n");
+
+ // A single pointer.
+ if (isa(Start) && Start->getType()->isPointerTy())
+return true;
+
+ const SCEVAddExpr *ASCEV = dyn_cast(Start);
+
+ // Now we only handle SCEVAddExpr.
+ if (!ASCEV)
+return false;
+
+ bool SawPointer = false;
+ LLVM_DEBUG(dbgs() << "operand number is " << ASCEV->getNumOperands() <<
"\n");
+ int i = 0;
+ for (const SCEV *Op : ASCEV->operands()) {
+i++;
+LLVM_DEBUG(dbgs() << "operand " << i << " is "; Op->dump());
+LLVM_DEBUG(dbgs() << "operand " << i << " type is ";
Op->getType()->dump());
+if (Op->getType()->isPointerTy()) {
+ if (SawPointer)
+return false;
+ SawPointer = true;
+}
+else if (!Op->getType()->isIntegerTy())
+ return false;
+ }
+
+ return SawPointer;
+}
+
+// Make sure the
diff between the base and new candidate is:
+// 1: an integer type.
+// 2: does not contain any pointer type.
+st
[llvm-branch-commits] [llvm] cb317d6 - update form prepare
Author: Chen Zheng
Date: 2021-07-15T08:02:10Z
New Revision: cb317d60cca17f5ab60bd841b0d25a145cedfa70
URL:
https://github.com/llvm/llvm-project/commit/cb317d60cca17f5ab60bd841b0d25a145cedfa70
DIFF:
https://github.com/llvm/llvm-project/commit/cb317d60cca17f5ab60bd841b0d25a145cedfa70.diff
LOG: update form prepare
Added:
Modified:
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
index 5f08268277a0e..010f49c8d3ebc 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -533,13 +533,6 @@ bool PPCLoopInstrFormPrep::rewriteLoadStores(Loop *L,
Bucket &BucketChain,
return MadeChange;
}
- // Now we only handle update form for constant increment.
- // FIXME: add support for non-constant increment UpdateForm.
- if (!IsConstantInc && Form == UpdateForm) {
-LLVM_DEBUG(dbgs() << "not a constant incresement for update form!\n");
-return MadeChange;
- }
-
// For some DS form load/store instructions, it can also be an update form,
// if the stride is a multipler of 4. Use update form if prefer it.
bool CanPreInc =
@@ -547,10 +540,13 @@ bool PPCLoopInstrFormPrep::rewriteLoadStores(Loop *L,
Bucket &BucketChain,
((Form == DSForm) && IsConstantInc &&
!BasePtrIncConstantSCEV->getAPInt().urem(4) && PreferUpdateForm));
const SCEV *BasePtrStartSCEV = nullptr;
- if (CanPreInc)
-BasePtrStartSCEV =
-SE->getMinusSCEV(BasePtrSCEV->getStart(), BasePtrIncConstantSCEV);
- else
+ if (CanPreInc) {
+assert(SE->isLoopInvariant(BasePtrIncSCEV, L) &&
+ "Increment is not loop invariant!\n");
+BasePtrStartSCEV = SE->getMinusSCEV(BasePtrSCEV->getStart(),
+IsConstantInc ? BasePtrIncConstantSCEV
+ : BasePtrIncSCEV);
+ } else
BasePtrStartSCEV = BasePtrSCEV->getStart();
if (!isSafeToExpand(BasePtrStartSCEV, *SE))
@@ -588,12 +584,10 @@ bool PPCLoopInstrFormPrep::rewriteLoadStores(Loop *L,
Bucket &BucketChain,
Instruction *PtrInc = nullptr;
Instruction *NewBasePtr = nullptr;
if (CanPreInc) {
-assert(BasePtrIncConstantSCEV &&
- "update form now only supports constant increment.");
Instruction *InsPoint = &*Header->getFirstInsertionPt();
-PtrInc = GetElementPtrInst::Create(
-I8Ty, NewPHI, BasePtrIncConstantSCEV->getValue(),
-getInstrName(MemI, GEPNodeIncNameSuffix), InsPoint);
+PtrInc = GetElementPtrInst::Create(I8Ty, NewPHI, IncNode,
+ getInstrName(MemI,
GEPNodeIncNameSuffix),
+ InsPoint);
cast(PtrInc)->setIsInBounds(IsPtrInBounds(BasePtr));
for (auto PI : predecessors(Header)) {
if (PI == LoopPredecessor)
diff --git
a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
index 6132074004305..6628ac89f79ad 100644
--- a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
@@ -85,18 +85,17 @@ define zeroext i8 @foo1(i8* %p, i32 signext %n, i32 signext
%count) {
; CHECK-NEXT:cmpwi r4, 1
; CHECK-NEXT:blt cr0, .LBB1_4
; CHECK-NEXT: # %bb.1: # %for.body.preheader
+; CHECK-NEXT:extsw r5, r5
+; CHECK-NEXT:sub r3, r3, r5
; CHECK-NEXT:addi r6, r3, 1000
; CHECK-NEXT:clrldi r3, r4, 32
-; CHECK-NEXT:extsw r5, r5
-; CHECK-NEXT:li r4, 0
; CHECK-NEXT:mtctr r3
; CHECK-NEXT:li r3, 0
; CHECK-NEXT:.p2align 4
; CHECK-NEXT: .LBB1_2: # %for.body
; CHECK-NEXT:#
-; CHECK-NEXT:lbzx r7, r6, r4
-; CHECK-NEXT:add r4, r4, r5
-; CHECK-NEXT:add r3, r7, r3
+; CHECK-NEXT:lbzux r4, r6, r5
+; CHECK-NEXT:add r3, r4, r3
; CHECK-NEXT:bdnz .LBB1_2
; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
; CHECK-NEXT:clrldi r3, r3, 56
diff --git a/llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
b/llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
index 346353bc12d0a..f2d8157faba32 100644
--- a/llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
+++ b/llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
@@ -50,26 +50,26 @@ define void @foo(double* readonly %0, double* %1, i64 %2,
i64 %3, i64 %4, i64 %5
; CHECK-NEXT:cmpd 6, 24
; CHECK-NEXT:bge 0, .LBB0_2
; CHECK-NEXT: # %bb.4:
-; CHECK-NEXT:maddld 19, 0, 27, 30
+; CHECK-NEXT:maddld 21, 0, 27, 30
; CHECK-NEXT:maddld 20, 0, 27, 12
-; CHECK-NEXT:add 22, 6, 28
-; CHECK-NEXT:add 21, 6, 8
+; CHECK-NEXT:add 23, 6, 28
+; CHE
[llvm-branch-commits] [llvm] 3bdf450 - [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike.
Author: Chen Zheng
Date: 2021-01-17T19:56:42-05:00
New Revision: 3bdf4507b66348ad78df4655a8e4f36c3fc10f3c
URL:
https://github.com/llvm/llvm-project/commit/3bdf4507b66348ad78df4655a8e4f36c3fc10f3c
DIFF:
https://github.com/llvm/llvm-project/commit/3bdf4507b66348ad78df4655a8e4f36c3fc10f3c.diff
LOG: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike.
add one use check to lookThruCopyLike.
The root node is safe to be deleted if we are sure that every
definition in the copy chain only has one use.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D92069
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/TargetRegisterInfo.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 6f32729a1e83..e07779e04b7b 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -410,10 +410,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// Returns the original SrcReg unless it is the target of a copy-like
/// operation, in which case we chain backwards through all such operations
- /// to the ultimate source register. If a physical register is encountered,
+ /// to the ultimate source register. If a physical register is encountered,
/// we stop the search.
+ /// If one definition in the copy chain has multiple uses, set \p
+ /// AllDefHaveOneUser to false, otherwise set it to true.
virtual Register lookThruCopyLike(Register SrcReg,
-const MachineRegisterInfo *MRI) const;
+const MachineRegisterInfo *MRI,
+bool *AllDefHaveOneUser = nullptr) const;
/// Return a null-terminated list of all of the callee-saved registers on
/// this target. The register should be in the order of desired callee-save
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 4a190c9f50af..09c7383a291b 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -510,13 +510,19 @@ TargetRegisterInfo::getRegSizeInBits(Register Reg,
return getRegSizeInBits(*RC);
}
-Register
-TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
- const MachineRegisterInfo *MRI) const {
+Register TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
+ const MachineRegisterInfo *MRI,
+ bool *AllDefHaveOneUser) const {
+ if (AllDefHaveOneUser)
+*AllDefHaveOneUser = true;
+
while (true) {
const MachineInstr *MI = MRI->getVRegDef(SrcReg);
-if (!MI->isCopyLike())
+if (!MI->isCopyLike()) {
+ if (AllDefHaveOneUser && !MRI->hasOneNonDBGUse(SrcReg))
+*AllDefHaveOneUser = false;
return SrcReg;
+}
Register CopySrcReg;
if (MI->isCopy())
@@ -526,8 +532,11 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
CopySrcReg = MI->getOperand(2).getReg();
}
-if (!CopySrcReg.isVirtual())
+if (!CopySrcReg.isVirtual()) {
+ if (AllDefHaveOneUser)
+*AllDefHaveOneUser = false;
return CopySrcReg;
+}
SrcReg = CopySrcReg;
}
___
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[llvm-branch-commits] [llvm] 26a396c - [PowerPC] support register pressure reduction in machine combiner.
Author: Chen Zheng
Date: 2021-01-17T23:56:13-05:00
New Revision: 26a396c4ef481cb159bba631982841736a125a9c
URL:
https://github.com/llvm/llvm-project/commit/26a396c4ef481cb159bba631982841736a125a9c
DIFF:
https://github.com/llvm/llvm-project/commit/26a396c4ef481cb159bba631982841736a125a9c.diff
LOG: [PowerPC] support register pressure reduction in machine combiner.
Reassociating some patterns to generate more fma instructions to
reduce register pressure.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D92071
Added:
llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
Modified:
llvm/include/llvm/CodeGen/MachineCombinerPattern.h
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
Removed:
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index e9f52fb064e1..ac0cc70744d1 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -29,6 +29,11 @@ enum class MachineCombinerPattern {
REASSOC_XY_AMM_BMM,
REASSOC_XMM_AMM_BMM,
+ // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
+ // reduce register pressure.
+ REASSOC_XY_BCA,
+ REASSOC_XY_BAC,
+
// These are multiply-add patterns matched by the AArch64 machine combiner.
MULADDW_OP1,
MULADDW_OP2,
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp
b/llvm/lib/CodeGen/MachineCombiner.cpp
index 878912a6032b..e2b6cfe55c16 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -279,6 +279,9 @@ static CombinerObjective
getCombinerObjective(MachineCombinerPattern P) {
case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
return CombinerObjective::MustReduceDepth;
+ case MachineCombinerPattern::REASSOC_XY_BCA:
+ case MachineCombinerPattern::REASSOC_XY_BAC:
+return CombinerObjective::MustReduceRegisterPressure;
default:
return CombinerObjective::Default;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 75a498b807cd..71d9fb2c179e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -21,12 +21,15 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
@@ -73,6 +76,14 @@ static cl::opt
UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
cl::desc("Use the old (incorrect) instruction latency calculation"));
+static cl::opt
+FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
+cl::desc("register pressure factor for the transformations."));
+
+static cl::opt EnableFMARegPressureReduction(
+"ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
+cl::desc("enable register pressure reduce in machine combiner pass."));
+
// Pin the vtable to this file.
void PPCInstrInfo::anchor() {}
@@ -278,21 +289,23 @@ bool PPCInstrInfo::isAssociativeAndCommutative(const
MachineInstr &Inst) const {
#define InfoArrayIdxFMULInst 2
#define InfoArrayIdxAddOpIdx 3
#define InfoArrayIdxMULOpIdx 4
+#define InfoArrayIdxFSubInst 5
// Array keeps info for FMA instructions:
// Index 0(InfoArrayIdxFMAInst): FMA instruction;
-// Index 1(InfoArrayIdxFAddInst): ADD instruction assoaicted with FMA;
-// Index 2(InfoArrayIdxFMULInst): MUL instruction assoaicted with FMA;
+// Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA;
+// Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA;
// Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands;
// Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands;
-//second MUL operand index is plus 1.
-static const uint16_t FMAOpIdxInfo[][5] = {
+//second MUL operand index is plus 1;
+// Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA.
+static const uint16_t FMAOpIdxInfo[][6] = {
// FIXME: Add more FMA instructions like XSNMADDADP and so on.
-{PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2},
-{PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2},
-{PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2},
-
[llvm-branch-commits] [llvm] a9b3303 - Revert "[NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike."
Author: Chen Zheng
Date: 2021-01-18T21:33:31-05:00
New Revision: a9b3303a8847e100ae23fa711f9b5b8963ebdaf9
URL:
https://github.com/llvm/llvm-project/commit/a9b3303a8847e100ae23fa711f9b5b8963ebdaf9
DIFF:
https://github.com/llvm/llvm-project/commit/a9b3303a8847e100ae23fa711f9b5b8963ebdaf9.diff
LOG: Revert "[NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike."
This reverts commit 3bdf4507b66348ad78df4655a8e4f36c3fc10f3c.
Post commit comments need to be addressed first.
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/TargetRegisterInfo.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index e07779e04b7b..6f32729a1e83 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -410,13 +410,10 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// Returns the original SrcReg unless it is the target of a copy-like
/// operation, in which case we chain backwards through all such operations
- /// to the ultimate source register. If a physical register is encountered,
+ /// to the ultimate source register. If a physical register is encountered,
/// we stop the search.
- /// If one definition in the copy chain has multiple uses, set \p
- /// AllDefHaveOneUser to false, otherwise set it to true.
virtual Register lookThruCopyLike(Register SrcReg,
-const MachineRegisterInfo *MRI,
-bool *AllDefHaveOneUser = nullptr) const;
+const MachineRegisterInfo *MRI) const;
/// Return a null-terminated list of all of the callee-saved registers on
/// this target. The register should be in the order of desired callee-save
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 09c7383a291b..4a190c9f50af 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -510,19 +510,13 @@ TargetRegisterInfo::getRegSizeInBits(Register Reg,
return getRegSizeInBits(*RC);
}
-Register TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
- const MachineRegisterInfo *MRI,
- bool *AllDefHaveOneUser) const {
- if (AllDefHaveOneUser)
-*AllDefHaveOneUser = true;
-
+Register
+TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
+ const MachineRegisterInfo *MRI) const {
while (true) {
const MachineInstr *MI = MRI->getVRegDef(SrcReg);
-if (!MI->isCopyLike()) {
- if (AllDefHaveOneUser && !MRI->hasOneNonDBGUse(SrcReg))
-*AllDefHaveOneUser = false;
+if (!MI->isCopyLike())
return SrcReg;
-}
Register CopySrcReg;
if (MI->isCopy())
@@ -532,11 +526,8 @@ Register TargetRegisterInfo::lookThruCopyLike(Register
SrcReg,
CopySrcReg = MI->getOperand(2).getReg();
}
-if (!CopySrcReg.isVirtual()) {
- if (AllDefHaveOneUser)
-*AllDefHaveOneUser = false;
+if (!CopySrcReg.isVirtual())
return CopySrcReg;
-}
SrcReg = CopySrcReg;
}
___
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[llvm-branch-commits] [llvm] 8120cfe - [NFC] [TargetRegisterInfo] add another API to get srcreg through copy.
Author: Chen Zheng
Date: 2021-01-21T20:10:25-05:00
New Revision: 8120cfedf55ade13a0a1a4a4629911aa2f8ed9c3
URL:
https://github.com/llvm/llvm-project/commit/8120cfedf55ade13a0a1a4a4629911aa2f8ed9c3
DIFF:
https://github.com/llvm/llvm-project/commit/8120cfedf55ade13a0a1a4a4629911aa2f8ed9c3.diff
LOG: [NFC] [TargetRegisterInfo] add another API to get srcreg through copy.
Reviewed By: nemanjai, jsji
Differential Revision: https://reviews.llvm.org/D92069
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/TargetRegisterInfo.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 6f32729a1e83..253f71cb5f1a 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -415,6 +415,16 @@ class TargetRegisterInfo : public MCRegisterInfo {
virtual Register lookThruCopyLike(Register SrcReg,
const MachineRegisterInfo *MRI) const;
+ /// Find the original SrcReg unless it is the target of a copy-like
operation,
+ /// in which case we chain backwards through all such operations to the
+ /// ultimate source register. If a physical register is encountered, we stop
+ /// the search.
+ /// Return the original SrcReg if all the definitions in the chain only have
+ /// one user and not a physical register.
+ virtual Register
+ lookThruSingleUseCopyChain(Register SrcReg,
+ const MachineRegisterInfo *MRI) const;
+
/// Return a null-terminated list of all of the callee-saved registers on
/// this target. The register should be in the order of desired callee-save
/// stack frame offset. The first register is closest to the incoming stack
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 4a190c9f50af..5fd7eef5808f 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -533,6 +533,31 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
}
}
+Register TargetRegisterInfo::lookThruSingleUseCopyChain(
+Register SrcReg, const MachineRegisterInfo *MRI) const {
+ while (true) {
+const MachineInstr *MI = MRI->getVRegDef(SrcReg);
+// Found the real definition, return it if it has a single use.
+if (!MI->isCopyLike())
+ return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
+
+Register CopySrcReg;
+if (MI->isCopy())
+ CopySrcReg = MI->getOperand(1).getReg();
+else {
+ assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
+ CopySrcReg = MI->getOperand(2).getReg();
+}
+
+// Continue only if the next definition in the chain is for a virtual
+// register that has a single use.
+if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
+ return Register();
+
+SrcReg = CopySrcReg;
+ }
+}
+
void TargetRegisterInfo::getOffsetOpcodes(
const StackOffset &Offset, SmallVectorImpl &Ops) const {
assert(!Offset.getScalable() && "Scalable offsets are not handled");
___
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[llvm-branch-commits] [llvm] 4dce7c2 - [MachineLICM] delete dead flag if the duplicated def outside of loop is dead.
Author: Chen Zheng
Date: 2020-12-20T19:26:22-05:00
New Revision: 4dce7c2e2092953f2cea1a2c1ffd4a53ec2531ac
URL:
https://github.com/llvm/llvm-project/commit/4dce7c2e2092953f2cea1a2c1ffd4a53ec2531ac
DIFF:
https://github.com/llvm/llvm-project/commit/4dce7c2e2092953f2cea1a2c1ffd4a53ec2531ac.diff
LOG: [MachineLICM] delete dead flag if the duplicated def outside of loop is
dead.
Fixup dead flags for CSE-ed instructions.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D92557
Added:
llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
Modified:
llvm/lib/CodeGen/MachineLICM.cpp
Removed:
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp
b/llvm/lib/CodeGen/MachineLICM.cpp
index be18581d866d..bc7bb66a82fb 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -157,7 +157,7 @@ namespace {
SmallVector, 16> BackTrace;
// For each opcode, keep a list of potential CSE instructions.
-DenseMap> CSEMap;
+DenseMap> CSEMap;
enum {
SpeculateFalse = 0,
@@ -259,13 +259,12 @@ namespace {
MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
-const MachineInstr *
-LookForDuplicate(const MachineInstr *MI,
- std::vector &PrevMIs);
+MachineInstr *LookForDuplicate(const MachineInstr *MI,
+ std::vector &PrevMIs);
-bool EliminateCSE(
-MachineInstr *MI,
-DenseMap>::iterator &CI);
+bool
+EliminateCSE(MachineInstr *MI,
+ DenseMap>::iterator
&CI);
bool MayCSE(MachineInstr *MI);
@@ -1405,10 +1404,10 @@ void MachineLICMBase::InitCSEMap(MachineBasicBlock *BB)
{
/// Find an instruction amount PrevMIs that is a duplicate of MI.
/// Return this instruction if it's found.
-const MachineInstr*
+MachineInstr *
MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
- std::vector &PrevMIs) {
- for (const MachineInstr *PrevMI : PrevMIs)
+ std::vector &PrevMIs) {
+ for (MachineInstr *PrevMI : PrevMIs)
if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
return PrevMI;
@@ -1419,14 +1418,15 @@ MachineLICMBase::LookForDuplicate(const MachineInstr
*MI,
/// computes the same value. If it's found, do a RAU on with the definition of
/// the existing instruction rather than hoisting the instruction to the
/// preheader.
-bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
-DenseMap>::iterator &CI) {
+bool MachineLICMBase::EliminateCSE(
+MachineInstr *MI,
+DenseMap>::iterator &CI) {
// Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
// the undef property onto uses.
if (CI == CSEMap.end() || MI->isImplicitDef())
return false;
- if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
+ if (MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
// Replace virtual registers defined by MI by their counterparts defined
@@ -1466,6 +1466,9 @@ bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
Register DupReg = Dup->getOperand(Idx).getReg();
MRI->replaceRegWith(Reg, DupReg);
MRI->clearKillFlags(DupReg);
+ // Clear Dup dead flag if any, we reuse it for Reg.
+ if (!MRI->use_nodbg_empty(DupReg))
+Dup->getOperand(Idx).setIsDead(false);
}
MI->eraseFromParent();
@@ -1479,8 +1482,8 @@ bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
/// the loop.
bool MachineLICMBase::MayCSE(MachineInstr *MI) {
unsigned Opcode = MI->getOpcode();
- DenseMap>::iterator
-CI = CSEMap.find(Opcode);
+ DenseMap>::iterator CI =
+ CSEMap.find(Opcode);
// Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
// the undef property onto uses.
if (CI == CSEMap.end() || MI->isImplicitDef())
@@ -1534,8 +1537,8 @@ bool MachineLICMBase::Hoist(MachineInstr *MI,
MachineBasicBlock *Preheader) {
// Look for opportunity to CSE the hoisted instruction.
unsigned Opcode = MI->getOpcode();
- DenseMap>::iterator
-CI = CSEMap.find(Opcode);
+ DenseMap>::iterator CI =
+ CSEMap.find(Opcode);
if (!EliminateCSE(MI, CI)) {
// Otherwise, splice the instruction to the preheader.
Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
diff --git a/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
new file mode 100644
index ..17913594003f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
@@ -0,0 +1,84 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+-
[llvm-branch-commits] [llvm] 5640665 - [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions
Author: Chen Zheng
Date: 2020-12-20T19:48:26-05:00
New Revision: 564066524ad0872eb8b7cadfaf7c94274f3d5951
URL:
https://github.com/llvm/llvm-project/commit/564066524ad0872eb8b7cadfaf7c94274f3d5951
DIFF:
https://github.com/llvm/llvm-project/commit/564066524ad0872eb8b7cadfaf7c94274f3d5951.diff
LOG: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions
This patch does two things:
1: fix the typo that intrinsic mfvscr should be with no readmem property
2: since VSCR is not modeled yet, add has side effect for SAT bit clobber
intrinsics/instructions.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D90807
Added:
llvm/test/CodeGen/PowerPC/sat-register-clobber.ll
Modified:
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Removed:
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 8a6ad8e8085c..075b6252d9a5 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -285,9 +285,9 @@ let TargetPrefix = "ppc" in { // All intrinsics start with
"llvm.ppc.".
// VSCR access.
def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">,
- Intrinsic<[llvm_v8i16_ty], [], [IntrReadMem]>;
+ Intrinsic<[llvm_v8i16_ty], [], [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_mtvscr : GCCBuiltin<"__builtin_altivec_mtvscr">,
- Intrinsic<[], [llvm_v4i32_ty], []>;
+ Intrinsic<[], [llvm_v4i32_ty], [IntrNoMem, IntrHasSideEffects]>;
// Loads. These don't map directly to GCC builtins because they represent
the
@@ -757,10 +757,12 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics
start with "llvm.ppc.".
// Saturating multiply-adds.
def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+ llvm_v8i16_ty, llvm_v8i16_ty],
+ [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vmhraddshs : GCCBuiltin<"__builtin_altivec_vmhraddshs">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+ llvm_v8i16_ty, llvm_v8i16_ty],
+ [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
@@ -778,7 +780,7 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start
with "llvm.ppc.".
llvm_v4i32_ty], [IntrNoMem]>;
def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
- llvm_v4i32_ty], [IntrNoMem]>;
+ llvm_v4i32_ty], [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v4i32_ty], [IntrNoMem]>;
@@ -790,7 +792,7 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start
with "llvm.ppc.".
llvm_v1i128_ty], [IntrNoMem]>;
def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
- llvm_v4i32_ty], [IntrNoMem]>;
+ llvm_v4i32_ty], [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vmsumcud : GCCBuiltin<"__builtin_altivec_vmsumcud">,
Intrinsic<[llvm_v1i128_ty],
[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v1i128_ty],
[IntrNoMem]>;
@@ -841,19 +843,19 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics
start with "llvm.ppc.".
// Vector Sum Instructions.
def int_ppc_altivec_vsumsws : GCCBuiltin<"__builtin_altivec_vsumsws">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- [IntrNoMem]>;
+ [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vsum2sws : GCCBuiltin<"__builtin_altivec_vsum2sws">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- [IntrNoMem]>;
+ [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vsum4sbs : GCCBuiltin<"__builtin_altivec_vsum4sbs">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v4i32_ty],
- [IntrNoMem]>;
+ [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vsum4shs : GCCBuiltin<"__builtin_altivec_vsum4shs">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v4i32_ty],
- [IntrNoMem]>
[llvm-branch-commits] [llvm] 31c2b93 - [MachineSink] add threshold in machinesink pass to reduce compiling time.
Author: Chen Zheng
Date: 2020-12-27T23:23:07-05:00
New Revision: 31c2b93d83f63ce7f9bb4977f58de2e00bf18e0f
URL:
https://github.com/llvm/llvm-project/commit/31c2b93d83f63ce7f9bb4977f58de2e00bf18e0f
DIFF:
https://github.com/llvm/llvm-project/commit/31c2b93d83f63ce7f9bb4977f58de2e00bf18e0f.diff
LOG: [MachineSink] add threshold in machinesink pass to reduce compiling time.
Added:
Modified:
llvm/lib/CodeGen/MachineSink.cpp
Removed:
diff --git a/llvm/lib/CodeGen/MachineSink.cpp
b/llvm/lib/CodeGen/MachineSink.cpp
index 0abdf897b319..265ca6dcb894 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -79,6 +79,18 @@ static cl::opt SplitEdgeProbabilityThreshold(
"splitted critical edge"),
cl::init(40), cl::Hidden);
+static cl::opt SinkLoadInstsPerBlockThreshold(
+"machine-sink-load-instrs-threshold",
+cl::desc("Do not try to find alias store for a load if there is a in-path "
+ "block whose instruction number is higher than this threshold."),
+cl::init(2000), cl::Hidden);
+
+static cl::opt SinkLoadBlocksThreshold(
+"machine-sink-load-blocks-threshold",
+cl::desc("Do not try to find alias store for a load if the block number in
"
+ "the straight line is higher than this threshold."),
+cl::init(20), cl::Hidden);
+
STATISTIC(NumSunk, "Number of machine instructions sunk");
STATISTIC(NumSplit, "Number of critical edges split");
STATISTIC(NumCoalesces, "Number of copies coalesced");
@@ -1020,6 +1032,7 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock
*From,
bool SawStore = false;
bool HasAliasedStore = false;
DenseSet HandledBlocks;
+ DenseSet HandledDomBlocks;
// Go through all reachable blocks from From.
for (MachineBasicBlock *BB : depth_first(From)) {
// We insert the instruction at the start of block To, so no need to worry
@@ -1036,10 +1049,33 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock
*From,
HandledBlocks.insert(BB);
// To post dominates BB, it must be a path from block From.
if (PDT->dominates(To, BB)) {
+ if (!HandledDomBlocks.count(BB))
+HandledDomBlocks.insert(BB);
+
+ // If this BB is too big or the block number in straight line between
From
+ // and To is too big, stop searching to save compiling time.
+ if (BB->size() > SinkLoadInstsPerBlockThreshold ||
+ HandledDomBlocks.size() > SinkLoadBlocksThreshold) {
+for (auto *DomBB : HandledDomBlocks) {
+ if (DomBB != BB && DT->dominates(DomBB, BB))
+HasStoreCache[std::make_pair(DomBB, To)] = true;
+ else if(DomBB != BB && DT->dominates(BB, DomBB))
+HasStoreCache[std::make_pair(From, DomBB)] = true;
+}
+HasStoreCache[BlockPair] = true;
+return true;
+ }
+
for (MachineInstr &I : *BB) {
// Treat as alias conservatively for a call or an ordered memory
// operation.
if (I.isCall() || I.hasOrderedMemoryRef()) {
+ for (auto *DomBB : HandledDomBlocks) {
+if (DomBB != BB && DT->dominates(DomBB, BB))
+ HasStoreCache[std::make_pair(DomBB, To)] = true;
+else if(DomBB != BB && DT->dominates(BB, DomBB))
+ HasStoreCache[std::make_pair(From, DomBB)] = true;
+ }
HasStoreCache[BlockPair] = true;
return true;
}
___
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[llvm-branch-commits] [llvm] 95d6042 - [NFC][PowerPC] code refactor: split IsReassociable to fma and add.
Author: Chen Zheng
Date: 2020-12-01T21:18:57-05:00
New Revision: 95d6042dd440f3db6a71e6a01413adc2f148f788
URL:
https://github.com/llvm/llvm-project/commit/95d6042dd440f3db6a71e6a01413adc2f148f788
DIFF:
https://github.com/llvm/llvm-project/commit/95d6042dd440f3db6a71e6a01413adc2f148f788.diff
LOG: [NFC][PowerPC] code refactor: split IsReassociable to fma and add.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D92070
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 45587504df56..4e3f0abf73c3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -339,16 +339,28 @@ bool PPCInstrInfo::getFMAPatterns(
return true;
};
- auto IsReassociable = [&](const MachineInstr &Instr, int16_t &AddOpIdx,
-bool IsLeaf, bool IsAdd) {
-int16_t Idx = -1;
-if (!IsAdd) {
- Idx = getFMAOpIdxInfo(Instr.getOpcode());
- if (Idx < 0)
-return false;
-} else if (Instr.getOpcode() !=
- FMAOpIdxInfo[getFMAOpIdxInfo(Root.getOpcode())]
- [InfoArrayIdxFAddInst])
+ auto IsReassociableAdd = [&](const MachineInstr &Instr) {
+if (Instr.getOpcode() !=
+FMAOpIdxInfo[getFMAOpIdxInfo(Root.getOpcode())][InfoArrayIdxFAddInst])
+ return false;
+
+// Instruction can be reassociated.
+// fast math flags may prohibit reassociation.
+if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
+ Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
+ return false;
+
+// Instruction operands are virtual registers for reassociation.
+if (!IsAllOpsVirtualReg(Instr))
+ return false;
+
+return true;
+ };
+
+ auto IsReassociableFMA = [&](const MachineInstr &Instr, int16_t &AddOpIdx,
+ bool IsLeaf) {
+int16_t Idx = getFMAOpIdxInfo(Instr.getOpcode());
+if (Idx < 0)
return false;
// Instruction can be reassociated.
@@ -361,7 +373,7 @@ bool PPCInstrInfo::getFMAPatterns(
if (!IsAllOpsVirtualReg(Instr))
return false;
-if (IsAdd && IsLeaf)
+if (IsLeaf)
return true;
AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
@@ -379,7 +391,7 @@ bool PPCInstrInfo::getFMAPatterns(
int16_t AddOpIdx = -1;
// Root must be a valid FMA like instruction.
- if (!IsReassociable(Root, AddOpIdx, false, false))
+ if (!IsReassociableFMA(Root, AddOpIdx, false))
return false;
assert((AddOpIdx >= 0) && "add operand index not right!");
@@ -389,7 +401,7 @@ bool PPCInstrInfo::getFMAPatterns(
// Prev must be a valid FMA like instruction.
AddOpIdx = -1;
- if (!IsReassociable(*Prev, AddOpIdx, false, false))
+ if (!IsReassociableFMA(*Prev, AddOpIdx, false))
return false;
assert((AddOpIdx >= 0) && "add operand index not right!");
@@ -397,11 +409,11 @@ bool PPCInstrInfo::getFMAPatterns(
Register RegA = Prev->getOperand(AddOpIdx).getReg();
MachineInstr *Leaf = MRI.getUniqueVRegDef(RegA);
AddOpIdx = -1;
- if (IsReassociable(*Leaf, AddOpIdx, true, false)) {
+ if (IsReassociableFMA(*Leaf, AddOpIdx, true)) {
Patterns.push_back(MachineCombinerPattern::REASSOC_XMM_AMM_BMM);
return true;
}
- if (IsReassociable(*Leaf, AddOpIdx, true, true)) {
+ if (IsReassociableAdd(*Leaf)) {
Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM);
return true;
}
___
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[llvm-branch-commits] [llvm] 3cb7d62 - [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false.
Author: Chen Zheng
Date: 2020-12-01T22:29:33-05:00
New Revision: 3cb7d6245249d61f443abfacc6d7b0272a71535e
URL:
https://github.com/llvm/llvm-project/commit/3cb7d6245249d61f443abfacc6d7b0272a71535e
DIFF:
https://github.com/llvm/llvm-project/commit/3cb7d6245249d61f443abfacc6d7b0272a71535e.diff
LOG: [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false.
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D92159
Added:
Modified:
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Removed:
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index a1d182931d0f..bfd8f00c228e 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -2858,20 +2858,12 @@ static bool isProfitableChain(IVChain &Chain,
unsigned NumVarIncrements = 0;
unsigned NumReusedIncrements = 0;
- // If any LSRUse in the chain is marked as profitable by target, mark this
- // chain as profitable.
- for (const IVInc &Inc : Chain.Incs)
-if (TTI.isProfitableLSRChainElement(Inc.UserInst))
- return true;
-
- // If number of registers is not the major cost, we cannot benefit from this
- // profitable chain which is based on number of registers.
- // FIXME: add profitable chain optimization for other kinds major cost, for
- // example number of instructions.
- if (!TTI.isNumRegsMajorCostOfLSR())
-return false;
+ if (TTI.isProfitableLSRChainElement(Chain.Incs[0].UserInst))
+return true;
for (const IVInc &Inc : Chain) {
+if (TTI.isProfitableLSRChainElement(Inc.UserInst))
+ return true;
if (Inc.IncExpr->isZero())
continue;
@@ -5635,7 +5627,13 @@ LSRInstance::LSRInstance(Loop *L, IVUsers &IU,
ScalarEvolution &SE,
}
// Start collecting data and preparing for the solver.
- CollectChains();
+ // If number of registers is not the major cost, we cannot benefit from the
+ // current profitable chain optimization which is based on number of
+ // registers.
+ // FIXME: add profitable chain optimization for other kinds major cost, for
+ // example number of instructions.
+ if (TTI.isNumRegsMajorCostOfLSR() || StressIVChain)
+CollectChains();
CollectInterestingTypesAndFactors();
CollectFixupsAndInitialFormulae();
CollectLoopInvariantFixupsAndFormulae();
___
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[llvm-branch-commits] [llvm] 66a03d1 - [PowerPC] prepare more dq form for P10 pair load/store
Author: Chen Zheng
Date: 2020-12-08T21:01:40-05:00
New Revision: 66a03d10220a56437352cafa1f6ff803e307eb8c
URL:
https://github.com/llvm/llvm-project/commit/66a03d10220a56437352cafa1f6ff803e307eb8c
DIFF:
https://github.com/llvm/llvm-project/commit/66a03d10220a56437352cafa1f6ff803e307eb8c.diff
LOG: [PowerPC] prepare more dq form for P10 pair load/store
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D92393
Added:
llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
Modified:
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
index ccbaea88d2f1..9c83f0a92482 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -81,10 +81,8 @@
using namespace llvm;
-// By default, we limit this to creating 16 common bases out of loops per
-// function. 16 is a little over half of the allocatable register set.
static cl::opt MaxVarsPrep("ppc-formprep-max-vars",
- cl::Hidden, cl::init(16),
+ cl::Hidden, cl::init(24),
cl::desc("Potential common base number threshold per function for PPC loop "
"prep"));
@@ -94,8 +92,7 @@ static cl::opt
PreferUpdateForm("ppc-formprep-prefer-update",
// Sum of following 3 per loop thresholds for all loops can not be larger
// than MaxVarsPrep.
-// By default, we limit this to creating 9 PHIs for one loop.
-// 9 and 3 for each kind prep are exterimental values on Power9.
+// now the thresholds for each kind prep are exterimental values on Power9.
static cl::opt MaxVarsUpdateForm("ppc-preinc-prep-max-vars",
cl::Hidden, cl::init(3),
cl::desc("Potential PHI threshold per loop for PPC loop prep of update "
@@ -106,7 +103,7 @@ static cl::opt
MaxVarsDSForm("ppc-dsprep-max-vars",
cl::desc("Potential PHI threshold per loop for PPC loop prep of DS form"));
static cl::opt MaxVarsDQForm("ppc-dqprep-max-vars",
- cl::Hidden, cl::init(3),
+ cl::Hidden, cl::init(8),
cl::desc("Potential PHI threshold per loop for PPC loop prep of DQ form"));
diff --git a/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
b/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
new file mode 100644
index ..93e1eb542989
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
@@ -0,0 +1,637 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-p:64:64-n32:64-v256:256:256-v512:512:512"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+%_elem_type_of_a = type <{ double }>
+%_elem_type_of_x = type <{ double }>
+
+define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x
%_elem_type_of_x]* %.x, i32* %.l, <2 x double>* %.vy01, <2 x double>* %.vy02,
<2 x double>* %.vy03, <2 x double>* %.vy04, <2 x double>* %.vy05, <2 x double>*
%.vy06, <2 x double>* %.vy07, <2 x double>* %.vy08, <2 x double>* %.vy09, <2 x
double>* %.vy0a, <2 x double>* %.vy0b, <2 x double>* %.vy0c, <2 x double>*
%.vy21, <2 x double>* %.vy22, <2 x double>* %.vy23, <2 x double>* %.vy24, <2 x
double>* %.vy25, <2 x double>* %.vy26, <2 x double>* %.vy27, <2 x double>*
%.vy28, <2 x double>* %.vy29, <2 x double>* %.vy2a, <2 x double>* %.vy2b, <2 x
double>* %.vy2c) {
+; CHECK-LABEL: foo:
+; CHECK: .localentry foo, 1
+; CHECK-NEXT: # %bb.0: # %entry
+; CHECK-NEXT:stdu 1, -448(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 448
+; CHECK-NEXT:.cfi_offset r14, -256
+; CHECK-NEXT:.cfi_offset r15, -248
+; CHECK-NEXT:.cfi_offset r16, -240
+; CHECK-NEXT:.cfi_offset r17, -232
+; CHECK-NEXT:.cfi_offset r18, -224
+; CHECK-NEXT:.cfi_offset r19, -216
+; CHECK-NEXT:.cfi_offset r20, -208
+; CHECK-NEXT:.cfi_offset r21, -200
+; CHECK-NEXT:.cfi_offset r22, -192
+; CHECK-NEXT:.cfi_offset r23, -184
+; CHECK-NEXT:.cfi_offset r24, -176
+; CHECK-NEXT:.cfi_offset r25, -168
+; CHECK-NEXT:.cfi_offset r26, -160
+; CHECK-NEXT:.cfi_offset r27, -152
+; CHECK-NEXT:.cfi_offset r28, -144
+; CHECK-NEXT:.cfi_offset r29, -136
+; CHECK-NEXT:.cfi_offset r30, -128
+; CHECK-NEXT:.cfi_offset r31, -120
+; CHECK-NEXT:.cfi_offset f18, -112
+; CHECK-NEXT:.cfi_offset f19, -104
+; CHECK-NEXT:.cfi_offset f20, -96
+; CHECK-NEXT:.cfi_offset f21, -88
+; CHECK-NEXT:.cfi_offset f22, -80
+; CHECK-NEXT:.cfi_offset f23, -72
+; CHECK-NEXT:.cfi_offset f24, -64
+; CHECK-NEXT:.cfi_offset f25, -56
+; CHECK-NEXT:.cfi_offset f26, -48
+; CHECK-NEXT:.cfi_offset f27, -40
+; CHECK-NEXT:.cfi_offset f28, -32
+; CHECK-NEXT:.cfi_offset
[llvm-branch-commits] [llvm] 4830d45 - [MachineCombiner][NFC] Add MustReduceRegisterPressure goal
Author: Chen Zheng
Date: 2020-12-14T00:02:42-05:00
New Revision: 4830d458dd0d133354cbe1a616e38dfda8e096b8
URL:
https://github.com/llvm/llvm-project/commit/4830d458dd0d133354cbe1a616e38dfda8e096b8
DIFF:
https://github.com/llvm/llvm-project/commit/4830d458dd0d133354cbe1a616e38dfda8e096b8.diff
LOG: [MachineCombiner][NFC] Add MustReduceRegisterPressure goal
add a new goal MustReduceRegisterPressure for machine combiner pass.
PowerPC will use this new goal to do some register pressure related
optimization.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D92068
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
Removed:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index d7a0e47d3bb5..1cf205f9f5a3 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOutliner.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/Support/BranchProbability.h"
@@ -1076,9 +1077,23 @@ class TargetInstrInfo : public MCInstrInfo {
/// faster sequence.
/// \param Root - Instruction that could be combined with one of its operands
/// \param Patterns - Vector of possible combination patterns
- virtual bool getMachineCombinerPatterns(
- MachineInstr &Root,
- SmallVectorImpl &Patterns) const;
+ virtual bool
+ getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl &Patterns,
+ bool DoRegPressureReduce) const;
+
+ /// Return true if target supports reassociation of instructions in machine
+ /// combiner pass to reduce register pressure for a given BB.
+ virtual bool
+ shouldReduceRegisterPressure(MachineBasicBlock *MBB,
+ RegisterClassInfo *RegClassInfo) const {
+return false;
+ }
+
+ /// Fix up the placeholder we may add in genAlternativeCodeSequence().
+ virtual void
+ finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+SmallVectorImpl &InsInstrs) const {}
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp
b/llvm/lib/CodeGen/MachineCombiner.cpp
index f241435a0482..878912a6032b 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineSizeOpts.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
@@ -72,6 +73,7 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Ensemble *MinInstr;
MachineBlockFrequencyInfo *MBFI;
ProfileSummaryInfo *PSI;
+ RegisterClassInfo RegClassInfo;
TargetSchedModel TSchedModel;
@@ -103,6 +105,10 @@ class MachineCombiner : public MachineFunctionPass {
SmallVectorImpl &DelInstrs,
DenseMap &InstrIdxForVirtReg,
MachineCombinerPattern Pattern, bool
SlackIsAccurate);
+ bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
+ SmallVectorImpl &InsInstrs,
+ SmallVectorImpl &DelInstrs,
+ MachineCombinerPattern Pattern);
bool preservesResourceLen(MachineBasicBlock *MBB,
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl &InsInstrs,
@@ -257,8 +263,9 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root,
MachineInstr *NewRoot,
/// The combiner's goal may
diff er based on which pattern it is attempting
/// to optimize.
enum class CombinerObjective {
- MustReduceDepth, // The data dependency chain must be improved.
- Default // The critical path must not be lengthened.
+ MustReduceDepth,// The data dependency chain must be improved.
+ MustReduceRegisterPressure, // The register pressure must be reduced.
+ Default // The critical path must not be lengthened.
};
static CombinerObjective getCombinerObjective(MachineCombinerPattern P) {
@@ -300,6 +307,18 @@ std::pair
MachineCombiner::getLaten
