[llvm-branch-commits] [llvm-branch] r326539 - Add some minimal release notes for retpoline support.

2018-03-01 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Thu Mar  1 21:48:38 2018
New Revision: 326539

URL: http://llvm.org/viewvc/llvm-project?rev=326539&view=rev
Log:
Add some minimal release notes for retpoline support.

Modified:
llvm/branches/release_60/docs/ReleaseNotes.rst

Modified: llvm/branches/release_60/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/docs/ReleaseNotes.rst?rev=326539&r1=326538&r2=326539&view=diff
==
--- llvm/branches/release_60/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_60/docs/ReleaseNotes.rst Thu Mar  1 21:48:38 2018
@@ -42,6 +42,12 @@ Non-comprehensive list of changes in thi
 * Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD
   (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer).
 
+* Support for `retpolines `_
+  was added to help mitigate "branch target injection" (variant #2) of the
+  "Spectre" speculative side channels described by `Project Zero
+  
`_
+  and the `Spectre paper `_.
+
 
 Changes to the LLVM IR
 --
@@ -183,6 +189,10 @@ During this release the X86 target has:
 
 * Improved documentation for SSE/AVX intrinsics in intrin.h header files.
 
+* Gained support for emitting `retpolines
+  `_, including automatic
+  insertion of the necessary thunks or using external thunks.
+
 
 External Open Source Projects Using LLVM 6
 ==


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[llvm-branch-commits] [cfe-branch] r326540 - Add some minimal release notes for retpolines.

2018-03-01 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Thu Mar  1 21:49:03 2018
New Revision: 326540

URL: http://llvm.org/viewvc/llvm-project?rev=326540&view=rev
Log:
Add some minimal release notes for retpolines.

Modified:
cfe/branches/release_60/docs/ReleaseNotes.rst

Modified: cfe/branches/release_60/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_60/docs/ReleaseNotes.rst?rev=326540&r1=326539&r2=326540&view=diff
==
--- cfe/branches/release_60/docs/ReleaseNotes.rst (original)
+++ cfe/branches/release_60/docs/ReleaseNotes.rst Thu Mar  1 21:49:03 2018
@@ -51,6 +51,12 @@ Non-comprehensive list of changes in thi
   ``__is_target_vendor``, ``__is_target_os``, and ``__is_target_environment``
   can be used to to examine the individual components of the target triple.
 
+- Support for `retpolines `_
+  was added to help mitigate "branch target injection" (variant #2) of the
+  "Spectre" speculative side channels described by `Project Zero
+  
`_
+  and the `Spectre paper `_.
+
 
 Improvements to Clang's diagnostics
 ---
@@ -138,6 +144,18 @@ New Compiler Flags
 - New ``-nostdlib++`` flag to disable linking the C++ standard library. Similar
   to using ``clang`` instead of ``clang++`` but doesn't disable ``-lm``.
 
+- Clang supports the ``-mretpoline`` flag to enable `retpolines
+  `_. Code compiled with this
+  flag will be hardened against variant #2 of the Spectre attack. Indirect
+  branches from switches or gotos removed from the code, and indirect calls
+  will be made through a "retpoline" thunk. The necessary thunks will
+  automatically be inserted into the generated code. Clang also supports
+  ``-mretpoline-external-thunk`` which works like ``-mretpoline`` but requires
+  the user to provide their own thunk definitions. The external thunk names
+  start with ``__x86_indirect_thunk_`` and end in a register name. For 64-bit
+  platforms, only an ``r11`` thunk is used, but for 32-bit platforms ``eax``,
+  ``ecx``, ``edx``, and ``edi`` thunks are used.
+
 
 Attribute Changes in Clang
 --


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[llvm-branch-commits] [openmp] f855751 - Fix openmp CMake build on non-Linux AArch64 systems.

2021-01-17 Thread Chandler Carruth via llvm-branch-commits 

Author: Chandler Carruth
Date: 2021-01-17T16:18:31-08:00
New Revision: f855751c1284c82c1c46b98f6d1b3ca2021d6cb9

URL: 
https://github.com/llvm/llvm-project/commit/f855751c1284c82c1c46b98f6d1b3ca2021d6cb9
DIFF: 
https://github.com/llvm/llvm-project/commit/f855751c1284c82c1c46b98f6d1b3ca2021d6cb9.diff

LOG: Fix openmp CMake build on non-Linux AArch64 systems.

This just checks for `/proc/cpuinfo` existing before reading it.

Tested on an ARM macOS machine.

Added: 


Modified: 
openmp/runtime/cmake/LibompGetArchitecture.cmake

Removed: 




diff  --git a/openmp/runtime/cmake/LibompGetArchitecture.cmake 
b/openmp/runtime/cmake/LibompGetArchitecture.cmake
index 45c2f279a7d1..dd60a2d347b1 100644
--- a/openmp/runtime/cmake/LibompGetArchitecture.cmake
+++ b/openmp/runtime/cmake/LibompGetArchitecture.cmake
@@ -71,13 +71,15 @@ function(libomp_get_architecture return_arch)
 endfunction()
 
 function(libomp_is_aarch64_a64fx return_is_aarch64_a64fx)
-  file(READ "/proc/cpuinfo" cpu_info_content)
-  string(REGEX MATCH "CPU implementer[ \t]*: 0x46\n" cpu_implementer 
${cpu_info_content})
-  string(REGEX MATCH "CPU architecture[ \t]*: 8\n" cpu_architecture 
${cpu_info_content})
-
   set(is_aarch64_a64fx FALSE)
-  if (cpu_architecture AND cpu_implementer)
-set(is_aarch64_a64fx TRUE)
+  if (EXISTS "/proc/cpuinfo")
+file(READ "/proc/cpuinfo" cpu_info_content)
+string(REGEX MATCH "CPU implementer[ \t]*: 0x46\n" cpu_implementer 
${cpu_info_content})
+string(REGEX MATCH "CPU architecture[ \t]*: 8\n" cpu_architecture 
${cpu_info_content})
+
+if (cpu_architecture AND cpu_implementer)
+  set(is_aarch64_a64fx TRUE)
+endif()
   endif()
 
   set(${return_is_aarch64_a64fx} "${is_aarch64_a64fx}" PARENT_SCOPE)



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[llvm-branch-commits] [llvm-branch] r332900 - Merging r329040 with re-generated CHECK lines via the script.

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 14:23:38 2018
New Revision: 332900

URL: http://llvm.org/viewvc/llvm-project?rev=332900&view=rev
Log:
Merging r329040 with re-generated CHECK lines via the script.

The CHECK lines in the trunk version don't work due to unrelated (unmerged)
changes to the backend.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 14:23:38 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,329040

Modified: llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll?rev=332900&r1=332899&r2=332900&view=diff
==
--- llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll 
(original)
+++ llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll Mon May 
21 14:23:38 2018
@@ -1,11 +1,12 @@
-; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s -check-prefix=i386
-; RUN: llc -mtriple=i386-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s 
-check-prefix=i386f
-
-; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s -check-prefix=x8664
-; RUN: llc -mtriple=x86_64-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s 
-check-prefix=x8664
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s 
-check-prefix=x8664-sahf
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf -pre-RA-sched=fast %s -o - | 
FileCheck %s -check-prefix=x8664-sahf
-; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=corei7 %s -o - | FileCheck %s 
-check-prefix=x8664-sahf
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s 
--check-prefixes=32-ALL,32-GOOD-RA
+; RUN: llc -mtriple=i386-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s 
--check-prefixes=32-ALL,32-FAST-RA
+
+; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s 
--check-prefixes=64-ALL,64-GOOD-RA
+; RUN: llc -mtriple=x86_64-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s 
--check-prefixes=64-ALL,64-FAST-RA
+; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s 
--check-prefixes=64-ALL,64-GOOD-RA-SAHF
+; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf -pre-RA-sched=fast %s -o - | 
FileCheck %s --check-prefixes=64-ALL,64-FAST-RA-SAHF
+; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=corei7 %s -o - | FileCheck %s 
--check-prefixes=64-ALL,64-GOOD-RA-SAHF
 
 ; TODO: Reenable verify-machineinstr once the if (!AXDead) // FIXME
 ; in X86InstrInfo::copyPhysReg() is resolved.
@@ -13,26 +14,8 @@
 declare i32 @foo()
 declare i32 @bar(i64)
 
-define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) {
-; i386-LABEL: test_intervening_call:
-; i386: cmpxchg8b
-; i386-NEXT: pushl %eax
-; i386-NEXT: seto %al
-; i386-NEXT: lahf
-; i386-NEXT: movl %eax, [[FLAGS:%.*]]
-; i386-NEXT: popl %eax
-; i386-NEXT: subl $8, %esp
-; i386-NEXT: pushl %edx
-; i386-NEXT: pushl %eax
-; i386-NEXT: calll bar
-; i386-NEXT: addl $16, %esp
-; i386-NEXT: movl [[FLAGS]], %eax
-; i386-NEXT: addb $127, %al
-; i386-NEXT: sahf
-; i386-NEXT: jne
-
-; In the following case we get a long chain of EFLAGS save/restore due to
-; a sequence of:
+; In the following case when using fast scheduling we get a long chain of
+

[llvm-branch-commits] [llvm-branch] r332928 - Merge r322521 - just regenerates the CHECK lines using the script. Will allow

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 19:02:03 2018
New Revision: 332928

URL: http://llvm.org/viewvc/llvm-project?rev=332928&view=rev
Log:
Merge r322521 - just regenerates the CHECK lines using the script. Will allow
subsequent cherrypicks to be much cleaner.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/test/CodeGen/X86/win64_frame.ll

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 19:02:03 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,329040,329055-329057
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,329040,329055-329057

Modified: llvm/branches/release_60/test/CodeGen/X86/win64_frame.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/X86/win64_frame.ll?rev=332928&r1=332927&r2=332928&view=diff
==
--- llvm/branches/release_60/test/CodeGen/X86/win64_frame.ll (original)
+++ llvm/branches/release_60/test/CodeGen/X86/win64_frame.ll Mon May 21 
19:02:03 2018
@@ -1,43 +1,85 @@
-; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s --check-prefix=CHECK 
--check-prefix=PUSHF
-; RUN: llc < %s -mtriple=x86_64-pc-win32 -mattr=+sahf | FileCheck %s 
--check-prefix=SAHF
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-pc-win32  | FileCheck %s 
--check-prefix=ALL --check-prefix=PUSHF
+; RUN: llc < %s -mtriple=x86_64-pc-win32 -mattr=+sahf | FileCheck %s 
--check-prefix=ALL --check-prefix=SAHF
 
 define i32 @f1(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) 
"no-frame-pointer-elim"="true" {
-  ; CHECK-LABEL: f1:
-  ; CHECK:   movl48(%rbp), %eax
+; ALL-LABEL: f1:
+; ALL:   # %bb.0:
+; ALL-NEXT:pushq %rbp
+; ALL-NEXT:.seh_pushreg 5
+; ALL-NEXT:movq %rsp, %rbp
+; ALL-NEXT:.seh_setframe 5, 0
+; ALL-NEXT:.seh_endprologue
+; ALL-NEXT:movl 48(%rbp), %eax
+; ALL-NEXT:popq %rbp
+; ALL-NEXT:retq
+; ALL-NEXT:.seh_handlerdata
+; ALL-NEXT:.text
+; ALL-NEXT:.seh_endproc
   ret i32 %p5
 }
 
 define void @f2(i32 %p, ...) "no-frame-pointer-elim"="true" {
-  ; CHECK-LABEL: f2:
-  ; CHECK:  .seh_stackalloc 8
-  ; CHECK:  movq%rsp, %rbp
-  ; CHECK:  .seh_setframe 5, 0
-  ; CHECK:  movq%rdx, 32(%rbp)
-  ; CHECK:  leaq32(%rbp), %rax
+; ALL-LABEL: f2:
+; ALL:   # %bb.0:
+; ALL-NEXT:pushq %rbp
+; ALL-NEXT:.seh_pushreg 5
+; ALL-NEXT:pushq %rax
+; ALL-NEXT:.seh_stackalloc 8
+; ALL-NEXT:movq %rsp, %rbp
+; ALL-NEXT:.seh_setframe 5, 0
+; ALL-NEXT:.seh_endprologue
+; ALL-NEXT:movq %r9, 48(%rbp)
+; ALL-NEXT:movq %r8, 40(%rbp)
+; ALL-NEXT:movq %rdx, 32(%rbp)
+; ALL-NEXT:leaq 32(%rbp), %rax
+; ALL-NEXT:movq %rax, (%rbp)
+; ALL-NEXT:addq $8, %rsp
+; ALL-NEXT:popq %rbp
+; ALL-NEXT:retq
+; ALL-NEXT:.seh_handlerdata
+; ALL-NEXT:.text
+; ALL-NEXT:.seh_endproc
   %ap = alloca i8, align 8
   call void @llvm.va_start(i8* %ap)
   ret void
 }
 
 define i8* @f3() "no-frame-pointer-elim"="true" {
-  ; CHECK-LABEL: f3:
-  ; CHECK:  movq%rsp, %rbp
-  ; CHECK:  .seh_setframe 5, 0
-  ; CHECK:  movq8(%rbp), %rax
+; ALL-LABEL: f3:
+; ALL:   # %bb.0:
+; ALL-NEXT:pushq %rbp
+; ALL-NEXT:.seh_pushreg 5
+; ALL-NEXT:movq %rsp, %rbp
+; ALL-NEXT:.seh_setframe 5, 0
+; ALL-NEXT:.seh_endprologue
+; ALL-NEXT:movq 8(%rbp), %rax
+; ALL-NEXT:popq %rbp
+; ALL

[llvm-branch-commits] [llvm-branch] r332932 - Merge r328945 which corrected the fundamental structure of the `adox`

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 19:39:59 2018
New Revision: 332932

URL: http://llvm.org/viewvc/llvm-project?rev=332932&view=rev
Log:
Merge r328945 which corrected the fundamental structure of the `adox`
instructions.

This is necessary to fully merge the EFLAGS fix patch series.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/lib/Target/X86/X86InstrArithmetic.td

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 19:39:59 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,329040,329055-329057
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057

Modified: llvm/branches/release_60/lib/Target/X86/X86InstrArithmetic.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86InstrArithmetic.td?rev=332932&r1=332931&r2=332932&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/branches/release_60/lib/Target/X86/X86InstrArithmetic.td Mon May 21 
19:39:59 2018
@@ -1334,7 +1334,7 @@ let Predicates = [HasBMI2] in {
 }
 
 
//===--===//
-// ADCX Instruction
+// ADCX and ADOX Instructions
 //
 let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
 Constraints = "$src0 = $dst", AddedComplexity = 10 in {
@@ -1349,6 +1349,13 @@ let Predicates = [HasADX], Defs = [EFLAG
  [(set GR64:$dst, EFLAGS,
  (X86adc_flag GR64:$src0, GR64:$src, EFLAGS))],
  IIC_BIN_CARRY_NONMEM>, T8PD;
+
+  // We don't have patterns for ADOX yet.
+  def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src0, 
GR32:$src),
+ "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS;
+
+  def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src0, 
GR64:$src),
+ "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS;
   } // SchedRW
 
   let mayLoad = 1, SchedRW = [WriteALULd] in {
@@ -1363,27 +1370,12 @@ let Predicates = [HasADX], Defs = [EFLAG
  [(set GR64:$dst, EFLAGS,
  (X86adc_flag GR64:$src0, (loadi64 addr:$src), EFLAGS))],
  IIC_BIN_CARRY_MEM>, T8PD;
-  }
-}
 
-//===--===//
-// ADOX Instruction
-//
-let Predicates = [HasADX], hasSideEffects = 0, Defs = [EFLAGS],
-Uses = [EFLAGS] in {
-  let SchedRW = [WriteALU] in {
-  def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
- "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS;
-
-  def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
- "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS;
-  } // SchedRW
-
-  let mayLoad = 1, SchedRW = [WriteALULd] in {
-  def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+  // We don't have patterns for ADOX yet.
+  def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src0, 
i32mem:$src),
  "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_MEM>, T8XS;
 
-  def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
+  def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src0, 
i64mem:$src),
  "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_MEM>, T8XS;
   }
 }


___
llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r332934 - Merge r329673, fixing test case to use %regname instead of $regname.

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 19:50:20 2018
New Revision: 332934

URL: http://llvm.org/viewvc/llvm-project?rev=332934&view=rev
Log:
Merge r329673, fixing test case to use %regname instead of $regname.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_60/lib/Target/X86/X86InstrCompiler.td
llvm/branches/release_60/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/release_60/lib/Target/X86/X86InstrInfo.td
llvm/branches/release_60/lib/Target/X86/X86InstrSystem.td
llvm/branches/release_60/lib/Target/X86/X86RegisterInfo.td
llvm/branches/release_60/test/CodeGen/X86/ipra-reg-usage.ll

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 19:50:20 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673

Modified: 
llvm/branches/release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=332934&r1=332933&r2=332934&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp 
(original)
+++ llvm/branches/release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp 
Mon May 21 19:50:20 2018
@@ -265,13 +265,10 @@ MCDisassembler::DecodeStatus X86GenericD
 /// @param reg- The Reg to append.
 static void translateRegister(MCInst &mcInst, Reg reg) {
 #define ENTRY(x) X86::x,
-  uint8_t llvmRegnums[] = {
-ALL_REGS
-0
-  };
+  static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
 #undef ENTRY
 
-  uint8_t llvmRegnum = llvmRegnums[reg];
+  MCPhysReg llvmRegnum = llvmRegnums[reg];
   mcInst.addOperand(MCOperand::createReg(llvmRegnum));
 }
 

Modified: llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp?rev=332934&r1=332933&r2=332934&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp Mon May 21 
19:50:20 2018
@@ -27781,11 +27781,16 @@ X86TargetLowering::EmitInstrWithCustomIn
 MI.getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64;
 unsigned Pop = MI.getOpcode() == X86::RDFLAGS32 ? X86::POP32r : 
X86::POP64r;
 MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));
-// Permit reads of the FLAGS register without it being defined.
+// Permit reads of the EFLAGS and DF registers without them being defined.
 // This intrinsic exists to read external processor state in flags, such as
 // the trap flag, interrupt flag, and direction flag, none of which are
 // modeled by the backend.
+assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
+   "Unexpected register in operand!");
 Push->getOperand(2).setIsUndef();
+assert(Push->getOperand(3).getReg() == X86::DF &&
+   "Unexpected register in operand!");
+Push->getOperand(3).setIsUndef();
 BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
 
 MI.eraseFromParent(); // The

[llvm-branch-commits] [llvm-branch] r332937 - Merge r329771, fixing $regname to be %regname.

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 19:53:53 2018
New Revision: 332937

URL: http://llvm.org/viewvc/llvm-project?rev=332937&view=rev
Log:
Merge r329771, fixing $regname to be %regname.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 19:53:53 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771

Modified: llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=332937&r1=332936&r2=332937&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp Mon May 21 
19:53:53 2018
@@ -727,8 +727,27 @@ void X86FlagsCopyLoweringPass::rewriteSe
   if (!CondReg)
 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
 
-  // Rewriting this is trivial: we just replace the register and remove the
-  // setcc.
-  MRI->replaceRegWith(SetCCI.getOperand(0).getReg(), CondReg);
+  // Rewriting a register def is trivial: we just replace the register and
+  // remove the setcc.
+  if (!SetCCI.mayStore()) {
+assert(SetCCI.getOperand(0).isReg() &&
+   "Cannot have a non-register defined operand to SETcc!");
+MRI->replaceRegWith(SetCCI.getOperand(0).getReg(), CondReg);
+SetCCI.eraseFromParent();
+return;
+  }
+
+  // Otherwise, we need to emit a store.
+  auto MIB = BuildMI(*SetCCI.getParent(), SetCCI.getIterator(),
+ SetCCI.getDebugLoc(), TII->get(X86::MOV8mr));
+  // Copy the address operands.
+  for (int i = 0; i < X86::AddrNumOperands; ++i)
+MIB.add(SetCCI.getOperand(i));
+
+  MIB.addReg(CondReg);
+
+  MIB->setMemRefs(SetCCI.memoperands_begin(), SetCCI.memoperands_end());
+
   SetCCI.eraseFromParent();
+  return;
 }

Modified: llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir?rev=332937&r1=332936&r2=332937&view=diff
==
--- llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir (original)
+++ llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir Mon May 
21 19:53:53 2018
@@ -208,11 +208,10 @@ body: |
 %3:gr8 = SETAr implicit %eflags
 %4:gr8 = SETBr implicit %eflags
 %5:gr8 = SETEr implicit %eflags
-%6:gr8 = SETNEr implicit killed %eflags
+SETNEm %rsp, 1, %noreg, -16, %noreg, implicit killed %eflags
 MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %3
 MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %4
 MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %5
-MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %6
   ; CHECK-NOT: %eflags =
   ; CHECK-NOT: = SET{{.*}}
   ; CHECK: MOV8mr {{.*}}, killed %[[A_REG]]


___
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llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r332938 - Merge r330264 for the fix to PR37100, a regression introduced with the new

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 20:01:19 2018
New Revision: 332938

URL: http://llvm.org/viewvc/llvm-project?rev=332938&view=rev
Log:
Merge r330264 for the fix to PR37100, a regression introduced with the new
EFLAGS lowering.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/branches/release_60/test/CodeGen/X86/O0-pipeline.ll
llvm/branches/release_60/test/CodeGen/X86/copy-eflags.ll

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 20:01:19 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771,330264

Modified: llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=332938&r1=332937&r2=332938&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp Mon May 21 
20:01:19 2018
@@ -36,6 +36,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
@@ -98,6 +99,7 @@ private:
   const X86InstrInfo *TII;
   const TargetRegisterInfo *TRI;
   const TargetRegisterClass *PromoteRC;
+  MachineDominatorTree *MDT;
 
   CondRegArray collectCondsInRegs(MachineBasicBlock &MBB,
   MachineInstr &CopyDefI);
@@ -145,6 +147,7 @@ FunctionPass *llvm::createX86FlagsCopyLo
 char X86FlagsCopyLoweringPass::ID = 0;
 
 void X86FlagsCopyLoweringPass::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.addRequired();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
@@ -342,6 +345,7 @@ bool X86FlagsCopyLoweringPass::runOnMach
   MRI = &MF.getRegInfo();
   TII = Subtarget.getInstrInfo();
   TRI = Subtarget.getRegisterInfo();
+  MDT = &getAnalysis();
   PromoteRC = &X86::GR8RegClass;
 
   if (MF.begin() == MF.end())
@@ -416,103 +420,142 @@ bool X86FlagsCopyLoweringPass::runOnMach
 // of these up front instead.
 CondRegArray CondRegs = collectCondsInRegs(TestMBB, CopyDefI);
 
-for (auto MII = std::next(CopyI->getIterator()), MIE = MBB.instr_end();
- MII != MIE;) {
-  MachineInstr &MI = *MII++;
-  MachineOperand *FlagUse = MI.findRegisterUseOperand(X86::EFLAGS);
-  if (!FlagUse) {
-if (MI.findRegisterDefOperand(X86::EFLAGS)) {
-  // If EFLAGS are defined, it's as-if they were killed. We can stop
-  // scanning here.
-  //
-  // NB!!! Many instructions only modify some flags. LLVM currently
-  // models this as clobbering all flags, but if that ever changes this
-  // will need to be carefully updated to handle that more complex
-  // logic.
-  FlagsKilled = true;
-  break;
-}
-continue;
-  }
-
-  DEBUG(dbgs() << "  Rewriting use: "; MI.dump());
+// Collect the basic blocks we need to scan. Typically this will just be
+// a single basic block but we may have to scan multiple blocks if the
+// EFLAGS co

[llvm-branch-commits] [llvm-branch] r332939 - Merge r330269 to fix egregiously bad codegeneration in the new EFLAGS lowering

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 20:03:11 2018
New Revision: 332939

URL: http://llvm.org/viewvc/llvm-project?rev=332939&view=rev
Log:
Merge r330269 to fix egregiously bad codegeneration in the new EFLAGS lowering
that was defferred to a follow-up commit by me not understanding how part of
the x86 backend worked.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll
llvm/branches/release_60/test/CodeGen/X86/copy-eflags.ll
llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir
llvm/branches/release_60/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
llvm/branches/release_60/test/CodeGen/X86/win64_frame.ll
llvm/branches/release_60/test/CodeGen/X86/x86-repmov-copy-eflags.ll

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 20:03:11 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771,330264
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771,330264,330269

Modified: llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=332939&r1=332938&r2=332939&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp Mon May 21 
20:03:11 2018
@@ -636,7 +636,7 @@ void X86FlagsCopyLoweringPass::insertTes
   // also allow us to select a shorter encoding of `testb %reg, %reg` when that
   // would be equivalent.
   auto TestI =
-  BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8ri)).addReg(Reg).addImm(-1);
+  BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
   (void)TestI;
   DEBUG(dbgs() << "test cond: "; TestI->dump());
   ++NumTestsInserted;

Modified: llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll?rev=332939&r1=332938&r2=332939&view=diff
==
--- llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll 
(original)
+++ llvm/branches/release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll Mon May 
21 20:03:11 2018
@@ -41,7 +41,7 @@ define i64 @test_intervening_call(i64* %
 ; 32-GOOD-RA-NEXT:pushl %eax
 ; 32-GOOD-RA-NEXT:calll bar
 ; 32-GOOD-RA-NEXT:addl $16, %esp
-; 32-GOOD-RA-NEXT:testb $-1, %bl
+; 32-GOOD-RA-NEXT:testb %bl, %bl
 ; 32-GOOD-RA-NEXT:jne .LBB0_3
 ; 32-GOOD-RA-NEXT:  # %bb.1: # %t
 ; 32-GOOD-RA-NEXT:movl $42, %eax
@@ -72,7 +72,7 @@ define i64 @test_intervening_call(i64* %
 ; 32-FAST-RA-NEXT:pushl %eax
 ; 32-FAST-RA-NEXT:calll bar
 ; 32-FAST-RA-NEXT:addl $16, %esp
-; 32-FAST-RA-NEXT:testb $-1, %bl
+; 32-FAST-RA-NEXT:testb %bl, %bl
 ; 32-FAST-RA-NEXT:jne .LBB0_3
 ; 32-FAST-RA-NEXT:  # %bb.1: # %t
 ; 32-FAST-RA-NEXT:movl $42, %eax
@@ -94,7 +94,7 @@ define i64 @test_intervening_call(i64* %
 ; 64-ALL-NEXT:setne %bl
 ; 64-ALL-NEXT:movq %rax, %rdi
 ; 64-ALL-NEXT:callq bar
-; 64-ALL-NEXT:testb $-1, %bl
+; 64-ALL-NEXT:testb %bl, %bl
 ; 64-ALL-NEXT:jn

[llvm-branch-commits] [llvm-branch] r332940 - Merge r332389 to pick up the fix for PR37431, a regression w/ the new EFLAGS lowering.

2018-05-21 Thread Chandler Carruth via llvm-branch-commits 
Author: chandlerc
Date: Mon May 21 20:06:34 2018
New Revision: 332940

URL: http://llvm.org/viewvc/llvm-project?rev=332940&view=rev
Log:
Merge r332389 to pick up the fix for PR37431, a regression w/ the new EFLAGS 
lowering.

Required switching $regname to %regname in the MIR test and regenerating the
CHECKs for the other test.

Modified:
llvm/branches/release_60/   (props changed)
llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/branches/release_60/test/CodeGen/X86/copy-eflags.ll
llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir

Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 20:06:34 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771,330264,330269
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771,330264,330269,332389

Modified: llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=332940&r1=332939&r2=332940&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp Mon May 21 
20:06:34 2018
@@ -127,6 +127,10 @@ private:
   MachineInstr &JmpI, CondRegArray &CondRegs);
   void rewriteCopy(MachineInstr &MI, MachineOperand &FlagUse,
MachineInstr &CopyDefI);
+  void rewriteSetCarryExtended(MachineBasicBlock &TestMBB,
+   MachineBasicBlock::iterator TestPos,
+   DebugLoc TestLoc, MachineInstr &SetBI,
+   MachineOperand &FlagUse, CondRegArray 
&CondRegs);
   void rewriteSetCC(MachineBasicBlock &TestMBB,
 MachineBasicBlock::iterator TestPos, DebugLoc TestLoc,
 MachineInstr &SetCCI, MachineOperand &FlagUse,
@@ -511,8 +515,7 @@ bool X86FlagsCopyLoweringPass::runOnMach
 } else if (MI.getOpcode() == TargetOpcode::COPY) {
   rewriteCopy(MI, *FlagUse, CopyDefI);
 } else {
-  // We assume that arithmetic instructions that use flags also def
-  // them.
+  // We assume all other instructions that use flags also def them.
   assert(MI.findRegisterDefOperand(X86::EFLAGS) &&
  "Expected a def of EFLAGS for this instruction!");
 
@@ -524,7 +527,23 @@ bool X86FlagsCopyLoweringPass::runOnMach
   // logic.
   FlagsKilled = true;
 
-  rewriteArithmetic(TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
+  switch (MI.getOpcode()) {
+  case X86::SETB_C8r:
+  case X86::SETB_C16r:
+  case X86::SETB_C32r:
+  case X86::SETB_C64r:
+// Use custom lowering for arithmetic that is merely extending the
+// carry flag. We model this as the SETB_C* pseudo instructions.
+rewriteSetCarryExtended(TestMBB, TestPos, TestLoc, MI, *FlagUse,
+CondRegs);
+break;
+
+  default:
+// Generically handle remaining uses as arithmetic instructions.
+rewriteArithmetic(TestMBB, TestPos, TestLoc, MI, *FlagUse,
+  CondRegs);
+break;
+  }
   break;
 }

[llvm-branch-commits] [clang] ff92274 - format

2024-12-11 Thread Chandler Carruth via llvm-branch-commits 

Author: Chandler Carruth
Date: 2024-12-12T01:56:05Z
New Revision: ff92274bb07a52dd05ce58e09bee582d4f96602d

URL: 
https://github.com/llvm/llvm-project/commit/ff92274bb07a52dd05ce58e09bee582d4f96602d
DIFF: 
https://github.com/llvm/llvm-project/commit/ff92274bb07a52dd05ce58e09bee582d4f96602d.diff

LOG: format

Added: 


Modified: 
clang/include/clang/Basic/Builtins.h
clang/include/clang/Basic/TargetInfo.h
clang/lib/Basic/Builtins.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/Builtins.h 
b/clang/include/clang/Basic/Builtins.h
index 89f65682ae5b41..e27d8ccce73664 100644
--- a/clang/include/clang/Basic/Builtins.h
+++ b/clang/include/clang/Basic/Builtins.h
@@ -103,9 +103,7 @@ class Context {
   llvm::StringRef getName(unsigned ID) const { return getRecord(ID).Name; }
 
   /// Get the type descriptor string for the specified builtin.
-  const char *getTypeString(unsigned ID) const {
-return getRecord(ID).Type;
-  }
+  const char *getTypeString(unsigned ID) const { return getRecord(ID).Type; }
 
   /// Return true if this function is a target-specific builtin.
   bool isTSBuiltin(unsigned ID) const {

diff  --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index 4420228793e95f..82bd537b242c1c 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1009,7 +1009,6 @@ class TargetInfo : public TransferrableTargetInfo,
   virtual void getTargetDefines(const LangOptions &Opts,
 MacroBuilder &Builder) const = 0;
 
-
   /// Return information about target-specific builtins for
   /// the current primary target, and info about which builtins are 
non-portable
   /// across the current set of primary and secondary targets.

diff  --git a/clang/lib/Basic/Builtins.cpp b/clang/lib/Basic/Builtins.cpp
index 25a601573698e7..8dd1888db29883 100644
--- a/clang/lib/Basic/Builtins.cpp
+++ b/clang/lib/Basic/Builtins.cpp
@@ -134,7 +134,7 @@ static bool builtinIsSupported(const Builtin::Info 
&BuiltinInfo,
 void Builtin::Context::initializeBuiltins(IdentifierTable &Table,
   const LangOptions& LangOpts) {
   // Step #1: mark all target-independent builtins with their ID's.
-  for (unsigned i = Builtin::NotBuiltin+1; i != Builtin::FirstTSBuiltin; ++i)
+  for (unsigned i = Builtin::NotBuiltin + 1; i != Builtin::FirstTSBuiltin; ++i)
 if (builtinIsSupported(BuiltinInfo[i], LangOpts)) {
   Table.get(BuiltinInfo[i].Name).setBuiltinID(i);
 }



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