[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Reduce TOC usage by merging internal and private global data (PR #101224)

2024-07-30 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan created 
https://github.com/llvm/llvm-project/pull/101224



This patch aims to reduce TOC usage by merging internal and private global data.

Moreover, we also add the GlobalMerge pass within the PPCTargetMachine 
pipeline, which is disabled by default. This transformation can be enabled by 
-ppc-global-merge.

>From 61a41df3ee9f90484f7a7f0fd576cd4646710d7c Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:53:15 -0500
Subject: [PATCH] [PowerPC][GlobalMerge] Reduce TOC usage by merging internal
 and private global data

This patch aims to reduce TOC usage by merging internal and private global data.

Moreover, we also add the GlobalMerge pass within the PPCTargetMachine pipeline,
which is disabled by default. This transformation can be enabled by 
-ppc-global-merge.
---
 llvm/include/llvm/CodeGen/GlobalMerge.h  |  4 +++
 llvm/include/llvm/CodeGen/Passes.h   |  4 ++-
 llvm/lib/CodeGen/GlobalMerge.cpp | 27 
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 13 ++
 llvm/test/CodeGen/PowerPC/merge-private.ll   | 20 +++
 5 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/GlobalMerge.h 
b/llvm/include/llvm/CodeGen/GlobalMerge.h
index 13ad67d4544bc..ef767d548dc6e 100644
--- a/llvm/include/llvm/CodeGen/GlobalMerge.h
+++ b/llvm/include/llvm/CodeGen/GlobalMerge.h
@@ -28,6 +28,10 @@ struct GlobalMergeOptions {
   bool MergeConst = false;
   /// Whether we should merge global variables that have external linkage.
   bool MergeExternal = true;
+  /// Whether we should merge global variables that have private linkage.
+  bool MergePrivateGlobals = false;
+  /// Whether we should merge constant global variables.
+  bool MergeConstantGlobals = false;
   /// Whether we should try to optimize for size only.
   /// Currently, this applies a dead simple heuristic: only consider globals
   /// used in minsize functions for merging.
diff --git a/llvm/include/llvm/CodeGen/Passes.h 
b/llvm/include/llvm/CodeGen/Passes.h
index cafb9781698a2..b401a8d9f10fd 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -476,7 +476,9 @@ namespace llvm {
   ///
   Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset,
   bool OnlyOptimizeForSize = false,
-  bool MergeExternalByDefault = false);
+  bool MergeExternalByDefault = false,
+  bool MergePrivateByDefault = false,
+  bool MergeConstantByDefault = false);
 
   /// This pass splits the stack into a safe stack and an unsafe stack to
   /// protect against stack-based overflow vulnerabilities.
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index e420c2bb7a25e..4056860fddd93 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -196,11 +196,14 @@ class GlobalMerge : public FunctionPass {
   }
 
   explicit GlobalMerge(const TargetMachine *TM, unsigned MaximalOffset,
-   bool OnlyOptimizeForSize, bool MergeExternalGlobals)
+   bool OnlyOptimizeForSize, bool MergeExternalGlobals,
+   bool MergePrivateGlobals, bool MergeConstantGlobals)
   : FunctionPass(ID), TM(TM) {
 Opt.MaxOffset = MaximalOffset;
 Opt.SizeOnly = OnlyOptimizeForSize;
 Opt.MergeExternal = MergeExternalGlobals;
+Opt.MergePrivateGlobals = MergePrivateGlobals;
+Opt.MergeConstantGlobals = MergeConstantGlobals;
 initializeGlobalMergePass(*PassRegistry::getPassRegistry());
   }
 
@@ -475,7 +478,8 @@ bool GlobalMergeImpl::doMerge(const 
SmallVectorImpl &Globals,
   auto &DL = M.getDataLayout();
 
   LLVM_DEBUG(dbgs() << " Trying to merge set, starts with #"
-<< GlobalSet.find_first() << "\n");
+<< GlobalSet.find_first() << ", total of " << 
Globals.size()
+<< "\n");
 
   bool Changed = false;
   ssize_t i = GlobalSet.find_first();
@@ -551,6 +555,8 @@ bool GlobalMergeImpl::doMerge(const 
SmallVectorImpl &Globals,
 MergedGV->setAlignment(MaxAlign);
 MergedGV->setSection(Globals[i]->getSection());
 
+LLVM_DEBUG(dbgs() << "MergedGV:  " << *MergedGV << "\n");
+
 const StructLayout *MergedLayout = DL.getStructLayout(MergedTy);
 for (ssize_t k = i, idx = 0; k != j; k = GlobalSet.find_next(k), ++idx) {
   GlobalValue::LinkageTypes Linkage = Globals[k]->getLinkage();
@@ -700,6 +706,11 @@ bool GlobalMergeImpl::run(Module &M) {
   else
 Globals[{AddressSpace, Section}].push_back(&GV);
 }
+LLVM_DEBUG(dbgs() << "GV "
+  << ((DL.getTypeAllocSize(Ty) < Opt.MaxOffset)
+  ? "to merge: "
+  : "not to merge: ")
+  << GV << "\n");
   }
 
   for (auto &P : Globals)

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)

2024-07-30 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan created 
https://github.com/llvm/llvm-project/pull/101226

This patch turns on the GlobalMerge pass by default on AIX and updates LIT 
tests accordingly.

>From 2dd0302dbe47b752d0452bb221fbea3a5dcc8b14 Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:55:34 -0500
Subject: [PATCH] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX

This patch turns on the GlobalMerge pass by default on AIX and updates LIT
tests accordingly.
---
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp| 5 -
 llvm/test/CodeGen/PowerPC/merge-private.ll  | 6 ++
 llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll  | 4 ++--
 llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll | 2 +-
 4 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp 
b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index e4045ec304435..f975d1495543b 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -500,7 +500,10 @@ void PPCPassConfig::addIRPasses() {
 }
 
 bool PPCPassConfig::addPreISel() {
-  if (EnableGlobalMerge)
+  if ((EnableGlobalMerge.getNumOccurrences() > 0)
+  ? EnableGlobalMerge
+  : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))
 addPass(createGlobalMergePass(TM, GlobalMergeMaxOffset, false, false, true,
   true));
 
diff --git a/llvm/test/CodeGen/PowerPC/merge-private.ll 
b/llvm/test/CodeGen/PowerPC/merge-private.ll
index 6ed2d6dfc542b..0ca706abb275f 100644
--- a/llvm/test/CodeGen/PowerPC/merge-private.ll
+++ b/llvm/test/CodeGen/PowerPC/merge-private.ll
@@ -11,6 +11,12 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN: -ppc-asm-full-reg-names -ppc-global-merge=true < %s | FileCheck %s \
 ; RUN: --check-prefix=LINUX64BE
+; The below run line is added to ensure that the assembly corresponding to
+; the following check-prefix is generated by default on AIX (without any
+; options).
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN: --check-prefix=AIX64
 
 @.str = private unnamed_addr constant [15 x i8] c"Private global\00", align 1
 @str = internal constant [16 x i8] c"Internal global\00", align 1
diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll 
b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
index 81147d10cde6e..833ed9fa65acf 100644
--- a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
+++ b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX32,AIXDATA
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX64,AIXDATA
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=LINUX64BE,LINUXDATA
diff --git a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll 
b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
index 5432b59d583ba..1a467ec72a75d 100644
--- a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
+++ b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
@@ -5,7 +5,7 @@
 ;; AIX assembly syntax.
 
 ; REQUIRES: powerpc-registered-target
-; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff < %s
+; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff 
-ppc-global-merge=false < %s
 ; RUN: llvm-symbolizer --obj=%t 'DATA 0x60' 'DATA 0x61' 'DATA 0x64' 'DATA 
0X68' \
 ; RUN:   'DATA 0x90' 'DATA 0x94' 'DATA 0X98' | \
 ; RUN:   FileCheck %s

___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Reduce TOC usage by merging internal and private global data (PR #101224)

2024-08-01 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan updated 
https://github.com/llvm/llvm-project/pull/101224

>From 7a0a6ba50edda592bf3acc1b5ae0d8d2272fc8f2 Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:53:15 -0500
Subject: [PATCH 1/2] [PowerPC][GlobalMerge] Reduce TOC usage by merging
 internal and private global data

This patch aims to reduce TOC usage by merging internal and private global data.

Moreover, we also add the GlobalMerge pass within the PPCTargetMachine pipeline,
which is disabled by default. This transformation can be enabled by 
-ppc-global-merge.
---
 llvm/include/llvm/CodeGen/GlobalMerge.h  |  4 +++
 llvm/include/llvm/CodeGen/Passes.h   |  4 ++-
 llvm/lib/CodeGen/GlobalMerge.cpp | 27 
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 13 ++
 llvm/test/CodeGen/PowerPC/merge-private.ll   | 20 +++
 5 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/GlobalMerge.h 
b/llvm/include/llvm/CodeGen/GlobalMerge.h
index 13ad67d4544bc..ef767d548dc6e 100644
--- a/llvm/include/llvm/CodeGen/GlobalMerge.h
+++ b/llvm/include/llvm/CodeGen/GlobalMerge.h
@@ -28,6 +28,10 @@ struct GlobalMergeOptions {
   bool MergeConst = false;
   /// Whether we should merge global variables that have external linkage.
   bool MergeExternal = true;
+  /// Whether we should merge global variables that have private linkage.
+  bool MergePrivateGlobals = false;
+  /// Whether we should merge constant global variables.
+  bool MergeConstantGlobals = false;
   /// Whether we should try to optimize for size only.
   /// Currently, this applies a dead simple heuristic: only consider globals
   /// used in minsize functions for merging.
diff --git a/llvm/include/llvm/CodeGen/Passes.h 
b/llvm/include/llvm/CodeGen/Passes.h
index cafb9781698a2..b401a8d9f10fd 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -476,7 +476,9 @@ namespace llvm {
   ///
   Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset,
   bool OnlyOptimizeForSize = false,
-  bool MergeExternalByDefault = false);
+  bool MergeExternalByDefault = false,
+  bool MergePrivateByDefault = false,
+  bool MergeConstantByDefault = false);
 
   /// This pass splits the stack into a safe stack and an unsafe stack to
   /// protect against stack-based overflow vulnerabilities.
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index 8aa4345cfd6df..46bda37ea45a5 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -196,11 +196,14 @@ class GlobalMerge : public FunctionPass {
   }
 
   explicit GlobalMerge(const TargetMachine *TM, unsigned MaximalOffset,
-   bool OnlyOptimizeForSize, bool MergeExternalGlobals)
+   bool OnlyOptimizeForSize, bool MergeExternalGlobals,
+   bool MergePrivateGlobals, bool MergeConstantGlobals)
   : FunctionPass(ID), TM(TM) {
 Opt.MaxOffset = MaximalOffset;
 Opt.SizeOnly = OnlyOptimizeForSize;
 Opt.MergeExternal = MergeExternalGlobals;
+Opt.MergePrivateGlobals = MergePrivateGlobals;
+Opt.MergeConstantGlobals = MergeConstantGlobals;
 initializeGlobalMergePass(*PassRegistry::getPassRegistry());
   }
 
@@ -475,7 +478,8 @@ bool GlobalMergeImpl::doMerge(const 
SmallVectorImpl &Globals,
   auto &DL = M.getDataLayout();
 
   LLVM_DEBUG(dbgs() << " Trying to merge set, starts with #"
-<< GlobalSet.find_first() << "\n");
+<< GlobalSet.find_first() << ", total of " << 
Globals.size()
+<< "\n");
 
   bool Changed = false;
   ssize_t i = GlobalSet.find_first();
@@ -551,6 +555,8 @@ bool GlobalMergeImpl::doMerge(const 
SmallVectorImpl &Globals,
 MergedGV->setAlignment(MaxAlign);
 MergedGV->setSection(Globals[i]->getSection());
 
+LLVM_DEBUG(dbgs() << "MergedGV:  " << *MergedGV << "\n");
+
 const StructLayout *MergedLayout = DL.getStructLayout(MergedTy);
 for (ssize_t k = i, idx = 0; k != j; k = GlobalSet.find_next(k), ++idx) {
   GlobalValue::LinkageTypes Linkage = Globals[k]->getLinkage();
@@ -700,6 +706,11 @@ bool GlobalMergeImpl::run(Module &M) {
   else
 Globals[{AddressSpace, Section}].push_back(&GV);
 }
+LLVM_DEBUG(dbgs() << "GV "
+  << ((DL.getTypeAllocSize(Ty) < Opt.MaxOffset)
+  ? "to merge: "
+  : "not to merge: ")
+  << GV << "\n");
   }
 
   for (auto &P : Globals)
@@ -710,7 +721,7 @@ bool GlobalMergeImpl::run(Module &M) {
 if (P.second.size() > 1)
   Changed |= doMerge(P.second, M, false, P.first.first);
 
-  if (EnableGlobalMergeOnConst)
+  if (Opt.MergeConstantGlobals)
 for (auto &P : ConstGlobal

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)

2024-08-01 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan updated 
https://github.com/llvm/llvm-project/pull/101226

>From e18bc365d7d1dbea3b5a08983a9635a46e0c81af Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:55:34 -0500
Subject: [PATCH] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX

This patch turns on the GlobalMerge pass by default on AIX and updates LIT
tests accordingly.
---
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp| 5 -
 llvm/test/CodeGen/PowerPC/merge-private.ll  | 6 ++
 llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll  | 4 ++--
 llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll | 2 +-
 4 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp 
b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 6a50223048281..de63c2bf61c43 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -500,7 +500,10 @@ void PPCPassConfig::addIRPasses() {
 }
 
 bool PPCPassConfig::addPreISel() {
-  if (EnableGlobalMerge)
+  if ((EnableGlobalMerge.getNumOccurrences() > 0)
+  ? EnableGlobalMerge
+  : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))
 addPass(createGlobalMergePass(TM, GlobalMergeMaxOffset, false, false,
   true));
 
diff --git a/llvm/test/CodeGen/PowerPC/merge-private.ll 
b/llvm/test/CodeGen/PowerPC/merge-private.ll
index 6ed2d6dfc542b..0ca706abb275f 100644
--- a/llvm/test/CodeGen/PowerPC/merge-private.ll
+++ b/llvm/test/CodeGen/PowerPC/merge-private.ll
@@ -11,6 +11,12 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN: -ppc-asm-full-reg-names -ppc-global-merge=true < %s | FileCheck %s \
 ; RUN: --check-prefix=LINUX64BE
+; The below run line is added to ensure that the assembly corresponding to
+; the following check-prefix is generated by default on AIX (without any
+; options).
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN: --check-prefix=AIX64
 
 @.str = private unnamed_addr constant [15 x i8] c"Private global\00", align 1
 @str = internal constant [16 x i8] c"Internal global\00", align 1
diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll 
b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
index 81147d10cde6e..833ed9fa65acf 100644
--- a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
+++ b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX32,AIXDATA
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX64,AIXDATA
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=LINUX64BE,LINUXDATA
diff --git a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll 
b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
index 5432b59d583ba..1a467ec72a75d 100644
--- a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
+++ b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
@@ -5,7 +5,7 @@
 ;; AIX assembly syntax.
 
 ; REQUIRES: powerpc-registered-target
-; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff < %s
+; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff 
-ppc-global-merge=false < %s
 ; RUN: llvm-symbolizer --obj=%t 'DATA 0x60' 'DATA 0x61' 'DATA 0x64' 'DATA 
0X68' \
 ; RUN:   'DATA 0x90' 'DATA 0x94' 'DATA 0X98' | \
 ; RUN:   FileCheck %s

___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)

2024-08-01 Thread Amy Kwan via llvm-branch-commits 


@@ -500,7 +500,10 @@ void PPCPassConfig::addIRPasses() {
 }
 
 bool PPCPassConfig::addPreISel() {
-  if (EnableGlobalMerge)
+  if ((EnableGlobalMerge.getNumOccurrences() > 0)
+  ? EnableGlobalMerge
+  : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))

amy-kwan wrote:

Hmm, I thought this could be simplified, too.

However, unless I am misunderstanding or I did something wrong, it seems the 
original code is still needed or else `xcoff-symbolize-data.ll` fails:
```
llvm-project/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll:38:10: 
error: CHECK: expected string not found in input
; CHECK: f()::function_global
 ^
:16:1: note: scanning from here

^
:17:1: note: possible intended match here
L.._MergedGlobals
^
```
I can see in that test that it seems we're still merging (with this code 
suggestion) since the `_MergedGlobals` is present:
```
$ llvm-symbolizer 
--obj=/data/amyk/llvm_trunk/build/test/DebugInfo/Symbolize/XCOFF/Output/xcoff-symbolize-data.ll.tmp
 'DATA 0x60' 'DATA 0x61' 'DATA 0x64' 'DATA 0X68''DATA 0x90' 'DATA 0x94'
bss_global
96 4
/t.cpp:1

bss_global
96 4
/t.cpp:1

data_global
100 4
/t.cpp:2

str
104 4
/t.cpp:4

L.._MergedGlobals
144 8
/t.cpp:13

L.._MergedGlobals
144 8
/t.cpp:12
```

Any opinions regarding this and/or keeping the original code, @chenzheng1030 
@redstar?

https://github.com/llvm/llvm-project/pull/101226
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Reduce TOC usage by merging internal and private global data (PR #101224)

2024-08-02 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan updated 
https://github.com/llvm/llvm-project/pull/101224

>From 4e4a4da18b5b262242cb7322820717af16e44ddb Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:53:15 -0500
Subject: [PATCH 1/2] [PowerPC][GlobalMerge] Reduce TOC usage by merging
 internal and private global data

This patch aims to reduce TOC usage by merging internal and private global data.

Moreover, we also add the GlobalMerge pass within the PPCTargetMachine pipeline,
which is disabled by default. This transformation can be enabled by 
-ppc-global-merge.
---
 llvm/include/llvm/CodeGen/GlobalMerge.h  |  4 +++
 llvm/include/llvm/CodeGen/Passes.h   |  4 ++-
 llvm/lib/CodeGen/GlobalMerge.cpp | 27 
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 13 ++
 llvm/test/CodeGen/PowerPC/merge-private.ll   | 20 +++
 5 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/GlobalMerge.h 
b/llvm/include/llvm/CodeGen/GlobalMerge.h
index 13ad67d4544bc..ef767d548dc6e 100644
--- a/llvm/include/llvm/CodeGen/GlobalMerge.h
+++ b/llvm/include/llvm/CodeGen/GlobalMerge.h
@@ -28,6 +28,10 @@ struct GlobalMergeOptions {
   bool MergeConst = false;
   /// Whether we should merge global variables that have external linkage.
   bool MergeExternal = true;
+  /// Whether we should merge global variables that have private linkage.
+  bool MergePrivateGlobals = false;
+  /// Whether we should merge constant global variables.
+  bool MergeConstantGlobals = false;
   /// Whether we should try to optimize for size only.
   /// Currently, this applies a dead simple heuristic: only consider globals
   /// used in minsize functions for merging.
diff --git a/llvm/include/llvm/CodeGen/Passes.h 
b/llvm/include/llvm/CodeGen/Passes.h
index cafb9781698a2..b401a8d9f10fd 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -476,7 +476,9 @@ namespace llvm {
   ///
   Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset,
   bool OnlyOptimizeForSize = false,
-  bool MergeExternalByDefault = false);
+  bool MergeExternalByDefault = false,
+  bool MergePrivateByDefault = false,
+  bool MergeConstantByDefault = false);
 
   /// This pass splits the stack into a safe stack and an unsafe stack to
   /// protect against stack-based overflow vulnerabilities.
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index 8aa4345cfd6df..46bda37ea45a5 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -196,11 +196,14 @@ class GlobalMerge : public FunctionPass {
   }
 
   explicit GlobalMerge(const TargetMachine *TM, unsigned MaximalOffset,
-   bool OnlyOptimizeForSize, bool MergeExternalGlobals)
+   bool OnlyOptimizeForSize, bool MergeExternalGlobals,
+   bool MergePrivateGlobals, bool MergeConstantGlobals)
   : FunctionPass(ID), TM(TM) {
 Opt.MaxOffset = MaximalOffset;
 Opt.SizeOnly = OnlyOptimizeForSize;
 Opt.MergeExternal = MergeExternalGlobals;
+Opt.MergePrivateGlobals = MergePrivateGlobals;
+Opt.MergeConstantGlobals = MergeConstantGlobals;
 initializeGlobalMergePass(*PassRegistry::getPassRegistry());
   }
 
@@ -475,7 +478,8 @@ bool GlobalMergeImpl::doMerge(const 
SmallVectorImpl &Globals,
   auto &DL = M.getDataLayout();
 
   LLVM_DEBUG(dbgs() << " Trying to merge set, starts with #"
-<< GlobalSet.find_first() << "\n");
+<< GlobalSet.find_first() << ", total of " << 
Globals.size()
+<< "\n");
 
   bool Changed = false;
   ssize_t i = GlobalSet.find_first();
@@ -551,6 +555,8 @@ bool GlobalMergeImpl::doMerge(const 
SmallVectorImpl &Globals,
 MergedGV->setAlignment(MaxAlign);
 MergedGV->setSection(Globals[i]->getSection());
 
+LLVM_DEBUG(dbgs() << "MergedGV:  " << *MergedGV << "\n");
+
 const StructLayout *MergedLayout = DL.getStructLayout(MergedTy);
 for (ssize_t k = i, idx = 0; k != j; k = GlobalSet.find_next(k), ++idx) {
   GlobalValue::LinkageTypes Linkage = Globals[k]->getLinkage();
@@ -700,6 +706,11 @@ bool GlobalMergeImpl::run(Module &M) {
   else
 Globals[{AddressSpace, Section}].push_back(&GV);
 }
+LLVM_DEBUG(dbgs() << "GV "
+  << ((DL.getTypeAllocSize(Ty) < Opt.MaxOffset)
+  ? "to merge: "
+  : "not to merge: ")
+  << GV << "\n");
   }
 
   for (auto &P : Globals)
@@ -710,7 +721,7 @@ bool GlobalMergeImpl::run(Module &M) {
 if (P.second.size() > 1)
   Changed |= doMerge(P.second, M, false, P.first.first);
 
-  if (EnableGlobalMergeOnConst)
+  if (Opt.MergeConstantGlobals)
 for (auto &P : ConstGlobal

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)

2024-08-02 Thread Amy Kwan via llvm-branch-commits 


@@ -500,7 +500,10 @@ void PPCPassConfig::addIRPasses() {
 }
 
 bool PPCPassConfig::addPreISel() {
-  if (EnableGlobalMerge)
+  if ((EnableGlobalMerge.getNumOccurrences() > 0)
+  ? EnableGlobalMerge
+  : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))

amy-kwan wrote:

Thanks a lot, Kai! I looked into this a bit and I agree. That would be the 
behaviour that we are after here, so I will keep the condition as is, and add a 
comment.

https://github.com/llvm/llvm-project/pull/101226
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)

2024-08-02 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan updated 
https://github.com/llvm/llvm-project/pull/101226

>From ffa2c5a982a9f2355ecdbef73dac9be1ba001210 Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:55:34 -0500
Subject: [PATCH] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX

This patch turns on the GlobalMerge pass by default on AIX and updates LIT
tests accordingly.
---
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp   | 7 ++-
 llvm/test/CodeGen/PowerPC/merge-private.ll | 6 ++
 llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll | 4 ++--
 .../test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll | 2 +-
 4 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp 
b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 6a50223048281..6ee25b1816892 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -500,7 +500,12 @@ void PPCPassConfig::addIRPasses() {
 }
 
 bool PPCPassConfig::addPreISel() {
-  if (EnableGlobalMerge)
+  // The GlobalMerge pass is intended to be on by default on AIX.
+  // Specifying the command line option overrides the AIX default.
+  if ((EnableGlobalMerge.getNumOccurrences() > 0)
+  ? EnableGlobalMerge
+  : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))
 addPass(createGlobalMergePass(TM, GlobalMergeMaxOffset, false, false,
   true));
 
diff --git a/llvm/test/CodeGen/PowerPC/merge-private.ll 
b/llvm/test/CodeGen/PowerPC/merge-private.ll
index 6ed2d6dfc542b..0ca706abb275f 100644
--- a/llvm/test/CodeGen/PowerPC/merge-private.ll
+++ b/llvm/test/CodeGen/PowerPC/merge-private.ll
@@ -11,6 +11,12 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN: -ppc-asm-full-reg-names -ppc-global-merge=true < %s | FileCheck %s \
 ; RUN: --check-prefix=LINUX64BE
+; The below run line is added to ensure that the assembly corresponding to
+; the following check-prefix is generated by default on AIX (without any
+; options).
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN: --check-prefix=AIX64
 
 @.str = private unnamed_addr constant [15 x i8] c"Private global\00", align 1
 @str = internal constant [16 x i8] c"Internal global\00", align 1
diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll 
b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
index 81147d10cde6e..833ed9fa65acf 100644
--- a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
+++ b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX32,AIXDATA
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX64,AIXDATA
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=LINUX64BE,LINUXDATA
diff --git a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll 
b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
index 5432b59d583ba..1a467ec72a75d 100644
--- a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
+++ b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
@@ -5,7 +5,7 @@
 ;; AIX assembly syntax.
 
 ; REQUIRES: powerpc-registered-target
-; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff < %s
+; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff 
-ppc-global-merge=false < %s
 ; RUN: llvm-symbolizer --obj=%t 'DATA 0x60' 'DATA 0x61' 'DATA 0x64' 'DATA 
0X68' \
 ; RUN:   'DATA 0x90' 'DATA 0x94' 'DATA 0X98' | \
 ; RUN:   FileCheck %s

___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX (PR #101226)

2024-08-13 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan updated 
https://github.com/llvm/llvm-project/pull/101226

>From a5d47e331e3bd754db092c194a5ca5b25ff99011 Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 30 Jul 2024 12:55:34 -0500
Subject: [PATCH] [PowerPC][GlobalMerge] Enable GlobalMerge by default on AIX

This patch turns on the GlobalMerge pass by default on AIX and updates LIT
tests accordingly.
---
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp   | 7 ++-
 llvm/test/CodeGen/PowerPC/merge-private.ll | 6 ++
 llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll | 4 ++--
 .../test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll | 2 +-
 4 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp 
b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 6a502230482816..6ee25b1816892a 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -500,7 +500,12 @@ void PPCPassConfig::addIRPasses() {
 }
 
 bool PPCPassConfig::addPreISel() {
-  if (EnableGlobalMerge)
+  // The GlobalMerge pass is intended to be on by default on AIX.
+  // Specifying the command line option overrides the AIX default.
+  if ((EnableGlobalMerge.getNumOccurrences() > 0)
+  ? EnableGlobalMerge
+  : (TM->getTargetTriple().isOSAIX() &&
+ getOptLevel() != CodeGenOptLevel::None))
 addPass(createGlobalMergePass(TM, GlobalMergeMaxOffset, false, false,
   true));
 
diff --git a/llvm/test/CodeGen/PowerPC/merge-private.ll 
b/llvm/test/CodeGen/PowerPC/merge-private.ll
index 6ed2d6dfc542b7..0ca706abb275fc 100644
--- a/llvm/test/CodeGen/PowerPC/merge-private.ll
+++ b/llvm/test/CodeGen/PowerPC/merge-private.ll
@@ -11,6 +11,12 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN: -ppc-asm-full-reg-names -ppc-global-merge=true < %s | FileCheck %s \
 ; RUN: --check-prefix=LINUX64BE
+; The below run line is added to ensure that the assembly corresponding to
+; the following check-prefix is generated by default on AIX (without any
+; options).
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN: --check-prefix=AIX64
 
 @.str = private unnamed_addr constant [15 x i8] c"Private global\00", align 1
 @str = internal constant [16 x i8] c"Internal global\00", align 1
diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll 
b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
index 81147d10cde6e7..833ed9fa65acf1 100644
--- a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
+++ b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX32,AIXDATA
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 
-enable-global-merge=false \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=AIX64,AIXDATA
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s 
--check-prefixes=LINUX64BE,LINUXDATA
diff --git a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll 
b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
index 5432b59d583bac..1a467ec72a75da 100644
--- a/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
+++ b/llvm/test/DebugInfo/Symbolize/XCOFF/xcoff-symbolize-data.ll
@@ -5,7 +5,7 @@
 ;; AIX assembly syntax.
 
 ; REQUIRES: powerpc-registered-target
-; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff < %s
+; RUN: llc -filetype=obj -o %t -mtriple=powerpc-aix-ibm-xcoff 
-ppc-global-merge=false < %s
 ; RUN: llvm-symbolizer --obj=%t 'DATA 0x60' 'DATA 0x61' 'DATA 0x64' 'DATA 
0X68' \
 ; RUN:   'DATA 0x90' 'DATA 0x94' 'DATA 0X98' | \
 ; RUN:   FileCheck %s

___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: Revert "[CGData] llvm-cgdata (#89884)" (PR #103886)

2024-08-14 Thread Amy Kwan via llvm-branch-commits 

amy-kwan wrote:

I've made a request for backporting to resolve the AIX LIT failures:
```
  LLVM :: tools/llvm-cgdata/merge-archive.test
  LLVM :: tools/llvm-cgdata/merge-concat.test
  LLVM :: tools/llvm-cgdata/merge-double.test
  LLVM :: tools/llvm-cgdata/merge-single.test
```
FYI @tru @azhan92 @kamaub @gulfemsavrun 

https://github.com/llvm/llvm-project/pull/103886
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: Revert "[CGData] llvm-cgdata (#89884)" (PR #103886)

2024-08-15 Thread Amy Kwan via llvm-branch-commits 

amy-kwan wrote:

> So we should remove this tool from the 19.x release? Can someone confirm?

@kyulee-com @thevinster Are you two able to help confirm this?

https://github.com/llvm/llvm-project/pull/103886
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: Revert "[CGData] llvm-cgdata (#89884)" (PR #103886)

2024-08-16 Thread Amy Kwan via llvm-branch-commits 

amy-kwan wrote:

> > > So we should remove this tool from the 19.x release? Can someone confirm?
> > 
> > 
> > @kyulee-com @thevinster Are you two able to help confirm this?
> 
> Yeah. I think we should remove this from the release as it was reverted. We 
> plan to re-land it via #101461 once it gets approved.

Thanks for confirming! If we can get this PR reviewed so @tru can help merge 
this, that would be awesome.

https://github.com/llvm/llvm-project/pull/103886
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Add AIX and PPC Clang/LLVM release notes for LLVM 19. (PR #105099)

2024-08-20 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan milestoned 
https://github.com/llvm/llvm-project/pull/105099
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Add AIX and PPC Clang/LLVM release notes for LLVM 19. (PR #105099)

2024-08-20 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan created 
https://github.com/llvm/llvm-project/pull/105099

This PR adds AIX and PPC Clang/LLVM release notes for LLVM 19 to the 
`release/19.x` branch.

>From 1aa3221f169f8be0fbe6156d97543c326f6ef97a Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 20 Aug 2024 10:30:09 -0500
Subject: [PATCH] Add AIX/PPC Clang/LLVM release notes for LLVM 19.

---
 clang/docs/ReleaseNotes.rst | 17 +
 llvm/docs/ReleaseNotes.rst  | 14 ++
 2 files changed, 31 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 17ddbfe910f878..b68b823ae6761d 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1276,6 +1276,14 @@ RISC-V Support
   accesses may be created. ``-m[no-]strict-align`` applies to both scalar and
   vector.
 
+PowerPC Support
+^^^
+
+- Clang now emits errors for impossible ``__attribute__((musttail))``.
+- Added support for ``-mcpu=[pwr11 | power11]`` and ``-mtune=[pwr11 | 
power11]``.
+- Added support for ``builtin_cpu_supports`` on AIX, along with a subset of
+  features that can be queried.
+
 CUDA/HIP Language Changes
 ^
 
@@ -1294,6 +1302,14 @@ AIX Support
   base is encoded as an immediate operand.
   This access sequence is not used for TLS variables larger than 32KB, and is
   currently only supported on 64-bit mode.
+- Introduced the options ``-mtocdata/-mno-tocdata`` to enable/disable TOC data
+  transformations for the listed suitable variables.
+- Introduced the ``-maix-shared-lib-tls-model-opt`` option to enable the tuning
+  of changing local-dynamic mode access(es) to initial-exec access(es) at the
+  function level on 64-bit mode.
+- Clang now emits errors for ``-gdwarf-5``.
+- Added the support of the OpenMP runtime libomp on AIX. OpenMP applications 
can be
+  compiled with ``-fopenmp`` and execute on AIX.
 
 NetBSD Support
 ^^
@@ -1451,6 +1467,7 @@ OpenMP Support
 --
 
 - Added support for the `[[omp::assume]]` attribute.
+- AIX added an include directory for ``omp.h`` at 
``/opt/IBM/openxlCSDK/include/openmp``.
 
 Additional Information
 ==
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 60b6c6e786df89..ac7bdf723a168d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -113,6 +113,8 @@ Changes to TableGen
 Changes to Interprocedural Optimizations
 
 
+* Hot cold region splitting analysis improvements for overlapping cold regions.
+
 Changes to the AArch64 Backend
 --
 
@@ -194,6 +196,16 @@ Changes to the MIPS Backend
 Changes to the PowerPC Backend
 --
 
+* PPC big-endian Linux now supports ``-fpatchable-function-entry``.
+* PPC AIX now supports local-dynamic TLS mode.
+* PPC AIX saves the Git revision in binaries when built with 
LLVM_APPEND_VC_REV=ON.
+* PPC AIX now supports toc-data attribute for large code model.
+* PPC AIX now supports passing arguments by value having greater alignment than
+  the pointer size. Currently only compatible with the IBM XL C compiler.
+* Add support for the per global code model attribute on AIX.
+* Support spilling non-volatile registers for traceback table accuracy on AIX.
+* Codegen improvements and bug fixes.
+
 Changes to the RISC-V Backend
 -
 
@@ -436,6 +448,8 @@ Changes to the LLVM tools
   be disabled by ``--no-verify-note-sections``. (`#90458
   `).
 
+* llvm-objdump now supports the ``--file-headers`` option for XCOFF object 
files.
+
 Changes to LLDB
 -
 

___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Add AIX and PPC Clang/LLVM release notes for LLVM 19. (PR #105099)

2024-08-20 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/105099
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/81631
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [PowerPC] Fix mask for __st[d/w/h/b]cx builtins (#104453) (PR #106085)

2024-08-26 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/106085
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] 68e77f1 - [ReleaseNotes]: Add PowerPC release notes for LLVM 15

2022-08-28 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-08-28T13:56:39-05:00
New Revision: 68e77f15953a9153c8c4a566297178df9b17aa9b

URL: 
https://github.com/llvm/llvm-project/commit/68e77f15953a9153c8c4a566297178df9b17aa9b
DIFF: 
https://github.com/llvm/llvm-project/commit/68e77f15953a9153c8c4a566297178df9b17aa9b.diff

LOG: [ReleaseNotes]: Add PowerPC release notes for LLVM 15

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
lld/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 8d5de9dc0b11e..75ea617a554bc 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -320,6 +320,11 @@ Improvements to Clang's diagnostics
   conversions now defaults to an error in all C language modes. It may be
   downgraded to a warning with ``-Wno-error=int-conversion``, or disabled
   entirely with ``-Wno-int-conversion``.
+- Deprecated lax vector conversions for Altivec vectors.
+  The default behaviour with respect to these conversions
+  will switch to disable them in an upcoming release.
+- On AIX, only emit XL compatibility warning when 16 byte aligned structs are
+  pass-by-value function arguments.
 
 
 Non-comprehensive list of changes in this release

diff  --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 5819d67d32971..80d89984f5df0 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -212,6 +212,8 @@ Fixes
   errors. (`D122624 `_)
 * Fixed handling of relocatable object files within frameworks.
   (`D114841 `_)
+* Fixed the PPC64R2SaveStub to only use non-pc-relative code.
+  (`D129580 `_)
 
 WebAssembly Improvements
 

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c1aa8f9fc64ee..aadd542fe66c2 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -115,6 +115,12 @@ Changes to building LLVM
 Changes to TableGen
 ---
 
+Changes to Loop Optimizations
+-
+
+* Loop interchange legality and cost model improvements
+
+
 Changes to the AArch64 Backend
 --
 
@@ -171,7 +177,25 @@ Changes to the MIPS Backend
 Changes to the PowerPC Backend
 --
 
-* ...
+Common PowerPC improvements:
+* Add a new post instruction selection pass to generate CTR loops.
+* Add SSE4 and BMI compatible intrinsics implementation.
+* Supported 16-byte lock free atomics on PowerPC8 and up.
+* Supported atomic load/store for pointer types.
+* Supported stack size larger than 2G
+* Add __builtin_min/__builtin_max/__abs builtins.
+* Code generation improvements for splat load/vector shuffle/mulli, etc.
+* Emit VSX instructions for vector loads and stores regardless of alignment.
+* The mcpu=future has its own ISA now (FutureISA).
+* Added the ppc-set-dscr option to set the Data Stream Control Register (DSCR).
+* Bug fixes.
+
+AIX improvements:
+* Supported 64 bit XCOFF for integrated-as path.
+* Supported X86-compatible vector intrinsics.
+* Program code csect default alignment now is 32-byte.
+* Supported auxiliary header in integrated-as path.
+* Improved alias symbol handling.
 
 Changes to the RISC-V Backend
 -
@@ -296,8 +320,25 @@ Changes to the LLVM tools
 * :doc:`llvm-objcopy ` has removed support for the 
legacy ``zlib-gnu`` format.
 * :doc:`llvm-objcopy ` now allows 
``--set-section-flags src=... --rename-section src=tst``.
   ``--add-section=.foo1=... --rename-section=.foo1=.foo2`` now adds ``.foo1`` 
instead of ``.foo2``.
+* New features supported on AIX for ``llvm-ar``:
+
+  * AIX big-format archive write operation (`D123949 
`_)
+
+  * A new object mode option, ``-X`` , to specify the type of object file 
``llvm-ar`` should operate upon (`D127864 `_)
+
+  * Read global symbols of AIX big archive (`D124865 
`_)
+
+* New options supported for ``llvm-nm``:
+
+  * ``-X``, to specify the type of object file that ``llvm-nm`` should examine 
(`D118193 `_)
+
+  * ``--export-symbols``, to create a list of symbols to export (`D112735 
`_)
+
 * The LLVM gold plugin now ignores bitcode from the ``.llvmbc`` section of ELF
   files when doing LTO.  https://github.com/llvm/llvm-project/issues/47216
+* llvm-objcopy now supports 32 bit XCOFF.
+* llvm-objdump: improved assembly printing for XCOFF.
+* llc now parses code-model attribute from input file.
 
 Changes to LLDB
 -
@@ -343,6 +384,14 @@ Other Changes
   has been removed. This had been obsolete and abandoned since Visual Studio
   started including an integration by default in 2019.

[llvm-branch-commits] [llvm] 1ef3199 - Kai's GISEL Patch 1

2022-09-02 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-08-30T15:04:50-05:00
New Revision: 1ef3199dcaa871f08e5707a11f82d101d7ff5e7f

URL: 
https://github.com/llvm/llvm-project/commit/1ef3199dcaa871f08e5707a11f82d101d7ff5e7f
DIFF: 
https://github.com/llvm/llvm-project/commit/1ef3199dcaa871f08e5707a11f82d101d7ff5e7f.diff

LOG: Kai's GISEL Patch 1

Added: 
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

Modified: 
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
index b71d59ed79edd..270a8c9e6757a 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
@@ -13,6 +13,7 @@
 
//===--===//
 
 #include "PPCCallLowering.h"
+#include "PPCCallingConv.h"
 #include "PPCISelLowering.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
@@ -27,6 +28,35 @@
 
 using namespace llvm;
 
+namespace {
+
+struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
+  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+ MachineInstrBuilder MIB)
+  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
+
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+CCValAssign VA) override {
+MIB.addUse(PhysReg, RegState::Implicit);
+Register ExtReg = extendRegister(ValVReg, VA);
+MIRBuilder.buildCopy(PhysReg, ExtReg);
+  }
+
+  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
+MachinePointerInfo &MPO, CCValAssign &VA) override 
{
+llvm_unreachable("unimplemented");
+  }
+
+  Register getStackAddress(uint64_t Size, int64_t Offset,
+   MachinePointerInfo &MPO,
+   ISD::ArgFlagsTy Flags) override {
+llvm_unreachable("unimplemented");
+  }
+
+  MachineInstrBuilder MIB;
+};
+}
+
 PPCCallLowering::PPCCallLowering(const PPCTargetLowering &TLI)
 : CallLowering(&TLI) {}
 
@@ -34,13 +64,35 @@ bool PPCCallLowering::lowerReturn(MachineIRBuilder 
&MIRBuilder,
   const Value *Val, ArrayRef VRegs,
   FunctionLoweringInfo &FLI,
   Register SwiftErrorVReg) const {
-  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
- "Return value without a vreg");
-  if (VRegs.size() > 0)
-return false;
+  auto MIB = MIRBuilder.buildInstrNoInsert(PPC::BLR8);
+  bool Success = true;
+  MachineFunction &MF = MIRBuilder.getMF();
+  const Function &F = MF.getFunction();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  auto &DL = F.getParent()->getDataLayout();
+  if (!VRegs.empty()) {
+// Setup the information about the return value.
+ArgInfo OrigArg{VRegs, Val->getType(), 0};
+setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
+
+// Split the return value into consecutive registers if needed.
+SmallVector SplitArgs;
+splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
+
+// Use the calling convention callback to determine type and location of
+// return value.
+OutgoingValueAssigner ArgAssigner(RetCC_PPC);
 
-  MIRBuilder.buildInstr(PPC::BLR8);
-  return true;
+// Handler to move the return value into the correct location.
+OutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
+
+// Iterate over all return values, and move them to the assigned location.
+Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
+MIRBuilder, F.getCallingConv(),
+F.isVarArg());
+  }
+  MIRBuilder.insertInstr(MIB);
+  return Success;
 }
 
 bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def 
b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
new file mode 100644
index 0..471af5d13d80d
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -0,0 +1,62 @@
+//===- PPCGenRegisterBankInfo.def ---*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===

[llvm-branch-commits] [llvm] a5b57bd - Kai's GISEL Patch 2

2022-09-02 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-08-30T15:04:50-05:00
New Revision: a5b57bde75e757dbf9769ad6c679b2be1c8ca8b6

URL: 
https://github.com/llvm/llvm-project/commit/a5b57bde75e757dbf9769ad6c679b2be1c8ca8b6
DIFF: 
https://github.com/llvm/llvm-project/commit/a5b57bde75e757dbf9769ad6c679b2be1c8ca8b6.diff

LOG: Kai's GISEL Patch 2

Added: 
llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll

Modified: 
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
index be56b6fe49589..bbbd211269d42 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -27,5 +27,8 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
   .legalFor({S64})
   .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_ADD, G_SUB})
+  .legalFor({S64})
+  .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index 64e6a04daabc1..f1732742438eb 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -66,6 +66,9 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) 
const {
   unsigned MappingID = DefaultMappingID;
 
   switch (Opc) {
+// Arithmetic ops.
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
 // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:

diff  --git a/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll 
b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
new file mode 100644
index 0..41012338e3545
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
@@ -0,0 +1,65 @@
+; RUN: llc -mtriple ppc64le-linux -global-isel -o - < %s | FileCheck %s 
-check-prefixes=CHECK,LINUX
+
+; CHECK-LABEL: test_addi8:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i8 @test_addi8(i8 %a, i8 %b) {
+  %res = add i8 %a, %b
+  ret i8 %res
+}
+
+; CHECK-LABEL: test_addi16:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i16 @test_addi16(i16 %a, i16 %b) {
+  %res = add i16 %a, %b
+  ret i16 %res
+}
+
+; CHECK-LABEL: test_addi32:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i32 @test_addi32(i32 %a, i32 %b) {
+  %res = add i32 %a, %b
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_addi64:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i64 @test_addi64(i64 %a, i64 %b) {
+  %res = add i64 %a, %b
+  ret i64 %res
+}
+
+; CHECK-LABEL: test_subi8:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i8 @test_subi8(i8 %a, i8 %b) {
+  %res = sub i8 %a, %b
+  ret i8 %res
+}
+
+; CHECK-LABEL: test_subi16:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i16 @test_subi16(i16 %a, i16 %b) {
+  %res = sub i16 %a, %b
+  ret i16 %res
+}
+
+; CHECK-LABEL: test_subi32:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i32 @test_subi32(i32 %a, i32 %b) {
+  %res = sub i32 %a, %b
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_subi64:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i64 @test_subi64(i64 %a, i64 %b) {
+  %res = sub i64 %a, %b
+  ret i64 %res
+}



___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 13e5c76 - Kai's GISEL Patch 3

2022-09-02 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-08-30T15:04:50-05:00
New Revision: 13e5c764a2e88d866d679cc73927648afaafd48e

URL: 
https://github.com/llvm/llvm-project/commit/13e5c764a2e88d866d679cc73927648afaafd48e
DIFF: 
https://github.com/llvm/llvm-project/commit/13e5c764a2e88d866d679cc73927648afaafd48e.diff

LOG: Kai's GISEL Patch 3

Added: 
llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-constant.ll

Modified: 
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index b461ca4a28e1..f44a22308496 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -43,6 +43,11 @@ class PPCInstructionSelector : public InstructionSelector {
   /// selector for the patterns that do not require complex C++.
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
+  bool selectConst(MachineInstr &I, MachineBasicBlock &MBB,
+   MachineRegisterInfo &MRI) const;
+  bool selectSExt(MachineInstr &I, MachineBasicBlock &MBB,
+  MachineRegisterInfo &MRI) const;
+
   const PPCInstrInfo &TII;
   const PPCRegisterInfo &TRI;
   const PPCRegisterBankInfo &RBI;
@@ -91,6 +96,102 @@ static bool selectCopy(MachineInstr &I, const 
TargetInstrInfo &TII,
   return true;
 }
 
+bool PPCInstructionSelector::selectConst(MachineInstr &I,
+ MachineBasicBlock &MBB,
+ MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_CONSTANT && "Unexpected G code");
+
+  MachineInstr *MI = nullptr;
+  Register DstReg = I.getOperand(0).getReg();
+  APInt ConstValue = I.getOperand(1).getCImm()->getValue();
+  if (ConstValue.isIntN(16)) {
+bool NeedMask = !ConstValue.isIntN(15);
+uint64_t Cst = ConstValue.getZExtValue();
+Register TmpReg =
+NeedMask ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;
+MI =
+BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), 
TmpReg).addImm(Cst);
+if (NeedMask) {
+  constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), DstReg)
+   .addReg(TmpReg, RegState::Kill)
+   .addImm(0)
+   .addImm(16);
+}
+  } else if (ConstValue.isSignedIntN(16)) {
+int64_t Cst = ConstValue.getSExtValue();
+MI =
+BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), 
DstReg).addImm(Cst);
+  } else if (ConstValue.isSignedIntN(32)) {
+int64_t Cst = ConstValue.getSExtValue();
+int64_t UpperCst = Cst >> 16;
+int64_t LowerCst = Cst & 0x;
+Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
+MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg)
+ .addImm(UpperCst);
+constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg)
+ .addReg(TmpReg, RegState::Kill)
+ .addImm(LowerCst);
+  } else if (ConstValue.isIntN(32)) {
+bool NeedMask = !ConstValue.isIntN(31);
+uint64_t Cst = ConstValue.getZExtValue();
+uint64_t UpperCst = Cst >> 16;
+uint64_t LowerCst = Cst & 0x;
+Register TmpReg =
+NeedMask ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;
+if (UpperCst == 0x && (LowerCst & 0x8000) == 0x8000) {
+  MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
+   .addImm(LowerCst);
+} else {
+  Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
+  MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Tmp2Reg)
+   .addImm(UpperCst);
+  constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), TmpReg)
+   .addReg(Tmp2Reg, RegState::Kill)
+   .addImm(LowerCst);
+}
+if (NeedMask) {
+  constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), DstReg)
+   .addReg(TmpReg, RegState::Kill)
+   .addImm(0)
+   .addImm(32);
+}
+  } else
+return false;
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
+bool PPCInstructionSelector::selectSExt(MachineInstr &I, MachineBasicBlock 
&MBB,
+MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_SEXT_INREG && "Unexpected G code");
+
+  Register DstReg = I.getOperand(0).getReg();
+  Regi

[llvm-branch-commits] [llvm] 4da2e94 - FP Patch by Western

2022-09-02 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-09-01T10:48:52-05:00
New Revision: 4da2e948311280fe0fe0d9845a5e9c12c056fb92

URL: 
https://github.com/llvm/llvm-project/commit/4da2e948311280fe0fe0d9845a5e9c12c056fb92
DIFF: 
https://github.com/llvm/llvm-project/commit/4da2e948311280fe0fe0d9845a5e9c12c056fb92.diff

LOG: FP Patch by Western

Added: 
llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll

Modified: 
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def 
b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
index 471af5d13d80..63ea629825c8 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -16,6 +16,10 @@ RegisterBankInfo::PartialMapping 
PPCGenRegisterBankInfo::PartMappings[]{
 /* StartIdx, Length, RegBank */
 // 0: GPR 64-bit value.
 {0, 64, PPC::GPRRegBank},
+// 1: FPR 32-bit value
+{0, 32, PPC::FPRRegBank},
+// 2: FPR 64-bit value
+{0, 64, PPC::FPRRegBank},
 };
 
 // ValueMappings.
@@ -37,6 +41,14 @@ RegisterBankInfo::ValueMapping 
PPCGenRegisterBankInfo::ValMappings[]{
 {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
 {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
 {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+// 2: FPR 32-bit value.
+{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+// 3: FPR 64-bit value.
+{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
 };
 
 // TODO Too simple!

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index f44a22308496..62a5b001b31c 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -80,18 +80,45 @@ PPCInstructionSelector::PPCInstructionSelector(const 
PPCTargetMachine &TM,
 {
 }
 
+static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
+  if (RB->getID() == PPC::GPRRegBankID) {
+if (Ty.getSizeInBits() == 64)
+  return &PPC::G8RCRegClass;
+  }
+  if (RB->getID() == PPC::FPRRegBankID) {
+if (Ty.getSizeInBits() == 32)
+  return &PPC::F4RCRegClass;
+if (Ty.getSizeInBits() == 64)
+  return &PPC::F8RCRegClass;
+  }
+
+  llvm_unreachable("Unknown RegBank!");
+}
+
 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) {
   Register DstReg = I.getOperand(0).getReg();
   Register SrcReg = I.getOperand(1).getReg();
 
-  if (!Register::isPhysicalRegister(DstReg))
-if (!RBI.constrainGenericRegister(DstReg, PPC::G8RCRegClass, MRI))
+  if (!Register::isPhysicalRegister(DstReg)) {
+const TargetRegisterClass *RC =
+getRegClass(MRI.getType(DstReg), RBI.getRegBank(DstReg, MRI, TRI));
+if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
+  LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+<< " dest operand\n");
   return false;
-  if (!Register::isPhysicalRegister(SrcReg))
-if (!RBI.constrainGenericRegister(SrcReg, PPC::G8RCRegClass, MRI))
+}
+  }
+  if (!Register::isPhysicalRegister(SrcReg)) {
+const TargetRegisterClass *RC =
+getRegClass(MRI.getType(SrcReg), RBI.getRegBank(SrcReg, MRI, TRI));
+if (!RBI.constrainGenericRegister(SrcReg, *RC, MRI)) {
+  LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+<< " source operand\n");
   return false;
+}
+  }
 
   return true;
 }

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
index 903ccb4dcd80..a6dafdea3086 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -40,5 +40,9 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   getActionDefinitionsBuilder({G_ADD, G_SUB})
   .legalFor({S64})
   .clampScalar(0, S64, S64);
+
+  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
+  .legalFor({S32, S64});
+

[llvm-branch-commits] [llvm] e2e4b92 - Vector implementation

2022-09-02 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-09-02T11:08:45-05:00
New Revision: e2e4b924e40d796c067917feafadbe2401ea5c5f

URL: 
https://github.com/llvm/llvm-project/commit/e2e4b924e40d796c067917feafadbe2401ea5c5f
DIFF: 
https://github.com/llvm/llvm-project/commit/e2e4b924e40d796c067917feafadbe2401ea5c5f.diff

LOG: Vector implementation

Added: 


Modified: 
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
index 270a8c9e6757..476d2d2f2dcf 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
@@ -113,6 +113,8 @@ bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder 
&MIRBuilder,
   SmallVector SplitArgs;
   unsigned I = 0;
   for (const auto &Arg : F.args()) {
+fprintf(stderr, "AKWAN - in lowerFormalArguments() - Dumping arguments\n");
+Arg.dump();
 if (DL.getTypeStoreSize(Arg.getType()).isZero())
   continue;
 

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def 
b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
index 63ea629825c8..bc3109cad01e 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -20,6 +20,8 @@ RegisterBankInfo::PartialMapping 
PPCGenRegisterBankInfo::PartMappings[]{
 {0, 32, PPC::FPRRegBank},
 // 2: FPR 64-bit value
 {0, 64, PPC::FPRRegBank},
+// 3: VSX 128-bit vector
+{0, 128, PPC::VSXRegBank}
 };
 
 // ValueMappings.
@@ -49,6 +51,10 @@ RegisterBankInfo::ValueMapping 
PPCGenRegisterBankInfo::ValMappings[]{
 {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
 {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
 {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+// 5: VSX 128-bit vector.
+{&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
 };
 
 // TODO Too simple!

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index 62a5b001b31c..eddfe36b165b 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -91,6 +91,11 @@ static const TargetRegisterClass *getRegClass(LLT Ty, const 
RegisterBank *RB) {
 if (Ty.getSizeInBits() == 64)
   return &PPC::F8RCRegClass;
   }
+  if (RB->getID() == PPC::VSXRegBankID) {
+if (Ty.getSizeInBits() == 128)
+  //return &PPC::VSRCRegClass;
+  return &PPC::VRRCRegClass;
+  }
 
   llvm_unreachable("Unknown RegBank!");
 }
@@ -224,6 +229,9 @@ bool PPCInstructionSelector::select(MachineInstr &I) {
   auto &MF = *MBB.getParent();
   auto &MRI = MF.getRegInfo();
 
+  fprintf(stderr, "AKWAN - Global ISel begins:\n");
+  I.dump();
+
   if (!isPreISelGenericOpcode(I.getOpcode())) {
 if (I.isCopy())
   return selectCopy(I, TII, MRI, TRI, RBI);

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
index a6dafdea3086..e6b52af13f56 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -23,6 +23,10 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
+  const LLT V16S8 = LLT::fixed_vector(16, 8);
+  const LLT V8S16 = LLT::fixed_vector(8, 16);
+  //const LLT V4S32 = LLT::fixed_vector(4, 32);
+  //const LLT V2S64 = LLT::fixed_vector(2, 64);
   getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
   getActionDefinitionsBuilder(G_CONSTANT)
   .legalFor({S64})
@@ -35,7 +39,7 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   getActionDefinitionsBuilder(G_SEXT_INREG)
.legalForTypeWithAnyImm({S64});
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
-  .legalFor({S64})
+  .legalFor({S64, V16S8, V8S16})
   .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_ADD, G_SUB})
   .legalFor({S64})

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index a9fb1ade5f95..206ff2e955ad 100644
--- a/llvm/lib/T

[llvm-branch-commits] [llvm] d905af0 - Update naming

2022-09-02 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2022-09-02T15:21:45-05:00
New Revision: d905af0392054dd4c5e9beb1960eae9477b9a181

URL: 
https://github.com/llvm/llvm-project/commit/d905af0392054dd4c5e9beb1960eae9477b9a181
DIFF: 
https://github.com/llvm/llvm-project/commit/d905af0392054dd4c5e9beb1960eae9477b9a181.diff

LOG: Update naming

Added: 


Modified: 
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def 
b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
index bc3109cad01e9..1765fa0be0b1b 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -20,8 +20,8 @@ RegisterBankInfo::PartialMapping 
PPCGenRegisterBankInfo::PartMappings[]{
 {0, 32, PPC::FPRRegBank},
 // 2: FPR 64-bit value
 {0, 64, PPC::FPRRegBank},
-// 3: VSX 128-bit vector
-{0, 128, PPC::VSXRegBank}
+// 3: 128-bit vector
+{0, 128, PPC::VECRegBank} // VSX
 };
 
 // ValueMappings.
@@ -52,9 +52,9 @@ RegisterBankInfo::ValueMapping 
PPCGenRegisterBankInfo::ValMappings[]{
 {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
 {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
 // 5: VSX 128-bit vector.
-{&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
-{&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
-{&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_VEC128 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_VEC128 - PMI_Min], 1},
+{&PPCGenRegisterBankInfo::PartMappings[PMI_VEC128 - PMI_Min], 1},
 };
 
 // TODO Too simple!

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index eddfe36b165bf..4e186820803bd 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -91,7 +91,7 @@ static const TargetRegisterClass *getRegClass(LLT Ty, const 
RegisterBank *RB) {
 if (Ty.getSizeInBits() == 64)
   return &PPC::F8RCRegClass;
   }
-  if (RB->getID() == PPC::VSXRegBankID) {
+  if (RB->getID() == PPC::VECRegBankID) {
 if (Ty.getSizeInBits() == 128)
   //return &PPC::VSRCRegClass;
   return &PPC::VRRCRegClass;

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp 
b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index 206ff2e955ad6..1239c77acf447 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -51,7 +51,7 @@ PPCRegisterBankInfo::getRegBankFromRegClass(const 
TargetRegisterClass &RC,
   case PPC::VSRCRegClassID:
   case PPC::VRRCRegClassID:
   case PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID:
-return getRegBank(PPC::VSXRegBankID);
+return getRegBank(PPC::VECRegBankID);
   default:
 llvm_unreachable("Unexpected register class");
   }
@@ -95,7 +95,7 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) 
const {
   case TargetOpcode::G_TRUNC:
 assert(NumOperands <= 3 &&
"This code is for instructions with 3 or less operands");
-OperandsMapping = 
getValueMapping(MF.getSubtarget().hasAltivec() ? PMI_VSX128 : 
PMI_GPR64);
+OperandsMapping = 
getValueMapping(MF.getSubtarget().hasAltivec() ? PMI_VEC128 : 
PMI_GPR64);
 break;
   case TargetOpcode::G_SEXT_INREG:
 OperandsMapping = getOperandsMapping(

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h 
b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
index 883dfa3f3c597..0aa126dfcf8c5 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
@@ -31,7 +31,7 @@ class PPCGenRegisterBankInfo : public RegisterBankInfo {
 PMI_GPR64 = 1,
 PMI_FPR32 = 2,
 PMI_FPR64 = 3,
-PMI_VSX128 = 4,
+PMI_VEC128 = 4,
 PMI_Min = PMI_GPR64,
   };
 

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td 
b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
index 5ed390d70d5f1..a1153dae140f1 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
@@ -15,6 +15,5 @@
 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
 /// Float point Registers
 def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
-/// VSX Vector Registers
-//def VSXRegBank : RegisterBank<"VSX", [VSRC]>;
-def VSXRegBank : RegisterBank<"VSX", [VRRC]>;
+/// Vector Registers
+def VECRegBank : RegisterBank<"VEC", [VS

[llvm-branch-commits] [clang] f53ab95 - [ReleaseNotes]: Add PowerPC release notes for LLVM 16.0.0

2023-03-01 Thread Amy Kwan via llvm-branch-commits 

Author: Amy Kwan
Date: 2023-02-28T23:12:24-06:00
New Revision: f53ab957ead2cba674e72c22dcbd0cd74007940a

URL: 
https://github.com/llvm/llvm-project/commit/f53ab957ead2cba674e72c22dcbd0cd74007940a
DIFF: 
https://github.com/llvm/llvm-project/commit/f53ab957ead2cba674e72c22dcbd0cd74007940a.diff

LOG: [ReleaseNotes]: Add PowerPC release notes for LLVM 16.0.0

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5f2c92e7c452..cae9281522be 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -893,6 +893,8 @@ Miscellaneous Bug Fixes
 
 - Fix the bug of inserting the ``ZeroInitializationFixit`` before the template
   argument list of ``VarTemplateSpecializationDecl``.
+- Fix the bug where Clang emits constrained float intrinsics when specifying
+  ``-ffp-model=strict -ffp-model=fast``.
 
 Miscellaneous Clang Crashes Fixed
 ^
@@ -1065,6 +1067,18 @@ AIX Support
 * When using ``-shared``, the clang driver now invokes llvm-nm to create an
   export list if the user doesn't specify one via linker flag or pass an
   alternative export control option.
+* Driver work done for ``-pg`` to link with the right paths and files.
+
+- Improved support for `-bcdtors:mbr` and `-bcdtors:csect` linker flags
+  when linking with -fprofile-generate.
+
+- Enabled LTO support. Requires AIX 7.2 TL5 SP3 or newer, or AIX 7.3. LTO
+  support is implemented with the `libLTO.so` plugin. To specify a
+  
diff erent plugin, use the linker option `-bplugin:`.
+  To pass options to the plugin, use the linker option `-bplugin_opt:`.
+
+- ``-mcpu`` option's values are checked against a list of known CPUs. An error
+  is reported if the specified CPU model is not found.
 
 WebAssembly Support
 ^^^

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 45230e28b6a3..d5206fb1c3b7 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -112,6 +112,8 @@ Changes to the LLVM IR
 
 * Added ``uinc_wrap`` and ``udec_wrap`` operations to ``atomicrmw``.
 
+* Renamed ``llvm.flt.rounds`` intrinsic to ``llvm.get.rounding``.
+
 Changes to building LLVM
 
 
@@ -192,7 +194,43 @@ Changes to the MIPS Backend
 Changes to the PowerPC Backend
 --
 
-* ...
+Common PowerPC improvements
+^^^
+
+* Supported selecting floating point and 'sync' family of instructions in
+  GlobalISel PowerPC.
+* Comparison operations are now optimized by record form instructions.
+* ``__test_data_class`` built-in now accepts ``__float128`` arguments for
+  Power9 and newer.
+* Fixed incorrect fence insertion in atomic FP operations on PowerPC.
+* Fixed alignment of aggregate with smaller size than register in variadic
+  function on PowerPC 64-bit.
+* CTR loops on PowerPC are now generated after instruction selection.
+* Enabled track-subreg-liveness option by default.
+* Store of link register in function prologue are now generated in location
+  after stack pointer update instructions.
+* Code generation improvements for atomic operations, vector permutes, and
+  constant materialization for some floating point constants.
+* Implement new register classes and a number of new instructions for 
``mcpu=future``.
+* Implement byte reverse instructions, and VSX Scalar Quad Precision compares
+  for ``mcpu=pwr10``.
+* Improved load-store forwarding for big-endian mode.
+* Bug fixes.
+
+AIX improvements
+
+
+* Supported TOC-data, overflow section, R_RBR relocation in XCOFF.
+* Fixed behavior of function sections, cold attribute, and handling of TLS 
symbols' name prefixes in XCOFF.
+* Fixed redundant spill and reload on AIX 64-bit when paired vector are 
enabled.
+* Disabled location attribution generation of TLS variables.
+* Fixed the mapping of built-in functions ``__builtin_frexpl``,
+  ``__builtin_ldexpl``, and ``__builtin_modfl`` to ``libm`` routines in 64-bit
+  ``long double`` mode.
+* Implemented ``libunwind`` function ``_Unwind_FindEnclosingFunction`` using
+  traceback table on AIX.
+* Changed to use non-unique implementation for ``typeinfo`` comparison.
+* Codegen work done for ``-pg`` to generate correct calls to ``__mcount``.
 
 Changes to the RISC-V Backend
 -
@@ -322,6 +360,8 @@ When emitting CodeView debug information, LLVM will now 
emit S_CONSTANT records
 for variables optimized into a constant via the SROA and SCCP passes.
 (`D138995 `_)
 
+``DW_LANG_C11`` now respects ``-gstrict-dwarf`` option.
+
 Changes to the LLVM tools
 -
 
@@ -333,12 +373,27 @@ Changes to the LLVM tools
   that consume ``llvm-readobj``'s JSON output should update their parsers
   accordingly.
 
+* ``l

[llvm-branch-commits] [llvm] release/20.x: [GlobalMerge][PPC] Don't merge globals in llvm.metadata section (#131801) (PR #134052)

2025-04-15 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/134052
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update LLVM 20.1.0 Release Notes (PR #128764)

2025-02-25 Thread Amy Kwan via llvm-branch-commits 

amy-kwan wrote:

@hubert-reinterpretcast Thanks for catching the typo!

https://github.com/llvm/llvm-project/pull/128764
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update LLVM 20.1.0 Release Notes (PR #128764)

2025-02-25 Thread Amy Kwan via llvm-branch-commits 

https://github.com/amy-kwan created 
https://github.com/llvm/llvm-project/pull/128764

This PR adds LLVM 20.1.0 release notes that are related to the PowerPC target.

>From d8479f20064d7043bf3caf466968fadab2ccb45e Mon Sep 17 00:00:00 2001
From: Amy Kwan 
Date: Tue, 25 Feb 2025 13:21:45 -0600
Subject: [PATCH] [PowerPC] Update LLVM 20.1.0 Release Notes

---
 clang/docs/ReleaseNotes.rst |  2 ++
 llvm/docs/ReleaseNotes.md   | 30 +-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a2518042cb5b0..153afdb3d59e3 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1269,6 +1269,8 @@ CUDA Support
 
 AIX Support
 ^^^
+- Fixed the ``-print-runtime-dir`` option.
+- Enable continuous profile syncing feature on AIX.
 
 NetBSD Support
 ^^
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index e654509792652..f4a8ac21a8312 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -263,7 +263,23 @@ Changes to the PowerPC Backend
 --
 
 * The Linux `ppc64` LLC default cpu is updated from `ppc` to `ppc64`.
-* The AIX LLC default cpu is updated from `generic` to `pwr7`.
+* Replaced PPCMergeStringPool with GlobalMerge.
+* Disabled vsx and altivec when -msoft-float is used.
+* Added support for -mcpu=pwr11 -mtune=pwr11.
+* Implemented BCD assist builtins.
+* Expanded global named register support.
+* Updated to use tablegen's MatchRegisterName().
+* Fixed saving of Link Register when using ROP Protect.
+* Fixed SUBREG_TO_REG handling in the RegisterCoalescer.
+* Fixed data layout alignment of i128 to 16.
+* Fixed codegen for transparent_union function parameters.
+* Added an error for incorrect use of memory operands.
+* Other various bug fixes and codegen improvements.
+
+AIX Specific:
+* LLC default cpu is updated from `generic` to `pwr7`.
+* Fixed handling in emitGlobalConstantImpl to emit aliases to subobjects at 
proper offsets.
+* Enabled aggressive merging of constants to reduce TOC entries.
 
 Changes to the RISC-V Backend
 -
@@ -478,6 +494,10 @@ Changes to the LLVM tools
 
 * llvm-objcopy now prints the correct file path in the error message when the 
output file specified by `--dump-section` cannot be opened.
 
+* llvm-cxxfilt now supports demangling call expressions encoded using `cp` 
instead of `cl`.
+
+* llvm-objdump now supports printing the file header, load section header and 
auxillary header for XCOFF object files under the ``--private-headers`` option.
+
 Changes to LLDB
 -
 
@@ -630,6 +650,14 @@ Changes to BOLT
 Changes to Sanitizers
 -
 
+Changes to the Profile Runtime
+--
+
+* On platforms where ``atexit``-registered functions are not called when
+  a DSO is ``dlclose``'d, a mechanism is added that implements this
+  missing functionality for calls to ``atexit`` in the profile runtime.
+  [This is currently only enabled on 
AIX](https://github.com/llvm/llvm-project/pull/102940).
+
 Other Changes
 -
 

___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits