[llvm-branch-commits] [clang] 89447e0 - Builtin defs

2021-06-21 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-09T13:04:56-05:00
New Revision: 89447e0846409fa9103b023912da6b56ef25204c

URL: 
https://github.com/llvm/llvm-project/commit/89447e0846409fa9103b023912da6b56ef25204c
DIFF: 
https://github.com/llvm/llvm-project/commit/89447e0846409fa9103b023912da6b56ef25204c.diff

LOG: Builtin defs

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 9d7f765a2133c..1b88c6797774b 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -45,6 +45,22 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_test_data_class, "bff", "")
+BUILTIN(__builtin_ppc_test_data_class, "bdd", "")
+BUILTIN(__builtin_ppc_ldarx, "LiLiD*iC", "")
+BUILTIN(__builtin_ppc_lwarx, "iiD*iC", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
+BUILTIN(__builtin_ppc_stdcx, "iLiD*", "")
+BUILTIN(__builtin_ppc_stwcx, "iiD*", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*Li", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*i", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*s", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*c", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "ULi", "")
+BUILTIN(__builtin_ppc_mtmsr, "vULi", "")
+BUILTIN(__builtin_ppc_mtspr, "viC", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 



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[llvm-branch-commits] [clang] 66a4ddd - Completed loads

2021-06-21 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-09T13:08:30-05:00
New Revision: 66a4ddde6548ff43f45f98ce15dd5bdac8bcf1ed

URL: 
https://github.com/llvm/llvm-project/commit/66a4ddde6548ff43f45f98ce15dd5bdac8bcf1ed
DIFF: 
https://github.com/llvm/llvm-project/commit/66a4ddde6548ff43f45f98ce15dd5bdac8bcf1ed.diff

LOG: Completed loads

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 1b88c6797774b..a8ed189007dc1 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -45,12 +45,10 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
-BUILTIN(__builtin_ppc_test_data_class, "bff", "")
-BUILTIN(__builtin_ppc_test_data_class, "bdd", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*iC", "")
-BUILTIN(__builtin_ppc_lwarx, "iiD*iC", "")
-BUILTIN(__builtin_ppc_lharx, "ssD*", "")
-BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
+BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "icD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*Li", "")

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index b183dbd4b3bbb..07c07baa0523d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2836,3 +2836,10 @@ let Predicates = [IsISA3_1, HasVSX, IsBigEndian, 
IsPPC64] in {
 def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
   (VINSD $vDi, !mul(i, 8), $rA)>;
 }
+
+def : Pat<(int_ppc_lwarx xoaddr:$dst),
+  (LWARX xoaddr:$dst)>;
+def : Pat<(int_ppc_lharx xoaddr:$dst),
+  (LHARX xoaddr:$dst)>;
+def : Pat<(int_ppc_lbarx xoaddr:$dst),
+  (LBARX xoaddr:$dst)>;



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[llvm-branch-commits] [clang] e335391 - Finish loads

2021-06-21 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-09T14:32:58-05:00
New Revision: e3353919498bd2235fb9a150f614ed43ea1ae9d1

URL: 
https://github.com/llvm/llvm-project/commit/e3353919498bd2235fb9a150f614ed43ea1ae9d1
DIFF: 
https://github.com/llvm/llvm-project/commit/e3353919498bd2235fb9a150f614ed43ea1ae9d1.diff

LOG: Finish loads

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index a8ed189007dc1..dbe816ac46783 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -45,7 +45,7 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
-BUILTIN(__builtin_ppc_ldarx, "LiLiD*iC", "")
+BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
 BUILTIN(__builtin_ppc_lharx, "isD*", "")
 BUILTIN(__builtin_ppc_lbarx, "icD*", "")

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ca1055c0d0cba..fbb3750b6af77 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1523,5 +1523,13 @@ let TargetPrefix = "ppc" in {
   Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
   Intrinsic<[],[],[]>;
+  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
+  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
+  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
+  def int_ppc_lharx : GCCBuiltin<"__builtin_ppc_lharx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
+  def int_ppc_lbarx : GCCBuiltin<"__builtin_ppc_lbarx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 07c07baa0523d..a2d024a4f93fc 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2837,6 +2837,10 @@ let Predicates = [IsISA3_1, HasVSX, IsBigEndian, 
IsPPC64] in {
   (VINSD $vDi, !mul(i, 8), $rA)>;
 }
 
+let Predicates = [HasP8Altivec] in {
+def : Pat<(int_ppc_ldarx xoaddr:$dst),
+  (LDARX xoaddr:$dst)>;
+}
 def : Pat<(int_ppc_lwarx xoaddr:$dst),
   (LWARX xoaddr:$dst)>;
 def : Pat<(int_ppc_lharx xoaddr:$dst),



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[llvm-branch-commits] [clang] f706b87 - Alias, test cases

2021-06-21 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-09T15:13:16-05:00
New Revision: f706b87ada57d1e0c618f8f2e370a8956712c9aa

URL: 
https://github.com/llvm/llvm-project/commit/f706b87ada57d1e0c618f8f2e370a8956712c9aa
DIFF: 
https://github.com/llvm/llvm-project/commit/f706b87ada57d1e0c618f8f2e370a8956712c9aa.diff

LOG: Alias, test cases

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c

Modified: 
clang/lib/Basic/Targets/PPC.h

Removed: 




diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 2ceb0b0cbf1c9..09d89f2688827 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -367,6 +367,10 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
 Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
 Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
 Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
+Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
   }
 };
 

diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
new file mode 100644
index 0..1d8915c21bc3e
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
@@ -0,0 +1,8 @@
+// RUN: %clang -c -O2 -S -mcpu=pwr8 %s -o - | \
+// RUN: FileCheck %s
+long test_ldarx(volatile long* a) {
+  // CHECK-LABEL: test_ldarx
+  // CHECK:   ldarx 3, 0, 3
+  // CHECK-NEXT:  blr
+  return __ldarx(a);
+}

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
new file mode 100644
index 0..e32e5fcab91c7
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
@@ -0,0 +1,40 @@
+// RUN: %clang -mcpu=pwr8 -c -m32 -O2 -S %s -o - | \
+// RUN: FileCheck %s --check-prefix=CHECK-32
+// RUN: %clang -mcpu=pwr8 -c -m64 -O2 -S %s -o - | \
+// RUN: FileCheck %s --check-prefix=CHECK-64
+
+int test_lwarx(volatile int* a) {
+  // CHECK-64-LABEL: test_lwarx
+  // CHECK-64:   lwarx 3, 0, 3
+  // CHECK-64-NEXT:  extsw 3, 3
+  // CHECK-64-NEXT:  blr
+
+  // CHECK-32-LABEL: test_lwarx
+  // CHECK-32:   lwarx 3, 0, 3
+  // CHECK-32-NEXT:  blr
+  return __lwarx(a);
+}
+
+short test_lharx(volatile short* a) {
+  // CHECK-64-LABEL: test_lharx
+  // CHECK-64:   lharx 3, 0, 3
+  // CHECK-64-NEXT:  extsh 3, 3
+  // CHECK-64-NEXT:  blr
+
+  // CHECK-32-LABEL: test_lharx
+  // CHECK-32:   lharx 3, 0, 3
+  // CHECK-32-NEXT:  blr
+  return __lharx(a);
+}
+
+char test_lbarx(volatile char* a) {
+  // CHECK-64-LABEL: test_lbarx
+  // CHECK-64:   lbarx 3, 0, 3
+  // CHECK-64-NEXT:  clrldi 3, 3, 56
+  // CHECK-64-NEXT:  blr
+
+  // CHECK-32-LABEL: test_lbarx
+  // CHECK-32:   clrlwi 3, 3, 24
+  // CHECK-32-NEXT:  blr
+  return __lbarx(a);
+}



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[llvm-branch-commits] [clang] 15b07a4 - Complete stores

2021-06-21 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-16T16:18:22-05:00
New Revision: 15b07a43deac3898c8496f6c4da6dbee88252751

URL: 
https://github.com/llvm/llvm-project/commit/15b07a43deac3898c8496f6c4da6dbee88252751
DIFF: 
https://github.com/llvm/llvm-project/commit/15b07a43deac3898c8496f6c4da6dbee88252751.diff

LOG: Complete stores

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index dbe816ac4678..2a8643c770f6 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -48,10 +48,10 @@ BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
 BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "icD*", "")
-BUILTIN(__builtin_ppc_stdcx, "iLiD*", "")
-BUILTIN(__builtin_ppc_stwcx, "iiD*", "")
-BUILTIN(__builtin_ppc_sthcx, "isD*Li", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*i", "")
 BUILTIN(__builtin_ppc_stbcx, "icD*i", "")
 BUILTIN(__builtin_ppc_dcbtstt, "vv*s", "")
 BUILTIN(__builtin_ppc_dcbtt, "vv*c", "")

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 09d89f268882..f5c551a5df93 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -371,6 +371,10 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
 Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
 Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
 Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
+Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
+Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
+Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
   }
 };
 

diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
index 1d8915c21bc3..0de55393c43a 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
@@ -6,3 +6,9 @@ long test_ldarx(volatile long* a) {
   // CHECK-NEXT:  blr
   return __ldarx(a);
 }
+
+int test_stdcx(volatile long* addr, long val) {
+  // CHECK-LABEL: test_stdcx
+  // CHECK:   stdcx. 3, 0, 4
+  return __stdcx(addr, val);
+}

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
index e32e5fcab91c..f4f02a01580f 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
@@ -23,18 +23,50 @@ short test_lharx(volatile short* a) {
 
   // CHECK-32-LABEL: test_lharx
   // CHECK-32:   lharx 3, 0, 3
+  // CHECK-32-NEXT:  extsh 3, 3
   // CHECK-32-NEXT:  blr
   return __lharx(a);
 }
 
-char test_lbarx(volatile char* a) {
+char test_lbarx(volatile unsigned char* a) {
   // CHECK-64-LABEL: test_lbarx
   // CHECK-64:   lbarx 3, 0, 3
   // CHECK-64-NEXT:  clrldi 3, 3, 56
   // CHECK-64-NEXT:  blr
 
   // CHECK-32-LABEL: test_lbarx
-  // CHECK-32:   clrlwi 3, 3, 24
+  // CHECK-32:   lbarx 3, 0, 3
+  // CHECK-32-NEXT:  clrlwi 3, 3, 24
   // CHECK-32-NEXT:  blr
   return __lbarx(a);
 }
+
+int test_stwcx(volatile int* a, int val) {
+  // CHECK-64-LABEL: test_stwcx
+  // CHECK-64:   stwcx. 4, 0, 3
+
+  // CHECK-32-LABEL: test_stwcx
+  // CHECK-32:   stwcx. 4, 0, 3
+
+  return __stwcx(a, val);
+}
+
+int test_sthcx(volatile short* a, short val) {
+  // CHECK-64-LABEL: test_sthcx
+  // CHECK-64:   sthcx. 4, 0, 3
+
+  // CHECK-32-LABEL: test_sthcx
+  // CHECK-32:   sthcx. 4, 0, 3
+
+  return __sthcx(a, val);
+}
+
+int test_stbcx(volatile char* a, char val) {
+  // CHECK-64-LABEL: test_stbcx
+  // CHECK-64:   stbcx. 4, 0, 3
+
+  // CHECK-32-LABEL: test_stbcx
+  // CHECK-32:   stbcx. 4, 0, 3
+
+  return __stbcx(a, val);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index fbb3750b6af7..ea5ca6181500 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1531,5 +1531,13 @@ let TargetPrefix = "ppc" in {
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
   def int_ppc_lbarx : GCCBuiltin<"__builtin_ppc_lbarx">,
   Intri

[llvm-branch-commits] [clang] d723f26 - Temp commit

2021-06-21 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-21T21:06:23-05:00
New Revision: d723f268ae83cf1e107d1d3ecf5c415682495a75

URL: 
https://github.com/llvm/llvm-project/commit/d723f268ae83cf1e107d1d3ecf5c415682495a75
DIFF: 
https://github.com/llvm/llvm-project/commit/d723f268ae83cf1e107d1d3ecf5c415682495a75.diff

LOG: Temp commit

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/IR/Instructions.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 2a8643c770f68..67fcd39b85689 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -51,8 +51,8 @@ BUILTIN(__builtin_ppc_lharx, "isD*", "")
 BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
-BUILTIN(__builtin_ppc_sthcx, "isD*i", "")
-BUILTIN(__builtin_ppc_stbcx, "icD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*c", "")
 BUILTIN(__builtin_ppc_dcbtstt, "vv*s", "")
 BUILTIN(__builtin_ppc_dcbtt, "vv*c", "")
 BUILTIN(__builtin_ppc_mftbu, "Ui","")

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1b30d44937f3e..2cf28f546a556 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15342,6 +15342,18 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+dbgs() << "GENNING CUSTOM SEXT:" << E->getNumArgs() <<"\n";
+// Value *Res =  Builder.CreateSExt(Ops[1], Int32Ty);
+Ops[1] =  Builder.CreateSExt(Ops[1], Int32Ty);
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+// SmallVector  NewOps;
+// NewOps.push_back(Ops[0]);
+// NewOps.push_back(Res);
+// return Builder.CreateCall(F, NewOps);
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
index f4f02a01580f6..ba29d8986564c 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
@@ -1,72 +1,76 @@
-// RUN: %clang -mcpu=pwr8 -c -m32 -O2 -S %s -o - | \
-// RUN: FileCheck %s --check-prefix=CHECK-32
-// RUN: %clang -mcpu=pwr8 -c -m64 -O2 -S %s -o - | \
-// RUN: FileCheck %s --check-prefix=CHECK-64
+// RUN: %clang_cc1 -triple=powerpc-unknown-aix -O2 -S %s -o - | \
+// RUN: FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -O2 -S %s -o - | \
+// RUN: FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -O2 -S %s \
+// RUN:  -o - | FileCheck %s --check-prefix=CHECK-COMMON
+// RUN: %clang_cc1 -triple=powerpc64be-unknown-unknown -O2 -S %s \
+// RUN:  -o - | FileCheck %s --check-prefix=CHECK-COMMON
 
 int test_lwarx(volatile int* a) {
-  // CHECK-64-LABEL: test_lwarx
-  // CHECK-64:   lwarx 3, 0, 3
-  // CHECK-64-NEXT:  extsw 3, 3
-  // CHECK-64-NEXT:  blr
+  // CHECK-COMMON-LABEL: test_lwarx
+  // CHECK-COMMON:   lwarx 3, 0, 3
+  // CHECK-COMMON-NEXT:  extsw 3, 3
+  // CHECK-COMMON-NEXT:  blr
 
-  // CHECK-32-LABEL: test_lwarx
-  // CHECK-32:   lwarx 3, 0, 3
-  // CHECK-32-NEXT:  blr
+  // CHECK-AIX-LABEL: test_lwarx
+  // CHECK-AIX:   lwarx 3, 0, 3
+  // CHECK-AIX-NEXT:  blr
   return __lwarx(a);
 }
 
 short test_lharx(volatile short* a) {
-  // CHECK-64-LABEL: test_lharx
-  // CHECK-64:   lharx 3, 0, 3
-  // CHECK-64-NEXT:  extsh 3, 3
-  // CHECK-64-NEXT:  blr
+  // CHECK-COMMON-LABEL: test_lharx
+  // CHECK-COMMON:   lharx 3, 0, 3
+  // CHECK-COMMON-NEXT:  extsh 3, 3
+  // CHECK-COMMON-NEXT:  blr
 
-  // CHECK-32-LABEL: test_lharx
-  // CHECK-32:   lharx 3, 0, 3
-  // CHECK-32-NEXT:  extsh 3, 3
-  // CHECK-32-NEXT:  blr
+  // CHECK-AIX-LABEL: test_lharx
+  // CHECK-AIX:   lharx 3, 0, 3
+  // CHECK-AIX-NEXT:  extsh 3, 3
+  // CHECK-AIX-NEXT:  blr
   return __lharx(a);
 }
 
 char test_lbarx(volatile unsigned char* a) {
-  // CHECK-64-LABEL: test_lbarx
-  // CHECK-64:   lbarx 3, 0, 3
-  // CHECK-64-NEXT:  clrldi 3, 3, 56
-  // CHECK-64-NEXT:  blr
+  // CHECK-COMMON-LABEL: test_lbarx
+  // CHECK-COMMON:   lbarx 3, 0, 3
+  // CHECK-COMMON-NEXT:  clrldi 3, 3, 56
+  // CHECK-COMMON-NEXT:  blr
 
-  // CHECK-32-LABEL: test_lbarx
-  // CH

[llvm-branch-commits] [llvm] f608ce8 - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-22 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-16T09:29:07-05:00
New Revision: f608ce814517ea1f42506507e9db0403313ca42c

URL: 
https://github.com/llvm/llvm-project/commit/f608ce814517ea1f42506507e9db0403313ca42c
DIFF: 
https://github.com/llvm/llvm-project/commit/f608ce814517ea1f42506507e9db0403313ca42c.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 9d7f765a2133c..96018a3b47b3c 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -45,6 +45,18 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 3dfc0c0751e44..f421311530bd0 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -97,6 +97,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
   Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
   Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a9915cb6d720e..c777a17d76679 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3331,6 +3331,21 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
+   SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_fcfid:
+  case PPC::BI__builtin_ppc_fcfud:
+  case PPC::BI__builtin_ppc_fctid:
+  case PPC::BI__builtin_ppc_fctidz:
+  case PPC::BI__builtin_ppc_fctudz:
+  case PPC::BI__builtin_ppc_trapd: {
+return TI.getTypeWidth(TI.getIntPtrType()) == 64;
+  }
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ca1055c0d0cba..87249e67c6827 

[llvm-branch-commits] [clang] c1e1a4e - temp commit

2021-06-23 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-23T13:53:36-05:00
New Revision: c1e1a4ee687e416d67c8520846269b18c45222c8

URL: 
https://github.com/llvm/llvm-project/commit/c1e1a4ee687e416d67c8520846269b18c45222c8
DIFF: 
https://github.com/llvm/llvm-project/commit/c1e1a4ee687e416d67c8520846269b18c45222c8.diff

LOG: temp commit

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index c777a17d76679..1b20d228f4e17 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3335,17 +3335,17 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
 return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   }
   case PPC::BI__builtin_ppc_tdw: {
-return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
-   SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
-  }
-  case PPC::BI__builtin_ppc_fcfid:
-  case PPC::BI__builtin_ppc_fcfud:
-  case PPC::BI__builtin_ppc_fctid:
-  case PPC::BI__builtin_ppc_fctidz:
-  case PPC::BI__builtin_ppc_fctudz:
-  case PPC::BI__builtin_ppc_trapd: {
-return TI.getTypeWidth(TI.getIntPtrType()) == 64;
-  }
+// return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
+   return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  // case PPC::BI__builtin_ppc_fcfid:
+  // case PPC::BI__builtin_ppc_fcfud:
+  // case PPC::BI__builtin_ppc_fctid:
+  // case PPC::BI__builtin_ppc_fctidz:
+  // case PPC::BI__builtin_ppc_fctudz:
+  // case PPC::BI__builtin_ppc_trapd: {
+// TI.getTypeWidth(TI.getIntPtrType()) == 64;
+  // }
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
new file mode 100644
index 0..ecdb6d15240cf
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,17 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+
+long long lla, llb;
+int ia, ib;
+
+void test_trap(void) {
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the 
valid range [1, 31]}}
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid 
range [1, 31]}}
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 87249e67c6827..7de234bbf025f 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -112,7 +112,7 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with 
"llvm.ppc.".
   : GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
 Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
 
-  // xl compatibility
+  // Intrinsics defined to maintain XL compatibility
   def int_ppc_tdw
   : GCCBuiltin<"__builtin_ppc_tdw">,
 Intrinsic <[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], 
[ImmArg>]>;

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 7e52ce2702a8a..1995bbec2c21e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1731,6 +1731,6 @@ def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31),
 def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
   (TD $IMM, $A, $B)>;
 
-// trap, trapd
+// trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
   (TDI 24, $A, 0)>;

diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
index 33cb493498ae7..b0dc7ede50623 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
@@ -1,115 +1,108 @@
-// RUN: clang -mcpu=pwr9 -O2 -c -S %s -o - | FileCheck %s
-
-double a;
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+

[llvm-branch-commits] [clang] bffcf34 - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-23 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-23T16:32:02-05:00
New Revision: bffcf34f13d87ffb0c360a50fea059a87cf2cbb0

URL: 
https://github.com/llvm/llvm-project/commit/bffcf34f13d87ffb0c360a50fea059a87cf2cbb0
DIFF: 
https://github.com/llvm/llvm-project/commit/bffcf34f13d87ffb0c360a50fea059a87cf2cbb0.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 9d7f765a2133..96018a3b47b3 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -45,6 +45,18 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 3dfc0c0751e4..f421311530bd 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -97,6 +97,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
   Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
   Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a9915cb6d720..1b20d228f4e1 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3331,6 +3331,21 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+// return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
+   return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  // case PPC::BI__builtin_ppc_fcfid:
+  // case PPC::BI__builtin_ppc_fcfud:
+  // case PPC::BI__builtin_ppc_fctid:
+  // case PPC::BI__builtin_ppc_fctidz:
+  // case PPC::BI__builtin_ppc_fctudz:
+  // case PPC::BI__builtin_ppc_trapd: {
+// TI.getTypeWidth(TI.getIntPtrType()) == 64;
+  // }
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__bu

[llvm-branch-commits] [clang] e043c24 - Fixed STBCX

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T02:04:33-05:00
New Revision: e043c2429d773878e4ea8d4daf48ae561c499478

URL: 
https://github.com/llvm/llvm-project/commit/e043c2429d773878e4ea8d4daf48ae561c499478
DIFF: 
https://github.com/llvm/llvm-project/commit/e043c2429d773878e4ea8d4daf48ae561c499478.diff

LOG: Fixed STBCX

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/IR/Instructions.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2cf28f546a55..ddd5605acaba 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15343,14 +15343,24 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   }
 
   case PPC::BI__builtin_ppc_sthcx: {
-dbgs() << "GENNING CUSTOM SEXT:" << E->getNumArgs() <<"\n";
-// Value *Res =  Builder.CreateSExt(Ops[1], Int32Ty);
-Ops[1] =  Builder.CreateSExt(Ops[1], Int32Ty);
 llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
-// SmallVector  NewOps;
-// NewOps.push_back(Ops[0]);
-// NewOps.push_back(Res);
-// return Builder.CreateCall(F, NewOps);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+  case PPC::BI__builtin_ppc_stbcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_stbcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+auto Signed = getIntegerWidthAndSignedness(CGM.getContext(),
+ E->getArg(1)->getType()).Signed;
+
+if (Signed) {
+  dbgs() << "SIGNED\n";
+  Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+} else {
+  dbgs() << "UNSIGNED\n";
+  Ops[1] = Builder.CreateZExt(Ops[1], Int32Ty);
+}
 return Builder.CreateCall(F, Ops);
   }
 

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index fc20f220894e..0383bc2a8a96 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1535,9 +1535,7 @@ let TargetPrefix = "ppc" in {
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty], 
[IntrWriteMem]>;
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
-  def int_ppc_sthcx : 
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
-  def int_ppc_stbcx : 
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
+  def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
+  def int_ppc_stbcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
 }
 

diff  --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index eb3bb8367759..f2316b609193 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -2936,8 +2936,6 @@ unsigned CastInst::isEliminableCastPair(
 
 CastInst *CastInst::Create(Instruction::CastOps op, Value *S, Type *Ty,
   const Twine &Name, Instruction *InsertBefore) {
-  dbgs() << "Op code bitcast: " << BitCast << "\n";
-  dbgs() << "DEBUG CREATE BEFORE: " << op << " NEXT " << *S << " TYPE " << *Ty 
<< "\n";
   assert(castIsValid(op, S, Ty) && "Invalid cast!");
   // Construct and return the appropriate CastInst subclass
   switch (op) {

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 8d544f6c1040..d1514bbebe05 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2851,7 +2851,7 @@ def : Pat<(int_ppc_lbarx xoaddr:$dst),
   (LBARX xoaddr:$dst)>;
 // def : Pat<(int_ppc_stwcx xoaddr:$dst, gprc:$A),
   // (STWCX gprc:$A, xoaddr:$dst)>;
-def : Pat<(int_ppc_sthcx xoaddr:$dst, (sextloadi32 gprc:$A)),
+def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A),
   (STHCX (EXTSH gprc:$A), xoaddr:$dst)>;
 def : Pat<(int_ppc_stbcx xoaddr:$dst, gprc:$A),
-  (STBCX (EXTSB gprc:$A), xoaddr:$dst)>;
+  (STBCX gprc:$A, xoaddr:$dst)>;



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[llvm-branch-commits] [llvm] 90c60a5 - Trap test case separation

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T02:08:39-05:00
New Revision: 90c60a5f59c5a3e1d1da9b7721fe5f89db2b2ad3

URL: 
https://github.com/llvm/llvm-project/commit/90c60a5f59c5a3e1d1da9b7721fe5f89db2b2ad3
DIFF: 
https://github.com/llvm/llvm-project/commit/90c60a5f59c5a3e1d1da9b7721fe5f89db2b2ad3.diff

LOG: Trap test case separation

Added: 


Modified: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Removed: 




diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
index 110c932936e1..2f5e2e6f7eea 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
@@ -11,6 +11,7 @@ long long lla, llb;
 double da;
 int ia, ib;
 
+#ifndef __PPC64__
 // tdw
 void test_xl_tdw(void) {
 // CHECK-LABEL: test_xl_tdw
@@ -25,8 +26,9 @@ void test_tdw(void) {
 // CHECK-NEXT: entry:
 // CHECK: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 13)
 
-  __tdw(lla, llb, 13);
+  __builtin_ppc_tdw(lla, llb, 13);
 }
+#endif
 
 // td
 void test_tw(void) {
@@ -34,7 +36,7 @@ void test_tw(void) {
 // CHECK-NEXT: entry:
 // CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
 
-  __tw(ia, ib, 1);
+  __builtin_ppc_tw(ia, ib, 1);
 }
 
 void test_xl_tw(void) {
@@ -60,6 +62,7 @@ void test_xl_trap(void) {
   __trap(ia);
 }
 
+#ifndef __PPC64__
 // trapd
 void test_trapd(void) {
 // CHECK-LABEL: test_trapd
@@ -74,3 +77,4 @@ void test_xl_trapd(void) {
 // CHECK: void @llvm.ppc.trapd(i64 %0)
   __trapd(da);
 }
+#endif

diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
index e8f7aa52f20d..1407dbf1db5f 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -9,6 +9,7 @@
 ; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
 
 ; tdw
+#ifndef __PPC64__
 declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
 define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
@@ -69,8 +70,9 @@ define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
   ret void
 }
+#endif
 
-; td
+; tw
 declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
 define dso_local void @test__twlgt(i32 %a, i32 %b) {
   call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)



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[llvm-branch-commits] [clang] 2f4e605 - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T02:09:06-05:00
New Revision: 2f4e605b9eb1aee5d97c67fc98c41c2cc8854969

URL: 
https://github.com/llvm/llvm-project/commit/2f4e605b9eb1aee5d97c67fc98c41c2cc8854969
DIFF: 
https://github.com/llvm/llvm-project/commit/2f4e605b9eb1aee5d97c67fc98c41c2cc8854969.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 9d7f765a2133..96018a3b47b3 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -45,6 +45,18 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 3dfc0c0751e4..f421311530bd 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -97,6 +97,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
   Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
   Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a9915cb6d720..1b20d228f4e1 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3331,6 +3331,21 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+// return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
+   return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  // case PPC::BI__builtin_ppc_fcfid:
+  // case PPC::BI__builtin_ppc_fcfud:
+  // case PPC::BI__builtin_ppc_fctid:
+  // case PPC::BI__builtin_ppc_fctidz:
+  // case PPC::BI__builtin_ppc_fctudz:
+  // case PPC::BI__builtin_ppc_trapd: {
+// TI.getTypeWidth(TI.getIntPtrType()) == 64;
+  // }
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__bu

[llvm-branch-commits] [clang] 63b9186 - [PowerPC] Store, load, move from and to registers related builtins

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T02:06:01-05:00
New Revision: 63b91860728beae25dfa38cee2a61679fa491887

URL: 
https://github.com/llvm/llvm-project/commit/63b91860728beae25dfa38cee2a61679fa491887
DIFF: 
https://github.com/llvm/llvm-project/commit/63b91860728beae25dfa38cee2a61679fa491887.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

  This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.h
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 9d7f765a2133..67fcd39b8568 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -45,6 +45,20 @@ BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
+BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*c", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*s", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*c", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "ULi", "")
+BUILTIN(__builtin_ppc_mtmsr, "vULi", "")
+BUILTIN(__builtin_ppc_mtspr, "viC", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 2ceb0b0cbf1c..f5c551a5df93 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -367,6 +367,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
 Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
 Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
 Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
+Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
+Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
+Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
+Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
   }
 };
 

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1b30d44937f3..ddd5605acaba 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15342,6 +15342,28 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+  case PPC::BI__builtin_ppc_stbcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_stbcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+auto Signed = getIntegerWidthAndSignedness(CGM.getContext(),
+ E->getArg(1)->getType()).Signed;
+
+if (Signed) {
+  dbgs() << "SIGNED\n";
+  Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+} else {
+  dbgs() << "UNSIGNED\n";
+  Ops[1] = Builder.CreateZExt(Ops[1], Int32Ty);
+}
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
new file mode 100644
index ..0de55393c43a
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore-64-only.c
@@ -0,0 +1,14 @@
+// RUN: %clang -c -O2 -S -mcpu=pwr8 %s -o - | \
+// RUN: FileCheck %s
+long test_ldarx(volatile long* a) {
+  // CHECK-LABEL: test_ldarx
+  // CHECK:   ldarx 3, 0, 3
+  // CHECK-NEXT:  blr
+  return __ldarx(a);
+}
+
+int test_stdcx(volatile long* addr, long val) {
+  // CHECK-LABEL: test_stdcx
+  // CHECK:   stdcx. 3, 0, 4

[llvm-branch-commits] [clang] 68f8fae - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T02:11:39-05:00
New Revision: 68f8fae19f3b20d4bdd88c22ee67ee3ba0114768

URL: 
https://github.com/llvm/llvm-project/commit/68f8fae19f3b20d4bdd88c22ee67ee3ba0114768
DIFF: 
https://github.com/llvm/llvm-project/commit/68f8fae19f3b20d4bdd88c22ee67ee3ba0114768.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 47b485473342..c660d8e2a344 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -47,6 +47,18 @@ BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e051826c5216..5a28ed95f5ca 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -100,6 +100,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
   Builder.defineMacro("__compare_and_swaplp",
   "__builtin_ppc_compare_and_swaplp");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 17eeebb0c679..ffac6dbf1f44 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3341,6 +3341,21 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+// return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
+   return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  // case PPC::BI__builtin_ppc_fcfid:
+  // case PPC::BI__builtin_ppc_fcfud:
+  // case PPC::BI__builtin_ppc_fctid:
+  // case PPC::BI__builtin_ppc_fctidz:
+  // case PPC::BI__builtin_ppc_fctudz:
+  // case PPC::BI__builtin_ppc_trapd: {
+// TI.getTypeWidth(TI.getIntPtrType()) == 64;
+  // }
 #define CUSTOM_B

[llvm-branch-commits] [clang] c421412 - Fixed C test case

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T13:54:53-05:00
New Revision: c42141216e05b92eedebdaae7565e596d0a7267e

URL: 
https://github.com/llvm/llvm-project/commit/c42141216e05b92eedebdaae7565e596d0a7267e
DIFF: 
https://github.com/llvm/llvm-project/commit/c42141216e05b92eedebdaae7565e596d0a7267e.diff

LOG: Fixed C test case

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c

Modified: 


Removed: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.c



diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
similarity index 75%
rename from llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
rename to clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
index f401cd8cf7c77..c72ede258c6aa 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
@@ -10,111 +10,111 @@
 double test_fcfid(double a) {
   // CHECK-LABEL: test_fcfid
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fcfid(double %0)
+  // CHECK: double @llvm.ppc.fcfid(double %a)
   return __builtin_ppc_fcfid(a);
 }
 
 double test_xl_fcfid(double a) {
   // CHECK-LABEL: test_xl_fcfid
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fcfid(double %0)
+  // CHECK: double @llvm.ppc.fcfid(double %a)
   return __fcfid(a);
 }
 
 double test_fcfud(double a) {
   // CHECK-LABEL: test_fcfud
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fcfud(double %0)
+  // CHECK: double @llvm.ppc.fcfud(double %a)
   return __builtin_ppc_fcfud(a);
 }
 
 double test_xl_fcfud(double a) {
   // CHECK-LABEL: test_xl_fcfud
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fcfud(double %0)
+  // CHECK: double @llvm.ppc.fcfud(double %a)
   return __fcfud(a);
 }
 
 double test_fctid(double a) {
   // CHECK-LABEL: test_fctid
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctid(double %a)
   return __builtin_ppc_fctid(a);
 }
 
 double test_xl_fctid(double a) {
   // CHECK-LABEL: test_xl_fctid
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctid(double %a)
   return __fctid(a);
 }
 
 double test_fctidz(double a) {
   // CHECK-LABEL: test_fctidz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctidz(double %a)
   return __builtin_ppc_fctidz(a);
 }
 
 double test_xl_fctidz(double a) {
   // CHECK-LABEL: test_xl_fctidz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctidz(double %a)
   return __fctidz(a);
 }
 
 double test_fctiw(double a) {
   // CHECK-LABEL: test_fctiw
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctiw(double %a)
   return __builtin_ppc_fctiw(a);
 }
 
 double test_xl_fctiw(double a) {
   // CHECK-LABEL: test_xl_fctiw
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctiw(double %a)
   return __fctiw(a);
 }
 
 double test_fctiwz(double a) {
   // CHECK-LABEL: test_fctiwz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctiwz(double %a)
   return __builtin_ppc_fctiwz(a);
 }
 
 double test_xl_fctiwz(double a) {
   // CHECK-LABEL: test_xl_fctiwz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctiwz(double %a)
   return __fctiwz(a);
 }
 
 double test_fctudz(double a) {
   // CHECK-LABEL: test_fctudz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctudz(double %a)
   return __builtin_ppc_fctudz(a);
 }
 
 double test_xl_fctudz(double a) {
   // CHECK-LABEL: test_xl_fctudz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctudz(double %a)
   return __fctudz(a);
 }
 
 double test_fctuwz(double a) {
   // CHECK-LABEL: test_fctuwz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctuwz(double %a)
   return __builtin_ppc_fctuwz(a);
 }
 
 double test_xl_fctuwz(double a) {
   // CHECK-LABEL: test_xl_fctuwz
   // CHECK-NEXT: entry:
-  // CHECK: double @llvm.ppc.fctid(double %0)
+  // CHECK: double @llvm.ppc.fctuwz(double %a)
   return __fctuwz(a);
-}
\ No newline at end of file
+}

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
new file mode 100644
index 0..bd66b34773cdb
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -O2 -triple powerpc

[llvm-branch-commits] [clang] 67bad64 - temp signed impelmentation

2021-06-25 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-25T15:35:28-05:00
New Revision: 67bad646076dfb46482b5bd5eeb80d14c168dcd4

URL: 
https://github.com/llvm/llvm-project/commit/67bad646076dfb46482b5bd5eeb80d14c168dcd4
DIFF: 
https://github.com/llvm/llvm-project/commit/67bad646076dfb46482b5bd5eeb80d14c168dcd4.diff

LOG: temp signed impelmentation

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ddd5605acaba..2f4955500f9c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15354,13 +15354,10 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 auto Signed = getIntegerWidthAndSignedness(CGM.getContext(),
  E->getArg(1)->getType()).Signed;
 
-if (Signed) {
-  dbgs() << "SIGNED\n";
+if (Signed)
   Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
-} else {
-  dbgs() << "UNSIGNED\n";
+else
   Ops[1] = Builder.CreateZExt(Ops[1], Int32Ty);
-}
 return Builder.CreateCall(F, Ops);
   }
 



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[llvm-branch-commits] [llvm] e2de46a - Updated tests

2021-06-28 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-28T15:21:49-05:00
New Revision: e2de46a63bcaeac2ed3511608c43de1e3c7abccd

URL: 
https://github.com/llvm/llvm-project/commit/e2de46a63bcaeac2ed3511608c43de1e3c7abccd
DIFF: 
https://github.com/llvm/llvm-project/commit/e2de46a63bcaeac2ed3511608c43de1e3c7abccd.diff

LOG: Updated tests

Added: 


Modified: 
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index c4bf8af943d3b..c325946290c17 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2230,6 +2230,15 @@ def TDI : DForm_base<2, (outs), (ins u5imm:$to, 
g8rc:$rA, s16imm:$imm),
 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
  "td $to, $rA, $rB", IIC_IntTrapD, []>;
 
+def : InstAlias<"tdlle $rA, $rB", (TD 6, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdlge $rA, $rB", (TD 5, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdge $rA, $rB", (TD 12, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdle $rA, $rB", (TD 20, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"twlle $rA, $rB", (TW 6, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twlge $rA, $rB", (TW 5, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twge $rA, $rB", (TW 12, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twle $rA, $rB", (TW 20, gprc:$rA, gprc:$rB)>;
+
 
//===--===//
 // PPC32 Load Instructions.
 //

diff  --git 
a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
index c70a99fca936b..c1bcf28e464d9 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -9,61 +9,109 @@
 ; tdw
 declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
 define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdlgt 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
   ret void
 }
 
 define dso_local void @test__tdwllt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdllt 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
   ret void
 }
 
 define dso_local void @test__tdweq(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdeq 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
   ret void
 }
 
 define dso_local void @test__tdwlge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 5, 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
   ret void
 }
 
 define dso_local void @test__tdwlle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 6, 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
   ret void
 }
 
 define dso_local void @test__tdwgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdgt 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
   ret void
 }
 
 define dso_local void @test__tdwge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 12, 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
   ret void
 }
 
 define dso_local void @test__tdwlt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdlt 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
   ret void
 }
 
 define dso_local void @test__tdwle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 20, 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
   ret void
 }
 
 define dso_local void @test__tdwne24(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdne 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
   ret void
 }
 
 define dso_local void @test__tdweq31(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq31:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdeq 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
   ret void
 }
 
 define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 13, 3, 4
+; CHECK-NEXT:blr
   call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
   ret void
 }
@@ -71,6 +119,10 @@ define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
 ; trapd
 declare void @llvm.ppc.trapd(i64 %a)
 

[llvm-branch-commits] [clang] 7921f04 - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-29 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-29T02:41:56-05:00
New Revision: 7921f048e0ccfbbc08d2176bbe0fcfb160b63c07

URL: 
https://github.com/llvm/llvm-project/commit/7921f048e0ccfbbc08d2176bbe0fcfb160b63c07
DIFF: 
https://github.com/llvm/llvm-project/commit/7921f048e0ccfbbc08d2176bbe0fcfb160b63c07.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 47b485473342b..c660d8e2a3448 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -47,6 +47,18 @@ BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e051826c52168..5a28ed95f5ca9 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -100,6 +100,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
   Builder.defineMacro("__compare_and_swaplp",
   "__builtin_ppc_compare_and_swaplp");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 17eeebb0c6799..587eaf63a9e8d 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3261,6 +3261,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_ppc_tdw:
+  case PPC::BI__builtin_ppc_trapd:
 return true;
   }
   return false;
@@ -3341,6 +3343,21 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+// return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&

[llvm-branch-commits] [clang] 666a204 - Removed unneccessary comments

2021-06-29 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-29T02:46:17-05:00
New Revision: 666a2043718050e4f34f7b50d74a7e7b2e882d93

URL: 
https://github.com/llvm/llvm-project/commit/666a2043718050e4f34f7b50d74a7e7b2e882d93
DIFF: 
https://github.com/llvm/llvm-project/commit/666a2043718050e4f34f7b50d74a7e7b2e882d93.diff

LOG: Removed unneccessary comments

Added: 


Modified: 
clang/lib/Sema/SemaChecking.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 587eaf63a9e8..e8d45bfe4aab 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3347,17 +3347,8 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
 return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   }
   case PPC::BI__builtin_ppc_tdw: {
-// return TI.getTypeWidth(TI.getIntPtrType()) == 64 &&
-   return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
-  }
-  // case PPC::BI__builtin_ppc_fcfid:
-  // case PPC::BI__builtin_ppc_fcfud:
-  // case PPC::BI__builtin_ppc_fctid:
-  // case PPC::BI__builtin_ppc_fctidz:
-  // case PPC::BI__builtin_ppc_fctudz:
-  // case PPC::BI__builtin_ppc_trapd: {
-// TI.getTypeWidth(TI.getIntPtrType()) == 64;
-  // }
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);



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[llvm-branch-commits] [clang] b20da27 - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-29 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-29T02:47:08-05:00
New Revision: b20da27fb4570a2aefe2d72d20565e054269f827

URL: 
https://github.com/llvm/llvm-project/commit/b20da27fb4570a2aefe2d72d20565e054269f827
DIFF: 
https://github.com/llvm/llvm-project/commit/b20da27fb4570a2aefe2d72d20565e054269f827.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 47b485473342b..c660d8e2a3448 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -47,6 +47,18 @@ BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e051826c52168..5a28ed95f5ca9 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -100,6 +100,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
   Builder.defineMacro("__compare_and_swaplp",
   "__builtin_ppc_compare_and_swaplp");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 17eeebb0c6799..e8d45bfe4aabb 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3261,6 +3261,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_ppc_tdw:
+  case PPC::BI__builtin_ppc_trapd:
 return true;
   }
   return false;
@@ -3341,6 +3343,12 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);

[llvm-branch-commits] [clang] baf0121 - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-06-29 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-06-29T02:49:36-05:00
New Revision: baf01216133277b44acdacb2de0c80aa44512bd1

URL: 
https://github.com/llvm/llvm-project/commit/baf01216133277b44acdacb2de0c80aa44512bd1
DIFF: 
https://github.com/llvm/llvm-project/commit/baf01216133277b44acdacb2de0c80aa44512bd1.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 47b485473342b..c660d8e2a3448 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -47,6 +47,18 @@ BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e051826c52168..5a28ed95f5ca9 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -100,6 +100,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
   Builder.defineMacro("__compare_and_swaplp",
   "__builtin_ppc_compare_and_swaplp");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 17eeebb0c6799..640f0b6fc9ea6 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3261,6 +3261,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_ppc_tdw:
+  case PPC::BI__builtin_ppc_trapd:
 return true;
   }
   return false;
@@ -3341,6 +3343,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw:
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  case PPC::BI__builtin_ppc_tdw:
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
 #define

[llvm-branch-commits] [llvm] 004c12b - [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-09 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-08T15:05:44-05:00
New Revision: 004c12b29997e29ce0105b314090e16649908152

URL: 
https://github.com/llvm/llvm-project/commit/004c12b29997e29ce0105b314090e16649908152
DIFF: 
https://github.com/llvm/llvm-project/commit/004c12b29997e29ce0105b314090e16649908152.diff

LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

Differential Revision: https://reviews.llvm.org/D103668

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index baaf5db9d1453..6a72cc089df7e 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -59,6 +59,18 @@ BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
+BUILTIN(__builtin_ppc_tw, "viiIUi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e3c77b2e4450b..b77b4a38bc46f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -112,6 +112,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 64d838d2cd74f..99621a226dea6 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3267,6 +3267,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_bpermd:
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_stdcx:
+  case PPC::BI__builtin_ppc_tdw:
+  case PPC::BI__builtin_ppc_trapd:
 return true;
   }
   return false;
@@ -3347,6 +3349,9 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
  return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw:
+  case PPC::BI__builtin_ppc_tdw:
+return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
new file mode 100644
index 0..babc16fcd3a7e
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
@@ -0,0 +1,121 

[llvm-branch-commits] [llvm] d67cbe8 - Fixed LDARX

2021-07-09 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-09T19:35:15-05:00
New Revision: d67cbe8b31a91fedd0233479eaded16af55e750f

URL: 
https://github.com/llvm/llvm-project/commit/d67cbe8b31a91fedd0233479eaded16af55e750f
DIFF: 
https://github.com/llvm/llvm-project/commit/d67cbe8b31a91fedd0233479eaded16af55e750f.diff

LOG: Fixed LDARX

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2c24b71d030ae..4b6b9c905254c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,49 @@ static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction 
&CGF,
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitLoadReserveIntrinsic(CodeGenFunction &CGF,
+ unsigned BuiltinID,
+ const CallExpr *E) {
+  Value *addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *retType = CGF.Int32Ty;
+
+  switch(BuiltinID) {
+case clang::PPC::BI__builtin_ppc_ldarx:
+  AsmOS << "ldarx ";
+  retType = CGF.Int64Ty;
+  break;
+case clang::PPC::BI__builtin_ppc_lwarx:
+  AsmOS << "lwarx ";
+  dbgs() << "LWARX\n";
+  retType = CGF.Int32Ty;
+  break;
+  }
+
+  AsmOS << "$0, $1";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::IntegerType *IntType = llvm::IntegerType::get(
+  CGF.getLLVMContext(),
+  CGF.getContext().getTypeSize(E->getArg(0)->getType()));
+  llvm::Type *IntPtrType = IntType->getPointerTo();
+  dbgs() << E->getArg(0)->getType().getAsString() << " HAHA\n";
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(retType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {addr});
+}
+
 namespace {
 enum class MSVCSetJmpKind {
   _setjmpex,
@@ -5103,6 +5146,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl 
GD, unsigned BuiltinID,
  Str.getPointer(), Zeros);
 return RValue::get(Ptr);
   }
+  case clang::PPC::BI__builtin_ppc_ldarx:
+  case clang::PPC::BI__builtin_ppc_lwarx:
+return RValue::get(emitLoadReserveIntrinsic(*this, BuiltinID, E));
   }
 
   // If this is an alias for a lib function (e.g. __builtin_sin), emit

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ad6a1e8d1a7a7..3ed156d7137ea 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@ let TargetPrefix = "ppc" in {
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index dc6a0c1a30e1c..ac6f4e5844a5b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@ def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", 
IIC_SprSLBSYNC, []>;
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 20429ee664b21..8d59cd8185c5e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@ def DWBytes3210 {
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;



___
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[llvm-branch-commits] [clang] 773beb6 - [PowerPC] Fix L[D|W]ARX Implementation

2021-07-10 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-09T20:56:41-05:00
New Revision: 773beb6fbed7fa7200ab35b88bf6b954628566cf

URL: 
https://github.com/llvm/llvm-project/commit/773beb6fbed7fa7200ab35b88bf6b954628566cf
DIFF: 
https://github.com/llvm/llvm-project/commit/773beb6fbed7fa7200ab35b88bf6b954628566cf.diff

LOG: [PowerPC] Fix L[D|W]ARX Implementation

LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.

Differential Revision: https://reviews.llvm.org/D105754

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2c24b71d030a..059dd4059818 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,44 @@ static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction 
&CGF,
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitLoadReserveIntrinsic(CodeGenFunction &CGF,
+ unsigned BuiltinID,
+ const CallExpr *E) {
+  Value *addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *RetType = CGF.Int32Ty;
+
+  switch (BuiltinID) {
+  case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+  }
+
+  AsmOS << "$0, ${1:y}";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::Type *IntPtrType = RetType->getPointerTo();
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {addr});
+}
+
 namespace {
 enum class MSVCSetJmpKind {
   _setjmpex,
@@ -5103,6 +5141,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl 
GD, unsigned BuiltinID,
  Str.getPointer(), Zeros);
 return RValue::get(Ptr);
   }
+  case clang::PPC::BI__builtin_ppc_ldarx:
+  case clang::PPC::BI__builtin_ppc_lwarx:
+return RValue::get(emitLoadReserveIntrinsic(*this, BuiltinID, E));
   }
 
   // If this is an alias for a lib function (e.g. __builtin_sin), emit

diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
index 80bb4de424a1..47aa1b973399 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -10,8 +10,7 @@
 long test_ldarx(volatile long* a) {
   // CHECK64-LABEL: @test_ldarx
   // CHECK64: %0 = load i64*, i64** %a.addr, align 8
-  // CHECK64: %1 = bitcast i64* %0 to i8*
-  // CHECK64: %2 = call i64 @llvm.ppc.ldarx(i8* %1)
+  // CHECK64: %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i64* %0)
   // CHECK32-ERROR: error: this builtin is only available on 64-bit targets
   return __ldarx(a);
 }

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
index 5b807973894e..9d41608a0de8 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -9,8 +9,8 @@
 
 int test_lwarx(volatile int* a) {
   // CHECK: @test_lwarx
-  // CHECK: %1 = bitcast i32* %0 to i8*
-  // CHECK: %2 = call i32 @llvm.ppc.lwarx(i8* %1)
+  // CHECK: %0 = load i32*, i32** %a.addr, align
+  // CHECK: %1 = call i32 asm sideeffect "lwarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i32* %0)
   return __lwarx(a);
 }
 int test_stwcx(volatile int* a, int val) {

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ad6a1e8d1a7a..3ed156d7137e 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@ let TargetPrefix = "ppc" in {
   d

[llvm-branch-commits] [clang] a18b3c5 - [PowerPC] Fix L[D|W]ARX Implementation

2021-07-11 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-11T22:00:21-05:00
New Revision: a18b3c586876ae7bf011705feb0b8756b8063a0f

URL: 
https://github.com/llvm/llvm-project/commit/a18b3c586876ae7bf011705feb0b8756b8063a0f
DIFF: 
https://github.com/llvm/llvm-project/commit/a18b3c586876ae7bf011705feb0b8756b8063a0f.diff

LOG: [PowerPC] Fix L[D|W]ARX Implementation

LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.

Differential Revision: https://reviews.llvm.org/D105754

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 41ea2bf5f43a..e417cfb34f3a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,46 @@ static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction 
&CGF,
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitPPCLoadReserveIntrinsic(CodeGenFunction &CGF,
+ unsigned BuiltinID,
+ const CallExpr *E) {
+  Value *Addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *RetType = CGF.Int32Ty;
+
+  switch (BuiltinID) {
+  case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+  default:
+llvm_unreachable("Expected only PowerPC load reserve intrinsics");
+  }
+
+  AsmOS << "$0, ${1:y}";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::Type *IntPtrType = RetType->getPointerTo();
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {Addr});
+}
+
 namespace {
 enum class MSVCSetJmpKind {
   _setjmpex,
@@ -15532,6 +15572,9 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return MakeBinaryAtomicValue(*this, AtomicRMWInst::Xchg, E,
  llvm::AtomicOrdering::Monotonic);
   }
+  case PPC::BI__builtin_ppc_ldarx:
+  case PPC::BI__builtin_ppc_lwarx:
+return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
   }
 }
 

diff  --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c 
b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
index ae3a2305fd71..9e050e044c30 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
@@ -1,7 +1,7 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d 
-target-feature +experimental-v \
-// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s 
-o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s 
-o - | opt -S -mem2reg --mtriple=riscv64 | FileCheck --check-prefix=CHECK-RV64 
%s
 
 #include 
 

diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
index 80bb4de424a1..f0a8ff184311 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -1,27 +1,23 @@
 // RUN: not %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
 // RUN: FileCheck %s --check-prefix=CHECK32-ERROR
-// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
 // RUN: FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -O2 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:  -

[llvm-branch-commits] [clang] b7df33f - [PowerPC] Fix L[D|W]ARX Implementation

2021-07-11 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-11T22:02:30-05:00
New Revision: b7df33f4ada9cbfa4ac2bb2b251497dc12e4d648

URL: 
https://github.com/llvm/llvm-project/commit/b7df33f4ada9cbfa4ac2bb2b251497dc12e4d648
DIFF: 
https://github.com/llvm/llvm-project/commit/b7df33f4ada9cbfa4ac2bb2b251497dc12e4d648.diff

LOG: [PowerPC] Fix L[D|W]ARX Implementation

LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.

Differential Revision: https://reviews.llvm.org/D105754

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 41ea2bf5f43a..ed81523540b2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,46 @@ static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction 
&CGF,
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitPPCLoadReserveIntrinsic(CodeGenFunction &CGF,
+unsigned BuiltinID,
+const CallExpr *E) {
+  Value *Addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *RetType = CGF.Int32Ty;
+
+  switch (BuiltinID) {
+  case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+  default:
+llvm_unreachable("Expected only PowerPC load reserve intrinsics");
+  }
+
+  AsmOS << "$0, ${1:y}";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::Type *IntPtrType = RetType->getPointerTo();
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {Addr});
+}
+
 namespace {
 enum class MSVCSetJmpKind {
   _setjmpex,
@@ -15532,6 +15572,9 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return MakeBinaryAtomicValue(*this, AtomicRMWInst::Xchg, E,
  llvm::AtomicOrdering::Monotonic);
   }
+  case PPC::BI__builtin_ppc_ldarx:
+  case PPC::BI__builtin_ppc_lwarx:
+return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
   }
 }
 

diff  --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c 
b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
index ae3a2305fd71..9e050e044c30 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
@@ -1,7 +1,7 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d 
-target-feature +experimental-v \
-// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s 
-o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s 
-o - | opt -S -mem2reg --mtriple=riscv64 | FileCheck --check-prefix=CHECK-RV64 
%s
 
 #include 
 

diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
index 80bb4de424a1..f0a8ff184311 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -1,27 +1,23 @@
 // RUN: not %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
 // RUN: FileCheck %s --check-prefix=CHECK32-ERROR
-// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
 // RUN: FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -O2 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
 // R

[llvm-branch-commits] [llvm] ffa2430 - Init implementation

2021-07-13 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-13T20:00:05-05:00
New Revision: ffa243081676383b5b3dc0f7b63cb19ec55d92be

URL: 
https://github.com/llvm/llvm-project/commit/ffa243081676383b5b3dc0f7b63cb19ec55d92be
DIFF: 
https://github.com/llvm/llvm-project/commit/ffa243081676383b5b3dc0f7b63cb19ec55d92be.diff

LOG: Init implementation

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 09769b3f974e..b8a14f85a4bd 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -83,6 +83,7 @@ BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
 BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
+BUILTIN(__builtin_ppc_mfspr, "ULiiC", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b79b30d7a4cd..2ecafa095dac 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -140,6 +140,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
   Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
   Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
+  Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa143695418..94ebb60fdd19 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15463,7 +15463,6 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
 return Builder.CreateExtractElement(Unpacked, Index);
   }
-
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to
@@ -15575,6 +15574,18 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+  case PPC::BI__builtin_ppc_mfspr: {
+dbgs() <<"Hello\n";
+llvm::Type *src0 = EmitScalarExpr(E->getArg(0))->getType();
+src0->dump();
+dbgs() << "Ops size: " << Ops.size() << "\n";
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, src0);
+// uint64_t Imm = cast(Ops[0])->getZExtValue();
+// Ops[0] = llvm::ConstantInt::get(Int32Ty, Imm);
+Value *temp =  Builder.CreateCall(F, Ops);
+temp->dump();
+return temp;
+  }
   }
 }
 

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b021b43afe59..2e5600e68f53 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1598,5 +1598,7 @@ let TargetPrefix = "ppc" in {
   def int_ppc_maddld
   : GCCBuiltin<"__builtin_ppc_maddld">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 
[IntrNoMem]>;
+
+  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
 }
 

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 496f76b69d2e..a709b496d75e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -412,7 +412,6 @@ def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins 
i32imm:$SPR),
 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
"mtspr $SPR, $RT", IIC_SprMTSPR>;
 
-
 
//===--===//
 // 64-bit SPR manipulation instrs.
 
@@ -1749,3 +1748,5 @@ def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
   (TDI 24, $A, 0)>;
+def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
+  (MFSPR $SPR)>;

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index d97881fe818b..6d592c9f9953 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5445,3 +5445,5 @@ def : Pat<(int_ppc_fctudz f64:$A),
 (XSCVDPUXDS $A)>;
 def : Pat<(int_ppc_fctuwz f64:$A),
 (XSCVDPUXWS $A)>;
+def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
+  (MFSPR $SPR)>;



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[llvm-branch-commits] [clang] 09df619 - Implementation of STBCX

2021-07-13 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-13T21:30:09-05:00
New Revision: 09df6199e796f9855c3fbc78df0eb42ff278cdb2

URL: 
https://github.com/llvm/llvm-project/commit/09df6199e796f9855c3fbc78df0eb42ff278cdb2
DIFF: 
https://github.com/llvm/llvm-project/commit/09df6199e796f9855c3fbc78df0eb42ff278cdb2.diff

LOG: Implementation of STBCX

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 09769b3f974e..a214c4e1cc7b 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -58,6 +58,7 @@ BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*c", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b79b30d7a4cd..a428f0c3a9f7 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -118,6 +118,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa143695418..b886f270615e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,6 +15575,21 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+  case PPC::BI__builtin_ppc_stbcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_stbcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+auto Signed = getIntegerWidthAndSignedness(CGM.getContext(),
+ E->getArg(1)->getType()).Signed;
+
+if (Signed) {
+  dbgs() << "SIGNED\n";
+  Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+} else {
+  dbgs() << "UNSIGNED\n";
+  Ops[1] = Builder.CreateZExt(Ops[1], Int32Ty);
+}
+return Builder.CreateCall(F, Ops);
+  }
   }
 }
 

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b021b43afe59..d95823ef59c5 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1565,6 +1565,7 @@ let TargetPrefix = "ppc" in {
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
+  def int_ppc_stbcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
   // compare
   def int_ppc_cmpeqb
   : GCCBuiltin<"__builtin_ppc_cmpeqb">,

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index d97881fe818b..2e8ca2df241e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5445,3 +5445,5 @@ def : Pat<(int_ppc_fctudz f64:$A),
 (XSCVDPUXDS $A)>;
 def : Pat<(int_ppc_fctuwz f64:$A),
 (XSCVDPUXWS $A)>;
+def : Pat<(int_ppc_stbcx xoaddr:$dst, gprc:$A),
+  (STBCX gprc:$A, xoaddr:$dst)>;



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[llvm-branch-commits] [clang] 7af1432 - Working (ish) version

2021-07-13 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-13T21:57:27-05:00
New Revision: 7af1432f63a2fe3d8902a5486eba5ba25dd3f509

URL: 
https://github.com/llvm/llvm-project/commit/7af1432f63a2fe3d8902a5486eba5ba25dd3f509
DIFF: 
https://github.com/llvm/llvm-project/commit/7af1432f63a2fe3d8902a5486eba5ba25dd3f509.diff

LOG: Working (ish) version

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 94ebb60fdd19..2dccd17bb8ee 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,15 +15575,10 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
   case PPC::BI__builtin_ppc_mfspr: {
-dbgs() <<"Hello\n";
-llvm::Type *src0 = EmitScalarExpr(E->getArg(0))->getType();
-src0->dump();
-dbgs() << "Ops size: " << Ops.size() << "\n";
-Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, src0);
-// uint64_t Imm = cast(Ops[0])->getZExtValue();
-// Ops[0] = llvm::ConstantInt::get(Int32Ty, Imm);
+// llvm::Type *src0 = EmitScalarExpr(E->getArg(0))->getType();
+dbgs() << "Width: " << Ops[0]->getType()->getPrimitiveSizeInBits() << "\n";
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, Int64Ty);
 Value *temp =  Builder.CreateCall(F, Ops);
-temp->dump();
 return temp;
   }
   }

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 2e5600e68f53..c1b421e168a6 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1599,6 +1599,6 @@ let TargetPrefix = "ppc" in {
   : GCCBuiltin<"__builtin_ppc_maddld">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 
[IntrNoMem]>;
 
-  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
+  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
 }
 

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index a709b496d75e..d245cc596e64 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1748,5 +1748,5 @@ def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
   (TDI 24, $A, 0)>;
-def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
-  (MFSPR $SPR)>;
+def : Pat<(i64 (int_ppc_mfspr i32:$SPR)),
+  (MFSPR8 $SPR)>;



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[llvm-branch-commits] [llvm] 8a8377e - Implementation of STBCX

2021-07-14 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-14T09:39:47-05:00
New Revision: 8a8377e1d2324f2631badbd02dc4ff0fd824ebb1

URL: 
https://github.com/llvm/llvm-project/commit/8a8377e1d2324f2631badbd02dc4ff0fd824ebb1
DIFF: 
https://github.com/llvm/llvm-project/commit/8a8377e1d2324f2631badbd02dc4ff0fd824ebb1.diff

LOG: Implementation of STBCX

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 09769b3f974eb..a214c4e1cc7b3 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -58,6 +58,7 @@ BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*c", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b79b30d7a4cdb..a428f0c3a9f70 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -118,6 +118,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..b886f270615ed 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,6 +15575,21 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+  case PPC::BI__builtin_ppc_stbcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_stbcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+auto Signed = getIntegerWidthAndSignedness(CGM.getContext(),
+ E->getArg(1)->getType()).Signed;
+
+if (Signed) {
+  dbgs() << "SIGNED\n";
+  Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+} else {
+  dbgs() << "UNSIGNED\n";
+  Ops[1] = Builder.CreateZExt(Ops[1], Int32Ty);
+}
+return Builder.CreateCall(F, Ops);
+  }
   }
 }
 

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
index 4ffa29a094558..7ae412a6c4803 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -18,3 +18,18 @@ int test_stwcx(volatile int* a, int val) {
   // CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
   return __stwcx(a, val);
 }
+
+int test_stbcx_signed(volatile char* a, signed char val) {
+  // TODO: fix current zext code gen to sext
+  // CHECK-LABEL: @test_stbcx_signed
+  // CHECK: %0 = sext i8 %b to i32
+  // CHECK: tail call i32 @llvm.ppc.stbcx(i8 *a, i32 %0)
+  return __stbcx(a, val);
+}
+
+int test_stbcx_unsigned(volatile char* a, unsigned char val) {
+  // CHECK-LABEL: @test_stbcx_unsigned
+  // CHECK: %0 = zext i8 %b to i32
+  // CHECK: tail call i32 @llvm.ppc.stbcx(i8 *a, i32 %0)
+  return __stbcx(a, val);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b021b43afe595..d95823ef59c52 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1565,6 +1565,7 @@ let TargetPrefix = "ppc" in {
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
+  def int_ppc_stbcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
   // compare
   def int_ppc_cmpeqb
   : GCCBuiltin<"__builtin_ppc_cmpeqb">,

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index d97881fe818bc..2e8ca2df241e0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5445,3 +5445,5 @@ def : Pat<(int_ppc_fctudz f64:$A),
 (XSCVDP

[llvm-branch-commits] [llvm] 2584eb9 - [PowerPC] Store, load, move from and to registers related builtins

2021-07-14 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-14T13:13:39-05:00
New Revision: 2584eb9d2050300fa01b7fd2e422acc788a46873

URL: 
https://github.com/llvm/llvm-project/commit/2584eb9d2050300fa01b7fd2e422acc788a46873
DIFF: 
https://github.com/llvm/llvm-project/commit/2584eb9d2050300fa01b7fd2e422acc788a46873.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

  This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.

Differential Revision: https://reviews.llvm.org/D105946

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..b311c52235a2a 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -57,8 +57,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -71,6 +74,10 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..1b43680799bf8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -116,8 +116,11 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -130,6 +133,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..fc2fb6a2f454f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15464,6 +15464,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e5..8

[llvm-branch-commits] [llvm] 89ccbda - [PowerPC] Implement MFSPR, MTMSR, MTSPR builtins

2021-07-14 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-14T14:33:39-05:00
New Revision: 89ccbdabb57b0782b2029a80c77d261e6fa6a138

URL: 
https://github.com/llvm/llvm-project/commit/89ccbdabb57b0782b2029a80c77d261e6fa6a138
DIFF: 
https://github.com/llvm/llvm-project/commit/89ccbdabb57b0782b2029a80c77d261e6fa6a138.diff

LOG: [PowerPC] Implement MFSPR, MTMSR, MTSPR builtins

The builtins for mtmsr, mtspr, mfspr are implemented in this patch.
This is for xlC compatibility.

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 94ebb60fdd19..3ffec5bf118f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,16 +15575,11 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
   case PPC::BI__builtin_ppc_mfspr: {
-dbgs() <<"Hello\n";
-llvm::Type *src0 = EmitScalarExpr(E->getArg(0))->getType();
-src0->dump();
-dbgs() << "Ops size: " << Ops.size() << "\n";
-Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, src0);
-// uint64_t Imm = cast(Ops[0])->getZExtValue();
-// Ops[0] = llvm::ConstantInt::get(Int32Ty, Imm);
-Value *temp =  Builder.CreateCall(F, Ops);
-temp->dump();
-return temp;
+llvm::Type *RetType = 
+  CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 32 ? Int32Ty :
+   Int64Ty;
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, RetType);
+return Builder.CreateCall(F, Ops);
   }
   }
 }

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 2e5600e68f53..c1b421e168a6 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1599,6 +1599,6 @@ let TargetPrefix = "ppc" in {
   : GCCBuiltin<"__builtin_ppc_maddld">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 
[IntrNoMem]>;
 
-  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
+  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
 }
 

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index a709b496d75e..d245cc596e64 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1748,5 +1748,5 @@ def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
   (TDI 24, $A, 0)>;
-def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
-  (MFSPR $SPR)>;
+def : Pat<(i64 (int_ppc_mfspr i32:$SPR)),
+  (MFSPR8 $SPR)>;



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[llvm-branch-commits] [clang] ad97d39 - [PowerPC] Store, load, move from and to registers related builtins

2021-07-14 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-14T15:52:48-05:00
New Revision: ad97d39617e4e62fd45c10539014fcd6812252f2

URL: 
https://github.com/llvm/llvm-project/commit/ad97d39617e4e62fd45c10539014fcd6812252f2
DIFF: 
https://github.com/llvm/llvm-project/commit/ad97d39617e4e62fd45c10539014fcd6812252f2.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

  This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.

Differential Revision: https://reviews.llvm.org/D105946

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..b311c52235a2a 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -57,8 +57,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -71,6 +74,10 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..1b43680799bf8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -116,8 +116,11 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -130,6 +133,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..fc2fb6a2f454f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15464,6 +15464,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e5..9

[llvm-branch-commits] [clang] f29785c - [PowerPC] Store, load, move from and to registers related builtins

2021-07-14 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-14T15:55:56-05:00
New Revision: f29785c0171867901cbe324058be1e997dd52e75

URL: 
https://github.com/llvm/llvm-project/commit/f29785c0171867901cbe324058be1e997dd52e75
DIFF: 
https://github.com/llvm/llvm-project/commit/f29785c0171867901cbe324058be1e997dd52e75.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

  This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.

Differential Revision: https://reviews.llvm.org/D105946

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..b311c52235a2a 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -57,8 +57,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -71,6 +74,10 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..1b43680799bf8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -116,8 +116,11 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -130,6 +133,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..fc2fb6a2f454f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15464,6 +15464,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e5..9

[llvm-branch-commits] [clang] 9601c05 - [PowerPC] Store, load, move from and to registers related builtins

2021-07-15 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-15T13:28:27-05:00
New Revision: 9601c05a241144d53aacd962c835c14676165f8e

URL: 
https://github.com/llvm/llvm-project/commit/9601c05a241144d53aacd962c835c14676165f8e
DIFF: 
https://github.com/llvm/llvm-project/commit/9601c05a241144d53aacd962c835c14676165f8e.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

  This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.

Differential Revision: https://reviews.llvm.org/D105946

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..b311c52235a2a 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -57,8 +57,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -71,6 +74,10 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..1b43680799bf8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -116,8 +116,11 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -130,6 +133,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..fc2fb6a2f454f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15464,6 +15464,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e5..6

[llvm-branch-commits] [clang] da6b871 - [PowerPC] Implement MFSPR, MTMSR, MTSPR builtins

2021-07-15 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-15T14:29:09-05:00
New Revision: da6b871e66c933fc0c33ac4eddb1db479321c33d

URL: 
https://github.com/llvm/llvm-project/commit/da6b871e66c933fc0c33ac4eddb1db479321c33d
DIFF: 
https://github.com/llvm/llvm-project/commit/da6b871e66c933fc0c33ac4eddb1db479321c33d.diff

LOG: [PowerPC] Implement MFSPR, MTMSR, MTSPR builtins

The builtins for mtmsr, mtspr, mfspr are implemented in this patch.
This is for xlC compatibility.

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index b8a14f85a4bdd..f0ac3eee2b3a8 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -84,6 +84,8 @@ BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_mfspr, "ULiiC", "")
+BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
+BUILTIN(__builtin_ppc_mtspr, "viCULi", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 94ebb60fdd193..019dc0350be69 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,16 +15575,18 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
   case PPC::BI__builtin_ppc_mfspr: {
-dbgs() <<"Hello\n";
-llvm::Type *src0 = EmitScalarExpr(E->getArg(0))->getType();
-src0->dump();
-dbgs() << "Ops size: " << Ops.size() << "\n";
-Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, src0);
-// uint64_t Imm = cast(Ops[0])->getZExtValue();
-// Ops[0] = llvm::ConstantInt::get(Int32Ty, Imm);
-Value *temp =  Builder.CreateCall(F, Ops);
-temp->dump();
-return temp;
+llvm::Type *RetType =
+  CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 32 ? Int32Ty :
+   Int64Ty;
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, RetType);
+return Builder.CreateCall(F, Ops);
+  }
+  case PPC::BI__builtin_ppc_mtspr: {
+llvm::Type *RetType =
+  CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 32 ? Int32Ty :
+   Int64Ty;
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtspr, RetType);
+return Builder.CreateCall(F, Ops);
   }
   }
 }

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 2e5600e68f53b..0f9206855becf 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1599,6 +1599,10 @@ let TargetPrefix = "ppc" in {
   : GCCBuiltin<"__builtin_ppc_maddld">,
 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 
[IntrNoMem]>;
 
-  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
+  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], 
[ImmArg>]>;
+  def int_ppc_mtmsr
+  : GCCBuiltin<"__builtin_ppc_mtmsr">, Intrinsic<[], [llvm_i32_ty], []>;
+  def int_ppc_mtspr
+  : Intrinsic<[], [llvm_i32_ty, llvm_anyint_ty], [ImmArg>]>;
 }
 

diff  --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td 
b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index a709b496d75e6..08bd7a9a183bc 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1748,5 +1748,7 @@ def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
   (TDI 24, $A, 0)>;
-def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
-  (MFSPR $SPR)>;
+def : Pat<(i64 (int_ppc_mfspr i32:$SPR)),
+  (MFSPR8 $SPR)>;
+def : Pat<(int_ppc_mtspr i32:$SPR, g8rc:$RT),
+  (MTSPR8 $SPR, $RT)>;

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 6d592c9f99532..6d7c1a6e20518 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5447,3 +5447,7 @@ def : Pat<(int_ppc_fctuwz f64:$A),
 (XSCVDPUXWS $A)>;
 def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
   (MFSPR $SPR)>;
+def : Pat<(int_ppc_mtspr i32:$SPR, gprc:$RT),
+  (MTSPR $SPR, $RT)>;
+def : Pat<(int_ppc_mtmsr gprc:$RS),
+  (MTMSR $RS, 0)>;



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[llvm-branch-commits] [llvm] ae5052d - [PowerPC] Store, load, move from and to registers related builtins

2021-07-15 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-15T14:52:57-05:00
New Revision: ae5052d2500626b3fc29d7a4778ccef0b95abaf2

URL: 
https://github.com/llvm/llvm-project/commit/ae5052d2500626b3fc29d7a4778ccef0b95abaf2
DIFF: 
https://github.com/llvm/llvm-project/commit/ae5052d2500626b3fc29d7a4778ccef0b95abaf2.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

  This patch implements store, load, move from and to registers related
builtins. The patch aims to provide feature parady with xlC on AIX.

Differential Revision: https://reviews.llvm.org/D105946

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..b311c52235a2a 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -57,8 +57,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -71,6 +74,10 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..1b43680799bf8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -116,8 +116,11 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -130,6 +133,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..fc2fb6a2f454f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15464,6 +15464,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 return Builder.CreateExtractElement(Unpacked, Index);
   }
 
+  case PPC::BI__builtin_ppc_sthcx: {
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx);
+Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty);
+return Builder.CreateCall(F, Ops);
+  }
+
   // The PPC MMA builtins take a pointer to a __vector_quad as an argument.
   // Some of the MMA instructions accumulate their result into an existing
   // accumulator whereas the others generate a new accumulator. So we need to

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e5..6

[llvm-branch-commits] [llvm] 657128f - [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-07-16T04:25:30-05:00
New Revision: 657128f3b76f3960040f043d229a7432fef6e66b

URL: 
https://github.com/llvm/llvm-project/commit/657128f3b76f3960040f043d229a7432fef6e66b
DIFF: 
https://github.com/llvm/llvm-project/commit/657128f3b76f3960040f043d229a7432fef6e66b.diff

LOG: [PowerPC] Store, load, move from and to registers related builtins

This patch implements store, load, move from and to registers related
builtins, as well as builtin for stfiw. The patch aims to provide
feature parady with xlC on AIX.

Differential Revision: https://reviews.llvm.org/D105946

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..482fd52bda439 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -57,8 +57,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -71,6 +74,11 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
+BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..8765bb4d7a2f8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -116,8 +116,12 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
+  Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -130,6 +134,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index baa1436954183..ca96e833c6fb3 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -1012,6 +1012,14 @@ static llvm::Value 
*emitPPCLoadReserveIntrinsic(CodeGenFunction &CGF,
 AsmOS << "lwarx ";
 RetType = CGF.Int32Ty;
 break;
+  case clang::PPC::BI__builtin_ppc_lharx:
+AsmOS << "lharx ";
+RetType = CGF.Int16Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lbarx:
+AsmOS << "lbarx ";
+RetType = CGF.Int8Ty;
+break;
   default:
 llvm_unreachable("Expected only PowerPC load reserve intrinsics");
   }
@

[llvm-branch-commits] [llvm] 719b563 - [PowerPC][Power10] Exploit splat instruction xxsplti32dx in Power10

2021-01-20 Thread Albion Fung via llvm-branch-commits

Author: Albion Fung
Date: 2021-01-20T12:55:52-05:00
New Revision: 719b563ecf6851136e4c1e6a5ff6c407522dd024

URL: 
https://github.com/llvm/llvm-project/commit/719b563ecf6851136e4c1e6a5ff6c407522dd024
DIFF: 
https://github.com/llvm/llvm-project/commit/719b563ecf6851136e4c1e6a5ff6c407522dd024.diff

LOG: [PowerPC][Power10] Exploit splat instruction xxsplti32dx in Power10

Exploits the instruction xxsplti32dx.

It can be used to materialize any 64 bit scalar/vector splat by using two 
instances, one for the upper 32 bits and the other for the lower 32 bits. It 
should not materialize the cases which can be materialized by using the 
instruction xxspltidp.

Differential Revision: https://https://reviews.llvm.org/D90173

Added: 


Modified: 
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
llvm/test/CodeGen/PowerPC/p10-splatImm32.ll

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d6dd70fb1a0c..b37ac7d72dc2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8604,14 +8604,41 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
 
   // If it is a splat of a double, check if we can shrink it to a 32 bit
   // non-denormal float which when converted back to double gives us the same
-  // double. This is to exploit the XXSPLTIDP instruction.
-  if (BVNIsConstantSplat && Subtarget.hasPrefixInstrs() &&
-  (SplatBitSize == 64) && (Op->getValueType(0) == MVT::v2f64) &&
-  convertToNonDenormSingle(APSplatBits)) {
-SDValue SplatNode = DAG.getNode(
-PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64,
-DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32));
-return DAG.getBitcast(Op.getValueType(), SplatNode);
+  // double. This is to exploit the XXSPLTIDP instruction.+  // If we lose 
precision, we use XXSPLTI32DX.
+  if (BVNIsConstantSplat && (SplatBitSize == 64) &&
+  Subtarget.hasPrefixInstrs()) {
+if (convertToNonDenormSingle(APSplatBits) &&
+(Op->getValueType(0) == MVT::v2f64)) {
+  SDValue SplatNode = DAG.getNode(
+  PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64,
+  DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32));
+  return DAG.getBitcast(Op.getValueType(), SplatNode);
+} else { // We may lose precision, so we have to use XXSPLTI32DX.
+
+  uint32_t Hi =
+  (uint32_t)((APSplatBits.getZExtValue() & 0xLL) >> 
32);
+  uint32_t Lo =
+  (uint32_t)(APSplatBits.getZExtValue() & 0x);
+  SDValue SplatNode = DAG.getUNDEF(MVT::v2i64);
+
+  if (!Hi || !Lo)
+// If either load is 0, then we should generate XXLXOR to set to 0.
+SplatNode = DAG.getTargetConstant(0, dl, MVT::v2i64);
+
+  if (Hi)
+SplatNode = DAG.getNode(
+PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode,
+DAG.getTargetConstant(0, dl, MVT::i32),
+DAG.getTargetConstant(Hi, dl, MVT::i32));
+
+  if (Lo)
+SplatNode =
+DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode,
+DAG.getTargetConstant(1, dl, MVT::i32),
+DAG.getTargetConstant(Lo, dl, MVT::i32));
+
+  return DAG.getBitcast(Op.getValueType(), SplatNode);
+}
   }
 
   if (!BVNIsConstantSplat || SplatBitSize > 32) {

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index b6e9562dd0f6..b9eb3b3b7d37 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2533,6 +2533,9 @@ let Predicates = [IsISA3_1] in {
 
   def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
+
+  def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
+ (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {

diff  --git a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll 
b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
index 0cb8fafe7a3c..0836c4cb7bbe 100644
--- a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
@@ -1,114 +1,216 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s 
--check-prefixes=CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
-; RUN: --check-prefix=CHECK-NOPCREL
+

[llvm-branch-commits] [llvm] c289297 - [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_

2020-12-17 Thread Albion Fung via llvm-branch-commits

Author: Baptiste Saleil
Date: 2020-12-17T13:19:27-05:00
New Revision: c2892978e919bf66535729c70fba73c4c3224548

URL: 
https://github.com/llvm/llvm-project/commit/c2892978e919bf66535729c70fba73c4c3224548
DIFF: 
https://github.com/llvm/llvm-project/commit/c2892978e919bf66535729c70fba73c4c3224548.diff

LOG: [PowerPC] Rename the vector pair intrinsics and builtins to replace the 
_mma_ prefix by _vsx_

On PPC, the vector pair instructions are independent from MMA.
This patch renames the vector pair LLVM intrinsics and Clang builtins to 
replace the _mma_ prefix by _vsx_ in their names.
We also move the vector pair type/intrinsic/builtin tests to their own files.

Differential Revision: https://reviews.llvm.org/D91974

Added: 
clang/test/CodeGen/builtins-ppc-pair-mma.c
clang/test/Sema/ppc-pair-mma-types.c
clang/test/SemaCXX/ppc-pair-mma-types.cpp
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll

Removed: 
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/Sema/ppc-mma-types.c
clang/test/SemaCXX/ppc-mma-types.cpp
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll



diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 8975d126b897..39c66f5daeb1 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -7,8 +7,9 @@
 
//===--===//
 //
 // This file defines the PowerPC-specific builtin function database.  Users of
-// this file must define the BUILTIN macro or the MMA_BUILTIN macro to make use
-// of this information.
+// this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to
+// make use of this information. The latter is used for builtins requiring
+// custom code generation and checking.
 //
 
//===--===//
 
@@ -18,9 +19,9 @@
 // The format of this database matches clang/Basic/Builtins.def except for the
 // MMA builtins that are using their own format documented below.
 
-#if defined(BUILTIN) && !defined(MMA_BUILTIN)
-#   define MMA_BUILTIN(ID, TYPES, ACCUMULATE) BUILTIN(__builtin_mma_##ID, 
"i.", "t")
-#elif defined(MMA_BUILTIN) && !defined(BUILTIN)
+#if defined(BUILTIN) && !defined(CUSTOM_BUILTIN)
+#   define CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) BUILTIN(__builtin_##ID, "i.", 
"t")
+#elif defined(CUSTOM_BUILTIN) && !defined(BUILTIN)
 #   define BUILTIN(ID, TYPES, ATTRS)
 #endif
 
@@ -659,94 +660,94 @@ BUILTIN(__builtin_setflm, "dd", "")
 // Cache built-ins
 BUILTIN(__builtin_dcbf, "vvC*", "")
 
-// MMA built-ins
-// All MMA built-ins are declared here using the MMA_BUILTIN macro. Because
-// these built-ins rely on target-dependent types and to avoid pervasive 
change,
-// they are type checked manually in Sema using custom type descriptors.
-// The first argument of the MMA_BUILTIN macro is the name of the built-in, the
-// second argument specifies the type of the function (result value, then each
-// argument) as follows:
+// Built-ins requiring custom code generation.
+// Because these built-ins rely on target-dependent types and to avoid 
pervasive
+// change, they are type checked manually in Sema using custom type 
descriptors.
+// The first argument of the CUSTOM_BUILTIN macro is the name of the built-in
+// with its prefix, the second argument specifies the type of the function
+// (result value, then each argument) as follows:
 //  i -> Unsigned integer followed by the greatest possible value for that
 //   argument or 0 if no constraint on the value.
 //   (e.g. i15 for a 4-bits value)
-//  v -> void
 //  V -> Vector type used with MMA builtins (vector unsigned char)
-//  W -> MMA vector type followed by the size of the vector type.
+//  W -> PPC Vector type followed by the size of the vector type.
 //   (e.g. W512 for __vector_quad)
+//  any other descriptor -> Fall back to generic type descriptor decoding.
 // The 'C' suffix can be used as a suffix to specify the const type.
 // The '*' suffix can be used as a suffix to specify a pointer to a type.
 // The third argument is set to true if the builtin accumulates its result into
 // i

[llvm-branch-commits] [llvm] 8a58f21 - [PowerPC][Power10] Exploit store rightmost vector element instructions

2020-12-22 Thread Albion Fung via llvm-branch-commits

Author: Kamau Bridgeman
Date: 2020-12-22T12:06:43-05:00
New Revision: 8a58f21f5b6c228137a9b87906fe5b720c4d1dfb

URL: 
https://github.com/llvm/llvm-project/commit/8a58f21f5b6c228137a9b87906fe5b720c4d1dfb
DIFF: 
https://github.com/llvm/llvm-project/commit/8a58f21f5b6c228137a9b87906fe5b720c4d1dfb.diff

LOG: [PowerPC][Power10] Exploit store rightmost vector element instructions

Using the store rightmost vector element instructions to do vector
element extraction and store. The rightmost vector element on little
endian is the zeroth vector element, with these patterns that element
can be extracted and stored in one instruction for all vector types.

Differential Revision: https://reviews.llvm.org/D89195

Added: 
llvm/test/CodeGen/PowerPC/store-rightmost-vector-elt.ll

Modified: 
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 54e9adae40d7..e7fa2affb730 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2554,16 +2554,21 @@ let Predicates = [IsISA3_1, HasVSX] in {
 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
 }
 
-let AddedComplexity = 400, Predicates = [IsISA3_1] in {
-  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$rS, 0)), xoaddr:$src),
-(STXVRBX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$rS, 0)), xoaddr:$src),
-(STXVRHX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-  def : Pat<(store (i32 (vector_extract v4i32:$rS, 0)), xoaddr:$src),
-(STXVRWX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-  def : Pat<(store (i64 (vector_extract v2i64:$rS, 0)), xoaddr:$src),
-(STXVRDX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-}
+let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
+  // Store element 0 of a VSX register to memory
+  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), xoaddr:$dst),
+(STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), xoaddr:$dst),
+(STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(store (i32 (extractelt v4i32:$src, 0)), xoaddr:$dst),
+(STXVRWX (COPY_TO_REGCLASS v4i32:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(store (f32 (extractelt v4f32:$src, 0)), xoaddr:$dst),
+(STXVRWX (COPY_TO_REGCLASS v4f32:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(store (i64 (extractelt v2i64:$src, 0)), xoaddr:$dst),
+(STXVRDX (COPY_TO_REGCLASS v2i64:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(store (f64 (extractelt v2f64:$src, 0)), xoaddr:$dst),
+(STXVRDX (COPY_TO_REGCLASS v2f64:$src, VSRC), xoaddr:$dst)>;
+ }
 
 class xxevalPattern  imm> :
   Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}

diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
index 17617e90a01f..9e8f8d073a1a 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -1,13 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s
+; RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s
+; RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s --check-prefix=CHECK-O0
+; RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-O0
 
 ; These test cases aims to test the builtins for the Power10 VSX vector
 ; instructions introduced in ISA 3.1.
@@ -22,14 +22,6 @@ define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> 
%vuca) {
 ; CHECK-NEXT:srwi r3, r3, 31
 ; CHECK-NEXT:extsw r3, r3
 ; CHECK-NEXT:blr
-;
-; CHECK-O0-LABEL: test_vec_test_lsbb_all_ones:
-; CHECK-O0:   # %bb.0: # %entry
-; CHECK-O0-NEXT:xvtlsbb cr0, v2
-; CHECK-O0-NEXT:mfocrf r3, 128
-; CHECK-O0-NEXT:srwi r3, r3, 31
-; CHECK-O0-NEXT:extsw r3, r3
-; CHECK-O0-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 1)
   ret i32 %0
@@ -43,24 +35,22 @@ define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> 
%vuca) {
 ; CHECK-NEXT:rlwinm r3, r3, 3, 31, 31
 ; CHECK-NEXT:extsw r3, r3
 ; CHECK-NEXT:blr
-;
-; CHECK-O0-LABEL: test_