[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
Akshat-Oke wrote: ping https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111634
>From 8e7f36627516a76d76ac7bb1d8c756261b6bbc5c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From bf5cc39e294bd6ff1b3361872e6d76a5e45100a8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 06:22:10 +
Subject: [PATCH 2/2] unrename RegInfo: doesn't belong here
---
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f10a480f7e6160..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-MRI.invalidateLiveness();
+RegInfo.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,7 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
-MRI.noteNewVirtualRegister(Info.VReg);
+RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -721,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-MRI.addLiveIn(Reg, VReg);
+RegInfo.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -734,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-MRI.setCalleeSavedRegs(CalleeSavedRegisters);
+RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
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[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke ready_for_review https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-Oke wrote:
I think Register info is an avenue for noting new virtual registers so I've put
it here https://github.com/llvm/llvm-project/pull/111634
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/7] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 553d5139960f0a26a5d3014fe36179c4ae0cf49d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 2/7] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2c84cdac76d027..b23fea33183354 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1716,6 +1716,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGP
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke created
https://github.com/llvm/llvm-project/pull/111634
None
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
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[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
Akshat-Oke wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111634?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#110229** https://app.graphite.dev/github/pr/llvm/llvm-project/110229?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#111634** https://app.graphite.dev/github/pr/llvm/llvm-project/111634?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#110228** https://app.graphite.dev/github/pr/llvm/llvm-project/110228?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @Akshat-Oke and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111634
>From 8e7f36627516a76d76ac7bb1d8c756261b6bbc5c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From f4a65dea10cd581aada8cbdf33dae5a66518ddcf Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/7] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2c84cdac76d027..b23fea33183354 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1716,6 +1716,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From f9a79de1ee2907baa3673ec504efb687bc4b8576 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/7] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterI
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
optimisan wrote: Also updated in PR. Initializes correct dependency as VirtRegMapWrapper is unused here https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From b337b06e2ecd3d6bbf740ee9ec857463f32d0f1c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f367b5fbea45af 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 2cefaf6d479b6c7ae6bc8a2267f8e4fee274923c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 604653e56782d625ab2444f02e67cda557cdb166 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 31 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 27 insertions(+), 25 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..2ca275cf950564 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s |
FileCheck %s --check-prefix=CHECK2
+# COM: auto-generated updates might remove checks for MachineFunctionInfo
reserved registers.
---
name: pre_allocate_wwm_regs_strict
@@ -9,6 +11,8 @@ body: |
bb.0:
liveins: $sgpr1
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: wwmReservedRegs:
+; CHECK-NEXT: - '$vgpr0'
; CHECK: liveins: $sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IM
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From d4cc049c53df27919103625417730595fc2183d7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index d89a5538b46975..3fee8c40a6607e 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bdc56ca03f392a..4497c1fce0db69 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -122,8 +123,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachineRegionInf
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From af1a1f15867edef93e69c43037a19ab69e8ec2e3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 20 +++
6 files changed, 92 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f367b5fbea45af 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 2cefaf6d479b6c7ae6bc8a2267f8e4fee274923c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 9bddae336227b80ba45be7d7f16ddc4f49fd0a15 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 24 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21
2 files changed, 21 insertions(+), 24 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..74a221084dce24 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2
---
@@ -19,8 +20,25 @@ body: |
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
%0:vgpr_32 = IMPLICIT_DEF
renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
-%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%2:vgpr_32 = V_MOV_B32_dpp %1, %0, 323, 12, 15, 0, implicit $exec
$exec = EXIT_STRICT_
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From dbc51871aab3d4b5d7d64ef78f2df7833359b17f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 9ef4d7c5293076be21240a1e8e696b8e1b58d2ff Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..771a530d8d8c47 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4331a96ab4cbe5939c8ae189140a9ea2f305c950 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/8] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterIn
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
optimisan wrote: ### Merge activity * **Oct 14, 4:57 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/110229). https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
@@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2 + +--- optimisan wrote: Added a comment for the manual check. https://github.com/llvm/llvm-project/pull/109963 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
@@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2 + +--- optimisan wrote: Is it for WWM reserved registers? https://github.com/llvm/llvm-project/pull/109963 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/109937 >From ca685074a7f8bfc75e40dd8172ce9e731e991f4d Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] Update correct dependency Replace unused analysis (VirtRegMap) dependency with the used one (SlotIndexes) --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 671b3c6b33c27374b33eefc4bb20a94aa803f65c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..771a530d8d8c47 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4da5550cabcf293f0beec8aae8c0752d84031cba Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/8] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterIn
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111634
>From ccb60e8277d3beeeffba72349ba0f1ffdb21b0fa Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 9dd11585f667dabc59cbe2b7b0279d42d92d3b77 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 06:22:10 +
Subject: [PATCH 2/2] unrename RegInfo: doesn't belong here
---
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f10a480f7e6160..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-MRI.invalidateLiveness();
+RegInfo.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,7 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
-MRI.noteNewVirtualRegister(Info.VReg);
+RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -721,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-MRI.addLiveIn(Reg, VReg);
+RegInfo.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -734,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-MRI.setCalleeSavedRegs(CalleeSavedRegisters);
+RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 6789308b56f950b89ca1ce822f071e3b499b2924 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..771a530d8d8c47 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 9a575fd028a74e57c858cb90d89f857829da97c8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/8] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterIn
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111634
>From 4d77407b08def09e2ff8e5b87bbce46630271e50 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 9390926f0379ff4d4311c8ce797178677927601a Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 06:22:10 +
Subject: [PATCH 2/2] unrename RegInfo: doesn't belong here
---
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f10a480f7e6160..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-MRI.invalidateLiveness();
+RegInfo.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,7 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
-MRI.noteNewVirtualRegister(Info.VReg);
+RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -721,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-MRI.addLiveIn(Reg, VReg);
+RegInfo.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -734,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-MRI.setCalleeSavedRegs(CalleeSavedRegisters);
+RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-Oke wrote:
It doesn't take effect here.
Might be better to move it to a separate commit.
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
Akshat-Oke wrote:
Should I change this to a const char* instead?
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 1cbc26fe2de38ae4e174aec128b39c899dab9136 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/5] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f2148c2922de9..28578a875c164c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1712,6 +1712,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 669f98dd865d61..e28c24bf8f8500 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -693,8 +693,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 9e1c4941dba283..84569b3f11df67 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 409e5418abc8ec..2c3707e119178a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -454,6 +454,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4c26b4f3b1ad8952767625ba949eaa750aec0652 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/5] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterI
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
Akshat-Oke wrote:
Alright, will keep this.
I have to keep the explicit construct since "WWM_REG" is being refused to be
casted to a SmallString (without creating a StringRef explicitly)
https://github.com/llvm/llvm-project/pull/110229
___
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
Akshat-Oke wrote:
Got it
https://github.com/llvm/llvm-project/pull/110229
___
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[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
Akshat-Oke wrote:
One for the `make_unique` in `MFAM.getResult` and another in internals -
`AnalysisPassModel` constructor.
https://github.com/llvm/llvm-project/pull/109938
___
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[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/109938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109939
>From 786fb970b7b1d12a6c6c6888d2b5cfe51363287d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 20 +++
6 files changed, 92 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f2148c2922de9..dc5330740f4a6b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -506,7 +507,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1505,7 +1506,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1537,7 +1538,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/109938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109963
>From 58fd5012dabc79c87b2b69a2a4d32d655215f144 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 8da3a2c25229b43a0710211d9763733e42bf15d3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 23 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 20 insertions(+), 24 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..4dcad87a985c0b 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2
---
@@ -19,8 +20,24 @@ body: |
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
%0:vgpr_32 = IMPLICIT_DEF
renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
-%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%2:vgpr_32 = V_MOV_B32_dpp %1, %0, 323, 12, 15, 0, implicit $exec
$exec = EXIT_STRIC
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/111357 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/Akshat-Oke ready_for_review https://github.com/llvm/llvm-project/pull/111357 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109938
>From 15692bd09ad90b2bedb7383a9acdb2b3b12453c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH 1/5] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
>From 3cf8e938b76984c86ede00cc85b8b2aa9d84b0fe Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 2/5] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index d89a5538b46975..3fee8c40a6607e 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
voi
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
Akshat-Oke wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111357?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#111357** https://app.graphite.dev/github/pr/llvm/llvm-project/111357?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#109937** https://app.graphite.dev/github/pr/llvm/llvm-project/109937?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 1 other dependent PR ([#109938](https://github.com/llvm/llvm-project/pull/109938) https://app.graphite.dev/github/pr/llvm/llvm-project/109938?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * **#109936** https://app.graphite.dev/github/pr/llvm/llvm-project/109936?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @Akshat-Oke and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/111357 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/Akshat-Oke created
https://github.com/llvm/llvm-project/pull/111357
None
>From 15692bd09ad90b2bedb7383a9acdb2b3b12453c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
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[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/Akshat-Oke updated https://github.com/llvm/llvm-project/pull/109937 >From 7b68d9fb711d73319d97abb2c03dac31956f1fa5 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] Update correct dependency --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -0,0 +1,16 @@ +# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s Akshat-Oke wrote: Negative test is now in MIR/Generic. https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-Oke wrote:
The MIR function is parsed after parsing the options, so the
`noteNewVirtualRegister` callback doesn't take effect.
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency initialization (PR #109937)
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/109937 >From dee5a2949f9b9a3bafef4062bc3c87524cfa73a3 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency Replace the unused analysis (VirtRegMap) dependency with the used one (SlotIndexes). This initializes `SlotIndexesWrapperPass` which is used by SILowerSGPRSpills to ensure that legacy pass manager finds it. Removes the initialization for `VirtRegMapWrapperLegacy` pass since it is not requested in this pass. --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From 709adf06299bd730628800ee45ee782faf76c1fe Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
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[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From 82eae1421ad7c883b9e6e7696357ff22ba6cad90 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 4d94faf5facf81..d93ec34a703d3d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index fbb04f404b4881..4c0500e9f06703 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency initialization (PR #109937)
optimisan wrote: I think this describes it better? https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From 679194b945345f0492a540254af5818be2b372fc Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 5 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 89 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index d2d5465637..d318b7955f8623 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index d92fd19a1882c5..c2a0328d242d13 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -121,8 +122,8 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachinePostDomin
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From de0c637b3ba6d431e6b491b1eee52c3f0488333c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 2ff11f51815928d817058dfb93ed2d96e6b882bc Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 31 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 27 insertions(+), 25 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..2ca275cf950564 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s |
FileCheck %s --check-prefix=CHECK2
+# COM: auto-generated updates might remove checks for MachineFunctionInfo
reserved registers.
---
name: pre_allocate_wwm_regs_strict
@@ -9,6 +11,8 @@ body: |
bb.0:
liveins: $sgpr1
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: wwmReservedRegs:
+; CHECK-NEXT: - '$vgpr0'
; CHECK: liveins: $sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IM
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109939
>From 839e0c12abe69f277810ff04be823c4fa07e4af3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 20 +++
6 files changed, 92 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f2148c2922de9..dc5330740f4a6b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -506,7 +507,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1505,7 +1506,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1537,7 +1538,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/Akshat-Oke updated https://github.com/llvm/llvm-project/pull/109937 >From a1925ae960ca3c8637ebb9a7bf7085dc787ee438 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] Update correct dependency Replace unused analysis dependency with the used one (SlotIndexes) --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109938
>From 60e7f83fe680b04e3cb7c8e2e7bb2383fa0fdded Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index d89a5538b46975..3fee8c40a6607e 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bdc56ca03f392a..4497c1fce0db69 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -122,8 +123,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachineRegionIn
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109963
>From 241cefb63e69298c0122b3aa7dcf2bcde7426c06 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 131cedbef983bf5142286d648009170478560f8e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 23 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 20 insertions(+), 24 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..4dcad87a985c0b 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2
---
@@ -19,8 +20,24 @@ body: |
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
%0:vgpr_32 = IMPLICIT_DEF
renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
-%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%2:vgpr_32 = V_MOV_B32_dpp %1, %0, 323, 12, 15, 0, implicit $exec
$exec = EXIT_STRIC
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111357
>From 47bb19208ed2de82109eb160ba6177b7f888be26 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -578,3 +578,18 @@ body: | SI_RETURN ... +--- Akshat-Oke wrote: I've put it in the generic test llvm/test/CodeGen/MIR/Generic/register-flag-error.mir https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 1cbc26fe2de38ae4e174aec128b39c899dab9136 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/4] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f2148c2922de9..28578a875c164c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1712,6 +1712,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 669f98dd865d61..e28c24bf8f8500 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -693,8 +693,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 9e1c4941dba283..84569b3f11df67 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 409e5418abc8ec..2c3707e119178a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -454,6 +454,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4c26b4f3b1ad8952767625ba949eaa750aec0652 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/4] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterI
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 80207b7bd00d4b0889918d9a7df627f7c304bd7d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/3] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f2148c2922de9..28578a875c164c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1712,6 +1712,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 669f98dd865d61..e28c24bf8f8500 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -693,8 +693,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 9e1c4941dba283..84569b3f11df67 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 409e5418abc8ec..2c3707e119178a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -454,6 +454,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From bc0ab7806225d8acac2d47a8d9a914698cbd1e05 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/3] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterI
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From c2a3cdc01eb492f341fce3d8580643003579880b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
optimisan wrote: ### Merge activity * **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109938). https://github.com/llvm/llvm-project/pull/109938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
optimisan wrote: ### Merge activity * **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109939). https://github.com/llvm/llvm-project/pull/109939 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Correct pass dependencies for SILowerSGPRSpills (PR #109937)
optimisan wrote: ### Merge activity * **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109937). https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From dcf4acd796468d093be999c2bd7d9b53b102ba61 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 5 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 89 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 537166c393c7f1..e2d1cc06d94e70 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index d92fd19a1882c5..c2a0328d242d13 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -121,8 +122,8 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachinePostDomin
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
@@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2 + +--- optimisan wrote: But we have that already(?) ``` wwmReservedRegs: - '$vgpr0' ``` https://github.com/llvm/llvm-project/pull/109963 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From 38940e946a1331426c99e095d26fe81fd2e34eb9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index d89a5538b46975..3fee8c40a6607e 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bdc56ca03f392a..4497c1fce0db69 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -122,8 +123,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachineRegionInf
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 6cf96bb203bc97862ac38776db14365fc75b451f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 43c0d2c61edc837da2ebe4c6166c14d12f8c64a1 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 31 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 27 insertions(+), 25 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..2ca275cf950564 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s |
FileCheck %s --check-prefix=CHECK2
+# COM: auto-generated updates might remove checks for MachineFunctionInfo
reserved registers.
---
name: pre_allocate_wwm_regs_strict
@@ -9,6 +11,8 @@ body: |
bb.0:
liveins: $sgpr1
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: wwmReservedRegs:
+; CHECK-NEXT: - '$vgpr0'
; CHECK: liveins: $sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IM
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency initialization (PR #109937)
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/109937 >From db91ca05946f4bd1067819f788edc45c360ef9d7 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] [AMDGPU][SILowerSGPRSpills] Correct pass dependency Replace the unused analysis (VirtRegMap) dependency with the used one (SlotIndexes). This initializes `SlotIndexesWrapperPass` which is used by SILowerSGPRSpills to ensure that legacy pass manager finds it. Removes the initialization for `VirtRegMapWrapperLegacy` pass since it is not requested in this pass. --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From 052c8b15b41b091cc5b91b41f5dee07f26ccd055 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From a94c78f1fb0de895fa153fe4948689e4523b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 16e23879cd735c..87a6e6cff6dc1d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency initialization (PR #109937)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Updated the correct pass dependency (PR #109937)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 5f42368e15bdba242c15f9f4493b88f80a8f09b7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
---
.../llvm/CodeGen/RegUsageInfoPropagate.h | 25 +++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp| 75 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AArch64/preserve.ll | 4 +
8 files changed, 86 insertions(+), 26 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
new file mode 100644
index 00..73624015e37d9d
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoPropagate.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+#define LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoPropagationPass
+: public PassInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index c881dcd57006db..a9ab739af33ad8 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -258,7 +258,7 @@ void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
-void initializeRegUsageInfoPropagationPass(PassRegistry &);
+void initializeRegUsageInfoPropagationLegacyPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
void initializeRegionOnlyViewerPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 14fcf9d79fbc23..a64ecd69e55913 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -54,6 +54,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
+#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 36d17b713639c1..099b009a2b3fee 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -156,6 +156,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
+MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -250,7 +251,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 76b74ea4e6fe0b..20d1417193a864 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -114,7 +114,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLega
[llvm-branch-commits] [llvm] [AMDGPU] Correct pass dependencies for SILowerSGPRSpills (PR #109937)
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/109937 >From 2cd5b9b848a13653fe8c42429932f598cd75e763 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] [AMDGPU] Correct pass dependencies for SILowerSGPRSpills Replace the unused analysis (VirtRegMap) dependency with the used one (SlotIndexes). This initializes `SlotIndexesWrapperPass` which is used by SILowerSGPRSpills to ensure that legacy pass manager finds it. Removes the initialization for `VirtRegMapWrapperLegacy` pass since it is not requested in this pass. --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From 79e5246844aed5c91b450f866a8862feb9577fa2 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 4d94faf5facf81..d93ec34a703d3d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index fbb04f404b4881..4c0500e9f06703 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From 79e5246844aed5c91b450f866a8862feb9577fa2 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 4d94faf5facf81..d93ec34a703d3d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index fbb04f404b4881..4c0500e9f06703 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From dcf4acd796468d093be999c2bd7d9b53b102ba61 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 5 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 89 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 537166c393c7f1..e2d1cc06d94e70 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index d92fd19a1882c5..c2a0328d242d13 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -121,8 +122,8 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachinePostDomin
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From b86a822c6eb4c7080eb45cde7a71da76346e19c7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From d2032b2fbe68d9d9cabb70c124a10ed6d0a35122 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 31 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 27 insertions(+), 25 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..2ca275cf950564 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s |
FileCheck %s --check-prefix=CHECK2
+# COM: auto-generated updates might remove checks for MachineFunctionInfo
reserved registers.
---
name: pre_allocate_wwm_regs_strict
@@ -9,6 +11,8 @@ body: |
bb.0:
liveins: $sgpr1
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: wwmReservedRegs:
+; CHECK-NEXT: - '$vgpr0'
; CHECK: liveins: $sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IM
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
optimisan wrote: ### Merge activity * **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109963). https://github.com/llvm/llvm-project/pull/109963 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
optimisan wrote: ### Merge activity * **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/111357). https://github.com/llvm/llvm-project/pull/111357 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From 7394bab5609ec2dc56f1851143d8eebb4a5f5b63 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/3] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
.../llvm/CodeGen/RegUsageInfoCollector.h | 25
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoCollector.cpp| 60 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 5 ++
8 files changed, 76 insertions(+), 22 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
new file mode 100644
index 00..6b88cc4f99089e
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoCollector.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+#define LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoCollectorPass
+: public AnalysisInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index f6f6797ec9f87c..c881dcd57006db 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -257,7 +257,7 @@ void
initializeRegAllocPriorityAdvisorAnalysisPass(PassRegistry &);
void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
-void initializeRegUsageInfoCollectorPass(PassRegistry &);
+void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
void initializeRegUsageInfoPropagationPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index e5de62935a8e48..14fcf9d79fbc23 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -53,6 +53,7 @@
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 183a777a93b9fa..36d17b713639c1 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -155,6 +155,7 @@ MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -249,7 +250,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass)
DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index cf5c35fe81b4c7..76b74ea4e6fe0b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -113,7 +113,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRABasicPass(Registry);
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Reg
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/114010
None
>From f84d99b53730031fef705949a5fd34283e9e9eeb Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
---
.../llvm/CodeGen/RegUsageInfoPropagate.h | 25 ++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp| 76 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AArch64/preserve.ll | 4 +
8 files changed, 88 insertions(+), 25 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
new file mode 100644
index 00..73624015e37d9d
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoPropagate.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+#define LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoPropagationPass
+: public PassInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index c881dcd57006db..a9ab739af33ad8 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -258,7 +258,7 @@ void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
-void initializeRegUsageInfoPropagationPass(PassRegistry &);
+void initializeRegUsageInfoPropagationLegacyPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
void initializeRegionOnlyViewerPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 14fcf9d79fbc23..a64ecd69e55913 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -54,6 +54,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
+#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 36d17b713639c1..099b009a2b3fee 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -156,6 +156,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
+MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -250,7 +251,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 76b74ea4e6fe0b..20d1417193a864 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -114,7 +114,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollecto
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114010?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#114010** https://app.graphite.dev/github/pr/llvm/llvm-project/114010?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#113874** https://app.graphite.dev/github/pr/llvm/llvm-project/113874?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#113873** https://app.graphite.dev/github/pr/llvm/llvm-project/113873?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @optimisan and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/114010 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
@@ -1,5 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \ optimisan wrote: `irtranslator` is just for global isel but it works here to print just the MIR. https://github.com/llvm/llvm-project/pull/113874 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan ready_for_review https://github.com/llvm/llvm-project/pull/114010 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 53067f5276ce2b4ae7a918cf732f5659c35ed81d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH 1/2] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
---
.../llvm/CodeGen/RegUsageInfoPropagate.h | 25 +++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp| 75 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AArch64/preserve.ll | 4 +
8 files changed, 86 insertions(+), 26 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
new file mode 100644
index 00..73624015e37d9d
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoPropagate.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+#define LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoPropagationPass
+: public PassInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 44b7ba830bb329..bc209a4e939415 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -258,7 +258,7 @@ void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
-void initializeRegUsageInfoPropagationPass(PassRegistry &);
+void initializeRegUsageInfoPropagationLegacyPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
void initializeRegionOnlyViewerPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 066cd70ec8b996..9f41cc41a7c926 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -54,6 +54,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
+#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 0ee4794034e98b..6327ab1abd48e9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -157,6 +157,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
+MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -251,7 +252,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index e7e8a121369b75..013a9b3c9c4ffa 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -114,7 +114,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollector
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From a95b69c07c7804d2e2a10b939a178a191643a41c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
.../llvm/CodeGen/RegUsageInfoCollector.h | 25
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoCollector.cpp| 60 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 5 ++
8 files changed, 76 insertions(+), 22 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
new file mode 100644
index 00..6b88cc4f99089e
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoCollector.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+#define LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoCollectorPass
+: public AnalysisInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index edc237f2819818..44b7ba830bb329 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -257,7 +257,7 @@ void
initializeRegAllocPriorityAdvisorAnalysisPass(PassRegistry &);
void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
-void initializeRegUsageInfoCollectorPass(PassRegistry &);
+void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
void initializeRegUsageInfoPropagationPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 8cbc9f71ab26d0..066cd70ec8b996 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -53,6 +53,7 @@
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 7db28cb0092525..0ee4794034e98b 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -156,6 +156,7 @@ MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -250,7 +251,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass)
DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..e7e8a121369b75 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -113,7 +113,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRABasicPass(Registry);
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Reg
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From dcf8feee9c8d410b42fa8bed29a15c14bb7d6d2e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 8
llvm/include/llvm/Target/TargetOptions.h | 8 +++-
llvm/lib/CodeGen/MachineSink.cpp | 5 -
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 ++--
5 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+/// a computation can be folded into the addressing mode of a memory
+/// load/store instruction or replace a copy.
+unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..a3a6b24f9be2d1 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include
#include
#include
@@ -729,7 +730,9 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
+ // EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
-setEnableSinkAndFold(EnableSinkFold);
+TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
i
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
@@ -95,12 +107,29 @@ static const Function *findCalledFunction(const Module &M,
return nullptr;
}
-bool RegUsageInfoPropagation::runOnMachineFunction(MachineFunction &MF) {
- const Module &M = *MF.getFunction().getParent();
+bool RegUsageInfoPropagationLegacy::runOnMachineFunction(MachineFunction &MF) {
PhysicalRegisterUsageInfo *PRUI =
&getAnalysis().getPRUI();
- LLVM_DEBUG(dbgs() << " " << getPassName()
+ RegUsageInfoPropagation RUIP(PRUI);
+ return RUIP.run(MF);
+}
+
+PreservedAnalyses
+RegUsageInfoPropagationPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ Module &MFA = *MF.getFunction().getParent();
+ auto *PRUI = MFAM.getResult(MF)
+ .getCachedResult(MFA);
+ assert(PRUI && "PhysicalRegisterUsageAnalysis not available");
optimisan wrote:
It is an outer analysis so cannot run it from an inner IR,
https://github.com/llvm/llvm-project/pull/114010
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/114010 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From a95b69c07c7804d2e2a10b939a178a191643a41c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
.../llvm/CodeGen/RegUsageInfoCollector.h | 25
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoCollector.cpp| 60 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 5 ++
8 files changed, 76 insertions(+), 22 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
new file mode 100644
index 00..6b88cc4f99089e
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoCollector.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+#define LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoCollectorPass
+: public AnalysisInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index edc237f2819818..44b7ba830bb329 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -257,7 +257,7 @@ void
initializeRegAllocPriorityAdvisorAnalysisPass(PassRegistry &);
void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
-void initializeRegUsageInfoCollectorPass(PassRegistry &);
+void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
void initializeRegUsageInfoPropagationPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 8cbc9f71ab26d0..066cd70ec8b996 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -53,6 +53,7 @@
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 7db28cb0092525..0ee4794034e98b 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -156,6 +156,7 @@ MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -250,7 +251,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass)
DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..e7e8a121369b75 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -113,7 +113,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRABasicPass(Registry);
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Reg
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 9792d73efca78fc55a9d25afb17448c7aeb490c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH 1/3] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
---
.../llvm/CodeGen/RegUsageInfoPropagate.h | 25 +++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp| 75 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AArch64/preserve.ll | 4 +
8 files changed, 86 insertions(+), 26 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
new file mode 100644
index 00..73624015e37d9d
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoPropagate.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+#define LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoPropagationPass
+: public PassInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 44b7ba830bb329..bc209a4e939415 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -258,7 +258,7 @@ void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
-void initializeRegUsageInfoPropagationPass(PassRegistry &);
+void initializeRegUsageInfoPropagationLegacyPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
void initializeRegionOnlyViewerPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 066cd70ec8b996..9f41cc41a7c926 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -54,6 +54,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
+#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 0ee4794034e98b..6327ab1abd48e9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -157,6 +157,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
+MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -251,7 +252,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index e7e8a121369b75..013a9b3c9c4ffa 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -114,7 +114,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollector
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
optimisan wrote: The default value is false, but two targets are setting it to true. Currently MachineSink is added by generic TargetPassConfig. Can add the option to `CGPassBuilderOptions` so targets can set it there instead. https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan closed https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114745
>From e7e38bc2bce6add242f8af0d2a1d942fdecab3ed Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:59:30 +
Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM
---
.../llvm/CodeGen/MachineCycleAnalysis.h | 18 ++
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 3 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/MachineCycleAnalysis.cpp | 34 ++-
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/X86/cycle-info.mir | 2 ++
7 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
index 1888dd053ce65e..f740a9599edf29 100644
--- a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/GenericCycleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineSSAContext.h"
namespace llvm {
@@ -46,6 +47,23 @@ class MachineCycleInfoWrapperPass : public
MachineFunctionPass {
// version.
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
+class MachineCycleAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = MachineCycleInfo;
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class MachineCycleInfoPrinterPass : public
PassInfoMixin {
+ raw_ostream &OS;
+ public:
+explicit MachineCycleInfoPrinterPass(raw_ostream &OS) : OS(OS) {}
+PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager
&MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINECYCLEANALYSIS_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 54c070401ec8a4..b040e7c096d1f5 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -191,7 +191,7 @@ void initializeMachineCFGPrinterPass(PassRegistry &);
void initializeMachineCSELegacyPass(PassRegistry &);
void initializeMachineCombinerPass(PassRegistry &);
void initializeMachineCopyPropagationPass(PassRegistry &);
-void initializeMachineCycleInfoPrinterPassPass(PassRegistry &);
+void initializeMachineCycleInfoPrinterLegacyPass(PassRegistry &);
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &);
void initializeMachineDominanceFrontierPass(PassRegistry &);
void initializeMachineDominatorTreeWrapperPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9d12a120ff7ac6..bfe8caba0ce0b3 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -101,6 +101,7 @@ MACHINE_FUNCTION_ANALYSIS("live-vars",
LiveVariablesAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-cycles", MachineCycleAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
@@ -151,6 +152,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print",
MachineDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", MachineLoopPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print",
MachineCycleInfoPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
@@ -241,7 +243,6 @@ DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched",
PostRASchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
-DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles",
MachineCycleInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity",
MachineUniformityInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..adddb8daaa0e91 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -78,7 +78,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachineCSELegacyPass(Registry);
initializeMachineCombinerPass(Re
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From 4e815d99d6c214f0780d70224559a5eb7504cdc6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 8
llvm/include/llvm/Target/TargetOptions.h | 8 +++-
llvm/lib/CodeGen/MachineSink.cpp | 5 -
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 ++--
5 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+/// a computation can be folded into the addressing mode of a memory
+/// load/store instruction or replace a copy.
+unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..a3a6b24f9be2d1 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include
#include
#include
@@ -729,7 +730,9 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
+ // EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
-setEnableSinkAndFold(EnableSinkFold);
+TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
i
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/114745
None
>From 431e6371f161d0f85c598c789902976e3fa74162 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:59:30 +
Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM
---
.../llvm/CodeGen/MachineCycleAnalysis.h | 18 ++
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 3 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/MachineCycleAnalysis.cpp | 34 ++-
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/X86/cycle-info.mir | 2 ++
7 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
index 1888dd053ce65ee..f740a9599edf292 100644
--- a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/GenericCycleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineSSAContext.h"
namespace llvm {
@@ -46,6 +47,23 @@ class MachineCycleInfoWrapperPass : public
MachineFunctionPass {
// version.
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
+class MachineCycleAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = MachineCycleInfo;
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class MachineCycleInfoPrinterPass : public
PassInfoMixin {
+ raw_ostream &OS;
+ public:
+explicit MachineCycleInfoPrinterPass(raw_ostream &OS) : OS(OS) {}
+PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager
&MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINECYCLEANALYSIS_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 54c070401ec8a40..b040e7c096d1f51 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -191,7 +191,7 @@ void initializeMachineCFGPrinterPass(PassRegistry &);
void initializeMachineCSELegacyPass(PassRegistry &);
void initializeMachineCombinerPass(PassRegistry &);
void initializeMachineCopyPropagationPass(PassRegistry &);
-void initializeMachineCycleInfoPrinterPassPass(PassRegistry &);
+void initializeMachineCycleInfoPrinterLegacyPass(PassRegistry &);
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &);
void initializeMachineDominanceFrontierPass(PassRegistry &);
void initializeMachineDominatorTreeWrapperPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9d12a120ff7ac6d..497bc97455a1b55 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -101,6 +101,7 @@ MACHINE_FUNCTION_ANALYSIS("live-vars",
LiveVariablesAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-cycles", MachineCycleAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
@@ -151,6 +152,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print",
MachineDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", MachineLoopPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print-machine-cycles",
MachineCycleInfoPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
@@ -241,7 +243,6 @@ DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched",
PostRASchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
-DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles",
MachineCycleInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity",
MachineUniformityInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef6..adddb8daaa0e914 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -78,7 +78,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachineCSELegacyPass(Registry);
ini
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114745?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#114746** https://app.graphite.dev/github/pr/llvm/llvm-project/114746?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#114745** https://app.graphite.dev/github/pr/llvm/llvm-project/114745?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#114027** https://app.graphite.dev/github/pr/llvm/llvm-project/114027?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @optimisan and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/114745 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
