[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for 64 bit divergent values (PR #96934)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/96934?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#96934** https://app.graphite.dev/github/pr/llvm/llvm-project/96934?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ * **#96933** https://app.graphite.dev/github/pr/llvm/llvm-project/96933?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @vikramRH and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for 64 bit divergent values (PR #96934)
https://github.com/vikramRH ready_for_review https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for 64 bit divergent values (PR #96934)
@@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool shouldOptimizeForType(Type *Ty) { vikramRH wrote: Any better suggestions ? https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
@@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool shouldOptimizeForType(Type *Ty) { + switch (Ty->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: +return true; + case Type::IntegerTyID: { +if (Ty->getIntegerBitWidth() == 32 || Ty->getIntegerBitWidth() == 64) + return true; + default: vikramRH wrote: I feel pointers should be handled as a follow up too since I intend this patch to reflect current requirements (changed the title since it was misleading) https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
@@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool shouldOptimizeForType(Type *Ty) { + switch (Ty->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: +return true; + case Type::IntegerTyID: { +if (Ty->getIntegerBitWidth() == 32 || Ty->getIntegerBitWidth() == 64) + return true; + default: vikramRH wrote: Also enabling for half, bfloat etc would require additional legalization support for intrinsics such as update.dpp , set.incactive.lane https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
@@ -178,6 +178,21 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool isOptimizableAtomic(Type *Ty) { + switch (Ty->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: +return true; + case Type::IntegerTyID: { +unsigned size = Ty->getIntegerBitWidth(); vikramRH wrote: done https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
@@ -230,8 +245,7 @@ void AMDGPUAtomicOptimizerImpl::visitAtomicRMWInst(AtomicRMWInst &I) { // value to the atomic calculation. We can only optimize divergent values if // we have DPP available on our subtarget, and the atomic operation is 32 // bits. - if (ValDivergent && - (!ST->hasDPP() || DL->getTypeSizeInBits(I.getType()) != 32)) { + if (ValDivergent && (!ST->hasDPP() || !isOptimizableAtomic(I.getType( { vikramRH wrote: updated https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
@@ -178,6 +178,21 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool isOptimizableAtomic(Type *Ty) { vikramRH wrote: updated, thanks https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
vikramRH wrote: > > [AMDGPU] Enable atomic optimizer for divergent i64 and double values > > Needs some i64 tests added new i64 tests, however I see there currently exists an issue with DPP path where dpp combine partially fuses the mov_dpp pieces causing machine CSE crash. I have proposed https://github.com/llvm/llvm-project/pull/97413 for now. what would be the correct way forward here ? https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)
vikramRH wrote: > > > > [AMDGPU] Enable atomic optimizer for divergent i64 and double values > > > > > > > > > Needs some i64 tests > > > > > > added new i64 tests, however I see there currently exists an issue with DPP > > path where dpp combine partially fuses the mov_dpp pieces causing machine > > CSE crash. I have proposed #97413 for now. what would be the correct way > > forward here ? > > You didn't include a (very necessary) test in #97413, but DPP instructions > shouldn't be candidates for trivial CSE in the first place? sorry about that, just wanted to bring this up first (I will update the PR with a test). The issue is not with DPP instructions themselves but with the REG_SEQUENCE which is generated after fusing the 32 bit pieces. https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 36a8539c86cfd3246e3268289f5797b067bb08e3 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llvm/CodeGen/MachineFunctionAnalysis.h | 5 + llvm/include/llvm/IR/PassManager.h | 16 llvm/include/llvm/Passes/CodeGenPassBuilder.h| 2 +- llvm/lib/CodeGen/MachineFunctionAnalysis.cpp | 6 ++ llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/tools/llc/new-pm/start-stop.ll | 2 +- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index 98a60c987bbe3..1d954cf60c68c 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -46,6 +46,11 @@ class MachineFunctionAnalysis LLVM_ABI Result run(Function &F, FunctionAnalysisManager &FAM); }; +class FreeMachineFunctionPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + } // namespace llvm #endif // LLVM_CODEGEN_MachineFunctionAnalysis diff --git a/llvm/include/llvm/IR/PassManager.h b/llvm/include/llvm/IR/PassManager.h index 4f44ae56eb3c7..ea8226c6e17ba 100644 --- a/llvm/include/llvm/IR/PassManager.h +++ b/llvm/include/llvm/IR/PassManager.h @@ -491,6 +491,22 @@ template class AnalysisManager { /// invalidate them, unless they are preserved by the PreservedAnalyses set. void invalidate(IRUnitT &IR, const PreservedAnalyses &PA); + /// Directly clear a cached analysis for an IR unit. + /// + /// Using invalidate() over this is preferred unless you are really + /// sure you want to *only* clear this analysis without asking if it is + /// invalid. + template void clearAnalysis(IRUnitT &IR) { +AnalysisResultListT &ResultsList = AnalysisResultLists[&IR]; +AnalysisKey *ID = AnalysisT::ID(); + +auto I = +llvm::find_if(ResultsList, [&ID](auto &E) { return E.first == ID; }); +assert(I != ResultsList.end() && "Analysis must be available"); +ResultsList.erase(I); +AnalysisResults.erase({ID, &IR}); + } + private: /// Look up a registered analysis pass. PassConceptT &lookUpPass(AnalysisKey *ID) { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index a8176ebb776cf..b0360f1903c0e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -281,7 +281,7 @@ template class CodeGenPassBuilder { FunctionPassManager FPM; FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM))); - FPM.addPass(InvalidateAnalysisPass()); + FPM.addPass(FreeMachineFunctionPass()); if (this->PB.AddInCGSCCOrder) { MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor( createCGSCCToFunctionPassAdaptor(std::move(FPM; diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp index e7a4d6d61e211..116a919585d70 100644 --- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp +++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp @@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { return Result(std::move(MF)); } + +PreservedAnalyses FreeMachineFunctionPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.clearAnalysis(F); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 9a943155aa19f..caa78b613b901 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -434,6 +434,7 @@ FUNCTION_PASS("extra-vector-passes", FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flatten-cfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 243cb95d24e4e..50fa7ac2a19aa 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-ha
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 4a28f6898a8b3a23a2e2699c22e9f3eb1e0811fa Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index 9967f46e085e4..78dbf62e5798f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -290,6 +290,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From fb8546e6940619373b4c3251f7391dc6d8ed7e15 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 36a8539c86cfd3246e3268289f5797b067bb08e3 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llvm/CodeGen/MachineFunctionAnalysis.h | 5 + llvm/include/llvm/IR/PassManager.h | 16 llvm/include/llvm/Passes/CodeGenPassBuilder.h| 2 +- llvm/lib/CodeGen/MachineFunctionAnalysis.cpp | 6 ++ llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/tools/llc/new-pm/start-stop.ll | 2 +- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index 98a60c987bbe3..1d954cf60c68c 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -46,6 +46,11 @@ class MachineFunctionAnalysis LLVM_ABI Result run(Function &F, FunctionAnalysisManager &FAM); }; +class FreeMachineFunctionPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + } // namespace llvm #endif // LLVM_CODEGEN_MachineFunctionAnalysis diff --git a/llvm/include/llvm/IR/PassManager.h b/llvm/include/llvm/IR/PassManager.h index 4f44ae56eb3c7..ea8226c6e17ba 100644 --- a/llvm/include/llvm/IR/PassManager.h +++ b/llvm/include/llvm/IR/PassManager.h @@ -491,6 +491,22 @@ template class AnalysisManager { /// invalidate them, unless they are preserved by the PreservedAnalyses set. void invalidate(IRUnitT &IR, const PreservedAnalyses &PA); + /// Directly clear a cached analysis for an IR unit. + /// + /// Using invalidate() over this is preferred unless you are really + /// sure you want to *only* clear this analysis without asking if it is + /// invalid. + template void clearAnalysis(IRUnitT &IR) { +AnalysisResultListT &ResultsList = AnalysisResultLists[&IR]; +AnalysisKey *ID = AnalysisT::ID(); + +auto I = +llvm::find_if(ResultsList, [&ID](auto &E) { return E.first == ID; }); +assert(I != ResultsList.end() && "Analysis must be available"); +ResultsList.erase(I); +AnalysisResults.erase({ID, &IR}); + } + private: /// Look up a registered analysis pass. PassConceptT &lookUpPass(AnalysisKey *ID) { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index a8176ebb776cf..b0360f1903c0e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -281,7 +281,7 @@ template class CodeGenPassBuilder { FunctionPassManager FPM; FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM))); - FPM.addPass(InvalidateAnalysisPass()); + FPM.addPass(FreeMachineFunctionPass()); if (this->PB.AddInCGSCCOrder) { MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor( createCGSCCToFunctionPassAdaptor(std::move(FPM; diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp index e7a4d6d61e211..116a919585d70 100644 --- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp +++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp @@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { return Result(std::move(MF)); } + +PreservedAnalyses FreeMachineFunctionPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.clearAnalysis(F); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 9a943155aa19f..caa78b613b901 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -434,6 +434,7 @@ FUNCTION_PASS("extra-vector-passes", FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flatten-cfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 243cb95d24e4e..50fa7ac2a19aa 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-ha
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From fb8546e6940619373b4c3251f7391dc6d8ed7e15 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 4a28f6898a8b3a23a2e2699c22e9f3eb1e0811fa Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index 9967f46e085e4..78dbf62e5798f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -290,6 +290,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio
[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148111 >From 245b1cd1df9bb2cae6d36428d30c4578fea0fd8b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:24:23 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Account inserted passes for -start/stop options --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 -- llvm/test/tools/llc/new-pm/start-stop-inserted.ll | 15 +++ 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 llvm/test/tools/llc/new-pm/start-stop-inserted.ll diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index dc5f3f80f547e..44024a4c0a8da 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -579,8 +579,10 @@ template class CodeGenPassBuilder { void insertPass(InsertedPassT &&Pass) const { AfterCallbacks.emplace_back( [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { - if (Name == TargetPassT::name()) -MFPM.addPass(std::forward(Pass)); + if (Name == TargetPassT::name()) { +if (runBeforeAdding(InsertedPassT::name())) + MFPM.addPass(std::forward(Pass)); + } }); } diff --git a/llvm/test/tools/llc/new-pm/start-stop-inserted.ll b/llvm/test/tools/llc/new-pm/start-stop-inserted.ll new file mode 100644 index 0..ce5ad2d9e5065 --- /dev/null +++ b/llvm/test/tools/llc/new-pm/start-stop-inserted.ll @@ -0,0 +1,15 @@ +; REQUIRES: amdgpu-registered-target + +; AMDGPU inserts the fourth instance of dead-mi-elimination pass after detect-dead-lanes +; This checks that the pipeline stops before that. + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -O3 -enable-new-pm -stop-before=dead-mi-elimination,4 --print-pipeline-passes -filetype=null %s | FileCheck %s + +; There is no way to -start-after an inserted pass right now. +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -O3 -enable-new-pm -start-after=dead-mi-elimination,4 --print-pipeline-passes -filetype=null %s + + +; CHECK: dead-mi-elimination +; CHECK: dead-mi-elimination +; CHECK: dead-mi-elimination +; CHECK-NOT: dead-mi-elimination >From 1eef1b97c806394f529faab4794fb14ddcddc3ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Mon, 14 Jul 2025 11:38:59 +0530 Subject: [PATCH 2/2] review comment --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 44024a4c0a8da..a8176ebb776cf 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -579,9 +579,9 @@ template class CodeGenPassBuilder { void insertPass(InsertedPassT &&Pass) const { AfterCallbacks.emplace_back( [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { - if (Name == TargetPassT::name()) { -if (runBeforeAdding(InsertedPassT::name())) - MFPM.addPass(std::forward(Pass)); + if (Name == TargetPassT::name() && + runBeforeAdding(InsertedPassT::name())) { +MFPM.addPass(std::forward(Pass)); } }); } ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 6b203cd5f6d6786dc2ddf8c5fb0e20b004c80c9b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llvm/CodeGen/MachineFunctionAnalysis.h | 5 + llvm/include/llvm/IR/PassManager.h | 16 llvm/include/llvm/Passes/CodeGenPassBuilder.h| 2 +- llvm/lib/CodeGen/MachineFunctionAnalysis.cpp | 6 ++ llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/tools/llc/new-pm/start-stop.ll | 2 +- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index 98a60c987bbe3..1d954cf60c68c 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -46,6 +46,11 @@ class MachineFunctionAnalysis LLVM_ABI Result run(Function &F, FunctionAnalysisManager &FAM); }; +class FreeMachineFunctionPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + } // namespace llvm #endif // LLVM_CODEGEN_MachineFunctionAnalysis diff --git a/llvm/include/llvm/IR/PassManager.h b/llvm/include/llvm/IR/PassManager.h index 4f44ae56eb3c7..ea8226c6e17ba 100644 --- a/llvm/include/llvm/IR/PassManager.h +++ b/llvm/include/llvm/IR/PassManager.h @@ -491,6 +491,22 @@ template class AnalysisManager { /// invalidate them, unless they are preserved by the PreservedAnalyses set. void invalidate(IRUnitT &IR, const PreservedAnalyses &PA); + /// Directly clear a cached analysis for an IR unit. + /// + /// Using invalidate() over this is preferred unless you are really + /// sure you want to *only* clear this analysis without asking if it is + /// invalid. + template void clearAnalysis(IRUnitT &IR) { +AnalysisResultListT &ResultsList = AnalysisResultLists[&IR]; +AnalysisKey *ID = AnalysisT::ID(); + +auto I = +llvm::find_if(ResultsList, [&ID](auto &E) { return E.first == ID; }); +assert(I != ResultsList.end() && "Analysis must be available"); +ResultsList.erase(I); +AnalysisResults.erase({ID, &IR}); + } + private: /// Look up a registered analysis pass. PassConceptT &lookUpPass(AnalysisKey *ID) { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index a8176ebb776cf..b0360f1903c0e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -281,7 +281,7 @@ template class CodeGenPassBuilder { FunctionPassManager FPM; FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM))); - FPM.addPass(InvalidateAnalysisPass()); + FPM.addPass(FreeMachineFunctionPass()); if (this->PB.AddInCGSCCOrder) { MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor( createCGSCCToFunctionPassAdaptor(std::move(FPM; diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp index e7a4d6d61e211..116a919585d70 100644 --- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp +++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp @@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { return Result(std::move(MF)); } + +PreservedAnalyses FreeMachineFunctionPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.clearAnalysis(F); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 9a943155aa19f..caa78b613b901 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -434,6 +434,7 @@ FUNCTION_PASS("extra-vector-passes", FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flatten-cfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 243cb95d24e4e..50fa7ac2a19aa 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-ha
[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148109 >From 24e03050c25d4c480e8e4540452495a908aca29b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:03:19 +0530 Subject: [PATCH] [CodeGen][NPM] Register Function Passes --- .../llvm/Passes/MachinePassRegistry.def | 35 --- llvm/lib/Passes/PassBuilder.cpp | 2 ++ llvm/lib/Passes/PassRegistry.def | 3 ++ llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 ++-- 4 files changed, 8 insertions(+), 38 deletions(-) diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index b6c1460313f86..245ea60fd146a 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -42,41 +42,6 @@ FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis()) FUNCTION_ANALYSIS("target-ir", TargetIRAnalysis(std::move(TM.getTargetIRAnalysis( #undef FUNCTION_ANALYSIS -#ifndef FUNCTION_PASS -#define FUNCTION_PASS(NAME, CREATE_PASS) -#endif -FUNCTION_PASS("callbr-prepare", CallBrPreparePass()) -FUNCTION_PASS("cfguard", CFGuardPass()) -FUNCTION_PASS("codegenprepare", CodeGenPreparePass(TM)) -FUNCTION_PASS("consthoist", ConstantHoistingPass()) -FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) -FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass(false)) -FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) -FUNCTION_PASS("expand-fp", ExpandFpPass(TM)) -FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) -FUNCTION_PASS("expand-reductions", ExpandReductionsPass()) -FUNCTION_PASS("gc-lowering", GCLoweringPass()) -FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass(TM)) -FUNCTION_PASS("interleaved-access", InterleavedAccessPass(TM)) -FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass(TM)) -FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass()) -FUNCTION_PASS("lower-invoke", LowerInvokePass()) -FUNCTION_PASS("mergeicmps", MergeICmpsPass()) -FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass()) -FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass(true)) -FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib()) -FUNCTION_PASS("safe-stack", SafeStackPass(TM)) -FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass()) -FUNCTION_PASS("select-optimize", SelectOptimizePass(TM)) -FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM)) -FUNCTION_PASS("stack-protector", StackProtectorPass(TM)) -FUNCTION_PASS("tlshoist", TLSVariableHoistPass()) -FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass()) -FUNCTION_PASS("verify", VerifierPass()) -FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass()) -FUNCTION_PASS("win-eh-prepare", WinEHPreparePass()) -#undef FUNCTION_PASS - #ifndef LOOP_PASS #define LOOP_PASS(NAME, CREATE_PASS) #endif diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 572e5f19a1972..75a8c8df0eff9 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -94,6 +94,7 @@ #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandPostRAPseudos.h" +#include "llvm/CodeGen/ExpandReductions.h" #include "llvm/CodeGen/FEntryInserter.h" #include "llvm/CodeGen/FinalizeISel.h" #include "llvm/CodeGen/FixupStatepointCallerSaved.h" @@ -153,6 +154,7 @@ #include "llvm/CodeGen/RemoveLoadsIntoFakeUses.h" #include "llvm/CodeGen/RemoveRedundantDebugValues.h" #include "llvm/CodeGen/RenameIndependentSubregs.h" +#include "llvm/CodeGen/ReplaceWithVeclib.h" #include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/SanitizerBinaryMetadata.h" #include "llvm/CodeGen/SelectOptimize.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 96250772da4a0..9a943155aa19f 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -428,6 +428,7 @@ FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) FUNCTION_PASS("expand-fp", ExpandFpPass(TM)) FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) +FUNCTION_PASS("expand-reductions", ExpandReductionsPass()) FUNCTION_PASS("extra-vector-passes", ExtraFunctionPassManager()) FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) @@ -520,6 +521,7 @@ FUNCTION_PASS("print", StackSafetyPrinterPass(errs())) FUNCTION_PASS("print", UniformityInfoPrinterPass(errs())) FUNCTION_PASS("reassociate", ReassociatePass()) FUNCTION_PASS("redundant-dbg-inst-elim", RedundantDbgInstEliminationPass()) +FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib()) FUNCTION_PASS("reg2mem", RegToMemPass()) FUNCTION_PASS("safe-stack", SafeStackPass(TM)) FUNCTION_PASS("sandbox-vectorizer", SandboxVectorizerPass()) @@ -541,6 +543,7 @@ FUNCTION_PASS("trigger-verifier-error", TriggerV
[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148108 >From 837ec7b0b82b939d87000bf12b7e22705c1c31b7 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:00:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Read TargetMachine's EnableIPRA option --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 4 llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 910e25a048815..977c2a1ae2238 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -173,6 +173,10 @@ template class CodeGenPassBuilder { // LLVMTM ctor. See TargetMachine::setGlobalISel for example. if (Opt.EnableIPRA) TM.Options.EnableIPRA = *Opt.EnableIPRA; +else { + // If not explicitly specified, use target default. + TM.Options.EnableIPRA |= TM.useIPRA(); +} if (Opt.EnableGlobalISelAbort) TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort; diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 2913fe001621d..ba76dc9c9ee5c 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,UnreachableBlockElimPass,ee-instrument,scalarize-masked-mem-intrin,ExpandReductionsPass,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,UnreachableBlockElimPass,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) +; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,UnreachableBlockElimPass,ee-instrument,scalarize-masked-mem-intrin,ExpandReductionsPass,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,UnreachableBlockElimPass,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,reg-usage-collector,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) -; GCN-O2: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,function(amdgpu-image-intrinsic-opt),expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(amdgpu-atomic-optimizer,atomic-expand,amdgpu-promote-alloca,separate-const-offset-from-gep<>,slsr,early-cse<>,nary-reassociate,early-cse<>,amdgpu-codegenprepare,verify,loop-mssa(loop-reduce),mergeicmps,expand-memcmp,gc-lowering,lower-constant-intrinsics,UnreachableBlockElimPass,consthoist,Re
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From fdd06a88e3a53f98fe3eaba9d70e1cf8913e Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f4dc4a483181c..31a80e00edd3b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2284,6 +2284,12 @@ void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const { Base::addPostRegAlloc(addPass); } +void AMDGPUCodeGenPassBuilder::addPreSched2(AddMachinePass &addPass) const { + if (TM.getOptLevel() > CodeGenOptLevel::None) +addPass(SIShrinkInstructionsPass()); + addPass(SIPostRABundlerPass()); +} + void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less)) { addPass(GCNCreateVOPDPass()); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 3c62cd19c6e57..3b2f39c14a9bc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -183,6 +183,7 @@ class AMDGPUCodeGenPassBuilder void addPreEmitPass(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; void addOptimizedRegAlloc(AddMachinePass &) const; + void addPreSched2(AddMachinePass &) const; /// Check if a pass is enabled given \p Opt option. The option always /// overrides defaults if explicitly used. Otherwise its default will be used diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 25d102847ab04..243cb95d24e4e 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,reg-usage-collector,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) +; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,si-post-ra-bundler,fentry-insert,xray-instrumentation,patchable-function,si-memory-legaliz
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 3fc8b6ea10eb633a208cedbe21656d3fe95698ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 3fc8b6ea10eb633a208cedbe21656d3fe95698ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From fdd06a88e3a53f98fe3eaba9d70e1cf8913e Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f4dc4a483181c..31a80e00edd3b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2284,6 +2284,12 @@ void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const { Base::addPostRegAlloc(addPass); } +void AMDGPUCodeGenPassBuilder::addPreSched2(AddMachinePass &addPass) const { + if (TM.getOptLevel() > CodeGenOptLevel::None) +addPass(SIShrinkInstructionsPass()); + addPass(SIPostRABundlerPass()); +} + void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less)) { addPass(GCNCreateVOPDPass()); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 3c62cd19c6e57..3b2f39c14a9bc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -183,6 +183,7 @@ class AMDGPUCodeGenPassBuilder void addPreEmitPass(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; void addOptimizedRegAlloc(AddMachinePass &) const; + void addPreSched2(AddMachinePass &) const; /// Check if a pass is enabled given \p Opt option. The option always /// overrides defaults if explicitly used. Otherwise its default will be used diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 25d102847ab04..243cb95d24e4e 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,reg-usage-collector,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) +; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,si-post-ra-bundler,fentry-insert,xray-instrumentation,patchable-function,si-memory-legaliz
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 6b203cd5f6d6786dc2ddf8c5fb0e20b004c80c9b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llvm/CodeGen/MachineFunctionAnalysis.h | 5 + llvm/include/llvm/IR/PassManager.h | 16 llvm/include/llvm/Passes/CodeGenPassBuilder.h| 2 +- llvm/lib/CodeGen/MachineFunctionAnalysis.cpp | 6 ++ llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/tools/llc/new-pm/start-stop.ll | 2 +- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index 98a60c987bbe3..1d954cf60c68c 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -46,6 +46,11 @@ class MachineFunctionAnalysis LLVM_ABI Result run(Function &F, FunctionAnalysisManager &FAM); }; +class FreeMachineFunctionPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + } // namespace llvm #endif // LLVM_CODEGEN_MachineFunctionAnalysis diff --git a/llvm/include/llvm/IR/PassManager.h b/llvm/include/llvm/IR/PassManager.h index 4f44ae56eb3c7..ea8226c6e17ba 100644 --- a/llvm/include/llvm/IR/PassManager.h +++ b/llvm/include/llvm/IR/PassManager.h @@ -491,6 +491,22 @@ template class AnalysisManager { /// invalidate them, unless they are preserved by the PreservedAnalyses set. void invalidate(IRUnitT &IR, const PreservedAnalyses &PA); + /// Directly clear a cached analysis for an IR unit. + /// + /// Using invalidate() over this is preferred unless you are really + /// sure you want to *only* clear this analysis without asking if it is + /// invalid. + template void clearAnalysis(IRUnitT &IR) { +AnalysisResultListT &ResultsList = AnalysisResultLists[&IR]; +AnalysisKey *ID = AnalysisT::ID(); + +auto I = +llvm::find_if(ResultsList, [&ID](auto &E) { return E.first == ID; }); +assert(I != ResultsList.end() && "Analysis must be available"); +ResultsList.erase(I); +AnalysisResults.erase({ID, &IR}); + } + private: /// Look up a registered analysis pass. PassConceptT &lookUpPass(AnalysisKey *ID) { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index a8176ebb776cf..b0360f1903c0e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -281,7 +281,7 @@ template class CodeGenPassBuilder { FunctionPassManager FPM; FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM))); - FPM.addPass(InvalidateAnalysisPass()); + FPM.addPass(FreeMachineFunctionPass()); if (this->PB.AddInCGSCCOrder) { MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor( createCGSCCToFunctionPassAdaptor(std::move(FPM; diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp index e7a4d6d61e211..116a919585d70 100644 --- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp +++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp @@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { return Result(std::move(MF)); } + +PreservedAnalyses FreeMachineFunctionPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.clearAnalysis(F); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 9a943155aa19f..caa78b613b901 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -434,6 +434,7 @@ FUNCTION_PASS("extra-vector-passes", FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flatten-cfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 243cb95d24e4e..50fa7ac2a19aa 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-ha
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 358f2e2b2aa99ce56ac8d24ff4d88cfa9bcb2327 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index f3b9364fdb92b..db5a1c0ac71aa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio
[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148109 >From 24e03050c25d4c480e8e4540452495a908aca29b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:03:19 +0530 Subject: [PATCH] [CodeGen][NPM] Register Function Passes --- .../llvm/Passes/MachinePassRegistry.def | 35 --- llvm/lib/Passes/PassBuilder.cpp | 2 ++ llvm/lib/Passes/PassRegistry.def | 3 ++ llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 ++-- 4 files changed, 8 insertions(+), 38 deletions(-) diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index b6c1460313f86..245ea60fd146a 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -42,41 +42,6 @@ FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis()) FUNCTION_ANALYSIS("target-ir", TargetIRAnalysis(std::move(TM.getTargetIRAnalysis( #undef FUNCTION_ANALYSIS -#ifndef FUNCTION_PASS -#define FUNCTION_PASS(NAME, CREATE_PASS) -#endif -FUNCTION_PASS("callbr-prepare", CallBrPreparePass()) -FUNCTION_PASS("cfguard", CFGuardPass()) -FUNCTION_PASS("codegenprepare", CodeGenPreparePass(TM)) -FUNCTION_PASS("consthoist", ConstantHoistingPass()) -FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) -FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass(false)) -FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) -FUNCTION_PASS("expand-fp", ExpandFpPass(TM)) -FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) -FUNCTION_PASS("expand-reductions", ExpandReductionsPass()) -FUNCTION_PASS("gc-lowering", GCLoweringPass()) -FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass(TM)) -FUNCTION_PASS("interleaved-access", InterleavedAccessPass(TM)) -FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass(TM)) -FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass()) -FUNCTION_PASS("lower-invoke", LowerInvokePass()) -FUNCTION_PASS("mergeicmps", MergeICmpsPass()) -FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass()) -FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass(true)) -FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib()) -FUNCTION_PASS("safe-stack", SafeStackPass(TM)) -FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass()) -FUNCTION_PASS("select-optimize", SelectOptimizePass(TM)) -FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM)) -FUNCTION_PASS("stack-protector", StackProtectorPass(TM)) -FUNCTION_PASS("tlshoist", TLSVariableHoistPass()) -FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass()) -FUNCTION_PASS("verify", VerifierPass()) -FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass()) -FUNCTION_PASS("win-eh-prepare", WinEHPreparePass()) -#undef FUNCTION_PASS - #ifndef LOOP_PASS #define LOOP_PASS(NAME, CREATE_PASS) #endif diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 572e5f19a1972..75a8c8df0eff9 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -94,6 +94,7 @@ #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandPostRAPseudos.h" +#include "llvm/CodeGen/ExpandReductions.h" #include "llvm/CodeGen/FEntryInserter.h" #include "llvm/CodeGen/FinalizeISel.h" #include "llvm/CodeGen/FixupStatepointCallerSaved.h" @@ -153,6 +154,7 @@ #include "llvm/CodeGen/RemoveLoadsIntoFakeUses.h" #include "llvm/CodeGen/RemoveRedundantDebugValues.h" #include "llvm/CodeGen/RenameIndependentSubregs.h" +#include "llvm/CodeGen/ReplaceWithVeclib.h" #include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/SanitizerBinaryMetadata.h" #include "llvm/CodeGen/SelectOptimize.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 96250772da4a0..9a943155aa19f 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -428,6 +428,7 @@ FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) FUNCTION_PASS("expand-fp", ExpandFpPass(TM)) FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) +FUNCTION_PASS("expand-reductions", ExpandReductionsPass()) FUNCTION_PASS("extra-vector-passes", ExtraFunctionPassManager()) FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) @@ -520,6 +521,7 @@ FUNCTION_PASS("print", StackSafetyPrinterPass(errs())) FUNCTION_PASS("print", UniformityInfoPrinterPass(errs())) FUNCTION_PASS("reassociate", ReassociatePass()) FUNCTION_PASS("redundant-dbg-inst-elim", RedundantDbgInstEliminationPass()) +FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib()) FUNCTION_PASS("reg2mem", RegToMemPass()) FUNCTION_PASS("safe-stack", SafeStackPass(TM)) FUNCTION_PASS("sandbox-vectorizer", SandboxVectorizerPass()) @@ -541,6 +543,7 @@ FUNCTION_PASS("trigger-verifier-error", TriggerV
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 358f2e2b2aa99ce56ac8d24ff4d88cfa9bcb2327 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index f3b9364fdb92b..db5a1c0ac71aa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio
[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148108 >From 837ec7b0b82b939d87000bf12b7e22705c1c31b7 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:00:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Read TargetMachine's EnableIPRA option --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 4 llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 910e25a048815..977c2a1ae2238 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -173,6 +173,10 @@ template class CodeGenPassBuilder { // LLVMTM ctor. See TargetMachine::setGlobalISel for example. if (Opt.EnableIPRA) TM.Options.EnableIPRA = *Opt.EnableIPRA; +else { + // If not explicitly specified, use target default. + TM.Options.EnableIPRA |= TM.useIPRA(); +} if (Opt.EnableGlobalISelAbort) TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort; diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 2913fe001621d..ba76dc9c9ee5c 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,UnreachableBlockElimPass,ee-instrument,scalarize-masked-mem-intrin,ExpandReductionsPass,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,UnreachableBlockElimPass,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) +; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,UnreachableBlockElimPass,ee-instrument,scalarize-masked-mem-intrin,ExpandReductionsPass,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,UnreachableBlockElimPass,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,reg-usage-collector,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) -; GCN-O2: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,function(amdgpu-image-intrinsic-opt),expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(amdgpu-atomic-optimizer,atomic-expand,amdgpu-promote-alloca,separate-const-offset-from-gep<>,slsr,early-cse<>,nary-reassociate,early-cse<>,amdgpu-codegenprepare,verify,loop-mssa(loop-reduce),mergeicmps,expand-memcmp,gc-lowering,lower-constant-intrinsics,UnreachableBlockElimPass,consthoist,Re
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 7d8f2ba9d3aa392c09f20a844ca5ea5cb97519cf Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 17afb0ff6329cb1cf676c5add1c1a3818ce96e11 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index f3b9364fdb92b..db5a1c0ac71aa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio
[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148110 >From 9563564e96325df0ce2f36701c65a7f95597cc47 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:15:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Port ProcessImplicitDefs to NPM --- .../llvm/CodeGen/ProcessImplicitDefs.h| 28 + llvm/include/llvm/InitializePasses.h | 2 +- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 + .../llvm/Passes/MachinePassRegistry.def | 2 +- llvm/lib/CodeGen/CodeGen.cpp | 2 +- llvm/lib/CodeGen/ProcessImplicitDefs.cpp | 57 +-- llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 +- .../CodeGen/X86/unreachable-mbb-undef-phi.mir | 1 + 9 files changed, 75 insertions(+), 23 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/ProcessImplicitDefs.h diff --git a/llvm/include/llvm/CodeGen/ProcessImplicitDefs.h b/llvm/include/llvm/CodeGen/ProcessImplicitDefs.h new file mode 100644 index 0..806f68adfded7 --- /dev/null +++ b/llvm/include/llvm/CodeGen/ProcessImplicitDefs.h @@ -0,0 +1,28 @@ +//===- llvm/CodeGen/ProcessImplicitDefs.h ---*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// + +#ifndef LLVM_CODEGEN_PROCESSIMPLICITDEFS_H +#define LLVM_CODEGEN_PROCESSIMPLICITDEFS_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +class ProcessImplicitDefsPass : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, +MachineFunctionAnalysisManager &MFAM); + MachineFunctionProperties getRequiredProperties() const { +return MachineFunctionProperties().set( +MachineFunctionProperties::Property::IsSSA); + } +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_PROCESSIMPLICITDEFS_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index c847716647825..2e231cfba2443 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -257,7 +257,7 @@ LLVM_ABI void initializePostRASchedulerLegacyPass(PassRegistry &); LLVM_ABI void initializePreISelIntrinsicLoweringLegacyPassPass(PassRegistry &); LLVM_ABI void initializePrintFunctionPassWrapperPass(PassRegistry &); LLVM_ABI void initializePrintModulePassWrapperPass(PassRegistry &); -LLVM_ABI void initializeProcessImplicitDefsPass(PassRegistry &); +LLVM_ABI void initializeProcessImplicitDefsLegacyPass(PassRegistry &); LLVM_ABI void initializeProfileSummaryInfoWrapperPassPass(PassRegistry &); LLVM_ABI void initializePromoteLegacyPassPass(PassRegistry &); LLVM_ABI void initializeRABasicPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index bf964fa1fa76d..dc5f3f80f547e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -72,6 +72,7 @@ #include "llvm/CodeGen/PostRAMachineSink.h" #include "llvm/CodeGen/PostRASchedulerList.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" +#include "llvm/CodeGen/ProcessImplicitDefs.h" #include "llvm/CodeGen/RegAllocEvictionAdvisor.h" #include "llvm/CodeGen/RegAllocFast.h" #include "llvm/CodeGen/RegAllocGreedyPass.h" diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 245ea60fd146a..732fdc7c9bc1f 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -152,6 +152,7 @@ MACHINE_FUNCTION_PASS("print", MachineUniformityPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(errs())) +MACHINE_FUNCTION_PASS("process-imp-defs", ProcessImplicitDefsPass()) MACHINE_FUNCTION_PASS("prolog-epilog", PrologEpilogInserterPass()) MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass()) MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass()) @@ -283,7 +284,6 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter) DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass) DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass) DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass) -DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass) DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass) DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass) DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass) diff --git a
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 17afb0ff6329cb1cf676c5add1c1a3818ce96e11 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index f3b9364fdb92b..db5a1c0ac71aa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 3035640f0f6f0ff104b3f69000f42d9d5f07f053 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llvm/CodeGen/MachineFunctionAnalysis.h | 5 + llvm/include/llvm/IR/PassManager.h | 16 llvm/include/llvm/Passes/CodeGenPassBuilder.h| 2 +- llvm/lib/CodeGen/MachineFunctionAnalysis.cpp | 6 ++ llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/tools/llc/new-pm/start-stop.ll | 2 +- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index 98a60c987bbe3..1d954cf60c68c 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -46,6 +46,11 @@ class MachineFunctionAnalysis LLVM_ABI Result run(Function &F, FunctionAnalysisManager &FAM); }; +class FreeMachineFunctionPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + } // namespace llvm #endif // LLVM_CODEGEN_MachineFunctionAnalysis diff --git a/llvm/include/llvm/IR/PassManager.h b/llvm/include/llvm/IR/PassManager.h index 4f44ae56eb3c7..ea8226c6e17ba 100644 --- a/llvm/include/llvm/IR/PassManager.h +++ b/llvm/include/llvm/IR/PassManager.h @@ -491,6 +491,22 @@ template class AnalysisManager { /// invalidate them, unless they are preserved by the PreservedAnalyses set. void invalidate(IRUnitT &IR, const PreservedAnalyses &PA); + /// Directly clear a cached analysis for an IR unit. + /// + /// Using invalidate() over this is preferred unless you are really + /// sure you want to *only* clear this analysis without asking if it is + /// invalid. + template void clearAnalysis(IRUnitT &IR) { +AnalysisResultListT &ResultsList = AnalysisResultLists[&IR]; +AnalysisKey *ID = AnalysisT::ID(); + +auto I = +llvm::find_if(ResultsList, [&ID](auto &E) { return E.first == ID; }); +assert(I != ResultsList.end() && "Analysis must be available"); +ResultsList.erase(I); +AnalysisResults.erase({ID, &IR}); + } + private: /// Look up a registered analysis pass. PassConceptT &lookUpPass(AnalysisKey *ID) { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index a8176ebb776cf..b0360f1903c0e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -281,7 +281,7 @@ template class CodeGenPassBuilder { FunctionPassManager FPM; FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM))); - FPM.addPass(InvalidateAnalysisPass()); + FPM.addPass(FreeMachineFunctionPass()); if (this->PB.AddInCGSCCOrder) { MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor( createCGSCCToFunctionPassAdaptor(std::move(FPM; diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp index e7a4d6d61e211..116a919585d70 100644 --- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp +++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp @@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { return Result(std::move(MF)); } + +PreservedAnalyses FreeMachineFunctionPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.clearAnalysis(F); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 9a943155aa19f..caa78b613b901 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -434,6 +434,7 @@ FUNCTION_PASS("extra-vector-passes", FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flatten-cfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 243cb95d24e4e..50fa7ac2a19aa 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-ha
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From 0216d9f0c2d183ad7cbe8fea1c19d197be2498ff Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f4dc4a483181c..31a80e00edd3b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2284,6 +2284,12 @@ void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const { Base::addPostRegAlloc(addPass); } +void AMDGPUCodeGenPassBuilder::addPreSched2(AddMachinePass &addPass) const { + if (TM.getOptLevel() > CodeGenOptLevel::None) +addPass(SIShrinkInstructionsPass()); + addPass(SIPostRABundlerPass()); +} + void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less)) { addPass(GCNCreateVOPDPass()); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 3c62cd19c6e57..3b2f39c14a9bc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -183,6 +183,7 @@ class AMDGPUCodeGenPassBuilder void addPreEmitPass(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; void addOptimizedRegAlloc(AddMachinePass &) const; + void addPreSched2(AddMachinePass &) const; /// Check if a pass is enabled given \p Opt option. The option always /// overrides defaults if explicitly used. Otherwise its default will be used diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 25d102847ab04..243cb95d24e4e 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,reg-usage-collector,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) +; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,si-post-ra-bundler,fentry-insert,xray-instrumentation,patchable-function,si-memory-legaliz
[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148111 >From 85f834967d5d32b9c687543b705271ffac2bbb32 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:24:23 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Account inserted passes for -start/stop options --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 -- llvm/test/tools/llc/new-pm/start-stop-inserted.ll | 15 +++ 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 llvm/test/tools/llc/new-pm/start-stop-inserted.ll diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index dc5f3f80f547e..44024a4c0a8da 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -579,8 +579,10 @@ template class CodeGenPassBuilder { void insertPass(InsertedPassT &&Pass) const { AfterCallbacks.emplace_back( [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { - if (Name == TargetPassT::name()) -MFPM.addPass(std::forward(Pass)); + if (Name == TargetPassT::name()) { +if (runBeforeAdding(InsertedPassT::name())) + MFPM.addPass(std::forward(Pass)); + } }); } diff --git a/llvm/test/tools/llc/new-pm/start-stop-inserted.ll b/llvm/test/tools/llc/new-pm/start-stop-inserted.ll new file mode 100644 index 0..ce5ad2d9e5065 --- /dev/null +++ b/llvm/test/tools/llc/new-pm/start-stop-inserted.ll @@ -0,0 +1,15 @@ +; REQUIRES: amdgpu-registered-target + +; AMDGPU inserts the fourth instance of dead-mi-elimination pass after detect-dead-lanes +; This checks that the pipeline stops before that. + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -O3 -enable-new-pm -stop-before=dead-mi-elimination,4 --print-pipeline-passes -filetype=null %s | FileCheck %s + +; There is no way to -start-after an inserted pass right now. +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -O3 -enable-new-pm -start-after=dead-mi-elimination,4 --print-pipeline-passes -filetype=null %s + + +; CHECK: dead-mi-elimination +; CHECK: dead-mi-elimination +; CHECK: dead-mi-elimination +; CHECK-NOT: dead-mi-elimination >From 7f105c019984693d21e5e4870c53ff9445764ee9 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Mon, 14 Jul 2025 11:38:59 +0530 Subject: [PATCH 2/2] review comment --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 44024a4c0a8da..a8176ebb776cf 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -579,9 +579,9 @@ template class CodeGenPassBuilder { void insertPass(InsertedPassT &&Pass) const { AfterCallbacks.emplace_back( [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { - if (Name == TargetPassT::name()) { -if (runBeforeAdding(InsertedPassT::name())) - MFPM.addPass(std::forward(Pass)); + if (Name == TargetPassT::name() && + runBeforeAdding(InsertedPassT::name())) { +MFPM.addPass(std::forward(Pass)); } }); } ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148110 >From 9563564e96325df0ce2f36701c65a7f95597cc47 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:15:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Port ProcessImplicitDefs to NPM --- .../llvm/CodeGen/ProcessImplicitDefs.h| 28 + llvm/include/llvm/InitializePasses.h | 2 +- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 + .../llvm/Passes/MachinePassRegistry.def | 2 +- llvm/lib/CodeGen/CodeGen.cpp | 2 +- llvm/lib/CodeGen/ProcessImplicitDefs.cpp | 57 +-- llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 +- .../CodeGen/X86/unreachable-mbb-undef-phi.mir | 1 + 9 files changed, 75 insertions(+), 23 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/ProcessImplicitDefs.h diff --git a/llvm/include/llvm/CodeGen/ProcessImplicitDefs.h b/llvm/include/llvm/CodeGen/ProcessImplicitDefs.h new file mode 100644 index 0..806f68adfded7 --- /dev/null +++ b/llvm/include/llvm/CodeGen/ProcessImplicitDefs.h @@ -0,0 +1,28 @@ +//===- llvm/CodeGen/ProcessImplicitDefs.h ---*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// + +#ifndef LLVM_CODEGEN_PROCESSIMPLICITDEFS_H +#define LLVM_CODEGEN_PROCESSIMPLICITDEFS_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +class ProcessImplicitDefsPass : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, +MachineFunctionAnalysisManager &MFAM); + MachineFunctionProperties getRequiredProperties() const { +return MachineFunctionProperties().set( +MachineFunctionProperties::Property::IsSSA); + } +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_PROCESSIMPLICITDEFS_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index c847716647825..2e231cfba2443 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -257,7 +257,7 @@ LLVM_ABI void initializePostRASchedulerLegacyPass(PassRegistry &); LLVM_ABI void initializePreISelIntrinsicLoweringLegacyPassPass(PassRegistry &); LLVM_ABI void initializePrintFunctionPassWrapperPass(PassRegistry &); LLVM_ABI void initializePrintModulePassWrapperPass(PassRegistry &); -LLVM_ABI void initializeProcessImplicitDefsPass(PassRegistry &); +LLVM_ABI void initializeProcessImplicitDefsLegacyPass(PassRegistry &); LLVM_ABI void initializeProfileSummaryInfoWrapperPassPass(PassRegistry &); LLVM_ABI void initializePromoteLegacyPassPass(PassRegistry &); LLVM_ABI void initializeRABasicPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index bf964fa1fa76d..dc5f3f80f547e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -72,6 +72,7 @@ #include "llvm/CodeGen/PostRAMachineSink.h" #include "llvm/CodeGen/PostRASchedulerList.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" +#include "llvm/CodeGen/ProcessImplicitDefs.h" #include "llvm/CodeGen/RegAllocEvictionAdvisor.h" #include "llvm/CodeGen/RegAllocFast.h" #include "llvm/CodeGen/RegAllocGreedyPass.h" diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 245ea60fd146a..732fdc7c9bc1f 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -152,6 +152,7 @@ MACHINE_FUNCTION_PASS("print", MachineUniformityPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(errs())) +MACHINE_FUNCTION_PASS("process-imp-defs", ProcessImplicitDefsPass()) MACHINE_FUNCTION_PASS("prolog-epilog", PrologEpilogInserterPass()) MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass()) MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass()) @@ -283,7 +284,6 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter) DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass) DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass) DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass) -DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass) DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass) DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass) DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass) diff --git a
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 7d8f2ba9d3aa392c09f20a844ca5ea5cb97519cf Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From 0216d9f0c2d183ad7cbe8fea1c19d197be2498ff Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f4dc4a483181c..31a80e00edd3b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2284,6 +2284,12 @@ void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const { Base::addPostRegAlloc(addPass); } +void AMDGPUCodeGenPassBuilder::addPreSched2(AddMachinePass &addPass) const { + if (TM.getOptLevel() > CodeGenOptLevel::None) +addPass(SIShrinkInstructionsPass()); + addPass(SIPostRABundlerPass()); +} + void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less)) { addPass(GCNCreateVOPDPass()); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 3c62cd19c6e57..3b2f39c14a9bc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -183,6 +183,7 @@ class AMDGPUCodeGenPassBuilder void addPreEmitPass(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; void addOptimizedRegAlloc(AddMachinePass &) const; + void addPreSched2(AddMachinePass &) const; /// Check if a pass is enabled given \p Opt option. The option always /// overrides defaults if explicitly used. Otherwise its default will be used diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 25d102847ab04..243cb95d24e4e 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,fentry-insert,xray-instrumentation,patchable-function,si-memory-legalizer,si-insert-waitcnts,si-late-branch-lowering,post-RA-hazard-rec,amdgpu-wait-sgpr-hazards,branch-relaxation,reg-usage-collector,remove-loads-into-fake-uses,live-debug-values,machine-sanmd,stack-frame-layout,verify),invalidate)) +; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-handles,amdgpu-sw-lower-lds,amdgpu-lower-module-lds,function(atomic-expand,verify,gc-lowering,lower-constant-intrinsics,unreachableblockelim,ee-instrument,scalarize-masked-mem-intrin,expand-reductions,amdgpu-lower-kernel-arguments),amdgpu-lower-buffer-fat-pointers,cgscc(function(lower-switch,lower-invoke,unreachableblockelim,amdgpu-unify-divergent-exit-nodes,fix-irreducible,unify-loop-exits,StructurizeCFGPass,amdgpu-annotate-uniform,si-annotate-control-flow,amdgpu-rewrite-undef-for-phi,lcssa,require,callbr-prepare,safe-stack,stack-protector,verify)),cgscc(function(machine-function(amdgpu-isel,si-fix-sgpr-copies,si-i1-copies,finalize-isel,localstackalloc))),require,cgscc(function(machine-function(reg-usage-propagation,phi-node-elimination,two-address-instruction,regallocfast,si-fix-vgpr-copies,remove-redundant-debug-values,fixup-statepoint-caller-saved,prolog-epilog,post-ra-pseudos,si-post-ra-bundler,fentry-insert,xray-instrumentation,patchable-function,si-memory-legaliz
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 3035640f0f6f0ff104b3f69000f42d9d5f07f053 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llvm/CodeGen/MachineFunctionAnalysis.h | 5 + llvm/include/llvm/IR/PassManager.h | 16 llvm/include/llvm/Passes/CodeGenPassBuilder.h| 2 +- llvm/lib/CodeGen/MachineFunctionAnalysis.cpp | 6 ++ llvm/lib/Passes/PassRegistry.def | 1 + llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/tools/llc/new-pm/start-stop.ll | 2 +- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index 98a60c987bbe3..1d954cf60c68c 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -46,6 +46,11 @@ class MachineFunctionAnalysis LLVM_ABI Result run(Function &F, FunctionAnalysisManager &FAM); }; +class FreeMachineFunctionPass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + } // namespace llvm #endif // LLVM_CODEGEN_MachineFunctionAnalysis diff --git a/llvm/include/llvm/IR/PassManager.h b/llvm/include/llvm/IR/PassManager.h index 4f44ae56eb3c7..ea8226c6e17ba 100644 --- a/llvm/include/llvm/IR/PassManager.h +++ b/llvm/include/llvm/IR/PassManager.h @@ -491,6 +491,22 @@ template class AnalysisManager { /// invalidate them, unless they are preserved by the PreservedAnalyses set. void invalidate(IRUnitT &IR, const PreservedAnalyses &PA); + /// Directly clear a cached analysis for an IR unit. + /// + /// Using invalidate() over this is preferred unless you are really + /// sure you want to *only* clear this analysis without asking if it is + /// invalid. + template void clearAnalysis(IRUnitT &IR) { +AnalysisResultListT &ResultsList = AnalysisResultLists[&IR]; +AnalysisKey *ID = AnalysisT::ID(); + +auto I = +llvm::find_if(ResultsList, [&ID](auto &E) { return E.first == ID; }); +assert(I != ResultsList.end() && "Analysis must be available"); +ResultsList.erase(I); +AnalysisResults.erase({ID, &IR}); + } + private: /// Look up a registered analysis pass. PassConceptT &lookUpPass(AnalysisKey *ID) { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index a8176ebb776cf..b0360f1903c0e 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -281,7 +281,7 @@ template class CodeGenPassBuilder { FunctionPassManager FPM; FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM))); - FPM.addPass(InvalidateAnalysisPass()); + FPM.addPass(FreeMachineFunctionPass()); if (this->PB.AddInCGSCCOrder) { MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor( createCGSCCToFunctionPassAdaptor(std::move(FPM; diff --git a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp index e7a4d6d61e211..116a919585d70 100644 --- a/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp +++ b/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp @@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { return Result(std::move(MF)); } + +PreservedAnalyses FreeMachineFunctionPass::run(Function &F, + FunctionAnalysisManager &FAM) { + FAM.clearAnalysis(F); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 9a943155aa19f..caa78b613b901 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -434,6 +434,7 @@ FUNCTION_PASS("extra-vector-passes", FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flatten-cfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) +FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) FUNCTION_PASS("gc-lowering", GCLoweringPass()) FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 243cb95d24e4e..50fa7ac2a19aa 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -8,11 +8,11 @@ ; RUN: | FileCheck -check-prefix=GCN-O3 %s -; GCN-O0: require,require,require,pre-isel-intrinsic-lowering,function(expand-large-div-rem,expand-fp),amdgpu-remove-incompatible-functions,amdgpu-printf-runtime-binding,amdgpu-lower-ctor-dtor,expand-variadics,amdgpu-always-inline,always-inline,amdgpu-export-kernel-runtime-ha
[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148111 >From 85f834967d5d32b9c687543b705271ffac2bbb32 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:24:23 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Account inserted passes for -start/stop options --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 -- llvm/test/tools/llc/new-pm/start-stop-inserted.ll | 15 +++ 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 llvm/test/tools/llc/new-pm/start-stop-inserted.ll diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index dc5f3f80f547e..44024a4c0a8da 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -579,8 +579,10 @@ template class CodeGenPassBuilder { void insertPass(InsertedPassT &&Pass) const { AfterCallbacks.emplace_back( [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { - if (Name == TargetPassT::name()) -MFPM.addPass(std::forward(Pass)); + if (Name == TargetPassT::name()) { +if (runBeforeAdding(InsertedPassT::name())) + MFPM.addPass(std::forward(Pass)); + } }); } diff --git a/llvm/test/tools/llc/new-pm/start-stop-inserted.ll b/llvm/test/tools/llc/new-pm/start-stop-inserted.ll new file mode 100644 index 0..ce5ad2d9e5065 --- /dev/null +++ b/llvm/test/tools/llc/new-pm/start-stop-inserted.ll @@ -0,0 +1,15 @@ +; REQUIRES: amdgpu-registered-target + +; AMDGPU inserts the fourth instance of dead-mi-elimination pass after detect-dead-lanes +; This checks that the pipeline stops before that. + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -O3 -enable-new-pm -stop-before=dead-mi-elimination,4 --print-pipeline-passes -filetype=null %s | FileCheck %s + +; There is no way to -start-after an inserted pass right now. +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -O3 -enable-new-pm -start-after=dead-mi-elimination,4 --print-pipeline-passes -filetype=null %s + + +; CHECK: dead-mi-elimination +; CHECK: dead-mi-elimination +; CHECK: dead-mi-elimination +; CHECK-NOT: dead-mi-elimination >From 7f105c019984693d21e5e4870c53ff9445764ee9 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Mon, 14 Jul 2025 11:38:59 +0530 Subject: [PATCH 2/2] review comment --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 44024a4c0a8da..a8176ebb776cf 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -579,9 +579,9 @@ template class CodeGenPassBuilder { void insertPass(InsertedPassT &&Pass) const { AfterCallbacks.emplace_back( [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { - if (Name == TargetPassT::name()) { -if (runBeforeAdding(InsertedPassT::name())) - MFPM.addPass(std::forward(Pass)); + if (Name == TargetPassT::name() && + runBeforeAdding(InsertedPassT::name())) { +MFPM.addPass(std::forward(Pass)); } }); } ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/148115 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/148113 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)
https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/148111 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
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[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148107 None >From a7b5f3a39a9f65757d1659eaca8ddf410cf6aa45 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 15:25:03 +0530 Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag --- llvm/include/llvm/CodeGen/VirtRegMap.h | 8 llvm/lib/CodeGen/VirtRegMap.cpp| 2 ++ 2 files changed, 10 insertions(+) diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h index 5ab3f7e742230..b5f962e0fb821 100644 --- a/llvm/include/llvm/CodeGen/VirtRegMap.h +++ b/llvm/include/llvm/CodeGen/VirtRegMap.h @@ -251,6 +251,14 @@ class VirtRegRewriterPass : public PassInfoMixin { LLVM_ABI void printPipeline(raw_ostream &OS, function_ref) const; + + MachineFunctionProperties getSetProperties() const { +if (ClearVirtRegs) { + return MachineFunctionProperties().set( + MachineFunctionProperties::Property::NoVRegs); +} +return {}; + } }; } // end llvm namespace diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 3d6ccba894e9c..99ba893d6f096 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -301,6 +301,8 @@ bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) { PreservedAnalyses VirtRegRewriterPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { + MFPropsModifier _(*this, MF); + VirtRegMap &VRM = MFAM.getResult(MF); LiveIntervals &LIS = MFAM.getResult(MF); LiveRegMatrix &LRM = MFAM.getResult(MF); ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148112** https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148112 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
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[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148109 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148109 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148114?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148115** https://app.graphite.dev/github/pr/llvm/llvm-project/148115?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148114** https://app.graphite.dev/github/pr/llvm/llvm-project/148114?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148114?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148113** https://app.graphite.dev/github/pr/llvm/llvm-project/148113?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148112** https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148114 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148110 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148107 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148108 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148113 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148110 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148112 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148108 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148114 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148111 None Unicorn! ยท GitHub body { background-color: #f1f1f1; margin: 0; font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; } .container { margin: 50px auto 40px auto; width: 600px; text-align: center; } a { color: #4183c4; text-decoration: none; } a:hover { text-decoration: underline; } h1 { letter-spacing: -1px; line-height: 60px; font-size: 60px; font-weight: 100; margin: 0px; text-shadow: 0 1px 0 #fff; } p { color: rgba(0, 0, 0, 0.5); margin: 10px 0 10px; font-size: 18px; font-weight: 200; line-height: 1.6em;} ul { list-style: none; margin: 25px 0; padding: 0; } li { display: table-cell; font-weight: bold; width: 1%; } .logo { display: inline-block; margin-top: 35px; } .logo-img-2x { display: none; } @media only screen and (-webkit-min-device-pixel-ratio: 2), only screen and ( min--moz-device-pixel-ratio: 2), only screen and ( -o-min-device-pixel-ratio: 2/1), only screen and (min-device-pixel-ratio: 2), only screen and (min-resolution: 192dpi), only screen and (min-resolution: 2dppx) { .logo-img-1x { display: none; } .logo-img-2x { display: inline-block; } } #suggestions { margin-top: 35px; color: #ccc; } #suggestions a { color: #66; font-weight: 200; font-size: 14px; margin: 0 10px; } No server is currently available to service your request. Sorry about that. Please try refreshing and contact us if the problem persists. https://github.com/contact";>Contact Support โ https://www.githubstatus.com";>GitHub Status โ https://twitter.com/githubstatus";>@githubstatus ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148115?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148115** https://app.graphite.dev/github/pr/llvm/llvm-project/148115?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148115?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148114** https://app.graphite.dev/github/pr/llvm/llvm-project/148114?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148113** https://app.graphite.dev/github/pr/llvm/llvm-project/148113?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148112** https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148115 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148111 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)
vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148113?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#148115** https://app.graphite.dev/github/pr/llvm/llvm-project/148115?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148114** https://app.graphite.dev/github/pr/llvm/llvm-project/148114?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148113** https://app.graphite.dev/github/pr/llvm/llvm-project/148113?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> ๐ https://app.graphite.dev/github/pr/llvm/llvm-project/148113?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#148112** https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148111** https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148110** https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148109** https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148108** https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148107** https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148106** https://app.graphite.dev/github/pr/llvm/llvm-project/148106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/148113 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 2cde96d807e0b2825489696ae94872ec752b48a9 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 2cde96d807e0b2825489696ae94872ec752b48a9 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 16 ++-- llvm/include/llvm/Target/CGPassBuilderOption.h | 2 ++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 - llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 ++-- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index b0360f1903c0e..97c3ff869edf4 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -114,13 +114,16 @@ #include "llvm/Target/CGPassBuilderOption.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/CFGuard.h" +#include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Scalar/ConstantHoisting.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/Transforms/Scalar/LoopTermFold.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" #include "llvm/Transforms/Scalar/MergeICmps.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" +#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/LowerInvoke.h" #include @@ -754,7 +757,12 @@ void CodeGenPassBuilder::addIRPasses( // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { -addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), +LoopPassManager LPM; +LPM.addPass(CanonicalizeFreezeInLoopsPass()); +LPM.addPass(LoopStrengthReducePass()); +if (Opt.EnableLoopTermFold) + LPM.addPass(LoopTermFoldPass()); +addPass(createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true)); } @@ -799,7 +807,8 @@ void CodeGenPassBuilder::addIRPasses( addPass(ScalarizeMaskedMemIntrinPass()); // Expand reduction intrinsics into shuffle sequences if the target wants to. - addPass(ExpandReductionsPass()); + if (!Opt.DisableExpandReductions) +addPass(ExpandReductionsPass()); // Convert conditional moves to conditional jumps when profitable. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize) @@ -877,6 +886,9 @@ void CodeGenPassBuilder::addISelPrepare( if (Opt.RequiresCodeGenSCCOrder) addPass.requireCGSCCOrder(); + if (getOptLevel() != CodeGenOptLevel::None) +addPass(ObjCARCContractPass()); + addPass(CallBrPreparePass()); // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index f29cbe78a1853..8d0a7e61970fa 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,6 +52,8 @@ struct CGPassBuilderOption { bool EnableMachineFunctionSplitter = false; bool EnableSinkAndFold = false; bool EnableTailMerge = true; + /// Enable LoopTermFold immediately after LSR. + bool EnableLoopTermFold = false; bool MISchedPostRA = false; bool EarlyLiveIntervals = false; bool GCEmptyBlocks = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 31a80e00edd3b..3848eeb380ce2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -103,7 +103,9 @@ #include "llvm/Transforms/Scalar/FlattenCFG.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" +#include "llvm/Transforms/Scalar/LICM.h" #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" #include "llvm/Transforms/Scalar/Sink.h" @@ -2054,7 +2056,12 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // TODO: May want to move later or split into an early and late one. addPass(AMDGPUCodeGenPreparePass(TM)); -// TODO: LICM +// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may +// have expanded. +if (TM.getOptLevel() > CodeGenOptLevel::Less) { + addPass(createFunctionToLoopPassAdaptor(LICMPass(LICMOptions()), + /*UseMemorySSA=*/true)); +} } Base::addIRPasses(addPass); d
[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 1ede33ef7233acdfe1dee3b632382886e1090fb8 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h | 1 + llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h| 3 +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h| 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 + llvm/lib/Target/AMDGPU/GCNNSAReassign.h| 1 + llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 1 + llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h | 1 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h | 1 + llvm/lib/Target/AMDGPU/SILowerControlFlow.h| 1 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 1 + llvm/lib/Target/AMDGPU/SILowerWWMCopies.h | 1 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 1 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 1 + llvm/test/Feature/optnone-opt.ll | 1 - 16 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h index f68067d935458..f50511c9c0972 100644 --- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h +++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin { function_ref MapClassName2PassName); PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // namespace llvm diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h index 8f3fa1f2b18ef..d179002fd6a27 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h +++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h @@ -54,6 +54,7 @@ class ScalarEvolution; class LoopSimplifyPass : public PassInfoMixin { public: LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; /// Simplify each loop in a loop nest recursively. diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 23f106a9c1d4d..4a19fe3df6fd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin { SILowerI1CopiesPass() = default; PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin { public: SIModeRegisterPass() {} PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; class SIMemoryLegalizerPass : public PassInfoMixin { @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass public: SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {} PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index 9967f46e085e4..78dbf62e5798f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -290,6 +290,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } }; class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h index 2fd98a2ee1a93..d6fb0e53e1169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass : public PassInfoMixin { public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h index 97a72e7ddbb24..4f2abe0dd0086 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunctio