[llvm-branch-commits] [TableGen] Support RegClassByHwMode in CompressPat (PR #171061)
llvmbot wrote:
@llvm/pr-subscribers-tablegen
Author: Alexander Richardson (arichardson)
Changes
This does not yet handle all cases but at least for the simple
cases such as:
```
def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
(PTR_MOV_SMALL PtrRC:$dst, PtrRC:$src)>;
```
tablegen generates sensible code instead of emitting confusing errors.
---
Full diff: https://github.com/llvm/llvm-project/pull/171061.diff
2 Files Affected:
- (added) llvm/test/TableGen/RegClassByHwModeCompressPat.td (+315)
- (modified) llvm/utils/TableGen/CompressInstEmitter.cpp (+10-9)
``diff
diff --git a/llvm/test/TableGen/RegClassByHwModeCompressPat.td
b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
new file mode 100644
index 0..263b53f6fbba5
--- /dev/null
+++ b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
@@ -0,0 +1,315 @@
+// RUN: llvm-tblgen --gen-compress-inst-emitter -I %p/../../include -I %S %s
-o - | FileCheck %s
+
+include "Common/RegClassByHwModeCommon.td"
+
+def IsPtr64 : Predicate<"Subtarget->isPtr64()">;
+defvar Ptr32 = DefaultMode;
+def Ptr64 : HwMode<[IsPtr64]>;
+def PtrRC : RegClassByHwMode<[Ptr32, Ptr64], [XRegs, YRegs]>;
+
+
+def X_MOV : TestInstruction {
+ let OutOperandList = (outs XRegs:$dst);
+ let InOperandList = (ins XRegs:$src);
+ let AsmString = "x_mov $dst, $src";
+ let opcode = 0;
+}
+
+def X_MOV_SMALL : TestInstruction {
+ let OutOperandList = (outs XRegs:$dst);
+ let InOperandList = (ins XRegs:$src);
+ let AsmString = "x_mov.small $dst, $src";
+ let opcode = 1;
+ let Size = 1;
+}
+def X_MOV_ZERO : TestInstruction {
+ let OutOperandList = (outs XRegs:$dst);
+ let InOperandList = (ins);
+ let AsmString = "x_mov.zero $dst";
+ let opcode = 2;
+ let Size = 1;
+}
+def X_MOV_TIED : TestInstruction {
+ let OutOperandList = (outs XRegs:$dst);
+ let InOperandList = (ins XRegs:$src);
+ let Constraints = "$src = $dst";
+ let AsmString = "x_mov.tied $dst, $src";
+ let opcode = 3;
+ let Size = 1;
+}
+
+def PTR_MOV : TestInstruction {
+ let OutOperandList = (outs PtrRC:$dst);
+ let InOperandList = (ins PtrRC:$src);
+ let AsmString = "ptr_mov $dst, $src";
+ let opcode = 3;
+}
+
+def PTR_MOV_SMALL : TestInstruction {
+ let OutOperandList = (outs PtrRC:$dst);
+ let InOperandList = (ins PtrRC:$src);
+ let AsmString = "ptr_mov.small $dst, $src";
+ let opcode = 4;
+ let Size = 1;
+}
+def PTR_MOV_ZERO : TestInstruction {
+ let OutOperandList = (outs PtrRC:$dst);
+ let InOperandList = (ins);
+ let AsmString = "ptr_mov.zero $dst";
+ let opcode = 3;
+ let Size = 1;
+}
+def PTR_MOV_TIED : TestInstruction {
+ let OutOperandList = (outs PtrRC:$dst);
+ let InOperandList = (ins PtrRC:$src);
+ let Constraints = "$src = $dst";
+ let AsmString = "ptr_mov.tied $dst, $src";
+ let opcode = 3;
+ let Size = 1;
+}
+
+def : CompressPat<(X_MOV XRegs:$dst, X0),
+ (X_MOV_ZERO XRegs:$dst)>;
+def : CompressPat<(X_MOV XRegs:$dst, XRegs:$dst),
+ (X_MOV_TIED XRegs:$dst)>;
+def : CompressPat<(X_MOV XRegs:$dst, XRegs:$src),
+ (X_MOV_SMALL XRegs:$dst, XRegs:$src)>;
+// TODO: Should also be able to use a fixed register with RegClassByHwMode
+// def : CompressPat<(PTR_MOV PtrRC:$dst, X0),
+// (PTR_MOV_ZERO PtrRC:$dst)>;
+def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$dst),
+ (PTR_MOV_TIED PtrRC:$dst)>;
+def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
+ (PTR_MOV_SMALL PtrRC:$dst, PtrRC:$src)>;
+
+// CHECK: static bool compressInst(MCInst &OutInst,
+// CHECK-NEXT: const MCInst &MI,
+// CHECK-NEXT: const MCSubtargetInfo &STI) {
+// CHECK-NEXT: switch (MI.getOpcode()) {
+// CHECK-NEXT: default: return false;
+// CHECK-NEXT: case MyTarget::PTR_MOV: {
+// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
+// CHECK-NEXT: (MI.getOperand(1).getReg() ==
MI.getOperand(0).getReg()) &&
+// CHECK-NEXT: MI.getOperand(1).isReg() &&
+// CHECK-NEXT:
MyTargetMCRegisterClasses[STI.getInstrInfo().getOpRegClassID(MI.getDesc().operands()[1])].contains(MI.getOperand(1).getReg()))
{
+// CHECK-NEXT: // ptr_mov.tied $dst, $src
+// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV_TIED);
+// CHECK-NEXT: // Operand: dst
+// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
+// CHECK-NEXT: // Operand: src
+// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
+// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
+// CHECK-NEXT: return true;
+// CHECK-NEXT: } // if
+// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
+// CHECK-NEXT:
MyTargetMCRegisterClasses[STI.getInstrInfo().getOpRegClassID(MI.getDesc().operands()[0])].contains(MI.getOperand(0).getReg())
&&
+// CHECK-NEXT: MI.getOperand(1).isReg() &&
+// CHECK-NEXT:
MyTargetMCRegisterClasses[STI.getInstrInfo().getOpRegClassID(MI.getDesc().operands()
[llvm-branch-commits] [TableGen] Slightly improve error location for a fatal error (PR #170790)
https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/170790 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [TableGen] Support RegClassByHwMode in CompressPat (PR #171061)
https://github.com/arichardson created https://github.com/llvm/llvm-project/pull/171061 This does not yet handle all cases but at least for the simple cases such as: ``` def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src), (PTR_MOV_SMALL PtrRC:$dst, PtrRC:$src)>; ``` tablegen generates sensible code instead of emitting confusing errors. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [TableGen] Support RegClassByHwMode in CompressPat (PR #171061)
arichardson wrote: I believe the output is correct, but I will wait before submitting this until I have some actual real-world tests for this (based on adding the RVY extension). https://github.com/llvm/llvm-project/pull/171061 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [TableGen] Slightly improve error location for a fatal error (PR #170790)
https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/170790 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [TableGen] Slightly improve error location for a fatal error (PR #170790)
@@ -1316,11 +1316,18 @@ CodeGenRegBank::getOrCreateSubClass(const
CodeGenRegisterClass *RC,
return {&RegClasses.back(), true};
}
-CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
+CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def,
+ ArrayRef Loc) const {
if (CodeGenRegisterClass *RC = Def2RC.lookup(Def))
return RC;
- PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
+ ArrayRef DiagLoc = Loc.empty() ? Def->getLoc() : Loc;
+ // TODO: Ideally we should update the API to allow resolving HwMode.
arichardson wrote:
I've added a test case for this. If there are no further comments I'll submit
this tomorrow.
https://github.com/llvm/llvm-project/pull/170790
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[llvm-branch-commits] [clang] [llvm] [RFC][LLVM][Clang] Add LLVM plugin hook for back-ends (PR #170846)
https://github.com/vgvassilev approved this pull request. LGTM! Thank you, @aengelke! https://github.com/llvm/llvm-project/pull/170846 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [CIR] Implement function personality attribute and its lowering (PR #171001)
https://github.com/AmrDeveloper approved this pull request. LGTM, Thanks https://github.com/llvm/llvm-project/pull/171001 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [TableGen] Slightly improve error location for a fatal error (PR #170790)
@@ -1316,11 +1316,18 @@ CodeGenRegBank::getOrCreateSubClass(const
CodeGenRegisterClass *RC,
return {&RegClasses.back(), true};
}
-CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
+CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def,
+ ArrayRef Loc) const {
if (CodeGenRegisterClass *RC = Def2RC.lookup(Def))
return RC;
- PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
+ ArrayRef DiagLoc = Loc.empty() ? Def->getLoc() : Loc;
+ // TODO: Ideally we should update the API to allow resolving HwMode.
arsenm wrote:
No, that would not be very ergonomic. The point is to have reusable patterns
and not have to spam every possible detail through every deeply nested multi
class
https://github.com/llvm/llvm-project/pull/170790
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[llvm-branch-commits] [llvm] [AMDGPU] Use different name scope for MIMGBaseOpcode (PR #170904)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/170904 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [CIR] Make CIR-to-LLVM a one shot conversion (PR #171083)
https://github.com/xlauko created
https://github.com/llvm/llvm-project/pull/171083
This had to fix memory and conversion bugs due to now immediate
conversion patterns and no longer present original MLIR.
>From b93a2e68fdc1a42d91e91eb543106054087aa8f1 Mon Sep 17 00:00:00 2001
From: xlauko
Date: Mon, 8 Dec 2025 07:32:02 +0100
Subject: [PATCH] [CIR] Make CIR-to-LLVM a one shot conversion
This had to fix memory and conversion bugs due to now immediate
conversion patterns and no longer present original MLIR.
---
clang/include/clang/CIR/Dialect/IR/CIROps.td | 2 +-
.../CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp | 127 --
2 files changed, 86 insertions(+), 43 deletions(-)
diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td
b/clang/include/clang/CIR/Dialect/IR/CIROps.td
index 3d6de2a97d650..1b7fa953e8a37 100644
--- a/clang/include/clang/CIR/Dialect/IR/CIROps.td
+++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td
@@ -2160,7 +2160,7 @@ def CIR_GlobalOp : CIR_Op<"global", [
cir::GlobalOp op, mlir::Attribute init,
mlir::ConversionPatternRewriter &rewriter) const;
-void setupRegionInitializedLLVMGlobalOp(
+mlir::LLVM::GlobalOp setupRegionInitializedLLVMGlobalOp(
cir::GlobalOp op, mlir::ConversionPatternRewriter &rewriter) const;
mutable mlir::LLVM::ComdatOp comdatOp = nullptr;
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index aea9e26341f8f..8e2b47dbeb629 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -716,8 +716,7 @@ mlir::LogicalResult
CIRToLLVMIsFPClassOpLowering::matchAndRewrite(
mlir::LogicalResult CIRToLLVMAssumeOpLowering::matchAndRewrite(
cir::AssumeOp op, OpAdaptor adaptor,
mlir::ConversionPatternRewriter &rewriter) const {
- auto cond = adaptor.getPredicate();
- rewriter.replaceOpWithNewOp(op, cond);
+ rewriter.replaceOpWithNewOp(op,
adaptor.getPredicate());
return mlir::success();
}
@@ -1130,11 +1129,11 @@ mlir::LogicalResult
CIRToLLVMBrCondOpLowering::matchAndRewrite(
// ZExtOp and if so, delete it if it has a single use.
assert(!cir::MissingFeatures::zextOp());
- mlir::Value i1Condition = adaptor.getCond();
-
+
rewriter.replaceOpWithNewOp(
- brOp, i1Condition, brOp.getDestTrue(), adaptor.getDestOperandsTrue(),
- brOp.getDestFalse(), adaptor.getDestOperandsFalse());
+ brOp, adaptor.getCond(), brOp.getDestTrue(),
+ adaptor.getDestOperandsTrue(), brOp.getDestFalse(),
+ adaptor.getDestOperandsFalse());
return mlir::success();
}
@@ -1942,12 +1941,12 @@ mlir::LogicalResult
CIRToLLVMFuncOpLowering::matchAndRewriteAlias(
lowerFuncAttributes(op, /*filterArgAndResAttrs=*/false, attributes);
mlir::Location loc = op.getLoc();
+ mlir::OpBuilder builder(op.getContext());
auto aliasOp = rewriter.replaceOpWithNewOp(
op, ty, convertLinkage(op.getLinkage()), op.getName(), op.getDsoLocal(),
/*threadLocal=*/false, attributes);
// Create the alias body
- mlir::OpBuilder builder(op.getContext());
mlir::Block *block = builder.createBlock(&aliasOp.getInitializerRegion());
builder.setInsertionPointToStart(block);
// The type of AddressOfOp is always a pointer.
@@ -2053,7 +2052,8 @@ mlir::LogicalResult
CIRToLLVMGetGlobalOpLowering::matchAndRewrite(
/// Replace CIR global with a region initialized LLVM global and update
/// insertion point to the end of the initializer block.
-void CIRToLLVMGlobalOpLowering::setupRegionInitializedLLVMGlobalOp(
+mlir::LLVM::GlobalOp
+CIRToLLVMGlobalOpLowering::setupRegionInitializedLLVMGlobalOp(
cir::GlobalOp op, mlir::ConversionPatternRewriter &rewriter) const {
const mlir::Type llvmType =
convertTypeForMemory(*getTypeConverter(), dataLayout, op.getSymType());
@@ -2080,6 +2080,7 @@ void
CIRToLLVMGlobalOpLowering::setupRegionInitializedLLVMGlobalOp(
isDsoLocal, isThreadLocal, comdatAttr, attributes);
newGlobalOp.getRegion().emplaceBlock();
rewriter.setInsertionPointToEnd(newGlobalOp.getInitializerBlock());
+ return newGlobalOp;
}
mlir::LogicalResult
@@ -2097,8 +2098,9 @@
CIRToLLVMGlobalOpLowering::matchAndRewriteRegionInitializedGlobal(
// should be updated. For now, we use a custom op to initialize globals
// to the appropriate value.
const mlir::Location loc = op.getLoc();
- setupRegionInitializedLLVMGlobalOp(op, rewriter);
- CIRAttrToValue valueConverter(op, rewriter, typeConverter);
+ mlir::LLVM::GlobalOp newGlobalOp =
+ setupRegionInitializedLLVMGlobalOp(op, rewriter);
+ CIRAttrToValue valueConverter(newGlobalOp, rewriter, typeConverter);
mlir::Value value = valueConverter.visit(init);
mlir::LLVM::ReturnOp::create(rewriter, loc, value);
return mlir::success();
@@ -2795,42 +2797,45 @@ mlir::LogicalResult
CIRToLLVMShiftOpLowering::matchAndRewrite(
mlir::LogicalResult CIRToLLVMSelectOpLowering::ma
[llvm-branch-commits] [clang] [CIR] Make CIR-to-LLVM a one shot conversion (PR #171083)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff origin/main HEAD --extensions cpp --
clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp --diff_from_common_commit
``
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
View the diff from clang-format here.
``diff
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index 8e2b47dbe..52455fdc4 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -1129,7 +1129,6 @@ mlir::LogicalResult
CIRToLLVMBrCondOpLowering::matchAndRewrite(
// ZExtOp and if so, delete it if it has a single use.
assert(!cir::MissingFeatures::zextOp());
-
rewriter.replaceOpWithNewOp(
brOp, adaptor.getCond(), brOp.getDestTrue(),
adaptor.getDestOperandsTrue(), brOp.getDestFalse(),
@@ -3781,7 +3780,7 @@ mlir::LogicalResult
CIRToLLVMComplexRealOpLowering::matchAndRewrite(
rewriter, op.getLoc(), resultLLVMTy, operand,
llvm::ArrayRef{0});
}
-
+
rewriter.replaceOp(op, operand);
return mlir::success();
}
``
https://github.com/llvm/llvm-project/pull/171083
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[llvm-branch-commits] [clang] [CIR] Make CIR-to-LLVM a one shot conversion (PR #171083)
xlauko wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/171083?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#171083** https://app.graphite.com/github/pr/llvm/llvm-project/171083?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.com/github/pr/llvm/llvm-project/171083?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#171001** https://app.graphite.com/github/pr/llvm/llvm-project/171001?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#171000** https://app.graphite.com/github/pr/llvm/llvm-project/171000?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/171083 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [CIR] Make CIR-to-LLVM a one shot conversion (PR #171083)
github-actions[bot] wrote: # :penguin: Linux x64 Test Results * 85763 tests passed * 758 tests skipped * 2 tests failed ## Failed Tests (click on a test name to see its output) ### Clang Clang.CIR/CodeGen/complex-compound-assignment.cpp ``` Exit Code: 1 Command Output (stdout): -- # RUN: at line 1 /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang -cc1 -internal-isystem /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/clang/22/include -nostdsysteminc -std=c++20 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -o /home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir # executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang -cc1 -internal-isystem /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/clang/22/include -nostdsysteminc -std=c++20 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -o /home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir # note: command had no output on stdout or stderr # RUN: at line 2 /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck --input-file=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp --check-prefixes=CIR,CXX_CIR # executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck --input-file=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp --check-prefixes=CIR,CXX_CIR # note: command had no output on stdout or stderr # RUN: at line 3 /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang -cc1 -internal-isystem /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/clang/22/include -nostdsysteminc -x c -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -o /home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir # executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang -cc1 -internal-isystem /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/clang/22/include -nostdsysteminc -x c -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -o /home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir # note: command had no output on stdout or stderr # RUN: at line 4 /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck --input-file=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -check-prefix=CIR # executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck --input-file=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp.cir /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -check-prefix=CIR # note: command had no output on stdout or stderr # RUN: at line 5 /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang -cc1 -internal-isystem /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/clang/22/include -nostdsysteminc -std=c++20 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-llvm /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/test/CIR/CodeGen/complex-compound-assignment.cpp -o /home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/test/CIR/CodeGen/Output/complex-compound-assignment.cpp.tmp-cir.ll # executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang -cc1 -internal-isystem /home/gha/actions-runner/_work/llvm-project/llvm-project/bu
[llvm-branch-commits] [llvm] 2e2eea7 - Revert "[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC (#170726)"
Author: Craig Topper
Date: 2025-12-07T22:50:15-08:00
New Revision: 2e2eea73f6a1a48978d54400ede4ae905d1bcf6d
URL:
https://github.com/llvm/llvm-project/commit/2e2eea73f6a1a48978d54400ede4ae905d1bcf6d
DIFF:
https://github.com/llvm/llvm-project/commit/2e2eea73f6a1a48978d54400ede4ae905d1bcf6d.diff
LOG: Revert "[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC
(#170726)"
This reverts commit 446a3a19ed93449a9b50533f924f4bb658fd113e.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
index 445e513d36a38..a3e02ee4fc430 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
@@ -278,7 +278,7 @@ let Uses = [FRM], mayRaiseFPException = true in {
} // DecoderNamespace = "XSfvector"
class VPseudoSF_VTileLoad
-: RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, GPRNoX0:$atn,
ixlenimm:$sew,
+: RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,
ixlenimm:$twiden)> {
let mayLoad = 1;
let mayStore = 0;
@@ -289,7 +289,7 @@ class VPseudoSF_VTileLoad
}
class VPseudoSF_VTileStore
-: RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, GPRNoX0:$atn,
ixlenimm:$sew,
+: RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,
ixlenimm:$twiden)> {
let mayLoad = 0;
let mayStore = 1;
@@ -300,7 +300,7 @@ class VPseudoSF_VTileStore
}
class VPseudoSF_VTileMove_V_T
-: RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, GPRNoX0:$atn, ixlenimm:$sew,
+: RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, AVL:$atn, ixlenimm:$sew,
ixlenimm:$twiden)> {
let mayLoad = 0;
let mayStore = 0;
@@ -311,7 +311,7 @@ class VPseudoSF_VTileMove_V_T
}
class VPseudoSF_VTileMove_T_V
-: RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, GPRNoX0:$atn,
ixlenimm:$sew,
+: RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, AVL:$atn, ixlenimm:$sew,
ixlenimm:$twiden)> {
let mayLoad = 0;
let mayStore = 0;
@@ -323,9 +323,8 @@ class VPseudoSF_VTileMove_T_V
class VPseudoSF_MatMul
: RISCVVPseudo<(outs),
- (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, GPRNoX0:$atm,
-GPRNoX0:$atn, GPRNoX0:$atk, ixlenimm:$sew,
-ixlenimm:$twiden)> {
+ (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, AVL:$atm,
AVL:$atn,
+AVL:$atk, ixlenimm:$sew, ixlenimm:$twiden)> {
let mayLoad = 0;
let mayStore = 0;
let HasTmOp = 1;
@@ -339,7 +338,7 @@ class VPseudoSF_MatMul
class VPseudoSF_MatMul_FRM
: RISCVVPseudo<(outs),
(ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, ixlenimm:$frm,
-GPRNoX0:$atm, GPRNoX0:$atn, GPRNoX0:$atk,
ixlenimm:$sew,
+AVL:$atm, AVL:$atn, AVL:$atk, ixlenimm:$sew,
ixlenimm:$twiden), []> {
let mayLoad = 0;
let mayStore = 0;
@@ -414,7 +413,7 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
let HasVLOp = 1, HasTmOp = 1, HasTWidenOp = 1, HasSEWOp = 1 in
def PseudoSF_VTZERO_T
: RISCVVPseudo<(outs),
- (ins TR:$rd, GPRNoX0:$atm, GPRNoX0:$atn, ixlenimm:$sew,
+ (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew,
ixlenimm:$twiden)>;
def PseudoSF_VTDISCARD : RISCVVPseudo<(outs), (ins), []>;
}
@@ -425,7 +424,7 @@ class VPatXSfmmTileStore(intrinsic_name)
(XLenVT GPR:$rs2),
(XLenVT GPR:$rs1),
- (XLenVT GPRNoX0:$tn)),
+ (XLenVT AVL:$tn)),
(!cast(inst_name)
(XLenVT GPR:$rs2),
(XLenVT GPR:$rs1),
@@ -438,7 +437,7 @@ class VPatXSfmmTileMove_T_V(intrinsic_name)
(XLenVT GPR:$rs1),
(reg_type VRM8:$vs2),
-(XLenVT GPRNoX0:$atn)),
+(XLenVT AVL:$atn)),
(!cast(inst_name)
(XLenVT GPR:$rs1),
(reg_type VRM8:$vs2),
@@ -450,7 +449,7 @@ class VPatXSfmmTileMove_V_T :
Pat<(result_type (!cast(intrinsic_name)
(XLenVT GPR:$rs1),
-(XLenVT GPRNoX0:$atn))),
+(XLenVT AVL:$atn))),
(!cast(inst_name)
(XLenVT GPR:$rs1),
GPR:$atn, log2sew, 1)>;
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