[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156840

>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 288b41bc42203..455de644daf00 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1289,6 +1289,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   // Check if QualType contains a pointer. Implements a simple DFS to
   // recursively check if a type contains a pointer type.
   llvm::SmallPtrSet VisitedRD;
+  bool IncompleteType = false;
   auto TypeContainsPtr = [&](auto &&self, QualType T) -> bool {
 QualType CanonicalType = T.getCanonicalType();
 if (CanonicalType->isPointerType())
@@ -1312,6 +1313,10 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   return self(self, AT->getElementType());
 // The type is a struct, class, or union.
 if (const RecordDecl *RD = CanonicalType->getAsRecordDecl()) {
+  if (!RD->isCompleteDefinition()) {
+IncompleteType = true;
+return false;
+  }
   if (!VisitedRD.insert(RD).second)
 return false; // already visited
   // Check all fields.
@@ -1333,6 +1338,8 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
 return false;
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
+  if (!ContainsPtr && IncompleteType)
+return nullptr;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

>From 7f706618ddc40375d4085bc2ebe03f02ec78823a Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:58:01 +0200
Subject: [PATCH 2/2] fixup!

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 455de644daf00..e7a0e7696e204 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1339,7 +1339,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
   if (!ContainsPtr && IncompleteType)
-return nullptr;
+return;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

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[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

[Marco Elver via llvm-branch-commits]

@@ -183,12 +201,20 @@ class TypeHashMode : public ModeBase {
   using ModeBase::ModeBase;
 
   uint64_t operator()(const CallBase &CB, OptimizationRemarkEmitter &ORE) {
+const auto [N, H] = getHash(CB, ORE);
+return N ? boundedToken(H) : H;
+  }
+
+protected:
+  std::pair getHash(const CallBase &CB,
+OptimizationRemarkEmitter &ORE) {
 if (MDNode *N = getAllocTokenMetadata(CB)) {
   MDString *S = cast(N->getOperand(0));
-  return boundedToken(xxHash64(S->getString()));
+  return {N, xxHash64(S->getString())};

melver wrote:

Yeah, xxHash64 appears to be stable but not defined to be. It's also used for 
KCFI for example.

However, I'd prefer something that has "stable" in it, so let's define 
getStableSipHash() which is what the ptrauth hash is based on: 
https://github.com/llvm/llvm-project/pull/160945

https://github.com/llvm/llvm-project/pull/156840
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[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156839

>From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Thu, 4 Sep 2025 12:07:26 +0200
Subject: [PATCH] fixup! Insert AllocToken into index.rst

Created using spr 1.3.8-beta.1
---
 clang/docs/index.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/docs/index.rst b/clang/docs/index.rst
index be654af57f890..aa2b3a73dc11b 100644
--- a/clang/docs/index.rst
+++ b/clang/docs/index.rst
@@ -40,6 +40,7 @@ Using Clang as a Compiler
SanitizerCoverage
SanitizerStats
SanitizerSpecialCaseList
+   AllocToken
BoundsSafety
BoundsSafetyAdoptionGuide
BoundsSafetyImplPlans

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[llvm-branch-commits] [llvm] Greedy: Use initializer list for recoloring candidates (NFC) (PR #160486)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160486

>From 35d5c37667cfebc6208a2f7d274f85e60675f661 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:14:06 +0900
Subject: [PATCH] Greedy: Use initializer list for recoloring candidates (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6957548ac6c7a..bb8ebe7d7ddf1 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2486,15 +2486,13 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   // We have a broken hint, check if it is possible to fix it by
   // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
   // some register and PhysReg may be available for the other live-ranges.
-  SmallSet Visited;
-  SmallVector RecoloringCandidates;
   HintsInfo Info;
   Register Reg = VirtReg.reg();
   MCRegister PhysReg = VRM->getPhys(Reg);
   // Start the recoloring algorithm from the input live-interval, then
   // it will propagate to the ones that are copy-related with it.
-  Visited.insert(Reg);
-  RecoloringCandidates.push_back(Reg);
+  SmallSet Visited = {Reg};
+  SmallVector RecoloringCandidates = {Reg};
 
   LLVM_DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI)
 << '(' << printReg(PhysReg, TRI) << ")\n");

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[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160467

>From ab5210369e2999663044dbabd34491daf75f53b1 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 16:53:33 +0900
Subject: [PATCH] Greedy: Take hints from copy to physical subreg

Previously this took hints from subregister extract of physreg,
like  %vreg.sub = COPY $physreg

This now also handles the rarer case:
  $physreg_sub = COPY %vreg

Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 35 -
 llvm/test/CodeGen/X86/shift-i128.ll |  3 +--
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..0df8713dd892b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2439,25 +2439,28 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 unsigned SubReg = Opnd.getSubReg();
 
 // Get the current assignment.
-MCRegister OtherPhysReg =
-OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg);
-if (OtherSubReg) {
-  if (OtherReg.isPhysical()) {
-MCRegister Tuple =
-TRI->getMatchingSuperReg(OtherPhysReg, OtherSubReg, RC);
-if (!Tuple)
-  continue;
-OtherPhysReg = Tuple;
-  } else {
-// TODO: There should be a hinting mechanism for subregisters
-if (SubReg != OtherSubReg)
-  continue;
-  }
+MCRegister OtherPhysReg;
+if (OtherReg.isPhysical()) {
+  if (OtherSubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, OtherSubReg, RC);
+  else if (SubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, SubReg, RC);
+  else
+OtherPhysReg = OtherReg;
+} else {
+  OtherPhysReg = VRM->getPhys(OtherReg);
+  // TODO: Should find matching superregister, but applying this in the
+  // non-hint case currently causes regressions
+
+  if (SubReg && OtherSubReg && SubReg != OtherSubReg)
+continue;
 }
 
 // Push the collected information.
-Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
-   OtherPhysReg));
+if (OtherPhysReg) {
+  Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
+ OtherPhysReg));
+}
   }
 }
 
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll 
b/llvm/test/CodeGen/X86/shift-i128.ll
index 7462c77482827..049ee47af9681 100644
--- a/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/llvm/test/CodeGen/X86/shift-i128.ll
@@ -613,8 +613,7 @@ define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, 
ptr nocapture %r) nou
 ; i686-NEXT:shldl %cl, %esi, %ebx
 ; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
 ; i686-NEXT:movl %edi, %esi
-; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; i686-NEXT:movl %eax, %ecx
+; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
 ; i686-NEXT:shll %cl, %esi
 ; i686-NEXT:shldl %cl, %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
 ; i686-NEXT:negl %edx

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[llvm-branch-commits] [llvm] Greedy: Move physreg check when trying to recolor vregs (NFC) (PR #160484)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160484

>From 5e1d9bbb70573ae0dba49769638b977895f4385e Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:02:49 +0900
Subject: [PATCH] Greedy: Move physreg check when trying to recolor vregs (NFC)

Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..dc23ab3ce9d2b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,10 +2502,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
-// We cannot recolor physical register.
-if (Reg.isPhysical())
-  continue;
-
 // This may be a skipped register.
 if (!VRM->hasPhys(Reg)) {
   assert(!shouldAllocateRegister(Reg) &&
@@ -2553,7 +2549,8 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Push all copy-related live-ranges to keep reconciling the broken
 // hints.
 for (const HintInfo &HI : Info) {
-  if (Visited.insert(HI.Reg).second)
+  // We cannot recolor physical register.
+  if (HI.Reg.isVirtual() && Visited.insert(HI.Reg).second)
 RecoloringCandidates.push_back(HI.Reg);
 }
   } while (!RecoloringCandidates.empty());

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[llvm-branch-commits] [llvm] Greedy: Merge VirtRegMap queries into one use (NFC) (PR #160485)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160485

>From b049f4ae5a64c12116b44dd35065e30983965f51 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:06:39 +0900
Subject: [PATCH] Greedy: Merge VirtRegMap queries into one use (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index dc23ab3ce9d2b..6957548ac6c7a 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,8 +2502,10 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
+MCRegister CurrPhys = VRM->getPhys(Reg);
+
 // This may be a skipped register.
-if (!VRM->hasPhys(Reg)) {
+if (!CurrPhys) {
   assert(!shouldAllocateRegister(Reg) &&
  "We have an unallocated variable which should have been handled");
   continue;
@@ -2512,7 +2514,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Get the live interval mapped with this virtual register to be able
 // to check for the interference with the new color.
 LiveInterval &LI = LIS->getInterval(Reg);
-MCRegister CurrPhys = VRM->getPhys(Reg);
 // Check that the new color matches the register class constraints and
 // that it is free for this live range.
 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||

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[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160467

>From ab5210369e2999663044dbabd34491daf75f53b1 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 16:53:33 +0900
Subject: [PATCH] Greedy: Take hints from copy to physical subreg

Previously this took hints from subregister extract of physreg,
like  %vreg.sub = COPY $physreg

This now also handles the rarer case:
  $physreg_sub = COPY %vreg

Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 35 -
 llvm/test/CodeGen/X86/shift-i128.ll |  3 +--
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..0df8713dd892b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2439,25 +2439,28 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 unsigned SubReg = Opnd.getSubReg();
 
 // Get the current assignment.
-MCRegister OtherPhysReg =
-OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg);
-if (OtherSubReg) {
-  if (OtherReg.isPhysical()) {
-MCRegister Tuple =
-TRI->getMatchingSuperReg(OtherPhysReg, OtherSubReg, RC);
-if (!Tuple)
-  continue;
-OtherPhysReg = Tuple;
-  } else {
-// TODO: There should be a hinting mechanism for subregisters
-if (SubReg != OtherSubReg)
-  continue;
-  }
+MCRegister OtherPhysReg;
+if (OtherReg.isPhysical()) {
+  if (OtherSubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, OtherSubReg, RC);
+  else if (SubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, SubReg, RC);
+  else
+OtherPhysReg = OtherReg;
+} else {
+  OtherPhysReg = VRM->getPhys(OtherReg);
+  // TODO: Should find matching superregister, but applying this in the
+  // non-hint case currently causes regressions
+
+  if (SubReg && OtherSubReg && SubReg != OtherSubReg)
+continue;
 }
 
 // Push the collected information.
-Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
-   OtherPhysReg));
+if (OtherPhysReg) {
+  Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
+ OtherPhysReg));
+}
   }
 }
 
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll 
b/llvm/test/CodeGen/X86/shift-i128.ll
index 7462c77482827..049ee47af9681 100644
--- a/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/llvm/test/CodeGen/X86/shift-i128.ll
@@ -613,8 +613,7 @@ define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, 
ptr nocapture %r) nou
 ; i686-NEXT:shldl %cl, %esi, %ebx
 ; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
 ; i686-NEXT:movl %edi, %esi
-; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; i686-NEXT:movl %eax, %ecx
+; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
 ; i686-NEXT:shll %cl, %esi
 ; i686-NEXT:shldl %cl, %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
 ; i686-NEXT:negl %edx

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[llvm-branch-commits] [clang] b88459a - Revert "[clang][DebugInfo][NFC] Simplify CollectRecordLambdaFields (#160690)"

[via llvm-branch-commits]

Author: Petr Hosek
Date: 2025-09-26T12:19:01-07:00
New Revision: b88459a993fe36f9ac31d8736711ca039394d667

URL: 
https://github.com/llvm/llvm-project/commit/b88459a993fe36f9ac31d8736711ca039394d667
DIFF: 
https://github.com/llvm/llvm-project/commit/b88459a993fe36f9ac31d8736711ca039394d667.diff

LOG: Revert "[clang][DebugInfo][NFC] Simplify CollectRecordLambdaFields 
(#160690)"

This reverts commit 0963cc262708034e41c3ecf412c4597fbec284c5.

Added: 


Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CGDebugInfo.h

Removed: 




diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 68080711c4ace..12c7d48e20d67 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -26,7 +26,6 @@
 #include "clang/AST/DeclObjC.h"
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/Expr.h"
-#include "clang/AST/LambdaCapture.h"
 #include "clang/AST/RecordLayout.h"
 #include "clang/AST/RecursiveASTVisitor.h"
 #include "clang/AST/VTableBuilder.h"
@@ -1904,59 +1903,46 @@ CGDebugInfo::createInlinedSubprogram(StringRef FuncName,
   return SP;
 }
 
-llvm::StringRef
-CGDebugInfo::GetLambdaCaptureName(const LambdaCapture &Capture) {
-  if (Capture.capturesThis())
-return CGM.getCodeGenOpts().EmitCodeView ? "__this" : "this";
-
-  assert(Capture.capturesVariable());
-
-  const ValueDecl *CaptureDecl = Capture.getCapturedVar();
-  assert(CaptureDecl && "Expected valid decl for captured variable.");
-
-  return CaptureDecl->getName();
-}
-
 void CGDebugInfo::CollectRecordLambdaFields(
 const CXXRecordDecl *CXXDecl, SmallVectorImpl &elements,
 llvm::DIType *RecordTy) {
   // For C++11 Lambdas a Field will be the same as a Capture, but the Capture
   // has the name and the location of the variable so we should iterate over
   // both concurrently.
+  const ASTRecordLayout &layout = CGM.getContext().getASTRecordLayout(CXXDecl);
   RecordDecl::field_iterator Field = CXXDecl->field_begin();
   unsigned fieldno = 0;
   for (CXXRecordDecl::capture_const_iterator I = CXXDecl->captures_begin(),
  E = CXXDecl->captures_end();
I != E; ++I, ++Field, ++fieldno) {
-const LambdaCapture &Capture = *I;
-const uint64_t FieldOffset =
-CGM.getContext().getASTRecordLayout(CXXDecl).getFieldOffset(fieldno);
-
-assert(!Field->isBitField() && "lambdas don't have bitfield members!");
-
-SourceLocation Loc;
-uint32_t Align = 0;
-
-if (Capture.capturesThis()) {
+const LambdaCapture &C = *I;
+if (C.capturesVariable()) {
+  SourceLocation Loc = C.getLocation();
+  assert(!Field->isBitField() && "lambdas don't have bitfield members!");
+  ValueDecl *V = C.getCapturedVar();
+  StringRef VName = V->getName();
+  llvm::DIFile *VUnit = getOrCreateFile(Loc);
+  auto Align = getDeclAlignIfRequired(V, CGM.getContext());
+  llvm::DIType *FieldType = createFieldType(
+  VName, Field->getType(), Loc, Field->getAccess(),
+  layout.getFieldOffset(fieldno), Align, VUnit, RecordTy, CXXDecl);
+  elements.push_back(FieldType);
+} else if (C.capturesThis()) {
   // TODO: Need to handle 'this' in some way by probably renaming the
   // this of the lambda class and having a field member of 'this' or
   // by using AT_object_pointer for the function and having that be
   // used as 'this' for semantic references.
-  Loc = Field->getLocation();
-} else {
-  Loc = Capture.getLocation();
-
-  const ValueDecl *CaptureDecl = Capture.getCapturedVar();
-  assert(CaptureDecl && "Expected valid decl for captured variable.");
-
-  Align = getDeclAlignIfRequired(CaptureDecl, CGM.getContext());
+  FieldDecl *f = *Field;
+  llvm::DIFile *VUnit = getOrCreateFile(f->getLocation());
+  QualType type = f->getType();
+  StringRef ThisName =
+  CGM.getCodeGenOpts().EmitCodeView ? "__this" : "this";
+  llvm::DIType *fieldType = createFieldType(
+  ThisName, type, f->getLocation(), f->getAccess(),
+  layout.getFieldOffset(fieldno), VUnit, RecordTy, CXXDecl);
+
+  elements.push_back(fieldType);
 }
-
-llvm::DIFile *VUnit = getOrCreateFile(Loc);
-
-elements.push_back(createFieldType(
-GetLambdaCaptureName(Capture), Field->getType(), Loc,
-Field->getAccess(), FieldOffset, Align, VUnit, RecordTy, CXXDecl));
   }
 }
 

diff  --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 78c3eb9c5792e..f86077369a42a 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -397,7 +397,6 @@ class CGDebugInfo {
   void CollectRecordFields(const RecordDecl *Decl, llvm::DIFile *F,
SmallVectorImpl &E,
llvm::DICompositeType *RecordTy);
-  llvm::StringRef GetLambdaCaptureN

[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156841


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[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156840

>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 288b41bc42203..455de644daf00 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1289,6 +1289,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   // Check if QualType contains a pointer. Implements a simple DFS to
   // recursively check if a type contains a pointer type.
   llvm::SmallPtrSet VisitedRD;
+  bool IncompleteType = false;
   auto TypeContainsPtr = [&](auto &&self, QualType T) -> bool {
 QualType CanonicalType = T.getCanonicalType();
 if (CanonicalType->isPointerType())
@@ -1312,6 +1313,10 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   return self(self, AT->getElementType());
 // The type is a struct, class, or union.
 if (const RecordDecl *RD = CanonicalType->getAsRecordDecl()) {
+  if (!RD->isCompleteDefinition()) {
+IncompleteType = true;
+return false;
+  }
   if (!VisitedRD.insert(RD).second)
 return false; // already visited
   // Check all fields.
@@ -1333,6 +1338,8 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
 return false;
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
+  if (!ContainsPtr && IncompleteType)
+return nullptr;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

>From 7f706618ddc40375d4085bc2ebe03f02ec78823a Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:58:01 +0200
Subject: [PATCH 2/2] fixup!

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 455de644daf00..e7a0e7696e204 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1339,7 +1339,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
   if (!ContainsPtr && IncompleteType)
-return nullptr;
+return;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

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[llvm-branch-commits] [llvm] [AllocToken, Clang] Implement __builtin_infer_alloc_token() and llvm.alloc.token.id (PR #156842)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156842

>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!

Created using spr 1.3.8-beta.1
---
 llvm/lib/Transforms/Instrumentation/AllocToken.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp 
b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
index d5ac3035df71b..3a28705d87523 100644
--- a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
@@ -151,7 +151,8 @@ STATISTIC(NumAllocations, "Allocations found");
 /// Expected format is: !{, }
 MDNode *getAllocTokenHintMetadata(const CallBase &CB) {
   MDNode *Ret = nullptr;
-  if (auto *II = dyn_cast(&CB)) {
+  if (auto *II = dyn_cast(&CB);
+  II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
 auto *MDV = cast(II->getArgOperand(0));
 Ret = cast(MDV->getMetadata());
 // If the intrinsic has an empty MDNode, type inference failed.
@@ -358,7 +359,7 @@ bool AllocToken::instrumentFunction(Function &F) {
   // Collect all allocation calls to avoid iterator invalidation.
   for (Instruction &I : instructions(F)) {
 // Collect all alloc_token_* intrinsics.
-if (IntrinsicInst *II = dyn_cast(&I);
+if (auto *II = dyn_cast(&I);
 II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
   IntrinsicInsts.emplace_back(II);
   continue;

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[llvm-branch-commits] [llvm] Greedy: Use initializer list for recoloring candidates (NFC) (PR #160486)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160486

>From 35d5c37667cfebc6208a2f7d274f85e60675f661 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:14:06 +0900
Subject: [PATCH] Greedy: Use initializer list for recoloring candidates (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6957548ac6c7a..bb8ebe7d7ddf1 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2486,15 +2486,13 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   // We have a broken hint, check if it is possible to fix it by
   // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
   // some register and PhysReg may be available for the other live-ranges.
-  SmallSet Visited;
-  SmallVector RecoloringCandidates;
   HintsInfo Info;
   Register Reg = VirtReg.reg();
   MCRegister PhysReg = VRM->getPhys(Reg);
   // Start the recoloring algorithm from the input live-interval, then
   // it will propagate to the ones that are copy-related with it.
-  Visited.insert(Reg);
-  RecoloringCandidates.push_back(Reg);
+  SmallSet Visited = {Reg};
+  SmallVector RecoloringCandidates = {Reg};
 
   LLVM_DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI)
 << '(' << printReg(PhysReg, TRI) << ")\n");

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[llvm-branch-commits] [llvm] [AArch64][PAC] Cleanup AArch64AsmPrinter::emitPtrauthDiscriminator (NFC) (PR #160900)

[Anatoly Trosinenko via llvm-branch-commits]

https://github.com/atrosinenko created 
https://github.com/llvm/llvm-project/pull/160900

Refactor emitPtrauthDiscriminator function: introduce `isPtrauthRegSafe`
function, update the comments and assertions for readability.

>From 9d7322653d8b992fd40305a06ff9a60435a9a999 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko 
Date: Wed, 24 Sep 2025 19:46:13 +0300
Subject: [PATCH] [AArch64][PAC] Cleanup
 AArch64AsmPrinter::emitPtrauthDiscriminator (NFC)

Refactor emitPtrauthDiscriminator function: introduce `isPtrauthRegSafe`
function, update the comments and assertions for readability.
---
 llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 46 ++-
 1 file changed, 25 insertions(+), 21 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp 
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 1a2808f4d56d8..e7135da17a8d5 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -155,6 +155,13 @@ class AArch64AsmPrinter : public AsmPrinter {
 
   void emitSled(const MachineInstr &MI, SledKind Kind);
 
+  bool isPtrauthRegSafe(Register Reg) const {
+if (STI->isX16X17Safer())
+  return Reg == AArch64::X16 || Reg == AArch64::X17;
+
+return true;
+  }
+
   // Emit the sequence for BRA/BLRA (authenticate + branch/call).
   void emitPtrauthBranch(const MachineInstr *MI);
 
@@ -180,13 +187,15 @@ class AArch64AsmPrinter : public AsmPrinter {
 
   // Emit the sequence to compute the discriminator.
   //
-  // The returned register is either unmodified AddrDisc or ScratchReg.
+  // The Scratch register passed to this function must be safe, see
+  // isPtrauthRegSafe(Reg) function.
+  //
+  // The returned register is either ScratchReg or AddrDisc. Furthermore, it
+  // is safe, unless unsafe AddrDisc was passed-through unmodified.
   //
   // If the expanded pseudo is allowed to clobber AddrDisc register, setting
-  // MayUseAddrAsScratch may save one MOV instruction, provided the address
-  // is already in x16/x17 (i.e. return x16/x17 which is the *modified* 
AddrDisc
-  // register at the same time) or the OS doesn't make it safer to use x16/x17
-  // (see AArch64Subtarget::isX16X17Safer()):
+  // MayUseAddrAsScratch may save one MOV instruction, provided
+  // isPtrauthRegSafe(AddrDisc) is true:
   //
   //   mov   x17, x16
   //   movk  x17, #1234, lsl #48
@@ -195,7 +204,7 @@ class AArch64AsmPrinter : public AsmPrinter {
   // can be replaced by
   //
   //   movk  x16, #1234, lsl #48
-  Register emitPtrauthDiscriminator(uint16_t Disc, Register AddrDisc,
+  Register emitPtrauthDiscriminator(uint64_t Disc, Register AddrDisc,
 Register ScratchReg,
 bool MayUseAddrAsScratch = false);
 
@@ -1902,12 +1911,14 @@ void AArch64AsmPrinter::emitFMov0AsFMov(const 
MachineInstr &MI,
   EmitToStreamer(*OutStreamer, FMov);
 }
 
-Register AArch64AsmPrinter::emitPtrauthDiscriminator(uint16_t Disc,
+Register AArch64AsmPrinter::emitPtrauthDiscriminator(uint64_t Disc,
  Register AddrDisc,
  Register ScratchReg,
  bool MayUseAddrAsScratch) 
{
-  assert(ScratchReg == AArch64::X16 || ScratchReg == AArch64::X17 ||
- !STI->isX16X17Safer());
+  assert(isPtrauthRegSafe(ScratchReg) &&
+ "Safe scratch register must be provided by the caller");
+  assert(isUInt<16>(Disc) && "Constant discriminator is too wide");
+
   // So far we've used NoRegister in pseudos.  Now we need real encodings.
   if (AddrDisc == AArch64::NoRegister)
 AddrDisc = AArch64::XZR;
@@ -1926,13 +1937,13 @@ Register 
AArch64AsmPrinter::emitPtrauthDiscriminator(uint16_t Disc,
   // If there are both, emit a blend into the scratch register.
 
   // Check if we can save one MOV instruction.
-  assert(MayUseAddrAsScratch || ScratchReg != AddrDisc);
-  bool AddrDiscIsSafe = AddrDisc == AArch64::X16 || AddrDisc == AArch64::X17 ||
-!STI->isX16X17Safer();
-  if (MayUseAddrAsScratch && AddrDiscIsSafe)
+  if (MayUseAddrAsScratch && isPtrauthRegSafe(AddrDisc)) {
 ScratchReg = AddrDisc;
-  else
+  } else {
 emitMovXReg(ScratchReg, AddrDisc);
+assert(ScratchReg != AddrDisc &&
+   "Forbidden to clobber AddrDisc, but have to");
+  }
 
   emitMOVK(ScratchReg, Disc, 48);
   return ScratchReg;
@@ -2151,7 +2162,6 @@ void AArch64AsmPrinter::emitPtrauthAuthResign(
   }
 
   // Compute aut discriminator
-  assert(isUInt<16>(AUTDisc));
   Register AUTDiscReg = emitPtrauthDiscriminator(
   AUTDisc, AUTAddrDisc->getReg(), Scratch, AUTAddrDisc->isKill());
   bool AUTZero = AUTDiscReg == AArch64::XZR;
@@ -2188,7 +2198,6 @@ void AArch64AsmPrinter::emitPtrauthAuthResign(
 return;
 
   // Compute pac discriminator
-  assert(isUInt<16>(PACDisc));
   Register PACDiscReg =
   emitPtrauthDiscriminator(PACDisc, PA

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Fix artificially-failing `preserve-branchweights.ll` (PR #160629)

[Mircea Trofin via llvm-branch-commits]

https://github.com/mtrofin converted_to_draft 
https://github.com/llvm/llvm-project/pull/160629
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[llvm-branch-commits] [clang] [clang] fix transformation of subst constant template parameter nodes (PR #160777)

[Matheus Izvekov via llvm-branch-commits]

https://github.com/mizvekov updated 
https://github.com/llvm/llvm-project/pull/160777

>From 1160542a693e22cc81c719e371d1b6282ecc3800 Mon Sep 17 00:00:00 2001
From: Matheus Izvekov 
Date: Wed, 24 Sep 2025 17:18:41 -0300
Subject: [PATCH] [clang] fix transformation of subst constant template
 parameter nodes

This simplifies those transforms a lot, removing a bunch of workarounds
which were introducing problems.

The transforms become independent of the template instantiator, so
they are moved to TreeTransform instead.

Fixes #131342
---
 clang/docs/ReleaseNotes.rst   |   1 +
 clang/include/clang/AST/ExprCXX.h |   2 +-
 clang/include/clang/AST/TypeBase.h|   4 +-
 clang/include/clang/Sema/Sema.h   |  17 ++
 clang/lib/AST/ExprCXX.cpp |   4 +-
 clang/lib/AST/StmtProfile.cpp |   3 +-
 clang/lib/Sema/SemaTemplate.cpp   |  34 +++
 clang/lib/Sema/SemaTemplateInstantiate.cpp| 203 ++
 .../lib/Sema/SemaTemplateInstantiateDecl.cpp  |  23 +-
 clang/lib/Sema/TreeTransform.h|  72 +--
 clang/test/SemaCXX/ctad.cpp   |   7 +
 clang/test/SemaCXX/cxx20-ctad-type-alias.cpp  |   2 +-
 .../SemaTemplate/temp_arg_nontype_cxx2c.cpp   |  11 +
 13 files changed, 168 insertions(+), 215 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 703fe2ab35af3..99ca301f54a57 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -361,6 +361,7 @@ Bug Fixes in This Version
   first parameter. (#GH113323).
 - Fixed a crash with incompatible pointer to integer conversions in designated
   initializers involving string literals. (#GH154046)
+- Fix crash on CTAD for alias template. (#GH131342)
 - Clang now emits a frontend error when a function marked with the `flatten` 
attribute
   calls another function that requires target features not enabled in the 
caller. This
   prevents a fatal error in the backend.
diff --git a/clang/include/clang/AST/ExprCXX.h 
b/clang/include/clang/AST/ExprCXX.h
index 9fedb230ce397..5f16bac94d5e6 100644
--- a/clang/include/clang/AST/ExprCXX.h
+++ b/clang/include/clang/AST/ExprCXX.h
@@ -4714,7 +4714,7 @@ class SubstNonTypeTemplateParmExpr : public Expr {
   // sugared: it doesn't need to be resugared later.
   bool getFinal() const { return Final; }
 
-  NamedDecl *getParameter() const;
+  NonTypeTemplateParmDecl *getParameter() const;
 
   bool isReferenceParameter() const { return AssociatedDeclAndRef.getInt(); }
 
diff --git a/clang/include/clang/AST/TypeBase.h 
b/clang/include/clang/AST/TypeBase.h
index b02d9c7499fe5..e0d00b82f2b76 100644
--- a/clang/include/clang/AST/TypeBase.h
+++ b/clang/include/clang/AST/TypeBase.h
@@ -3495,7 +3495,9 @@ class AdjustedType : public Type, public 
llvm::FoldingSetNode {
 
   AdjustedType(TypeClass TC, QualType OriginalTy, QualType AdjustedTy,
QualType CanonicalPtr)
-  : Type(TC, CanonicalPtr, OriginalTy->getDependence()),
+  : Type(TC, CanonicalPtr,
+ AdjustedTy->getDependence() |
+ (OriginalTy->getDependence() & ~TypeDependence::Dependent)),
 OriginalTy(OriginalTy), AdjustedTy(AdjustedTy) {}
 
 public:
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 5edfc29d93781..2bd6be2a32cd5 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -11714,6 +11714,23 @@ class Sema final : public SemaBase {
const TemplateArgumentListInfo *TemplateArgs,
bool IsAddressOfOperand);
 
+  UnsignedOrNone getPackIndex(TemplateArgument Pack) const {
+return Pack.pack_size() - 1 - *ArgPackSubstIndex;
+  }
+
+  TemplateArgument
+  getPackSubstitutedTemplateArgument(TemplateArgument Arg) const {
+Arg = Arg.pack_elements()[*ArgPackSubstIndex];
+if (Arg.isPackExpansion())
+  Arg = Arg.getPackExpansionPattern();
+return Arg;
+  }
+
+  ExprResult BuildSubstNonTypeTemplateParmExpr(
+  Decl *AssociatedDecl, const NonTypeTemplateParmDecl *NTTP,
+  SourceLocation loc, TemplateArgument Replacement,
+  UnsignedOrNone PackIndex, bool Final);
+
   /// Form a template name from a name that is syntactically required to name a
   /// template, either due to use of the 'template' keyword or because a name 
in
   /// this syntactic context is assumed to name a template (C++
diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp
index 97ae4a07f32aa..95de6a82a5270 100644
--- a/clang/lib/AST/ExprCXX.cpp
+++ b/clang/lib/AST/ExprCXX.cpp
@@ -1725,8 +1725,8 @@ SizeOfPackExpr 
*SizeOfPackExpr::CreateDeserialized(ASTContext &Context,
   return new (Storage) SizeOfPackExpr(EmptyShell(), NumPartialArgs);
 }
 
-NamedDecl *SubstNonTypeTemplateParmExpr::getParameter() const {
-  return cast(
+NonTypeTemplateParmDecl *SubstNonTypeTemplateParmExpr::getParameter() const {
+  return cast(
   getRe

[llvm-branch-commits] [llvm] Greedy: Merge VirtRegMap queries into one use (NFC) (PR #160485)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160485

>From b049f4ae5a64c12116b44dd35065e30983965f51 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:06:39 +0900
Subject: [PATCH] Greedy: Merge VirtRegMap queries into one use (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index dc23ab3ce9d2b..6957548ac6c7a 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,8 +2502,10 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
+MCRegister CurrPhys = VRM->getPhys(Reg);
+
 // This may be a skipped register.
-if (!VRM->hasPhys(Reg)) {
+if (!CurrPhys) {
   assert(!shouldAllocateRegister(Reg) &&
  "We have an unallocated variable which should have been handled");
   continue;
@@ -2512,7 +2514,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Get the live interval mapped with this virtual register to be able
 // to check for the interference with the new color.
 LiveInterval &LI = LIS->getInterval(Reg);
-MCRegister CurrPhys = VRM->getPhys(Reg);
 // Check that the new color matches the register class constraints and
 // that it is free for this live range.
 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||

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[llvm-branch-commits] [llvm] Greedy: Move physreg check when trying to recolor vregs (NFC) (PR #160484)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160484

>From 5e1d9bbb70573ae0dba49769638b977895f4385e Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:02:49 +0900
Subject: [PATCH] Greedy: Move physreg check when trying to recolor vregs (NFC)

Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..dc23ab3ce9d2b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,10 +2502,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
-// We cannot recolor physical register.
-if (Reg.isPhysical())
-  continue;
-
 // This may be a skipped register.
 if (!VRM->hasPhys(Reg)) {
   assert(!shouldAllocateRegister(Reg) &&
@@ -2553,7 +2549,8 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Push all copy-related live-ranges to keep reconciling the broken
 // hints.
 for (const HintInfo &HI : Info) {
-  if (Visited.insert(HI.Reg).second)
+  // We cannot recolor physical register.
+  if (HI.Reg.isVirtual() && Visited.insert(HI.Reg).second)
 RecoloringCandidates.push_back(HI.Reg);
 }
   } while (!RecoloringCandidates.empty());

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[llvm-branch-commits] [clang] [llvm] [DirectX] Updating Root Signature Metadata to contain Static Sampler flags (PR #160210)

[Justin Bogner via llvm-branch-commits]

@@ -212,7 +212,7 @@ MDNode *MetadataBuilder::BuildStaticSampler(const 
StaticSampler &Sampler) {
   ConstantAsMetadata::get(Builder.getInt32(Sampler.Space)),
   ConstantAsMetadata::get(
   Builder.getInt32(to_underlying(Sampler.Visibility))),
-  };
+  ConstantAsMetadata::get(Builder.getInt32(0))};

bogner wrote:

There are a few ways to stage this, but I agree that if we're doing either the 
backend or the frontend first we run into similar problems. However, I do share 
@inbelic's concern that this is a bit of an awkward temporary state.

It might be worthwhile to just wire up enough of the frontend in this PR that 
it's explicitly writing out the empty flags. That is, update the [StaticSampler 
definition](https://github.com/joaosaffran/llvm-project/blob/main/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h#L120)
 to include the flags now, but just initialize it to zero in the frontend. This 
way the metadata stays consistent between the frontend and the backend.

https://github.com/llvm/llvm-project/pull/160210
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[llvm-branch-commits] [llvm] Revert "[DirectX] Validating Root flags are denying shader stage" (PR #160917)

[via llvm-branch-commits]

https://github.com/joaosaffran created 
https://github.com/llvm/llvm-project/pull/160917

Reverts llvm/llvm-project#153287

>From ac34c5a7f113faf0cb8e1e05aea939a603b3412a Mon Sep 17 00:00:00 2001
From: joaosaffran 
Date: Fri, 26 Sep 2025 12:00:50 -0400
Subject: [PATCH] Revert "[DirectX] Validating Root flags are denying shader
 stage (#153287)"

This reverts commit d7dd8f0317b789333aac2569921188a59ff6cef9.
---
 .../DXILPostOptimizationValidation.cpp| 72 ---
 ...ootsignature-validation-deny-no-binding.ll | 17 -
 ...re-validation-fail-deny-multiple-shader.ll | 20 --
 ...re-validation-fail-deny-root-descriptor.ll | 20 --
 ...ture-validation-fail-deny-single-shader.ll | 19 -
 ...tsignature-validation-not-dening-shader.ll | 21 --
 6 files changed, 12 insertions(+), 157 deletions(-)
 delete mode 100644 
llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll
 delete mode 100644 
llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-multiple-shader.ll
 delete mode 100644 
llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-root-descriptor.ll
 delete mode 100644 
llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-single-shader.ll
 delete mode 100644 
llvm/test/CodeGen/DirectX/rootsignature-validation-not-dening-shader.ll

diff --git a/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp 
b/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
index 6e95a4232fabe..7e93474e73118 100644
--- a/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
+++ b/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
@@ -160,41 +160,6 @@ tripleToVisibility(llvm::Triple::EnvironmentType ET) {
   }
 }
 
-static void reportIfDeniedShaderStageAccess(Module &M,
-const dxbc::RootFlags &Flags,
-const dxbc::RootFlags &Mask) {
-  if ((Flags & Mask) != Mask)
-return;
-
-  SmallString<128> Message;
-  raw_svector_ostream OS(Message);
-  OS << "Shader has root bindings but root signature uses a DENY flag to "
-"disallow root binding access to the shader stage.";
-  M.getContext().diagnose(DiagnosticInfoGeneric(Message));
-}
-
-static std::optional
-getEnvironmentDenyFlagMask(Triple::EnvironmentType ShaderProfile) {
-  switch (ShaderProfile) {
-  case Triple::Pixel:
-return dxbc::RootFlags::DenyPixelShaderRootAccess;
-  case Triple::Vertex:
-return dxbc::RootFlags::DenyVertexShaderRootAccess;
-  case Triple::Geometry:
-return dxbc::RootFlags::DenyGeometryShaderRootAccess;
-  case Triple::Hull:
-return dxbc::RootFlags::DenyHullShaderRootAccess;
-  case Triple::Domain:
-return dxbc::RootFlags::DenyDomainShaderRootAccess;
-  case Triple::Mesh:
-return dxbc::RootFlags::DenyMeshShaderRootAccess;
-  case Triple::Amplification:
-return dxbc::RootFlags::DenyAmplificationShaderRootAccess;
-  default:
-return std::nullopt;
-  }
-}
-
 static void validateRootSignature(Module &M,
   const mcdxbc::RootSignatureDesc &RSD,
   dxil::ModuleMetadataInfo &MMI,
@@ -260,9 +225,7 @@ static void validateRootSignature(Module &M,
 Builder.findOverlapping(ReportedBinding);
 reportOverlappingRegisters(M, ReportedBinding, Overlaping);
   });
-
   const hlsl::BoundRegs &BoundRegs = Builder.takeBoundRegs();
-  bool HasBindings = false;
   for (const ResourceInfo &RI : DRM) {
 const ResourceInfo::ResourceBinding &Binding = RI.getBinding();
 const dxil::ResourceTypeInfo &RTI = DRTM[RI.getHandleTy()];
@@ -273,33 +236,22 @@ static void validateRootSignature(Module &M,
 BoundRegs.findBoundReg(RC, Binding.Space, Binding.LowerBound,
Binding.LowerBound + Binding.Size - 1);
 
-if (!Reg) {
-  reportRegNotBound(M, RC, Binding);
-  continue;
-}
+if (Reg != nullptr) {
+  const auto *ParamInfo =
+  static_cast(Reg->Cookie);
+
+  if (RC != ResourceClass::SRV && RC != ResourceClass::UAV)
+continue;
 
-const auto *ParamInfo =
-static_cast(Reg->Cookie);
+  if (ParamInfo->Type == dxbc::RootParameterType::DescriptorTable)
+continue;
 
-bool IsSRVOrUAV = RC == ResourceClass::SRV || RC == ResourceClass::UAV;
-bool IsDescriptorTable =
-ParamInfo->Type == dxbc::RootParameterType::DescriptorTable;
-bool IsRawOrStructuredBuffer =
-RK != ResourceKind::RawBuffer && RK != ResourceKind::StructuredBuffer;
-if (IsSRVOrUAV && !IsDescriptorTable && IsRawOrStructuredBuffer) {
-  reportInvalidHandleTyError(M, RC, Binding);
-  continue;
+  if (RK != ResourceKind::RawBuffer && RK != 
ResourceKind::StructuredBuffer)
+reportInvalidHandleTyError(M, RC, Binding);
+} else {
+  reportRegNotBound(M, RC, Binding);
 }
-
-HasBindings = true;
   }
-
-  if (!HasBindings)
-return;
-
-  if (std::optional Mask =
-  

[llvm-branch-commits] [llvm] Revert "[DirectX] Validating Root flags are denying shader stage" (PR #160917)

[via llvm-branch-commits]

https://github.com/joaosaffran closed 
https://github.com/llvm/llvm-project/pull/160917
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[llvm-branch-commits] [llvm] [DirectX] Validating Root flags are denying shader stage (PR #153287)

[via llvm-branch-commits]

https://github.com/joaosaffran closed 
https://github.com/llvm/llvm-project/pull/153287
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[llvm-branch-commits] [clang] [clang] simplify placeholder type deduction for constant template parameters (PR #160439)

[Matheus Izvekov via llvm-branch-commits]

mizvekov wrote:

> Give others some time with this, but I think we need to do a better job with 
> figuring out what that diagnostic is trying to say, vs leaving empty quotes.

Yes, pre-existing, the file is riddled with those. It's just that the template 
parameters are anonymous, it's not a thing super likely in user code.

https://github.com/llvm/llvm-project/pull/160439
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sam Tebbs via llvm-branch-commits]

https://github.com/SamTebbs33 updated 
https://github.com/llvm/llvm-project/pull/160154

>From 1e26f885620a00e9733102c36dd626552cb9dda5 Mon Sep 17 00:00:00 2001
From: Sam Tebbs 
Date: Mon, 22 Sep 2025 17:16:40 +0100
Subject: [PATCH 1/7] [LV] Add ExtNegatedMulAccReduction expression type

This PR adds the ExtNegatedMulAccReduction expression type for
VPExpressionRecipe so that extend-multiply-accumulate reductions with a
negated multiply can be bundled.

Stacked PRs:

1. https://github.com/llvm/llvm-project/pull/156976
2. -> This
3. https://github.com/llvm/llvm-project/pull/147302
---
 llvm/lib/Transforms/Vectorize/VPlan.h |  11 ++
 .../lib/Transforms/Vectorize/VPlanRecipes.cpp |  31 -
 .../Transforms/Vectorize/VPlanTransforms.cpp  |  46 ---
 .../vplan-printing-reductions.ll  | 121 ++
 4 files changed, 192 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h 
b/llvm/lib/Transforms/Vectorize/VPlan.h
index e6f6067bc9df3..1cb0c889528ec 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -2989,6 +2989,12 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
 /// vector operands, performing a reduction.add on the result, and adding
 /// the scalar result to a chain.
 MulAccReduction,
+/// Represent an inloop multiply-accumulate reduction, multiplying the
+/// extended vector operands, negating the multiplication, performing a
+/// reduction.add
+/// on the result, and adding
+/// the scalar result to a chain.
+ExtNegatedMulAccReduction,
   };
 
   /// Type of the expression.
@@ -3012,6 +3018,11 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
  VPWidenRecipe *Mul, VPReductionRecipe *Red)
   : VPExpressionRecipe(ExpressionTypes::ExtMulAccReduction,
{Ext0, Ext1, Mul, Red}) {}
+  VPExpressionRecipe(VPWidenCastRecipe *Ext0, VPWidenCastRecipe *Ext1,
+ VPWidenRecipe *Mul, VPWidenRecipe *Sub,
+ VPReductionRecipe *Red)
+  : VPExpressionRecipe(ExpressionTypes::ExtNegatedMulAccReduction,
+   {Ext0, Ext1, Mul, Sub, Red}) {}
 
   ~VPExpressionRecipe() override {
 SmallSet ExpressionRecipesSeen;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp 
b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 4568d4f37a751..02be0db102547 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2861,12 +2861,17 @@ InstructionCost 
VPExpressionRecipe::computeCost(ElementCount VF,
 return Ctx.TTI.getMulAccReductionCost(false, Opcode, RedTy, SrcVecTy,
   Ctx.CostKind);
 
-  case ExpressionTypes::ExtMulAccReduction:
+  case ExpressionTypes::ExtNegatedMulAccReduction:
+  case ExpressionTypes::ExtMulAccReduction: {
+if (ExpressionType == ExpressionTypes::ExtNegatedMulAccReduction &&
+Opcode == Instruction::Add)
+  Opcode = Instruction::Sub;
 return Ctx.TTI.getMulAccReductionCost(
 cast(ExpressionRecipes.front())->getOpcode() ==
 Instruction::ZExt,
 Opcode, RedTy, SrcVecTy, Ctx.CostKind);
   }
+  }
   llvm_unreachable("Unknown VPExpressionRecipe::ExpressionTypes enum");
 }
 
@@ -2912,6 +2917,30 @@ void VPExpressionRecipe::print(raw_ostream &O, const 
Twine &Indent,
 O << ")";
 break;
   }
+  case ExpressionTypes::ExtNegatedMulAccReduction: {
+getOperand(getNumOperands() - 1)->printAsOperand(O, SlotTracker);
+O << " + reduce."
+  << Instruction::getOpcodeName(
+ RecurrenceDescriptor::getOpcode(Red->getRecurrenceKind()))
+  << " (sub (0, mul";
+auto *Mul = cast(ExpressionRecipes[2]);
+Mul->printFlags(O);
+O << "(";
+getOperand(0)->printAsOperand(O, SlotTracker);
+auto *Ext0 = cast(ExpressionRecipes[0]);
+O << " " << Instruction::getOpcodeName(Ext0->getOpcode()) << " to "
+  << *Ext0->getResultType() << "), (";
+getOperand(1)->printAsOperand(O, SlotTracker);
+auto *Ext1 = cast(ExpressionRecipes[1]);
+O << " " << Instruction::getOpcodeName(Ext1->getOpcode()) << " to "
+  << *Ext1->getResultType() << ")";
+if (Red->isConditional()) {
+  O << ", ";
+  Red->getCondOp()->printAsOperand(O, SlotTracker);
+}
+O << "))";
+break;
+  }
   case ExpressionTypes::MulAccReduction:
   case ExpressionTypes::ExtMulAccReduction: {
 getOperand(getNumOperands() - 1)->printAsOperand(O, SlotTracker);
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp 
b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 1f6b85270607e..ca89c4fa0d2e6 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -3524,14 +3524,22 @@ 
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
   };
 
   VPValue *VecOp = Red->getVecOp();
+  VPValue *Mul = 

[llvm-branch-commits] [llvm] Revert "[DirectX] Validating Root flags are denying shader stage" (PR #160917)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-directx

Author: None (joaosaffran)


Changes

Reverts llvm/llvm-project#153287

---
Full diff: https://github.com/llvm/llvm-project/pull/160917.diff


6 Files Affected:

- (modified) llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp 
(+12-60) 
- (removed) 
llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll (-17) 
- (removed) 
llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-multiple-shader.ll 
(-20) 
- (removed) 
llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-root-descriptor.ll 
(-20) 
- (removed) 
llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-single-shader.ll 
(-19) 
- (removed) 
llvm/test/CodeGen/DirectX/rootsignature-validation-not-dening-shader.ll (-21) 


``diff
diff --git a/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp 
b/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
index 6e95a4232fabe..7e93474e73118 100644
--- a/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
+++ b/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
@@ -160,41 +160,6 @@ tripleToVisibility(llvm::Triple::EnvironmentType ET) {
   }
 }
 
-static void reportIfDeniedShaderStageAccess(Module &M,
-const dxbc::RootFlags &Flags,
-const dxbc::RootFlags &Mask) {
-  if ((Flags & Mask) != Mask)
-return;
-
-  SmallString<128> Message;
-  raw_svector_ostream OS(Message);
-  OS << "Shader has root bindings but root signature uses a DENY flag to "
-"disallow root binding access to the shader stage.";
-  M.getContext().diagnose(DiagnosticInfoGeneric(Message));
-}
-
-static std::optional
-getEnvironmentDenyFlagMask(Triple::EnvironmentType ShaderProfile) {
-  switch (ShaderProfile) {
-  case Triple::Pixel:
-return dxbc::RootFlags::DenyPixelShaderRootAccess;
-  case Triple::Vertex:
-return dxbc::RootFlags::DenyVertexShaderRootAccess;
-  case Triple::Geometry:
-return dxbc::RootFlags::DenyGeometryShaderRootAccess;
-  case Triple::Hull:
-return dxbc::RootFlags::DenyHullShaderRootAccess;
-  case Triple::Domain:
-return dxbc::RootFlags::DenyDomainShaderRootAccess;
-  case Triple::Mesh:
-return dxbc::RootFlags::DenyMeshShaderRootAccess;
-  case Triple::Amplification:
-return dxbc::RootFlags::DenyAmplificationShaderRootAccess;
-  default:
-return std::nullopt;
-  }
-}
-
 static void validateRootSignature(Module &M,
   const mcdxbc::RootSignatureDesc &RSD,
   dxil::ModuleMetadataInfo &MMI,
@@ -260,9 +225,7 @@ static void validateRootSignature(Module &M,
 Builder.findOverlapping(ReportedBinding);
 reportOverlappingRegisters(M, ReportedBinding, Overlaping);
   });
-
   const hlsl::BoundRegs &BoundRegs = Builder.takeBoundRegs();
-  bool HasBindings = false;
   for (const ResourceInfo &RI : DRM) {
 const ResourceInfo::ResourceBinding &Binding = RI.getBinding();
 const dxil::ResourceTypeInfo &RTI = DRTM[RI.getHandleTy()];
@@ -273,33 +236,22 @@ static void validateRootSignature(Module &M,
 BoundRegs.findBoundReg(RC, Binding.Space, Binding.LowerBound,
Binding.LowerBound + Binding.Size - 1);
 
-if (!Reg) {
-  reportRegNotBound(M, RC, Binding);
-  continue;
-}
+if (Reg != nullptr) {
+  const auto *ParamInfo =
+  static_cast(Reg->Cookie);
+
+  if (RC != ResourceClass::SRV && RC != ResourceClass::UAV)
+continue;
 
-const auto *ParamInfo =
-static_cast(Reg->Cookie);
+  if (ParamInfo->Type == dxbc::RootParameterType::DescriptorTable)
+continue;
 
-bool IsSRVOrUAV = RC == ResourceClass::SRV || RC == ResourceClass::UAV;
-bool IsDescriptorTable =
-ParamInfo->Type == dxbc::RootParameterType::DescriptorTable;
-bool IsRawOrStructuredBuffer =
-RK != ResourceKind::RawBuffer && RK != ResourceKind::StructuredBuffer;
-if (IsSRVOrUAV && !IsDescriptorTable && IsRawOrStructuredBuffer) {
-  reportInvalidHandleTyError(M, RC, Binding);
-  continue;
+  if (RK != ResourceKind::RawBuffer && RK != 
ResourceKind::StructuredBuffer)
+reportInvalidHandleTyError(M, RC, Binding);
+} else {
+  reportRegNotBound(M, RC, Binding);
 }
-
-HasBindings = true;
   }
-
-  if (!HasBindings)
-return;
-
-  if (std::optional Mask =
-  getEnvironmentDenyFlagMask(MMI.ShaderProfile))
-reportIfDeniedShaderStageAccess(M, dxbc::RootFlags(RSD.Flags), *Mask);
 }
 
 static mcdxbc::RootSignatureDesc *
diff --git 
a/llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll 
b/llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll
deleted file mode 100644
index 15326d438f021..0
--- a/llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: opt -S -passes='

[llvm-branch-commits] [llvm] Greedy: Use initializer list for recoloring candidates (NFC) (PR #160486)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160486

>From 757179588b9274b1a7ce65885d6ce7b9f79db150 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:14:06 +0900
Subject: [PATCH] Greedy: Use initializer list for recoloring candidates (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6957548ac6c7a..bb8ebe7d7ddf1 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2486,15 +2486,13 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   // We have a broken hint, check if it is possible to fix it by
   // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
   // some register and PhysReg may be available for the other live-ranges.
-  SmallSet Visited;
-  SmallVector RecoloringCandidates;
   HintsInfo Info;
   Register Reg = VirtReg.reg();
   MCRegister PhysReg = VRM->getPhys(Reg);
   // Start the recoloring algorithm from the input live-interval, then
   // it will propagate to the ones that are copy-related with it.
-  Visited.insert(Reg);
-  RecoloringCandidates.push_back(Reg);
+  SmallSet Visited = {Reg};
+  SmallVector RecoloringCandidates = {Reg};
 
   LLVM_DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI)
 << '(' << printReg(PhysReg, TRI) << ")\n");

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[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

[via llvm-branch-commits]

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- 
llvm/lib/CodeGen/RegAllocGreedy.cpp llvm/lib/CodeGen/RegAllocGreedy.h
``

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:





View the diff from clang-format here.


``diff
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 9d3165b79..7414ba32b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2464,7 +2464,8 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 const TargetRegisterClass *OtherRC = MRI->getRegClass(OtherReg);
 unsigned FullRegCopyCost = OtherRC->getCopyCost();
 
-const TargetRegisterClass *OtherSubRC = 
TRI->getSubRegisterClass(OtherRC, OtherSubReg);
+const TargetRegisterClass *OtherSubRC =
+TRI->getSubRegisterClass(OtherRC, OtherSubReg);
 unsigned SubRegCopyCost = OtherSubRC->getCopyCost();
 
 BranchProbability Scaling(SubRegCopyCost, FullRegCopyCost);
@@ -2476,11 +2477,9 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 
 BranchProbability Scaling(SubRegCopyCost, FullRegCopyCost);
 Freq *= Scaling;
-
   }
 
-  Out.push_back(HintInfo(Freq, OtherReg,
- OtherPhysReg));
+  Out.push_back(HintInfo(Freq, OtherReg, OtherPhysReg));
 }
   }
 }
@@ -2498,7 +2497,6 @@ BlockFrequency RAGreedy::getBrokenHintFreq(const 
HintsInfo &List,
   continue;
 }
 
-
 if (Info.PhysReg != PhysReg)
   Cost += Info.Freq;
   }
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h 
b/llvm/lib/CodeGen/RegAllocGreedy.h
index e0bb26e63..1e711f7db 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -395,13 +395,12 @@ private:
 MCRegister PhysReg;
 
 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg)
-  : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
+: Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
 
-HintInfo(BlockFrequency Freq,
- Register Reg, unsigned SubReg,
+HintInfo(BlockFrequency Freq, Register Reg, unsigned SubReg,
  Register HintReg, unsigned HintSubReg)
-  : Freq(Freq), Reg(Reg), SubReg(SubReg),
-  HintReg(HintReg), HintSubReg(HintSubReg) {}
+: Freq(Freq), Reg(Reg), SubReg(SubReg), HintReg(HintReg),
+  HintSubReg(HintSubReg) {}
   };
   using HintsInfo = SmallVector;
 

``




https://github.com/llvm/llvm-project/pull/160467
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sander de Smalen via llvm-branch-commits]

https://github.com/sdesmalen-arm approved this pull request.

LGTM with nits addressed

https://github.com/llvm/llvm-project/pull/160154
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sander de Smalen via llvm-branch-commits]

@@ -3524,7 +3524,13 @@ 
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
   };
 
   VPValue *VecOp = Red->getVecOp();
+  VPValue *Sub = nullptr;
   VPValue *A, *B;
+  // Sub reductions could have a sub between the add reduction and vec op.
+  if (match(VecOp, m_Binary(m_SpecificInt(0), m_VPValue( 
{

sdesmalen-arm wrote:

just a minor nit: is it worth creating a `VPValue *Tmp`, and matching 
`m_VPValue(Tmp)`, and then doing `VecOp = Tmp;` rather than getting operand 1 
from the defining recipe?

https://github.com/llvm/llvm-project/pull/160154
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sander de Smalen via llvm-branch-commits]

@@ -3524,7 +3524,13 @@ 
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
   };
 
   VPValue *VecOp = Red->getVecOp();
+  VPValue *Sub = nullptr;

sdesmalen-arm wrote:

nit: Is it worth making `Sub` a `VPRecipeBase`? (since that's the only use-case 
of it)

https://github.com/llvm/llvm-project/pull/160154
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[llvm-branch-commits] [llvm] ac34c5a - Revert "[DirectX] Validating Root flags are denying shader stage (#153287)"

[via llvm-branch-commits]

Author: joaosaffran
Date: 2025-09-26T12:00:50-04:00
New Revision: ac34c5a7f113faf0cb8e1e05aea939a603b3412a

URL: 
https://github.com/llvm/llvm-project/commit/ac34c5a7f113faf0cb8e1e05aea939a603b3412a
DIFF: 
https://github.com/llvm/llvm-project/commit/ac34c5a7f113faf0cb8e1e05aea939a603b3412a.diff

LOG: Revert "[DirectX] Validating Root flags are denying shader stage (#153287)"

This reverts commit d7dd8f0317b789333aac2569921188a59ff6cef9.

Added: 


Modified: 
llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp

Removed: 
llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll

llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-multiple-shader.ll

llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-root-descriptor.ll

llvm/test/CodeGen/DirectX/rootsignature-validation-fail-deny-single-shader.ll
llvm/test/CodeGen/DirectX/rootsignature-validation-not-dening-shader.ll



diff  --git a/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp 
b/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
index 6e95a4232fabe..7e93474e73118 100644
--- a/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
+++ b/llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp
@@ -160,41 +160,6 @@ tripleToVisibility(llvm::Triple::EnvironmentType ET) {
   }
 }
 
-static void reportIfDeniedShaderStageAccess(Module &M,
-const dxbc::RootFlags &Flags,
-const dxbc::RootFlags &Mask) {
-  if ((Flags & Mask) != Mask)
-return;
-
-  SmallString<128> Message;
-  raw_svector_ostream OS(Message);
-  OS << "Shader has root bindings but root signature uses a DENY flag to "
-"disallow root binding access to the shader stage.";
-  M.getContext().diagnose(DiagnosticInfoGeneric(Message));
-}
-
-static std::optional
-getEnvironmentDenyFlagMask(Triple::EnvironmentType ShaderProfile) {
-  switch (ShaderProfile) {
-  case Triple::Pixel:
-return dxbc::RootFlags::DenyPixelShaderRootAccess;
-  case Triple::Vertex:
-return dxbc::RootFlags::DenyVertexShaderRootAccess;
-  case Triple::Geometry:
-return dxbc::RootFlags::DenyGeometryShaderRootAccess;
-  case Triple::Hull:
-return dxbc::RootFlags::DenyHullShaderRootAccess;
-  case Triple::Domain:
-return dxbc::RootFlags::DenyDomainShaderRootAccess;
-  case Triple::Mesh:
-return dxbc::RootFlags::DenyMeshShaderRootAccess;
-  case Triple::Amplification:
-return dxbc::RootFlags::DenyAmplificationShaderRootAccess;
-  default:
-return std::nullopt;
-  }
-}
-
 static void validateRootSignature(Module &M,
   const mcdxbc::RootSignatureDesc &RSD,
   dxil::ModuleMetadataInfo &MMI,
@@ -260,9 +225,7 @@ static void validateRootSignature(Module &M,
 Builder.findOverlapping(ReportedBinding);
 reportOverlappingRegisters(M, ReportedBinding, Overlaping);
   });
-
   const hlsl::BoundRegs &BoundRegs = Builder.takeBoundRegs();
-  bool HasBindings = false;
   for (const ResourceInfo &RI : DRM) {
 const ResourceInfo::ResourceBinding &Binding = RI.getBinding();
 const dxil::ResourceTypeInfo &RTI = DRTM[RI.getHandleTy()];
@@ -273,33 +236,22 @@ static void validateRootSignature(Module &M,
 BoundRegs.findBoundReg(RC, Binding.Space, Binding.LowerBound,
Binding.LowerBound + Binding.Size - 1);
 
-if (!Reg) {
-  reportRegNotBound(M, RC, Binding);
-  continue;
-}
+if (Reg != nullptr) {
+  const auto *ParamInfo =
+  static_cast(Reg->Cookie);
+
+  if (RC != ResourceClass::SRV && RC != ResourceClass::UAV)
+continue;
 
-const auto *ParamInfo =
-static_cast(Reg->Cookie);
+  if (ParamInfo->Type == dxbc::RootParameterType::DescriptorTable)
+continue;
 
-bool IsSRVOrUAV = RC == ResourceClass::SRV || RC == ResourceClass::UAV;
-bool IsDescriptorTable =
-ParamInfo->Type == dxbc::RootParameterType::DescriptorTable;
-bool IsRawOrStructuredBuffer =
-RK != ResourceKind::RawBuffer && RK != ResourceKind::StructuredBuffer;
-if (IsSRVOrUAV && !IsDescriptorTable && IsRawOrStructuredBuffer) {
-  reportInvalidHandleTyError(M, RC, Binding);
-  continue;
+  if (RK != ResourceKind::RawBuffer && RK != 
ResourceKind::StructuredBuffer)
+reportInvalidHandleTyError(M, RC, Binding);
+} else {
+  reportRegNotBound(M, RC, Binding);
 }
-
-HasBindings = true;
   }
-
-  if (!HasBindings)
-return;
-
-  if (std::optional Mask =
-  getEnvironmentDenyFlagMask(MMI.ShaderProfile))
-reportIfDeniedShaderStageAccess(M, dxbc::RootFlags(RSD.Flags), *Mask);
 }
 
 static mcdxbc::RootSignatureDesc *

diff  --git 
a/llvm/test/CodeGen/DirectX/rootsignature-validation-deny-no-binding.ll 
b/llvm/test/CodeGen/DirectX/rootsig

[llvm-branch-commits] [llvm] [AllocToken, Clang] Implement __builtin_infer_alloc_token() and llvm.alloc.token.id (PR #156842)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156842

>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!

Created using spr 1.3.8-beta.1
---
 llvm/lib/Transforms/Instrumentation/AllocToken.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp 
b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
index d5ac3035df71b..3a28705d87523 100644
--- a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
@@ -151,7 +151,8 @@ STATISTIC(NumAllocations, "Allocations found");
 /// Expected format is: !{, }
 MDNode *getAllocTokenHintMetadata(const CallBase &CB) {
   MDNode *Ret = nullptr;
-  if (auto *II = dyn_cast(&CB)) {
+  if (auto *II = dyn_cast(&CB);
+  II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
 auto *MDV = cast(II->getArgOperand(0));
 Ret = cast(MDV->getMetadata());
 // If the intrinsic has an empty MDNode, type inference failed.
@@ -358,7 +359,7 @@ bool AllocToken::instrumentFunction(Function &F) {
   // Collect all allocation calls to avoid iterator invalidation.
   for (Instruction &I : instructions(F)) {
 // Collect all alloc_token_* intrinsics.
-if (IntrinsicInst *II = dyn_cast(&I);
+if (auto *II = dyn_cast(&I);
 II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
   IntrinsicInsts.emplace_back(II);
   continue;

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[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156839

>From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Thu, 4 Sep 2025 12:07:26 +0200
Subject: [PATCH] fixup! Insert AllocToken into index.rst

Created using spr 1.3.8-beta.1
---
 clang/docs/index.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/docs/index.rst b/clang/docs/index.rst
index be654af57f890..aa2b3a73dc11b 100644
--- a/clang/docs/index.rst
+++ b/clang/docs/index.rst
@@ -40,6 +40,7 @@ Using Clang as a Compiler
SanitizerCoverage
SanitizerStats
SanitizerSpecialCaseList
+   AllocToken
BoundsSafety
BoundsSafetyAdoptionGuide
BoundsSafetyImplPlans

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[llvm-branch-commits] [lit] Remove support for %T (PR #160028)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/160028


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[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)

[Alexander Richardson via llvm-branch-commits]

https://github.com/arichardson updated 
https://github.com/llvm/llvm-project/pull/105735

>From e4bd1181d160b8728e7d4158417a83e183bd1709 Mon Sep 17 00:00:00 2001
From: Alex Richardson 
Date: Thu, 22 Aug 2024 14:36:04 -0700
Subject: [PATCH 01/10] fix indentation in langref

Created using spr 1.3.6-beta.1
---
 llvm/docs/LangRef.rst | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 200224c78be00..1a59fba65815c 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -3103,19 +3103,19 @@ as follows:
 ``A``
 Specifies the address space of objects created by '``alloca``'.
 Defaults to the default address space of 0.
-``p[][n]::[:][:]``
+``p[][]::[:][:]``
 This specifies the *size* of a pointer and its  and
 \erred alignments for address space ``n``.  is optional
 and defaults to . The fourth parameter  is the size of 
the
 index that used for address calculation, which must be less than or equal
 to the pointer size. If not
 specified, the default index size is equal to the pointer size. All sizes
-are in bits. The address space, ``n``, is optional, and if not specified,
-denotes the default address space 0. The value of ``n`` must be
-in the range [1,2^24).
+are in bits. The , is optional, and if not specified,
+denotes the default address space 0. The value of  must
+be in the range [1,2^24).
 The optional are used to specify properties of pointers in this
-address space: the character ``u`` marks pointers as having an unstable
-representation and ```n`` marks pointers as non-integral (i.e. having
+address space: the character ``u`` marks pointers as having an unstable
+representation and ``n`` marks pointers as non-integral (i.e. having
 additional metadata). See :ref:`Non-Integral Pointer Types `.
 
 ``i:[:]``

>From db97145d3a653f2999b5935f9b1cb4550230689d Mon Sep 17 00:00:00 2001
From: Alex Richardson 
Date: Fri, 25 Oct 2024 12:51:11 -0700
Subject: [PATCH 02/10] include feedback

Created using spr 1.3.6-beta.1
---
 llvm/docs/LangRef.rst | 30 +-
 llvm/include/llvm/IR/DataLayout.h |  8 
 2 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index c137318af678b..3c3d0e0b4ab8e 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -659,7 +659,7 @@ LLVM IR optionally allows the frontend to denote pointers 
in certain address
 spaces as "non-integral" or "unstable" (or both "non-integral" and "unstable")
 via the :ref:`datalayout string`.
 
-These exact implications of these properties are target-specific, but the
+The exact implications of these properties are target-specific, but the
 following IR semantics and restrictions to optimization passes apply:
 
 Unstable pointer representation
@@ -668,7 +668,7 @@ Unstable pointer representation
 Pointers in this address space have an *unspecified* bitwise representation
 (i.e. not backed by a fixed integer). The bitwise pattern of such pointers is
 allowed to change in a target-specific way. For example, this could be a 
pointer
-type used for with copying garbage collection where the garbage collector could
+type used with copying garbage collection where the garbage collector could
 update the pointer at any time in the collection sweep.
 
 ``inttoptr`` and ``ptrtoint`` instructions have the same semantics as for
@@ -705,10 +705,10 @@ representation of the pointer.
 Non-integral pointer representation
 ^^^
 
-Pointers are not represented as an address, but may instead include
+Pointers are not represented as just an address, but may instead include
 additional metadata such as bounds information or a temporal identifier.
 Examples include AMDGPU buffer descriptors with a 128-bit fat pointer and a
-32-bit offset or CHERI capabilities that contain bounds, permissions and an
+32-bit offset, or CHERI capabilities that contain bounds, permissions and an
 out-of-band validity bit. In general, these pointers cannot be re-created
 from just an integer value.
 
@@ -716,23 +716,25 @@ In most cases pointers with a non-integral representation 
behave exactly the
 same as an integral pointer, the only difference is that it is not possible to
 create a pointer just from an address.
 
-"Non-integral" pointers also impose restrictions on the optimizer, but in
-general these are less restrictive than for "unstable" pointers. The main
+"Non-integral" pointers also impose restrictions on transformation passes, but
+in general these are less restrictive than for "unstable" pointers. The main
 difference compared to integral pointers is that ``inttoptr`` instructions
 should not be inserted by passes as they may not be able to create a valid
 pointer. This property also means that ``inttoptr(ptrtoint(x))`` cannot be
 folded to ``x`` as the ``

[llvm-branch-commits] [clang] [clang] fix transformation of subst constant template parameter nodes (PR #160777)

[Corentin Jabot via llvm-branch-commits]

@@ -16289,20 +16289,68 @@ 
TreeTransform::TransformPackIndexingExpr(PackIndexingExpr *E) {
   IndexExpr.get(), ExpandedExprs, FullySubstituted);
 }
 
-template
-ExprResult
-TreeTransform::TransformSubstNonTypeTemplateParmPackExpr(
-  SubstNonTypeTemplateParmPackExpr *E) 
{
-  // Default behavior is to do nothing with this transformation.
-  return E;
+template 
+ExprResult TreeTransform::TransformSubstNonTypeTemplateParmPackExpr(
+SubstNonTypeTemplateParmPackExpr *E) {
+  if (!getSema().ArgPackSubstIndex)
+// We aren't expanding the parameter pack, so just return ourselves.
+return E;
+
+  TemplateArgument Pack = E->getArgumentPack();
+  TemplateArgument Arg = SemaRef.getPackSubstitutedTemplateArgument(Pack);
+  return SemaRef.BuildSubstNonTypeTemplateParmExpr(
+  E->getAssociatedDecl(), E->getParameterPack(),
+  E->getParameterPackLocation(), Arg, SemaRef.getPackIndex(Pack),
+  E->getFinal());
 }
 
-template
-ExprResult
-TreeTransform::TransformSubstNonTypeTemplateParmExpr(
-  SubstNonTypeTemplateParmExpr *E) {
-  // Default behavior is to do nothing with this transformation.
-  return E;
+template 
+ExprResult TreeTransform::TransformSubstNonTypeTemplateParmExpr(
+SubstNonTypeTemplateParmExpr *E) {
+  Expr *OrigReplacement = E->getReplacement()->IgnoreImplicitAsWritten();
+  ExprResult Replacement = getDerived().TransformExpr(OrigReplacement);
+  if (Replacement.isInvalid())
+return true;
+
+  Decl *AssociatedDecl =
+  getDerived().TransformDecl(E->getNameLoc(), E->getAssociatedDecl());
+  if (!AssociatedDecl)
+return true;
+
+  if (Replacement.get() == OrigReplacement &&
+  AssociatedDecl == E->getAssociatedDecl())
+return E;
+
+  // If the replacement expression did not change, and the parameter type
+  // did not change, we can skip the semantic action because it would
+  // produce the same result anyway.
+  auto *Param = cast(
+  getReplacedTemplateParameterList(AssociatedDecl)
+  ->asArray()[E->getIndex()]);
+  if (QualType ParamType = Param->getType();
+  !SemaRef.Context.hasSameType(ParamType, E->getParameter()->getType()) ||
+  Replacement.get() != OrigReplacement) {
+
+// When transforming the replacement expression previously, all Sema
+// specific annotations, such as implicit casts, are erased. Calling the

cor3ntin wrote:

```suggestion
// specific annotations, such as implicit casts, are discarded. Calling the
```


https://github.com/llvm/llvm-project/pull/160777
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[llvm-branch-commits] [clang] [clang] fix transformation of subst constant template parameter nodes (PR #160777)

[Corentin Jabot via llvm-branch-commits]

@@ -113,7 +113,7 @@ using Bar = Foo; // expected-note {{candidate 
template ignored: co
// expected-note {{implicit deduction guide 
declared as 'template  requires __is_deducible(test9::Bar, 
test9::Foo) Bar(test9::Foo) -> test9::Foo'}} \
// expected-note {{implicit deduction guide 
declared as 'template  requires __is_deducible(test9::Bar, 
test9::Foo) Bar(const X (&)[sizeof(X)]) -> test9::Foo'}} \
// expected-note {{candidate template ignored: 
constraints not satisfied [with X = int]}} \
-   // expected-note {{cannot deduce template 
arguments for 'test9::Bar' from 'test9::Foo'}}
+   // expected-note {{cannot deduce template 
arguments for 'test9::Bar' from 'test9::Foo'}}

cor3ntin wrote:

isn't that a (very slight) regression?

https://github.com/llvm/llvm-project/pull/160777
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[llvm-branch-commits] [clang] [clang] fix transformation of subst constant template parameter nodes (PR #160777)

[Corentin Jabot via llvm-branch-commits]

@@ -16289,20 +16289,68 @@ 
TreeTransform::TransformPackIndexingExpr(PackIndexingExpr *E) {
   IndexExpr.get(), ExpandedExprs, FullySubstituted);
 }
 
-template
-ExprResult
-TreeTransform::TransformSubstNonTypeTemplateParmPackExpr(
-  SubstNonTypeTemplateParmPackExpr *E) 
{
-  // Default behavior is to do nothing with this transformation.
-  return E;
+template 
+ExprResult TreeTransform::TransformSubstNonTypeTemplateParmPackExpr(
+SubstNonTypeTemplateParmPackExpr *E) {
+  if (!getSema().ArgPackSubstIndex)
+// We aren't expanding the parameter pack, so just return ourselves.
+return E;
+
+  TemplateArgument Pack = E->getArgumentPack();
+  TemplateArgument Arg = SemaRef.getPackSubstitutedTemplateArgument(Pack);
+  return SemaRef.BuildSubstNonTypeTemplateParmExpr(
+  E->getAssociatedDecl(), E->getParameterPack(),
+  E->getParameterPackLocation(), Arg, SemaRef.getPackIndex(Pack),
+  E->getFinal());
 }
 
-template
-ExprResult
-TreeTransform::TransformSubstNonTypeTemplateParmExpr(
-  SubstNonTypeTemplateParmExpr *E) {
-  // Default behavior is to do nothing with this transformation.
-  return E;
+template 
+ExprResult TreeTransform::TransformSubstNonTypeTemplateParmExpr(
+SubstNonTypeTemplateParmExpr *E) {
+  Expr *OrigReplacement = E->getReplacement()->IgnoreImplicitAsWritten();
+  ExprResult Replacement = getDerived().TransformExpr(OrigReplacement);
+  if (Replacement.isInvalid())
+return true;
+
+  Decl *AssociatedDecl =
+  getDerived().TransformDecl(E->getNameLoc(), E->getAssociatedDecl());
+  if (!AssociatedDecl)
+return true;
+
+  if (Replacement.get() == OrigReplacement &&
+  AssociatedDecl == E->getAssociatedDecl())
+return E;
+
+  // If the replacement expression did not change, and the parameter type
+  // did not change, we can skip the semantic action because it would
+  // produce the same result anyway.
+  auto *Param = cast(
+  getReplacedTemplateParameterList(AssociatedDecl)
+  ->asArray()[E->getIndex()]);
+  if (QualType ParamType = Param->getType();
+  !SemaRef.Context.hasSameType(ParamType, E->getParameter()->getType()) ||
+  Replacement.get() != OrigReplacement) {
+
+// When transforming the replacement expression previously, all Sema
+// specific annotations, such as implicit casts, are erased. Calling the
+// corresponding sema action is necessary to recover those. Otherwise,
+// equivalency would be lost on the result.

cor3ntin wrote:

"the equivalence of the result would be lost" or something like that 

https://github.com/llvm/llvm-project/pull/160777
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[llvm-branch-commits] [llvm] release/21.x: [Mips] Fix atomic min/max generate mips4 instructions when compiling for mips2 (#159717) (PR #160807)

[via llvm-branch-commits]

https://github.com/yingopq approved this pull request.


https://github.com/llvm/llvm-project/pull/160807
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[llvm-branch-commits] [llvm] [DirectX] Introduce `dx.Padding` type (PR #160957)

[Justin Bogner via llvm-branch-commits]

https://github.com/bogner created 
https://github.com/llvm/llvm-project/pull/160957

This introduces the `dx.Padding` type as an alternative to the `dx.Layout` 
types that are currently used for cbuffers. Later, we'll remove the `dx.Layout` 
types completely, but making the backend handle either makes it easier to stage 
the necessary changes to get there.

See #147352 for details.

>From d8512f795eb6034050044ebbab3a7dfa44b133dc Mon Sep 17 00:00:00 2001
From: Justin Bogner 
Date: Thu, 7 Aug 2025 15:02:49 -0700
Subject: [PATCH] [DirectX] Introduce `dx.Padding` type

This introduces the `dx.Padding` type as an alternative to the
`dx.Layout` types that are currently used for cbuffers. Later, we'll
remove the `dx.Layout` types completely, but making the backend handle
either makes it easier to stage the necessary changes to get there.

See #147352 for details.
---
 llvm/include/llvm/Analysis/DXILResource.h | 19 +
 llvm/lib/Analysis/DXILResource.cpp| 47 ++-
 llvm/lib/IR/Type.cpp  |  4 +
 .../DXILResource/buffer-frombinding.ll|  4 +-
 .../DirectX/CBufferLoadLegacy-errors.ll   | 12 +--
 .../test/CodeGen/DirectX/CBufferLoadLegacy.ll | 12 +--
 .../ContainerData/PSVResources-order.ll   |  2 +-
 .../DirectX/ContainerData/PSVResources.ll |  2 +-
 .../DirectX/CreateHandleFromBinding.ll|  2 +-
 .../ForwardHandleAccesses/cbuffer-access.ll   | 20 ++---
 ...ffer_metadata.ll => cbuffer-layouttype.ll} |  3 +
 .../DirectX/Metadata/cbuffer-metadata.ll  | 84 +++
 .../CodeGen/DirectX/Metadata/cbuffer-only.ll  |  2 +-
 llvm/unittests/Analysis/DXILResourceTest.cpp  |  4 +-
 14 files changed, 182 insertions(+), 35 deletions(-)
 rename llvm/test/CodeGen/DirectX/Metadata/{cbuffer_metadata.ll => 
cbuffer-layouttype.ll} (96%)
 create mode 100644 llvm/test/CodeGen/DirectX/Metadata/cbuffer-metadata.ll

diff --git a/llvm/include/llvm/Analysis/DXILResource.h 
b/llvm/include/llvm/Analysis/DXILResource.h
index 88ac0a11fe5a2..c7aff167324e6 100644
--- a/llvm/include/llvm/Analysis/DXILResource.h
+++ b/llvm/include/llvm/Analysis/DXILResource.h
@@ -243,6 +243,25 @@ class LayoutExtType : public TargetExtType {
   }
 };
 
+/// The dx.Padding target extension type
+///
+/// `target("dx.Padding", NumBytes)`
+class PaddingExtType : public TargetExtType {
+public:
+  PaddingExtType() = delete;
+  PaddingExtType(const PaddingExtType &) = delete;
+  PaddingExtType &operator=(const PaddingExtType &) = delete;
+
+  unsigned getNumBytes() const { return getIntParameter(0); }
+
+  static bool classof(const TargetExtType *T) {
+return T->getName() == "dx.Padding";
+  }
+  static bool classof(const Type *T) {
+return isa(T) && classof(cast(T));
+  }
+};
+
 
//===--===//
 
 class ResourceTypeInfo {
diff --git a/llvm/lib/Analysis/DXILResource.cpp 
b/llvm/lib/Analysis/DXILResource.cpp
index b78cc03e34dbc..f9bf09262dd1f 100644
--- a/llvm/lib/Analysis/DXILResource.cpp
+++ b/llvm/lib/Analysis/DXILResource.cpp
@@ -281,6 +281,38 @@ static StructType *getOrCreateElementStruct(Type 
*ElemType, StringRef Name) {
   return StructType::create(ElemType, Name);
 }
 
+static Type *getTypeWithoutPadding(Type *Ty) {
+  // Recursively remove padding from structures.
+  if (auto *ST = dyn_cast(Ty)) {
+LLVMContext &Ctx = Ty->getContext();
+SmallVector ElementTypes;
+ElementTypes.reserve(ST->getNumElements());
+for (Type *ElTy : ST->elements()) {
+  if (isa(ElTy))
+continue;
+  ElementTypes.push_back(getTypeWithoutPadding(ElTy));
+}
+
+// Handle explicitly padded cbuffer arrays like { [ n x paddedty ], ty }
+if (ElementTypes.size() == 2)
+  if (auto *AT = dyn_cast(ElementTypes[0]))
+if (ElementTypes[1] == AT->getElementType())
+  return ArrayType::get(ElementTypes[1], AT->getNumElements() + 1);
+
+// If we only have a single element, don't wrap it in a struct.
+if (ElementTypes.size() == 1)
+  return ElementTypes[0];
+
+return StructType::get(Ctx, ElementTypes, /*IsPacked=*/false);
+  }
+  // Arrays just need to have their element type adjusted.
+  if (auto *AT = dyn_cast(Ty))
+return ArrayType::get(getTypeWithoutPadding(AT->getElementType()),
+  AT->getNumElements());
+  // Anything else should be good as is.
+  return Ty;
+}
+
 StructType *ResourceTypeInfo::createElementStruct(StringRef CBufferName) {
   SmallString<64> TypeName;
 
@@ -334,14 +366,21 @@ StructType 
*ResourceTypeInfo::createElementStruct(StringRef CBufferName) {
   }
   case ResourceKind::CBuffer: {
 auto *RTy = cast(HandleTy);
-LayoutExtType *LayoutType = cast(RTy->getResourceType());
-StructType *Ty = cast(LayoutType->getWrappedType());
 SmallString<64> Name = getResourceKindName(Kind);
 if (!CBufferName.empty()) {
   Name.append(".");
   Name.append(CBufferName);
 }
-return StructType::create(Ty-

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156840

>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 288b41bc42203..455de644daf00 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1289,6 +1289,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   // Check if QualType contains a pointer. Implements a simple DFS to
   // recursively check if a type contains a pointer type.
   llvm::SmallPtrSet VisitedRD;
+  bool IncompleteType = false;
   auto TypeContainsPtr = [&](auto &&self, QualType T) -> bool {
 QualType CanonicalType = T.getCanonicalType();
 if (CanonicalType->isPointerType())
@@ -1312,6 +1313,10 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   return self(self, AT->getElementType());
 // The type is a struct, class, or union.
 if (const RecordDecl *RD = CanonicalType->getAsRecordDecl()) {
+  if (!RD->isCompleteDefinition()) {
+IncompleteType = true;
+return false;
+  }
   if (!VisitedRD.insert(RD).second)
 return false; // already visited
   // Check all fields.
@@ -1333,6 +1338,8 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
 return false;
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
+  if (!ContainsPtr && IncompleteType)
+return nullptr;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

>From 7f706618ddc40375d4085bc2ebe03f02ec78823a Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:58:01 +0200
Subject: [PATCH 2/2] fixup!

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 455de644daf00..e7a0e7696e204 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1339,7 +1339,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
   if (!ContainsPtr && IncompleteType)
-return nullptr;
+return;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

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[llvm-branch-commits] [lit] Remove %T from tests (PR #160027)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/160027


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[llvm-branch-commits] [lit] Remove %T from tests (PR #160027)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/160027


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[llvm-branch-commits] [lit] Remove support for %T (PR #160028)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/160028


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[llvm-branch-commits] [lit] Remove support for %T (PR #160028)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/160028


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[llvm-branch-commits] [lit] Remove support for %T (PR #160028)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/160028


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[llvm-branch-commits] [llvm] [AllocToken] Introduce sanitize_alloc_token attribute and alloc_token metadata (PR #160131)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/160131

>From 8bd83ce9eeb447edb7b0d983a85c8ab50c323a37 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 22 Sep 2025 17:34:08 +0200
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.8-beta.1
---
 llvm/docs/LangRef.rst | 10 +
 llvm/include/llvm/Bitcode/LLVMBitCodes.h  |  1 +
 llvm/include/llvm/IR/Attributes.td|  3 ++
 llvm/include/llvm/IR/FixedMetadataKinds.def   |  1 +
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp |  2 +
 llvm/lib/Bitcode/Writer/BitcodeWriter.cpp |  2 +
 llvm/lib/Transforms/Utils/CodeExtractor.cpp   |  1 +
 llvm/lib/Transforms/Utils/Local.cpp   |  4 ++
 llvm/test/Bitcode/attributes.ll   |  6 +++
 llvm/test/Bitcode/compatibility.ll|  8 +++-
 llvm/test/Transforms/Inline/attributes.ll | 42 +++
 llvm/utils/emacs/llvm-mode.el |  2 +-
 llvm/utils/llvm.grm   |  1 +
 llvm/utils/vim/syntax/llvm.vim|  1 +
 .../vscode/llvm/syntaxes/ll.tmLanguage.yaml   |  1 +
 15 files changed, 82 insertions(+), 3 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index e64b9343b7622..1cf7ccc463b38 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -2427,6 +2427,9 @@ For example:
 if the attributed function is called during invocation of a function
 attributed with ``sanitize_realtime``.
 This attribute is incompatible with the ``sanitize_realtime`` attribute.
+``sanitize_alloc_token``
+This attribute indicates that implicit allocation token instrumentation
+is enabled for this function.
 ``speculative_load_hardening``
 This attribute indicates that
 `Speculative Load Hardening 
`_
@@ -8389,6 +8392,13 @@ Example:
 The ``nofree`` metadata indicates the memory pointed by the pointer will not be
 freed after the attached instruction.
 
+'``alloc_token``' Metadata
+^^
+
+The ``alloc_token`` metadata may be attached to calls to memory allocation
+functions, and contains richer semantic information about the type of the
+allocation. This information is consumed by the ``alloc-token`` pass to
+instrument such calls with allocation token IDs.
 
 Module Flags Metadata
 =
diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h 
b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
index 1c7d3462b6bae..464f475098ec5 100644
--- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h
+++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
@@ -800,6 +800,7 @@ enum AttributeKindCodes {
   ATTR_KIND_SANITIZE_TYPE = 101,
   ATTR_KIND_CAPTURES = 102,
   ATTR_KIND_DEAD_ON_RETURN = 103,
+  ATTR_KIND_SANITIZE_ALLOC_TOKEN = 104,
 };
 
 enum ComdatSelectionKindCodes {
diff --git a/llvm/include/llvm/IR/Attributes.td 
b/llvm/include/llvm/IR/Attributes.td
index ef816fb86ed1d..8e7d9dcebfe2a 100644
--- a/llvm/include/llvm/IR/Attributes.td
+++ b/llvm/include/llvm/IR/Attributes.td
@@ -342,6 +342,9 @@ def SanitizeRealtime : EnumAttr<"sanitize_realtime", 
IntersectPreserve, [FnAttr]
 /// during a real-time sanitized function (see `sanitize_realtime`).
 def SanitizeRealtimeBlocking : EnumAttr<"sanitize_realtime_blocking", 
IntersectPreserve, [FnAttr]>;
 
+/// Allocation token instrumentation is on.
+def SanitizeAllocToken : EnumAttr<"sanitize_alloc_token", IntersectPreserve, 
[FnAttr]>;
+
 /// Speculative Load Hardening is enabled.
 ///
 /// Note that this uses the default compatibility (always compatible during
diff --git a/llvm/include/llvm/IR/FixedMetadataKinds.def 
b/llvm/include/llvm/IR/FixedMetadataKinds.def
index d09cc15d65ff6..86a4d79afc2de 100644
--- a/llvm/include/llvm/IR/FixedMetadataKinds.def
+++ b/llvm/include/llvm/IR/FixedMetadataKinds.def
@@ -55,3 +55,4 @@ LLVM_FIXED_MD_KIND(MD_mmra, "mmra", 40)
 LLVM_FIXED_MD_KIND(MD_noalias_addrspace, "noalias.addrspace", 41)
 LLVM_FIXED_MD_KIND(MD_callee_type, "callee_type", 42)
 LLVM_FIXED_MD_KIND(MD_nofree, "nofree", 43)
+LLVM_FIXED_MD_KIND(MD_alloc_token, "alloc_token", 44)
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp 
b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 22a0d0ffdbaab..67ad4a2655ecd 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -2203,6 +2203,8 @@ static Attribute::AttrKind getAttrFromCode(uint64_t Code) 
{
 return Attribute::SanitizeRealtime;
   case bitc::ATTR_KIND_SANITIZE_REALTIME_BLOCKING:
 return Attribute::SanitizeRealtimeBlocking;
+  case bitc::ATTR_KIND_SANITIZE_ALLOC_TOKEN:
+return Attribute::SanitizeAllocToken;
   case bitc::ATTR_KIND_SPECULATIVE_LOAD_HARDENING:
 return Attribute::SpeculativeLoadHardening;
   case bitc::ATTR_KIND_SWIFT_ERROR:
diff --git a/llvm/l

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156839

>From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Thu, 4 Sep 2025 12:07:26 +0200
Subject: [PATCH] fixup! Insert AllocToken into index.rst

Created using spr 1.3.8-beta.1
---
 clang/docs/index.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/docs/index.rst b/clang/docs/index.rst
index be654af57f890..aa2b3a73dc11b 100644
--- a/clang/docs/index.rst
+++ b/clang/docs/index.rst
@@ -40,6 +40,7 @@ Using Clang as a Compiler
SanitizerCoverage
SanitizerStats
SanitizerSpecialCaseList
+   AllocToken
BoundsSafety
BoundsSafetyAdoptionGuide
BoundsSafetyImplPlans

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[llvm-branch-commits] [llvm] [AllocToken, Clang] Implement __builtin_infer_alloc_token() and llvm.alloc.token.id (PR #156842)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156842

>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!

Created using spr 1.3.8-beta.1
---
 llvm/lib/Transforms/Instrumentation/AllocToken.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp 
b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
index d5ac3035df71b..3a28705d87523 100644
--- a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
@@ -151,7 +151,8 @@ STATISTIC(NumAllocations, "Allocations found");
 /// Expected format is: !{, }
 MDNode *getAllocTokenHintMetadata(const CallBase &CB) {
   MDNode *Ret = nullptr;
-  if (auto *II = dyn_cast(&CB)) {
+  if (auto *II = dyn_cast(&CB);
+  II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
 auto *MDV = cast(II->getArgOperand(0));
 Ret = cast(MDV->getMetadata());
 // If the intrinsic has an empty MDNode, type inference failed.
@@ -358,7 +359,7 @@ bool AllocToken::instrumentFunction(Function &F) {
   // Collect all allocation calls to avoid iterator invalidation.
   for (Instruction &I : instructions(F)) {
 // Collect all alloc_token_* intrinsics.
-if (IntrinsicInst *II = dyn_cast(&I);
+if (auto *II = dyn_cast(&I);
 II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
   IntrinsicInsts.emplace_back(II);
   continue;

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[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Fix artificially-failing `preserve-branchweights.ll` (PR #160629)

[Nikita Popov via llvm-branch-commits]

https://github.com/nikic commented:

The test says:
```llvm
; Don't crash processing degenerate metadata.

define void @or_icmps_empty_metadata(i32 %x, i32 %y, ptr %p) {
```
So I believe the intention here is specifically to test this degenerate 
situation of 0, 0 branch weights.

Possibly these should be rejected by the verifier? If that were the case, there 
would be no need to test them here.

https://github.com/llvm/llvm-project/pull/160629
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[llvm-branch-commits] [compiler-rt] 82903ac - Revert "[compiler-rt] Fix some tests to work with lit internal shell. (#160728)"

[via llvm-branch-commits]

Author: cmtice
Date: 2025-09-26T13:43:48-07:00
New Revision: 82903acbcb8fa521594c6c3b0efa3331dcc0abb0

URL: 
https://github.com/llvm/llvm-project/commit/82903acbcb8fa521594c6c3b0efa3331dcc0abb0
DIFF: 
https://github.com/llvm/llvm-project/commit/82903acbcb8fa521594c6c3b0efa3331dcc0abb0.diff

LOG: Revert "[compiler-rt] Fix some tests to work with lit internal shell. 
(#160728)"

This reverts commit e9185af70a4898d050899aa83aa350e570459128.

Added: 


Modified: 
compiler-rt/test/fuzzer/fork-sigusr.test
compiler-rt/test/fuzzer/sigint.test
compiler-rt/test/fuzzer/sigusr.test
compiler-rt/test/msan/allocator_mapping.cpp
compiler-rt/test/nsan/Posix/allocator_mapping.cpp

Removed: 




diff  --git a/compiler-rt/test/fuzzer/fork-sigusr.test 
b/compiler-rt/test/fuzzer/fork-sigusr.test
index 226c4147b7380..088e63cae4311 100644
--- a/compiler-rt/test/fuzzer/fork-sigusr.test
+++ b/compiler-rt/test/fuzzer/fork-sigusr.test
@@ -1,16 +1,14 @@
 # Check that libFuzzer honors SIGUSR1/SIGUSR2
 # Disabled on Windows which does not have SIGUSR1/SIGUSR2.
+REQUIRES: shell
 UNSUPPORTED: darwin, target={{.*windows.*}}, target=aarch64{{.*}}
 RUN: rm -rf %t
 RUN: mkdir -p %t
 RUN: %cpp_compiler %S/SleepOneSecondTest.cpp -o %t/ForkSIGUSR
 
-# The line below needs the " | env" at the end, in order to make the
-# script continue executing, rather than waiting (forever) for the
-# 'nohup run...' command to finish.
-RUN: bash -c "nohup %run %t/ForkSIGUSR -fork=3 -ignore_crashes=1 2>%t/log & 
echo -n $! > %t2" | env
+RUN: %run %t/ForkSIGUSR -fork=3 -ignore_crashes=1 2>%t/log & export PID=$!
 RUN: sleep 3
-RUN: kill -SIGUSR2 %{readfile:%t2}
+RUN: kill -SIGUSR2 $PID
 RUN: sleep 6
 RUN: cat %t/log | FileCheck %s --dump-input=fail
 

diff  --git a/compiler-rt/test/fuzzer/sigint.test 
b/compiler-rt/test/fuzzer/sigint.test
index aa112f086066f..ac482d79b8e28 100644
--- a/compiler-rt/test/fuzzer/sigint.test
+++ b/compiler-rt/test/fuzzer/sigint.test
@@ -1,4 +1,4 @@
-REQUIRES: msan
+REQUIRES: shell, msan
 UNSUPPORTED: target=arm{{.*}}
 
 # Check that libFuzzer exits gracefully under SIGINT with MSan.
@@ -6,12 +6,9 @@ RUN: rm -rf %t
 RUN: mkdir -p %t
 RUN: %msan_compiler %S/SleepOneSecondTest.cpp -o %t/LFSIGINT
 
-# The line below needs the " | env" at the end, in order to make the
-# script continue executing, rather than waiting (forever) for the
-# 'nohup run...' command to finish.
-RUN: bash -c "nohup %run %t/LFSIGINT 2> %t/log & echo -n $! > %t2" | env
+RUN: %run %t/LFSIGINT 2> %t/log & export PID=$!
 RUN: sleep 2
-RUN: kill -SIGINT %{readfile:%t2}
+RUN: kill -SIGINT $PID
 RUN: sleep 3
 RUN: cat %t/log | FileCheck %s
 

diff  --git a/compiler-rt/test/fuzzer/sigusr.test 
b/compiler-rt/test/fuzzer/sigusr.test
index 0c1d29231e1a0..c8a77ac63a6d7 100644
--- a/compiler-rt/test/fuzzer/sigusr.test
+++ b/compiler-rt/test/fuzzer/sigusr.test
@@ -1,17 +1,15 @@
 # FIXME: Disabled on Windows for now because of reliance on posix only features
 # (eg: export, "&", pkill).
+REQUIRES: shell
 UNSUPPORTED: darwin, target={{.*windows.*}}
 # Check that libFuzzer honors SIGUSR1/SIGUSR2
 RUN: rm -rf %t
 RUN: mkdir -p %t
 RUN: %cpp_compiler %S/SleepOneSecondTest.cpp -o %t/LFSIGUSR
 
-# The line below needs the " | env" at the end, in order to make the
-# script continue executing, rather than waiting (forever) for the
-# 'nohup run...' command to finish.
-RUN: bash -c "nohup %run %t/LFSIGUSR 2> %t/log & echo -n $! > %t2"| env
+RUN: %run %t/LFSIGUSR 2> %t/log & export PID=$!
 RUN: sleep 2
-RUN: kill -SIGUSR1 %{readfile:%t2}
+RUN: kill -SIGUSR1 $PID
 RUN: sleep 3
 RUN: cat %t/log | FileCheck %s
 

diff  --git a/compiler-rt/test/msan/allocator_mapping.cpp 
b/compiler-rt/test/msan/allocator_mapping.cpp
index aa48863861ecb..e7a12da489152 100644
--- a/compiler-rt/test/msan/allocator_mapping.cpp
+++ b/compiler-rt/test/msan/allocator_mapping.cpp
@@ -3,8 +3,7 @@
 // mapping the heap early, in __msan_init.
 //
 // RUN: %clangxx_msan -O0 %s -o %t_1
-// RUN: %run %t_1 > %t_3
-// RUN: %clangxx_msan -O0 -DHEAP_ADDRESS=%{readfile:%t_3} %s -o %t_2 && %run 
%t_2
+// RUN: %clangxx_msan -O0 -DHEAP_ADDRESS=$(%run %t_1) %s -o %t_2 && %run %t_2
 //
 // This test only makes sense for the 64-bit allocator. The 32-bit allocator
 // does not have a fixed mapping. Exclude platforms that use the 32-bit

diff  --git a/compiler-rt/test/nsan/Posix/allocator_mapping.cpp 
b/compiler-rt/test/nsan/Posix/allocator_mapping.cpp
index 8be5008686385..3a3e655e259d0 100644
--- a/compiler-rt/test/nsan/Posix/allocator_mapping.cpp
+++ b/compiler-rt/test/nsan/Posix/allocator_mapping.cpp
@@ -2,8 +2,7 @@
 /// Test that a module constructor can not map memory over the NSan heap
 /// (without MAP_FIXED, of course).
 // RUN: %clangxx_nsan -O0 %s -o %t_1
-// RUN: %run %t_1 > %t_3
-// RUN: %clangxx_nsan -O0 -DHEAP_ADDRESS=%{readfile:%t_3} %s -o %t_2 && %run 
%t_2
+// RUN: %clangxx_nsan -O0 -DHEAP_ADDRESS=$(%run %t_1)

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

[Marco Elver via llvm-branch-commits]

https://github.com/melver updated 
https://github.com/llvm/llvm-project/pull/156840

>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 288b41bc42203..455de644daf00 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1289,6 +1289,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   // Check if QualType contains a pointer. Implements a simple DFS to
   // recursively check if a type contains a pointer type.
   llvm::SmallPtrSet VisitedRD;
+  bool IncompleteType = false;
   auto TypeContainsPtr = [&](auto &&self, QualType T) -> bool {
 QualType CanonicalType = T.getCanonicalType();
 if (CanonicalType->isPointerType())
@@ -1312,6 +1313,10 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   return self(self, AT->getElementType());
 // The type is a struct, class, or union.
 if (const RecordDecl *RD = CanonicalType->getAsRecordDecl()) {
+  if (!RD->isCompleteDefinition()) {
+IncompleteType = true;
+return false;
+  }
   if (!VisitedRD.insert(RD).second)
 return false; // already visited
   // Check all fields.
@@ -1333,6 +1338,8 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
 return false;
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
+  if (!ContainsPtr && IncompleteType)
+return nullptr;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

>From 7f706618ddc40375d4085bc2ebe03f02ec78823a Mon Sep 17 00:00:00 2001
From: Marco Elver 
Date: Mon, 8 Sep 2025 21:58:01 +0200
Subject: [PATCH 2/2] fixup!

Created using spr 1.3.8-beta.1
---
 clang/lib/CodeGen/CGExpr.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 455de644daf00..e7a0e7696e204 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1339,7 +1339,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase 
*CB,
   };
   const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
   if (!ContainsPtr && IncompleteType)
-return nullptr;
+return;
   auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
   auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
 

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[llvm-branch-commits] [llvm] [DirectX] Introduce `dx.Padding` type (PR #160957)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-directx

Author: Justin Bogner (bogner)


Changes

This introduces the `dx.Padding` type as an alternative to the `dx.Layout` 
types that are currently used for cbuffers. Later, we'll remove the `dx.Layout` 
types completely, but making the backend handle either makes it easier to stage 
the necessary changes to get there.

See #147352 for details.

---

Patch is 21.62 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/160957.diff


14 Files Affected:

- (modified) llvm/include/llvm/Analysis/DXILResource.h (+19) 
- (modified) llvm/lib/Analysis/DXILResource.cpp (+43-4) 
- (modified) llvm/lib/IR/Type.cpp (+4) 
- (modified) llvm/test/Analysis/DXILResource/buffer-frombinding.ll (+2-2) 
- (modified) llvm/test/CodeGen/DirectX/CBufferLoadLegacy-errors.ll (+6-6) 
- (modified) llvm/test/CodeGen/DirectX/CBufferLoadLegacy.ll (+6-6) 
- (modified) llvm/test/CodeGen/DirectX/ContainerData/PSVResources-order.ll 
(+1-1) 
- (modified) llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll (+1-1) 
- (modified) llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll (+1-1) 
- (modified) llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll 
(+10-10) 
- (renamed) llvm/test/CodeGen/DirectX/Metadata/cbuffer-layouttype.ll (+3) 
- (added) llvm/test/CodeGen/DirectX/Metadata/cbuffer-metadata.ll (+84) 
- (modified) llvm/test/CodeGen/DirectX/Metadata/cbuffer-only.ll (+1-1) 
- (modified) llvm/unittests/Analysis/DXILResourceTest.cpp (+1-3) 


``diff
diff --git a/llvm/include/llvm/Analysis/DXILResource.h 
b/llvm/include/llvm/Analysis/DXILResource.h
index 88ac0a11fe5a2..c7aff167324e6 100644
--- a/llvm/include/llvm/Analysis/DXILResource.h
+++ b/llvm/include/llvm/Analysis/DXILResource.h
@@ -243,6 +243,25 @@ class LayoutExtType : public TargetExtType {
   }
 };
 
+/// The dx.Padding target extension type
+///
+/// `target("dx.Padding", NumBytes)`
+class PaddingExtType : public TargetExtType {
+public:
+  PaddingExtType() = delete;
+  PaddingExtType(const PaddingExtType &) = delete;
+  PaddingExtType &operator=(const PaddingExtType &) = delete;
+
+  unsigned getNumBytes() const { return getIntParameter(0); }
+
+  static bool classof(const TargetExtType *T) {
+return T->getName() == "dx.Padding";
+  }
+  static bool classof(const Type *T) {
+return isa(T) && classof(cast(T));
+  }
+};
+
 
//===--===//
 
 class ResourceTypeInfo {
diff --git a/llvm/lib/Analysis/DXILResource.cpp 
b/llvm/lib/Analysis/DXILResource.cpp
index b78cc03e34dbc..f9bf09262dd1f 100644
--- a/llvm/lib/Analysis/DXILResource.cpp
+++ b/llvm/lib/Analysis/DXILResource.cpp
@@ -281,6 +281,38 @@ static StructType *getOrCreateElementStruct(Type 
*ElemType, StringRef Name) {
   return StructType::create(ElemType, Name);
 }
 
+static Type *getTypeWithoutPadding(Type *Ty) {
+  // Recursively remove padding from structures.
+  if (auto *ST = dyn_cast(Ty)) {
+LLVMContext &Ctx = Ty->getContext();
+SmallVector ElementTypes;
+ElementTypes.reserve(ST->getNumElements());
+for (Type *ElTy : ST->elements()) {
+  if (isa(ElTy))
+continue;
+  ElementTypes.push_back(getTypeWithoutPadding(ElTy));
+}
+
+// Handle explicitly padded cbuffer arrays like { [ n x paddedty ], ty }
+if (ElementTypes.size() == 2)
+  if (auto *AT = dyn_cast(ElementTypes[0]))
+if (ElementTypes[1] == AT->getElementType())
+  return ArrayType::get(ElementTypes[1], AT->getNumElements() + 1);
+
+// If we only have a single element, don't wrap it in a struct.
+if (ElementTypes.size() == 1)
+  return ElementTypes[0];
+
+return StructType::get(Ctx, ElementTypes, /*IsPacked=*/false);
+  }
+  // Arrays just need to have their element type adjusted.
+  if (auto *AT = dyn_cast(Ty))
+return ArrayType::get(getTypeWithoutPadding(AT->getElementType()),
+  AT->getNumElements());
+  // Anything else should be good as is.
+  return Ty;
+}
+
 StructType *ResourceTypeInfo::createElementStruct(StringRef CBufferName) {
   SmallString<64> TypeName;
 
@@ -334,14 +366,21 @@ StructType 
*ResourceTypeInfo::createElementStruct(StringRef CBufferName) {
   }
   case ResourceKind::CBuffer: {
 auto *RTy = cast(HandleTy);
-LayoutExtType *LayoutType = cast(RTy->getResourceType());
-StructType *Ty = cast(LayoutType->getWrappedType());
 SmallString<64> Name = getResourceKindName(Kind);
 if (!CBufferName.empty()) {
   Name.append(".");
   Name.append(CBufferName);
 }
-return StructType::create(Ty->elements(), Name);
+
+// TODO: Remove this when we update the frontend to use explicit padding.
+if (LayoutExtType *LayoutType =
+dyn_cast(RTy->getResourceType())) {
+  StructType *Ty = cast(LayoutType->getWrappedType());
+  return StructType::create(Ty->elements(), Name);
+}
+
+return getOrCreateElementStruct(
+ 

[llvm-branch-commits] [clang] [clang] fix transformation of subst constant template parameter nodes (PR #160777)

[Matheus Izvekov via llvm-branch-commits]

@@ -113,7 +113,7 @@ using Bar = Foo; // expected-note {{candidate 
template ignored: co
// expected-note {{implicit deduction guide 
declared as 'template  requires __is_deducible(test9::Bar, 
test9::Foo) Bar(test9::Foo) -> test9::Foo'}} \
// expected-note {{implicit deduction guide 
declared as 'template  requires __is_deducible(test9::Bar, 
test9::Foo) Bar(const X (&)[sizeof(X)]) -> test9::Foo'}} \
// expected-note {{candidate template ignored: 
constraints not satisfied [with X = int]}} \
-   // expected-note {{cannot deduce template 
arguments for 'test9::Bar' from 'test9::Foo'}}
+   // expected-note {{cannot deduce template 
arguments for 'test9::Bar' from 'test9::Foo'}}

mizvekov wrote:

Now this increases the amount of sugar that we can preserve.

Now whether this extra sugar is supposed to be printed in this case is a 
separate question, related to the pre-existing problem that we don't preserve 
whether the replacement expression for the Subst node was canonicalized or not.

https://github.com/llvm/llvm-project/pull/160777
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[llvm-branch-commits] [llvm] [DirectX] Introduce `dx.Padding` type (PR #160957)

[Helena Kotas via llvm-branch-commits]

@@ -0,0 +1,84 @@
+; RUN: opt -S -dxil-translate-metadata < %s | FileCheck %s
+; RUN: opt -S --passes="dxil-pretty-printer" < %s 2>&1 | FileCheck %s 
--check-prefix=PRINT
+; RUN: llc %s --filetype=asm -o - < %s 2>&1 | FileCheck %s 
--check-prefixes=CHECK,PRINT
+
+target triple = "dxil-pc-shadermodel6.6-compute"
+
+%__cblayout_CB1 = type <{ float, i32, double, <2 x i32> }>
+@CB1.cb = global target("dx.CBuffer", %__cblayout_CB1) poison
+@CB1.str = private unnamed_addr constant [4 x i8] c"CB1\00", align 1
+
+%__cblayout_CB2 = type <{ float, [4 x i8], double, float, half, i16, i64, i32 
}>
+@CB2.cb = global target("dx.CBuffer", %__cblayout_CB2) poison
+@CB2.str = private unnamed_addr constant [4 x i8] c"CB2\00", align 1
+
+%__cblayout_MyConstants = type <{
+  double, target("dx.Padding", 8),
+  <3 x float>, float,
+  <3 x double>, half, target("dx.Padding", 6),
+  <2 x double>,
+  float, <3 x half>, <3 x half>
+}>
+@MyConstants.cb = global target("dx.CBuffer", %__cblayout_MyConstants) poison
+@MyConstants.str = private unnamed_addr constant [12 x i8] c"MyConstants\00", 
align 1
+
+; PRINT:; Resource Bindings:
+; PRINT-NEXT:;
+; PRINT-NEXT:; NameType  Format  Dim   IDHLSL Bind  Count
+; PRINT-NEXT:; 
+; PRINT-NEXT:; CB1  cbuffer  NA   NA  CB0  cb0 1
+; PRINT-NEXT:; CB2  cbuffer  NA   NA  CB1  cb1 1
+; PRINT-NEXT:; MyConstants  cbuffer  NA   NA  CB2  cb5,space15 1
+
+define void @test() #0 {
+
+  ; cbuffer CB1 : register(b0) {
+  ;   float a;
+  ;   int b;
+  ;   double c;
+  ;   int2 d;
+  ; }
+  %CB1.cb_h = call target("dx.CBuffer", %__cblayout_CB1)
+@llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, 
ptr @CB1.str)
+  ; cbuffer CB2 : register(b0) {

hekota wrote:

```suggestion

  ; cbuffer CB2 : register(b0) {
```

https://github.com/llvm/llvm-project/pull/160957
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[llvm-branch-commits] [llvm] [DirectX] Introduce `dx.Padding` type (PR #160957)

[Helena Kotas via llvm-branch-commits]

@@ -0,0 +1,84 @@
+; RUN: opt -S -dxil-translate-metadata < %s | FileCheck %s
+; RUN: opt -S --passes="dxil-pretty-printer" < %s 2>&1 | FileCheck %s 
--check-prefix=PRINT
+; RUN: llc %s --filetype=asm -o - < %s 2>&1 | FileCheck %s 
--check-prefixes=CHECK,PRINT
+
+target triple = "dxil-pc-shadermodel6.6-compute"
+
+%__cblayout_CB1 = type <{ float, i32, double, <2 x i32> }>
+@CB1.cb = global target("dx.CBuffer", %__cblayout_CB1) poison
+@CB1.str = private unnamed_addr constant [4 x i8] c"CB1\00", align 1
+
+%__cblayout_CB2 = type <{ float, [4 x i8], double, float, half, i16, i64, i32 
}>
+@CB2.cb = global target("dx.CBuffer", %__cblayout_CB2) poison
+@CB2.str = private unnamed_addr constant [4 x i8] c"CB2\00", align 1
+
+%__cblayout_MyConstants = type <{
+  double, target("dx.Padding", 8),
+  <3 x float>, float,
+  <3 x double>, half, target("dx.Padding", 6),
+  <2 x double>,
+  float, <3 x half>, <3 x half>
+}>
+@MyConstants.cb = global target("dx.CBuffer", %__cblayout_MyConstants) poison
+@MyConstants.str = private unnamed_addr constant [12 x i8] c"MyConstants\00", 
align 1
+
+; PRINT:; Resource Bindings:
+; PRINT-NEXT:;
+; PRINT-NEXT:; NameType  Format  Dim   IDHLSL Bind  Count
+; PRINT-NEXT:; 
+; PRINT-NEXT:; CB1  cbuffer  NA   NA  CB0  cb0 1
+; PRINT-NEXT:; CB2  cbuffer  NA   NA  CB1  cb1 1
+; PRINT-NEXT:; MyConstants  cbuffer  NA   NA  CB2  cb5,space15 1
+
+define void @test() #0 {
+
+  ; cbuffer CB1 : register(b0) {
+  ;   float a;
+  ;   int b;
+  ;   double c;
+  ;   int2 d;
+  ; }
+  %CB1.cb_h = call target("dx.CBuffer", %__cblayout_CB1)
+@llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, 
ptr @CB1.str)
+  ; cbuffer CB2 : register(b0) {
+  ;   float a;
+  ;   double b;
+  ;   float c;
+  ;   half d;
+  ;   uint16_t e;
+  ;   int64_t f;
+  ;   int g;
+  ;}
+
+  %CB2.cb_h = call target("dx.CBuffer", %__cblayout_CB2)
+@llvm.dx.resource.handlefrombinding(i32 0, i32 1, i32 1, i32 0, 
ptr @CB2.str)
+  ; cbuffer CB3 : register(b5) {
+  ;   double B0;
+  ;   float3 B1;
+  ;   float B2;
+  ;   double3 B3;
+  ;   half B4;
+  ;   double2 B5;
+  ;   float B6;
+  ;   half3 B7;
+  ;   half3 B8;
+  ; }
+  %CB3.cb_h = call target("dx.CBuffer", %__cblayout_MyConstants)
+@llvm.dx.resource.handlefrombinding(i32 15, i32 5, i32 1, i32 0, 
ptr @MyConstants.str)
+
+  ret void
+}
+
+attributes #0 = { noinline nounwind "hlsl.shader"="compute" }
+
+; CHECK: @CB1 = external constant %CBuffer.CB1
+; CHECK: @CB2 = external constant %CBuffer.CB2
+; CHECK: @MyConstants = external constant %CBuffer.MyConstants

hekota wrote:

Could you please add CHECKs for ` %CBuffer.CB1`,  `%CBuffer.CB2` and 
`%CBuffer.MyConstants` to show the padding has been filtered out?

https://github.com/llvm/llvm-project/pull/160957
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[llvm-branch-commits] [llvm] [DirectX] Introduce `dx.Padding` type (PR #160957)

[Helena Kotas via llvm-branch-commits]

https://github.com/hekota approved this pull request.

LGTM!

https://github.com/llvm/llvm-project/pull/160957
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[llvm-branch-commits] [mlir] [mlir][omp] Add omp.tile operation (PR #160292)

[Tom Eccles via llvm-branch-commits]

@@ -403,6 +403,7 @@ void DefFormat::genLiteralParser(StringRef value, 
FmtContext &ctx,
   .Case("]", "RSquare")
   .Case("?", "Question")
   .Case("+", "Plus")
+  .Case("-", "Minus")

tblah wrote:

Thanks for the context!

https://github.com/llvm/llvm-project/pull/160292
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[llvm-branch-commits] [llvm] [LoongArch] Custom legalize vector_shuffle to `xvinsve0.{w/d}` when possible (PR #160857)

[via llvm-branch-commits]

https://github.com/zhaoqi5 updated 
https://github.com/llvm/llvm-project/pull/160857

>From 9e5c32ebd39d726dadee02aa47659fa7b2b2053d Mon Sep 17 00:00:00 2001
From: Qi Zhao 
Date: Fri, 26 Sep 2025 19:07:22 +0800
Subject: [PATCH 1/2] [LoongArch] Custom legalize vector_shuffle to
 `xvinsve0.{w/d}` when possible

---
 .../LoongArch/LoongArchISelLowering.cpp   |  52 
 .../Target/LoongArch/LoongArchISelLowering.h  |   1 +
 .../LoongArch/LoongArchLASXInstrInfo.td   |   9 +
 .../ir-instruction/shuffle-as-xvinsve0.ll | 247 --
 4 files changed, 109 insertions(+), 200 deletions(-)

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 5d4a8fd080202..194f42995d55a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2317,6 +2317,54 @@ static SDValue lowerVECTOR_SHUFFLE_XVPICKOD(const SDLoc 
&DL, ArrayRef Mask,
   return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
 }
 
+// Check if exactly one element of the Mask is replaced by 'Replaced', while
+// all other elements are either 'Base + i' or undef (-1). On success, return
+// the index of the replaced element. Otherwise, just return -1.
+static int checkReplaceOne(ArrayRef Mask, int Base, int Replaced) {
+  int MaskSize = Mask.size();
+  int Idx = -1;
+  for (int i = 0; i < MaskSize; ++i) {
+if (Mask[i] == Base + i || Mask[i] == -1)
+  continue;
+if (Mask[i] != Replaced)
+  return -1;
+if (Idx == -1)
+  Idx = i;
+else
+  return -1;
+  }
+  return Idx;
+}
+
+/// Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).
+static SDValue
+lowerVECTOR_SHUFFLE_XVINSVE0(const SDLoc &DL, ArrayRef Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
+  // LoongArch LASX only supports xvinsve0.{w/d}.
+  if (VT != MVT::v8i32 && VT != MVT::v8f32 && VT != MVT::v4i64 &&
+  VT != MVT::v4f64)
+return SDValue();
+
+  MVT GRLenVT = Subtarget.getGRLenVT();
+  int MaskSize = Mask.size();
+  assert(MaskSize == (int)VT.getVectorNumElements() && "Unexpected mask size");
+
+  // Case 1: the lowest element of V2 replaces one element in V1.
+  int Idx = checkReplaceOne(Mask, 0, MaskSize);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V1, V2,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  // Case 2: the lowest element of V1 replaces one element in V2.
+  Idx = checkReplaceOne(Mask, MaskSize, 0);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V2, V1,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  return SDValue();
+}
+
 /// Lower VECTOR_SHUFFLE into XVSHUF (if possible).
 static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef Mask,
   MVT VT, SDValue V1, SDValue V2,
@@ -2593,6 +2641,9 @@ static SDValue lower256BitShuffle(const SDLoc &DL, 
ArrayRef Mask, MVT VT,
   if ((Result = lowerVECTOR_SHUFFLEAsShift(DL, Mask, VT, V1, V2, DAG, 
Subtarget,
Zeroable)))
 return Result;
+  if ((Result =
+   lowerVECTOR_SHUFFLE_XVINSVE0(DL, Mask, VT, V1, V2, DAG, Subtarget)))
+return Result;
   if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG,
 Subtarget)))
 return Result;
@@ -7450,6 +7501,7 @@ const char 
*LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
 NODE_NAME_CASE(XVPERM)
 NODE_NAME_CASE(XVREPLVE0)
 NODE_NAME_CASE(XVREPLVE0Q)
+NODE_NAME_CASE(XVINSVE0)
 NODE_NAME_CASE(VPICK_SEXT_ELT)
 NODE_NAME_CASE(VPICK_ZEXT_ELT)
 NODE_NAME_CASE(VREPLVE)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index b2fccf59169ff..3e7ea5ebba79e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -151,6 +151,7 @@ enum NodeType : unsigned {
   XVPERM,
   XVREPLVE0,
   XVREPLVE0Q,
+  XVINSVE0,
 
   // Extended vector element extraction
   VPICK_SEXT_ELT,
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td 
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index adfe990ba1234..dfcbfff2a9a72 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -20,6 +20,7 @@ def loongarch_xvpermi: SDNode<"LoongArchISD::XVPERMI", 
SDT_LoongArchV1RUimm>;
 def loongarch_xvperm: SDNode<"LoongArchISD::XVPERM", SDT_LoongArchXVPERM>;
 def loongarch_xvreplve0: SDNode<"LoongArchISD::XVREPLVE0", 
SDT_LoongArchXVREPLVE0>;
 def loongarch_xvreplve0q: SDNode<"LoongArchISD::XVREPLVE0Q", 
SDT_LoongArchXVREPLVE0>;
+def loongarch_xvinsve0 : SDNode<"LoongArchISD::XVINSVE0", 
SDT_LoongArchV2RUimm>;
 def loongarch

[llvm-branch-commits] [flang] [flang][OpenMP] Use OmpDirectiveSpecification in REQUIRES (PR #160595)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-flang-semantics

Author: Krzysztof Parzyszek (kparzysz)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/160595.diff


7 Files Affected:

- (modified) flang/include/flang/Parser/openmp-utils.h (+1-3) 
- (modified) flang/include/flang/Parser/parse-tree.h (+1-2) 
- (modified) flang/lib/Parser/openmp-parsers.cpp (+3-1) 
- (modified) flang/lib/Parser/unparse.cpp (+3-3) 
- (modified) flang/lib/Semantics/check-omp-structure.cpp (+3-8) 
- (modified) flang/lib/Semantics/resolve-directives.cpp (+1-1) 
- (added) flang/test/Parser/OpenMP/requires.f90 (+33) 


``diff
diff --git a/flang/include/flang/Parser/openmp-utils.h 
b/flang/include/flang/Parser/openmp-utils.h
index 77c31b939e522..b8f3559097750 100644
--- a/flang/include/flang/Parser/openmp-utils.h
+++ b/flang/include/flang/Parser/openmp-utils.h
@@ -41,7 +41,6 @@ struct ConstructId {
 MAKE_CONSTR_ID(OpenMPDeclarativeAllocate, D::OMPD_allocate);
 MAKE_CONSTR_ID(OpenMPDeclareReductionConstruct, D::OMPD_declare_reduction);
 MAKE_CONSTR_ID(OpenMPExecutableAllocate, D::OMPD_allocate);
-MAKE_CONSTR_ID(OpenMPRequiresConstruct, D::OMPD_requires);
 
 #undef MAKE_CONSTR_ID
 
@@ -94,8 +93,7 @@ struct DirectiveNameScope {
 return std::get(x.t).DirName();
   } else if constexpr (std::is_same_v ||
   std::is_same_v ||
-  std::is_same_v ||
-  std::is_same_v) {
+  std::is_same_v) {
 return MakeName(std::get(x.t).source, ConstructId::id);
   } else {
 return GetFromTuple(
diff --git a/flang/include/flang/Parser/parse-tree.h 
b/flang/include/flang/Parser/parse-tree.h
index bd55166eb9f80..8b23189bc1e90 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -4991,9 +4991,8 @@ struct OpenMPGroupprivate {
 
 // 2.4 requires -> REQUIRES requires-clause[ [ [,] requires-clause]...]
 struct OpenMPRequiresConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPRequiresConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPRequiresConstruct, 
OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // 2.15.2 threadprivate -> THREADPRIVATE (variable-name-list)
diff --git a/flang/lib/Parser/openmp-parsers.cpp 
b/flang/lib/Parser/openmp-parsers.cpp
index 5fd3c1768a17f..ea09fe04f07a0 100644
--- a/flang/lib/Parser/openmp-parsers.cpp
+++ b/flang/lib/Parser/openmp-parsers.cpp
@@ -1836,7 +1836,9 @@ TYPE_PARSER(sourced( //
 
 // 2.4 Requires construct
 TYPE_PARSER(sourced(construct(
-verbatim("REQUIRES"_tok), Parser{})))
+predicated(OmpDirectiveNameParser{},
+IsDirective(llvm::omp::Directive::OMPD_requires)) >=
+Parser{})))
 
 // 2.15.2 Threadprivate directive
 TYPE_PARSER(sourced( //
diff --git a/flang/lib/Parser/unparse.cpp b/flang/lib/Parser/unparse.cpp
index 9812a656092ac..0fbd347e91b18 100644
--- a/flang/lib/Parser/unparse.cpp
+++ b/flang/lib/Parser/unparse.cpp
@@ -2594,10 +2594,10 @@ class UnparseVisitor {
 Put("\n");
 EndOpenMP();
   }
-  void Unparse(const OpenMPRequiresConstruct &y) {
+  void Unparse(const OpenMPRequiresConstruct &x) {
 BeginOpenMP();
-Word("!$OMP REQUIRES ");
-Walk(std::get(y.t));
+Word("!$OMP ");
+Walk(x.v);
 Put("\n");
 EndOpenMP();
   }
diff --git a/flang/lib/Semantics/check-omp-structure.cpp 
b/flang/lib/Semantics/check-omp-structure.cpp
index 6538e0b794791..223523f2a46ff 100644
--- a/flang/lib/Semantics/check-omp-structure.cpp
+++ b/flang/lib/Semantics/check-omp-structure.cpp
@@ -624,10 +624,6 @@ template  struct 
DirectiveSpellingVisitor {
 checker_(x.v.DirName().source, Directive::OMPD_groupprivate);
 return false;
   }
-  bool Pre(const parser::OpenMPRequiresConstruct &x) {
-checker_(std::get(x.t).source, Directive::OMPD_requires);
-return false;
-  }
   bool Pre(const parser::OmpBeginDirective &x) {
 checker_(x.DirName().source, x.DirId());
 return false;
@@ -1498,14 +1494,13 @@ void OmpStructureChecker::Leave(const 
parser::OpenMPDepobjConstruct &x) {
 }
 
 void OmpStructureChecker::Enter(const parser::OpenMPRequiresConstruct &x) {
-  const auto &dir{std::get(x.t)};
-  PushContextAndClauseSets(dir.source, llvm::omp::Directive::OMPD_requires);
+  const auto &dirName{x.v.DirName()};
+  PushContextAndClauseSets(dirName.source, dirName.v);
 
   if (visitedAtomicSource_.empty()) {
 return;
   }
-  const auto &clauseList{std::get(x.t)};
-  for (const parser::OmpClause &clause : clauseList.v) {
+  for (const parser::OmpClause &clause : x.v.Clauses().v) {
 llvm::omp::Clause id{clause.Id()};
 if (id == llvm::omp::Clause::OMPC_atomic_default_mem_order) {
   parser::MessageFormattedText txt(
diff --git a/flang/lib/Semantics/resolve-directives.cpp 
b/flang/lib/Semantics/resolve-directives.cpp
index 7ef211c8b428c..a4c8922f58c6c 100644
--- a/flang/lib/Semantics/resolve-directives.cpp
+++ b/flang/lib/Semantics/resolve-directives.cpp
@@ -523,7 +523,7 @@ class OmpAttributeVisitor : 
DirectiveAttributeVisitor {

[llvm-branch-commits] [mlir] [mlir][omp] Improve canonloop/iv naming (PR #159773)

[Tom Eccles via llvm-branch-commits]

tblah wrote:

Thanks for the replies.

> Do you have a suggestion which operation? Need to be an operation that takes 
> at least two region arguments.

The reduction and privatisation declaration operations have multiple regions. I 
can't imagine why we would ever generate canonical loops inside of them but it 
should work for testing this.

https://github.com/llvm/llvm-project/pull/159773
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[llvm-branch-commits] [mlir] [mlir][omp] Improve canonloop/iv naming (PR #159773)

[Michael Kruse via llvm-branch-commits]

https://github.com/Meinersbur edited 
https://github.com/llvm/llvm-project/pull/159773
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[llvm-branch-commits] [llvm] [LoopUnroll] Fix block frequencies for epilogue (PR #159163)

[Joel E. Denny via llvm-branch-commits]

https://github.com/jdenny-ornl updated 
https://github.com/llvm/llvm-project/pull/159163

>From 5a9959313c0aebc1c707d19e30055cb925be7760 Mon Sep 17 00:00:00 2001
From: "Joel E. Denny" 
Date: Tue, 16 Sep 2025 16:03:11 -0400
Subject: [PATCH 1/5] [LoopUnroll] Fix block frequencies for epilogue

As another step in issue #135812, this patch fixes block frequencies
for partial loop unrolling with an epilogue remainder loop.  It does
not fully handle the case when the epilogue loop itself is unrolled.
That will be handled in the next patch.

For the guard and latch of each of the unrolled loop and epilogue
loop, this patch sets branch weights derived directly from the
original loop latch branch weights.  The total frequency of the
original loop body, summed across all its occurrences in the unrolled
loop and epilogue loop, is the same as in the original loop.  This
patch also sets `llvm.loop.estimated_trip_count` for the epilogue loop
instead of relying on the epilogue's latch branch weights to imply it.

This patch removes the XFAIL directives that PR #157754 added to the
test suite.
---
 .../include/llvm/Transforms/Utils/LoopUtils.h |  32 
 .../llvm/Transforms/Utils/UnrollLoop.h|   4 +-
 llvm/lib/Transforms/Utils/LoopUnroll.cpp  |  31 ++--
 .../Transforms/Utils/LoopUnrollRuntime.cpp|  94 --
 llvm/lib/Transforms/Utils/LoopUtils.cpp   |  48 ++
 .../branch-weights-freq/unroll-epilog.ll  | 160 ++
 .../runtime-exit-phi-scev-invalidation.ll |   4 +-
 .../LoopUnroll/runtime-loop-branchweight.ll   |  56 +-
 .../Transforms/LoopUnroll/runtime-loop.ll |   9 +-
 .../LoopUnroll/unroll-heuristics-pgo.ll   |  64 +--
 10 files changed, 448 insertions(+), 54 deletions(-)
 create mode 100644 
llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-epilog.ll

diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h 
b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
index c5dbb2bdd1dd8..71754b8f62a16 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
@@ -365,6 +365,38 @@ LLVM_ABI bool setLoopEstimatedTripCount(
 Loop *L, unsigned EstimatedTripCount,
 std::optional EstimatedLoopInvocationWeight = std::nullopt);
 
+/// Based on branch weight metadata, return either:
+/// - \c std::nullopt if the implementation is unable to handle the loop form
+///   of \p L (e.g., \p L must have a latch block that controls the loop exit).
+/// - Else, the estimated probability that, at the end of any iteration, the
+///   latch of \p L will start another iteration.  The result \c P is such that
+///   `0 <= P <= 1`, and `1 - P` is the probability of exiting the loop.
+std::optional getLoopProbability(Loop *L);
+
+/// Set branch weight metadata for the latch of \p L to indicate that, at the
+/// end of any iteration, its estimated probability of starting another
+/// iteration is \p P.  Return false if the implementation is unable to handle
+/// the loop form of \p L (e.g., \p L must have a latch block that controls the
+/// loop exit).  Otherwise, return true.
+bool setLoopProbability(Loop *L, double P);
+
+/// Based on branch weight metadata, return either:
+/// - \c std::nullopt if the implementation cannot extract the probability
+///   (e.g., \p B must have exactly two target labels, so it must be a
+///   conditional branch).
+/// - The probability \c P that control flows from \p B to its first target
+///   label such that `1 - P` is the probability of control flowing to its
+///   second target label, or vice-versa if \p ForFirstTarget is false.
+std::optional getBranchProbability(BranchInst *B, bool ForFirstTarget);
+
+/// Set branch weight metadata for \p B to indicate that \p P and `1 - P` are
+/// the probabilities of control flowing to its first and second target labels,
+/// respectively, or vice-versa if \p ForFirstTarget is false.  Return false if
+/// the implementation cannot set the probability (e.g., \p B must have exactly
+/// two target labels, so it must be a conditional branch).  Otherwise, return
+/// true.
+bool setBranchProbability(BranchInst *B, double P, bool ForFirstTarget);
+
 /// Check inner loop (L) backedge count is known to be invariant on all
 /// iterations of its outer loop. If the loop has no parent, this is trivially
 /// true.
diff --git a/llvm/include/llvm/Transforms/Utils/UnrollLoop.h 
b/llvm/include/llvm/Transforms/Utils/UnrollLoop.h
index 871c13d972470..571a0af6fd0db 100644
--- a/llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+++ b/llvm/include/llvm/Transforms/Utils/UnrollLoop.h
@@ -97,7 +97,9 @@ LLVM_ABI bool UnrollRuntimeLoopRemainder(
 LoopInfo *LI, ScalarEvolution *SE, DominatorTree *DT, AssumptionCache *AC,
 const TargetTransformInfo *TTI, bool PreserveLCSSA,
 unsigned SCEVExpansionBudget, bool RuntimeUnrollMultiExit,
-Loop **ResultLoop = nullptr);
+Loop **ResultLoop = nullptr,
+std::optional OriginalTripCount = std::nullopt,

[llvm-branch-commits] [flang] [llvm] [openmp] [Flang] Add standalone tile support (PR #160298)

[Tom Eccles via llvm-branch-commits]

https://github.com/tblah approved this pull request.

LGTM, thanks

https://github.com/llvm/llvm-project/pull/160298
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[llvm-branch-commits] [flang] [llvm] [openmp] [Flang] Add standalone tile support (PR #160298)

[Tom Eccles via llvm-branch-commits]

@@ -0,0 +1,31 @@
+! This test checks lowering of the OpenMP tile directive
+! It is done 3 times corresponding to every possible fraction of the last
+! iteration before passing beyond UB.
+
+! RUN: %flang %flags %openmp_flags -fopenmp-version=51 -DUB=16 %s -o 
%t-ub16.exe

tblah wrote:

That sounds okay to me. Thank you for the detailed explanation.

https://github.com/llvm/llvm-project/pull/160298
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[llvm-branch-commits] [mlir] [mlir][omp] Add omp.tile operation (PR #160292)

[Tom Eccles via llvm-branch-commits]

https://github.com/tblah approved this pull request.

Looks great!

https://github.com/llvm/llvm-project/pull/160292
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[llvm-branch-commits] [llvm] [LoongArch] Custom legalize vector_shuffle to `xvinsve0.{w/d}` when possible (PR #160857)

[via llvm-branch-commits]

https://github.com/zhaoqi5 created 
https://github.com/llvm/llvm-project/pull/160857

None

>From f0b8917ccc6109e64d16f2bc4966f2696843b5e7 Mon Sep 17 00:00:00 2001
From: Qi Zhao 
Date: Fri, 26 Sep 2025 19:07:22 +0800
Subject: [PATCH] [LoongArch] Custom legalize vector_shuffle to
 `xvinsve0.{w/d}` when possible

---
 .../LoongArch/LoongArchISelLowering.cpp   |  52 ++
 .../Target/LoongArch/LoongArchISelLowering.h  |   1 +
 .../LoongArch/LoongArchLASXInstrInfo.td   |   9 +
 .../ir-instruction/shuffle-as-xvinsve0.ll | 704 +++---
 4 files changed, 180 insertions(+), 586 deletions(-)

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 5d4a8fd080202..194f42995d55a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2317,6 +2317,54 @@ static SDValue lowerVECTOR_SHUFFLE_XVPICKOD(const SDLoc 
&DL, ArrayRef Mask,
   return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
 }
 
+// Check if exactly one element of the Mask is replaced by 'Replaced', while
+// all other elements are either 'Base + i' or undef (-1). On success, return
+// the index of the replaced element. Otherwise, just return -1.
+static int checkReplaceOne(ArrayRef Mask, int Base, int Replaced) {
+  int MaskSize = Mask.size();
+  int Idx = -1;
+  for (int i = 0; i < MaskSize; ++i) {
+if (Mask[i] == Base + i || Mask[i] == -1)
+  continue;
+if (Mask[i] != Replaced)
+  return -1;
+if (Idx == -1)
+  Idx = i;
+else
+  return -1;
+  }
+  return Idx;
+}
+
+/// Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).
+static SDValue
+lowerVECTOR_SHUFFLE_XVINSVE0(const SDLoc &DL, ArrayRef Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
+  // LoongArch LASX only supports xvinsve0.{w/d}.
+  if (VT != MVT::v8i32 && VT != MVT::v8f32 && VT != MVT::v4i64 &&
+  VT != MVT::v4f64)
+return SDValue();
+
+  MVT GRLenVT = Subtarget.getGRLenVT();
+  int MaskSize = Mask.size();
+  assert(MaskSize == (int)VT.getVectorNumElements() && "Unexpected mask size");
+
+  // Case 1: the lowest element of V2 replaces one element in V1.
+  int Idx = checkReplaceOne(Mask, 0, MaskSize);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V1, V2,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  // Case 2: the lowest element of V1 replaces one element in V2.
+  Idx = checkReplaceOne(Mask, MaskSize, 0);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V2, V1,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  return SDValue();
+}
+
 /// Lower VECTOR_SHUFFLE into XVSHUF (if possible).
 static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef Mask,
   MVT VT, SDValue V1, SDValue V2,
@@ -2593,6 +2641,9 @@ static SDValue lower256BitShuffle(const SDLoc &DL, 
ArrayRef Mask, MVT VT,
   if ((Result = lowerVECTOR_SHUFFLEAsShift(DL, Mask, VT, V1, V2, DAG, 
Subtarget,
Zeroable)))
 return Result;
+  if ((Result =
+   lowerVECTOR_SHUFFLE_XVINSVE0(DL, Mask, VT, V1, V2, DAG, Subtarget)))
+return Result;
   if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG,
 Subtarget)))
 return Result;
@@ -7450,6 +7501,7 @@ const char 
*LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
 NODE_NAME_CASE(XVPERM)
 NODE_NAME_CASE(XVREPLVE0)
 NODE_NAME_CASE(XVREPLVE0Q)
+NODE_NAME_CASE(XVINSVE0)
 NODE_NAME_CASE(VPICK_SEXT_ELT)
 NODE_NAME_CASE(VPICK_ZEXT_ELT)
 NODE_NAME_CASE(VREPLVE)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index b2fccf59169ff..3e7ea5ebba79e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -151,6 +151,7 @@ enum NodeType : unsigned {
   XVPERM,
   XVREPLVE0,
   XVREPLVE0Q,
+  XVINSVE0,
 
   // Extended vector element extraction
   VPICK_SEXT_ELT,
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td 
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index adfe990ba1234..dfcbfff2a9a72 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -20,6 +20,7 @@ def loongarch_xvpermi: SDNode<"LoongArchISD::XVPERMI", 
SDT_LoongArchV1RUimm>;
 def loongarch_xvperm: SDNode<"LoongArchISD::XVPERM", SDT_LoongArchXVPERM>;
 def loongarch_xvreplve0: SDNode<"LoongArchISD::XVREPLVE0", 
SDT_LoongArchXVREPLVE0>;
 def loongarch_xvreplve0q: SDNode<"LoongArchISD::XVREPLVE0Q", 
SDT_LoongArchXVREPLVE0>;
+def loongarch_xvinsve0 : SDNode<"LoongArchISD::XVINSVE0", 
SDT_LoongArchV2RUimm>;
 def loongarch

[llvm-branch-commits] [llvm] [AllocToken] Introduce AllocToken instrumentation pass (PR #156838)

[Nikita Popov via llvm-branch-commits]

@@ -0,0 +1,469 @@
+//===- AllocToken.cpp - Allocation token instrumentation 
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements AllocToken, an instrumentation pass that
+// replaces allocation calls with token-enabled versions.
+//
+//===--===//
+
+#include "llvm/Transforms/Instrumentation/AllocToken.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/MemoryBuiltins.h"
+#include "llvm/Analysis/OptimizationRemarkEmitter.h"
+#include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/IR/Analysis.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/InstrTypes.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/Metadata.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/PassManager.h"
+#include "llvm/IR/Type.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/RandomNumberGenerator.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/xxhash.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+using namespace llvm;
+
+#define DEBUG_TYPE "alloc-token"
+
+namespace {
+
+//===--- Constants 
===//
+
+enum class TokenMode : unsigned {
+  /// Incrementally increasing token ID.
+  Increment = 0,
+
+  /// Simple mode that returns a statically-assigned random token ID.
+  Random = 1,
+
+  /// Token ID based on allocated type hash.
+  TypeHash = 2,
+};
+
+//===--- Command-line options 
-===//
+
+cl::opt
+ClMode("alloc-token-mode", cl::Hidden, cl::desc("Token assignment mode"),
+   cl::init(TokenMode::TypeHash),
+   cl::values(clEnumValN(TokenMode::Increment, "increment",
+ "Incrementally increasing token ID"),
+  clEnumValN(TokenMode::Random, "random",
+ "Statically-assigned random token ID"),
+  clEnumValN(TokenMode::TypeHash, "typehash",
+ "Token ID based on allocated type hash")));
+
+cl::opt ClFuncPrefix("alloc-token-prefix",
+  cl::desc("The allocation function prefix"),
+  cl::Hidden, cl::init("__alloc_token_"));
+
+cl::opt ClMaxTokens("alloc-token-max",
+  cl::desc("Maximum number of tokens (0 = no 
max)"),
+  cl::Hidden, cl::init(0));
+
+cl::opt
+ClFastABI("alloc-token-fast-abi",
+  cl::desc("The token ID is encoded in the function name"),
+  cl::Hidden, cl::init(false));
+
+// Instrument libcalls only by default - compatible allocators only need to 
take
+// care of providing standard allocation functions. With extended coverage, 
also
+// instrument non-libcall allocation function calls with !alloc_token
+// metadata.
+cl::opt
+ClExtended("alloc-token-extended",
+   cl::desc("Extend coverage to custom allocation functions"),
+   cl::Hidden, cl::init(false));
+
+// C++ defines ::operator new (and variants) as replaceable (vs. standard
+// library versions), which are nobuiltin, and are therefore not covered by
+// isAllocationFn(). Cover by default, as users of AllocToken are already
+// required to provide token-aware allocation functions (no defaults).
+cl::opt ClCoverReplaceableNew("alloc-token-cover-replaceable-new",
+cl::desc("Cover replaceable operator new"),
+cl::Hidden, cl::init(true));
+
+cl::opt ClFallbackToken(
+"alloc-token-fallback",
+cl::desc("The default fallback token where none could be determined"),
+cl::Hidden, cl::init(0));
+
+//===--- Statistics 
---===//
+
+STATISTIC(NumFunctionsInstrumented, "Functions instrumented");
+STATISTIC(NumAllocationsInstrumented, "Allocations instrumented");
+
+//===--===//
+
+/// Returns the !alloc_token metadata if available.
+///
+/// Expected format is: !{}
+MDNode *getAllocTokenMetadata(const 

[llvm-branch-commits] [llvm] [LoongArch] Custom legalize vector_shuffle to `xvinsve0.{w/d}` when possible (PR #160857)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-loongarch

Author: ZhaoQi (zhaoqi5)


Changes



---

Patch is 39.04 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/160857.diff


4 Files Affected:

- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+52) 
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.h (+1) 
- (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+9) 
- (modified) 
llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvinsve0.ll 
(+118-586) 


``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 5d4a8fd080202..194f42995d55a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2317,6 +2317,54 @@ static SDValue lowerVECTOR_SHUFFLE_XVPICKOD(const SDLoc 
&DL, ArrayRef Mask,
   return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
 }
 
+// Check if exactly one element of the Mask is replaced by 'Replaced', while
+// all other elements are either 'Base + i' or undef (-1). On success, return
+// the index of the replaced element. Otherwise, just return -1.
+static int checkReplaceOne(ArrayRef Mask, int Base, int Replaced) {
+  int MaskSize = Mask.size();
+  int Idx = -1;
+  for (int i = 0; i < MaskSize; ++i) {
+if (Mask[i] == Base + i || Mask[i] == -1)
+  continue;
+if (Mask[i] != Replaced)
+  return -1;
+if (Idx == -1)
+  Idx = i;
+else
+  return -1;
+  }
+  return Idx;
+}
+
+/// Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).
+static SDValue
+lowerVECTOR_SHUFFLE_XVINSVE0(const SDLoc &DL, ArrayRef Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
+  // LoongArch LASX only supports xvinsve0.{w/d}.
+  if (VT != MVT::v8i32 && VT != MVT::v8f32 && VT != MVT::v4i64 &&
+  VT != MVT::v4f64)
+return SDValue();
+
+  MVT GRLenVT = Subtarget.getGRLenVT();
+  int MaskSize = Mask.size();
+  assert(MaskSize == (int)VT.getVectorNumElements() && "Unexpected mask size");
+
+  // Case 1: the lowest element of V2 replaces one element in V1.
+  int Idx = checkReplaceOne(Mask, 0, MaskSize);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V1, V2,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  // Case 2: the lowest element of V1 replaces one element in V2.
+  Idx = checkReplaceOne(Mask, MaskSize, 0);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V2, V1,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  return SDValue();
+}
+
 /// Lower VECTOR_SHUFFLE into XVSHUF (if possible).
 static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef Mask,
   MVT VT, SDValue V1, SDValue V2,
@@ -2593,6 +2641,9 @@ static SDValue lower256BitShuffle(const SDLoc &DL, 
ArrayRef Mask, MVT VT,
   if ((Result = lowerVECTOR_SHUFFLEAsShift(DL, Mask, VT, V1, V2, DAG, 
Subtarget,
Zeroable)))
 return Result;
+  if ((Result =
+   lowerVECTOR_SHUFFLE_XVINSVE0(DL, Mask, VT, V1, V2, DAG, Subtarget)))
+return Result;
   if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG,
 Subtarget)))
 return Result;
@@ -7450,6 +7501,7 @@ const char 
*LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
 NODE_NAME_CASE(XVPERM)
 NODE_NAME_CASE(XVREPLVE0)
 NODE_NAME_CASE(XVREPLVE0Q)
+NODE_NAME_CASE(XVINSVE0)
 NODE_NAME_CASE(VPICK_SEXT_ELT)
 NODE_NAME_CASE(VPICK_ZEXT_ELT)
 NODE_NAME_CASE(VREPLVE)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index b2fccf59169ff..3e7ea5ebba79e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -151,6 +151,7 @@ enum NodeType : unsigned {
   XVPERM,
   XVREPLVE0,
   XVREPLVE0Q,
+  XVINSVE0,
 
   // Extended vector element extraction
   VPICK_SEXT_ELT,
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td 
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index adfe990ba1234..dfcbfff2a9a72 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -20,6 +20,7 @@ def loongarch_xvpermi: SDNode<"LoongArchISD::XVPERMI", 
SDT_LoongArchV1RUimm>;
 def loongarch_xvperm: SDNode<"LoongArchISD::XVPERM", SDT_LoongArchXVPERM>;
 def loongarch_xvreplve0: SDNode<"LoongArchISD::XVREPLVE0", 
SDT_LoongArchXVREPLVE0>;
 def loongarch_xvreplve0q: SDNode<"LoongArchISD::XVREPLVE0Q", 
SDT_LoongArchXVREPLVE0>;
+def loongarch_xvinsve0 : SDNode<"LoongArchISD::XVINSVE0", 
SDT_LoongArchV2RUimm>;
 def loongarch_xvmskltz: SDNode<"LoongArchISD::XVMSKLTZ

[llvm-branch-commits] [lld] release/21.x: [LLD] [COFF] Fix symbol names for import thunks (#160694) (PR #160770)

[Jacek Caban via llvm-branch-commits]

https://github.com/cjacek approved this pull request.


https://github.com/llvm/llvm-project/pull/160770
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[llvm-branch-commits] [llvm] 9119e5c - Revert "[WebAssembly] Remove FAKE_USEs before ExplicitLocals (#160228)"

[via llvm-branch-commits]

Author: Derek Schuff
Date: 2025-09-24T09:22:03-07:00
New Revision: 9119e5cb91a81ec07a84dca19b88960f501b46e7

URL: 
https://github.com/llvm/llvm-project/commit/9119e5cb91a81ec07a84dca19b88960f501b46e7
DIFF: 
https://github.com/llvm/llvm-project/commit/9119e5cb91a81ec07a84dca19b88960f501b46e7.diff

LOG: Revert "[WebAssembly] Remove FAKE_USEs before ExplicitLocals (#160228)"

This reverts commit d27654f9d8e2d0637a2f3de0d2aad7d70b3f71f8.

Added: 


Modified: 
llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

Removed: 
llvm/test/CodeGen/WebAssembly/fake-use.ll



diff  --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 
b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
index 5c3127e2d3dc6..e6486e247209b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
@@ -216,18 +216,6 @@ static MachineInstr *findStartOfTree(MachineOperand &MO,
   return Def;
 }
 
-// FAKE_USEs are no-ops, so remove them here so that the values used by them
-// will be correctly dropped later.
-static void removeFakeUses(MachineFunction &MF) {
-  SmallVector ToDelete;
-  for (auto &MBB : MF)
-for (auto &MI : MBB)
-  if (MI.isFakeUse())
-ToDelete.push_back(&MI);
-  for (auto *MI : ToDelete)
-MI->eraseFromParent();
-}
-
 bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "** Make Locals Explicit **\n"
"** Function: "
@@ -238,8 +226,6 @@ bool 
WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
   WebAssemblyFunctionInfo &MFI = *MF.getInfo();
   const auto *TII = MF.getSubtarget().getInstrInfo();
 
-  removeFakeUses(MF);
-
   // Map non-stackified virtual registers to their local ids.
   DenseMap Reg2Local;
 

diff  --git a/llvm/test/CodeGen/WebAssembly/fake-use.ll 
b/llvm/test/CodeGen/WebAssembly/fake-use.ll
deleted file mode 100644
index d5732e628440a..0
--- a/llvm/test/CodeGen/WebAssembly/fake-use.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc < %s | llvm-mc -triple=wasm32-unknown-unknown
-
-target triple = "wasm32-unknown-unknown"
-
-define void @fake_use_test() {
-  %t = call i32 @foo()
-  tail call void (...) @llvm.fake.use(i32 %t)
-  ret void
-}
-
-declare void @foo()
-; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn 
memory(inaccessiblemem: readwrite)
-declare void @llvm.fake.use(...) #0
-
-attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn 
memory(inaccessiblemem: readwrite) }



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[llvm-branch-commits] [llvm] [LoongArch] Introduce instruction patterns for vector sign/zero extensions (PR #160810)

[via llvm-branch-commits]

tangaac wrote:

For LSX zext, I believe previous behavior is the best practice.
For LSX sext,  vector element sext as twice element size, the best practice is 
like below:
``` llvm
%B = sext <4 x i16> %A to <4 x i32>
vslti.h v2, v1, 0
vilvl.h v1, v2, v1 

%B = sext <4 x i32> %A to <4 x i64>
vslti.w v3, v1, 0
vilvh.w v2, v3, v1
vilvl.w v1, v3, v1
```


https://github.com/llvm/llvm-project/pull/160810
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[llvm-branch-commits] [mlir] [mlir][omp] Improve canonloop/iv naming (PR #159773)

[Michael Kruse via llvm-branch-commits]

@@ -77,6 +77,177 @@ struct LLVMPointerPointerLikeModel
 };
 } // namespace
 
+/// Generate a name of a canonical loop nest of the format
+/// `(_s_r)*` that describes its nesting inside parent
+/// operations (`_r`) and that operation's region (`_s`). The region
+/// number is omitted if the parent operation has just one region. If a loop
+/// nest just consists of canonical loops nested inside each other, also uses
+/// `d` where  is the nesting depth of the loop.
+static std::string generateLoopNestingName(StringRef prefix,
+   CanonicalLoopOp op) {
+  struct Component {
+// An region argument of an operation
+Operation *parentOp;
+size_t regionInOpIdx;
+bool isOnlyRegionInOp;
+bool skipRegion;
+
+// An operation somewhere in a parent region
+Operation *thisOp;
+Region *parentRegion;
+size_t opInRegionIdx;
+bool isOnlyOpInRegion;
+bool skipOp;
+int depth = -1;
+  };
+  SmallVector components;
+
+  // Gather a list of parent regions and operations, and the position within
+  // their parent
+  Operation *o = op.getOperation();
+  while (o) {
+if (o->hasTrait())
+  break;
+
+// Operation within a region
+Region *r = o->getParentRegion();
+if (!r)
+  break;
+
+llvm::ReversePostOrderTraversal 
traversal(&r->getBlocks().front());
+size_t idx = 0;
+bool found = false;
+size_t sequentialIdx = -1;
+bool isOnlyLoop = true;
+for (Block *b : traversal) {
+  for (Operation &op : *b) {
+if (&op == o && !found) {
+  sequentialIdx = idx;
+  found = true;
+}
+if (op.getNumRegions()) {
+  idx += 1;
+  if (idx > 1)
+isOnlyLoop = false;
+}
+if (found && !isOnlyLoop)
+  break;
+  }
+}
+
+Component &comp = components.emplace_back();
+comp.thisOp = o;
+comp.parentRegion = r;
+comp.opInRegionIdx = sequentialIdx;
+comp.isOnlyOpInRegion = isOnlyLoop;
+
+// Region argument of an operation
+Operation *parent = r->getParentOp();
+
+comp.parentOp = parent;
+comp.regionInOpIdx = 0;
+comp.isOnlyRegionInOp = true;
+if (parent && parent->getRegions().size() > 1) {
+  auto getRegionIndex = [](Operation *o, Region *r) {
+for (auto [idx, region] : llvm::enumerate(o->getRegions())) {
+  if (®ion == r)
+return idx;
+}
+llvm_unreachable("Region not child of its parent operation");
+  };
+  comp.regionInOpIdx = getRegionIndex(parent, r);
+  comp.isOnlyRegionInOp = false;
+}
+
+if (!parent)
+  break;
+
+// next parent
+o = parent;
+  }
+
+  // Reorder components from outermost to innermost
+  std::reverse(components.begin(), components.end());

Meinersbur wrote:

I already experimented using `llvm::reverse` iterators instead of explicitly 
reversing it. But it also found that it makes `mergeLoopNest` (which uses 
indices to access the next/previous loop) harder to understand. We need to 
iterate from outer to inner[^1], and starting with index 0, and +1 being the 
next component, just felt more natural.

[^1]: Iterating up to a components gets us to that component's name and the 
next iteration can just add to that sourrounding's loop's name.

https://github.com/llvm/llvm-project/pull/159773
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[llvm-branch-commits] [mlir] [mlir][omp] Improve canonloop/iv naming (PR #159773)

[Tom Eccles via llvm-branch-commits]

@@ -77,6 +77,177 @@ struct LLVMPointerPointerLikeModel
 };
 } // namespace
 
+/// Generate a name of a canonical loop nest of the format
+/// `(_s_r)*` that describes its nesting inside parent
+/// operations (`_r`) and that operation's region (`_s`). The region
+/// number is omitted if the parent operation has just one region. If a loop
+/// nest just consists of canonical loops nested inside each other, also uses
+/// `d` where  is the nesting depth of the loop.
+static std::string generateLoopNestingName(StringRef prefix,
+   CanonicalLoopOp op) {
+  struct Component {
+// An region argument of an operation
+Operation *parentOp;
+size_t regionInOpIdx;
+bool isOnlyRegionInOp;
+bool skipRegion;
+
+// An operation somewhere in a parent region
+Operation *thisOp;
+Region *parentRegion;
+size_t opInRegionIdx;
+bool isOnlyOpInRegion;
+bool skipOp;
+int depth = -1;
+  };
+  SmallVector components;
+
+  // Gather a list of parent regions and operations, and the position within
+  // their parent
+  Operation *o = op.getOperation();
+  while (o) {
+if (o->hasTrait())
+  break;
+
+// Operation within a region
+Region *r = o->getParentRegion();
+if (!r)
+  break;
+
+llvm::ReversePostOrderTraversal 
traversal(&r->getBlocks().front());
+size_t idx = 0;
+bool found = false;
+size_t sequentialIdx = -1;
+bool isOnlyLoop = true;
+for (Block *b : traversal) {
+  for (Operation &op : *b) {
+if (&op == o && !found) {
+  sequentialIdx = idx;
+  found = true;
+}
+if (op.getNumRegions()) {
+  idx += 1;
+  if (idx > 1)
+isOnlyLoop = false;
+}
+if (found && !isOnlyLoop)
+  break;
+  }
+}
+
+Component &comp = components.emplace_back();
+comp.thisOp = o;
+comp.parentRegion = r;
+comp.opInRegionIdx = sequentialIdx;
+comp.isOnlyOpInRegion = isOnlyLoop;
+
+// Region argument of an operation
+Operation *parent = r->getParentOp();
+
+comp.parentOp = parent;
+comp.regionInOpIdx = 0;
+comp.isOnlyRegionInOp = true;
+if (parent && parent->getRegions().size() > 1) {
+  auto getRegionIndex = [](Operation *o, Region *r) {
+for (auto [idx, region] : llvm::enumerate(o->getRegions())) {
+  if (®ion == r)
+return idx;
+}
+llvm_unreachable("Region not child of its parent operation");
+  };
+  comp.regionInOpIdx = getRegionIndex(parent, r);
+  comp.isOnlyRegionInOp = false;
+}
+
+if (!parent)
+  break;
+
+// next parent
+o = parent;
+  }
+
+  // Reorder components from outermost to innermost
+  std::reverse(components.begin(), components.end());

tblah wrote:

Okay sounds good to me.

https://github.com/llvm/llvm-project/pull/159773
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[llvm-branch-commits] [llvm] [LoongArch] Custom legalize vector_shuffle to `xvinsve0.{w/d}` when possible (PR #160857)

[via llvm-branch-commits]

https://github.com/zhaoqi5 updated 
https://github.com/llvm/llvm-project/pull/160857

>From f8c413dcb8cb641d94770df48eff80e6dd8a21fb Mon Sep 17 00:00:00 2001
From: Qi Zhao 
Date: Fri, 26 Sep 2025 19:07:22 +0800
Subject: [PATCH 1/2] [LoongArch] Custom legalize vector_shuffle to
 `xvinsve0.{w/d}` when possible

---
 .../LoongArch/LoongArchISelLowering.cpp   | 52 +++
 .../Target/LoongArch/LoongArchISelLowering.h  |  1 +
 .../LoongArch/LoongArchLASXInstrInfo.td   |  9 
 .../ir-instruction/shuffle-as-xvinsve0.ll |  4 +-
 4 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 5d4a8fd080202..194f42995d55a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2317,6 +2317,54 @@ static SDValue lowerVECTOR_SHUFFLE_XVPICKOD(const SDLoc 
&DL, ArrayRef Mask,
   return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
 }
 
+// Check if exactly one element of the Mask is replaced by 'Replaced', while
+// all other elements are either 'Base + i' or undef (-1). On success, return
+// the index of the replaced element. Otherwise, just return -1.
+static int checkReplaceOne(ArrayRef Mask, int Base, int Replaced) {
+  int MaskSize = Mask.size();
+  int Idx = -1;
+  for (int i = 0; i < MaskSize; ++i) {
+if (Mask[i] == Base + i || Mask[i] == -1)
+  continue;
+if (Mask[i] != Replaced)
+  return -1;
+if (Idx == -1)
+  Idx = i;
+else
+  return -1;
+  }
+  return Idx;
+}
+
+/// Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).
+static SDValue
+lowerVECTOR_SHUFFLE_XVINSVE0(const SDLoc &DL, ArrayRef Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
+  // LoongArch LASX only supports xvinsve0.{w/d}.
+  if (VT != MVT::v8i32 && VT != MVT::v8f32 && VT != MVT::v4i64 &&
+  VT != MVT::v4f64)
+return SDValue();
+
+  MVT GRLenVT = Subtarget.getGRLenVT();
+  int MaskSize = Mask.size();
+  assert(MaskSize == (int)VT.getVectorNumElements() && "Unexpected mask size");
+
+  // Case 1: the lowest element of V2 replaces one element in V1.
+  int Idx = checkReplaceOne(Mask, 0, MaskSize);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V1, V2,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  // Case 2: the lowest element of V1 replaces one element in V2.
+  Idx = checkReplaceOne(Mask, MaskSize, 0);
+  if (Idx != -1)
+return DAG.getNode(LoongArchISD::XVINSVE0, DL, VT, V2, V1,
+   DAG.getConstant(Idx, DL, GRLenVT));
+
+  return SDValue();
+}
+
 /// Lower VECTOR_SHUFFLE into XVSHUF (if possible).
 static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef Mask,
   MVT VT, SDValue V1, SDValue V2,
@@ -2593,6 +2641,9 @@ static SDValue lower256BitShuffle(const SDLoc &DL, 
ArrayRef Mask, MVT VT,
   if ((Result = lowerVECTOR_SHUFFLEAsShift(DL, Mask, VT, V1, V2, DAG, 
Subtarget,
Zeroable)))
 return Result;
+  if ((Result =
+   lowerVECTOR_SHUFFLE_XVINSVE0(DL, Mask, VT, V1, V2, DAG, Subtarget)))
+return Result;
   if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG,
 Subtarget)))
 return Result;
@@ -7450,6 +7501,7 @@ const char 
*LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
 NODE_NAME_CASE(XVPERM)
 NODE_NAME_CASE(XVREPLVE0)
 NODE_NAME_CASE(XVREPLVE0Q)
+NODE_NAME_CASE(XVINSVE0)
 NODE_NAME_CASE(VPICK_SEXT_ELT)
 NODE_NAME_CASE(VPICK_ZEXT_ELT)
 NODE_NAME_CASE(VREPLVE)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h 
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index b2fccf59169ff..3e7ea5ebba79e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -151,6 +151,7 @@ enum NodeType : unsigned {
   XVPERM,
   XVREPLVE0,
   XVREPLVE0Q,
+  XVINSVE0,
 
   // Extended vector element extraction
   VPICK_SEXT_ELT,
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td 
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index adfe990ba1234..dfcbfff2a9a72 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -20,6 +20,7 @@ def loongarch_xvpermi: SDNode<"LoongArchISD::XVPERMI", 
SDT_LoongArchV1RUimm>;
 def loongarch_xvperm: SDNode<"LoongArchISD::XVPERM", SDT_LoongArchXVPERM>;
 def loongarch_xvreplve0: SDNode<"LoongArchISD::XVREPLVE0", 
SDT_LoongArchXVREPLVE0>;
 def loongarch_xvreplve0q: SDNode<"LoongArchISD::XVREPLVE0Q", 
SDT_LoongArchXVREPLVE0>;
+def loongarch_xvinsve0 : SDNode<"LoongArchISD::XVINSVE0", 
SDT_LoongArchV2RUimm>;
 def loongarch_xvms

[llvm-branch-commits] [clang] release/21.x: Generalize test over 32 and 64bit targets (PR #160680)

[via llvm-branch-commits]

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/160680
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[llvm-branch-commits] [clang] [clang] fix transformation of subst constant template parameter nodes (PR #160777)

[Erich Keane via llvm-branch-commits]

@@ -113,7 +113,7 @@ using Bar = Foo; // expected-note {{candidate 
template ignored: co
// expected-note {{implicit deduction guide 
declared as 'template  requires __is_deducible(test9::Bar, 
test9::Foo) Bar(test9::Foo) -> test9::Foo'}} \
// expected-note {{implicit deduction guide 
declared as 'template  requires __is_deducible(test9::Bar, 
test9::Foo) Bar(const X (&)[sizeof(X)]) -> test9::Foo'}} \
// expected-note {{candidate template ignored: 
constraints not satisfied [with X = int]}} \
-   // expected-note {{cannot deduce template 
arguments for 'test9::Bar' from 'test9::Foo'}}
+   // expected-note {{cannot deduce template 
arguments for 'test9::Bar' from 'test9::Foo'}}

erichkeane wrote:

Isn't it the opposite?  It goes from the value to a slightly sugared value?

https://github.com/llvm/llvm-project/pull/160777
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sam Tebbs via llvm-branch-commits]

https://github.com/SamTebbs33 updated 
https://github.com/llvm/llvm-project/pull/160154

>From 1e26f885620a00e9733102c36dd626552cb9dda5 Mon Sep 17 00:00:00 2001
From: Sam Tebbs 
Date: Mon, 22 Sep 2025 17:16:40 +0100
Subject: [PATCH 1/5] [LV] Add ExtNegatedMulAccReduction expression type

This PR adds the ExtNegatedMulAccReduction expression type for
VPExpressionRecipe so that extend-multiply-accumulate reductions with a
negated multiply can be bundled.

Stacked PRs:

1. https://github.com/llvm/llvm-project/pull/156976
2. -> This
3. https://github.com/llvm/llvm-project/pull/147302
---
 llvm/lib/Transforms/Vectorize/VPlan.h |  11 ++
 .../lib/Transforms/Vectorize/VPlanRecipes.cpp |  31 -
 .../Transforms/Vectorize/VPlanTransforms.cpp  |  46 ---
 .../vplan-printing-reductions.ll  | 121 ++
 4 files changed, 192 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h 
b/llvm/lib/Transforms/Vectorize/VPlan.h
index e6f6067bc9df3..1cb0c889528ec 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -2989,6 +2989,12 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
 /// vector operands, performing a reduction.add on the result, and adding
 /// the scalar result to a chain.
 MulAccReduction,
+/// Represent an inloop multiply-accumulate reduction, multiplying the
+/// extended vector operands, negating the multiplication, performing a
+/// reduction.add
+/// on the result, and adding
+/// the scalar result to a chain.
+ExtNegatedMulAccReduction,
   };
 
   /// Type of the expression.
@@ -3012,6 +3018,11 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
  VPWidenRecipe *Mul, VPReductionRecipe *Red)
   : VPExpressionRecipe(ExpressionTypes::ExtMulAccReduction,
{Ext0, Ext1, Mul, Red}) {}
+  VPExpressionRecipe(VPWidenCastRecipe *Ext0, VPWidenCastRecipe *Ext1,
+ VPWidenRecipe *Mul, VPWidenRecipe *Sub,
+ VPReductionRecipe *Red)
+  : VPExpressionRecipe(ExpressionTypes::ExtNegatedMulAccReduction,
+   {Ext0, Ext1, Mul, Sub, Red}) {}
 
   ~VPExpressionRecipe() override {
 SmallSet ExpressionRecipesSeen;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp 
b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 4568d4f37a751..02be0db102547 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2861,12 +2861,17 @@ InstructionCost 
VPExpressionRecipe::computeCost(ElementCount VF,
 return Ctx.TTI.getMulAccReductionCost(false, Opcode, RedTy, SrcVecTy,
   Ctx.CostKind);
 
-  case ExpressionTypes::ExtMulAccReduction:
+  case ExpressionTypes::ExtNegatedMulAccReduction:
+  case ExpressionTypes::ExtMulAccReduction: {
+if (ExpressionType == ExpressionTypes::ExtNegatedMulAccReduction &&
+Opcode == Instruction::Add)
+  Opcode = Instruction::Sub;
 return Ctx.TTI.getMulAccReductionCost(
 cast(ExpressionRecipes.front())->getOpcode() ==
 Instruction::ZExt,
 Opcode, RedTy, SrcVecTy, Ctx.CostKind);
   }
+  }
   llvm_unreachable("Unknown VPExpressionRecipe::ExpressionTypes enum");
 }
 
@@ -2912,6 +2917,30 @@ void VPExpressionRecipe::print(raw_ostream &O, const 
Twine &Indent,
 O << ")";
 break;
   }
+  case ExpressionTypes::ExtNegatedMulAccReduction: {
+getOperand(getNumOperands() - 1)->printAsOperand(O, SlotTracker);
+O << " + reduce."
+  << Instruction::getOpcodeName(
+ RecurrenceDescriptor::getOpcode(Red->getRecurrenceKind()))
+  << " (sub (0, mul";
+auto *Mul = cast(ExpressionRecipes[2]);
+Mul->printFlags(O);
+O << "(";
+getOperand(0)->printAsOperand(O, SlotTracker);
+auto *Ext0 = cast(ExpressionRecipes[0]);
+O << " " << Instruction::getOpcodeName(Ext0->getOpcode()) << " to "
+  << *Ext0->getResultType() << "), (";
+getOperand(1)->printAsOperand(O, SlotTracker);
+auto *Ext1 = cast(ExpressionRecipes[1]);
+O << " " << Instruction::getOpcodeName(Ext1->getOpcode()) << " to "
+  << *Ext1->getResultType() << ")";
+if (Red->isConditional()) {
+  O << ", ";
+  Red->getCondOp()->printAsOperand(O, SlotTracker);
+}
+O << "))";
+break;
+  }
   case ExpressionTypes::MulAccReduction:
   case ExpressionTypes::ExtMulAccReduction: {
 getOperand(getNumOperands() - 1)->printAsOperand(O, SlotTracker);
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp 
b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 1f6b85270607e..ca89c4fa0d2e6 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -3524,14 +3524,22 @@ 
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
   };
 
   VPValue *VecOp = Red->getVecOp();
+  VPValue *Mul = 

[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sam Tebbs via llvm-branch-commits]

@@ -3012,6 +3018,11 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
  VPWidenRecipe *Mul, VPReductionRecipe *Red)
   : VPExpressionRecipe(ExpressionTypes::ExtMulAccReduction,
{Ext0, Ext1, Mul, Red}) {}
+  VPExpressionRecipe(VPWidenCastRecipe *Ext0, VPWidenCastRecipe *Ext1,
+ VPWidenRecipe *Mul, VPWidenRecipe *Sub,
+ VPReductionRecipe *Red)
+  : VPExpressionRecipe(ExpressionTypes::ExtNegatedMulAccReduction,
+   {Ext0, Ext1, Mul, Sub, Red}) {}

SamTebbs33 wrote:

Done.

https://github.com/llvm/llvm-project/pull/160154
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[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

[Marco Elver via llvm-branch-commits]

@@ -0,0 +1,157 @@
+// RUN: %clang_cc1-fsanitize=alloc-token -falloc-token-max=2147483647 
-triple x86_64-linux-gnu -std=c++20 -fexceptions -fcxx-exceptions -emit-llvm %s 
-o - | FileCheck %s
+// RUN: %clang_cc1 -O -fsanitize=alloc-token -falloc-token-max=2147483647 
-triple x86_64-linux-gnu -std=c++20 -fexceptions -fcxx-exceptions -emit-llvm %s 
-o - | FileCheck %s
+
+#include "../Analysis/Inputs/system-header-simulator-cxx.h"

melver wrote:

Maybe this could be moved somewhere else, but it's either that or redefining 
what's in that header here.

https://github.com/llvm/llvm-project/pull/156839
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[llvm-branch-commits] [llvm] 22e10bb - Revert "[RegAlloc] Strengthen asserts in LiveRangeEdit::scanRemattable [nfc] …"

[via llvm-branch-commits]

Author: Philip Reames
Date: 2025-09-26T07:55:18-07:00
New Revision: 22e10bb12cab65673e7259c63f322208761a0da6

URL: 
https://github.com/llvm/llvm-project/commit/22e10bb12cab65673e7259c63f322208761a0da6
DIFF: 
https://github.com/llvm/llvm-project/commit/22e10bb12cab65673e7259c63f322208761a0da6.diff

LOG: Revert "[RegAlloc] Strengthen asserts in LiveRangeEdit::scanRemattable 
[nfc] …"

This reverts commit bba91727789bed302758dac282107a44c7b33504.

Added: 


Modified: 
llvm/lib/CodeGen/LiveRangeEdit.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp 
b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index 4aeacc332476d..59bc82dc267b5 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -75,11 +75,11 @@ void LiveRangeEdit::scanRemattable() {
 Register Original = VRM->getOriginal(getReg());
 LiveInterval &OrigLI = LIS.getInterval(Original);
 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
-assert(OrigVNI && "Corrupt interval mapping?");
-if (OrigVNI->isPHIDef())
+if (!OrigVNI)
   continue;
 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
-assert(DefMI && "Missing instruction for def slot");
+if (!DefMI)
+  continue;
 if (TII.isReMaterializable(*DefMI))
   Remattable.insert(OrigVNI);
   }



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[llvm-branch-commits] [clang] [llvm] [openmp] [OpenMP] Taskgraph Clang 'record and replay' frontend support (PR #159774)

[Julian Brown via llvm-branch-commits]

https://github.com/jtb20 updated 
https://github.com/llvm/llvm-project/pull/159774

>From 56dc3e12256472425106c8b059bdc6dfad6c4fdd Mon Sep 17 00:00:00 2001
From: Julian Brown 
Date: Mon, 15 Sep 2025 05:25:55 -0500
Subject: [PATCH 1/3] [OpenMP] Taskgraph frontend support

This is a version of the 'ompx taskgraph' support posted in PR66919,
adapted to the official OpenMP 6.0 spelling of 'omp taskgraph', and with
the 'ompx' extension parts removed.

Co-authored-by: Adrian Munera 
Co-authored-by: Jose M Monsalve Diaz 
---
 clang/bindings/python/clang/cindex.py |  3 +
 clang/include/clang-c/Index.h |  4 +
 clang/include/clang/AST/RecursiveASTVisitor.h |  3 +
 clang/include/clang/AST/StmtOpenMP.h  | 49 
 clang/include/clang/Basic/StmtNodes.td|  1 +
 clang/include/clang/Sema/SemaOpenMP.h |  4 +
 .../include/clang/Serialization/ASTBitCodes.h |  1 +
 clang/lib/AST/StmtOpenMP.cpp  | 15 
 clang/lib/AST/StmtPrinter.cpp |  5 ++
 clang/lib/AST/StmtProfile.cpp |  5 ++
 clang/lib/Basic/OpenMPKinds.cpp   |  3 +
 clang/lib/CodeGen/CGOpenMPRuntime.cpp | 74 +++
 clang/lib/CodeGen/CGOpenMPRuntime.h   |  8 ++
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |  2 +
 clang/lib/CodeGen/CGStmt.cpp  |  3 +
 clang/lib/CodeGen/CGStmtOpenMP.cpp|  6 ++
 clang/lib/CodeGen/CodeGenFunction.h   |  1 +
 clang/lib/Sema/SemaExceptionSpec.cpp  |  1 +
 clang/lib/Sema/SemaOpenMP.cpp | 31 
 clang/lib/Sema/TreeTransform.h| 11 +++
 clang/lib/Serialization/ASTReaderStmt.cpp | 10 +++
 clang/lib/Serialization/ASTWriterStmt.cpp |  6 ++
 clang/lib/StaticAnalyzer/Core/ExprEngine.cpp  |  1 +
 clang/tools/libclang/CIndex.cpp   |  2 +
 clang/tools/libclang/CXCursor.cpp |  3 +
 .../include/llvm/Frontend/OpenMP/OMPKinds.def |  1 +
 26 files changed, 253 insertions(+)

diff --git a/clang/bindings/python/clang/cindex.py 
b/clang/bindings/python/clang/cindex.py
index c44e646a30f17..ff7b486ad5211 100644
--- a/clang/bindings/python/clang/cindex.py
+++ b/clang/bindings/python/clang/cindex.py
@@ -1446,6 +1446,9 @@ def is_unexposed(self):
 # OpenMP stripe directive.
 OMP_STRIPE_DIRECTIVE = 310
 
+# OpenMP taskgraph directive.
+OMP_TASKGRAPH_DIRECTIVE = 312
+
 # OpenACC Compute Construct.
 OPEN_ACC_COMPUTE_DIRECTIVE = 320
 
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index be038d9165fc6..e5e3d8d7e42eb 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2162,6 +2162,10 @@ enum CXCursorKind {
*/
   CXCursor_OMPStripeDirective = 310,
 
+  /** OpenMP taskgraph directive.
+   */
+  CXCursor_OMPTaskgraphDirective = 312,
+
   /** OpenACC Compute Construct.
*/
   CXCursor_OpenACCComputeConstruct = 320,
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h 
b/clang/include/clang/AST/RecursiveASTVisitor.h
index af1a073cc4a5a..67fb7836c7a3f 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3233,6 +3233,9 @@ DEF_TRAVERSE_STMT(OMPBarrierDirective,
 DEF_TRAVERSE_STMT(OMPTaskwaitDirective,
   { TRY_TO(TraverseOMPExecutableDirective(S)); })
 
+DEF_TRAVERSE_STMT(OMPTaskgraphDirective,
+  { TRY_TO(TraverseOMPExecutableDirective(S)); })
+
 DEF_TRAVERSE_STMT(OMPTaskgroupDirective,
   { TRY_TO(TraverseOMPExecutableDirective(S)); })
 
diff --git a/clang/include/clang/AST/StmtOpenMP.h 
b/clang/include/clang/AST/StmtOpenMP.h
index d9f87f1e49b40..3750ccae41fb4 100644
--- a/clang/include/clang/AST/StmtOpenMP.h
+++ b/clang/include/clang/AST/StmtOpenMP.h
@@ -2729,6 +2729,55 @@ class OMPTaskwaitDirective : public 
OMPExecutableDirective {
   }
 };
 
+/// This represents '#pragma omp taskgraph' directive.
+/// Available with OpenMP 6.0.
+///
+/// \code
+/// #pragma omp taskgraph
+/// \endcode
+///
+class OMPTaskgraphDirective final : public OMPExecutableDirective {
+  friend class ASTStmtReader;
+  friend class OMPExecutableDirective;
+  /// Build directive with the given start and end location.
+  ///
+  /// \param StartLoc Starting location of the directive kind.
+  /// \param EndLoc Ending location of the directive.
+  ///
+  OMPTaskgraphDirective(SourceLocation StartLoc, SourceLocation EndLoc)
+  : OMPExecutableDirective(OMPTaskgraphDirectiveClass,
+   llvm::omp::OMPD_taskgraph, StartLoc, EndLoc) {}
+
+  /// Build an empty directive.
+  ///
+  explicit OMPTaskgraphDirective()
+  : OMPExecutableDirective(OMPTaskgraphDirectiveClass,
+   llvm::omp::OMPD_taskgraph, SourceLocation(),
+   SourceLocation()) {}
+
+public:
+  /// Creates directive.
+  ///
+  /// \param C AST context.
+  /// \param StartLoc Starting location of the directiv

[llvm-branch-commits] [clang] [llvm] [openmp] [OpenMP] Taskgraph Clang 'record and replay' frontend support (PR #159774)

[Julian Brown via llvm-branch-commits]

@@ -5954,6 +5976,48 @@ void CGOpenMPRuntime::emitTaskwaitCall(CodeGenFunction 
&CGF, SourceLocation Loc,
 Region->emitUntiedSwitch(CGF);
 }
 
+void CGOpenMPRuntime::emitTaskgraphCall(CodeGenFunction &CGF,
+SourceLocation Loc,
+const OMPExecutableDirective &D) {
+  if (!CGF.HaveInsertPoint())
+return;
+
+  // Building kmp_taskgraph_flags_t flags for kmpc_taskgraph. C.f., kmp.h
+  enum {
+NowaitFlag = 0x1, // Not used yet.
+ReRecordFlag = 0x2,
+  };
+
+  unsigned Flags = 0;
+
+  CodeGenFunction OutlinedCGF(CGM, /*suppressNewContext=*/true);
+
+  const auto *CS = cast(D.getAssociatedStmt());
+
+  auto BodyGen = [CS](CodeGenFunction &CGF, PrePostActionTy &) {
+CGF.EmitStmt(CS->getCapturedStmt());
+  };
+
+  LValue CapStruct = CGF.InitCapturedStruct(*CS);
+  CGOpenMPTaskgraphRegionInfo TaskgraphRegion(*CS, BodyGen);
+  CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(OutlinedCGF,
+  &TaskgraphRegion);
+  llvm::Function *FnT = OutlinedCGF.GenerateCapturedStmtFunction(*CS);
+
+  SmallVector Args{

jtb20 wrote:

Done.

https://github.com/llvm/llvm-project/pull/159774
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[llvm-branch-commits] [llvm] [AArch64][PAC] Cleanup AArch64AsmPrinter::emitPtrauthDiscriminator (NFC) (PR #160900)

[Anatoly Trosinenko via llvm-branch-commits]

https://github.com/atrosinenko ready_for_review 
https://github.com/llvm/llvm-project/pull/160900
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sam Tebbs via llvm-branch-commits]

https://github.com/SamTebbs33 updated 
https://github.com/llvm/llvm-project/pull/160154

>From 1e26f885620a00e9733102c36dd626552cb9dda5 Mon Sep 17 00:00:00 2001
From: Sam Tebbs 
Date: Mon, 22 Sep 2025 17:16:40 +0100
Subject: [PATCH 1/6] [LV] Add ExtNegatedMulAccReduction expression type

This PR adds the ExtNegatedMulAccReduction expression type for
VPExpressionRecipe so that extend-multiply-accumulate reductions with a
negated multiply can be bundled.

Stacked PRs:

1. https://github.com/llvm/llvm-project/pull/156976
2. -> This
3. https://github.com/llvm/llvm-project/pull/147302
---
 llvm/lib/Transforms/Vectorize/VPlan.h |  11 ++
 .../lib/Transforms/Vectorize/VPlanRecipes.cpp |  31 -
 .../Transforms/Vectorize/VPlanTransforms.cpp  |  46 ---
 .../vplan-printing-reductions.ll  | 121 ++
 4 files changed, 192 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h 
b/llvm/lib/Transforms/Vectorize/VPlan.h
index e6f6067bc9df3..1cb0c889528ec 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -2989,6 +2989,12 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
 /// vector operands, performing a reduction.add on the result, and adding
 /// the scalar result to a chain.
 MulAccReduction,
+/// Represent an inloop multiply-accumulate reduction, multiplying the
+/// extended vector operands, negating the multiplication, performing a
+/// reduction.add
+/// on the result, and adding
+/// the scalar result to a chain.
+ExtNegatedMulAccReduction,
   };
 
   /// Type of the expression.
@@ -3012,6 +3018,11 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
  VPWidenRecipe *Mul, VPReductionRecipe *Red)
   : VPExpressionRecipe(ExpressionTypes::ExtMulAccReduction,
{Ext0, Ext1, Mul, Red}) {}
+  VPExpressionRecipe(VPWidenCastRecipe *Ext0, VPWidenCastRecipe *Ext1,
+ VPWidenRecipe *Mul, VPWidenRecipe *Sub,
+ VPReductionRecipe *Red)
+  : VPExpressionRecipe(ExpressionTypes::ExtNegatedMulAccReduction,
+   {Ext0, Ext1, Mul, Sub, Red}) {}
 
   ~VPExpressionRecipe() override {
 SmallSet ExpressionRecipesSeen;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp 
b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 4568d4f37a751..02be0db102547 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2861,12 +2861,17 @@ InstructionCost 
VPExpressionRecipe::computeCost(ElementCount VF,
 return Ctx.TTI.getMulAccReductionCost(false, Opcode, RedTy, SrcVecTy,
   Ctx.CostKind);
 
-  case ExpressionTypes::ExtMulAccReduction:
+  case ExpressionTypes::ExtNegatedMulAccReduction:
+  case ExpressionTypes::ExtMulAccReduction: {
+if (ExpressionType == ExpressionTypes::ExtNegatedMulAccReduction &&
+Opcode == Instruction::Add)
+  Opcode = Instruction::Sub;
 return Ctx.TTI.getMulAccReductionCost(
 cast(ExpressionRecipes.front())->getOpcode() ==
 Instruction::ZExt,
 Opcode, RedTy, SrcVecTy, Ctx.CostKind);
   }
+  }
   llvm_unreachable("Unknown VPExpressionRecipe::ExpressionTypes enum");
 }
 
@@ -2912,6 +2917,30 @@ void VPExpressionRecipe::print(raw_ostream &O, const 
Twine &Indent,
 O << ")";
 break;
   }
+  case ExpressionTypes::ExtNegatedMulAccReduction: {
+getOperand(getNumOperands() - 1)->printAsOperand(O, SlotTracker);
+O << " + reduce."
+  << Instruction::getOpcodeName(
+ RecurrenceDescriptor::getOpcode(Red->getRecurrenceKind()))
+  << " (sub (0, mul";
+auto *Mul = cast(ExpressionRecipes[2]);
+Mul->printFlags(O);
+O << "(";
+getOperand(0)->printAsOperand(O, SlotTracker);
+auto *Ext0 = cast(ExpressionRecipes[0]);
+O << " " << Instruction::getOpcodeName(Ext0->getOpcode()) << " to "
+  << *Ext0->getResultType() << "), (";
+getOperand(1)->printAsOperand(O, SlotTracker);
+auto *Ext1 = cast(ExpressionRecipes[1]);
+O << " " << Instruction::getOpcodeName(Ext1->getOpcode()) << " to "
+  << *Ext1->getResultType() << ")";
+if (Red->isConditional()) {
+  O << ", ";
+  Red->getCondOp()->printAsOperand(O, SlotTracker);
+}
+O << "))";
+break;
+  }
   case ExpressionTypes::MulAccReduction:
   case ExpressionTypes::ExtMulAccReduction: {
 getOperand(getNumOperands() - 1)->printAsOperand(O, SlotTracker);
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp 
b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 1f6b85270607e..ca89c4fa0d2e6 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -3524,14 +3524,22 @@ 
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
   };
 
   VPValue *VecOp = Red->getVecOp();
+  VPValue *Mul = 

[llvm-branch-commits] [flang] [flang] Consolidate copy-in/copy-out determination in evaluate framework (PR #155810)

[Tom Eccles via llvm-branch-commits]

https://github.com/tblah closed https://github.com/llvm/llvm-project/pull/155810
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[llvm-branch-commits] [clang] [llvm] [openmp] [OpenMP] Taskgraph Clang 'record and replay' frontend support (PR #159774)

[Julian Brown via llvm-branch-commits]

jtb20 wrote:

> clang unit tests (parsing, sema, codegen) are required. Also, need to update 
> OpenMP.rst and ReleseNotes docs

I added a couple of tests, but forgot about the docs. I'll push again in a 
bit...

https://github.com/llvm/llvm-project/pull/159774
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[llvm-branch-commits] [llvm] [AArch64][PAC] Factor out printing real AUT/PAC/BLRA encodings (NFC) (PR #160901)

[Anatoly Trosinenko via llvm-branch-commits]

atrosinenko wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/160901?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

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 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
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* **#160899** https://app.graphite.dev/github/pr/llvm/llvm-project/160899?utm_source=stack-comment-icon";
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https://github.com/llvm/llvm-project/pull/160901
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[llvm-branch-commits] [llvm] [LV] Add ExtNegatedMulAccReduction expression type (PR #160154)

[Sam Tebbs via llvm-branch-commits]

@@ -2861,12 +2861,17 @@ InstructionCost 
VPExpressionRecipe::computeCost(ElementCount VF,
 return Ctx.TTI.getMulAccReductionCost(false, Opcode, RedTy, SrcVecTy,
   Ctx.CostKind);
 
-  case ExpressionTypes::ExtMulAccReduction:
+  case ExpressionTypes::ExtNegatedMulAccReduction:
+  case ExpressionTypes::ExtMulAccReduction: {
+if (ExpressionType == ExpressionTypes::ExtNegatedMulAccReduction &&
+Opcode == Instruction::Add)
+  Opcode = Instruction::Sub;

SamTebbs33 wrote:

Addressed now, thanks!

https://github.com/llvm/llvm-project/pull/160154
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[llvm-branch-commits] [llvm] Greedy: Move physreg check when trying to recolor vregs (NFC) (PR #160484)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160484

>From f588d48f0e41e7c28bd5f5ff9f7c8c673f9310b2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:02:49 +0900
Subject: [PATCH] Greedy: Move physreg check when trying to recolor vregs (NFC)

Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..dc23ab3ce9d2b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,10 +2502,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
-// We cannot recolor physical register.
-if (Reg.isPhysical())
-  continue;
-
 // This may be a skipped register.
 if (!VRM->hasPhys(Reg)) {
   assert(!shouldAllocateRegister(Reg) &&
@@ -2553,7 +2549,8 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Push all copy-related live-ranges to keep reconciling the broken
 // hints.
 for (const HintInfo &HI : Info) {
-  if (Visited.insert(HI.Reg).second)
+  // We cannot recolor physical register.
+  if (HI.Reg.isVirtual() && Visited.insert(HI.Reg).second)
 RecoloringCandidates.push_back(HI.Reg);
 }
   } while (!RecoloringCandidates.empty());

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[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160467

>From f409ccc1223fc7965f52e522d260295cb6053e4f Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 16:53:33 +0900
Subject: [PATCH 1/2] Greedy: Take hints from copy to physical subreg

Previously this took hints from subregister extract of physreg,
like  %vreg.sub = COPY $physreg

This now also handles the rarer case:
  $physreg_sub = COPY %vreg

Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 35 -
 llvm/test/CodeGen/X86/shift-i128.ll |  3 +--
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..0df8713dd892b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2439,25 +2439,28 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 unsigned SubReg = Opnd.getSubReg();
 
 // Get the current assignment.
-MCRegister OtherPhysReg =
-OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg);
-if (OtherSubReg) {
-  if (OtherReg.isPhysical()) {
-MCRegister Tuple =
-TRI->getMatchingSuperReg(OtherPhysReg, OtherSubReg, RC);
-if (!Tuple)
-  continue;
-OtherPhysReg = Tuple;
-  } else {
-// TODO: There should be a hinting mechanism for subregisters
-if (SubReg != OtherSubReg)
-  continue;
-  }
+MCRegister OtherPhysReg;
+if (OtherReg.isPhysical()) {
+  if (OtherSubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, OtherSubReg, RC);
+  else if (SubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, SubReg, RC);
+  else
+OtherPhysReg = OtherReg;
+} else {
+  OtherPhysReg = VRM->getPhys(OtherReg);
+  // TODO: Should find matching superregister, but applying this in the
+  // non-hint case currently causes regressions
+
+  if (SubReg && OtherSubReg && SubReg != OtherSubReg)
+continue;
 }
 
 // Push the collected information.
-Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
-   OtherPhysReg));
+if (OtherPhysReg) {
+  Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
+ OtherPhysReg));
+}
   }
 }
 
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll 
b/llvm/test/CodeGen/X86/shift-i128.ll
index 7462c77482827..049ee47af9681 100644
--- a/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/llvm/test/CodeGen/X86/shift-i128.ll
@@ -613,8 +613,7 @@ define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, 
ptr nocapture %r) nou
 ; i686-NEXT:shldl %cl, %esi, %ebx
 ; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
 ; i686-NEXT:movl %edi, %esi
-; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; i686-NEXT:movl %eax, %ecx
+; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
 ; i686-NEXT:shll %cl, %esi
 ; i686-NEXT:shldl %cl, %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
 ; i686-NEXT:negl %edx

>From 0581982382d14b2451abfc6f2fc593d5d15e22a0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 18:54:59 +0900
Subject: [PATCH 2/2] XXX scale block frequencies by subreg

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 32 -
 llvm/lib/CodeGen/RegAllocGreedy.h   | 13 +++-
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 0df8713dd892b..9d3165b790642 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2458,7 +2458,28 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 
 // Push the collected information.
 if (OtherPhysReg) {
-  Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
+  BlockFrequency Freq = MBFI->getBlockFreq(Instr.getParent());
+
+  if (OtherSubReg) {
+const TargetRegisterClass *OtherRC = MRI->getRegClass(OtherReg);
+unsigned FullRegCopyCost = OtherRC->getCopyCost();
+
+const TargetRegisterClass *OtherSubRC = 
TRI->getSubRegisterClass(OtherRC, OtherSubReg);
+unsigned SubRegCopyCost = OtherSubRC->getCopyCost();
+
+BranchProbability Scaling(SubRegCopyCost, FullRegCopyCost);
+Freq *= Scaling;
+  } else if (SubReg) {
+unsigned FullRegCopyCost = RC->getCopyCost();
+const TargetRegisterClass *SubRC = TRI->getSubRegisterClass(RC, 
SubReg);
+unsigned SubRegCopyCost = SubRC->getCopyCost();
+
+Branc

[llvm-branch-commits] [llvm] Greedy: Move physreg check when trying to recolor vregs (NFC) (PR #160484)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160484

>From f588d48f0e41e7c28bd5f5ff9f7c8c673f9310b2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:02:49 +0900
Subject: [PATCH] Greedy: Move physreg check when trying to recolor vregs (NFC)

Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..dc23ab3ce9d2b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,10 +2502,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
-// We cannot recolor physical register.
-if (Reg.isPhysical())
-  continue;
-
 // This may be a skipped register.
 if (!VRM->hasPhys(Reg)) {
   assert(!shouldAllocateRegister(Reg) &&
@@ -2553,7 +2549,8 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Push all copy-related live-ranges to keep reconciling the broken
 // hints.
 for (const HintInfo &HI : Info) {
-  if (Visited.insert(HI.Reg).second)
+  // We cannot recolor physical register.
+  if (HI.Reg.isVirtual() && Visited.insert(HI.Reg).second)
 RecoloringCandidates.push_back(HI.Reg);
 }
   } while (!RecoloringCandidates.empty());

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[llvm-branch-commits] [llvm] Greedy: Merge VirtRegMap queries into one use (NFC) (PR #160485)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160485

>From b9629d1bf8fe6609b443438f2f62305f7f30dd8d Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:06:39 +0900
Subject: [PATCH] Greedy: Merge VirtRegMap queries into one use (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index dc23ab3ce9d2b..6957548ac6c7a 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,8 +2502,10 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
+MCRegister CurrPhys = VRM->getPhys(Reg);
+
 // This may be a skipped register.
-if (!VRM->hasPhys(Reg)) {
+if (!CurrPhys) {
   assert(!shouldAllocateRegister(Reg) &&
  "We have an unallocated variable which should have been handled");
   continue;
@@ -2512,7 +2514,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Get the live interval mapped with this virtual register to be able
 // to check for the interference with the new color.
 LiveInterval &LI = LIS->getInterval(Reg);
-MCRegister CurrPhys = VRM->getPhys(Reg);
 // Check that the new color matches the register class constraints and
 // that it is free for this live range.
 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||

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[llvm-branch-commits] [llvm] Greedy: Merge VirtRegMap queries into one use (NFC) (PR #160485)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160485

>From b9629d1bf8fe6609b443438f2f62305f7f30dd8d Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 19:06:39 +0900
Subject: [PATCH] Greedy: Merge VirtRegMap queries into one use (NFC)

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index dc23ab3ce9d2b..6957548ac6c7a 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2502,8 +2502,10 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
   do {
 Reg = RecoloringCandidates.pop_back_val();
 
+MCRegister CurrPhys = VRM->getPhys(Reg);
+
 // This may be a skipped register.
-if (!VRM->hasPhys(Reg)) {
+if (!CurrPhys) {
   assert(!shouldAllocateRegister(Reg) &&
  "We have an unallocated variable which should have been handled");
   continue;
@@ -2512,7 +2514,6 @@ void RAGreedy::tryHintRecoloring(const LiveInterval 
&VirtReg) {
 // Get the live interval mapped with this virtual register to be able
 // to check for the interference with the new color.
 LiveInterval &LI = LIS->getInterval(Reg);
-MCRegister CurrPhys = VRM->getPhys(Reg);
 // Check that the new color matches the register class constraints and
 // that it is free for this live range.
 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||

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[llvm-branch-commits] [llvm] [AArch64][PAC] Cleanup AArch64AsmPrinter::emitPtrauthDiscriminator (NFC) (PR #160900)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-aarch64

Author: Anatoly Trosinenko (atrosinenko)


Changes

Refactor emitPtrauthDiscriminator function: introduce `isPtrauthRegSafe`
function, update the comments and assertions for readability.

---
Full diff: https://github.com/llvm/llvm-project/pull/160900.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (+25-21) 


``diff
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp 
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 1a2808f4d56d8..e7135da17a8d5 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -155,6 +155,13 @@ class AArch64AsmPrinter : public AsmPrinter {
 
   void emitSled(const MachineInstr &MI, SledKind Kind);
 
+  bool isPtrauthRegSafe(Register Reg) const {
+if (STI->isX16X17Safer())
+  return Reg == AArch64::X16 || Reg == AArch64::X17;
+
+return true;
+  }
+
   // Emit the sequence for BRA/BLRA (authenticate + branch/call).
   void emitPtrauthBranch(const MachineInstr *MI);
 
@@ -180,13 +187,15 @@ class AArch64AsmPrinter : public AsmPrinter {
 
   // Emit the sequence to compute the discriminator.
   //
-  // The returned register is either unmodified AddrDisc or ScratchReg.
+  // The Scratch register passed to this function must be safe, see
+  // isPtrauthRegSafe(Reg) function.
+  //
+  // The returned register is either ScratchReg or AddrDisc. Furthermore, it
+  // is safe, unless unsafe AddrDisc was passed-through unmodified.
   //
   // If the expanded pseudo is allowed to clobber AddrDisc register, setting
-  // MayUseAddrAsScratch may save one MOV instruction, provided the address
-  // is already in x16/x17 (i.e. return x16/x17 which is the *modified* 
AddrDisc
-  // register at the same time) or the OS doesn't make it safer to use x16/x17
-  // (see AArch64Subtarget::isX16X17Safer()):
+  // MayUseAddrAsScratch may save one MOV instruction, provided
+  // isPtrauthRegSafe(AddrDisc) is true:
   //
   //   mov   x17, x16
   //   movk  x17, #1234, lsl #48
@@ -195,7 +204,7 @@ class AArch64AsmPrinter : public AsmPrinter {
   // can be replaced by
   //
   //   movk  x16, #1234, lsl #48
-  Register emitPtrauthDiscriminator(uint16_t Disc, Register AddrDisc,
+  Register emitPtrauthDiscriminator(uint64_t Disc, Register AddrDisc,
 Register ScratchReg,
 bool MayUseAddrAsScratch = false);
 
@@ -1902,12 +1911,14 @@ void AArch64AsmPrinter::emitFMov0AsFMov(const 
MachineInstr &MI,
   EmitToStreamer(*OutStreamer, FMov);
 }
 
-Register AArch64AsmPrinter::emitPtrauthDiscriminator(uint16_t Disc,
+Register AArch64AsmPrinter::emitPtrauthDiscriminator(uint64_t Disc,
  Register AddrDisc,
  Register ScratchReg,
  bool MayUseAddrAsScratch) 
{
-  assert(ScratchReg == AArch64::X16 || ScratchReg == AArch64::X17 ||
- !STI->isX16X17Safer());
+  assert(isPtrauthRegSafe(ScratchReg) &&
+ "Safe scratch register must be provided by the caller");
+  assert(isUInt<16>(Disc) && "Constant discriminator is too wide");
+
   // So far we've used NoRegister in pseudos.  Now we need real encodings.
   if (AddrDisc == AArch64::NoRegister)
 AddrDisc = AArch64::XZR;
@@ -1926,13 +1937,13 @@ Register 
AArch64AsmPrinter::emitPtrauthDiscriminator(uint16_t Disc,
   // If there are both, emit a blend into the scratch register.
 
   // Check if we can save one MOV instruction.
-  assert(MayUseAddrAsScratch || ScratchReg != AddrDisc);
-  bool AddrDiscIsSafe = AddrDisc == AArch64::X16 || AddrDisc == AArch64::X17 ||
-!STI->isX16X17Safer();
-  if (MayUseAddrAsScratch && AddrDiscIsSafe)
+  if (MayUseAddrAsScratch && isPtrauthRegSafe(AddrDisc)) {
 ScratchReg = AddrDisc;
-  else
+  } else {
 emitMovXReg(ScratchReg, AddrDisc);
+assert(ScratchReg != AddrDisc &&
+   "Forbidden to clobber AddrDisc, but have to");
+  }
 
   emitMOVK(ScratchReg, Disc, 48);
   return ScratchReg;
@@ -2151,7 +2162,6 @@ void AArch64AsmPrinter::emitPtrauthAuthResign(
   }
 
   // Compute aut discriminator
-  assert(isUInt<16>(AUTDisc));
   Register AUTDiscReg = emitPtrauthDiscriminator(
   AUTDisc, AUTAddrDisc->getReg(), Scratch, AUTAddrDisc->isKill());
   bool AUTZero = AUTDiscReg == AArch64::XZR;
@@ -2188,7 +2198,6 @@ void AArch64AsmPrinter::emitPtrauthAuthResign(
 return;
 
   // Compute pac discriminator
-  assert(isUInt<16>(PACDisc));
   Register PACDiscReg =
   emitPtrauthDiscriminator(PACDisc, PACAddrDisc, Scratch);
   bool PACZero = PACDiscReg == AArch64::XZR;
@@ -2223,7 +2232,6 @@ void AArch64AsmPrinter::emitPtrauthSign(const 
MachineInstr *MI) {
  "Neither X16 nor X17 is available as a scratch register");
 
   // Compute pac discriminator
-  assert(isUInt<16>(Disc));
   Regis

[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/160467

>From f409ccc1223fc7965f52e522d260295cb6053e4f Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 16:53:33 +0900
Subject: [PATCH 1/2] Greedy: Take hints from copy to physical subreg

Previously this took hints from subregister extract of physreg,
like  %vreg.sub = COPY $physreg

This now also handles the rarer case:
  $physreg_sub = COPY %vreg

Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 35 -
 llvm/test/CodeGen/X86/shift-i128.ll |  3 +--
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6e0585b2e9e55..0df8713dd892b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2439,25 +2439,28 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 unsigned SubReg = Opnd.getSubReg();
 
 // Get the current assignment.
-MCRegister OtherPhysReg =
-OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg);
-if (OtherSubReg) {
-  if (OtherReg.isPhysical()) {
-MCRegister Tuple =
-TRI->getMatchingSuperReg(OtherPhysReg, OtherSubReg, RC);
-if (!Tuple)
-  continue;
-OtherPhysReg = Tuple;
-  } else {
-// TODO: There should be a hinting mechanism for subregisters
-if (SubReg != OtherSubReg)
-  continue;
-  }
+MCRegister OtherPhysReg;
+if (OtherReg.isPhysical()) {
+  if (OtherSubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, OtherSubReg, RC);
+  else if (SubReg)
+OtherPhysReg = TRI->getMatchingSuperReg(OtherReg, SubReg, RC);
+  else
+OtherPhysReg = OtherReg;
+} else {
+  OtherPhysReg = VRM->getPhys(OtherReg);
+  // TODO: Should find matching superregister, but applying this in the
+  // non-hint case currently causes regressions
+
+  if (SubReg && OtherSubReg && SubReg != OtherSubReg)
+continue;
 }
 
 // Push the collected information.
-Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
-   OtherPhysReg));
+if (OtherPhysReg) {
+  Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
+ OtherPhysReg));
+}
   }
 }
 
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll 
b/llvm/test/CodeGen/X86/shift-i128.ll
index 7462c77482827..049ee47af9681 100644
--- a/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/llvm/test/CodeGen/X86/shift-i128.ll
@@ -613,8 +613,7 @@ define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, 
ptr nocapture %r) nou
 ; i686-NEXT:shldl %cl, %esi, %ebx
 ; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
 ; i686-NEXT:movl %edi, %esi
-; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; i686-NEXT:movl %eax, %ecx
+; i686-NEXT:movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
 ; i686-NEXT:shll %cl, %esi
 ; i686-NEXT:shldl %cl, %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
 ; i686-NEXT:negl %edx

>From 0581982382d14b2451abfc6f2fc593d5d15e22a0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Wed, 24 Sep 2025 18:54:59 +0900
Subject: [PATCH 2/2] XXX scale block frequencies by subreg

---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 32 -
 llvm/lib/CodeGen/RegAllocGreedy.h   | 13 +++-
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp 
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 0df8713dd892b..9d3165b790642 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2458,7 +2458,28 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo 
&Out) {
 
 // Push the collected information.
 if (OtherPhysReg) {
-  Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
+  BlockFrequency Freq = MBFI->getBlockFreq(Instr.getParent());
+
+  if (OtherSubReg) {
+const TargetRegisterClass *OtherRC = MRI->getRegClass(OtherReg);
+unsigned FullRegCopyCost = OtherRC->getCopyCost();
+
+const TargetRegisterClass *OtherSubRC = 
TRI->getSubRegisterClass(OtherRC, OtherSubReg);
+unsigned SubRegCopyCost = OtherSubRC->getCopyCost();
+
+BranchProbability Scaling(SubRegCopyCost, FullRegCopyCost);
+Freq *= Scaling;
+  } else if (SubReg) {
+unsigned FullRegCopyCost = RC->getCopyCost();
+const TargetRegisterClass *SubRC = TRI->getSubRegisterClass(RC, 
SubReg);
+unsigned SubRegCopyCost = SubRC->getCopyCost();
+
+Branc