[llvm-branch-commits] [llvm] PPC: Replace PointerLikeRegClass with RegClassByHwMode (PR #158777)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158777
>From 0e5dfd5493a599e6eb9e5a0a0b21cd542c964e8f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 5 Sep 2025 18:03:59 +0900
Subject: [PATCH 1/3] PPC: Replace PointerLikeRegClass with RegClassByHwMode
---
.../PowerPC/Disassembler/PPCDisassembler.cpp | 3 --
llvm/lib/Target/PowerPC/PPC.td| 6
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 28 ++-
llvm/lib/Target/PowerPC/PPCRegisterInfo.td| 10 +--
4 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 47586c417cfe3..70e619cc22b19 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -185,9 +185,6 @@ DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
}
-#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
-#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
-
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 386d0f65d1ed1..d491e88b66ad8 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -394,6 +394,12 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
+//===--===//
+// HwModes
+//===--===//
+
+defvar PPC32 = DefaultMode;
+def PPC64 : HwMode<[In64BitMode]>;
// Since new processors generally contain a superset of features of those that
// came before them, the idea is to make implementations of new processors
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index db066bc4b7bdd..55e38bcf4afc9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2142,33 +2142,23 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr
&UseMI, MachineInstr &DefMI,
assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
assert(UseIdx < UseMCID.getNumOperands() && "No operand description for
Reg");
- const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx];
-
// We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
// register (which might also be specified as a pointer class kind).
- if (UseInfo->isLookupPtrRegClass()) {
-if (UseInfo->RegClass /* Kind */ != 1)
- return false;
- } else {
-if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
-UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
- return false;
- }
+
+ const MCOperandInfo &UseInfo = UseMCID.operands()[UseIdx];
+ int16_t RegClass = getOpRegClassID(UseInfo);
+ if (UseInfo.RegClass != PPC::GPRC_NOR0RegClassID &&
+ UseInfo.RegClass != PPC::G8RC_NOX0RegClassID)
+return false;
// Make sure this is not tied to an output register (or otherwise
// constrained). This is true for ST?UX registers, for example, which
// are tied to their output registers.
- if (UseInfo->Constraints != 0)
+ if (UseInfo.Constraints != 0)
return false;
- MCRegister ZeroReg;
- if (UseInfo->isLookupPtrRegClass()) {
-bool isPPC64 = Subtarget.isPPC64();
-ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
- } else {
-ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
- PPC::ZERO8 : PPC::ZERO;
- }
+ MCRegister ZeroReg =
+ RegClass == PPC::G8RC_NOX0RegClassID ? PPC::ZERO8 : PPC::ZERO;
LLVM_DEBUG(dbgs() << "Folded immediate zero for: ");
LLVM_DEBUG(UseMI.dump());
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8b690b7b833b3..adda91786d19c 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -868,7 +868,11 @@ def crbitm: Operand {
def PPCRegGxRCNoR0Operand : AsmOperandClass {
let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
}
-def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : Operand,
+ RegClassByHwMode<
+[PPC32, PPC64],
+[GPRC_NOR0, G8RC_NOX0]> {
let ParserMatchClass = PPCRegGxRCNoR0Operand;
}
@@ -902,7 +906,9 @@ def memri34_pcrel : Operand { // memri, imm is a
34-bit value.
def PPCRegGxRCOperand : AsmOperandClass {
let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
}
-def ptr_rc_idx : Operand, PointerLikeRegClass<0> {
+def ptr_rc_idx : Operand,
[llvm-branch-commits] [llvm] AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (PR #158272)
@@ -2926,6 +2929,20 @@ def HasLdsBarrierArriveAtomic : Predicate<"Subtarget->hasLdsBarrierArriveAtomic( def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">, AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>; +def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">, + AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>; + +//===--===// +// HwModes +//===--===// + +// gfx90a-gfx950. Has AGPRs, and also the align2 VGPR/AGPR requirement +def AVAlign2LoadStoreMode : HwMode<[HasMAIInsts, NeedsAlignedVGPRs]>; + +// gfx1250, has alignment requirement but no AGPRs. +def AlignedVGPRNoAGPRMode : HwMode<[NotHasMAIInsts, NeedsAlignedVGPRs]>; cdevadas wrote: Got it. https://github.com/llvm/llvm-project/pull/158272 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MC] Rewrite stdin.s to use python (PR #157232)
@@ -0,0 +1,17 @@ +# RUN: echo "// comment" > %t.input +# RUN: which llvm-mc | %python %s %t + +import subprocess +import sys + +llvm_mc_binary = sys.stdin.readlines()[0].strip() +temp_file = sys.argv[1] +input_file = temp_file + ".input" + +with open(temp_file, "w") as mc_stdout: +mc_stdout.seek(4) ilovepi wrote: Can we get a comment here about the seek being the property under test? Cribbing from the original commit: ``` ## We need to test that starting on an input stream that is not at offset 0 would trigger the assert in WinCOFFObjectWriter.cpp ``` https://github.com/llvm/llvm-project/pull/157232 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] X86: Switch to RegClassByHwMode (PR #158274)
llvmbot wrote:
@llvm/pr-subscribers-llvm-mc
Author: Matt Arsenault (arsenm)
Changes
Replace the target uses of PointerLikeRegClass with RegClassByHwMode
---
Full diff: https://github.com/llvm/llvm-project/pull/158274.diff
8 Files Affected:
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (+3)
- (modified) llvm/lib/Target/X86/X86.td (+2)
- (modified) llvm/lib/Target/X86/X86InstrInfo.td (+4-4)
- (modified) llvm/lib/Target/X86/X86InstrOperands.td (+22-8)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (+14)
- (modified) llvm/lib/Target/X86/X86RegisterInfo.cpp (+8-27)
- (modified) llvm/lib/Target/X86/X86Subtarget.h (+2-2)
- (modified) llvm/utils/TableGen/X86FoldTablesEmitter.cpp (+2-2)
``diff
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index bb1e716c33ed5..1d5ef8b0996dc 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -55,6 +55,9 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
else
FS = "-64bit-mode,-32bit-mode,+16bit-mode";
+ if (TT.isX32())
+FS += ",+x32";
+
return FS;
}
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 7c9e821c02fda..3af8b3e060a16 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -25,6 +25,8 @@ def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit",
"true",
"32-bit mode (80386)">;
def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
"16-bit mode (i8086)">;
+def IsX32 : SubtargetFeature<"x32", "IsX32", "true",
+ "64-bit with ILP32 programming model (e.g. x32
ABI)">;
//===--===//
// X86 Subtarget ISA features
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td
b/llvm/lib/Target/X86/X86InstrInfo.td
index 7f6c5614847e3..0c4abc2c400f6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -18,14 +18,14 @@ include "X86InstrFragments.td"
include "X86InstrFragmentsSIMD.td"
//===--===//
-// X86 Operand Definitions.
+// X86 Predicate Definitions.
//
-include "X86InstrOperands.td"
+include "X86InstrPredicates.td"
//===--===//
-// X86 Predicate Definitions.
+// X86 Operand Definitions.
//
-include "X86InstrPredicates.td"
+include "X86InstrOperands.td"
//===--===//
// X86 Instruction Format Definitions.
diff --git a/llvm/lib/Target/X86/X86InstrOperands.td
b/llvm/lib/Target/X86/X86InstrOperands.td
index 80843f6bb80e6..5207ecad127a2 100644
--- a/llvm/lib/Target/X86/X86InstrOperands.td
+++ b/llvm/lib/Target/X86/X86InstrOperands.td
@@ -6,9 +6,15 @@
//
//===--===//
+def x86_ptr_rc : RegClassByHwMode<
+ [X86_32, X86_64, X86_64_X32],
+ [GR32, GR64, LOW32_ADDR_ACCESS]>;
+
// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
// the index operand of an address, to conform to x86 encoding restrictions.
-def ptr_rc_nosp : PointerLikeRegClass<1>;
+def ptr_rc_nosp : RegClassByHwMode<
+ [X86_32, X86_64, X86_64_X32],
+ [GR32_NOSP, GR64_NOSP, GR32_NOSP]>;
// *mem - Operand definitions for the funky X86 addressing mode operands.
//
@@ -53,7 +59,7 @@ class X86MemOperand : Operand {
let PrintMethod = printMethod;
- let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
+ let MIOperandInfo = (ops x86_ptr_rc, i8imm, ptr_rc_nosp, i32imm,
SEGMENT_REG);
let ParserMatchClass = parserMatchClass;
let OperandType = "OPERAND_MEMORY";
int Size = size;
@@ -63,7 +69,7 @@ class X86MemOperand
: X86MemOperand {
- let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
+ let MIOperandInfo = (ops x86_ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
}
def anymem : X86MemOperand<"printMemReference">;
@@ -113,8 +119,14 @@ def sdmem : X86MemOperand<"printqwordmem",
X86Mem64AsmOperand>;
// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
// of a plain GPR, so that it doesn't potentially require a REX prefix.
-def ptr_rc_norex : PointerLikeRegClass<2>;
-def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
+def ptr_rc_norex : RegClassByHwMode<
+ [X86_32, X86_64, X86_64_X32],
+ [GR32_NOREX, GR64_NOREX, GR32_NOREX]>;
+
+def ptr_rc_norex_nosp : RegClassByHwMode<
+ [X86_32, X86_64, X86_64_X32],
+ [GR32_NOREX_NOSP, GR64_NOREX_NOSP, GR32_NOREX_NOSP]>;
+
def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> {
let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm,
@@ -123,7 +135,9 @@ def i8mem_NOREX : X86MemOperand<"print
[llvm-branch-commits] [llvm] [AllocToken, Clang] Implement __builtin_infer_alloc_token() and llvm.alloc.token.id (PR #156842)
melver wrote: > I would really prefer the codegen changes to be separate from the inference > pass. In this change, or in preceding ones? > What I _really_ want is a __builtin_infer_allocation_type(expr) that somehow > produces a human readable output - for the purpose of testing mostly as it's > of questionable real world use. You could imagine a hypothetical case where > it returns a human readable description of the inferred type information, and > a developer _could_ have a custom type descriptor that was "hash the string". > Though I remain on the "this would still be of questionable value outside of > test" side of the fence. Where are those tests? In the LLVM repo or outside? Because if it's inside the LLVM repo, we can already do exactly that, and that's also what the clang/test/CodeGenCXX/alloc-token-builtin.cpp test currently does (in one case it does not let the IR pass run, so we can check the type it inferred in the metadata). Of course, should all this become constexpr, we need the 2nd builtin. > Regardless, I'd then expect both `__builtin_infer_allocation_type` and > `__builtin_infer_allocation_token` to call the same underlying inference > routine, and just convert the output differently. > > `__builtin_infer_allocation*` also need to be able to be constant evaluated > so the can be used in consteval contexts, though that should just be a matter > of calling the method that does the inference, and then wrapping that in the > appropriate CE container For the `__builtin_infer_allocation_type` that'd be ok, but for `__builtin_infer_allocation_token` that won't work, because then we have to pull out all the token calculation logic in a way that Clang can access it. And some of that depends on configuration specific to the LLVM IR pass, that is not yet known. Not sure if there's a clean way other than somehow creating an API that can be used to do the token calculation that can be shared between Clang and IR pass. Preferences? https://github.com/llvm/llvm-project/pull/156842 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD transforms (PR #146074)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From 72a940883e91a0fc0c67454b1e01b8f96cae34ab Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH 1/2] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
transforms
This PR adds a TargetLowering hook, canTransformPtrArithOutOfBounds,
that targets can use to allow transformations to introduce out-of-bounds
pointer arithmetic. It also moves two such transformations from the
AMDGPU-specific DAG combines to the generic DAGCombiner.
This is motivated by target features like AArch64's checked pointer
arithmetic, CPA, which does not tolerate the introduction of
out-of-bounds pointer arithmetic.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 7 +
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 125 +++---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 59 ++---
llvm/lib/Target/AMDGPU/SIISelLowering.h | 3 +
4 files changed, 94 insertions(+), 100 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 46be271320fdd..4c2d991308d30 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3518,6 +3518,13 @@ class LLVM_ABI TargetLoweringBase {
return false;
}
+ /// True if the target allows transformations of in-bounds pointer
+ /// arithmetic that cause out-of-bounds intermediate results.
+ virtual bool canTransformPtrArithOutOfBounds(const Function &F,
+ EVT PtrVT) const {
+return false;
+ }
+
/// Does this target support complex deinterleaving
virtual bool isComplexDeinterleavingSupported() const { return false; }
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 77bc47f28fc80..67db08c3f9bac 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2696,59 +2696,82 @@ SDValue DAGCombiner::visitPTRADD(SDNode *N) {
if (PtrVT == IntVT && isNullConstant(N0))
return N1;
- if (N0.getOpcode() != ISD::PTRADD ||
- reassociationCanBreakAddressingModePattern(ISD::PTRADD, DL, N, N0, N1))
-return SDValue();
-
- SDValue X = N0.getOperand(0);
- SDValue Y = N0.getOperand(1);
- SDValue Z = N1;
- bool N0OneUse = N0.hasOneUse();
- bool YIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Y);
- bool ZIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Z);
-
- // (ptradd (ptradd x, y), z) -> (ptradd x, (add y, z)) if:
- // * y is a constant and (ptradd x, y) has one use; or
- // * y and z are both constants.
- if ((YIsConstant && N0OneUse) || (YIsConstant && ZIsConstant)) {
-// If both additions in the original were NUW, the new ones are as well.
-SDNodeFlags Flags =
-(N->getFlags() & N0->getFlags()) & SDNodeFlags::NoUnsignedWrap;
-SDValue Add = DAG.getNode(ISD::ADD, DL, IntVT, {Y, Z}, Flags);
-AddToWorklist(Add.getNode());
-return DAG.getMemBasePlusOffset(X, Add, DL, Flags);
+ if (N0.getOpcode() == ISD::PTRADD &&
+ !reassociationCanBreakAddressingModePattern(ISD::PTRADD, DL, N, N0, N1))
{
+SDValue X = N0.getOperand(0);
+SDValue Y = N0.getOperand(1);
+SDValue Z = N1;
+bool N0OneUse = N0.hasOneUse();
+bool YIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Y);
+bool ZIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Z);
+
+// (ptradd (ptradd x, y), z) -> (ptradd x, (add y, z)) if:
+// * y is a constant and (ptradd x, y) has one use; or
+// * y and z are both constants.
+if ((YIsConstant && N0OneUse) || (YIsConstant && ZIsConstant)) {
+ // If both additions in the original were NUW, the new ones are as well.
+ SDNodeFlags Flags =
+ (N->getFlags() & N0->getFlags()) & SDNodeFlags::NoUnsignedWrap;
+ SDValue Add = DAG.getNode(ISD::ADD, DL, IntVT, {Y, Z}, Flags);
+ AddToWorklist(Add.getNode());
+ return DAG.getMemBasePlusOffset(X, Add, DL, Flags);
+}
+ }
+
+ // The following combines can turn in-bounds pointer arithmetic out of
bounds.
+ // That is problematic for settings like AArch64's CPA, which checks that
+ // intermediate results of pointer arithmetic remain in bounds. The target
+ // therefore needs to opt-in to enable them.
+ if (!TLI.canTransformPtrArithOutOfBounds(
+ DAG.getMachineFunction().getFunction(), PtrVT))
+return SDValue();
+
+ if (N0.getOpcode() == ISD::PTRADD && N1.getOpcode() == ISD::Constant) {
+// Fold (ptradd (ptradd GA, v), c) -> (ptradd (ptradd GA, c) v) with
+// global address GA and constant c, such that c can be folded into GA.
+SDValue GAValue = N0.getOperand(0);
+if (const GlobalAddressSDNode *GA =
+dyn_cast(GAValue)) {
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ if (!LegalOperations && TLI.
[llvm-branch-commits] [llvm] AMDGPU: Stop using aligned VGPR classes for addRegisterClass (PR #158278)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158278
>From 96a4d9030b00b30f6aa7d9a70b191c1aaab1f2e8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass
This is unnecessary. At use emission time, InstrEmitter will
use the common subclass of the value type's register class and
the use instruction register classes. This removes one of the
obstacles to treating special case instructions that do not have
the alignment requirement overly conservatively.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 32 +++
llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 14 +-
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 363717b017ef0..37beb192293f9 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -111,52 +111,52 @@ SITargetLowering::SITargetLowering(const TargetMachine
&TM,
addRegisterClass(MVT::Untyped, V64RegClass);
addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
- addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
+ addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
- addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
+ addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
- addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
+ addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
- addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
+ addRegisterClass(MVT::v6f32, &AMDGPU::VReg_192RegClass);
addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
- addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
+ addRegisterClass(MVT::v3f64, &AMDGPU::VReg_192RegClass);
addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
- addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
+ addRegisterClass(MVT::v7f32, &AMDGPU::VReg_224RegClass);
addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
- addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
+ addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
- addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
+ addRegisterClass(MVT::v4f64, &AMDGPU::VReg_256RegClass);
addRegisterClass(MVT::v9i32, &AMDGPU::SGPR_288RegClass);
- addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288));
+ addRegisterClass(MVT::v9f32, &AMDGPU::VReg_288RegClass);
addRegisterClass(MVT::v10i32, &AMDGPU::SGPR_320RegClass);
- addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320));
+ addRegisterClass(MVT::v10f32, &AMDGPU::VReg_320RegClass);
addRegisterClass(MVT::v11i32, &AMDGPU::SGPR_352RegClass);
- addRegisterClass(MVT::v11f32, TRI->getVGPRClassForBitWidth(352));
+ addRegisterClass(MVT::v11f32, &AMDGPU::VReg_352RegClass);
addRegisterClass(MVT::v12i32, &AMDGPU::SGPR_384RegClass);
- addRegisterClass(MVT::v12f32, TRI->getVGPRClassForBitWidth(384));
+ addRegisterClass(MVT::v12f32, &AMDGPU::VReg_384RegClass);
addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
- addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
+ addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
- addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
+ addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
- addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
+ addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
if (Subtarget->has16BitInsts()) {
if (Subtarget->useRealTrue16Insts()) {
@@ -188,7 +188,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
}
addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
- addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
+ addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
computeRegisterProperties(Subtarget->getRegisterInfo());
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index 0af655dfbbee9..4bb653848cbf0 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -2399,8 +2399,9 @@ define amdgpu_kernel void
@test_mfma_nested_loop_zeroinit(ptr addrspace(1) %arg)
; GFX90A-NEXT:v_accvgpr_mov_b32 a29, a0
; GFX90A-NEXT:v_accvgpr_mov_b32 a30, a0
; GFX90A-NEXT
[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)
https://github.com/melver updated https://github.com/llvm/llvm-project/pull/156839 >From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Thu, 4 Sep 2025 12:07:26 +0200 Subject: [PATCH] fixup! Insert AllocToken into index.rst Created using spr 1.3.8-beta.1 --- clang/docs/index.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/docs/index.rst b/clang/docs/index.rst index be654af57f890..aa2b3a73dc11b 100644 --- a/clang/docs/index.rst +++ b/clang/docs/index.rst @@ -40,6 +40,7 @@ Using Clang as a Compiler SanitizerCoverage SanitizerStats SanitizerSpecialCaseList + AllocToken BoundsSafety BoundsSafetyAdoptionGuide BoundsSafetyImplPlans ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [mlir] [flang][OpenMP] Support multi-block reduction combiner regions on the GPU (PR #156837)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/156837 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lit] Remove python 2.7 code paths in builtin diff (PR #157558)
https://github.com/ilovepi approved this pull request. This seems fine to me, especially since it follows our written policy on version support. Does this need any kind of release note? It's a pure dev dependency, so I'd say "no", but I could also see how a consumer would have wanted to know about it. https://github.com/llvm/llvm-project/pull/157558 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [not] Update disable-symbolization.test to work with internal shell (PR #157236)
boomanaiden154 wrote: > Should we update the lit implementation handling for not/env to avoid > reordering those two commands when combined? We theoretically can, but it's not that simple. The test runner already explicitly reorders them due to how `not` needs to be run. I'm not sure of exact test cases where the following is relevant, but it seems like it would be difficult to tease apart, and was not worth it for this test based on my assessment: https://github.com/llvm/llvm-project/blob/d2646cac857294604afaae67f165323b0af35430/llvm/utils/lit/lit/TestRunner.py#L851 https://github.com/llvm/llvm-project/pull/157236 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [libc++] Test triggering a benchmarking job comment (PR #158138)
https://github.com/ldionne converted_to_draft https://github.com/llvm/llvm-project/pull/158138 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Use lit internal shell by default (PR #157237)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/157237 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][CodeGen][CFI] Add GeneralizePointers parameter to GeneralizeFunctionType (PR #158191)
https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/158191 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (PR #157810)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/157810 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/21.x: MC: Better handle backslash-escaped symbols (PR #159420)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/159420 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-remarkutil] Introduce filter command (PR #159784)
https://github.com/tobias-stadler created https://github.com/llvm/llvm-project/pull/159784 Add a filter command to llvm-remarkutil. This can be used to extract remarks for a certain function, pass, type, etc. from a large remarks file to a new remarks file. This uses the same filter arguments as the count command. Depends on #156715. Thanks to this change, we don't need to buffer all remarks before reserializing them, so we should be able to process arbitrarily large files. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 9907ef2 - Revert "RISCV enable assembly unwinding (#158161)"
Author: David Spickett
Date: 2025-09-19T16:19:19+01:00
New Revision: 9907ef2d116b893e0c3cce2cbf228ce52a82a285
URL:
https://github.com/llvm/llvm-project/commit/9907ef2d116b893e0c3cce2cbf228ce52a82a285
DIFF:
https://github.com/llvm/llvm-project/commit/9907ef2d116b893e0c3cce2cbf228ce52a82a285.diff
LOG: Revert "RISCV enable assembly unwinding (#158161)"
This reverts commit 1c95d80ba68efd2ca9a0336529ea5fb7dc871417.
Added:
Modified:
lldb/include/lldb/Core/Opcode.h
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
lldb/unittests/Instruction/CMakeLists.txt
Removed:
lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp
diff --git a/lldb/include/lldb/Core/Opcode.h b/lldb/include/lldb/Core/Opcode.h
index 7e756d3f15d22..7bbd73d039f99 100644
--- a/lldb/include/lldb/Core/Opcode.h
+++ b/lldb/include/lldb/Core/Opcode.h
@@ -223,9 +223,7 @@ class Opcode {
int Dump(Stream *s, uint32_t min_byte_width) const;
const void *GetOpcodeBytes() const {
-return ((m_type == Opcode::eTypeBytes || m_type ==
Opcode::eType16_32Tuples)
-? m_data.inst.bytes
-: nullptr);
+return ((m_type == Opcode::eTypeBytes) ? m_data.inst.bytes : nullptr);
}
uint32_t GetByteSize() const {
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 20661290ca4c6..5e429a92613ce 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -33,10 +33,6 @@ LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionRISCV,
InstructionRISCV)
namespace lldb_private {
-// RISC-V General Purpose Register numbers
-static constexpr uint32_t RISCV_GPR_SP = 2; // x2 is the stack pointer
-static constexpr uint32_t RISCV_GPR_FP = 8; // x8 is the frame pointer
-
/// Returns all values wrapped in Optional, or std::nullopt if any of the
values
/// is std::nullopt.
template
@@ -112,16 +108,6 @@ static uint32_t FPREncodingToLLDB(uint32_t reg_encode) {
return LLDB_INVALID_REGNUM;
}
-// Helper function to get register info from GPR encoding
-static std::optional
-GPREncodingToRegisterInfo(EmulateInstructionRISCV &emulator,
- uint32_t reg_encode) {
- uint32_t lldb_reg = GPREncodingToLLDB(reg_encode);
- if (lldb_reg == LLDB_INVALID_REGNUM)
-return std::nullopt;
- return emulator.GetRegisterInfo(eRegisterKindLLDB, lldb_reg);
-}
-
bool Rd::Write(EmulateInstructionRISCV &emulator, uint64_t value) {
uint32_t lldb_reg = GPREncodingToLLDB(rd);
EmulateInstruction::Context ctx;
@@ -244,34 +230,10 @@ Load(EmulateInstructionRISCV &emulator, I inst, uint64_t
(*extend)(E)) {
auto addr = LoadStoreAddr(emulator, inst);
if (!addr)
return false;
-
- // Set up context for the load operation, similar to ARM64.
- EmulateInstructionRISCV::Context context;
-
- // Get register info for base register
- std::optional reg_info_rs1 =
- GPREncodingToRegisterInfo(emulator, inst.rs1.rs);
-
- if (!reg_info_rs1)
-return false;
-
- // Set context type based on whether this is a stack-based load.
- if (inst.rs1.rs == RISCV_GPR_SP)
-context.type = EmulateInstruction::eContextPopRegisterOffStack;
- else
-context.type = EmulateInstruction::eContextRegisterLoad;
-
- // Set the context address information
- context.SetAddress(*addr);
-
- // Read from memory with context and write to register.
- bool success = false;
- uint64_t value =
- emulator.ReadMemoryUnsigned(context, *addr, sizeof(T), 0, &success);
- if (!success)
-return false;
-
- return inst.rd.Write(emulator, extend(E(T(value;
+ return transformOptional(
+ emulator.ReadMem(*addr),
+ [&](T t) { return inst.rd.Write(emulator, extend(E(t))); })
+ .value_or(false);
}
template
@@ -280,35 +242,9 @@ Store(EmulateInstructionRISCV &emulator, I inst) {
auto addr = LoadStoreAddr(emulator, inst);
if (!addr)
return false;
-
- // Set up context for the store operation, similar to ARM64.
- EmulateInstructionRISCV::Context context;
-
- // Get register info for source and base registers.
- std::optional reg_info_rs1 =
- GPREncodingToRegisterInfo(emulator, inst.rs1.rs);
- std::optional reg_info_rs2 =
- GPREncodingToRegisterInfo(emulator, inst.rs2.rs);
-
- if (!reg_info_rs1 || !reg_info_rs2)
-return false;
-
- // Set context type based on whether this is a stack-based store.
- if (inst.rs1.rs == RISCV_GPR_SP)
-context.type = EmulateInstruction::eContextPushRegisterOnStack;
- else
-context.type = EmulateInstruction::eContextRegisterStore;
-
- // Set the context to show which register is being stored to which base
- // register + offset.
- context.SetRegisterToRegi
[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/158447
>From 5bd8d4f925f3b5f82d85ef693861b6b1067d9f38 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 22:54:58 +
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
---
clang/test/Misc/dev-fd-fs.c| 1 -
llvm/utils/lit/lit/builtin_commands/cat.py | 3 +++
llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt | 4
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index ea94d950b0716..b989ab8a439cf 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -1,6 +1,5 @@
// Check that we can operate on files from /dev/fd.
// REQUIRES: dev-fd-fs
-// REQUIRES: shell
// Check reading from named pipes. We cat the input here instead of redirecting
// it to ensure that /dev/fd/0 is a named pipe, not just a redirected file.
diff --git a/llvm/utils/lit/lit/builtin_commands/cat.py
b/llvm/utils/lit/lit/builtin_commands/cat.py
index ddab555662045..2797e0cbb4154 100644
--- a/llvm/utils/lit/lit/builtin_commands/cat.py
+++ b/llvm/utils/lit/lit/builtin_commands/cat.py
@@ -49,6 +49,9 @@ def main(argv):
import os, msvcrt
msvcrt.setmode(sys.stdout.fileno(), os.O_BINARY)
+if len(filenames) == 0:
+sys.stdout.write(sys.stdin.read())
+sys.exit(0)
for filename in filenames:
try:
contents = None
diff --git a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
index 4014b0fca1f24..c5b5d247c2f95 100644
--- a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
+++ b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
@@ -70,3 +70,7 @@
#
NP-CAT-OUTPUT-NEXT:M-HM-IM-JM-KM-LM-MM-NM-OM-PM-QM-RM-SM-TM-UM-VM-WM-XM-YM-ZM-[
#
NP-CAT-OUTPUT-NEXT:M-\M-]M-^M-_M-`M-aM-bM-cM-dM-eM-fM-gM-hM-iM-jM-kM-lM-mM-nM-o
# NP-CAT-OUTPUT-NEXT:M-pM-qM-rM-sM-tM-uM-vM-wM-xM-yM-zM-{M-|M-}M-~M-^?
+
+## Test that cat will pipe stdin to stdout if no other files are specified.
+# RUN: echo test | cat | FileCheck --check-prefix=CAT-STDIN %s
+# CAT-STDIN: test
>From 572975066e843b76e51020bcf6abc7822d3dfb75 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 23:14:52 +
Subject: [PATCH 2/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
[skip ci]
---
clang/test/ClangScanDeps/pr61006.cppm | 3 ++-
clang/test/ClangScanDeps/resource_directory.c | 9 -
clang/test/Driver/env.c | 5 +++--
clang/test/Driver/program-path-priority.c | 16 +++
clang/test/Modules/relative-resource-dir.m| 6 +++---
llvm/docs/CommandGuide/lit.rst| 1 +
llvm/test/tools/llvm-cgdata/empty.test| 1 +
llvm/utils/lit/lit/TestRunner.py | 20 +++
.../Inputs/shtest-readfile/absolute-paths.txt | 6 ++
.../lit/tests/Inputs/shtest-readfile/lit.cfg | 8
.../Inputs/shtest-readfile/relative-paths.txt | 7 +++
.../Inputs/shtest-readfile/two-same-line.txt | 8
llvm/utils/lit/tests/shtest-readfile.py | 17
13 files changed, 88 insertions(+), 19 deletions(-)
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/absolute-paths.txt
create mode 100644 llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/relative-paths.txt
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/two-same-line.txt
create mode 100644 llvm/utils/lit/tests/shtest-readfile.py
diff --git a/clang/test/ClangScanDeps/pr61006.cppm
b/clang/test/ClangScanDeps/pr61006.cppm
index f75edd38c81ba..f10bc1e673987 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -6,7 +6,8 @@
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
-// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \
+// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
+// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
// RUN: ln -s %clang++ %t/clang++ && \
// RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g"
%t/P1689.json.in > %t/P1689.json && \
// RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 |
FileCheck %t/a.cpp -DPREFIX=%/t && \
diff --git a/clang/test/ClangScanDeps/resource_directory.c
b/clang/test/ClangScanDeps/resource_directory.c
index 55d5d90bbcdea..6183e8aefacfa 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -12,14 +12,14 @@
//
[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/158447
>From 5bd8d4f925f3b5f82d85ef693861b6b1067d9f38 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 22:54:58 +
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
---
clang/test/Misc/dev-fd-fs.c| 1 -
llvm/utils/lit/lit/builtin_commands/cat.py | 3 +++
llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt | 4
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index ea94d950b0716..b989ab8a439cf 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -1,6 +1,5 @@
// Check that we can operate on files from /dev/fd.
// REQUIRES: dev-fd-fs
-// REQUIRES: shell
// Check reading from named pipes. We cat the input here instead of redirecting
// it to ensure that /dev/fd/0 is a named pipe, not just a redirected file.
diff --git a/llvm/utils/lit/lit/builtin_commands/cat.py
b/llvm/utils/lit/lit/builtin_commands/cat.py
index ddab555662045..2797e0cbb4154 100644
--- a/llvm/utils/lit/lit/builtin_commands/cat.py
+++ b/llvm/utils/lit/lit/builtin_commands/cat.py
@@ -49,6 +49,9 @@ def main(argv):
import os, msvcrt
msvcrt.setmode(sys.stdout.fileno(), os.O_BINARY)
+if len(filenames) == 0:
+sys.stdout.write(sys.stdin.read())
+sys.exit(0)
for filename in filenames:
try:
contents = None
diff --git a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
index 4014b0fca1f24..c5b5d247c2f95 100644
--- a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
+++ b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
@@ -70,3 +70,7 @@
#
NP-CAT-OUTPUT-NEXT:M-HM-IM-JM-KM-LM-MM-NM-OM-PM-QM-RM-SM-TM-UM-VM-WM-XM-YM-ZM-[
#
NP-CAT-OUTPUT-NEXT:M-\M-]M-^M-_M-`M-aM-bM-cM-dM-eM-fM-gM-hM-iM-jM-kM-lM-mM-nM-o
# NP-CAT-OUTPUT-NEXT:M-pM-qM-rM-sM-tM-uM-vM-wM-xM-yM-zM-{M-|M-}M-~M-^?
+
+## Test that cat will pipe stdin to stdout if no other files are specified.
+# RUN: echo test | cat | FileCheck --check-prefix=CAT-STDIN %s
+# CAT-STDIN: test
>From 572975066e843b76e51020bcf6abc7822d3dfb75 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 23:14:52 +
Subject: [PATCH 2/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
[skip ci]
---
clang/test/ClangScanDeps/pr61006.cppm | 3 ++-
clang/test/ClangScanDeps/resource_directory.c | 9 -
clang/test/Driver/env.c | 5 +++--
clang/test/Driver/program-path-priority.c | 16 +++
clang/test/Modules/relative-resource-dir.m| 6 +++---
llvm/docs/CommandGuide/lit.rst| 1 +
llvm/test/tools/llvm-cgdata/empty.test| 1 +
llvm/utils/lit/lit/TestRunner.py | 20 +++
.../Inputs/shtest-readfile/absolute-paths.txt | 6 ++
.../lit/tests/Inputs/shtest-readfile/lit.cfg | 8
.../Inputs/shtest-readfile/relative-paths.txt | 7 +++
.../Inputs/shtest-readfile/two-same-line.txt | 8
llvm/utils/lit/tests/shtest-readfile.py | 17
13 files changed, 88 insertions(+), 19 deletions(-)
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/absolute-paths.txt
create mode 100644 llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/relative-paths.txt
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/two-same-line.txt
create mode 100644 llvm/utils/lit/tests/shtest-readfile.py
diff --git a/clang/test/ClangScanDeps/pr61006.cppm
b/clang/test/ClangScanDeps/pr61006.cppm
index f75edd38c81ba..f10bc1e673987 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -6,7 +6,8 @@
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
-// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \
+// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
+// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
// RUN: ln -s %clang++ %t/clang++ && \
// RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g"
%t/P1689.json.in > %t/P1689.json && \
// RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 |
FileCheck %t/a.cpp -DPREFIX=%/t && \
diff --git a/clang/test/ClangScanDeps/resource_directory.c
b/clang/test/ClangScanDeps/resource_directory.c
index 55d5d90bbcdea..6183e8aefacfa 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -12,14 +12,14 @@
//
[llvm-branch-commits] [Clang] Make rewrite-includes-bom.c work with internal shell (PR #158463)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158463 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Clang] Rewrite tests using subshells to set env variables (PR #158446)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/158446
>From 3ea0a2c82a707adde245d0aaa293c26afa84eb91 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Fri, 19 Sep 2025 23:03:05 +
Subject: [PATCH] fix CI
Created using spr 1.3.6
---
clang/test/ClangScanDeps/pr61006.cppm | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/ClangScanDeps/pr61006.cppm
b/clang/test/ClangScanDeps/pr61006.cppm
index f10bc1e673987..6c3783308b645 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -7,7 +7,7 @@
// RUN: split-file %s %t
//
// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
-// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
+// RUN: export EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir}
// RUN: ln -s %clang++ %t/clang++ && \
// RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g"
%t/P1689.json.in > %t/P1689.json && \
// RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 |
FileCheck %t/a.cpp -DPREFIX=%/t && \
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[llvm-branch-commits] [llvm] release/21.x: [Loads] Check for overflow when adding MaxPtrDiff + Offset. (PR #158918)
https://github.com/annamthomas approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/158918 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [profcheck][SimplifyCFG] Propagate !prof from `switch` to `select` (PR #159645)
https://github.com/alanzhao1 commented: In general this patch LGTM. I noticed that one downside of using `-profcheck-weights-for-test` is that the original branch weights aren't in the test, so it's hard for me to understand how this change modifies the branch weights. https://github.com/llvm/llvm-project/pull/159645 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/21.x: [RISCV] Re-work how VWADD_W_VL and similar _W_VL nodes are handled in combineOp_VLToVWOp_VL. (#159205) (PR #159891)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/159891 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regclass to use by using
-/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
-///
-/// This is deprecated in favor of RegClassByHwMode.
+/// PointerLikeRegClass - Pseudoinstruction operands that are designed
+/// to have pointer width are derived from this. This should only be
+/// used by StandardPseudoInstruction instructions. No target specific
+/// instruction should use this.
class PointerLikeRegClass {
int RegClassKind = Kind;
}
+/// ptr_rc definition - Mark this operand as being a pointer value
+/// whose register class needs to be defined by the target. Targets
+/// should provide instruction definition overrides which substitute
+/// the uses of this with the backend defined RegisterClass or
+/// RegClassByHwMode to use for pointer virtual registers for a
+/// particular opcode (typically by defining a subsitute instruction
+/// with RemapPointerOperands).
+def ptr_rc : PointerLikeRegClass<0>;
s-barannikov wrote:
Never mind, found the answer in a PR down the stack.
https://github.com/llvm/llvm-project/pull/159883
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[llvm-branch-commits] [llvm] CodeGen: Make all targets override pseudos with pointers (PR #159881)
llvmbot wrote:
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-tablegen
Author: Matt Arsenault (arsenm)
Changes
This eliminates the need to have PointerLikeRegClass handling in
codegen.
---
Full diff: https://github.com/llvm/llvm-project/pull/159881.diff
26 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64.td (+2)
- (modified) llvm/lib/Target/AMDGPU/R600.td (+12-9)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+11)
- (modified) llvm/lib/Target/ARM/ARM.td (+8)
- (modified) llvm/lib/Target/AVR/AVR.td (+2)
- (modified) llvm/lib/Target/BPF/BPF.td (+3)
- (modified) llvm/lib/Target/CSKY/CSKY.td (+2)
- (modified) llvm/lib/Target/DirectX/DirectX.td (+2)
- (modified) llvm/lib/Target/Hexagon/Hexagon.td (+2)
- (modified) llvm/lib/Target/Lanai/Lanai.td (+2)
- (modified) llvm/lib/Target/LoongArch/LoongArch.td (+2)
- (modified) llvm/lib/Target/M68k/M68k.td (+2)
- (modified) llvm/lib/Target/MSP430/MSP430.td (+2)
- (modified) llvm/lib/Target/Mips/Mips.td (+2)
- (modified) llvm/lib/Target/NVPTX/NVPTX.td (+10)
- (modified) llvm/lib/Target/PowerPC/PPC.td (+2)
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.td (+4)
- (modified) llvm/lib/Target/RISCV/RISCV.td (+2)
- (modified) llvm/lib/Target/SPIRV/SPIRV.td (+2)
- (modified) llvm/lib/Target/Sparc/Sparc.td (+2)
- (modified) llvm/lib/Target/SystemZ/SystemZ.td (+3-1)
- (modified) llvm/lib/Target/VE/VE.td (+1)
- (modified) llvm/lib/Target/WebAssembly/WebAssembly.td (+8)
- (modified) llvm/lib/Target/X86/X86.td (+2)
- (modified) llvm/lib/Target/XCore/XCore.td (+2)
- (modified) llvm/lib/Target/Xtensa/Xtensa.td (+2)
``diff
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 86f95488e6bb7..d98c235dab15e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -40,6 +40,8 @@ include "AArch64SchedPredExynos.td"
include "AArch64SchedPredNeoverse.td"
include "AArch64Combine.td"
+defm : RemapAllTargetPseudoPointerOperands;
+
def AArch64InstrInfo : InstrInfo;
//===--===//
diff --git a/llvm/lib/Target/AMDGPU/R600.td b/llvm/lib/Target/AMDGPU/R600.td
index 9148edb92b084..bdfaac9f42ea7 100644
--- a/llvm/lib/Target/AMDGPU/R600.td
+++ b/llvm/lib/Target/AMDGPU/R600.td
@@ -8,15 +8,6 @@
include "llvm/Target/Target.td"
-def R600InstrInfo : InstrInfo {
- let guessInstructionProperties = 1;
-}
-
-def R600 : Target {
- let InstructionSet = R600InstrInfo;
- let AllowRegisterRenaming = 1;
-}
-
let Namespace = "R600" in {
foreach Index = 0-15 in {
@@ -27,6 +18,18 @@ include "R600RegisterInfo.td"
}
+defm : RemapAllTargetPseudoPointerOperands;
+
+def R600InstrInfo : InstrInfo {
+ let guessInstructionProperties = 1;
+}
+
+def R600 : Target {
+ let InstructionSet = R600InstrInfo;
+ let AllowRegisterRenaming = 1;
+}
+
+
def NullALU : InstrItinClass;
def ALU_NULL : FuncUnit;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td
b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 88a26832980d6..eecccd2e0e395 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4745,3 +4745,14 @@ def V_ILLEGAL : Enc32, InstSI<(outs), (ins),
"v_illegal"> {
let hasSideEffects = 1;
let SubtargetPredicate = isGFX10Plus;
}
+
+defvar VGPR32_Ptr_Opcodes = [LOAD_STACK_GUARD];
+defvar VGPR64_Ptr_Opcodes = !listremove(PseudosWithPtrOps, VGPR32_Ptr_Opcodes);
+
+foreach inst = VGPR32_Ptr_Opcodes in {
+ def : RemapPointerOperands;
+}
+
+foreach inst = VGPR64_Ptr_Opcodes in {
+ def : RemapPointerOperands;
+}
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 570aae9b3c7a7..1f71d810983db 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -38,6 +38,14 @@ include "ARMSchedule.td"
//===--===//
include "ARMInstrInfo.td"
+
+def Thumb1OnlyMode : HwMode<[IsThumb1Only]>;
+def arm_ptr_rc : RegClassByHwMode<
+ [DefaultMode, Thumb1OnlyMode],
+ [GPR, tGPR]>;
+
+defm : RemapAllTargetPseudoPointerOperands;
+
def ARMInstrInfo : InstrInfo;
//===--===//
diff --git a/llvm/lib/Target/AVR/AVR.td b/llvm/lib/Target/AVR/AVR.td
index 22ffc4a368ad6..f4ee11984cb73 100644
--- a/llvm/lib/Target/AVR/AVR.td
+++ b/llvm/lib/Target/AVR/AVR.td
@@ -32,6 +32,8 @@ include "AVRRegisterInfo.td"
include "AVRInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands;
+
def AVRInstrInfo : InstrInfo;
//===-===//
diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td
index dff76ca07af51..399be731b44f6 100644
--- a/llvm/lib/Target/BPF/BPF.td
+++ b/llvm/lib/Target/BPF/BPF.td
@@ -13,6 +13,9 @@ include "BPFCallingConv.td"
include "BPFInstrInfo.td"
include "GISel/BPFRegisterBanks.td"
+
+defm :
[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)
https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/105735 >From e4bd1181d160b8728e7d4158417a83e183bd1709 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Thu, 22 Aug 2024 14:36:04 -0700 Subject: [PATCH 1/5] fix indentation in langref Created using spr 1.3.6-beta.1 --- llvm/docs/LangRef.rst | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 200224c78be00..1a59fba65815c 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3103,19 +3103,19 @@ as follows: ``A`` Specifies the address space of objects created by '``alloca``'. Defaults to the default address space of 0. -``p[][n]::[:][:]`` +``p[][]::[:][:]`` This specifies the *size* of a pointer and its and \erred alignments for address space ``n``. is optional and defaults to . The fourth parameter is the size of the index that used for address calculation, which must be less than or equal to the pointer size. If not specified, the default index size is equal to the pointer size. All sizes -are in bits. The address space, ``n``, is optional, and if not specified, -denotes the default address space 0. The value of ``n`` must be -in the range [1,2^24). +are in bits. The , is optional, and if not specified, +denotes the default address space 0. The value of must +be in the range [1,2^24). The optional are used to specify properties of pointers in this -address space: the character ``u`` marks pointers as having an unstable -representation and ```n`` marks pointers as non-integral (i.e. having +address space: the character ``u`` marks pointers as having an unstable +representation and ``n`` marks pointers as non-integral (i.e. having additional metadata). See :ref:`Non-Integral Pointer Types `. ``i:[:]`` >From db97145d3a653f2999b5935f9b1cb4550230689d Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Fri, 25 Oct 2024 12:51:11 -0700 Subject: [PATCH 2/5] include feedback Created using spr 1.3.6-beta.1 --- llvm/docs/LangRef.rst | 30 +- llvm/include/llvm/IR/DataLayout.h | 8 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index c137318af678b..3c3d0e0b4ab8e 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -659,7 +659,7 @@ LLVM IR optionally allows the frontend to denote pointers in certain address spaces as "non-integral" or "unstable" (or both "non-integral" and "unstable") via the :ref:`datalayout string`. -These exact implications of these properties are target-specific, but the +The exact implications of these properties are target-specific, but the following IR semantics and restrictions to optimization passes apply: Unstable pointer representation @@ -668,7 +668,7 @@ Unstable pointer representation Pointers in this address space have an *unspecified* bitwise representation (i.e. not backed by a fixed integer). The bitwise pattern of such pointers is allowed to change in a target-specific way. For example, this could be a pointer -type used for with copying garbage collection where the garbage collector could +type used with copying garbage collection where the garbage collector could update the pointer at any time in the collection sweep. ``inttoptr`` and ``ptrtoint`` instructions have the same semantics as for @@ -705,10 +705,10 @@ representation of the pointer. Non-integral pointer representation ^^^ -Pointers are not represented as an address, but may instead include +Pointers are not represented as just an address, but may instead include additional metadata such as bounds information or a temporal identifier. Examples include AMDGPU buffer descriptors with a 128-bit fat pointer and a -32-bit offset or CHERI capabilities that contain bounds, permissions and an +32-bit offset, or CHERI capabilities that contain bounds, permissions and an out-of-band validity bit. In general, these pointers cannot be re-created from just an integer value. @@ -716,23 +716,25 @@ In most cases pointers with a non-integral representation behave exactly the same as an integral pointer, the only difference is that it is not possible to create a pointer just from an address. -"Non-integral" pointers also impose restrictions on the optimizer, but in -general these are less restrictive than for "unstable" pointers. The main +"Non-integral" pointers also impose restrictions on transformation passes, but +in general these are less restrictive than for "unstable" pointers. The main difference compared to integral pointers is that ``inttoptr`` instructions should not be inserted by passes as they may not be able to create a valid pointer. This property also means that ``inttoptr(ptrtoint(x))`` cannot be folded to ``x`` as the ``ptrt
[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)
https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/105735 >From e4bd1181d160b8728e7d4158417a83e183bd1709 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Thu, 22 Aug 2024 14:36:04 -0700 Subject: [PATCH 1/5] fix indentation in langref Created using spr 1.3.6-beta.1 --- llvm/docs/LangRef.rst | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 200224c78be00..1a59fba65815c 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3103,19 +3103,19 @@ as follows: ``A`` Specifies the address space of objects created by '``alloca``'. Defaults to the default address space of 0. -``p[][n]::[:][:]`` +``p[][]::[:][:]`` This specifies the *size* of a pointer and its and \erred alignments for address space ``n``. is optional and defaults to . The fourth parameter is the size of the index that used for address calculation, which must be less than or equal to the pointer size. If not specified, the default index size is equal to the pointer size. All sizes -are in bits. The address space, ``n``, is optional, and if not specified, -denotes the default address space 0. The value of ``n`` must be -in the range [1,2^24). +are in bits. The , is optional, and if not specified, +denotes the default address space 0. The value of must +be in the range [1,2^24). The optional are used to specify properties of pointers in this -address space: the character ``u`` marks pointers as having an unstable -representation and ```n`` marks pointers as non-integral (i.e. having +address space: the character ``u`` marks pointers as having an unstable +representation and ``n`` marks pointers as non-integral (i.e. having additional metadata). See :ref:`Non-Integral Pointer Types `. ``i:[:]`` >From db97145d3a653f2999b5935f9b1cb4550230689d Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Fri, 25 Oct 2024 12:51:11 -0700 Subject: [PATCH 2/5] include feedback Created using spr 1.3.6-beta.1 --- llvm/docs/LangRef.rst | 30 +- llvm/include/llvm/IR/DataLayout.h | 8 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index c137318af678b..3c3d0e0b4ab8e 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -659,7 +659,7 @@ LLVM IR optionally allows the frontend to denote pointers in certain address spaces as "non-integral" or "unstable" (or both "non-integral" and "unstable") via the :ref:`datalayout string`. -These exact implications of these properties are target-specific, but the +The exact implications of these properties are target-specific, but the following IR semantics and restrictions to optimization passes apply: Unstable pointer representation @@ -668,7 +668,7 @@ Unstable pointer representation Pointers in this address space have an *unspecified* bitwise representation (i.e. not backed by a fixed integer). The bitwise pattern of such pointers is allowed to change in a target-specific way. For example, this could be a pointer -type used for with copying garbage collection where the garbage collector could +type used with copying garbage collection where the garbage collector could update the pointer at any time in the collection sweep. ``inttoptr`` and ``ptrtoint`` instructions have the same semantics as for @@ -705,10 +705,10 @@ representation of the pointer. Non-integral pointer representation ^^^ -Pointers are not represented as an address, but may instead include +Pointers are not represented as just an address, but may instead include additional metadata such as bounds information or a temporal identifier. Examples include AMDGPU buffer descriptors with a 128-bit fat pointer and a -32-bit offset or CHERI capabilities that contain bounds, permissions and an +32-bit offset, or CHERI capabilities that contain bounds, permissions and an out-of-band validity bit. In general, these pointers cannot be re-created from just an integer value. @@ -716,23 +716,25 @@ In most cases pointers with a non-integral representation behave exactly the same as an integral pointer, the only difference is that it is not possible to create a pointer just from an address. -"Non-integral" pointers also impose restrictions on the optimizer, but in -general these are less restrictive than for "unstable" pointers. The main +"Non-integral" pointers also impose restrictions on transformation passes, but +in general these are less restrictive than for "unstable" pointers. The main difference compared to integral pointers is that ``inttoptr`` instructions should not be inserted by passes as they may not be able to create a valid pointer. This property also means that ``inttoptr(ptrtoint(x))`` cannot be folded to ``x`` as the ``ptrt
[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)
https://github.com/arichardson edited https://github.com/llvm/llvm-project/pull/105735 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff origin/main HEAD --extensions cpp --
clang/lib/Analysis/LifetimeSafety.cpp
``
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
View the diff from clang-format here.
``diff
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index ac761d73b..0fd09cf63 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -968,7 +968,8 @@ using ExpiredLoanMap = llvm::ImmutableMap;
struct LifetimeFactory {
OriginLoanMap::Factory OriginMapFactory = OriginLoanMap::Factory(false);
LoanSet::Factory LoanSetFactory = LoanSet::Factory(false);
- ExpiredLoanMap::Factory ExpiredLoanMapFactory =
ExpiredLoanMap::Factory(false);
+ ExpiredLoanMap::Factory ExpiredLoanMapFactory =
+ ExpiredLoanMap::Factory(false);
};
/// Represents the dataflow lattice for loan propagation.
``
https://github.com/llvm/llvm-project/pull/159850
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[llvm-branch-commits] [clang] [LifetimeSafety] Disable canonicalization in immutable collections (PR #159850)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/159850
>From 0775d9ec1d9dffb1b2e29f28d986384660ae77d2 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Fri, 19 Sep 2025 21:30:46 +
Subject: [PATCH] no-canonicalize
---
clang/lib/Analysis/LifetimeSafety.cpp | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 0dd5716d93fb6..da4af42853e55 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -966,9 +966,13 @@ using ExpiredLoanMap = llvm::ImmutableMap;
/// An object to hold the factories for immutable collections, ensuring
/// that all created states share the same underlying memory management.
struct LifetimeFactory {
- OriginLoanMap::Factory OriginMapFactory;
- LoanSet::Factory LoanSetFactory;
- ExpiredLoanMap::Factory ExpiredLoanMapFactory;
+ llvm::BumpPtrAllocator Allocator;
+ OriginLoanMap::Factory OriginMapFactory =
+ OriginLoanMap::Factory(Allocator, /*canonicalize=*/false);
+ LoanSet::Factory LoanSetFactory =
+ LoanSet::Factory(Allocator, /*canonicalize=*/false);
+ ExpiredLoanMap::Factory ExpiredLoanMapFactory =
+ ExpiredLoanMap::Factory(Allocator, /*canonicalize=*/false);
};
/// Represents the dataflow lattice for loan propagation.
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[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/159850
>From 9916bece21522597542492e3209166518b9a5e6d Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Fri, 19 Sep 2025 21:30:46 +
Subject: [PATCH] no-canonicalize
---
clang/lib/Analysis/LifetimeSafety.cpp | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 0dd5716d93fb6..43cab406a9dc3 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -966,9 +966,12 @@ using ExpiredLoanMap = llvm::ImmutableMap;
/// An object to hold the factories for immutable collections, ensuring
/// that all created states share the same underlying memory management.
struct LifetimeFactory {
- OriginLoanMap::Factory OriginMapFactory;
- LoanSet::Factory LoanSetFactory;
- ExpiredLoanMap::Factory ExpiredLoanMapFactory;
+ // Avoid canonicalising
+ OriginLoanMap::Factory OriginMapFactory =
+ OriginLoanMap::Factory(/*canonicalize=*/false);
+ LoanSet::Factory LoanSetFactory = LoanSet::Factory(/*canonicalize=*/false);
+ ExpiredLoanMap::Factory ExpiredLoanMapFactory =
+ ExpiredLoanMap::Factory(/*canonicalize=*/false);
};
/// Represents the dataflow lattice for loan propagation.
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Disable canonicalization in immutable collections (PR #159850)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Clang] Rewrite tests using subshells to set env variables (PR #158446)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158446 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/158447
>From 5bd8d4f925f3b5f82d85ef693861b6b1067d9f38 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 22:54:58 +
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
---
clang/test/Misc/dev-fd-fs.c| 1 -
llvm/utils/lit/lit/builtin_commands/cat.py | 3 +++
llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt | 4
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index ea94d950b0716..b989ab8a439cf 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -1,6 +1,5 @@
// Check that we can operate on files from /dev/fd.
// REQUIRES: dev-fd-fs
-// REQUIRES: shell
// Check reading from named pipes. We cat the input here instead of redirecting
// it to ensure that /dev/fd/0 is a named pipe, not just a redirected file.
diff --git a/llvm/utils/lit/lit/builtin_commands/cat.py
b/llvm/utils/lit/lit/builtin_commands/cat.py
index ddab555662045..2797e0cbb4154 100644
--- a/llvm/utils/lit/lit/builtin_commands/cat.py
+++ b/llvm/utils/lit/lit/builtin_commands/cat.py
@@ -49,6 +49,9 @@ def main(argv):
import os, msvcrt
msvcrt.setmode(sys.stdout.fileno(), os.O_BINARY)
+if len(filenames) == 0:
+sys.stdout.write(sys.stdin.read())
+sys.exit(0)
for filename in filenames:
try:
contents = None
diff --git a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
index 4014b0fca1f24..c5b5d247c2f95 100644
--- a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
+++ b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
@@ -70,3 +70,7 @@
#
NP-CAT-OUTPUT-NEXT:M-HM-IM-JM-KM-LM-MM-NM-OM-PM-QM-RM-SM-TM-UM-VM-WM-XM-YM-ZM-[
#
NP-CAT-OUTPUT-NEXT:M-\M-]M-^M-_M-`M-aM-bM-cM-dM-eM-fM-gM-hM-iM-jM-kM-lM-mM-nM-o
# NP-CAT-OUTPUT-NEXT:M-pM-qM-rM-sM-tM-uM-vM-wM-xM-yM-zM-{M-|M-}M-~M-^?
+
+## Test that cat will pipe stdin to stdout if no other files are specified.
+# RUN: echo test | cat | FileCheck --check-prefix=CAT-STDIN %s
+# CAT-STDIN: test
>From 572975066e843b76e51020bcf6abc7822d3dfb75 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 23:14:52 +
Subject: [PATCH 2/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
[skip ci]
---
clang/test/ClangScanDeps/pr61006.cppm | 3 ++-
clang/test/ClangScanDeps/resource_directory.c | 9 -
clang/test/Driver/env.c | 5 +++--
clang/test/Driver/program-path-priority.c | 16 +++
clang/test/Modules/relative-resource-dir.m| 6 +++---
llvm/docs/CommandGuide/lit.rst| 1 +
llvm/test/tools/llvm-cgdata/empty.test| 1 +
llvm/utils/lit/lit/TestRunner.py | 20 +++
.../Inputs/shtest-readfile/absolute-paths.txt | 6 ++
.../lit/tests/Inputs/shtest-readfile/lit.cfg | 8
.../Inputs/shtest-readfile/relative-paths.txt | 7 +++
.../Inputs/shtest-readfile/two-same-line.txt | 8
llvm/utils/lit/tests/shtest-readfile.py | 17
13 files changed, 88 insertions(+), 19 deletions(-)
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/absolute-paths.txt
create mode 100644 llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/relative-paths.txt
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/two-same-line.txt
create mode 100644 llvm/utils/lit/tests/shtest-readfile.py
diff --git a/clang/test/ClangScanDeps/pr61006.cppm
b/clang/test/ClangScanDeps/pr61006.cppm
index f75edd38c81ba..f10bc1e673987 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -6,7 +6,8 @@
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
-// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \
+// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
+// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
// RUN: ln -s %clang++ %t/clang++ && \
// RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g"
%t/P1689.json.in > %t/P1689.json && \
// RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 |
FileCheck %t/a.cpp -DPREFIX=%/t && \
diff --git a/clang/test/ClangScanDeps/resource_directory.c
b/clang/test/ClangScanDeps/resource_directory.c
index 55d5d90bbcdea..6183e8aefacfa 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -12,14 +12,14 @@
//
[llvm-branch-commits] [Clang] Make rewrite-includes-bom.c work with internal shell (PR #158463)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158463 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Clang] Make rewrite-includes-bom.c work with internal shell (PR #158463)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158463 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/158447
>From 5bd8d4f925f3b5f82d85ef693861b6b1067d9f38 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 22:54:58 +
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
---
clang/test/Misc/dev-fd-fs.c| 1 -
llvm/utils/lit/lit/builtin_commands/cat.py | 3 +++
llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt | 4
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index ea94d950b0716..b989ab8a439cf 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -1,6 +1,5 @@
// Check that we can operate on files from /dev/fd.
// REQUIRES: dev-fd-fs
-// REQUIRES: shell
// Check reading from named pipes. We cat the input here instead of redirecting
// it to ensure that /dev/fd/0 is a named pipe, not just a redirected file.
diff --git a/llvm/utils/lit/lit/builtin_commands/cat.py
b/llvm/utils/lit/lit/builtin_commands/cat.py
index ddab555662045..2797e0cbb4154 100644
--- a/llvm/utils/lit/lit/builtin_commands/cat.py
+++ b/llvm/utils/lit/lit/builtin_commands/cat.py
@@ -49,6 +49,9 @@ def main(argv):
import os, msvcrt
msvcrt.setmode(sys.stdout.fileno(), os.O_BINARY)
+if len(filenames) == 0:
+sys.stdout.write(sys.stdin.read())
+sys.exit(0)
for filename in filenames:
try:
contents = None
diff --git a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
index 4014b0fca1f24..c5b5d247c2f95 100644
--- a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
+++ b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
@@ -70,3 +70,7 @@
#
NP-CAT-OUTPUT-NEXT:M-HM-IM-JM-KM-LM-MM-NM-OM-PM-QM-RM-SM-TM-UM-VM-WM-XM-YM-ZM-[
#
NP-CAT-OUTPUT-NEXT:M-\M-]M-^M-_M-`M-aM-bM-cM-dM-eM-fM-gM-hM-iM-jM-kM-lM-mM-nM-o
# NP-CAT-OUTPUT-NEXT:M-pM-qM-rM-sM-tM-uM-vM-wM-xM-yM-zM-{M-|M-}M-~M-^?
+
+## Test that cat will pipe stdin to stdout if no other files are specified.
+# RUN: echo test | cat | FileCheck --check-prefix=CAT-STDIN %s
+# CAT-STDIN: test
>From 572975066e843b76e51020bcf6abc7822d3dfb75 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sat, 13 Sep 2025 23:14:52 +
Subject: [PATCH 2/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6
[skip ci]
---
clang/test/ClangScanDeps/pr61006.cppm | 3 ++-
clang/test/ClangScanDeps/resource_directory.c | 9 -
clang/test/Driver/env.c | 5 +++--
clang/test/Driver/program-path-priority.c | 16 +++
clang/test/Modules/relative-resource-dir.m| 6 +++---
llvm/docs/CommandGuide/lit.rst| 1 +
llvm/test/tools/llvm-cgdata/empty.test| 1 +
llvm/utils/lit/lit/TestRunner.py | 20 +++
.../Inputs/shtest-readfile/absolute-paths.txt | 6 ++
.../lit/tests/Inputs/shtest-readfile/lit.cfg | 8
.../Inputs/shtest-readfile/relative-paths.txt | 7 +++
.../Inputs/shtest-readfile/two-same-line.txt | 8
llvm/utils/lit/tests/shtest-readfile.py | 17
13 files changed, 88 insertions(+), 19 deletions(-)
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/absolute-paths.txt
create mode 100644 llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/relative-paths.txt
create mode 100644
llvm/utils/lit/tests/Inputs/shtest-readfile/two-same-line.txt
create mode 100644 llvm/utils/lit/tests/shtest-readfile.py
diff --git a/clang/test/ClangScanDeps/pr61006.cppm
b/clang/test/ClangScanDeps/pr61006.cppm
index f75edd38c81ba..f10bc1e673987 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -6,7 +6,8 @@
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
-// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \
+// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
+// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
// RUN: ln -s %clang++ %t/clang++ && \
// RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g"
%t/P1689.json.in > %t/P1689.json && \
// RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 |
FileCheck %t/a.cpp -DPREFIX=%/t && \
diff --git a/clang/test/ClangScanDeps/resource_directory.c
b/clang/test/ClangScanDeps/resource_directory.c
index 55d5d90bbcdea..6183e8aefacfa 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -12,14 +12,14 @@
//
[llvm-branch-commits] [lit] Add support for deleting symlinks to directories without -r (PR #158464)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158464 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Clang] Enable lit internal shell by default (PR #158465)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158465 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Clang] Enable lit internal shell by default (PR #158465)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158465 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lit] Add support for deleting symlinks to directories without -r (PR #158464)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158464 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Clang] Rewrite tests using subshells to set env variables (PR #158446)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/158446 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Disable canonicalization in immutable collections (PR #159850)
llvmbot wrote:
@llvm/pr-subscribers-clang-analysis
Author: Utkarsh Saxena (usx95)
Changes
Disable canonicalization in immutable collections for lifetime analysis.
Modified the `LifetimeFactory` struct in `LifetimeSafety.cpp` to explicitly
initialize the immutable collection factories with `canonicalize=false`. This
prevents the factories from canonicalizing their data structures, which can
improve performance by avoiding unnecessary comparisons and digest computations.
---
Full diff: https://github.com/llvm/llvm-project/pull/159850.diff
1 Files Affected:
- (modified) clang/lib/Analysis/LifetimeSafety.cpp (+6-3)
``diff
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 0dd5716d93fb6..43cab406a9dc3 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -966,9 +966,12 @@ using ExpiredLoanMap = llvm::ImmutableMap;
/// An object to hold the factories for immutable collections, ensuring
/// that all created states share the same underlying memory management.
struct LifetimeFactory {
- OriginLoanMap::Factory OriginMapFactory;
- LoanSet::Factory LoanSetFactory;
- ExpiredLoanMap::Factory ExpiredLoanMapFactory;
+ // Avoid canonicalising
+ OriginLoanMap::Factory OriginMapFactory =
+ OriginLoanMap::Factory(/*canonicalize=*/false);
+ LoanSet::Factory LoanSetFactory = LoanSet::Factory(/*canonicalize=*/false);
+ ExpiredLoanMap::Factory ExpiredLoanMapFactory =
+ ExpiredLoanMap::Factory(/*canonicalize=*/false);
};
/// Represents the dataflow lattice for loan propagation.
``
https://github.com/llvm/llvm-project/pull/159850
___
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[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Disable canonicalization in immutable collections (PR #159850)
https://github.com/usx95 ready_for_review https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] db1b1b2 - Revert "[PowerPC] clean unused PPC target feature FeatureBPERMD (#159782)"
Author: Sergei Barannikov
Date: 2025-09-19T22:31:34+03:00
New Revision: db1b1b28278693272ec6222e2096b755d15fbf9b
URL:
https://github.com/llvm/llvm-project/commit/db1b1b28278693272ec6222e2096b755d15fbf9b
DIFF:
https://github.com/llvm/llvm-project/commit/db1b1b28278693272ec6222e2096b755d15fbf9b.diff
LOG: Revert "[PowerPC] clean unused PPC target feature FeatureBPERMD (#159782)"
This reverts commit 2e34188513e296f0c3d84b5a808924cafc6fd5a4.
Added:
Modified:
llvm/lib/Target/PowerPC/PPC.td
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 7a03927df4aff..d491e88b66ad8 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -129,6 +129,8 @@ def FeatureFPCVT : SubtargetFeature<"fpcvt",
"HasFPCVT", "true",
[FeatureFPU]>;
def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
"Enable the isel instruction">;
+def FeatureBPERMD: SubtargetFeature<"bpermd", "HasBPERMD", "true",
+"Enable the bpermd instruction">;
def FeatureExtDiv: SubtargetFeature<"extdiv", "HasExtDiv", "true",
"Enable extended divide instructions">;
def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
@@ -375,7 +377,7 @@ def NoNaNsFPMath
: Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def NaNsFPMath
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
-def HasBPERMD : Predicate<"Subtarget->getCPUDirective() >= PPC::DIR_PWR7">;
+def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
@@ -440,6 +442,7 @@ def ProcessorFeatures {
FeatureLDBRX,
Feature64BitSupport,
/* Feature64BitRegs, */
+ FeatureBPERMD,
FeatureExtDiv,
FeatureMFTB,
DeprecatedDST,
___
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[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)
@@ -0,0 +1,172 @@
+=
+Allocation Tokens
+=
+
+.. contents::
+ :local:
+
+Introduction
+
+
+Clang provides support for allocation tokens to enable allocator-level heap
+organization strategies. Clang assigns mode-dependent token IDs to allocation
+calls; the runtime behavior depends entirely on the implementation of a
+compatible memory allocator.
+
+Possible allocator strategies include:
+
+* **Security Hardening**: Placing allocations into separate, isolated heap
+ partitions. For example, separating pointer-containing types from raw data
+ can mitigate exploits that rely on overflowing a primitive buffer to corrupt
+ object metadata.
+
+* **Memory Layout Optimization**: Grouping related allocations to improve data
+ locality and cache utilization.
+
+* **Custom Allocation Policies**: Applying different management strategies to
+ different partitions.
+
+Token Assignment Mode
+=
+
+The default mode to calculate tokens is:
+
+* ``typehash``: This mode assigns a token ID based on the hash of the allocated
+ type's name.
+
+Other token ID assignment modes are supported, but they may be subject to
+change or removal. These may (experimentally) be selected with ``-mllvm
+-alloc-token-mode=``:
+
+* ``random``: This mode assigns a statically-determined random token ID to each
+ allocation site.
+
+* ``increment``: This mode assigns a simple, incrementally increasing token ID
+ to each allocation site.
+
+Allocation Token Instrumentation
+
+
+To enable instrumentation of allocation functions, code can be compiled with
+the ``-fsanitize=alloc-token`` flag:
+
+.. code-block:: console
+
+% clang++ -fsanitize=alloc-token example.cc
+
+The instrumentation transforms allocation calls to include a token ID. For
+example:
+
+.. code-block:: c
+
+// Original:
+ptr = malloc(size);
+
+// Instrumented:
+ptr = __alloc_token_malloc(size, token_id);
+
+In addition, it is typically recommended to configure the following:
+
+* ``-falloc-token-max=``
+Configures the maximum number of tokens. No max by default (tokens bounded
+by ``SIZE_MAX``).
+
+.. code-block:: console
+
+% clang++ -fsanitize=alloc-token -falloc-token-max=512 example.cc
+
+Runtime Interface
+-
+
+A compatible runtime must be provided that implements the token-enabled
+allocation functions. The instrumentation generates calls to functions that
+take a final ``size_t token_id`` argument.
+
+.. code-block:: c
+
+// C standard library functions
+void *__alloc_token_malloc(size_t size, size_t token_id);
+void *__alloc_token_calloc(size_t count, size_t size, size_t token_id);
+void *__alloc_token_realloc(void *ptr, size_t size, size_t token_id);
+// ...
+
+// C++ operators (mangled names)
+// operator new(size_t, size_t)
+void *__alloc_token_Znwm(size_t size, size_t token_id);
+// operator new[](size_t, size_t)
+void *__alloc_token_Znam(size_t size, size_t token_id);
+// ... other variants like nothrow, etc., are also instrumented.
+
+Fast ABI
+
+
+An alternative ABI can be enabled with ``-fsanitize-alloc-token-fast-abi``,
+which encodes the token ID hint in the allocation function name.
+
+.. code-block:: c
+
+void *__alloc_token_0_malloc(size_t size);
+void *__alloc_token_1_malloc(size_t size);
+void *__alloc_token_2_malloc(size_t size);
+...
+void *__alloc_token_0_Znwm(size_t size);
+void *__alloc_token_1_Znwm(size_t size);
+void *__alloc_token_2_Znwm(size_t size);
+...
+
+This ABI provides a more efficient alternative where
+``-falloc-token-max`` is small.
+
+Disabling Instrumentation
+-
+
+To exclude specific functions from instrumentation, you can use the
+``no_sanitize("alloc-token")`` attribute:
+
+.. code-block:: c
+
+__attribute__((no_sanitize("alloc-token")))
+void* custom_allocator(size_t size) {
+return malloc(size); // Uses original malloc
+}
+
+Note: Independent of any given allocator support, the instrumentation aims to
+remain performance neutral. As such, ``no_sanitize("alloc-token")``
+functions may be inlined into instrumented functions and vice-versa. If
+correctness is affected, such functions should explicitly be marked
+``noinline``.
+
+The ``__attribute__((disable_sanitizer_instrumentation))`` is also supported to
+disable this and other sanitizer instrumentations.
+
+Suppressions File (Ignorelist)
+--
+
+AllocToken respects the ``src`` and ``fun`` entity types in the
+:doc:`SanitizerSpecialCaseList`, which can be used to omit specified source
+files or functions from instrumentation.
+
+.. code-block:: bash
melver wrote:
Adding the header:
```
.. code-block:: bash
+[alloc-token]
# Exclude specific source files
src:third_party/allocator.c
# Exclude function name patterns
```
[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (PR #146076)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From b67b9c58a1612903f409cfdcec80e8565e4d5dc2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by
default
Also removes the command line option to control this feature.
There seem to be mainly two kinds of test changes:
- Some operands of addition instructions are swapped; that is to be expected
since PTRADD is not commutative.
- Improvements in code generation, probably because the legacy lowering enabled
some transformations that were sometimes harmful.
For SWDEV-516125.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 +-
.../identical-subrange-spill-infloop.ll | 352 +++---
.../AMDGPU/infer-addrspace-flat-atomic.ll | 14 +-
llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll | 8 +-
.../AMDGPU/lower-module-lds-via-hybrid.ll | 4 +-
.../AMDGPU/lower-module-lds-via-table.ll | 16 +-
.../match-perm-extract-vector-elt-bug.ll | 22 +-
llvm/test/CodeGen/AMDGPU/memmove-var-size.ll | 16 +-
.../AMDGPU/preload-implicit-kernargs.ll | 6 +-
.../AMDGPU/promote-constOffset-to-imm.ll | 8 +-
llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll | 7 +-
.../AMDGPU/ptradd-sdag-optimizations.ll | 94 ++---
.../AMDGPU/ptradd-sdag-undef-poison.ll| 6 +-
llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll | 27 +-
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 29 +-
15 files changed, 310 insertions(+), 309 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 78d608556f056..ac3d322ad65c3 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -64,14 +64,6 @@ static cl::opt UseDivergentRegisterIndexing(
cl::desc("Use indirect register addressing for divergent indexes"),
cl::init(false));
-// TODO: This option should be removed once we switch to always using PTRADD in
-// the SelectionDAG.
-static cl::opt UseSelectionDAGPTRADD(
-"amdgpu-use-sdag-ptradd", cl::Hidden,
-cl::desc("Generate ISD::PTRADD nodes for 64-bit pointer arithmetic in the "
- "SelectionDAG ISel"),
-cl::init(false));
-
static bool denormalModeIsFlushAllF32(const MachineFunction &MF) {
const SIMachineFunctionInfo *Info = MF.getInfo();
return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign();
@@ -11473,7 +11465,7 @@ static bool isNoUnsignedWrap(SDValue Addr) {
bool SITargetLowering::shouldPreservePtrArith(const Function &F,
EVT PtrVT) const {
- return UseSelectionDAGPTRADD && PtrVT == MVT::i64;
+ return PtrVT == MVT::i64;
}
bool SITargetLowering::canTransformPtrArithOutOfBounds(const Function &F,
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 2c03113e8af47..805cdd37d6e70 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -6,96 +6,150 @@ define void @main(i1 %arg) #0 {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT:buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; CHECK-NEXT:buffer_store_dword v6, off, s[0:3], s32 offset:4 ; 4-byte
Folded Spill
+; CHECK-NEXT:buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT:buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte
Folded Spill
; CHECK-NEXT:s_mov_b64 exec, s[4:5]
-; CHECK-NEXT:v_writelane_b32 v5, s30, 0
-; CHECK-NEXT:v_writelane_b32 v5, s31, 1
-; CHECK-NEXT:v_writelane_b32 v5, s36, 2
-; CHECK-NEXT:v_writelane_b32 v5, s37, 3
-; CHECK-NEXT:v_writelane_b32 v5, s38, 4
-; CHECK-NEXT:v_writelane_b32 v5, s39, 5
-; CHECK-NEXT:v_writelane_b32 v5, s48, 6
-; CHECK-NEXT:v_writelane_b32 v5, s49, 7
-; CHECK-NEXT:v_writelane_b32 v5, s50, 8
-; CHECK-NEXT:v_writelane_b32 v5, s51, 9
-; CHECK-NEXT:v_writelane_b32 v5, s52, 10
-; CHECK-NEXT:v_writelane_b32 v5, s53, 11
-; CHECK-NEXT:v_writelane_b32 v5, s54, 12
-; CHECK-NEXT:v_writelane_b32 v5, s55, 13
-; CHECK-NEXT:s_getpc_b64 s[24:25]
-; CHECK-NEXT:v_writelane_b32 v5, s64, 14
-; CHECK-NEXT:s_movk_i32 s4, 0xf0
-; CHECK-NEXT:s_mov_b32 s5, s24
-; CHECK-NEXT:v_writelane_b32 v5, s65, 15
-; CHECK-NEXT:s_load_dwordx16 s[8:23], s[4:5], 0x0
-; CHECK-NEXT:s_mov_b64 s[4:5], 0
-; CHECK-NEXT:v_writelane_b32 v5, s66, 16
-; CHECK-NEXT:s_load_dwordx4 s[4:7], s[4:5], 0x0
-; CHECK-NEXT:v_writelane_b32 v5, s67, 17
-; CHECK-NEXT:s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:s_movk_i32 s6, 0x130
-; CHECK-NEXT:s_mov_b32 s7, s24
-; CHECK-NEXT:v_writelane_b32 v5
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR (PR #146075)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 395fdf948ee1864d6fc427e62db5433a5ef3eba0 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we can't fold a PTRADD's offset into its users, lowering them to
disjoint ORs is preferable: Often, a 32-bit OR instruction suffices
where we'd otherwise use a pair of 32-bit additions with carry.
This needs to be a DAGCombine (and not a selection rule) because its
main purpose is to enable subsequent DAGCombines for bitwise operations.
We don't want to just turn PTRADDs into disjoint ORs whenever that's
sound because this transform loses the information that the operation
implements pointer arithmetic, which we will soon need to fold offsets
into FLAT instructions. Currently, disjoint ORs can still be used for
offset folding, so that part of the logic can't be tested.
The PR contains a hacky workaround for a situation where an AssertAlign
operand of a PTRADD is not DAGCombined before the PTRADD, causing the
PTRADD to be turned into a disjoint OR although reassociating it with
the operand of the AssertAlign would be better. This wouldn't be a
problem if the DAGCombiner ensured that a node is only processed after
all its operands have been processed.
For SWDEV-516125.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 35
.../AMDGPU/ptradd-sdag-optimizations.ll | 56 ++-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 78d608556f056..ffaaef65569ae 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16145,6 +16145,41 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode
*N,
return Folded;
}
+ // Transform (ptradd a, b) -> (or disjoint a, b) if it is equivalent and if
+ // that transformation can't block an offset folding at any use of the
ptradd.
+ // This should be done late, after legalization, so that it doesn't block
+ // other ptradd combines that could enable more offset folding.
+ bool HasIntermediateAssertAlign =
+ N0->getOpcode() == ISD::AssertAlign && N0->getOperand(0)->isAnyAdd();
+ // This is a hack to work around an ordering problem for DAGs like this:
+ // (ptradd (AssertAlign (ptradd p, c1), k), c2)
+ // If the outer ptradd is handled first by the DAGCombiner, it can be
+ // transformed into a disjoint or. Then, when the generic AssertAlign combine
+ // pushes the AssertAlign through the inner ptradd, it's too late for the
+ // ptradd reassociation to trigger.
+ if (!DCI.isBeforeLegalizeOps() && !HasIntermediateAssertAlign &&
+ DAG.haveNoCommonBitsSet(N0, N1)) {
+bool TransformCanBreakAddrMode = any_of(N->users(), [&](SDNode *User) {
+ if (auto *LoadStore = dyn_cast(User);
+ LoadStore && LoadStore->getBasePtr().getNode() == N) {
+unsigned AS = LoadStore->getAddressSpace();
+// Currently, we only really need ptradds to fold offsets into flat
+// memory instructions.
+if (AS != AMDGPUAS::FLAT_ADDRESS)
+ return false;
+TargetLoweringBase::AddrMode AM;
+AM.HasBaseReg = true;
+EVT VT = LoadStore->getMemoryVT();
+Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
+return isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS);
+ }
+ return false;
+});
+
+if (!TransformCanBreakAddrMode)
+ return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
+ }
+
if (N1.getOpcode() != ISD::ADD || !N1.hasOneUse())
return SDValue();
diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index 199c1f61d2522..7d7fe141e5440 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -100,7 +100,7 @@ define void @baseptr_null(i64 %offset, i8 %v) {
; Taken from implicit-kernarg-backend-usage.ll, tests the PTRADD handling in
the
; assertalign DAG combine.
-define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) #0 {
+define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) {
; GFX942-LABEL: llvm_amdgcn_queue_ptr:
; GFX942: ; %bb.0:
; GFX942-NEXT:v_mov_b32_e32 v0, 0
@@ -415,6 +415,60 @@ entry:
ret void
}
+; Check that ptradds can be lowered to disjoint ORs.
+define ptr @gep_disjoint_or(ptr %base) {
+; GFX942-LABEL: gep_disjoint_or:
+; GFX942: ; %bb.0:
+; GFX942-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:v_and_or_b32 v0, v0, -16, 4
+; GFX942-NEXT:s_setpc_b64 s[30:31]
+ %p = call ptr @llvm.ptrmask(ptr %base, i64 s0xf0)
+ %gep = getelementptr nuw inbounds i8, ptr %p, i64 4
+ ret ptr %gep
+}
+
+; Check that AssertAlign no
[llvm-branch-commits] [llvm] [DA] Add test where WeakCrossingSIV misses dependency due to overflow (NFC) (PR #158281)
https://github.com/kasuga-fj updated
https://github.com/llvm/llvm-project/pull/158281
>From bdde305c338bffd9958f17e3a11a08f2bb30b5bf Mon Sep 17 00:00:00 2001
From: Ryotaro Kasuga
Date: Fri, 12 Sep 2025 11:06:39 +
Subject: [PATCH] [DA] Add test where WeakCrossingSIV misses dependency due to
overflow
---
.../DependenceAnalysis/WeakCrossingSIV.ll | 224 ++
1 file changed, 224 insertions(+)
diff --git a/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
b/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
index cd044032e34f1..58dded965de27 100644
--- a/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by
utils/update_analyze_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -disable-output "-passes=print" -aa-pipeline=basic-aa 2>&1
\
; RUN: | FileCheck %s
+; RUN: opt < %s -disable-output "-passes=print" -da-run-siv-routines-only
2>&1 \
+; RUN: | FileCheck %s --check-prefix=CHECK-SIV-ONLY
; ModuleID = 'WeakCrossingSIV.bc'
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
@@ -26,6 +28,20 @@ define void @weakcrossing0(ptr %A, ptr %B, i64 %n) nounwind
uwtable ssp {
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32
%0, ptr %B.addr.02, align 4
; CHECK-NEXT:da analyze - none!
;
+; CHECK-SIV-ONLY-LABEL: 'weakcrossing0'
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %conv, ptr %arrayidx, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - flow [0|<]!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+;
entry:
%cmp1 = icmp eq i64 %n, 0
br i1 %cmp1, label %for.end, label %for.body.preheader
@@ -79,6 +95,21 @@ define void @weakcrossing1(ptr %A, ptr %B, i64 %n) nounwind
uwtable ssp {
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32
%0, ptr %B.addr.02, align 4
; CHECK-NEXT:da analyze - none!
;
+; CHECK-SIV-ONLY-LABEL: 'weakcrossing1'
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %conv, ptr %arrayidx, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - flow [<>] splitable!
+; CHECK-SIV-ONLY-NEXT:da analyze - split level = 1, iteration = 0!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+;
entry:
%cmp1 = icmp eq i64 %n, 0
br i1 %cmp1, label %for.end, label %for.body.preheader
@@ -130,6 +161,20 @@ define void @weakcrossing2(ptr %A, ptr %B, i64 %n)
nounwind uwtable ssp {
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32
%0, ptr %B.addr.01, align 4
; CHECK-NEXT:da analyze - none!
;
+; CHECK-SIV-ONLY-LABEL: 'weakcrossing2'
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %conv, ptr %arrayidx, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
%0 = load i32, ptr %arrayidx1, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %0, ptr %B.addr.01, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst:
%0 = load i32
[llvm-branch-commits] [llvm] AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (PR #158272)
@@ -2926,6 +2929,20 @@ def HasLdsBarrierArriveAtomic : Predicate<"Subtarget->hasLdsBarrierArriveAtomic( def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">, AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>; +def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">, + AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>; + +//===--===// +// HwModes +//===--===// + +// gfx90a-gfx950. Has AGPRs, and also the align2 VGPR/AGPR requirement +def AVAlign2LoadStoreMode : HwMode<[HasMAIInsts, NeedsAlignedVGPRs]>; + +// gfx1250, has alignment requirement but no AGPRs. +def AlignedVGPRNoAGPRMode : HwMode<[NotHasMAIInsts, NeedsAlignedVGPRs]>; arsenm wrote: DefaultMode. That's mostly the reason for having separate AV and AV_LdSt cases https://github.com/llvm/llvm-project/pull/158272 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (PR #146076)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From fcaebb21fdbc19ada18e20902a4626ba9ace9f99 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by
default
Also removes the command line option to control this feature.
There seem to be mainly two kinds of test changes:
- Some operands of addition instructions are swapped; that is to be expected
since PTRADD is not commutative.
- Improvements in code generation, probably because the legacy lowering enabled
some transformations that were sometimes harmful.
For SWDEV-516125.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 +-
.../identical-subrange-spill-infloop.ll | 352 +++---
.../AMDGPU/infer-addrspace-flat-atomic.ll | 14 +-
llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll | 8 +-
.../AMDGPU/lower-module-lds-via-hybrid.ll | 4 +-
.../AMDGPU/lower-module-lds-via-table.ll | 16 +-
.../match-perm-extract-vector-elt-bug.ll | 22 +-
llvm/test/CodeGen/AMDGPU/memmove-var-size.ll | 16 +-
.../AMDGPU/preload-implicit-kernargs.ll | 6 +-
.../AMDGPU/promote-constOffset-to-imm.ll | 8 +-
llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll | 7 +-
.../AMDGPU/ptradd-sdag-optimizations.ll | 94 ++---
.../AMDGPU/ptradd-sdag-undef-poison.ll| 6 +-
llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll | 27 +-
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 29 +-
15 files changed, 310 insertions(+), 309 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 78d608556f056..ac3d322ad65c3 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -64,14 +64,6 @@ static cl::opt UseDivergentRegisterIndexing(
cl::desc("Use indirect register addressing for divergent indexes"),
cl::init(false));
-// TODO: This option should be removed once we switch to always using PTRADD in
-// the SelectionDAG.
-static cl::opt UseSelectionDAGPTRADD(
-"amdgpu-use-sdag-ptradd", cl::Hidden,
-cl::desc("Generate ISD::PTRADD nodes for 64-bit pointer arithmetic in the "
- "SelectionDAG ISel"),
-cl::init(false));
-
static bool denormalModeIsFlushAllF32(const MachineFunction &MF) {
const SIMachineFunctionInfo *Info = MF.getInfo();
return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign();
@@ -11473,7 +11465,7 @@ static bool isNoUnsignedWrap(SDValue Addr) {
bool SITargetLowering::shouldPreservePtrArith(const Function &F,
EVT PtrVT) const {
- return UseSelectionDAGPTRADD && PtrVT == MVT::i64;
+ return PtrVT == MVT::i64;
}
bool SITargetLowering::canTransformPtrArithOutOfBounds(const Function &F,
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 2c03113e8af47..805cdd37d6e70 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -6,96 +6,150 @@ define void @main(i1 %arg) #0 {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT:buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; CHECK-NEXT:buffer_store_dword v6, off, s[0:3], s32 offset:4 ; 4-byte
Folded Spill
+; CHECK-NEXT:buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT:buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte
Folded Spill
; CHECK-NEXT:s_mov_b64 exec, s[4:5]
-; CHECK-NEXT:v_writelane_b32 v5, s30, 0
-; CHECK-NEXT:v_writelane_b32 v5, s31, 1
-; CHECK-NEXT:v_writelane_b32 v5, s36, 2
-; CHECK-NEXT:v_writelane_b32 v5, s37, 3
-; CHECK-NEXT:v_writelane_b32 v5, s38, 4
-; CHECK-NEXT:v_writelane_b32 v5, s39, 5
-; CHECK-NEXT:v_writelane_b32 v5, s48, 6
-; CHECK-NEXT:v_writelane_b32 v5, s49, 7
-; CHECK-NEXT:v_writelane_b32 v5, s50, 8
-; CHECK-NEXT:v_writelane_b32 v5, s51, 9
-; CHECK-NEXT:v_writelane_b32 v5, s52, 10
-; CHECK-NEXT:v_writelane_b32 v5, s53, 11
-; CHECK-NEXT:v_writelane_b32 v5, s54, 12
-; CHECK-NEXT:v_writelane_b32 v5, s55, 13
-; CHECK-NEXT:s_getpc_b64 s[24:25]
-; CHECK-NEXT:v_writelane_b32 v5, s64, 14
-; CHECK-NEXT:s_movk_i32 s4, 0xf0
-; CHECK-NEXT:s_mov_b32 s5, s24
-; CHECK-NEXT:v_writelane_b32 v5, s65, 15
-; CHECK-NEXT:s_load_dwordx16 s[8:23], s[4:5], 0x0
-; CHECK-NEXT:s_mov_b64 s[4:5], 0
-; CHECK-NEXT:v_writelane_b32 v5, s66, 16
-; CHECK-NEXT:s_load_dwordx4 s[4:7], s[4:5], 0x0
-; CHECK-NEXT:v_writelane_b32 v5, s67, 17
-; CHECK-NEXT:s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:s_movk_i32 s6, 0x130
-; CHECK-NEXT:s_mov_b32 s7, s24
-; CHECK-NEXT:v_writelane_b32 v5
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR (PR #146075)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 157f6a257a5771cff71fd5ea4be46251bd26d97f Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we can't fold a PTRADD's offset into its users, lowering them to
disjoint ORs is preferable: Often, a 32-bit OR instruction suffices
where we'd otherwise use a pair of 32-bit additions with carry.
This needs to be a DAGCombine (and not a selection rule) because its
main purpose is to enable subsequent DAGCombines for bitwise operations.
We don't want to just turn PTRADDs into disjoint ORs whenever that's
sound because this transform loses the information that the operation
implements pointer arithmetic, which we will soon need to fold offsets
into FLAT instructions. Currently, disjoint ORs can still be used for
offset folding, so that part of the logic can't be tested.
The PR contains a hacky workaround for a situation where an AssertAlign
operand of a PTRADD is not DAGCombined before the PTRADD, causing the
PTRADD to be turned into a disjoint OR although reassociating it with
the operand of the AssertAlign would be better. This wouldn't be a
problem if the DAGCombiner ensured that a node is only processed after
all its operands have been processed.
For SWDEV-516125.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 35
.../AMDGPU/ptradd-sdag-optimizations.ll | 56 ++-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 78d608556f056..ffaaef65569ae 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16145,6 +16145,41 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode
*N,
return Folded;
}
+ // Transform (ptradd a, b) -> (or disjoint a, b) if it is equivalent and if
+ // that transformation can't block an offset folding at any use of the
ptradd.
+ // This should be done late, after legalization, so that it doesn't block
+ // other ptradd combines that could enable more offset folding.
+ bool HasIntermediateAssertAlign =
+ N0->getOpcode() == ISD::AssertAlign && N0->getOperand(0)->isAnyAdd();
+ // This is a hack to work around an ordering problem for DAGs like this:
+ // (ptradd (AssertAlign (ptradd p, c1), k), c2)
+ // If the outer ptradd is handled first by the DAGCombiner, it can be
+ // transformed into a disjoint or. Then, when the generic AssertAlign combine
+ // pushes the AssertAlign through the inner ptradd, it's too late for the
+ // ptradd reassociation to trigger.
+ if (!DCI.isBeforeLegalizeOps() && !HasIntermediateAssertAlign &&
+ DAG.haveNoCommonBitsSet(N0, N1)) {
+bool TransformCanBreakAddrMode = any_of(N->users(), [&](SDNode *User) {
+ if (auto *LoadStore = dyn_cast(User);
+ LoadStore && LoadStore->getBasePtr().getNode() == N) {
+unsigned AS = LoadStore->getAddressSpace();
+// Currently, we only really need ptradds to fold offsets into flat
+// memory instructions.
+if (AS != AMDGPUAS::FLAT_ADDRESS)
+ return false;
+TargetLoweringBase::AddrMode AM;
+AM.HasBaseReg = true;
+EVT VT = LoadStore->getMemoryVT();
+Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
+return isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS);
+ }
+ return false;
+});
+
+if (!TransformCanBreakAddrMode)
+ return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
+ }
+
if (N1.getOpcode() != ISD::ADD || !N1.hasOneUse())
return SDValue();
diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index 199c1f61d2522..7d7fe141e5440 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -100,7 +100,7 @@ define void @baseptr_null(i64 %offset, i8 %v) {
; Taken from implicit-kernarg-backend-usage.ll, tests the PTRADD handling in
the
; assertalign DAG combine.
-define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) #0 {
+define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) {
; GFX942-LABEL: llvm_amdgcn_queue_ptr:
; GFX942: ; %bb.0:
; GFX942-NEXT:v_mov_b32_e32 v0, 0
@@ -415,6 +415,60 @@ entry:
ret void
}
+; Check that ptradds can be lowered to disjoint ORs.
+define ptr @gep_disjoint_or(ptr %base) {
+; GFX942-LABEL: gep_disjoint_or:
+; GFX942: ; %bb.0:
+; GFX942-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:v_and_or_b32 v0, v0, -16, 4
+; GFX942-NEXT:s_setpc_b64 s[30:31]
+ %p = call ptr @llvm.ptrmask(ptr %base, i64 s0xf0)
+ %gep = getelementptr nuw inbounds i8, ptr %p, i64 4
+ ret ptr %gep
+}
+
+; Check that AssertAlign no
[llvm-branch-commits] [llvm] AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (PR #158272)
@@ -2926,6 +2929,20 @@ def HasLdsBarrierArriveAtomic : Predicate<"Subtarget->hasLdsBarrierArriveAtomic( def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">, AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>; +def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">, + AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>; + +//===--===// +// HwModes +//===--===// + +// gfx90a-gfx950. Has AGPRs, and also the align2 VGPR/AGPR requirement +def AVAlign2LoadStoreMode : HwMode<[HasMAIInsts, NeedsAlignedVGPRs]>; + +// gfx1250, has alignment requirement but no AGPRs. +def AlignedVGPRNoAGPRMode : HwMode<[NotHasMAIInsts, NeedsAlignedVGPRs]>; cdevadas wrote: What will be the Mode for gfx908 that has AGPRs but no strict VGPR align requirement? https://github.com/llvm/llvm-project/pull/158272 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] X86: Switch to RegClassByHwMode (PR #158274)
https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/158274 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LoongArch] Override shouldScalarizeBinop to enable `extract(binop)->binop(extract)` combination (PR #159726)
https://github.com/zhaoqi5 created
https://github.com/llvm/llvm-project/pull/159726
None
>From 058b3f901ddb9107d56d6fbb48d7f7b08d4f5562 Mon Sep 17 00:00:00 2001
From: Qi Zhao
Date: Fri, 19 Sep 2025 16:56:53 +0800
Subject: [PATCH] [LoongArch] Override shouldScalarizeBinop hook to enable
`extract(binop)->binop(extract)` combination
---
.../LoongArch/LoongArchISelLowering.cpp | 19 ++
.../Target/LoongArch/LoongArchISelLowering.h | 2 +
.../CodeGen/LoongArch/lasx/extract-binop.ll | 59 ---
.../CodeGen/LoongArch/lsx/extract-binop.ll| 59 ---
4 files changed, 67 insertions(+), 72 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index add6bec686c71..a471001086b68 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -9105,3 +9105,22 @@ bool
LoongArchTargetLowering::SimplifyDemandedBitsForTargetNode(
return TargetLowering::SimplifyDemandedBitsForTargetNode(
Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
}
+
+bool LoongArchTargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
+ unsigned Opc = VecOp.getOpcode();
+
+ // Assume target opcodes can't be scalarized.
+ // TODO - do we have any exceptions?
+ if (Opc >= ISD::BUILTIN_OP_END || !isBinOp(Opc))
+return false;
+
+ // If the vector op is not supported, try to convert to scalar.
+ EVT VecVT = VecOp.getValueType();
+ if (!isOperationLegalOrCustomOrPromote(Opc, VecVT))
+return true;
+
+ // If the vector op is supported, but the scalar op is not, the transform may
+ // not be worthwhile.
+ EVT ScalarVT = VecVT.getScalarType();
+ return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
+}
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 9d14934a9d363..8da492570146e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -332,6 +332,8 @@ class LoongArchTargetLowering : public TargetLowering {
TargetLoweringOpt &TLO,
unsigned Depth) const override;
+ bool shouldScalarizeBinop(SDValue VecOp) const override;
+
private:
/// Target-specific function used to lower LoongArch calling conventions.
typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
diff --git a/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
b/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
index 1517e11aa7d7a..4986b12199c31 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
@@ -31,12 +31,18 @@ entry:
}
define i32 @extractelt_add_v8i32(ptr %p) {
-; CHECK-LABEL: extractelt_add_v8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xvld $xr0, $a0, 0
-; CHECK-NEXT:xvaddi.wu $xr0, $xr0, 13
-; CHECK-NEXT:xvpickve2gr.w $a0, $xr0, 2
-; CHECK-NEXT:ret
+; LA32-LABEL: extractelt_add_v8i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT:ld.w $a0, $a0, 8
+; LA32-NEXT:addi.w $a0, $a0, 13
+; LA32-NEXT:ret
+;
+; LA64-LABEL: extractelt_add_v8i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT:xvld $xr0, $a0, 0
+; LA64-NEXT:xvaddi.wu $xr0, $xr0, 13
+; LA64-NEXT:xvpickve2gr.w $a0, $xr0, 2
+; LA64-NEXT:ret
entry:
%x = load <8 x i32>, ptr %p
%add = add <8 x i32> %x,
@@ -55,9 +61,8 @@ define i64 @extractelt_add_v4i64(ptr %p) {
;
; LA64-LABEL: extractelt_add_v4i64:
; LA64: # %bb.0: # %entry
-; LA64-NEXT:xvld $xr0, $a0, 0
-; LA64-NEXT:xvaddi.du $xr0, $xr0, 12
-; LA64-NEXT:xvpickve2gr.d $a0, $xr0, 1
+; LA64-NEXT:ld.d $a0, $a0, 8
+; LA64-NEXT:addi.d $a0, $a0, 12
; LA64-NEXT:ret
entry:
%x = load <4 x i64>, ptr %p
@@ -69,12 +74,9 @@ entry:
define float @extractelt_fadd_v8f32(ptr %p) {
; CHECK-LABEL: extractelt_fadd_v8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xvld $xr0, $a0, 0
-; CHECK-NEXT:lu12i.w $a0, 267520
-; CHECK-NEXT:xvreplgr2vr.w $xr1, $a0
-; CHECK-NEXT:xvfadd.s $xr0, $xr0, $xr1
-; CHECK-NEXT:xvpickve.w $xr0, $xr0, 2
-; CHECK-NEXT:# kill: def $f0 killed $f0 killed $xr0
+; CHECK-NEXT:fld.s $fa0, $a0, 8
+; CHECK-NEXT:vldi $vr1, -1238
+; CHECK-NEXT:fadd.s $fa0, $fa0, $fa1
; CHECK-NEXT:ret
entry:
%x = load <8 x float>, ptr %p
@@ -84,27 +86,12 @@ entry:
}
define double @extractelt_fadd_v4f64(ptr %p) {
-; LA32-LABEL: extractelt_fadd_v4f64:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT:xvld $xr0, $a0, 0
-; LA32-NEXT:pcalau12i $a0, %pc_hi20(.LCPI5_0)
-; LA32-NEXT:xvld $xr1, $a0, %pc_lo12(.LCPI5_0)
-; LA32-NEXT:xvfadd.d $xr0, $xr0, $xr1
-; LA32-NEXT:xvpickve.d $xr0, $xr0, 1
-; LA32-NEXT:# kill: def $f0_64 killed $f0_64 killed $xr0
-; LA32-NEXT:ret
-;
-; LA64-LABEL: ex
[llvm-branch-commits] [llvm] ARM: Remove TRI argument from AddDReg (PR #158228)
@@ -929,15 +929,15 @@ ARMBaseInstrInfo::describeLoadedValue(const MachineInstr
&MI,
return TargetInstrInfo::describeLoadedValue(MI, Reg);
}
-const MachineInstrBuilder &
-ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
- unsigned SubIdx, unsigned State,
- const TargetRegisterInfo *TRI) const {
+const MachineInstrBuilder &ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB,
+ unsigned Reg,
+ unsigned SubIdx,
+ unsigned State) const {
if (!SubIdx)
return MIB.addReg(Reg, State);
if (Register::isPhysicalRegister(Reg))
-return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
+return MIB.addReg(getRegisterInfo().getSubReg(Reg, SubIdx), State);
arsenm wrote:
This is ARMBaseInstrInfo, which doesn't have the owning reference. That's in
the subclasses
https://github.com/llvm/llvm-project/pull/158228
___
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[llvm-branch-commits] [clang] [HLSL] Use static create methods to initialize resources in arrays (PR #157005)
@@ -243,16 +238,18 @@ static Value *initializeLocalResourceArray( Index = CGF.Builder.CreateAdd(Index, One); GEPIndices.back() = llvm::ConstantInt::get(IntTy, I); } -Address ThisAddress = +Address ReturnAddress = CGF.Builder.CreateGEP(TmpArrayAddr, GEPIndices, Ty, Align); -llvm::Value *ThisPtr = CGF.getAsNaturalPointerTo(ThisAddress, ElemType); CallArgList Args; -createResourceCtorArgs(CGF.CGM, CD, ThisPtr, Range, Index, ResourceName, - RBA, VkBinding, Args); -CGF.EmitCXXConstructorCall(CD, Ctor_Complete, false, false, ThisAddress, - Args, ValueSlot.mayOverlap(), ArraySubsExprLoc, - ValueSlot.isSanitizerChecked()); +CXXMethodDecl *CreateMethod = lookupResourceInitMethodAndSetupArgs( +CGF.CGM, ResourceDecl, Range, Index, ResourceName, RBA, VkBinding, +Args); + +if (!CreateMethod) + return std::nullopt; llvm-beanz wrote: Chatted with @hekota offline. Seems like this happens for manually written structs containing handles, and the outcome here is that they just don't get bindings generated. I think not supporting automatically binding handles for people writing their own types against internal compiler details is completely reasonable. https://github.com/llvm/llvm-project/pull/157005 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [DA] Add test where WeakCrossingSIV misses dependency due to overflow (NFC) (PR #158281)
https://github.com/kasuga-fj updated
https://github.com/llvm/llvm-project/pull/158281
>From bdde305c338bffd9958f17e3a11a08f2bb30b5bf Mon Sep 17 00:00:00 2001
From: Ryotaro Kasuga
Date: Fri, 12 Sep 2025 11:06:39 +
Subject: [PATCH] [DA] Add test where WeakCrossingSIV misses dependency due to
overflow
---
.../DependenceAnalysis/WeakCrossingSIV.ll | 224 ++
1 file changed, 224 insertions(+)
diff --git a/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
b/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
index cd044032e34f1..58dded965de27 100644
--- a/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by
utils/update_analyze_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -disable-output "-passes=print" -aa-pipeline=basic-aa 2>&1
\
; RUN: | FileCheck %s
+; RUN: opt < %s -disable-output "-passes=print" -da-run-siv-routines-only
2>&1 \
+; RUN: | FileCheck %s --check-prefix=CHECK-SIV-ONLY
; ModuleID = 'WeakCrossingSIV.bc'
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
@@ -26,6 +28,20 @@ define void @weakcrossing0(ptr %A, ptr %B, i64 %n) nounwind
uwtable ssp {
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32
%0, ptr %B.addr.02, align 4
; CHECK-NEXT:da analyze - none!
;
+; CHECK-SIV-ONLY-LABEL: 'weakcrossing0'
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %conv, ptr %arrayidx, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - flow [0|<]!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+;
entry:
%cmp1 = icmp eq i64 %n, 0
br i1 %cmp1, label %for.end, label %for.body.preheader
@@ -79,6 +95,21 @@ define void @weakcrossing1(ptr %A, ptr %B, i64 %n) nounwind
uwtable ssp {
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32
%0, ptr %B.addr.02, align 4
; CHECK-NEXT:da analyze - none!
;
+; CHECK-SIV-ONLY-LABEL: 'weakcrossing1'
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %conv, ptr %arrayidx, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - flow [<>] splitable!
+; CHECK-SIV-ONLY-NEXT:da analyze - split level = 1, iteration = 0!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
%0 = load i32, ptr %arrayidx2, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst:
store i32 %0, ptr %B.addr.02, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+;
entry:
%cmp1 = icmp eq i64 %n, 0
br i1 %cmp1, label %for.end, label %for.body.preheader
@@ -130,6 +161,20 @@ define void @weakcrossing2(ptr %A, ptr %B, i64 %n)
nounwind uwtable ssp {
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32
%0, ptr %B.addr.01, align 4
; CHECK-NEXT:da analyze - none!
;
+; CHECK-SIV-ONLY-LABEL: 'weakcrossing2'
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %conv, ptr %arrayidx, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
%0 = load i32, ptr %arrayidx1, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - none!
+; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst:
store i32 %0, ptr %B.addr.01, align 4
+; CHECK-SIV-ONLY-NEXT:da analyze - confused!
+; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst:
%0 = load i32
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (PR #146076)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 33152a969116d67be445347b59dba9e9a902b09f Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by
default
Also removes the command line option to control this feature.
There seem to be mainly two kinds of test changes:
- Some operands of addition instructions are swapped; that is to be expected
since PTRADD is not commutative.
- Improvements in code generation, probably because the legacy lowering enabled
some transformations that were sometimes harmful.
For SWDEV-516125.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 +-
.../identical-subrange-spill-infloop.ll | 352 +++---
.../AMDGPU/infer-addrspace-flat-atomic.ll | 14 +-
llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll | 8 +-
.../AMDGPU/lower-module-lds-via-hybrid.ll | 4 +-
.../AMDGPU/lower-module-lds-via-table.ll | 16 +-
.../match-perm-extract-vector-elt-bug.ll | 22 +-
llvm/test/CodeGen/AMDGPU/memmove-var-size.ll | 16 +-
.../AMDGPU/preload-implicit-kernargs.ll | 6 +-
.../AMDGPU/promote-constOffset-to-imm.ll | 8 +-
llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll | 7 +-
.../AMDGPU/ptradd-sdag-optimizations.ll | 94 ++---
.../AMDGPU/ptradd-sdag-undef-poison.ll| 6 +-
llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll | 27 +-
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 29 +-
15 files changed, 310 insertions(+), 309 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 78d608556f056..ac3d322ad65c3 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -64,14 +64,6 @@ static cl::opt UseDivergentRegisterIndexing(
cl::desc("Use indirect register addressing for divergent indexes"),
cl::init(false));
-// TODO: This option should be removed once we switch to always using PTRADD in
-// the SelectionDAG.
-static cl::opt UseSelectionDAGPTRADD(
-"amdgpu-use-sdag-ptradd", cl::Hidden,
-cl::desc("Generate ISD::PTRADD nodes for 64-bit pointer arithmetic in the "
- "SelectionDAG ISel"),
-cl::init(false));
-
static bool denormalModeIsFlushAllF32(const MachineFunction &MF) {
const SIMachineFunctionInfo *Info = MF.getInfo();
return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign();
@@ -11473,7 +11465,7 @@ static bool isNoUnsignedWrap(SDValue Addr) {
bool SITargetLowering::shouldPreservePtrArith(const Function &F,
EVT PtrVT) const {
- return UseSelectionDAGPTRADD && PtrVT == MVT::i64;
+ return PtrVT == MVT::i64;
}
bool SITargetLowering::canTransformPtrArithOutOfBounds(const Function &F,
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 2c03113e8af47..805cdd37d6e70 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -6,96 +6,150 @@ define void @main(i1 %arg) #0 {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT:buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; CHECK-NEXT:buffer_store_dword v6, off, s[0:3], s32 offset:4 ; 4-byte
Folded Spill
+; CHECK-NEXT:buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT:buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte
Folded Spill
; CHECK-NEXT:s_mov_b64 exec, s[4:5]
-; CHECK-NEXT:v_writelane_b32 v5, s30, 0
-; CHECK-NEXT:v_writelane_b32 v5, s31, 1
-; CHECK-NEXT:v_writelane_b32 v5, s36, 2
-; CHECK-NEXT:v_writelane_b32 v5, s37, 3
-; CHECK-NEXT:v_writelane_b32 v5, s38, 4
-; CHECK-NEXT:v_writelane_b32 v5, s39, 5
-; CHECK-NEXT:v_writelane_b32 v5, s48, 6
-; CHECK-NEXT:v_writelane_b32 v5, s49, 7
-; CHECK-NEXT:v_writelane_b32 v5, s50, 8
-; CHECK-NEXT:v_writelane_b32 v5, s51, 9
-; CHECK-NEXT:v_writelane_b32 v5, s52, 10
-; CHECK-NEXT:v_writelane_b32 v5, s53, 11
-; CHECK-NEXT:v_writelane_b32 v5, s54, 12
-; CHECK-NEXT:v_writelane_b32 v5, s55, 13
-; CHECK-NEXT:s_getpc_b64 s[24:25]
-; CHECK-NEXT:v_writelane_b32 v5, s64, 14
-; CHECK-NEXT:s_movk_i32 s4, 0xf0
-; CHECK-NEXT:s_mov_b32 s5, s24
-; CHECK-NEXT:v_writelane_b32 v5, s65, 15
-; CHECK-NEXT:s_load_dwordx16 s[8:23], s[4:5], 0x0
-; CHECK-NEXT:s_mov_b64 s[4:5], 0
-; CHECK-NEXT:v_writelane_b32 v5, s66, 16
-; CHECK-NEXT:s_load_dwordx4 s[4:7], s[4:5], 0x0
-; CHECK-NEXT:v_writelane_b32 v5, s67, 17
-; CHECK-NEXT:s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:s_movk_i32 s6, 0x130
-; CHECK-NEXT:s_mov_b32 s7, s24
-; CHECK-NEXT:v_writelane_b32 v5
[llvm-branch-commits] [llvm] [LoongArch] Override shouldScalarizeBinop to enable `extract(binop)->binop(extract)` combination (PR #159726)
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: ZhaoQi (zhaoqi5)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/159726.diff
4 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+19)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.h (+2)
- (modified) llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll (+23-36)
- (modified) llvm/test/CodeGen/LoongArch/lsx/extract-binop.ll (+23-36)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index add6bec686c71..a471001086b68 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -9105,3 +9105,22 @@ bool
LoongArchTargetLowering::SimplifyDemandedBitsForTargetNode(
return TargetLowering::SimplifyDemandedBitsForTargetNode(
Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
}
+
+bool LoongArchTargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
+ unsigned Opc = VecOp.getOpcode();
+
+ // Assume target opcodes can't be scalarized.
+ // TODO - do we have any exceptions?
+ if (Opc >= ISD::BUILTIN_OP_END || !isBinOp(Opc))
+return false;
+
+ // If the vector op is not supported, try to convert to scalar.
+ EVT VecVT = VecOp.getValueType();
+ if (!isOperationLegalOrCustomOrPromote(Opc, VecVT))
+return true;
+
+ // If the vector op is supported, but the scalar op is not, the transform may
+ // not be worthwhile.
+ EVT ScalarVT = VecVT.getScalarType();
+ return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
+}
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 9d14934a9d363..8da492570146e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -332,6 +332,8 @@ class LoongArchTargetLowering : public TargetLowering {
TargetLoweringOpt &TLO,
unsigned Depth) const override;
+ bool shouldScalarizeBinop(SDValue VecOp) const override;
+
private:
/// Target-specific function used to lower LoongArch calling conventions.
typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
diff --git a/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
b/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
index 1517e11aa7d7a..4986b12199c31 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/extract-binop.ll
@@ -31,12 +31,18 @@ entry:
}
define i32 @extractelt_add_v8i32(ptr %p) {
-; CHECK-LABEL: extractelt_add_v8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xvld $xr0, $a0, 0
-; CHECK-NEXT:xvaddi.wu $xr0, $xr0, 13
-; CHECK-NEXT:xvpickve2gr.w $a0, $xr0, 2
-; CHECK-NEXT:ret
+; LA32-LABEL: extractelt_add_v8i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT:ld.w $a0, $a0, 8
+; LA32-NEXT:addi.w $a0, $a0, 13
+; LA32-NEXT:ret
+;
+; LA64-LABEL: extractelt_add_v8i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT:xvld $xr0, $a0, 0
+; LA64-NEXT:xvaddi.wu $xr0, $xr0, 13
+; LA64-NEXT:xvpickve2gr.w $a0, $xr0, 2
+; LA64-NEXT:ret
entry:
%x = load <8 x i32>, ptr %p
%add = add <8 x i32> %x,
@@ -55,9 +61,8 @@ define i64 @extractelt_add_v4i64(ptr %p) {
;
; LA64-LABEL: extractelt_add_v4i64:
; LA64: # %bb.0: # %entry
-; LA64-NEXT:xvld $xr0, $a0, 0
-; LA64-NEXT:xvaddi.du $xr0, $xr0, 12
-; LA64-NEXT:xvpickve2gr.d $a0, $xr0, 1
+; LA64-NEXT:ld.d $a0, $a0, 8
+; LA64-NEXT:addi.d $a0, $a0, 12
; LA64-NEXT:ret
entry:
%x = load <4 x i64>, ptr %p
@@ -69,12 +74,9 @@ entry:
define float @extractelt_fadd_v8f32(ptr %p) {
; CHECK-LABEL: extractelt_fadd_v8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xvld $xr0, $a0, 0
-; CHECK-NEXT:lu12i.w $a0, 267520
-; CHECK-NEXT:xvreplgr2vr.w $xr1, $a0
-; CHECK-NEXT:xvfadd.s $xr0, $xr0, $xr1
-; CHECK-NEXT:xvpickve.w $xr0, $xr0, 2
-; CHECK-NEXT:# kill: def $f0 killed $f0 killed $xr0
+; CHECK-NEXT:fld.s $fa0, $a0, 8
+; CHECK-NEXT:vldi $vr1, -1238
+; CHECK-NEXT:fadd.s $fa0, $fa0, $fa1
; CHECK-NEXT:ret
entry:
%x = load <8 x float>, ptr %p
@@ -84,27 +86,12 @@ entry:
}
define double @extractelt_fadd_v4f64(ptr %p) {
-; LA32-LABEL: extractelt_fadd_v4f64:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT:xvld $xr0, $a0, 0
-; LA32-NEXT:pcalau12i $a0, %pc_hi20(.LCPI5_0)
-; LA32-NEXT:xvld $xr1, $a0, %pc_lo12(.LCPI5_0)
-; LA32-NEXT:xvfadd.d $xr0, $xr0, $xr1
-; LA32-NEXT:xvpickve.d $xr0, $xr0, 1
-; LA32-NEXT:# kill: def $f0_64 killed $f0_64 killed $xr0
-; LA32-NEXT:ret
-;
-; LA64-LABEL: extractelt_fadd_v4f64:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT:xvld $xr0, $a0, 0
-; LA64-NEXT:ori $a0, $zero, 0
-; LA64-NEXT:lu32i.d $a0, -524288
[llvm-branch-commits] [Remarks] YAMLRemarkSerializer: Fix StringRef out-of-bounds read (PR #159759)
https://github.com/tobias-stadler created https://github.com/llvm/llvm-project/pull/159759 YAML IO `mapRequired` expects a null-terminated `const char *` Key, so we can't legally pass a StringRef to it. We should add StringRef Key support to YAML IO, but for now just copy the key into a correctly null-terminated string. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Offload] Add GenericPluginTy::get_mem_info (PR #157484)
@@ -3561,6 +3564,28 @@ struct AMDGPUPluginTy final : public GenericPluginTy {
return KernelAgents;
}
+ Expected getMemoryInfo(const void *TgtPtr) override {
jplehr wrote:
The code in `OffloadImpl` and the code in the NVidia case had/have
`std::lock_guard` guarding. Is this not necessary here or has it been missed,
or do I simply not see it?
https://github.com/llvm/llvm-project/pull/157484
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [CodeGen][CFI] Generalize transparent union parameters (PR #158193)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff origin/main HEAD --extensions cpp,c --
clang/lib/CodeGen/CodeGenModule.cpp clang/test/CodeGen/cfi-icall-generalize.c
clang/test/CodeGen/cfi-icall-normalize2.c clang/test/CodeGen/kcfi-generalize.c
clang/test/CodeGen/kcfi-normalize.c
``
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
View the diff from clang-format here.
``diff
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 46dbd8566..54597ca58 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2352,8 +2352,7 @@ static QualType GeneralizeTransparentUnion(QualType Ty) {
return Ty;
}
-static QualType GeneralizeTransparentUnion(QualType Ty) {
-}
+static QualType GeneralizeTransparentUnion(QualType Ty) {}
// Generalize pointer types to a void pointer with the qualifiers of the
// originally pointed-to type, e.g. 'const char *' and 'char * const *'
``
https://github.com/llvm/llvm-project/pull/158193
___
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[email protected]
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[llvm-branch-commits] [flang] [flang][OpenMP] `do concurrent` to device mapping lit tests (PR #155992)
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/155992
>From 6d564c61ee23d20f411aadf598705140d5fbca2c Mon Sep 17 00:00:00 2001
From: ergawy
Date: Fri, 29 Aug 2025 03:53:51 -0500
Subject: [PATCH] [flang][OpenMP] `do concurrent` to device mapping lit tests
Adds more lit tests for `do concurrent` device mapping.
---
.../Transforms/DoConcurrent/allocatable.f90 | 29 +
.../Transforms/DoConcurrent/host_eval.f90 | 63 +++
.../DoConcurrent/locally_destroyed_temp.f90 | 43 ---
.../DoConcurrent/map_shape_info.f90 | 104 +
.../multiple_iteration_ranges.f90 | 106 +++---
.../DoConcurrent/non_reference_to_device.f90 | 34 ++
.../DoConcurrent/not_perfectly_nested.f90 | 66 +++
.../DoConcurrent/runtime_sized_array.f90 | 42 +++
.../DoConcurrent/skip_all_nested_loops.f90| 68 +++
9 files changed, 478 insertions(+), 77 deletions(-)
create mode 100644 flang/test/Transforms/DoConcurrent/allocatable.f90
create mode 100644 flang/test/Transforms/DoConcurrent/host_eval.f90
create mode 100644 flang/test/Transforms/DoConcurrent/map_shape_info.f90
create mode 100644
flang/test/Transforms/DoConcurrent/non_reference_to_device.f90
create mode 100644 flang/test/Transforms/DoConcurrent/runtime_sized_array.f90
create mode 100644 flang/test/Transforms/DoConcurrent/skip_all_nested_loops.f90
diff --git a/flang/test/Transforms/DoConcurrent/allocatable.f90
b/flang/test/Transforms/DoConcurrent/allocatable.f90
new file mode 100644
index 0..03962f150eb95
--- /dev/null
+++ b/flang/test/Transforms/DoConcurrent/allocatable.f90
@@ -0,0 +1,29 @@
+! Verifies that proper `omp.map.bounds` ops are emitted when an allocatable is
+! implicitly mapped by a `do concurrent` loop.
+
+! RUN: %flang_fc1 -emit-hlfir -fopenmp -fdo-concurrent-to-openmp=device %s -o
- \
+! RUN: | FileCheck %s
+program main
+ implicit none
+
+ integer,parameter :: n = 100
+ real, allocatable, dimension(:) :: y
+ integer :: i
+
+ allocate(y(1:n))
+
+ do concurrent(i=1:n)
+ y(i) = 42
+ end do
+
+ deallocate(y)
+end program main
+
+! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs =
#fir.var_attrs, uniq_name = "_QFEy"}
+! CHECK: %[[Y_VAL:.*]] = fir.load %[[Y_DECL]]#0
+! CHECK: %[[Y_DIM0:.*]]:3 = fir.box_dims %[[Y_VAL]], %{{c0_.*}}
+! CHECK: %[[Y_LB:.*]] = arith.constant 0 : index
+! CHECK: %[[Y_UB:.*]] = arith.subi %[[Y_DIM0]]#1, %{{c1_.*}} : index
+! CHECK: %[[Y_BOUNDS:.*]] = omp.map.bounds lower_bound(%[[Y_LB]] : index)
upper_bound(%[[Y_UB]] : index) extent(%[[Y_DIM0]]#1 : index)
+! CHECK: %[[MEM_MAP:.*]] = omp.map.info {{.*}} bounds(%[[Y_BOUNDS]])
+! CHECK: omp.map.info var_ptr(%[[Y_DECL]]#1 : {{.*}}) {{.*}}
members(%[[MEM_MAP]] : {{.*}})
diff --git a/flang/test/Transforms/DoConcurrent/host_eval.f90
b/flang/test/Transforms/DoConcurrent/host_eval.f90
new file mode 100644
index 0..7d16a91ae6941
--- /dev/null
+++ b/flang/test/Transforms/DoConcurrent/host_eval.f90
@@ -0,0 +1,63 @@
+! Tests `host_eval` clause code-gen and loop nest bounds on host vs. device.
+
+! RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa \
+! RUN: -fdo-concurrent-to-openmp=device %s -o - \
+! RUN: | FileCheck %s --check-prefix=HOST -vv
+
+! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp\
+! RUN: -fopenmp-is-target-device -fdo-concurrent-to-openmp=device %s -o - \
+! RUN: | FileCheck %s --check-prefix=DEVICE
+
+program do_concurrent_host_eval
+implicit none
+integer :: i, j
+
+do concurrent (i=1:10, j=1:20)
+end do
+end program do_concurrent_host_eval
+
+! HOST: omp.target host_eval(
+! HOST-SAME:%{{[^[:space:]]+}} -> %[[I_LB:[^,]+]],
+! HOST-SAME:%{{[^[:space:]]+}} -> %[[I_UB:[^,]+]],
+! HOST-SAME:%{{[^[:space:]]+}} -> %[[I_ST:[^,]+]],
+! HOST-SAME:%{{[^[:space:]]+}} -> %[[J_LB:[^,]+]],
+! HOST-SAME:%{{[^[:space:]]+}} -> %[[J_UB:[^,]+]],
+! HOST-SAME:%{{[^[:space:]]+}} -> %[[J_ST:[^,]+]] : {{.*}}) map_entries
+
+! HOST: omp.loop_nest ({{.*}}, {{.*}}) : index = (%[[I_LB]], %[[J_LB]]) to
+! HOST-SAME:(%[[I_UB]], %[[J_UB]]) inclusive step
+! HOST-SAME:(%[[I_ST]], %[[J_ST]])
+
+! DEVICE: omp.target map_entries(
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %[[I_LB_MAP:[^,]+]],
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %[[I_UB_MAP:[^,]+]],
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %[[I_ST_MAP:[^,]+]],
+
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %[[J_LB_MAP:[^,]+]],
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %[[J_UB_MAP:[^,]+]],
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %[[J_ST_MAP:[^,]+]],
+
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %{{[^,]+}},
+! DEVICE-SAME: %{{[^[:space:]]+}} -> %{{[^,]+}} : {{.*}})
+
+! DEVICE: %[[I_LB_DECL:.*]]:2 = hlfir.declare %[[I_LB_MAP]]
+! DEVICE: %[[I_LB:.*]] = fir.load %[[I_LB_DECL]]#1 : !fir.ref
+
+! DEVICE: %[[I_UB_DECL:.*]]:2 = hlfir.declare %[[I_UB_MAP]
[llvm-branch-commits] [llvm] 5fd3aad - [DirectX] Updating Root Signature YAML representation to use Enums instead of uint (#154827)
Author: joaosaffran
Date: 2025-09-12T14:31:27-04:00
New Revision: 5fd3aad54c1be20c96fe407348604b4657ce53ab
URL:
https://github.com/llvm/llvm-project/commit/5fd3aad54c1be20c96fe407348604b4657ce53ab
DIFF:
https://github.com/llvm/llvm-project/commit/5fd3aad54c1be20c96fe407348604b4657ce53ab.diff
LOG: [DirectX] Updating Root Signature YAML representation to use Enums instead
of uint (#154827)
This PR is updating Root Signature YAML to use enums, this is a required
change to remove the use of to_underlying from DirectXContainer binary
file.
Closes: [#150676](https://github.com/llvm/llvm-project/issues/150676)
Added:
Modified:
llvm/include/llvm/ObjectYAML/DXContainerYAML.h
llvm/include/llvm/Support/DXILABI.h
llvm/lib/ObjectYAML/DXContainerEmitter.cpp
llvm/lib/ObjectYAML/DXContainerYAML.cpp
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants.ll
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor.ll
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor_V1.ll
llvm/test/CodeGen/DirectX/ContainerData/RootSignature-StaticSamplers.ll
llvm/test/ObjectYAML/DXContainer/RootSignature-Descriptor1.0.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-Descriptor1.1.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-DescriptorTable1.0.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-DescriptorTable1.1.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-Invalid-StaticSamplersOffset.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-MultipleParameters.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-OptionalOffsets.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-StaticSamplerOffset1.0.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-StaticSamplerOffset1.1.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-StaticSamplers-Defaults.yaml
llvm/test/ObjectYAML/DXContainer/RootSignature-StaticSamplers.yaml
llvm/unittests/ObjectYAML/DXContainerYAMLTest.cpp
Removed:
diff --git a/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
b/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
index 359b27761cea3..62bfee7693db1 100644
--- a/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
+++ b/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
@@ -92,7 +92,7 @@ struct RootDescriptorYaml {
};
struct DescriptorRangeYaml {
- uint32_t RangeType;
+ dxil::ResourceClass RangeType;
uint32_t NumDescriptors;
uint32_t BaseShaderRegister;
uint32_t RegisterSpace;
@@ -111,12 +111,12 @@ struct DescriptorTableYaml {
};
struct RootParameterHeaderYaml {
- uint32_t Type;
- uint32_t Visibility;
+ dxbc::RootParameterType Type;
+ dxbc::ShaderVisibility Visibility;
uint32_t Offset;
RootParameterHeaderYaml(){};
- RootParameterHeaderYaml(uint32_t T) : Type(T) {}
+ RootParameterHeaderYaml(dxbc::RootParameterType T) : Type(T) {}
};
struct RootParameterLocationYaml {
@@ -165,21 +165,19 @@ struct RootParameterYamlDesc {
};
struct StaticSamplerYamlDesc {
- uint32_t Filter = llvm::to_underlying(dxbc::SamplerFilter::Anisotropic);
- uint32_t AddressU = llvm::to_underlying(dxbc::TextureAddressMode::Wrap);
- uint32_t AddressV = llvm::to_underlying(dxbc::TextureAddressMode::Wrap);
- uint32_t AddressW = llvm::to_underlying(dxbc::TextureAddressMode::Wrap);
+ dxbc::SamplerFilter Filter = dxbc::SamplerFilter::Anisotropic;
+ dxbc::TextureAddressMode AddressU = dxbc::TextureAddressMode::Wrap;
+ dxbc::TextureAddressMode AddressV = dxbc::TextureAddressMode::Wrap;
+ dxbc::TextureAddressMode AddressW = dxbc::TextureAddressMode::Wrap;
float MipLODBias = 0.f;
uint32_t MaxAnisotropy = 16u;
- uint32_t ComparisonFunc =
- llvm::to_underlying(dxbc::ComparisonFunc::LessEqual);
- uint32_t BorderColor =
- llvm::to_underlying(dxbc::StaticBorderColor::OpaqueWhite);
+ dxbc::ComparisonFunc ComparisonFunc = dxbc::ComparisonFunc::LessEqual;
+ dxbc::StaticBorderColor BorderColor = dxbc::StaticBorderColor::OpaqueWhite;
float MinLOD = 0.f;
float MaxLOD = std::numeric_limits::max();
uint32_t ShaderRegister;
uint32_t RegisterSpace;
- uint32_t ShaderVisibility;
+ dxbc::ShaderVisibility ShaderVisibility;
};
struct RootSignatureYamlDesc {
@@ -321,6 +319,13 @@
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::PSV::ResourceKind)
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::D3DSystemValue)
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::SigComponentType)
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::SigMinPrecision)
+LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::RootParameterType)
+LLVM_YAML_DECLARE_ENUM_TRAITS(dxil::ResourceClass)
+LLVM_YAML
[llvm-branch-commits] [clang] b0c713d - Add null checks
Author: Samira Bakon
Date: 2025-09-09T14:12:39-04:00
New Revision: b0c713d5851dcb5dd5002ea15793947e17b4ae1f
URL:
https://github.com/llvm/llvm-project/commit/b0c713d5851dcb5dd5002ea15793947e17b4ae1f
DIFF:
https://github.com/llvm/llvm-project/commit/b0c713d5851dcb5dd5002ea15793947e17b4ae1f.diff
LOG: Add null checks
Added:
Modified:
clang/lib/Analysis/FlowSensitive/RecordOps.cpp
Removed:
diff --git a/clang/lib/Analysis/FlowSensitive/RecordOps.cpp
b/clang/lib/Analysis/FlowSensitive/RecordOps.cpp
index 71b2aa9ff2ec4..ed827ac2c7c90 100644
--- a/clang/lib/Analysis/FlowSensitive/RecordOps.cpp
+++ b/clang/lib/Analysis/FlowSensitive/RecordOps.cpp
@@ -84,7 +84,8 @@ void copyRecord(RecordStorageLocation &Src,
RecordStorageLocation &Dst,
for (const auto &[Name, DstFieldLoc] : Dst.synthetic_fields())
copySyntheticField(DstFieldLoc->getType(), Src.getSyntheticField(Name),
*DstFieldLoc, Env);
- } else if (DstDecl->isDerivedFrom(SrcDecl)) {
+ } else if (SrcDecl != nullptr && DstDecl != nullptr &&
+ DstDecl->isDerivedFrom(SrcDecl)) {
for (auto [Field, SrcFieldLoc] : Src.children())
copyField(*Field, SrcFieldLoc, Dst.getChild(*Field), Dst, Env);
for (const auto &[Name, SrcFieldLoc] : Src.synthetic_fields())
___
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[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)
https://github.com/melver updated https://github.com/llvm/llvm-project/pull/156841 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156840
>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types
Created using spr 1.3.8-beta.1
---
clang/lib/CodeGen/CGExpr.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 288b41bc42203..455de644daf00 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1289,6 +1289,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
// Check if QualType contains a pointer. Implements a simple DFS to
// recursively check if a type contains a pointer type.
llvm::SmallPtrSet VisitedRD;
+ bool IncompleteType = false;
auto TypeContainsPtr = [&](auto &&self, QualType T) -> bool {
QualType CanonicalType = T.getCanonicalType();
if (CanonicalType->isPointerType())
@@ -1312,6 +1313,10 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
return self(self, AT->getElementType());
// The type is a struct, class, or union.
if (const RecordDecl *RD = CanonicalType->getAsRecordDecl()) {
+ if (!RD->isCompleteDefinition()) {
+IncompleteType = true;
+return false;
+ }
if (!VisitedRD.insert(RD).second)
return false; // already visited
// Check all fields.
@@ -1333,6 +1338,8 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
return false;
};
const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
+ if (!ContainsPtr && IncompleteType)
+return nullptr;
auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
>From 7f706618ddc40375d4085bc2ebe03f02ec78823a Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:58:01 +0200
Subject: [PATCH 2/2] fixup!
Created using spr 1.3.8-beta.1
---
clang/lib/CodeGen/CGExpr.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 455de644daf00..e7a0e7696e204 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1339,7 +1339,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
};
const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
if (!ContainsPtr && IncompleteType)
-return nullptr;
+return;
auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
___
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[llvm-branch-commits] [lit] Add support for readfile to external shell (PR #159431)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/159431 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
https://github.com/usx95 created
https://github.com/llvm/llvm-project/pull/159850
None
>From 05da67b132b73bef44de71fe950983f87ce883b8 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Fri, 19 Sep 2025 21:30:46 +
Subject: [PATCH] no-canonicalize
---
clang/lib/Analysis/LifetimeSafety.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 0dd5716d93fb6..ac761d73ba0da 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -966,9 +966,9 @@ using ExpiredLoanMap = llvm::ImmutableMap;
/// An object to hold the factories for immutable collections, ensuring
/// that all created states share the same underlying memory management.
struct LifetimeFactory {
- OriginLoanMap::Factory OriginMapFactory;
- LoanSet::Factory LoanSetFactory;
- ExpiredLoanMap::Factory ExpiredLoanMapFactory;
+ OriginLoanMap::Factory OriginMapFactory = OriginLoanMap::Factory(false);
+ LoanSet::Factory LoanSetFactory = LoanSet::Factory(false);
+ ExpiredLoanMap::Factory ExpiredLoanMapFactory =
ExpiredLoanMap::Factory(false);
};
/// Represents the dataflow lattice for loan propagation.
___
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[llvm-branch-commits] [clang] no-canonicalize (PR #159850)
usx95 wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159850?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#159850** https://app.graphite.dev/github/pr/llvm/llvm-project/159850?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/159850?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#159845** https://app.graphite.dev/github/pr/llvm/llvm-project/159845?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/159850 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] TableGen: Support target specialized pseudoinstructions (PR #159880)
llvmbot wrote:
@llvm/pr-subscribers-tablegen
Author: Matt Arsenault (arsenm)
Changes
Allow a target to steal the definition of a generic pseudoinstruction
and remap the operands. This works by defining a new instruction, which
will simply swap out the emitted entry in the InstrInfo table.
This is intended to eliminate the C++ half of the implementation
of PointerLikeRegClass. With RegClassByHwMode, the remaining usecase
for PointerLikeRegClass are the common codegen pseudoinstructions.
Every target maintains its own copy of the generic pseudo operand
definitions anyway, so we can stub out the register operands with
an appropriate class instead of waiting for runtime resolution.
In the future we could probably take this a bit further. For example,
there is a similar problem for ADJCALLSTACKUP/DOWN since they depend
on target register definitions for the stack pointer register.
---
Full diff: https://github.com/llvm/llvm-project/pull/159880.diff
4 Files Affected:
- (modified) llvm/include/llvm/Target/Target.td (+93)
- (added) llvm/test/TableGen/target-specialized-pseudos.td (+101)
- (modified) llvm/utils/TableGen/Common/CodeGenTarget.cpp (+12-1)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+37)
``diff
diff --git a/llvm/include/llvm/Target/Target.td
b/llvm/include/llvm/Target/Target.td
index 13175177edd3e..4a759a99d1d25 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1574,6 +1574,99 @@ def CONVERGENCECTRL_GLUE : StandardPseudoInstruction {
}
}
+/// Allow a target to replace the instruction definition of a
+/// StandardPseudoInstruction. A target should only define one
+/// instance of this per instruction.
+///
+/// This is intended to allow targets to specify the register class
+/// used for pointers. It should not be used to change the fundamental
+/// operand structure (e.g., this should not add or remove operands,
+/// or change the operand types).
+class TargetSpecializedStandardPseudoInstruction<
+ StandardPseudoInstruction base_inst> : Instruction {
+
+ StandardPseudoInstruction Instruction = base_inst;
+ let OutOperandList = base_inst.OutOperandList;
+ let InOperandList = base_inst.InOperandList;
+
+ // TODO: Copy everything
+ let usesCustomInserter = base_inst.usesCustomInserter;
+ let hasSideEffects = base_inst.hasSideEffects;
+ let mayLoad = base_inst.mayLoad;
+ let mayStore = base_inst.mayStore;
+ let isTerminator = base_inst.isTerminator;
+ let isBranch = base_inst.isBranch;
+ let isIndirectBranch = base_inst.isIndirectBranch;
+ let isEHScopeReturn = base_inst.isEHScopeReturn;
+ let isReturn = base_inst.isReturn;
+ let isCall = base_inst.isCall;
+ let hasCtrlDep = base_inst.hasCtrlDep;
+ let isReMaterializable = base_inst.isReMaterializable;
+ let isMeta = base_inst.isMeta;
+ let Size = base_inst.Size;
+ let isAsCheapAsAMove = base_inst.isAsCheapAsAMove;
+ let isPseudo = true;
+ let hasNoSchedulingInfo = true;
+ let isNotDuplicable = base_inst.isNotDuplicable;
+ let isConvergent = base_inst.isConvergent;
+ let hasExtraSrcRegAllocReq = base_inst.hasExtraSrcRegAllocReq;
+ let hasExtraDefRegAllocReq = base_inst.hasExtraDefRegAllocReq;
+}
+
+// All pseudo instructions which need a pointer register class, which
+// should be specialized by a target.
+defvar PseudosWithPtrOps = [
+ LOAD_STACK_GUARD,
+ PREALLOCATED_ARG,
+ PATCHABLE_EVENT_CALL,
+ PATCHABLE_TYPED_EVENT_CALL
+];
+
+
+/// Replace PointerLikeRegClass operands in OperandList with new_rc.
+class RemapPointerOperandList {
+ // Collect the set of names so we can query and rewrite them.
+ list op_names = !foreach(i, !range(!size(OperandList)),
+ !getdagname(OperandList, i));
+
+ // Beautiful language. This would be a lot easier if !getdagarg
+ // didn't require a specific type. We can't just collect a list of
+ // the operand values and reconstruct the dag, since there isn't a
+ // common base class for all the field kinds used in
+ // pseudoinstruction definitions; therefore everything must be
+ // maintained as a dag, so use a foldl. Additionally, ? doesn't
+ // evaluate as false so we get even more noise.
+ dag ret =
+!foldl(OperandList, op_names, acc, name,
+ !cond(
+!initialized(!getdagarg(OperandList, name))
+ : !setdagarg(acc, name, new_rc),
+!initialized(!getdagarg(OperandList, name)) : acc,
+!initialized(!getdagarg(OperandList, name)) : acc
+ )
+);
+}
+
+/// Define an override for a pseudoinstruction which uses a pointer
+/// register class, specialized to the target's pointer type.
+class RemapPointerOperands :
+ TargetSpecializedStandardPseudoInstruction {
+ let OutOperandList =
+RemapPointerOperandList.ret;
+ let InOperandList =
+RemapPointerOperandList.ret;
+}
+
+/// Helper to replace all pseudoinstructions using pointers to a
+/// target register class. Most targets should use this
+multiclass RemapAllTargetP
[llvm-branch-commits] [llvm] CodeGen: Make all targets override pseudos with pointers (PR #159881)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
This eliminates the need to have PointerLikeRegClass handling in
codegen.
---
Full diff: https://github.com/llvm/llvm-project/pull/159881.diff
26 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64.td (+2)
- (modified) llvm/lib/Target/AMDGPU/R600.td (+12-9)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+11)
- (modified) llvm/lib/Target/ARM/ARM.td (+8)
- (modified) llvm/lib/Target/AVR/AVR.td (+2)
- (modified) llvm/lib/Target/BPF/BPF.td (+3)
- (modified) llvm/lib/Target/CSKY/CSKY.td (+2)
- (modified) llvm/lib/Target/DirectX/DirectX.td (+2)
- (modified) llvm/lib/Target/Hexagon/Hexagon.td (+2)
- (modified) llvm/lib/Target/Lanai/Lanai.td (+2)
- (modified) llvm/lib/Target/LoongArch/LoongArch.td (+2)
- (modified) llvm/lib/Target/M68k/M68k.td (+2)
- (modified) llvm/lib/Target/MSP430/MSP430.td (+2)
- (modified) llvm/lib/Target/Mips/Mips.td (+2)
- (modified) llvm/lib/Target/NVPTX/NVPTX.td (+10)
- (modified) llvm/lib/Target/PowerPC/PPC.td (+2)
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.td (+4)
- (modified) llvm/lib/Target/RISCV/RISCV.td (+2)
- (modified) llvm/lib/Target/SPIRV/SPIRV.td (+2)
- (modified) llvm/lib/Target/Sparc/Sparc.td (+2)
- (modified) llvm/lib/Target/SystemZ/SystemZ.td (+3-1)
- (modified) llvm/lib/Target/VE/VE.td (+1)
- (modified) llvm/lib/Target/WebAssembly/WebAssembly.td (+8)
- (modified) llvm/lib/Target/X86/X86.td (+2)
- (modified) llvm/lib/Target/XCore/XCore.td (+2)
- (modified) llvm/lib/Target/Xtensa/Xtensa.td (+2)
``diff
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 86f95488e6bb7..d98c235dab15e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -40,6 +40,8 @@ include "AArch64SchedPredExynos.td"
include "AArch64SchedPredNeoverse.td"
include "AArch64Combine.td"
+defm : RemapAllTargetPseudoPointerOperands;
+
def AArch64InstrInfo : InstrInfo;
//===--===//
diff --git a/llvm/lib/Target/AMDGPU/R600.td b/llvm/lib/Target/AMDGPU/R600.td
index 9148edb92b084..bdfaac9f42ea7 100644
--- a/llvm/lib/Target/AMDGPU/R600.td
+++ b/llvm/lib/Target/AMDGPU/R600.td
@@ -8,15 +8,6 @@
include "llvm/Target/Target.td"
-def R600InstrInfo : InstrInfo {
- let guessInstructionProperties = 1;
-}
-
-def R600 : Target {
- let InstructionSet = R600InstrInfo;
- let AllowRegisterRenaming = 1;
-}
-
let Namespace = "R600" in {
foreach Index = 0-15 in {
@@ -27,6 +18,18 @@ include "R600RegisterInfo.td"
}
+defm : RemapAllTargetPseudoPointerOperands;
+
+def R600InstrInfo : InstrInfo {
+ let guessInstructionProperties = 1;
+}
+
+def R600 : Target {
+ let InstructionSet = R600InstrInfo;
+ let AllowRegisterRenaming = 1;
+}
+
+
def NullALU : InstrItinClass;
def ALU_NULL : FuncUnit;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td
b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 88a26832980d6..eecccd2e0e395 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4745,3 +4745,14 @@ def V_ILLEGAL : Enc32, InstSI<(outs), (ins),
"v_illegal"> {
let hasSideEffects = 1;
let SubtargetPredicate = isGFX10Plus;
}
+
+defvar VGPR32_Ptr_Opcodes = [LOAD_STACK_GUARD];
+defvar VGPR64_Ptr_Opcodes = !listremove(PseudosWithPtrOps, VGPR32_Ptr_Opcodes);
+
+foreach inst = VGPR32_Ptr_Opcodes in {
+ def : RemapPointerOperands;
+}
+
+foreach inst = VGPR64_Ptr_Opcodes in {
+ def : RemapPointerOperands;
+}
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 570aae9b3c7a7..1f71d810983db 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -38,6 +38,14 @@ include "ARMSchedule.td"
//===--===//
include "ARMInstrInfo.td"
+
+def Thumb1OnlyMode : HwMode<[IsThumb1Only]>;
+def arm_ptr_rc : RegClassByHwMode<
+ [DefaultMode, Thumb1OnlyMode],
+ [GPR, tGPR]>;
+
+defm : RemapAllTargetPseudoPointerOperands;
+
def ARMInstrInfo : InstrInfo;
//===--===//
diff --git a/llvm/lib/Target/AVR/AVR.td b/llvm/lib/Target/AVR/AVR.td
index 22ffc4a368ad6..f4ee11984cb73 100644
--- a/llvm/lib/Target/AVR/AVR.td
+++ b/llvm/lib/Target/AVR/AVR.td
@@ -32,6 +32,8 @@ include "AVRRegisterInfo.td"
include "AVRInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands;
+
def AVRInstrInfo : InstrInfo;
//===-===//
diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td
index dff76ca07af51..399be731b44f6 100644
--- a/llvm/lib/Target/BPF/BPF.td
+++ b/llvm/lib/Target/BPF/BPF.td
@@ -13,6 +13,9 @@ include "BPFCallingConv.td"
include "BPFInstrInfo.td"
include "GISel/BPFRegisterBanks.td"
+
+defm : RemapAllTargetPseudoPointerOpera
[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/159883
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
>From 9d6a7e1dbf85eecadc522c341e9959122f46b2d3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 20:13:52 +0900
Subject: [PATCH] CodeGen: Remove PointerLikeRegClass handling from codegen
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
---
llvm/include/llvm/MC/MCInstrDesc.h| 13 +-
llvm/include/llvm/Target/Target.td| 26 +--
llvm/lib/CodeGen/TargetInstrInfo.cpp | 4 ---
.../llvm-exegesis/lib/MCInstrDescView.cpp | 2 +-
.../TableGen/Common/CodeGenDAGPatterns.cpp| 13 +-
.../TableGen/Common/InstructionEncoding.cpp | 3 ---
llvm/utils/TableGen/DAGISelMatcherGen.cpp | 1 -
llvm/utils/TableGen/InstrInfoEmitter.cpp | 6 +
8 files changed, 17 insertions(+), 51 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h
b/llvm/include/llvm/MC/MCInstrDesc.h
index 0a4bd17e20738..fd637f956592b 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -49,8 +49,7 @@ enum OperandConstraint {
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
- LookupPtrRegClass = 0,
- LookupRegClassByHwMode,
+ LookupRegClassByHwMode = 0,
Predicate,
OptionalDef,
BranchTarget
@@ -90,9 +89,6 @@ class MCOperandInfo {
/// operand is a register. If LookupRegClassByHwMode is set, then this is an
/// index into a table in TargetInstrInfo or MCInstrInfo which contains the
/// real register class ID.
- ///
- /// If isLookupPtrRegClass is set, then this is an index that is passed to
- /// TargetRegisterInfo::getPointerRegClass(x) to get a dynamic register
class.
int16_t RegClass;
/// These are flags from the MCOI::OperandFlags enum.
@@ -104,13 +100,6 @@ class MCOperandInfo {
/// Operand constraints (see OperandConstraint enum).
uint16_t Constraints;
- /// Set if this operand is a pointer value and it requires a callback
- /// to look up its register class.
- // TODO: Deprecated in favor of isLookupRegClassByHwMode
- bool isLookupPtrRegClass() const {
-return Flags & (1 << MCOI::LookupPtrRegClass);
- }
-
/// Set if this operand is a value that requires the current hwmode to look
up
/// its register class.
bool isLookupRegClassByHwMode() const {
diff --git a/llvm/include/llvm/Target/Target.td
b/llvm/include/llvm/Target/Target.td
index 4a759a99d1d25..7cbf131640917 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regclass to use by using
-/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
-///
-/// This is deprecated in favor of RegClassByHwMode.
+/// PointerLikeRegClass - Pseudoinstruction operands that are designed
+/// to have pointer width are derived from this. This should only be
+/// used by StandardPseudoInstruction instructions. No target specific
+/// instruction should use this.
class PointerLikeRegClass {
int RegClassKind = Kind;
}
+/// ptr_rc definition - Mark this operand as being a pointer value
+/// whose register class needs to be defined by the target. Targets
+/// should provide instruction definition overrides which substitute
+/// the uses of this with the backend defined RegisterClass or
+/// RegClassByHwMode to use for pointer virtual registers for a
+/// particular opcode (typically by defining a subsitute instruction
+/// with RemapPointerOperands).
+def ptr_rc : PointerLikeRegClass<0>;
+
/// RegClassByHwMode - Operands that change the register class based
/// on the subtarget are derived from this. TableGen
/// treats the register class as having a symbolic kind that it
@@ -941,13 +948,6 @@ class RegClassByHwMode Modes,
list Objects = RegClasses;
}
-/// ptr_rc definition - Mark this operand as being a pointer value whose
-/// register class is resolved dynamically via a callback to TargetInstrInfo.
-/// FIXME: We should probably change this to a class which contain a list of
-/// flags. But currently we have but one flag.
-// Deprecated, use RegClassByHwMode instead.
-def ptr_rc : PointerLikeRegClass<0>;
-
/// unknown definition - Mark this operand as being of unknown type, causing
/// it to be resolved by inference in the context it is used.
class unknown_class;
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp
b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 5be89b49fb6ba..761
[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Matt Arsenault (arsenm)
Changes
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
---
Full diff: https://github.com/llvm/llvm-project/pull/159883.diff
8 Files Affected:
- (modified) llvm/include/llvm/MC/MCInstrDesc.h (+1-12)
- (modified) llvm/include/llvm/Target/Target.td (+13-13)
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (-4)
- (modified) llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp (+1-1)
- (modified) llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (+1-12)
- (modified) llvm/utils/TableGen/Common/InstructionEncoding.cpp (-3)
- (modified) llvm/utils/TableGen/DAGISelMatcherGen.cpp (-1)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+1-5)
``diff
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h
b/llvm/include/llvm/MC/MCInstrDesc.h
index 0a4bd17e20738..fd637f956592b 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -49,8 +49,7 @@ enum OperandConstraint {
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
- LookupPtrRegClass = 0,
- LookupRegClassByHwMode,
+ LookupRegClassByHwMode = 0,
Predicate,
OptionalDef,
BranchTarget
@@ -90,9 +89,6 @@ class MCOperandInfo {
/// operand is a register. If LookupRegClassByHwMode is set, then this is an
/// index into a table in TargetInstrInfo or MCInstrInfo which contains the
/// real register class ID.
- ///
- /// If isLookupPtrRegClass is set, then this is an index that is passed to
- /// TargetRegisterInfo::getPointerRegClass(x) to get a dynamic register
class.
int16_t RegClass;
/// These are flags from the MCOI::OperandFlags enum.
@@ -104,13 +100,6 @@ class MCOperandInfo {
/// Operand constraints (see OperandConstraint enum).
uint16_t Constraints;
- /// Set if this operand is a pointer value and it requires a callback
- /// to look up its register class.
- // TODO: Deprecated in favor of isLookupRegClassByHwMode
- bool isLookupPtrRegClass() const {
-return Flags & (1 << MCOI::LookupPtrRegClass);
- }
-
/// Set if this operand is a value that requires the current hwmode to look
up
/// its register class.
bool isLookupRegClassByHwMode() const {
diff --git a/llvm/include/llvm/Target/Target.td
b/llvm/include/llvm/Target/Target.td
index 4a759a99d1d25..7cbf131640917 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regclass to use by using
-/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
-///
-/// This is deprecated in favor of RegClassByHwMode.
+/// PointerLikeRegClass - Pseudoinstruction operands that are designed
+/// to have pointer width are derived from this. This should only be
+/// used by StandardPseudoInstruction instructions. No target specific
+/// instruction should use this.
class PointerLikeRegClass {
int RegClassKind = Kind;
}
+/// ptr_rc definition - Mark this operand as being a pointer value
+/// whose register class needs to be defined by the target. Targets
+/// should provide instruction definition overrides which substitute
+/// the uses of this with the backend defined RegisterClass or
+/// RegClassByHwMode to use for pointer virtual registers for a
+/// particular opcode (typically by defining a subsitute instruction
+/// with RemapPointerOperands).
+def ptr_rc : PointerLikeRegClass<0>;
+
/// RegClassByHwMode - Operands that change the register class based
/// on the subtarget are derived from this. TableGen
/// treats the register class as having a symbolic kind that it
@@ -941,13 +948,6 @@ class RegClassByHwMode Modes,
list Objects = RegClasses;
}
-/// ptr_rc definition - Mark this operand as being a pointer value whose
-/// register class is resolved dynamically via a callback to TargetInstrInfo.
-/// FIXME: We should probably change this to a class which contain a list of
-/// flags. But currently we have but one flag.
-// Deprecated, use RegClassByHwMode instead.
-def ptr_rc : PointerLikeRegClass<0>;
-
/// unknown definition - Mark this operand as being of unknown type, causing
/// it to be resolved by inference in the context it is used.
class unknown_class;
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp
b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 5be89b49fb6ba..761e6ed213d95 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -67,10 +67,6 @@ TargetInstrInfo::getRegClass(const MCInstrDesc &MCID,
unsigned OpNum,
const MCOperandInfo &OpInfo = MCID.operands()[
[llvm-branch-commits] [llvm] CodeGen: Make target overrides of PointerLikeRegClass mandatory (PR #159882)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/159882 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/159883 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Make target overrides of PointerLikeRegClass mandatory (PR #159882)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159882?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#159883** https://app.graphite.dev/github/pr/llvm/llvm-project/159883?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#159882** https://app.graphite.dev/github/pr/llvm/llvm-project/159882?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/159882?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#159881** https://app.graphite.dev/github/pr/llvm/llvm-project/159881?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#159880** https://app.graphite.dev/github/pr/llvm/llvm-project/159880?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#158272** https://app.graphite.dev/github/pr/llvm/llvm-project/158272?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 1 other dependent PR ([#158278](https://github.com/llvm/llvm-project/pull/158278) https://app.graphite.dev/github/pr/llvm/llvm-project/158278?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * **#158269** https://app.graphite.dev/github/pr/llvm/llvm-project/158269?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 4 other dependent PRs ([#158271](https://github.com/llvm/llvm-project/pull/158271) https://app.graphite.dev/github/pr/llvm/llvm-project/158271?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>, [#158273](https://github.com/llvm/llvm-project/pull/158273) https://app.graphite.dev/github/pr/llvm/llvm-project/158273?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>, [#158274](https://github.com/llvm/llvm-project/pull/158274) https://app.graphite.dev/github/pr/llvm/llvm-project/158274?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> and 1 other) * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/159882 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] TableGen: Support target specialized pseudoinstructions (PR #159880)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/159880
Allow a target to steal the definition of a generic pseudoinstruction
and remap the operands. This works by defining a new instruction, which
will simply swap out the emitted entry in the InstrInfo table.
This is intended to eliminate the C++ half of the implementation
of PointerLikeRegClass. With RegClassByHwMode, the remaining usecase
for PointerLikeRegClass are the common codegen pseudoinstructions.
Every target maintains its own copy of the generic pseudo operand
definitions anyway, so we can stub out the register operands with
an appropriate class instead of waiting for runtime resolution.
In the future we could probably take this a bit further. For example,
there is a similar problem for ADJCALLSTACKUP/DOWN since they depend
on target register definitions for the stack pointer register.
>From 8f62ad4e96a0976f19f7337cf7326fd95edcc41c Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 15 Sep 2025 22:41:07 +0900
Subject: [PATCH] TableGen: Support target specialized pseudoinstructions
Allow a target to steal the definition of a generic pseudoinstruction
and remap the operands. This works by defining a new instruction, which
will simply swap out the emitted entry in the InstrInfo table.
This is intended to eliminate the C++ half of the implementation
of PointerLikeRegClass. With RegClassByHwMode, the remaining usecase
for PointerLikeRegClass are the common codegen pseudoinstructions.
Every target maintains its own copy of the generic pseudo operand
definitions anyway, so we can stub out the register operands with
an appropriate class instead of waiting for runtime resolution.
In the future we could probably take this a bit further. For example,
there is a similar problem for ADJCALLSTACKUP/DOWN since they depend
on target register definitions for the stack pointer register.
---
llvm/include/llvm/Target/Target.td| 93
.../TableGen/target-specialized-pseudos.td| 101 ++
llvm/utils/TableGen/Common/CodeGenTarget.cpp | 13 ++-
llvm/utils/TableGen/InstrInfoEmitter.cpp | 37 +++
4 files changed, 243 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/TableGen/target-specialized-pseudos.td
diff --git a/llvm/include/llvm/Target/Target.td
b/llvm/include/llvm/Target/Target.td
index 13175177edd3e..4a759a99d1d25 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1574,6 +1574,99 @@ def CONVERGENCECTRL_GLUE : StandardPseudoInstruction {
}
}
+/// Allow a target to replace the instruction definition of a
+/// StandardPseudoInstruction. A target should only define one
+/// instance of this per instruction.
+///
+/// This is intended to allow targets to specify the register class
+/// used for pointers. It should not be used to change the fundamental
+/// operand structure (e.g., this should not add or remove operands,
+/// or change the operand types).
+class TargetSpecializedStandardPseudoInstruction<
+ StandardPseudoInstruction base_inst> : Instruction {
+
+ StandardPseudoInstruction Instruction = base_inst;
+ let OutOperandList = base_inst.OutOperandList;
+ let InOperandList = base_inst.InOperandList;
+
+ // TODO: Copy everything
+ let usesCustomInserter = base_inst.usesCustomInserter;
+ let hasSideEffects = base_inst.hasSideEffects;
+ let mayLoad = base_inst.mayLoad;
+ let mayStore = base_inst.mayStore;
+ let isTerminator = base_inst.isTerminator;
+ let isBranch = base_inst.isBranch;
+ let isIndirectBranch = base_inst.isIndirectBranch;
+ let isEHScopeReturn = base_inst.isEHScopeReturn;
+ let isReturn = base_inst.isReturn;
+ let isCall = base_inst.isCall;
+ let hasCtrlDep = base_inst.hasCtrlDep;
+ let isReMaterializable = base_inst.isReMaterializable;
+ let isMeta = base_inst.isMeta;
+ let Size = base_inst.Size;
+ let isAsCheapAsAMove = base_inst.isAsCheapAsAMove;
+ let isPseudo = true;
+ let hasNoSchedulingInfo = true;
+ let isNotDuplicable = base_inst.isNotDuplicable;
+ let isConvergent = base_inst.isConvergent;
+ let hasExtraSrcRegAllocReq = base_inst.hasExtraSrcRegAllocReq;
+ let hasExtraDefRegAllocReq = base_inst.hasExtraDefRegAllocReq;
+}
+
+// All pseudo instructions which need a pointer register class, which
+// should be specialized by a target.
+defvar PseudosWithPtrOps = [
+ LOAD_STACK_GUARD,
+ PREALLOCATED_ARG,
+ PATCHABLE_EVENT_CALL,
+ PATCHABLE_TYPED_EVENT_CALL
+];
+
+
+/// Replace PointerLikeRegClass operands in OperandList with new_rc.
+class RemapPointerOperandList {
+ // Collect the set of names so we can query and rewrite them.
+ list op_names = !foreach(i, !range(!size(OperandList)),
+ !getdagname(OperandList, i));
+
+ // Beautiful language. This would be a lot easier if !getdagarg
+ // didn't require a specific type. We can't just collect a list of
+ // the operand values and reconstruct the dag, since there isn't a
[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
---
Full diff: https://github.com/llvm/llvm-project/pull/159883.diff
8 Files Affected:
- (modified) llvm/include/llvm/MC/MCInstrDesc.h (+1-12)
- (modified) llvm/include/llvm/Target/Target.td (+13-13)
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (-4)
- (modified) llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp (+1-1)
- (modified) llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (+1-12)
- (modified) llvm/utils/TableGen/Common/InstructionEncoding.cpp (-3)
- (modified) llvm/utils/TableGen/DAGISelMatcherGen.cpp (-1)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+1-5)
``diff
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h
b/llvm/include/llvm/MC/MCInstrDesc.h
index 0a4bd17e20738..fd637f956592b 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -49,8 +49,7 @@ enum OperandConstraint {
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
- LookupPtrRegClass = 0,
- LookupRegClassByHwMode,
+ LookupRegClassByHwMode = 0,
Predicate,
OptionalDef,
BranchTarget
@@ -90,9 +89,6 @@ class MCOperandInfo {
/// operand is a register. If LookupRegClassByHwMode is set, then this is an
/// index into a table in TargetInstrInfo or MCInstrInfo which contains the
/// real register class ID.
- ///
- /// If isLookupPtrRegClass is set, then this is an index that is passed to
- /// TargetRegisterInfo::getPointerRegClass(x) to get a dynamic register
class.
int16_t RegClass;
/// These are flags from the MCOI::OperandFlags enum.
@@ -104,13 +100,6 @@ class MCOperandInfo {
/// Operand constraints (see OperandConstraint enum).
uint16_t Constraints;
- /// Set if this operand is a pointer value and it requires a callback
- /// to look up its register class.
- // TODO: Deprecated in favor of isLookupRegClassByHwMode
- bool isLookupPtrRegClass() const {
-return Flags & (1 << MCOI::LookupPtrRegClass);
- }
-
/// Set if this operand is a value that requires the current hwmode to look
up
/// its register class.
bool isLookupRegClassByHwMode() const {
diff --git a/llvm/include/llvm/Target/Target.td
b/llvm/include/llvm/Target/Target.td
index 4a759a99d1d25..7cbf131640917 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regclass to use by using
-/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
-///
-/// This is deprecated in favor of RegClassByHwMode.
+/// PointerLikeRegClass - Pseudoinstruction operands that are designed
+/// to have pointer width are derived from this. This should only be
+/// used by StandardPseudoInstruction instructions. No target specific
+/// instruction should use this.
class PointerLikeRegClass {
int RegClassKind = Kind;
}
+/// ptr_rc definition - Mark this operand as being a pointer value
+/// whose register class needs to be defined by the target. Targets
+/// should provide instruction definition overrides which substitute
+/// the uses of this with the backend defined RegisterClass or
+/// RegClassByHwMode to use for pointer virtual registers for a
+/// particular opcode (typically by defining a subsitute instruction
+/// with RemapPointerOperands).
+def ptr_rc : PointerLikeRegClass<0>;
+
/// RegClassByHwMode - Operands that change the register class based
/// on the subtarget are derived from this. TableGen
/// treats the register class as having a symbolic kind that it
@@ -941,13 +948,6 @@ class RegClassByHwMode Modes,
list Objects = RegClasses;
}
-/// ptr_rc definition - Mark this operand as being a pointer value whose
-/// register class is resolved dynamically via a callback to TargetInstrInfo.
-/// FIXME: We should probably change this to a class which contain a list of
-/// flags. But currently we have but one flag.
-// Deprecated, use RegClassByHwMode instead.
-def ptr_rc : PointerLikeRegClass<0>;
-
/// unknown definition - Mark this operand as being of unknown type, causing
/// it to be resolved by inference in the context it is used.
class unknown_class;
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp
b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 5be89b49fb6ba..761e6ed213d95 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -67,10 +67,6 @@ TargetInstrInfo::getRegClass(const MCInstrDesc &MCID,
unsigned OpNum,
const MCOperandInfo &OpInfo = MCID.operands()[O
[llvm-branch-commits] [llvm] TableGen: Support target specialized pseudoinstructions (PR #159880)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/159880 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regclass to use by using
-/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
-///
-/// This is deprecated in favor of RegClassByHwMode.
+/// PointerLikeRegClass - Pseudoinstruction operands that are designed
+/// to have pointer width are derived from this. This should only be
+/// used by StandardPseudoInstruction instructions. No target specific
+/// instruction should use this.
class PointerLikeRegClass {
int RegClassKind = Kind;
}
+/// ptr_rc definition - Mark this operand as being a pointer value
+/// whose register class needs to be defined by the target. Targets
+/// should provide instruction definition overrides which substitute
+/// the uses of this with the backend defined RegisterClass or
+/// RegClassByHwMode to use for pointer virtual registers for a
+/// particular opcode (typically by defining a subsitute instruction
+/// with RemapPointerOperands).
+def ptr_rc : PointerLikeRegClass<0>;
s-barannikov wrote:
What's the semantics if a target doesn't provide the overrides?
https://github.com/llvm/llvm-project/pull/159883
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[llvm-branch-commits] [llvm] [LoopUnroll] Fix block frequencies when no runtime (PR #157754)
@@ -1,4 +1,5 @@ ; RUN: opt < %s -S -passes=loop-unroll -unroll-runtime=true -unroll-count=4 | FileCheck %s +; XFAIL: * arsenm wrote: No xfailing tests? https://github.com/llvm/llvm-project/pull/157754 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Prepare libcxx and libcxxabi for pointer field protection. (PR #151651)
@@ -109,4 +109,14 @@ # define _LIBCXXABI_NOEXCEPT noexcept #endif +#if defined(_LIBCXXABI_COMPILER_CLANG) +# if defined(__POINTER_FIELD_PROTECTION__) +#define _LIBCXXABI_NO_PFP [[clang::no_field_protection]] +# else +#define _LIBCXXABI_NO_PFP +# endif +#else +# define _LIBCXXABI_NO_PFP +#endif philnik777 wrote: Why is this different from the libc++ version? https://github.com/llvm/llvm-project/pull/151651 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156840
>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types
Created using spr 1.3.8-beta.1
---
clang/lib/CodeGen/CGExpr.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 288b41bc42203..455de644daf00 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1289,6 +1289,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
// Check if QualType contains a pointer. Implements a simple DFS to
// recursively check if a type contains a pointer type.
llvm::SmallPtrSet VisitedRD;
+ bool IncompleteType = false;
auto TypeContainsPtr = [&](auto &&self, QualType T) -> bool {
QualType CanonicalType = T.getCanonicalType();
if (CanonicalType->isPointerType())
@@ -1312,6 +1313,10 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
return self(self, AT->getElementType());
// The type is a struct, class, or union.
if (const RecordDecl *RD = CanonicalType->getAsRecordDecl()) {
+ if (!RD->isCompleteDefinition()) {
+IncompleteType = true;
+return false;
+ }
if (!VisitedRD.insert(RD).second)
return false; // already visited
// Check all fields.
@@ -1333,6 +1338,8 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
return false;
};
const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
+ if (!ContainsPtr && IncompleteType)
+return nullptr;
auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
>From 7f706618ddc40375d4085bc2ebe03f02ec78823a Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:58:01 +0200
Subject: [PATCH 2/2] fixup!
Created using spr 1.3.8-beta.1
---
clang/lib/CodeGen/CGExpr.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 455de644daf00..e7a0e7696e204 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1339,7 +1339,7 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
};
const bool ContainsPtr = TypeContainsPtr(TypeContainsPtr, AllocType);
if (!ContainsPtr && IncompleteType)
-return nullptr;
+return;
auto *ContainsPtrC = Builder.getInt1(ContainsPtr);
auto *ContainsPtrMD = MDB.createConstant(ContainsPtrC);
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[llvm-branch-commits] [llvm] [AllocToken, Clang] Implement __builtin_infer_alloc_token() and llvm.alloc.token.id (PR #156842)
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156842
>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!
Created using spr 1.3.8-beta.1
---
llvm/lib/Transforms/Instrumentation/AllocToken.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
index d5ac3035df71b..3a28705d87523 100644
--- a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
@@ -151,7 +151,8 @@ STATISTIC(NumAllocations, "Allocations found");
/// Expected format is: !{, }
MDNode *getAllocTokenHintMetadata(const CallBase &CB) {
MDNode *Ret = nullptr;
- if (auto *II = dyn_cast(&CB)) {
+ if (auto *II = dyn_cast(&CB);
+ II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
auto *MDV = cast(II->getArgOperand(0));
Ret = cast(MDV->getMetadata());
// If the intrinsic has an empty MDNode, type inference failed.
@@ -358,7 +359,7 @@ bool AllocToken::instrumentFunction(Function &F) {
// Collect all allocation calls to avoid iterator invalidation.
for (Instruction &I : instructions(F)) {
// Collect all alloc_token_* intrinsics.
-if (IntrinsicInst *II = dyn_cast(&I);
+if (auto *II = dyn_cast(&I);
II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
IntrinsicInsts.emplace_back(II);
continue;
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[llvm-branch-commits] [llvm] [AllocToken, Clang] Implement __builtin_infer_alloc_token() and llvm.alloc.token.id (PR #156842)
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156842
>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!
Created using spr 1.3.8-beta.1
---
llvm/lib/Transforms/Instrumentation/AllocToken.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
index d5ac3035df71b..3a28705d87523 100644
--- a/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AllocToken.cpp
@@ -151,7 +151,8 @@ STATISTIC(NumAllocations, "Allocations found");
/// Expected format is: !{, }
MDNode *getAllocTokenHintMetadata(const CallBase &CB) {
MDNode *Ret = nullptr;
- if (auto *II = dyn_cast(&CB)) {
+ if (auto *II = dyn_cast(&CB);
+ II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
auto *MDV = cast(II->getArgOperand(0));
Ret = cast(MDV->getMetadata());
// If the intrinsic has an empty MDNode, type inference failed.
@@ -358,7 +359,7 @@ bool AllocToken::instrumentFunction(Function &F) {
// Collect all allocation calls to avoid iterator invalidation.
for (Instruction &I : instructions(F)) {
// Collect all alloc_token_* intrinsics.
-if (IntrinsicInst *II = dyn_cast(&I);
+if (auto *II = dyn_cast(&I);
II && II->getIntrinsicID() == Intrinsic::alloc_token_id) {
IntrinsicInsts.emplace_back(II);
continue;
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[llvm-branch-commits] [clang] [HLSL] NonUniformResourceIndex implementation (PR #159655)
https://github.com/damyanp commented: Is there value in testing cases where `NonUniformResourceIndex` is used in odd places? eg https://godbolt.org/z/jrdc1ErMM https://github.com/llvm/llvm-project/pull/159655 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64] Split large loop dependence masks (PR #153187)
SamTebbs33 wrote: Ping. https://github.com/llvm/llvm-project/pull/153187 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)
https://github.com/melver updated https://github.com/llvm/llvm-project/pull/156841 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang-tools-extra] [compiler-rt] [libcxx] [libcxxabi] [libunwind] [lldb] [llvm] [mlir] [openmp] release/21.x: [CMake][AIX] quote the string AIX `if` conditions (PR #1565
amy-kwan wrote: > > Uhm - this looks pretty big and seems like something that can easily break > > certain build configurations since it doesn't seem to touch only AIX > > Agreed that this looks big and scary, but it's a purely mechanical change, > that is a no-op for most targets. I'll add a long form rational at the end of > the comment about why I don't think the patch effects anyone but AIX to keep > my answers brief. > > > Is this in main without any issues? > > Yes, these patches have been in main for several weeks at this point with no > reported issues. > > > Does it really NEED to be merged for the release branch at this point? > > It would help us out for the point releases. Without this patch, we're unable > to build on AIX with CMake from our package manager (4.0). We can manually > downgrade if we're unwilling to merge this, but it's a bit of a pain. > > **Rationale about why the patch doesn't affect targets besides AIX** > > We quote the string AIX and variable expansions which might expand to string > AIX (i.e. `CMAKE_SYSTEM_NAME`), so that we do the intent string comparison. > If not quoted the if will expand the string if it happens to match a variable > name (which `AIX` does in CMake 4.0+). > > This has an effect only if `CMAKE_SYSTEM_NAME` > (https://cmake.org/cmake/help/latest/variable/CMAKE_SYSTEM_NAME.html) expands > to something which is a CMake variable > (https://cmake.org/cmake/help/latest/manual/cmake-variables.7.html#variables-that-describe-the-system) > > Intersecting the two list gives me the following list of affect targets: > > ``` > AIX > CYGWIN > MSYS > WASI > ``` > > Of those targets, only CYGWIN appears in the lines affected by the patch, and > it's already using a variable check (i.e. it checks `CYGWIN`) not a string > comparison to `CMAKE_SYSTEM_NAME`, so it's unaffected. Hi @tru! Any thoughts regarding @daltenty's response on this backport? https://github.com/llvm/llvm-project/pull/156505 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SimplifyCFG] Avoid using isNonIntegralPointerType() (PR #159890)
@@ -525,28 +525,32 @@ static bool dominatesMergePoint(
static ConstantInt *getConstantInt(Value *V, const DataLayout &DL) {
// Normal constant int.
ConstantInt *CI = dyn_cast(V);
- if (CI || !isa(V) || !V->getType()->isPointerTy() ||
- DL.isNonIntegralPointerType(V->getType()))
+ if (CI || !isa(V) || !V->getType()->isPointerTy())
return CI;
// This is some kind of pointer constant. Turn it into a pointer-sized
// ConstantInt if possible.
- IntegerType *PtrTy = cast(DL.getIntPtrType(V->getType()));
+ IntegerType *IntPtrTy = cast(DL.getIntPtrType(V->getType()));
// Null pointer means 0, see SelectionDAGBuilder::getValue(const Value*).
if (isa(V))
-return ConstantInt::get(PtrTy, 0);
+return ConstantInt::get(IntPtrTy, 0);
- // IntToPtr const int.
+ // IntToPtr const int, we can look through this unless the semantics of
+ // inttoptr for this address space aren't a simple bitcast.
+ // TODO: should this be relaxed to hasUnstableRepresentation? The
+ // transformation made here should also be safe for CHERI.
+ if (DL.shouldAvoidIntToPtr(V->getType()))
arsenm wrote:
I don't love the "shouldAvoidIntToPtr" name but that exists already. The name
should express the property, not a behavior to avoid
https://github.com/llvm/llvm-project/pull/159890
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[llvm-branch-commits] [llvm] [SimplifyCFG] Avoid using isNonIntegralPointerType() (PR #159890)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/159890 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] TableGen: Support target specialized pseudoinstructions (PR #159880)
arsenm wrote: That might work, but that also is more limiting. In particular that doesn't allow you to set implicit uses / defs like you would want for adjcallstack pseudos https://github.com/llvm/llvm-project/pull/159880 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
