[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 54a58aba634a49079976dd9733a320b522f483aa Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
These instructions can now be fully decoded automatically.
---
llvm/lib/Target/Hexagon/CMakeLists.txt| 3 +-
.../Disassembler/HexagonDisassembler.cpp | 65 ++---
.../Target/Hexagon/HexagonDepInstrFormats.td | 129 --
llvm/lib/Target/Hexagon/HexagonOperands.td| 10 +-
4 files changed, 49 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt
b/llvm/lib/Target/Hexagon/CMakeLists.txt
index b615536af03be..d758260a8ab5d 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de10092cbe3c8..0639878c1256f 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -173,6 +173,19 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned
tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);
+
+static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MCContext &Ctx = Decoder->getContext();
+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
+ return DecodeStatus::Success;
+}
+
+static DecodeStatus sgp10ConstDecoder(MCInst &MI,
+ const MCDisassembler *Decoder) {
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ return DecodeStatus::Success;
+}
+
#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"
@@ -349,21 +362,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr)
const {
}
}
-static void adjustDuplex(MCInst &MI, MCContext &Context) {
- switch (MI.getOpcode()) {
- case Hexagon::SA1_setin1:
-MI.insert(MI.begin() + 1,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- case Hexagon::SA1_dec:
-MI.insert(MI.begin() + 2,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- default:
-break;
- }
-}
-
DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef Bytes,
uint64_t Address,
@@ -468,12 +466,10 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
@@ -499,41 +495,6 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
}
- switch (MI.getOpcode()) {
- case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_f_jumpnv_t:
- case Hexagon::J4_cmpeqn1_fp0_jump_nt:
- case Hexagon::J4_cmpeqn1_fp0_jump_t:
- case Hexagon::J4_cmpeqn1_fp1_jump_nt:
- case Hexagon::J4_cmpeqn1_fp1_jump_t:
- case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_t_jumpnv_t:
- case Hexagon::J4_cmpeqn1_tp0_jump_nt:
- case Hexagon::J4_cmpeqn1_tp0_jump_t:
- case Hexagon::J4_cmpeqn1_tp1_jump_nt:
- case Hexagon::J4_cmpeqn1_tp1_jump_t:
- case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_f_jumpnv_t:
- case Hexagon::J4_cmpgtn1_fp0_jump_nt:
- case Hexagon::J4_cmpgtn1_fp0_jump_t:
- case Hexagon::J4_cmpgtn1_fp1_jump_nt:
- case Hexagon::J4_cmpgtn1_fp1_jump_t:
- case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_t_jumpnv_t:
- case Hexagon::J4_cmpgtn1_tp0_jump_nt:
[llvm-branch-commits] [llvm] AMDGPU: Add agpr versions of global return atomics (PR #156890)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Incremental step towards removing the special case hack
in TargetInstrInfo::getRegClass.
---
Full diff: https://github.com/llvm/llvm-project/pull/156890.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/DSInstructions.td (+4-20)
- (modified) llvm/lib/Target/AMDGPU/FLATInstructions.td (+39-2)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.td (+24)
``diff
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index bec920380e081..f2e432fa8d7f5 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -51,22 +51,6 @@ class DS_Pseudo patt
let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
}
-class DstOperandIsAV {
- bit ret = OperandIsAV(OperandList, "vdst")>.ret;
-}
-
-class DstOperandIsAGPR {
- bit ret = OperandIsAGPR(OperandList, "vdst")>.ret;
-}
-
-class DataOperandIsAV {
- bit ret = OperandIsAV(OperandList, "data0")>.ret;
-}
-
-class DataOperandIsAGPR {
- bit ret = OperandIsAGPR(OperandList, "data0")>.ret;
-}
-
class DS_Real :
InstSI ,
Enc64 {
@@ -115,13 +99,13 @@ class DS_Real :
// register fields are only 8-bit, so data operands must all be AGPR
// or VGPR.
defvar DstOpIsAV = !if(ps.has_vdst,
- DstOperandIsAV.ret, 0);
+ VDstOperandIsAV.ret, 0);
defvar DstOpIsAGPR = !if(ps.has_vdst,
- DstOperandIsAGPR.ret, 0);
+ VDstOperandIsAGPR.ret, 0);
defvar DataOpIsAV = !if(!or(ps.has_data0, ps.has_gws_data0),
- DataOperandIsAV.ret, 0);
+ Data0OperandIsAV.ret, 0);
defvar DataOpIsAGPR = !if(!or(ps.has_data0, ps.has_gws_data0),
-DataOperandIsAGPR.ret, 0);
+Data0OperandIsAGPR.ret, 0);
bits<1> acc = !if(ps.has_vdst,
!if(DstOpIsAV, vdst{9}, DstOpIsAGPR),
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td
b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 0ac5f3d50f1b5..fd7c9a741c301 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -137,7 +137,18 @@ class FLAT_Real op, FLAT_Pseudo ps, string opName
= ps.Mnemonic> :
// unsigned for flat accesses.
bits<13> offset;
// GFX90A+ only: instruction uses AccVGPR for data
- bits<1> acc = !if(ps.has_vdst, vdst{9}, !if(ps.has_data, vdata{9}, 0));
+ defvar DstOpIsAV = !if(ps.has_vdst,
+ VDstOperandIsAV.ret, 0);
+ defvar DstOpIsAGPR = !if(ps.has_vdst,
+ VDstOperandIsAGPR.ret, 0);
+ defvar DataOpIsAV = !if(ps.has_data,
+ VDataOperandIsAV.ret, 0);
+ defvar DataOpIsAGPR = !if(ps.has_data,
+VDataOperandIsAGPR.ret, 0);
+
+ bits<1> acc = !if(ps.has_vdst,
+!if(DstOpIsAV, vdst{9}, DstOpIsAGPR),
+!if(DataOpIsAV, vdata{9}, DataOpIsAGPR));
// We don't use tfe right now, and it was removed in gfx9.
bits<1> tfe = 0;
@@ -860,6 +871,30 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
let enabled_saddr = 1;
let FPAtomic = data_vt.isFP;
}
+
+defvar vdst_op_agpr = getEquivalentAGPROperand.ret;
+defvar data_op_agpr = getEquivalentAGPROperand.ret;
+
+let SubtargetPredicate = isGFX90APlus in {
+ def _RTN_agpr : FLAT_AtomicRet_Pseudo ,
+GlobalSaddrTable<0, opName#"_rtn_agpr"> {
+let has_saddr = 1;
+let FPAtomic = data_vt.isFP;
+ }
+
+ def _SADDR_RTN_agpr : FLAT_AtomicRet_Pseudo ,
+GlobalSaddrTable<1, opName#"_rtn_agpr"> {
+ let has_saddr = 1;
+ let enabled_saddr = 1;
+ let FPAtomic = data_vt.isFP;
+ }
+}
}
}
@@ -2637,8 +2672,10 @@ multiclass FLAT_Global_Real_Atomics_vi op,
FLAT_Real_AllAddr_vi {
def _RTN_vi : FLAT_Real_vi (NAME#"_RTN"), has_sccb>;
def _SADDR_RTN_vi : FLAT_Real_vi (NAME#"_SADDR_RTN"),
has_sccb>;
-}
+ def _RTN_agpr_vi : FLAT_Real_vi (NAME#"_RTN_agpr"),
has_sccb>;
+ def _SADDR_RTN_agpr_vi : FLAT_Real_vi (NAME#"_SADDR_RTN_agpr"), has_sccb>;
+}
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40>;
defm FLAT_ATOMIC_CMPSWAP: FLAT_Real_Atomics_vi <0x41>;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 8c2bd3d3962ce..d9746a17e75eb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1492,3 +1492,27 @@ class OperandIsVGPR {
defvar reg_class = getRegClassFromOp.ret;
bit ret = !and(reg_class.HasVGPR, !not(reg_class.HasAGPR));
}
+
+class VDstOperandIsAV {
+ bit ret = OperandIsAV(OperandList, "vdst")>.ret;
+}
+
+class VDstOperandIsAGPR {
+ bit ret = OperandIsAGPR(OperandList, "vdst")>.ret;
+}
+
+class Data0OperandIsAV {
+ bit ret = OperandI
[llvm-branch-commits] [llvm] X86: Stop using MachineFunction in getPointerRegClass (PR #156880)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156880
This should be a low level function used to interpret an
MCInstrDesc that only depends on the hwmode. It should not depend
on other dynamic context like the parent function. In general more
ABI properties like this should be expressed directly in the instruction
definitions, so introduce new TCRETURN pseudos to use with the special
case register classes (e.g. in a better future the callee saved registers
would always be encoded directly in a mask on the return instruction).
This will help unify X86 onto a pending replacement mechanism for
getPointerRegClass.
>From 3fe72b6bcfa87e1734c92f52a69c7cf372162a3b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 14:44:56 +0900
Subject: [PATCH] X86: Stop using MachineFunction in getPointerRegClass
This should be a low level function used to interpret an
MCInstrDesc that only depends on the hwmode. It should not depend
on other dynamic context like the parent function. In general more
ABI properties like this should be expressed directly in the instruction
definitions, so introduce new TCRETURN pseudos to use with the special
case register classes (e.g. in a better future the callee saved registers
would always be encoded directly in a mask on the return instruction).
This will help unify X86 onto a pending replacement mechanism for
getPointerRegClass.
---
llvm/lib/Target/X86/X86AsmPrinter.cpp | 3 ++-
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 7 +--
llvm/lib/Target/X86/X86FrameLowering.cpp | 3 ++-
llvm/lib/Target/X86/X86InstrCompiler.td | 10 +-
llvm/lib/Target/X86/X86InstrControl.td| 6 ++
llvm/lib/Target/X86/X86InstrPredicates.td | 6 ++
llvm/lib/Target/X86/X86RegisterInfo.cpp | 18 +++---
llvm/lib/Target/X86/X86RegisterInfo.h | 5 -
8 files changed, 33 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index d406277e440bb..ff22ee8c86fac 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp
@@ -476,7 +476,8 @@ static bool isIndirectBranchOrTailCall(const MachineInstr
&MI) {
return MI.getDesc().isIndirectBranch() /*Make below code in a good shape*/ ||
Opc == X86::TAILJMPr || Opc == X86::TAILJMPm ||
Opc == X86::TAILJMPr64 || Opc == X86::TAILJMPm64 ||
- Opc == X86::TCRETURNri || Opc == X86::TCRETURNmi ||
+ Opc == X86::TCRETURNri || Opc == X86::TCRETURN_WIN64ri ||
+ Opc == X86::TCRETURN_HIPE32ri || Opc == X86::TCRETURNmi ||
Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNmi64 ||
Opc == X86::TCRETURNri64_ImpCall || Opc == X86::TAILJMPr64_REX ||
Opc == X86::TAILJMPm64_REX;
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index 0e6b4dffec3a6..9457e718de699 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -269,6 +269,8 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::TCRETURNdi:
case X86::TCRETURNdicc:
case X86::TCRETURNri:
+ case X86::TCRETURN_WIN64ri:
+ case X86::TCRETURN_HIPE32ri:
case X86::TCRETURNmi:
case X86::TCRETURNdi64:
case X86::TCRETURNdi64cc:
@@ -346,8 +348,9 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
MIB.add(MBBI->getOperand(i));
-} else if ((Opcode == X86::TCRETURNri64) ||
- (Opcode == X86::TCRETURNri64_ImpCall)) {
+} else if (Opcode == X86::TCRETURNri64 ||
+ Opcode == X86::TCRETURNri64_ImpCall ||
+ Opcode == X86::TCRETURN_WIN64ri) {
JumpTarget.setIsKill();
BuildMI(MBB, MBBI, DL,
TII->get(IsX64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp
b/llvm/lib/Target/X86/X86FrameLowering.cpp
index cba7843d53e3f..a293b4c87cfe4 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -2398,7 +2398,8 @@ X86FrameLowering::getWinEHFuncletFrameSize(const
MachineFunction &MF) const {
}
static bool isTailCallOpcode(unsigned Opc) {
- return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
+ return Opc == X86::TCRETURNri || Opc == X86::TCRETURN_WIN64ri ||
+ Opc == X86::TCRETURN_HIPE32ri || Opc == X86::TCRETURNdi ||
Opc == X86::TCRETURNmi || Opc == X86::TCRETURNri64 ||
Opc == X86::TCRETURNri64_ImpCall || Opc == X86::TCRETURNdi64 ||
Opc == X86::TCRETURNmi64;
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td
b/llvm/lib/Target/X86/X86InstrCompiler.td
index 927b2c8b22f05..734c488fe3159 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -1326,7 +1326,11 @@ def : P
[llvm-branch-commits] [llvm] AMDGPU: Change FLAT classes to use RegisterOperand parameters (PR #156581)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From a09ada3d217bcf5728f32d7a16c334fb0330e617 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
This will make it easier to precisely express operand constraints
without having the implicit getLdStRegisterOperand at the bottom.
Also prunes out using AV classes in some instructions where AGPRs
are not relevant.
---
llvm/lib/Target/AMDGPU/FLATInstructions.td | 421 ++---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 2 +-
2 files changed, 208 insertions(+), 215 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td
b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index dcb4f506dfbd2..69aef421bba45 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -216,11 +216,10 @@ class GlobalSaddrTable {
// same encoding value as exec_hi, so it isn't possible to use that if
// saddr is 32-bit (which isn't handled here yet).
class FLAT_Load_Pseudo<
-string opName, RegisterClass regClass, bit HasTiedOutput = 0,
+string opName, RegisterOperand vdata_op, bit HasTiedOutput = 0,
bit HasSaddr = 0, bit EnableSaddr = 0>
: FLAT_Pseudo {
- defvar vdata_op = getLdStRegisterOperand.ret;
let OutOperandList = (outs vdata_op:$vdst);
let InOperandList = !con(
!if(EnableSaddr,
@@ -243,7 +242,7 @@ class FLAT_Load_Pseudo<
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
}
-multiclass FLAT_Flat_Load_Pseudo {
+multiclass FLAT_Flat_Load_Pseudo {
def "" : FLAT_Load_Pseudo,
GlobalSaddrTable<0, opName>;
let OtherPredicates = [HasFlatGVSMode] in
@@ -252,19 +251,19 @@ multiclass FLAT_Flat_Load_Pseudo {
- defm "" : FLAT_Flat_Load_Pseudo;
+ defm "" : FLAT_Flat_Load_Pseudo;
let True16Predicate = UseRealTrue16Insts in
-defm _t16 : FLAT_Flat_Load_Pseudo,
True16D16Table;
+defm _t16 : FLAT_Flat_Load_Pseudo,
True16D16Table;
}
-class FLAT_Store_Pseudo : FLAT_Pseudo<
opName,
(outs),
!con(
!if(EnableSaddr,
- (ins VGPR_32:$vaddr, getLdStRegisterOperand.ret:$vdata,
SReg_64_XEXEC_XNULL:$saddr),
- (ins VReg_64:$vaddr, getLdStRegisterOperand.ret:$vdata)),
+ (ins VGPR_32:$vaddr, vdataClass:$vdata, SReg_64_XEXEC_XNULL:$saddr),
+ (ins VReg_64:$vaddr, vdataClass:$vdata)),
(ins flat_offset:$offset, CPol_0:$cpol)),
" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"),
"")#"$offset$cpol"> {
let mayLoad = 0;
@@ -274,7 +273,7 @@ class FLAT_Store_Pseudo {
+multiclass FLAT_Flat_Store_Pseudo {
def "" : FLAT_Store_Pseudo,
GlobalSaddrTable<0, opName>;
let OtherPredicates = [HasFlatGVSMode] in
@@ -283,20 +282,21 @@ multiclass FLAT_Flat_Store_Pseudo {
}
multiclass FLAT_Flat_Store_Pseudo_t16 {
- defm "" : FLAT_Flat_Store_Pseudo;
+ defm "" : FLAT_Flat_Store_Pseudo;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasFlatGVSMode, HasTrue16BitInsts] in {
-def _t16 : FLAT_Store_Pseudo,
+def _t16 : FLAT_Store_Pseudo,
GlobalSaddrTable<0, Name16>,
True16D16Table;
- def _SADDR_t16 : FLAT_Store_Pseudo,
+ def _SADDR_t16 : FLAT_Store_Pseudo,
GlobalSaddrTable<1, Name16>,
True16D16Table;
}
}
-multiclass FLAT_Global_Load_Pseudo {
+multiclass FLAT_Global_Load_Pseudo {
let is_flat_global = 1 in {
def "" : FLAT_Load_Pseudo,
GlobalSaddrTable<0, opName>;
@@ -306,21 +306,21 @@ multiclass FLAT_Global_Load_Pseudo {
- defm "" : FLAT_Global_Load_Pseudo;
+ defm "" : FLAT_Global_Load_Pseudo;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts],
SubtargetPredicate = HasFlatGlobalInsts, is_flat_global = 1 in {
-def _t16 : FLAT_Load_Pseudo,
+def _t16 : FLAT_Load_Pseudo,
GlobalSaddrTable<0, Name16>,
True16D16Table;
-def _SADDR_t16 : FLAT_Load_Pseudo,
+def _SADDR_t16 : FLAT_Load_Pseudo,
GlobalSaddrTable<1, Name16>,
True16D16Table;
}
}
-class FLAT_Global_Load_AddTid_Pseudo : FLAT_Pseudo<
opName,
(outs regClass:$vdst),
@@ -338,7 +338,7 @@ class FLAT_Global_Load_AddTid_Pseudo {
def "" : FLAT_Global_Load_AddTid_Pseudo,
GlobalSaddrTable<0, opName>;
@@ -346,7 +346,7 @@ multiclass FLAT_Global_Load_AddTid_Pseudo;
}
-multiclass FLAT_Global_Store_Pseudo {
+multiclass FLAT_Global_Store_Pseudo {
let is_flat_global = 1 in {
def "" : FLAT_Store_Pseudo,
GlobalSaddrTable<0, opName>;
@@ -356,15 +356,15 @@ multiclass FLAT_Global_Store_Pseudo {
}
multiclass FLAT_Global_Store_Pseudo_t16 {
- defm "" : FLAT_Global_Store_Pseudo;
+ defm "" : FLAT_Global_Store_Pseudo;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts],
SubtargetPredicate = HasFlatGlobalInsts, is_flat_global = 1 in {
-def _t16 : FLAT_Store_Pseudo,
+def _t16 : FLAT_Store_Ps
[llvm-branch-commits] [clang] release/21.x: [clang][docs] Fix implicit-int-conversion-on-negation typos (PR #156815)
llvmbot wrote: @llvm/pr-subscribers-clang Author: None (correctmost) Changes References to `-Wimplicit-int-comparison-on-negation` should be `-Wimplicit-int-conversion-on-negation` instead. See: https://github.com/llvm/llvm-project/pull/139429/files#r2124372667 --- Full diff: https://github.com/llvm/llvm-project/pull/156815.diff 1 Files Affected: - (modified) clang/docs/ReleaseNotes.rst (+2-2) ``diff diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 9400be296e7c2..f03a3273c4518 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -677,8 +677,8 @@ Improvements to Clang's diagnostics trigger a ``'Blue' is deprecated`` warning, which can be turned off with ``-Wno-deprecated-declarations-switch-case``. -- Split diagnosis of implicit integer comparison on negation to a new - diagnostic group ``-Wimplicit-int-comparison-on-negation``, grouped under +- Split diagnosis of implicit integer conversion on negation to a new + diagnostic group ``-Wimplicit-int-conversion-on-negation``, grouped under ``-Wimplicit-int-conversion``, so user can turn it off independently. - Improved the FixIts for unused lambda captures. `` https://github.com/llvm/llvm-project/pull/156815 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/21.x: [clang][docs] Fix implicit-int-conversion-on-negation typos (PR #156815)
https://github.com/nikic milestoned https://github.com/llvm/llvm-project/pull/156815 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] X86: Stop using MachineFunction in getPointerRegClass (PR #156880)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/156880 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [lldb] release/21.x: [libc++] Ensure that we restore invariants in basic_filebuf::overflow (#147389) (PR #155712)
tuliom wrote: > Yeah, this should be good. We should probably also backport the AIX CI fix (I > just have to remember where it was). @philnik777 Are you looking for #156502 ? https://github.com/llvm/llvm-project/pull/155712 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] X86: Stop using MachineFunction in getPointerRegClass (PR #156880)
https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/156880 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/21.x: [libc++][AIX] Fixup problems with ABI list checking (#155643) (PR #156502)
https://github.com/philnik777 approved this pull request. https://github.com/llvm/llvm-project/pull/156502 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [lldb] release/21.x: [libc++] Ensure that we restore invariants in basic_filebuf::overflow (#147389) (PR #155712)
philnik777 wrote: > > Yeah, this should be good. We should probably also backport the AIX CI fix > > (I just have to remember where it was). > > @philnik777 Are you looking for #156502 ? Yes, thanks! https://github.com/llvm/llvm-project/pull/155712 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/21.x: [Coroutines] Restore accidentally dropped intrinsic IDs (PR #156925)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: None (llvmbot)
Changes
Backport a647bb4a7ba23b5a7c7484fd5162fef2d10c7068
Requested by: @nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/156925.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/Coroutines/Coroutines.cpp (+3)
``diff
diff --git a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
index 59ae057cae793..ac93f748ce65c 100644
--- a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
+++ b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
@@ -85,6 +85,9 @@ static Intrinsic::ID NonOverloadedCoroIntrinsics[] = {
Intrinsic::coro_id_async,
Intrinsic::coro_id_retcon,
Intrinsic::coro_id_retcon_once,
+Intrinsic::coro_noop,
+Intrinsic::coro_prepare_async,
+Intrinsic::coro_prepare_retcon,
Intrinsic::coro_promise,
Intrinsic::coro_resume,
Intrinsic::coro_save,
``
https://github.com/llvm/llvm-project/pull/156925
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[llvm-branch-commits] [llvm] release/21.x: [Coroutines] Restore accidentally dropped intrinsic IDs (PR #156925)
llvmbot wrote:
@llvm/pr-subscribers-coroutines
Author: None (llvmbot)
Changes
Backport a647bb4a7ba23b5a7c7484fd5162fef2d10c7068
Requested by: @nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/156925.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/Coroutines/Coroutines.cpp (+3)
``diff
diff --git a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
index 59ae057cae793..ac93f748ce65c 100644
--- a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
+++ b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
@@ -85,6 +85,9 @@ static Intrinsic::ID NonOverloadedCoroIntrinsics[] = {
Intrinsic::coro_id_async,
Intrinsic::coro_id_retcon,
Intrinsic::coro_id_retcon_once,
+Intrinsic::coro_noop,
+Intrinsic::coro_prepare_async,
+Intrinsic::coro_prepare_retcon,
Intrinsic::coro_promise,
Intrinsic::coro_resume,
Intrinsic::coro_save,
``
https://github.com/llvm/llvm-project/pull/156925
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[llvm-branch-commits] [llvm] release/21.x: [Coroutines] Restore accidentally dropped intrinsic IDs (PR #156925)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156925
Backport a647bb4a7ba23b5a7c7484fd5162fef2d10c7068
Requested by: @nikic
>From e11e09364d6438e66b0abb53fcd73056f10ec501 Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Thu, 24 Jul 2025 14:36:02 +0200
Subject: [PATCH] [Coroutines] Restore accidentally dropped intrinsic IDs
These were unintentionally dropped in #145518. These intrinsics
are not overloaded, so should be part of this list.
(cherry picked from commit a647bb4a7ba23b5a7c7484fd5162fef2d10c7068)
---
llvm/lib/Transforms/Coroutines/Coroutines.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
index 59ae057cae793..ac93f748ce65c 100644
--- a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
+++ b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
@@ -85,6 +85,9 @@ static Intrinsic::ID NonOverloadedCoroIntrinsics[] = {
Intrinsic::coro_id_async,
Intrinsic::coro_id_retcon,
Intrinsic::coro_id_retcon_once,
+Intrinsic::coro_noop,
+Intrinsic::coro_prepare_async,
+Intrinsic::coro_prepare_retcon,
Intrinsic::coro_promise,
Intrinsic::coro_resume,
Intrinsic::coro_save,
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[llvm-branch-commits] [clang] release/21.x: [clang][docs] Fix implicit-int-conversion-on-negation typos (PR #156815)
github-actions[bot] wrote: ⚠️ We detected that you are using a GitHub private e-mail address to contribute to the repo. Please turn off [Keep my email addresses private](https://github.com/settings/emails) setting in your account. See [LLVM Developer Policy](https://llvm.org/docs/DeveloperPolicy.html#email-addresses) and [LLVM Discourse](https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it) for more information. https://github.com/llvm/llvm-project/pull/156815 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
@@ -438,12 +452,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclStmt(const DeclStmt *DS) {
for (const Decl *D : DS->decls())
if (const auto *VD = dyn_cast(D))
-if (hasOrigin(VD->getType()))
+if (hasOrigin(VD))
if (const Expr *InitExpr = VD->getInit())
addAssignOriginFact(*VD, *InitExpr);
}
- void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) {
+handleUse(DRE);
+// For non-pointer/non-view types, a reference to the variable's storage
+// is a borrow. We create a loan for it.
+// For pointer/view types, we stick to the existing model for now and do
+// not create an extra origin for the l-value expression itself.
+
+// FIXME: A loan to `DeclRefExpr` for a pointer or view type can be
Xazax-hun wrote:
That being said, I think there is no ambiguity here. The DeclRefExpr is always
referring to the lvalue. And we should always have the LValueToRValue
conversion when we refer to the value. Handling that conversion correctly can
help us never be ambiguous.
https://github.com/llvm/llvm-project/pull/156896
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[llvm-branch-commits] [llvm] X86: Stop using MachineFunction in getPointerRegClass (PR #156880)
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Matt Arsenault (arsenm)
Changes
This should be a low level function used to interpret an
MCInstrDesc that only depends on the hwmode. It should not depend
on other dynamic context like the parent function. In general more
ABI properties like this should be expressed directly in the instruction
definitions, so introduce new TCRETURN pseudos to use with the special
case register classes (e.g. in a better future the callee saved registers
would always be encoded directly in a mask on the return instruction).
This will help unify X86 onto a pending replacement mechanism for
getPointerRegClass.
---
Full diff: https://github.com/llvm/llvm-project/pull/156880.diff
8 Files Affected:
- (modified) llvm/lib/Target/X86/X86AsmPrinter.cpp (+2-1)
- (modified) llvm/lib/Target/X86/X86ExpandPseudo.cpp (+5-2)
- (modified) llvm/lib/Target/X86/X86FrameLowering.cpp (+2-1)
- (modified) llvm/lib/Target/X86/X86InstrCompiler.td (+9-1)
- (modified) llvm/lib/Target/X86/X86InstrControl.td (+6)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (+6)
- (modified) llvm/lib/Target/X86/X86RegisterInfo.cpp (+3-15)
- (modified) llvm/lib/Target/X86/X86RegisterInfo.h (-5)
``diff
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index d406277e440bb..ff22ee8c86fac 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp
@@ -476,7 +476,8 @@ static bool isIndirectBranchOrTailCall(const MachineInstr
&MI) {
return MI.getDesc().isIndirectBranch() /*Make below code in a good shape*/ ||
Opc == X86::TAILJMPr || Opc == X86::TAILJMPm ||
Opc == X86::TAILJMPr64 || Opc == X86::TAILJMPm64 ||
- Opc == X86::TCRETURNri || Opc == X86::TCRETURNmi ||
+ Opc == X86::TCRETURNri || Opc == X86::TCRETURN_WIN64ri ||
+ Opc == X86::TCRETURN_HIPE32ri || Opc == X86::TCRETURNmi ||
Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNmi64 ||
Opc == X86::TCRETURNri64_ImpCall || Opc == X86::TAILJMPr64_REX ||
Opc == X86::TAILJMPm64_REX;
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index 0e6b4dffec3a6..9457e718de699 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -269,6 +269,8 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::TCRETURNdi:
case X86::TCRETURNdicc:
case X86::TCRETURNri:
+ case X86::TCRETURN_WIN64ri:
+ case X86::TCRETURN_HIPE32ri:
case X86::TCRETURNmi:
case X86::TCRETURNdi64:
case X86::TCRETURNdi64cc:
@@ -346,8 +348,9 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
MIB.add(MBBI->getOperand(i));
-} else if ((Opcode == X86::TCRETURNri64) ||
- (Opcode == X86::TCRETURNri64_ImpCall)) {
+} else if (Opcode == X86::TCRETURNri64 ||
+ Opcode == X86::TCRETURNri64_ImpCall ||
+ Opcode == X86::TCRETURN_WIN64ri) {
JumpTarget.setIsKill();
BuildMI(MBB, MBBI, DL,
TII->get(IsX64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp
b/llvm/lib/Target/X86/X86FrameLowering.cpp
index cba7843d53e3f..a293b4c87cfe4 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -2398,7 +2398,8 @@ X86FrameLowering::getWinEHFuncletFrameSize(const
MachineFunction &MF) const {
}
static bool isTailCallOpcode(unsigned Opc) {
- return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
+ return Opc == X86::TCRETURNri || Opc == X86::TCRETURN_WIN64ri ||
+ Opc == X86::TCRETURN_HIPE32ri || Opc == X86::TCRETURNdi ||
Opc == X86::TCRETURNmi || Opc == X86::TCRETURNri64 ||
Opc == X86::TCRETURNri64_ImpCall || Opc == X86::TCRETURNdi64 ||
Opc == X86::TCRETURNmi64;
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td
b/llvm/lib/Target/X86/X86InstrCompiler.td
index 927b2c8b22f05..734c488fe3159 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -1326,7 +1326,11 @@ def : Pat<(X86imp_call (i64 tglobaladdr:$dst)),
// Match an X86tcret that uses less than 7 volatile registers.
def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
(TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>,
- Requires<[Not64BitMode, NotUseIndirectThunkCalls]>;
+ Requires<[Not64BitMode, IsNotHiPECCFunc, NotUseIndirectThunkCalls]>;
+
+def : Pat<(X86tcret GR32:$dst, timm:$off),
+ (TCRETURN_HIPE32ri GR32:$dst, timm:$off)>,
+ Requires<[Not64BitMode, IsHiPECCFunc, NotUseIndirectThunkCalls]>;
// FIXME: This is disabled for 32-bit PIC mode because the global base
// register which is part of the address mode may be assigned a
[llvm-branch-commits] [clang] [llvm] [HLSL][DirectX] Add support for `rootsig` as a target environment (PR #156373)
@@ -1472,5 +1473,38 @@ IdentifierInfo *ParseHLSLRootSignature(Sema &Actions,
return DeclIdent;
}
+void HandleRootSignatureTarget(Sema &S, StringRef EntryRootSig) {
+ ASTConsumer *Consumer = &S.getASTConsumer();
+
+ // Minimally initalize the parser. This does a couple things:
+ // - initializes Sema scope handling
+ // - invokes HLSLExternalSemaSource
+ // - invokes the preprocessor to lex the macros in the file
+ std::unique_ptr P(new Parser(S.getPreprocessor(), S, true));
+ S.getPreprocessor().EnterMainSourceFile();
+
+ bool HaveLexer = S.getPreprocessor().getCurrentLexer();
+ if (HaveLexer) {
bogner wrote:
When can we not have a lexer? Is this the case where we try to do this without
any input file?
https://github.com/llvm/llvm-project/pull/156373
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[llvm-branch-commits] [clang] release/21.x: [clang][docs] Fix implicit-int-conversion-on-negation typos (PR #156815)
https://github.com/correctmost updated https://github.com/llvm/llvm-project/pull/156815 >From b960876ad9568b414a0aed6d61f67f3f31636119 Mon Sep 17 00:00:00 2001 From: correctmost Date: Thu, 4 Sep 2025 13:13:57 -0400 Subject: [PATCH] [clang][docs] Fix implicit-int-conversion-on-negation typos References to -Wimplicit-int-comparison-on-negation should be -Wimplicit-int-conversion-on-negation instead. --- clang/docs/ReleaseNotes.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 9400be296e7c2..f03a3273c4518 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -677,8 +677,8 @@ Improvements to Clang's diagnostics trigger a ``'Blue' is deprecated`` warning, which can be turned off with ``-Wno-deprecated-declarations-switch-case``. -- Split diagnosis of implicit integer comparison on negation to a new - diagnostic group ``-Wimplicit-int-comparison-on-negation``, grouped under +- Split diagnosis of implicit integer conversion on negation to a new + diagnostic group ``-Wimplicit-int-conversion-on-negation``, grouped under ``-Wimplicit-int-conversion``, so user can turn it off independently. - Improved the FixIts for unused lambda captures. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Remove shell requirements from tests (PR #156905)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/156905
>From f6a61c9ba23ff3139dedbc0b81e7133bc2e07345 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Thu, 4 Sep 2025 16:12:07 +
Subject: [PATCH] fix
Created using spr 1.3.6
---
clang/test/ClangScanDeps/modules-context-hash-cwd.c| 2 ++
clang/test/ClangScanDeps/modules-in-stable-dirs.c | 3 +++
clang/test/ClangScanDeps/modules-symlink-dir.c | 3 +++
clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c | 3 +++
clang/test/Driver/config-file3.c | 2 ++
clang/test/Driver/config-zos.c | 2 ++
clang/test/Driver/config-zos1.c| 1 +
clang/test/Driver/nvptx-cuda-system-arch.c | 1 +
clang/test/Frontend/dependency-gen-symlink.c | 3 +++
clang/test/Index/preamble-reparse-changed-module.m | 2 ++
clang/test/Modules/crash-vfs-path-emptydir-entries.m | 1 +
clang/test/Modules/crash-vfs-path-symlink-component.m | 2 ++
clang/test/Modules/crash-vfs-path-symlink-topheader.m | 2 ++
clang/test/Modules/crash-vfs-relative-overlay.m| 1 +
clang/test/Modules/framework-name.m| 3 +++
clang/test/Modules/module-symlink.m| 3 +++
clang/test/Modules/modulemap-collision.m | 3 +++
clang/test/Preprocessor/nonportable-include-with-hmap.c| 2 ++
18 files changed, 39 insertions(+)
diff --git a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
index e631b7b897eec..b5086ed409223 100644
--- a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
+++ b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
@@ -1,3 +1,5 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
// Test current directory pruning when computing the context hash.
// RUN: rm -rf %t
diff --git a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
index 0a7b732e5d8ac..f54e09fecee94 100644
--- a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
// This test verifies modules that are entirely comprised from stable
directory inputs are captured in
// dependency information.
diff --git a/clang/test/ClangScanDeps/modules-symlink-dir.c
b/clang/test/ClangScanDeps/modules-symlink-dir.c
index da3cf23ce6257..cf4a0998a80f9 100644
--- a/clang/test/ClangScanDeps/modules-symlink-dir.c
+++ b/clang/test/ClangScanDeps/modules-symlink-dir.c
@@ -1,3 +1,6 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
+
// Check that we canonicalize the module map path without changing the module
// directory, which would break header lookup.
diff --git a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
index 74be4a97001fe..39b2863d966c3 100644
--- a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+/// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
/// This test validates that modules that depend on prebuilt modules
/// resolve `is-in-stable-directories` correctly.
/// The steps are:
diff --git a/clang/test/Driver/config-file3.c b/clang/test/Driver/config-file3.c
index 9ba807da84414..7de77af330f6d 100644
--- a/clang/test/Driver/config-file3.c
+++ b/clang/test/Driver/config-file3.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: x86-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos.c b/clang/test/Driver/config-zos.c
index dbed97adaf5d5..055c4c981977b 100644
--- a/clang/test/Driver/config-zos.c
+++ b/clang/test/Driver/config-zos.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos1.c b/clang/test/Driver/config-zos1.c
index 6a4c17a660999..cf4f13b3879df 100644
--- a/clang/test/Driver/config-zos1.c
+++ b/clang/test/Driver/config-zos1.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: export CLANG_CONFIG_PATH=%S/Inputs/config-zos
diff --git a/clang/test/Driver/nvptx-cuda-system-arch.c
b/clang/test/Driver/nvptx-cuda-system-arch.c
index d5ce60fa6c0eb..675d15bf22cc0 100644
--- a/clang/test/Driver/nvptx-cuda-system-arch.c
+++ b/clang/test/Driver/nvptx-cuda-system-arch.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// XFAIL: target={{.*}}-zos{{.*}}
// RUN: mkdir -p %t
diff --git a/clang/test/Frontend/dependency-gen-symlink.c
b/clang/test/Frontend/dependency-gen-symlink.c
index 34b1a74a628a5..39a976a1617d
[llvm-branch-commits] [clang] release/21.x: [clang][docs] Fix implicit-int-conversion-on-negation typos (PR #156815)
correctmost wrote: > ⚠️ We detected that you are using a GitHub private e-mail address to > contribute to the repo. Fixed with a force push https://github.com/llvm/llvm-project/pull/156815 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Remove shell requirements from tests (PR #156905)
https://github.com/boomanaiden154 ready_for_review https://github.com/llvm/llvm-project/pull/156905 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
@@ -438,12 +452,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclStmt(const DeclStmt *DS) {
for (const Decl *D : DS->decls())
if (const auto *VD = dyn_cast(D))
-if (hasOrigin(VD->getType()))
+if (hasOrigin(VD))
if (const Expr *InitExpr = VD->getInit())
addAssignOriginFact(*VD, *InitExpr);
}
- void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) {
+handleUse(DRE);
+// For non-pointer/non-view types, a reference to the variable's storage
+// is a borrow. We create a loan for it.
+// For pointer/view types, we stick to the existing model for now and do
+// not create an extra origin for the l-value expression itself.
+
+// FIXME: A loan to `DeclRefExpr` for a pointer or view type can be
Xazax-hun wrote:
Couldn't we disambiguate based on the value category? I'd expect us to only
create loans here when the DRE is not an r-value.
https://github.com/llvm/llvm-project/pull/156896
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[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/156361 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Enable unbounded resource arrays at global scope (PR #155053)
@@ -0,0 +1,64 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.6-compute
-finclude-default-header \
+// RUN: -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s
-check-prefixes=CHECK,DXIL
+// RUN: %clang_cc1 -finclude-default-header -triple
spirv-unknown-vulkan-compute \
+// RUN: -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s
-check-prefixes=CHECK,SPV
+
+// CHECK: @[[BufA:.*]] = private unnamed_addr constant [2 x i8] c"A\00", align
1
+// CHECK: @[[BufB:.*]] = private unnamed_addr constant [2 x i8] c"B\00", align
1
+
+RWBuffer A[] : register(u10, space1);
+RWBuffer B[][5][4];
+
+RWStructuredBuffer Out;
+
+float foo(RWBuffer Arr[4], uint Index) {
+ return (float)Arr[Index][0];
+}
+
+// NOTE:
+// - _ZN4hlsl8RWBufferIfEC1EjjijPKc is the constructor call for explicit
binding for RWBuffer
+//(has "jjij" in the mangled name) and the arguments are (register, space,
range_size, index, name).
+// - _ZN4hlsl8RWBufferIiEC1EjijjPKc is the constructor call for implicit
binding for RWBuffer
+//(has "jijj" in the mangled name) and the arguments are (space,
range_size, index, order_id, name).
+// - _ZN4hlsl8RWBufferIfEixEj is the subscript operator on RWBuffer
hekota wrote:
Good idea! If it's ok with you, I would add the `llvm-cxxfilt` filter as part
of the change to use static create methods that will be removing these lines
anyway.
https://github.com/llvm/llvm-project/pull/155053
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[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
benshi001 wrote: It would be better to add an `[NFC]` in the title. https://github.com/llvm/llvm-project/pull/156361 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Remove the DS special case in getRegClass (PR #156696)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From c7238cff2feb2f7e1e7d7b0f55ae5b9917a682a2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instructions should now have proper representation
with separate instructions for operands which must be paired.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 946917f675318..44d819258da67 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5960,7 +5960,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const
SIRegisterInfo &RI,
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
- (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG {
+ (TID.TSFlags & SIInstrFlags::MIMG))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
@@ -5996,23 +5996,18 @@ const TargetRegisterClass
*SIInstrInfo::getRegClass(const MCInstrDesc &TID,
return nullptr;
auto RegClass = TID.operands()[OpNum].RegClass;
bool IsAllocatable = false;
- if (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::FLAT)) {
+ if (TID.TSFlags & SIInstrFlags::FLAT) {
// vdst and vdata should be both VGPR or AGPR, same for the DS instructions
// with two data operands. Request register class constrained to VGPR only
// of both operands present as Machine Copy Propagation can not check this
// constraint and possibly other passes too.
//
-// The check is limited to FLAT and DS because atomics in non-flat encoding
-// have their vdst and vdata tied to be the same register.
-const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
- AMDGPU::OpName::vdst);
-const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
-(TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata);
-if (DataIdx != -1) {
- IsAllocatable = VDstIdx != -1 || AMDGPU::hasNamedOperand(
- TID.Opcode, AMDGPU::OpName::data1);
-}
+// The check is limited to FLAT because atomics in non-flat encoding have
+// their vdst and vdata tied to be the same register, and DS instructions
+// have separate instruction definitions with AGPR and VGPR operand lists.
+IsAllocatable =
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdata) &&
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdst);
} else if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO) {
// Special pseudos have no alignment requirement
return RI.getRegClass(RegClass);
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[llvm-branch-commits] [flang] [llvm] [mlir] [MLIR][OpenMP] Introduce overlapped record type map support (PR #119588)
agozillon wrote: Sorry everyone, just the usual ping to ask for a little reviewer attention if that's at all possible, thank you all very much! :-) https://github.com/llvm/llvm-project/pull/119588 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [llvm] [mlir] [Flang][OpenMP][MLIR] Initial declare target to for variables implementation (PR #119589)
agozillon wrote: Sorry everyone, just the usual ping to ask for a little reviewer attention if that's at all possible, thank you all very much! :-) https://github.com/llvm/llvm-project/pull/119589 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Remove resource constructors with binding (PR #157008)
https://github.com/hekota ready_for_review https://github.com/llvm/llvm-project/pull/157008 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (PR #156971)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Stanislav Mekhanoshin (rampitec)
Changes
---
Patch is 23.90 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/156971.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp (+31-15)
- (added) llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h (+25)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def (+1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+4-2)
- (modified) llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll (+3-3)
``diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 4ca1011ea1312..0f2c33585884f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -501,8 +501,8 @@ extern char &SIModeRegisterID;
void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
extern char &AMDGPUInsertDelayAluID;
-void initializeAMDGPULowerVGPREncodingPass(PassRegistry &);
-extern char &AMDGPULowerVGPREncodingID;
+void initializeAMDGPULowerVGPREncodingLegacyPass(PassRegistry &);
+extern char &AMDGPULowerVGPREncodingLegacyID;
void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
extern char &SIInsertHardClausesID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index ca06c316c2bfc..adaa578583d73 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -40,6 +40,7 @@
//
//===--===//
+#include "AMDGPULowerVGPREncoding.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -52,7 +53,7 @@ using namespace llvm;
namespace {
-class AMDGPULowerVGPREncoding : public MachineFunctionPass {
+class AMDGPULowerVGPREncoding {
static constexpr unsigned OpNum = 4;
static constexpr unsigned BitsPerField = 2;
static constexpr unsigned NumFields = 4;
@@ -75,16 +76,7 @@ class AMDGPULowerVGPREncoding : public MachineFunctionPass {
};
public:
- static char ID;
-
- AMDGPULowerVGPREncoding() : MachineFunctionPass(ID) {}
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
-AU.setPreservesCFG();
-MachineFunctionPass::getAnalysisUsage(AU);
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
+ bool run(MachineFunction &MF);
private:
const SIInstrInfo *TII;
@@ -280,7 +272,7 @@ MachineInstr
*AMDGPULowerVGPREncoding::handleClause(MachineInstr *I) {
return I;
}
-bool AMDGPULowerVGPREncoding::runOnMachineFunction(MachineFunction &MF) {
+bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget();
if (!ST.has1024AddressableVGPRs())
return false;
@@ -344,11 +336,35 @@ bool
AMDGPULowerVGPREncoding::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+class AMDGPULowerVGPREncodingLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ AMDGPULowerVGPREncodingLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+return AMDGPULowerVGPREncoding().run(MF);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.setPreservesCFG();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+
} // namespace
-char AMDGPULowerVGPREncoding::ID = 0;
+char AMDGPULowerVGPREncodingLegacy::ID = 0;
-char &llvm::AMDGPULowerVGPREncodingID = AMDGPULowerVGPREncoding::ID;
+char &llvm::AMDGPULowerVGPREncodingLegacyID =
AMDGPULowerVGPREncodingLegacy::ID;
-INITIALIZE_PASS(AMDGPULowerVGPREncoding, DEBUG_TYPE,
+INITIALIZE_PASS(AMDGPULowerVGPREncodingLegacy, DEBUG_TYPE,
"AMDGPU Lower VGPR Encoding", false, false)
+
+PreservedAnalyses
+AMDGPULowerVGPREncodingPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (AMDGPULowerVGPREncoding().run(MF))
+return PreservedAnalyses::none();
+ return PreservedAnalyses::all();
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
new file mode 100644
index 0..c8c2051c9fddd
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
@@ -0,0 +1,25 @@
+//===--- AMDGPULowerVGPREncoding.h --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPULOWERVGPRENCODING_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPULOWERVGPRENCODING_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llv
[llvm-branch-commits] [clang] [HLSL] Remove resource constructors with binding (PR #157008)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Helena Kotas (hekota)
Changes
The constructors are replaced by static `__createFromBinding` and
`__createFromImplicitBinding` methods on the resource class.
Depends on #157005
Part 4 of #154221
---
Full diff: https://github.com/llvm/llvm-project/pull/157008.diff
6 Files Affected:
- (modified) clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp (-43)
- (modified) clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h (-2)
- (modified) clang/lib/Sema/HLSLExternalSemaSource.cpp (+1-3)
- (modified) clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl (-48)
- (modified) clang/test/AST/HLSL/StructuredBuffers-AST.hlsl (-48)
- (modified) clang/test/AST/HLSL/TypedBuffers-AST.hlsl (-48)
``diff
diff --git a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
index a4d75155d8511..f1fdf84800fea 100644
--- a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+++ b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
@@ -731,49 +731,6 @@ BuiltinTypeDeclBuilder
&BuiltinTypeDeclBuilder::addDefaultHandleConstructor() {
.finalize();
}
-BuiltinTypeDeclBuilder &
-BuiltinTypeDeclBuilder::addHandleConstructorFromBinding() {
- if (Record->isCompleteDefinition())
-return *this;
-
- using PH = BuiltinTypeMethodBuilder::PlaceHolder;
- ASTContext &AST = SemaRef.getASTContext();
- QualType HandleType = getResourceHandleField()->getType();
-
- return BuiltinTypeMethodBuilder(*this, "", AST.VoidTy, false, true)
- .addParam("registerNo", AST.UnsignedIntTy)
- .addParam("spaceNo", AST.UnsignedIntTy)
- .addParam("range", AST.IntTy)
- .addParam("index", AST.UnsignedIntTy)
- .addParam("name", AST.getPointerType(AST.CharTy.withConst()))
- .callBuiltin("__builtin_hlsl_resource_handlefrombinding", HandleType,
- PH::Handle, PH::_0, PH::_1, PH::_2, PH::_3, PH::_4)
- .assign(PH::Handle, PH::LastStmt)
- .finalize();
-}
-
-BuiltinTypeDeclBuilder &
-BuiltinTypeDeclBuilder::addHandleConstructorFromImplicitBinding() {
- if (Record->isCompleteDefinition())
-return *this;
-
- using PH = BuiltinTypeMethodBuilder::PlaceHolder;
- ASTContext &AST = SemaRef.getASTContext();
- QualType HandleType = getResourceHandleField()->getType();
-
- return BuiltinTypeMethodBuilder(*this, "", AST.VoidTy, false, true)
- .addParam("spaceNo", AST.UnsignedIntTy)
- .addParam("range", AST.IntTy)
- .addParam("index", AST.UnsignedIntTy)
- .addParam("orderId", AST.UnsignedIntTy)
- .addParam("name", AST.getPointerType(AST.CharTy.withConst()))
- .callBuiltin("__builtin_hlsl_resource_handlefromimplicitbinding",
- HandleType, PH::Handle, PH::_3, PH::_0, PH::_1, PH::_2,
- PH::_4)
- .assign(PH::Handle, PH::LastStmt)
- .finalize();
-}
-
BuiltinTypeDeclBuilder &BuiltinTypeDeclBuilder::addCreateFromBinding() {
if (Record->isCompleteDefinition())
return *this;
diff --git a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
index ba860a9080cea..674a750d905fa 100644
--- a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
+++ b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
@@ -78,8 +78,6 @@ class BuiltinTypeDeclBuilder {
// Builtin types constructors
BuiltinTypeDeclBuilder &addDefaultHandleConstructor();
- BuiltinTypeDeclBuilder &addHandleConstructorFromBinding();
- BuiltinTypeDeclBuilder &addHandleConstructorFromImplicitBinding();
// Static create methods
BuiltinTypeDeclBuilder &addCreateFromBinding();
diff --git a/clang/lib/Sema/HLSLExternalSemaSource.cpp
b/clang/lib/Sema/HLSLExternalSemaSource.cpp
index a5d51ca7d35be..e3d5e8f1b6b52 100644
--- a/clang/lib/Sema/HLSLExternalSemaSource.cpp
+++ b/clang/lib/Sema/HLSLExternalSemaSource.cpp
@@ -133,9 +133,7 @@ static BuiltinTypeDeclBuilder setupBufferType(CXXRecordDecl
*Decl, Sema &S,
.addHandleMember(RC, IsROV, RawBuffer)
.addDefaultHandleConstructor()
.addCreateFromBinding()
- .addCreateFromImplicitBinding()
- .addHandleConstructorFromBinding()
- .addHandleConstructorFromImplicitBinding();
+ .addCreateFromImplicitBinding();
}
// This function is responsible for constructing the constraint expression for
diff --git a/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
b/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
index 93418e4877465..3aebb528ce126 100644
--- a/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
+++ b/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
@@ -112,53 +112,5 @@ RESOURCE Buffer;
// CHECK-NEXT: DeclRefExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue Var {{.*}} 'tmp'
'hlsl::[[RESOURCE]]'
// CHECK-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline
-// Constructor from binding
-
-// CHECK: CXXConstructorDecl {{.*}} [[RESOURCE]] 'void (unsigned int, unsigned
int, int, unsigned int, const char *)' inline
-// CHECK-NEXT: ParmVarDecl {{.*}} registerNo 'unsigned int'
-// CHECK-NEXT: Pa
[llvm-branch-commits] [llvm] release/21.x: [Coroutines] Restore accidentally dropped intrinsic IDs (PR #156925)
https://github.com/ChuanqiXu9 approved this pull request. https://github.com/llvm/llvm-project/pull/156925 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Enable unbounded resource arrays at global scope (PR #155053)
https://github.com/hekota edited https://github.com/llvm/llvm-project/pull/155053 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Use static create methods to initialize resources in arrays (PR #157005)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Helena Kotas (hekota)
Changes
Use static methods __createFromBinding and __createFromImplicitBinding to
initialize resources in resource arrays.
Depends on #156544
Part 3 of #154221
---
Patch is 51.42 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/157005.diff
9 Files Affected:
- (modified) clang/include/clang/Sema/SemaHLSL.h (-5)
- (modified) clang/lib/CodeGen/CGHLSLRuntime.cpp (+74-52)
- (modified) clang/lib/Sema/SemaHLSL.cpp (+26-66)
- (modified) clang/test/CodeGenHLSL/resources/res-array-global-dyn-index.hlsl
(+7-7)
- (modified) clang/test/CodeGenHLSL/resources/res-array-global-multi-dim.hlsl
(+22-22)
- (modified)
clang/test/CodeGenHLSL/resources/res-array-global-subarray-many.hlsl (+53-26)
- (modified)
clang/test/CodeGenHLSL/resources/res-array-global-subarray-one.hlsl (+19-16)
- (modified) clang/test/CodeGenHLSL/resources/res-array-global.hlsl (+40-27)
- (modified) clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl (+2-2)
``diff
diff --git a/clang/include/clang/Sema/SemaHLSL.h
b/clang/include/clang/Sema/SemaHLSL.h
index 5cbe1b658f5cd..86265a51fb252 100644
--- a/clang/include/clang/Sema/SemaHLSL.h
+++ b/clang/include/clang/Sema/SemaHLSL.h
@@ -241,11 +241,6 @@ class SemaHLSL : public SemaBase {
bool initGlobalResourceDecl(VarDecl *VD);
bool initGlobalResourceArrayDecl(VarDecl *VD);
- void createResourceRecordCtorArgs(const Type *ResourceTy, StringRef VarName,
-HLSLResourceBindingAttr *RBA,
-HLSLVkBindingAttr *VkBinding,
-uint32_t ArrayIndex,
-llvm::SmallVectorImpl &Args);
};
} // namespace clang
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp
b/clang/lib/CodeGen/CGHLSLRuntime.cpp
index d27f3781c69a3..fa365f419cdb1 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.cpp
+++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp
@@ -13,6 +13,7 @@
//===--===//
#include "CGHLSLRuntime.h"
+#include "Address.h"
#include "CGDebugInfo.h"
#include "CodeGenFunction.h"
#include "CodeGenModule.h"
@@ -38,6 +39,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormatVariadic.h"
#include
+#include
using namespace clang;
using namespace CodeGen;
@@ -148,14 +150,22 @@ static Value *buildNameForResource(llvm::StringRef
BaseName,
.getPointer();
}
-static void createResourceCtorArgs(CodeGenModule &CGM, CXXConstructorDecl *CD,
- llvm::Value *ThisPtr, llvm::Value *Range,
- llvm::Value *Index, StringRef Name,
- HLSLResourceBindingAttr *RBA,
- HLSLVkBindingAttr *VkBinding,
- CallArgList &Args) {
+static CXXMethodDecl *lookupMethod(CXXRecordDecl *Record, StringRef Name,
+ StorageClass SC = SC_None) {
+ for (auto *Method : Record->methods()) {
+if (Method->getStorageClass() == SC && Method->getName() == Name)
+ return Method;
+ }
+ return nullptr;
+}
+
+static CXXMethodDecl *lookupResourceInitMethodAndSetupArgs(
+CodeGenModule &CGM, CXXRecordDecl *ResourceDecl, llvm::Value *Range,
+llvm::Value *Index, StringRef Name, HLSLResourceBindingAttr *RBA,
+HLSLVkBindingAttr *VkBinding, CallArgList &Args) {
assert((VkBinding || RBA) && "at least one a binding attribute expected");
+ ASTContext &AST = CGM.getContext();
std::optional RegisterSlot;
uint32_t SpaceNo = 0;
if (VkBinding) {
@@ -167,44 +177,57 @@ static void createResourceCtorArgs(CodeGenModule &CGM,
CXXConstructorDecl *CD,
SpaceNo = RBA->getSpaceNumber();
}
- ASTContext &AST = CD->getASTContext();
+ CXXMethodDecl *CreateMethod = nullptr;
Value *NameStr = buildNameForResource(Name, CGM);
Value *Space = llvm::ConstantInt::get(CGM.IntTy, SpaceNo);
- Args.add(RValue::get(ThisPtr), CD->getThisType());
if (RegisterSlot.has_value()) {
// explicit binding
auto *RegSlot = llvm::ConstantInt::get(CGM.IntTy, RegisterSlot.value());
Args.add(RValue::get(RegSlot), AST.UnsignedIntTy);
-Args.add(RValue::get(Space), AST.UnsignedIntTy);
-Args.add(RValue::get(Range), AST.IntTy);
-Args.add(RValue::get(Index), AST.UnsignedIntTy);
-
+CreateMethod = lookupMethod(ResourceDecl, "__createFromBinding",
SC_Static);
} else {
// implicit binding
-assert(RBA && "missing implicit binding attribute");
auto *OrderID =
llvm::ConstantInt::get(CGM.IntTy, RBA->getImplicitBindingOrderID());
-Args.add(RValue::get(Space), AST.UnsignedIntTy);
-Args.add(RValue::get(Range), AST.IntTy);
-Args.add(RValue::get(Index), AST.UnsignedIntTy);
Args.add(RValue::get(OrderID), AST.UnsignedIntTy);
+CreateMe
[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/156896 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Add more tests for flat/global atomicrmw with agprs (PR #156874)
https://github.com/rampitec commented: The files better be named like flat-atomicrmw-a-v.ll etc. So they do not popup at the top of the directory sort order but close to other flat/global stuff. https://github.com/llvm/llvm-project/pull/156874 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NFC][IR2Vec] Initialize Embedding vectors with zeros by default (PR #155690)
https://github.com/svkeerthy updated
https://github.com/llvm/llvm-project/pull/155690
>From 8c8500cd277936888d7031a503b5e3ce416469a3 Mon Sep 17 00:00:00 2001
From: svkeerthy
Date: Wed, 27 Aug 2025 20:25:30 +
Subject: [PATCH] Default constructor
---
llvm/include/llvm/Analysis/IR2Vec.h | 2 +-
llvm/lib/Analysis/IR2Vec.cpp| 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/Analysis/IR2Vec.h
b/llvm/include/llvm/Analysis/IR2Vec.h
index 4c2546323cb2c..b7b881999241e 100644
--- a/llvm/include/llvm/Analysis/IR2Vec.h
+++ b/llvm/include/llvm/Analysis/IR2Vec.h
@@ -92,7 +92,7 @@ struct Embedding {
Embedding(std::vector &&V) : Data(std::move(V)) {}
Embedding(std::initializer_list IL) : Data(IL) {}
- explicit Embedding(size_t Size) : Data(Size) {}
+ explicit Embedding(size_t Size) : Data(Size, 0.0) {}
Embedding(size_t Size, double InitialValue) : Data(Size, InitialValue) {}
size_t size() const { return Data.size(); }
diff --git a/llvm/lib/Analysis/IR2Vec.cpp b/llvm/lib/Analysis/IR2Vec.cpp
index cbaa8301d722b..98849fd922843 100644
--- a/llvm/lib/Analysis/IR2Vec.cpp
+++ b/llvm/lib/Analysis/IR2Vec.cpp
@@ -155,7 +155,7 @@ void Embedding::print(raw_ostream &OS) const {
Embedder::Embedder(const Function &F, const Vocabulary &Vocab)
: F(F), Vocab(Vocab), Dimension(Vocab.getDimension()),
OpcWeight(::OpcWeight), TypeWeight(::TypeWeight), ArgWeight(::ArgWeight),
- FuncVector(Embedding(Dimension, 0)) {}
+ FuncVector(Embedding(Dimension)) {}
std::unique_ptr Embedder::create(IR2VecKind Mode, const Function &F,
const Vocabulary &Vocab) {
@@ -472,7 +472,7 @@ void IR2VecVocabAnalysis::generateNumMappedVocab() {
// Handle Opcodes
std::vector NumericOpcodeEmbeddings(Vocabulary::MaxOpcodes,
- Embedding(Dim, 0));
+ Embedding(Dim));
NumericOpcodeEmbeddings.reserve(Vocabulary::MaxOpcodes);
for (unsigned Opcode : seq(0u, Vocabulary::MaxOpcodes)) {
StringRef VocabKey = Vocabulary::getVocabKeyForOpcode(Opcode + 1);
@@ -487,7 +487,7 @@ void IR2VecVocabAnalysis::generateNumMappedVocab() {
// Handle Types - only canonical types are present in vocabulary
std::vector NumericTypeEmbeddings(Vocabulary::MaxCanonicalTypeIDs,
- Embedding(Dim, 0));
+ Embedding(Dim));
NumericTypeEmbeddings.reserve(Vocabulary::MaxCanonicalTypeIDs);
for (unsigned CTypeID : seq(0u, Vocabulary::MaxCanonicalTypeIDs)) {
StringRef VocabKey = Vocabulary::getVocabKeyForCanonicalTypeID(
@@ -503,7 +503,7 @@ void IR2VecVocabAnalysis::generateNumMappedVocab() {
// Handle Arguments/Operands
std::vector NumericArgEmbeddings(Vocabulary::MaxOperandKinds,
- Embedding(Dim, 0));
+ Embedding(Dim));
NumericArgEmbeddings.reserve(Vocabulary::MaxOperandKinds);
for (unsigned OpKind : seq(0u, Vocabulary::MaxOperandKinds)) {
Vocabulary::OperandKind Kind =
static_cast(OpKind);
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (PR #156971)
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/156971
None
>From 52485b517c9030fca5a01d4e572f82a7e306a53f Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 4 Sep 2025 14:46:15 -0700
Subject: [PATCH] [AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 4 +-
.../Target/AMDGPU/AMDGPULowerVGPREncoding.cpp | 46 +--
.../Target/AMDGPU/AMDGPULowerVGPREncoding.h | 25 ++
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 ++-
llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +--
6 files changed, 66 insertions(+), 22 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 4ca1011ea1312..0f2c33585884f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -501,8 +501,8 @@ extern char &SIModeRegisterID;
void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
extern char &AMDGPUInsertDelayAluID;
-void initializeAMDGPULowerVGPREncodingPass(PassRegistry &);
-extern char &AMDGPULowerVGPREncodingID;
+void initializeAMDGPULowerVGPREncodingLegacyPass(PassRegistry &);
+extern char &AMDGPULowerVGPREncodingLegacyID;
void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
extern char &SIInsertHardClausesID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index ca06c316c2bfc..adaa578583d73 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -40,6 +40,7 @@
//
//===--===//
+#include "AMDGPULowerVGPREncoding.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -52,7 +53,7 @@ using namespace llvm;
namespace {
-class AMDGPULowerVGPREncoding : public MachineFunctionPass {
+class AMDGPULowerVGPREncoding {
static constexpr unsigned OpNum = 4;
static constexpr unsigned BitsPerField = 2;
static constexpr unsigned NumFields = 4;
@@ -75,16 +76,7 @@ class AMDGPULowerVGPREncoding : public MachineFunctionPass {
};
public:
- static char ID;
-
- AMDGPULowerVGPREncoding() : MachineFunctionPass(ID) {}
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
-AU.setPreservesCFG();
-MachineFunctionPass::getAnalysisUsage(AU);
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
+ bool run(MachineFunction &MF);
private:
const SIInstrInfo *TII;
@@ -280,7 +272,7 @@ MachineInstr
*AMDGPULowerVGPREncoding::handleClause(MachineInstr *I) {
return I;
}
-bool AMDGPULowerVGPREncoding::runOnMachineFunction(MachineFunction &MF) {
+bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget();
if (!ST.has1024AddressableVGPRs())
return false;
@@ -344,11 +336,35 @@ bool
AMDGPULowerVGPREncoding::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+class AMDGPULowerVGPREncodingLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ AMDGPULowerVGPREncodingLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
+return AMDGPULowerVGPREncoding().run(MF);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.setPreservesCFG();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+
} // namespace
-char AMDGPULowerVGPREncoding::ID = 0;
+char AMDGPULowerVGPREncodingLegacy::ID = 0;
-char &llvm::AMDGPULowerVGPREncodingID = AMDGPULowerVGPREncoding::ID;
+char &llvm::AMDGPULowerVGPREncodingLegacyID =
AMDGPULowerVGPREncodingLegacy::ID;
-INITIALIZE_PASS(AMDGPULowerVGPREncoding, DEBUG_TYPE,
+INITIALIZE_PASS(AMDGPULowerVGPREncodingLegacy, DEBUG_TYPE,
"AMDGPU Lower VGPR Encoding", false, false)
+
+PreservedAnalyses
+AMDGPULowerVGPREncodingPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (AMDGPULowerVGPREncoding().run(MF))
+return PreservedAnalyses::none();
+ return PreservedAnalyses::all();
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
new file mode 100644
index 0..c8c2051c9fddd
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.h
@@ -0,0 +1,25 @@
+//===--- AMDGPULowerVGPREncoding.h --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPULOWERVGPRENCODING_
[llvm-branch-commits] [llvm] [AMDGPU] Print high vgpr operand comments from objdump (PR #156966)
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/156966
>From 13c8adce4fdae87644adfa29fd82bba8c3e47d64 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 4 Sep 2025 13:39:32 -0700
Subject: [PATCH] [AMDGPU] Print high vgpr operand comments from objdump
This followed the agreed convention: every basic block shall
start with all MSBs zero. Codegen does the same lowering.
---
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 39 +++
.../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 48 ++-
.../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 23 +
.../CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir | 1 +
4 files changed, 89 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index d1e8b7e4bad0d..f098e7a3c6c67 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -336,6 +336,42 @@ static MCPhysReg getRegForPrinting(MCPhysReg Reg, const
MCRegisterInfo &MRI) {
return RC->getRegister(Idx % 0x100);
}
+// Restore MSBs of a VGPR above 255 from the MCInstrAnalysis.
+static MCPhysReg getRegFromMIA(MCPhysReg Reg, unsigned OpNo,
+ const MCInstrDesc &Desc,
+ const MCRegisterInfo &MRI,
+ const AMDGPUMCInstrAnalysis &MIA) {
+ unsigned VgprMSBs = MIA.getVgprMSBs();
+ if (!VgprMSBs)
+return Reg;
+
+ unsigned Enc = MRI.getEncodingValue(Reg);
+ if (!(Enc & AMDGPU::HWEncoding::IS_VGPR))
+return Reg;
+
+ auto Ops = AMDGPU::getVGPRLoweringOperandTables(Desc);
+ if (!Ops.first)
+return Reg;
+ unsigned Opc = Desc.getOpcode();
+ unsigned I;
+ for (I = 0; I < 4; ++I) {
+if (Ops.first[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
+(unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.first[I]) == OpNo)
+ break;
+if (Ops.second && Ops.second[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
+(unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.second[I]) == OpNo)
+ break;
+ }
+ if (I == 4)
+return Reg;
+ unsigned OpMSBs = (VgprMSBs >> (I * 2)) & 3;
+ if (!OpMSBs)
+return Reg;
+ if (MCRegister NewReg = AMDGPU::getVGPRWithMSBs(Reg, OpMSBs, MRI))
+return NewReg;
+ return Reg;
+}
+
void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O,
const MCRegisterInfo &MRI) {
#if !defined(NDEBUG)
@@ -359,6 +395,9 @@ void AMDGPUInstPrinter::printRegOperand(MCRegister Reg,
raw_ostream &O,
void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, unsigned Opc,
unsigned OpNo, raw_ostream &O,
const MCRegisterInfo &MRI) {
+ if (MIA)
+Reg = getRegFromMIA(Reg, OpNo, MII.get(Opc), MRI,
+*static_cast(MIA));
printRegOperand(Reg, O, MRI);
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index d66725d3a6c4b..90c56f6901460 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -21,9 +21,9 @@
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectWriter.h"
@@ -130,31 +130,35 @@ static MCStreamer *createMCStreamer(const Triple &T,
MCContext &Context,
std::move(Emitter));
}
-namespace {
-
-class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
-public:
- explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
- : MCInstrAnalysis(Info) {}
-
- bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
-if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
-Info->get(Inst.getOpcode()).operands()[0].OperandType !=
-MCOI::OPERAND_PCREL)
- return false;
+namespace llvm {
+namespace AMDGPU {
+
+bool AMDGPUMCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size,
+ uint64_t &Target) const {
+ if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
+ Info->get(Inst.getOpcode()).operands()[0].OperandType !=
+ MCOI::OPERAND_PCREL)
+return false;
+
+ int64_t Imm = Inst.getOperand(0).getImm();
+ // Our branches take a simm16.
+ Target = SignExtend64<16>(Imm) * 4 + Addr + Size;
+ return true;
+}
-int64_t Imm = Inst.getOperand(0).getImm();
-// Our
[llvm-branch-commits] [llvm] [AMDGPU] Print high vgpr operand comments from objdump (PR #156966)
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/156966
>From 13c8adce4fdae87644adfa29fd82bba8c3e47d64 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 4 Sep 2025 13:39:32 -0700
Subject: [PATCH] [AMDGPU] Print high vgpr operand comments from objdump
This followed the agreed convention: every basic block shall
start with all MSBs zero. Codegen does the same lowering.
---
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 39 +++
.../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 48 ++-
.../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 23 +
.../CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir | 1 +
4 files changed, 89 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index d1e8b7e4bad0d..f098e7a3c6c67 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -336,6 +336,42 @@ static MCPhysReg getRegForPrinting(MCPhysReg Reg, const
MCRegisterInfo &MRI) {
return RC->getRegister(Idx % 0x100);
}
+// Restore MSBs of a VGPR above 255 from the MCInstrAnalysis.
+static MCPhysReg getRegFromMIA(MCPhysReg Reg, unsigned OpNo,
+ const MCInstrDesc &Desc,
+ const MCRegisterInfo &MRI,
+ const AMDGPUMCInstrAnalysis &MIA) {
+ unsigned VgprMSBs = MIA.getVgprMSBs();
+ if (!VgprMSBs)
+return Reg;
+
+ unsigned Enc = MRI.getEncodingValue(Reg);
+ if (!(Enc & AMDGPU::HWEncoding::IS_VGPR))
+return Reg;
+
+ auto Ops = AMDGPU::getVGPRLoweringOperandTables(Desc);
+ if (!Ops.first)
+return Reg;
+ unsigned Opc = Desc.getOpcode();
+ unsigned I;
+ for (I = 0; I < 4; ++I) {
+if (Ops.first[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
+(unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.first[I]) == OpNo)
+ break;
+if (Ops.second && Ops.second[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
+(unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.second[I]) == OpNo)
+ break;
+ }
+ if (I == 4)
+return Reg;
+ unsigned OpMSBs = (VgprMSBs >> (I * 2)) & 3;
+ if (!OpMSBs)
+return Reg;
+ if (MCRegister NewReg = AMDGPU::getVGPRWithMSBs(Reg, OpMSBs, MRI))
+return NewReg;
+ return Reg;
+}
+
void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O,
const MCRegisterInfo &MRI) {
#if !defined(NDEBUG)
@@ -359,6 +395,9 @@ void AMDGPUInstPrinter::printRegOperand(MCRegister Reg,
raw_ostream &O,
void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, unsigned Opc,
unsigned OpNo, raw_ostream &O,
const MCRegisterInfo &MRI) {
+ if (MIA)
+Reg = getRegFromMIA(Reg, OpNo, MII.get(Opc), MRI,
+*static_cast(MIA));
printRegOperand(Reg, O, MRI);
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index d66725d3a6c4b..90c56f6901460 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -21,9 +21,9 @@
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectWriter.h"
@@ -130,31 +130,35 @@ static MCStreamer *createMCStreamer(const Triple &T,
MCContext &Context,
std::move(Emitter));
}
-namespace {
-
-class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
-public:
- explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
- : MCInstrAnalysis(Info) {}
-
- bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
-if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
-Info->get(Inst.getOpcode()).operands()[0].OperandType !=
-MCOI::OPERAND_PCREL)
- return false;
+namespace llvm {
+namespace AMDGPU {
+
+bool AMDGPUMCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size,
+ uint64_t &Target) const {
+ if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
+ Info->get(Inst.getOpcode()).operands()[0].OperandType !=
+ MCOI::OPERAND_PCREL)
+return false;
+
+ int64_t Imm = Inst.getOperand(0).getImm();
+ // Our branches take a simm16.
+ Target = SignExtend64<16>(Imm) * 4 + Addr + Size;
+ return true;
+}
-int64_t Imm = Inst.getOperand(0).getImm();
-// Our
[llvm-branch-commits] [llvm] [AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (PR #156971)
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156971?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#156971** https://app.graphite.dev/github/pr/llvm/llvm-project/156971?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/156971?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#156966** https://app.graphite.dev/github/pr/llvm/llvm-project/156966?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156965** https://app.graphite.dev/github/pr/llvm/llvm-project/156965?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/156971 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (PR #156971)
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/156971 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Remarks] BitstreamRemarkParser: Refactor error handling (PR #156511)
francisvm wrote: Is the main goal to unify the API for the standalone/separate parsers under `BitstreamBlockParserHelper`? https://github.com/llvm/llvm-project/pull/156511 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Remarks] Restructure bitstream remarks to be fully standalone (PR #156715)
francisvm wrote: > because only the standalone files can be read by llvm-remarkutil `llvm-remarkutil` would also work if you extract the section from the object file. It would be nice to have a mode of `llvm-remarkutil` that detects an object file and looks for the section automatically. https://github.com/llvm/llvm-project/pull/156715 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Remarks] Restructure bitstream remarks to be fully standalone (PR #156715)
francisvm wrote: Thanks for putting in the work to simplify this. Could you please update the description with a summary of the new flow of how remarks are emitted and parsed in both modes? I'll keep reviewing this over the next few days. https://github.com/llvm/llvm-project/pull/156715 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Add support for GSL Pointer types (PR #154009)
https://github.com/usx95 edited https://github.com/llvm/llvm-project/pull/154009 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Remove shell requirements from tests (PR #156905)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/156905
>From f6a61c9ba23ff3139dedbc0b81e7133bc2e07345 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Thu, 4 Sep 2025 16:12:07 +
Subject: [PATCH] fix
Created using spr 1.3.6
---
clang/test/ClangScanDeps/modules-context-hash-cwd.c| 2 ++
clang/test/ClangScanDeps/modules-in-stable-dirs.c | 3 +++
clang/test/ClangScanDeps/modules-symlink-dir.c | 3 +++
clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c | 3 +++
clang/test/Driver/config-file3.c | 2 ++
clang/test/Driver/config-zos.c | 2 ++
clang/test/Driver/config-zos1.c| 1 +
clang/test/Driver/nvptx-cuda-system-arch.c | 1 +
clang/test/Frontend/dependency-gen-symlink.c | 3 +++
clang/test/Index/preamble-reparse-changed-module.m | 2 ++
clang/test/Modules/crash-vfs-path-emptydir-entries.m | 1 +
clang/test/Modules/crash-vfs-path-symlink-component.m | 2 ++
clang/test/Modules/crash-vfs-path-symlink-topheader.m | 2 ++
clang/test/Modules/crash-vfs-relative-overlay.m| 1 +
clang/test/Modules/framework-name.m| 3 +++
clang/test/Modules/module-symlink.m| 3 +++
clang/test/Modules/modulemap-collision.m | 3 +++
clang/test/Preprocessor/nonportable-include-with-hmap.c| 2 ++
18 files changed, 39 insertions(+)
diff --git a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
index e631b7b897eec..b5086ed409223 100644
--- a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
+++ b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
@@ -1,3 +1,5 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
// Test current directory pruning when computing the context hash.
// RUN: rm -rf %t
diff --git a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
index 0a7b732e5d8ac..f54e09fecee94 100644
--- a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
// This test verifies modules that are entirely comprised from stable
directory inputs are captured in
// dependency information.
diff --git a/clang/test/ClangScanDeps/modules-symlink-dir.c
b/clang/test/ClangScanDeps/modules-symlink-dir.c
index da3cf23ce6257..cf4a0998a80f9 100644
--- a/clang/test/ClangScanDeps/modules-symlink-dir.c
+++ b/clang/test/ClangScanDeps/modules-symlink-dir.c
@@ -1,3 +1,6 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
+
// Check that we canonicalize the module map path without changing the module
// directory, which would break header lookup.
diff --git a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
index 74be4a97001fe..39b2863d966c3 100644
--- a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+/// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
/// This test validates that modules that depend on prebuilt modules
/// resolve `is-in-stable-directories` correctly.
/// The steps are:
diff --git a/clang/test/Driver/config-file3.c b/clang/test/Driver/config-file3.c
index 9ba807da84414..7de77af330f6d 100644
--- a/clang/test/Driver/config-file3.c
+++ b/clang/test/Driver/config-file3.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: x86-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos.c b/clang/test/Driver/config-zos.c
index dbed97adaf5d5..055c4c981977b 100644
--- a/clang/test/Driver/config-zos.c
+++ b/clang/test/Driver/config-zos.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos1.c b/clang/test/Driver/config-zos1.c
index 6a4c17a660999..cf4f13b3879df 100644
--- a/clang/test/Driver/config-zos1.c
+++ b/clang/test/Driver/config-zos1.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: export CLANG_CONFIG_PATH=%S/Inputs/config-zos
diff --git a/clang/test/Driver/nvptx-cuda-system-arch.c
b/clang/test/Driver/nvptx-cuda-system-arch.c
index d5ce60fa6c0eb..675d15bf22cc0 100644
--- a/clang/test/Driver/nvptx-cuda-system-arch.c
+++ b/clang/test/Driver/nvptx-cuda-system-arch.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// XFAIL: target={{.*}}-zos{{.*}}
// RUN: mkdir -p %t
diff --git a/clang/test/Frontend/dependency-gen-symlink.c
b/clang/test/Frontend/dependency-gen-symlink.c
index 34b1a74a628a5..39a976a1617d
[llvm-branch-commits] [clang] [clang] Remove shell requirements from tests (PR #156905)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/156905
>From f6a61c9ba23ff3139dedbc0b81e7133bc2e07345 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Thu, 4 Sep 2025 16:12:07 +
Subject: [PATCH] fix
Created using spr 1.3.6
---
clang/test/ClangScanDeps/modules-context-hash-cwd.c| 2 ++
clang/test/ClangScanDeps/modules-in-stable-dirs.c | 3 +++
clang/test/ClangScanDeps/modules-symlink-dir.c | 3 +++
clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c | 3 +++
clang/test/Driver/config-file3.c | 2 ++
clang/test/Driver/config-zos.c | 2 ++
clang/test/Driver/config-zos1.c| 1 +
clang/test/Driver/nvptx-cuda-system-arch.c | 1 +
clang/test/Frontend/dependency-gen-symlink.c | 3 +++
clang/test/Index/preamble-reparse-changed-module.m | 2 ++
clang/test/Modules/crash-vfs-path-emptydir-entries.m | 1 +
clang/test/Modules/crash-vfs-path-symlink-component.m | 2 ++
clang/test/Modules/crash-vfs-path-symlink-topheader.m | 2 ++
clang/test/Modules/crash-vfs-relative-overlay.m| 1 +
clang/test/Modules/framework-name.m| 3 +++
clang/test/Modules/module-symlink.m| 3 +++
clang/test/Modules/modulemap-collision.m | 3 +++
clang/test/Preprocessor/nonportable-include-with-hmap.c| 2 ++
18 files changed, 39 insertions(+)
diff --git a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
index e631b7b897eec..b5086ed409223 100644
--- a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
+++ b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
@@ -1,3 +1,5 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
// Test current directory pruning when computing the context hash.
// RUN: rm -rf %t
diff --git a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
index 0a7b732e5d8ac..f54e09fecee94 100644
--- a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
// This test verifies modules that are entirely comprised from stable
directory inputs are captured in
// dependency information.
diff --git a/clang/test/ClangScanDeps/modules-symlink-dir.c
b/clang/test/ClangScanDeps/modules-symlink-dir.c
index da3cf23ce6257..cf4a0998a80f9 100644
--- a/clang/test/ClangScanDeps/modules-symlink-dir.c
+++ b/clang/test/ClangScanDeps/modules-symlink-dir.c
@@ -1,3 +1,6 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
+
// Check that we canonicalize the module map path without changing the module
// directory, which would break header lookup.
diff --git a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
index 74be4a97001fe..39b2863d966c3 100644
--- a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+/// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
/// This test validates that modules that depend on prebuilt modules
/// resolve `is-in-stable-directories` correctly.
/// The steps are:
diff --git a/clang/test/Driver/config-file3.c b/clang/test/Driver/config-file3.c
index 9ba807da84414..7de77af330f6d 100644
--- a/clang/test/Driver/config-file3.c
+++ b/clang/test/Driver/config-file3.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: x86-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos.c b/clang/test/Driver/config-zos.c
index dbed97adaf5d5..055c4c981977b 100644
--- a/clang/test/Driver/config-zos.c
+++ b/clang/test/Driver/config-zos.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos1.c b/clang/test/Driver/config-zos1.c
index 6a4c17a660999..cf4f13b3879df 100644
--- a/clang/test/Driver/config-zos1.c
+++ b/clang/test/Driver/config-zos1.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: export CLANG_CONFIG_PATH=%S/Inputs/config-zos
diff --git a/clang/test/Driver/nvptx-cuda-system-arch.c
b/clang/test/Driver/nvptx-cuda-system-arch.c
index d5ce60fa6c0eb..675d15bf22cc0 100644
--- a/clang/test/Driver/nvptx-cuda-system-arch.c
+++ b/clang/test/Driver/nvptx-cuda-system-arch.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// XFAIL: target={{.*}}-zos{{.*}}
// RUN: mkdir -p %t
diff --git a/clang/test/Frontend/dependency-gen-symlink.c
b/clang/test/Frontend/dependency-gen-symlink.c
index 34b1a74a628a5..39a976a1617d
[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
@@ -438,12 +452,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclStmt(const DeclStmt *DS) {
for (const Decl *D : DS->decls())
if (const auto *VD = dyn_cast(D))
-if (hasOrigin(VD->getType()))
+if (hasOrigin(VD))
if (const Expr *InitExpr = VD->getInit())
addAssignOriginFact(*VD, *InitExpr);
}
- void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) {
+handleUse(DRE);
+// For non-pointer/non-view types, a reference to the variable's storage
+// is a borrow. We create a loan for it.
+// For pointer/view types, we stick to the existing model for now and do
+// not create an extra origin for the l-value expression itself.
+
+// FIXME: A loan to `DeclRefExpr` for a pointer or view type can be
Xazax-hun wrote:
Ah, never mind. The `DeclRefExpr` itself is always an lvalue. We just have an
LValueToRValue conversion on top.
https://github.com/llvm/llvm-project/pull/156896
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Add support for GSL Pointer types (PR #154009)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From 2f0c4c10dc8295f4eb3f323c5129f1ef0b3ac2a1 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Thu, 4 Sep 2025 14:27:37 +
Subject: [PATCH 1/2] all-lvalues-have-origin
---
clang/lib/Analysis/LifetimeSafety.cpp | 172 +++-
.../Sema/warn-lifetime-safety-dataflow.cpp| 260 +++---
2 files changed, 266 insertions(+), 166 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index dbbf7f3cc14b1..1b5837ff0004d 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -50,6 +50,11 @@ struct Loan {
Loan(LoanID id, AccessPath path, const Expr *IssueExpr)
: ID(id), Path(path), IssueExpr(IssueExpr) {}
+
+ void dump(llvm::raw_ostream &OS) const {
+OS << ID << " (Path: ";
+OS << Path.D->getNameAsString() << ")";
+ }
};
/// An Origin is a symbolic identifier that represents the set of possible
@@ -120,17 +125,19 @@ class OriginManager {
// TODO: Mark this method as const once we remove the call to getOrCreate.
OriginID get(const Expr &E) {
-// Origin of DeclRefExpr is that of the declaration it refers to.
+auto It = ExprToOriginID.find(&E);
+if (It != ExprToOriginID.end())
+ return It->second;
+// If the expression itself has no specific origin, and it's a reference
+// to a declaration, its origin is that of the declaration it refers to.
+// For pointer types, where we don't pre-emptively create an origin for the
+// DeclRefExpr itself.
if (const auto *DRE = dyn_cast(&E))
return get(*DRE->getDecl());
-auto It = ExprToOriginID.find(&E);
// TODO: This should be an assert(It != ExprToOriginID.end()). The current
// implementation falls back to getOrCreate to avoid crashing on
// yet-unhandled pointer expressions, creating an empty origin for them.
-if (It == ExprToOriginID.end())
- return getOrCreate(E);
-
-return It->second;
+return getOrCreate(E);
}
OriginID get(const ValueDecl &D) {
@@ -149,10 +156,6 @@ class OriginManager {
if (It != ExprToOriginID.end())
return It->second;
-if (const auto *DRE = dyn_cast(&E)) {
- // Origin of DeclRefExpr is that of the declaration it refers to.
- return getOrCreate(*DRE->getDecl());
-}
OriginID NewID = getNextOriginID();
addOrigin(NewID, E);
ExprToOriginID[&E] = NewID;
@@ -235,7 +238,8 @@ class Fact {
return nullptr;
}
- virtual void dump(llvm::raw_ostream &OS, const OriginManager &) const {
+ virtual void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &) const {
OS << "Fact (Kind: " << static_cast(K) << ")\n";
}
};
@@ -250,8 +254,11 @@ class IssueFact : public Fact {
IssueFact(LoanID LID, OriginID OID) : Fact(Kind::Issue), LID(LID), OID(OID)
{}
LoanID getLoanID() const { return LID; }
OriginID getOriginID() const { return OID; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
-OS << "Issue (LoanID: " << getLoanID() << ", ToOrigin: ";
+ void dump(llvm::raw_ostream &OS, const LoanManager &LM,
+const OriginManager &OM) const override {
+OS << "Issue (";
+LM.getLoan(getLoanID()).dump(OS);
+OS << ", ToOrigin: ";
OM.dump(getOriginID(), OS);
OS << ")\n";
}
@@ -270,8 +277,11 @@ class ExpireFact : public Fact {
LoanID getLoanID() const { return LID; }
SourceLocation getExpiryLoc() const { return ExpiryLoc; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
-OS << "Expire (LoanID: " << getLoanID() << ")\n";
+ void dump(llvm::raw_ostream &OS, const LoanManager &LM,
+const OriginManager &) const override {
+OS << "Expire (";
+LM.getLoan(getLoanID()).dump(OS);
+OS << ")\n";
}
};
@@ -288,7 +298,8 @@ class AssignOriginFact : public Fact {
: Fact(Kind::AssignOrigin), OIDDest(OIDDest), OIDSrc(OIDSrc) {}
OriginID getDestOriginID() const { return OIDDest; }
OriginID getSrcOriginID() const { return OIDSrc; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
+ void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &OM) const override {
OS << "AssignOrigin (Dest: ";
OM.dump(getDestOriginID(), OS);
OS << ", Src: ";
@@ -307,7 +318,8 @@ class ReturnOfOriginFact : public Fact {
ReturnOfOriginFact(OriginID OID) : Fact(Kind::ReturnOfOrigin), OID(OID) {}
OriginID getReturnedOriginID() const { return OID; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
+ void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &OM) const override {
OS << "ReturnOfOrigin (";
OM.dump(getReturnedOriginID(), OS);
OS << ")\n";
@@ -333,10 +345,11 @@ class UseFact : pub
[llvm-branch-commits] [llvm] [NFC][IR2Vec] Initialize Embedding vectors with zeros by default (PR #155690)
https://github.com/svkeerthy updated
https://github.com/llvm/llvm-project/pull/155690
>From 8c8500cd277936888d7031a503b5e3ce416469a3 Mon Sep 17 00:00:00 2001
From: svkeerthy
Date: Wed, 27 Aug 2025 20:25:30 +
Subject: [PATCH] Default constructor
---
llvm/include/llvm/Analysis/IR2Vec.h | 2 +-
llvm/lib/Analysis/IR2Vec.cpp| 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/Analysis/IR2Vec.h
b/llvm/include/llvm/Analysis/IR2Vec.h
index 4c2546323cb2c..b7b881999241e 100644
--- a/llvm/include/llvm/Analysis/IR2Vec.h
+++ b/llvm/include/llvm/Analysis/IR2Vec.h
@@ -92,7 +92,7 @@ struct Embedding {
Embedding(std::vector &&V) : Data(std::move(V)) {}
Embedding(std::initializer_list IL) : Data(IL) {}
- explicit Embedding(size_t Size) : Data(Size) {}
+ explicit Embedding(size_t Size) : Data(Size, 0.0) {}
Embedding(size_t Size, double InitialValue) : Data(Size, InitialValue) {}
size_t size() const { return Data.size(); }
diff --git a/llvm/lib/Analysis/IR2Vec.cpp b/llvm/lib/Analysis/IR2Vec.cpp
index cbaa8301d722b..98849fd922843 100644
--- a/llvm/lib/Analysis/IR2Vec.cpp
+++ b/llvm/lib/Analysis/IR2Vec.cpp
@@ -155,7 +155,7 @@ void Embedding::print(raw_ostream &OS) const {
Embedder::Embedder(const Function &F, const Vocabulary &Vocab)
: F(F), Vocab(Vocab), Dimension(Vocab.getDimension()),
OpcWeight(::OpcWeight), TypeWeight(::TypeWeight), ArgWeight(::ArgWeight),
- FuncVector(Embedding(Dimension, 0)) {}
+ FuncVector(Embedding(Dimension)) {}
std::unique_ptr Embedder::create(IR2VecKind Mode, const Function &F,
const Vocabulary &Vocab) {
@@ -472,7 +472,7 @@ void IR2VecVocabAnalysis::generateNumMappedVocab() {
// Handle Opcodes
std::vector NumericOpcodeEmbeddings(Vocabulary::MaxOpcodes,
- Embedding(Dim, 0));
+ Embedding(Dim));
NumericOpcodeEmbeddings.reserve(Vocabulary::MaxOpcodes);
for (unsigned Opcode : seq(0u, Vocabulary::MaxOpcodes)) {
StringRef VocabKey = Vocabulary::getVocabKeyForOpcode(Opcode + 1);
@@ -487,7 +487,7 @@ void IR2VecVocabAnalysis::generateNumMappedVocab() {
// Handle Types - only canonical types are present in vocabulary
std::vector NumericTypeEmbeddings(Vocabulary::MaxCanonicalTypeIDs,
- Embedding(Dim, 0));
+ Embedding(Dim));
NumericTypeEmbeddings.reserve(Vocabulary::MaxCanonicalTypeIDs);
for (unsigned CTypeID : seq(0u, Vocabulary::MaxCanonicalTypeIDs)) {
StringRef VocabKey = Vocabulary::getVocabKeyForCanonicalTypeID(
@@ -503,7 +503,7 @@ void IR2VecVocabAnalysis::generateNumMappedVocab() {
// Handle Arguments/Operands
std::vector NumericArgEmbeddings(Vocabulary::MaxOperandKinds,
- Embedding(Dim, 0));
+ Embedding(Dim));
NumericArgEmbeddings.reserve(Vocabulary::MaxOperandKinds);
for (unsigned OpKind : seq(0u, Vocabulary::MaxOperandKinds)) {
Vocabulary::OperandKind Kind =
static_cast(OpKind);
___
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[llvm-branch-commits] [lldb] release/21.x: [lldb][DWARFASTParserClang] Don't complete conflicting Objective-C++ types (#156681) (PR #156764)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/156764 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From e48805779b288d87477d2e7f9c8fcedcf3850511 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 6 ++
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..d874697185fac 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
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[llvm-branch-commits] [llvm] [IR] Add `MD_prof` to the `Keep` list of `dropUBImplyingAttrsAndMetadata` (PR #154635)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/154635
>From 6f1eaf036babb9f8a8f555aa6b930f60ef977ec6 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Wed, 20 Aug 2025 15:04:49 -0700
Subject: [PATCH] [Local] preserve `MD_prof` in `hoistAllInstructionsInto`
---
llvm/lib/IR/Instruction.cpp | 7 ---
llvm/lib/Transforms/Scalar/LICM.cpp | 5 +
.../Transforms/SimplifyCFG/PhiBlockMerge.ll | 21 ---
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp
index 5e87b5ff941ad..c1fafd759b5ab 100644
--- a/llvm/lib/IR/Instruction.cpp
+++ b/llvm/lib/IR/Instruction.cpp
@@ -553,16 +553,17 @@ void Instruction::dropUBImplyingAttrsAndUnknownMetadata(
}
void Instruction::dropUBImplyingAttrsAndMetadata(ArrayRef Keep) {
- // !annotation metadata does not impact semantics.
+ // !annotation and !prof metadata does not impact semantics.
// !range, !nonnull and !align produce poison, so they are safe to speculate.
// !noundef and various AA metadata must be dropped, as it generally produces
// immediate undefined behavior.
static const unsigned KnownIDs[] = {
LLVMContext::MD_annotation, LLVMContext::MD_range,
- LLVMContext::MD_nonnull, LLVMContext::MD_align};
+ LLVMContext::MD_nonnull, LLVMContext::MD_align, LLVMContext::MD_prof};
SmallVector KeepIDs;
KeepIDs.reserve(Keep.size() + std::size(KnownIDs));
- append_range(KeepIDs, KnownIDs);
+ append_range(KeepIDs, (!ProfcheckDisableMetadataFixes ? KnownIDs
+: drop_end(KnownIDs)));
append_range(KeepIDs, Keep);
dropUBImplyingAttrsAndUnknownMetadata(KeepIDs);
}
diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp
b/llvm/lib/Transforms/Scalar/LICM.cpp
index e157cc9212769..973a8aa0002c2 100644
--- a/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -1705,10 +1705,7 @@ static void hoist(Instruction &I, const DominatorTree
*DT, const Loop *CurLoop,
// time in isGuaranteedToExecute if we don't actually have anything to
// drop. It is a compile time optimization, not required for
correctness.
!SafetyInfo->isGuaranteedToExecute(I, DT, CurLoop)) {
-if (ProfcheckDisableMetadataFixes)
- I.dropUBImplyingAttrsAndMetadata();
-else
- I.dropUBImplyingAttrsAndMetadata({LLVMContext::MD_prof});
+I.dropUBImplyingAttrsAndMetadata();
}
if (isa(I))
diff --git a/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
b/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
index 2c5889a981db2..08397b5755a3f 100644
--- a/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
+++ b/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
@@ -1,20 +1,21 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
; Test merging of blocks that only have PHI nodes in them
;
; RUN: opt < %s -passes=simplifycfg
-simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
;
define i32 @test(i1 %a, i1 %b) {
-; CHECK-LABEL: @test(
-; CHECK: M:
-; CHECK-NEXT:[[DOT:%.*]] = select i1 %b, i32 0, i32 1
-; CHECK-NEXT:[[W:%.*]] = select i1 %a, i32 2, i32 [[DOT]]
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {
+; CHECK-NEXT: [[M:.*:]]
+; CHECK-NEXT:[[SPEC_SELECT:%.*]] = select i1 [[B]], i32 0, i32 1, !prof
[[PROF0:![0-9]+]]
+; CHECK-NEXT:[[W:%.*]] = select i1 [[A]], i32 2, i32 [[SPEC_SELECT]],
!prof [[PROF1:![0-9]+]]
; CHECK-NEXT:[[R:%.*]] = add i32 [[W]], 1
; CHECK-NEXT:ret i32 [[R]]
;
- br i1 %a, label %M, label %O
+ br i1 %a, label %M, label %O, !prof !0
O: ; preds = %0
- br i1 %b, label %N, label %Q
+ br i1 %b, label %N, label %Q, !prof !1
Q: ; preds = %O
br label %N
N: ; preds = %Q, %O
@@ -27,3 +28,9 @@ M: ; preds = %N, %0
ret i32 %R
}
+!0 = !{!"branch_weights", i32 11, i32 7}
+!1 = !{!"branch_weights", i32 3, i32 5}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 3, i32 5}
+; CHECK: [[PROF1]] = !{!"branch_weights", i32 11, i32 7}
+;.
___
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[llvm-branch-commits] [llvm] [NFC] Leave a comment in `Local.cpp` about debug info & sample profiling (PR #155296)
https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/155296 >From 2c17eab265e9a52176552dfbd07d6ffd60973f2f Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Mon, 25 Aug 2025 21:04:05 + Subject: [PATCH] [NFC] Leave a comment in `Local.cpp` about debug info & sample profiling --- llvm/lib/Transforms/Utils/Local.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 2cfd70a1746c8..57dc1b38b8ec3 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -3342,8 +3342,11 @@ void llvm::hoistAllInstructionsInto(BasicBlock *DomBlock, Instruction *InsertPt, // retain their original debug locations (DILocations) and debug intrinsic // instructions. // - // Doing so would degrade the debugging experience and adversely affect the - // accuracy of profiling information. + // Doing so would degrade the debugging experience. + // + // FIXME: Issue #152767: debug info should also be the same as the + // original branch, **if** the user explicitly indicated that (for sampling + // PGO) // // Currently, when hoisting the instructions, we take the following actions: // - Remove their debug intrinsic instructions. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/154426
>From 80e4431563d62682ee72fd506123cca172c14cca Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 19 Aug 2025 14:35:01 -0700
Subject: [PATCH] [SimplfyCFG] Set `MD_prof` for `select` used for certain
conditional simplifications
---
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 34 ++-
.../SimplifyCFG/branch-fold-threshold.ll | 29 +++-
.../Transforms/SimplifyCFG/branch-fold.ll | 18 +++---
3 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 86d4750f6f000..66d6dbac8e90b 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -203,6 +203,8 @@ static cl::opt MaxJumpThreadingLiveBlocks(
cl::desc("Limit number of blocks a define in a threaded block is allowed "
"to be live in"));
+extern cl::opt ProfcheckDisableMetadataFixes;
+
STATISTIC(NumBitMaps, "Number of switch instructions turned into bitmaps");
STATISTIC(NumLinearMaps,
"Number of switch instructions turned into linear mapping");
@@ -330,6 +332,16 @@ class SimplifyCFGOpt {
}
};
+// we synthesize a || b as select a, true, b
+// we synthesize a && b as select a, b, false
+// this function determines if SI is playing one of those roles.
+bool isSelectInRoleOfConjunctionOrDisjunction(const SelectInst *SI) {
+ return ((isa(SI->getTrueValue()) &&
+ (dyn_cast(SI->getTrueValue())->isOne())) ||
+ (isa(SI->getFalseValue()) &&
+ (dyn_cast(SI->getFalseValue())->isNullValue(;
+}
+
} // end anonymous namespace
/// Return true if all the PHI nodes in the basic block \p BB
@@ -4028,6 +4040,7 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
// Try to update branch weights.
uint64_t PredTrueWeight, PredFalseWeight, SuccTrueWeight, SuccFalseWeight;
+ SmallVector MDWeights;
if (extractPredSuccWeights(PBI, BI, PredTrueWeight, PredFalseWeight,
SuccTrueWeight, SuccFalseWeight)) {
SmallVector NewWeights;
@@ -4058,7 +4071,7 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
// Halve the weights if any of them cannot fit in an uint32_t
fitWeights(NewWeights);
-SmallVector MDWeights(NewWeights.begin(), NewWeights.end());
+append_range(MDWeights, NewWeights);
setBranchWeights(PBI, MDWeights[0], MDWeights[1], /*IsExpected=*/false);
// TODO: If BB is reachable from all paths through PredBlock, then we
@@ -4095,6 +4108,13 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
Value *BICond = VMap[BI->getCondition()];
PBI->setCondition(
createLogicalOp(Builder, Opc, PBI->getCondition(), BICond, "or.cond"));
+ if (!ProfcheckDisableMetadataFixes)
+if (auto *SI = dyn_cast(PBI->getCondition()))
+ if (!MDWeights.empty()) {
+assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
+setBranchWeights(SI, MDWeights[0], MDWeights[1],
+ /*IsExpected=*/false);
+ }
++NumFoldBranchToCommonDest;
return true;
@@ -4793,6 +4813,18 @@ static bool SimplifyCondBranchToCondBranch(BranchInst
*PBI, BranchInst *BI,
fitWeights(NewWeights);
setBranchWeights(PBI, NewWeights[0], NewWeights[1], /*IsExpected=*/false);
+// Cond may be a select instruction with the first operand set to "true",
or
+// the second to "false" (see how createLogicalOp works for `and` and `or`)
+if (!ProfcheckDisableMetadataFixes)
+ if (auto *SI = dyn_cast(Cond)) {
+assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
+// The select is predicated on PBICond
+assert(dyn_cast(SI)->getCondition() == PBICond);
+// The corresponding probabilities are what was referred to above as
+// PredCommon and PredOther.
+setBranchWeights(SI, PredCommon, PredOther,
+ /*IsExpected=*/false);
+ }
}
// OtherDest may have phi nodes. If so, add an entry from PBI's
diff --git a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
index 4384847ce156b..71ad069fb8d06 100644
--- a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
+++ b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1
-S | FileCheck %s --check-prefixes=NORMAL,BASELINE
; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1
-S -bonus-inst-threshold=2 | FileCheck %s --check-
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/154426
>From 80e4431563d62682ee72fd506123cca172c14cca Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 19 Aug 2025 14:35:01 -0700
Subject: [PATCH] [SimplfyCFG] Set `MD_prof` for `select` used for certain
conditional simplifications
---
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 34 ++-
.../SimplifyCFG/branch-fold-threshold.ll | 29 +++-
.../Transforms/SimplifyCFG/branch-fold.ll | 18 +++---
3 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 86d4750f6f000..66d6dbac8e90b 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -203,6 +203,8 @@ static cl::opt MaxJumpThreadingLiveBlocks(
cl::desc("Limit number of blocks a define in a threaded block is allowed "
"to be live in"));
+extern cl::opt ProfcheckDisableMetadataFixes;
+
STATISTIC(NumBitMaps, "Number of switch instructions turned into bitmaps");
STATISTIC(NumLinearMaps,
"Number of switch instructions turned into linear mapping");
@@ -330,6 +332,16 @@ class SimplifyCFGOpt {
}
};
+// we synthesize a || b as select a, true, b
+// we synthesize a && b as select a, b, false
+// this function determines if SI is playing one of those roles.
+bool isSelectInRoleOfConjunctionOrDisjunction(const SelectInst *SI) {
+ return ((isa(SI->getTrueValue()) &&
+ (dyn_cast(SI->getTrueValue())->isOne())) ||
+ (isa(SI->getFalseValue()) &&
+ (dyn_cast(SI->getFalseValue())->isNullValue(;
+}
+
} // end anonymous namespace
/// Return true if all the PHI nodes in the basic block \p BB
@@ -4028,6 +4040,7 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
// Try to update branch weights.
uint64_t PredTrueWeight, PredFalseWeight, SuccTrueWeight, SuccFalseWeight;
+ SmallVector MDWeights;
if (extractPredSuccWeights(PBI, BI, PredTrueWeight, PredFalseWeight,
SuccTrueWeight, SuccFalseWeight)) {
SmallVector NewWeights;
@@ -4058,7 +4071,7 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
// Halve the weights if any of them cannot fit in an uint32_t
fitWeights(NewWeights);
-SmallVector MDWeights(NewWeights.begin(), NewWeights.end());
+append_range(MDWeights, NewWeights);
setBranchWeights(PBI, MDWeights[0], MDWeights[1], /*IsExpected=*/false);
// TODO: If BB is reachable from all paths through PredBlock, then we
@@ -4095,6 +4108,13 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
Value *BICond = VMap[BI->getCondition()];
PBI->setCondition(
createLogicalOp(Builder, Opc, PBI->getCondition(), BICond, "or.cond"));
+ if (!ProfcheckDisableMetadataFixes)
+if (auto *SI = dyn_cast(PBI->getCondition()))
+ if (!MDWeights.empty()) {
+assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
+setBranchWeights(SI, MDWeights[0], MDWeights[1],
+ /*IsExpected=*/false);
+ }
++NumFoldBranchToCommonDest;
return true;
@@ -4793,6 +4813,18 @@ static bool SimplifyCondBranchToCondBranch(BranchInst
*PBI, BranchInst *BI,
fitWeights(NewWeights);
setBranchWeights(PBI, NewWeights[0], NewWeights[1], /*IsExpected=*/false);
+// Cond may be a select instruction with the first operand set to "true",
or
+// the second to "false" (see how createLogicalOp works for `and` and `or`)
+if (!ProfcheckDisableMetadataFixes)
+ if (auto *SI = dyn_cast(Cond)) {
+assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
+// The select is predicated on PBICond
+assert(dyn_cast(SI)->getCondition() == PBICond);
+// The corresponding probabilities are what was referred to above as
+// PredCommon and PredOther.
+setBranchWeights(SI, PredCommon, PredOther,
+ /*IsExpected=*/false);
+ }
}
// OtherDest may have phi nodes. If so, add an entry from PBI's
diff --git a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
index 4384847ce156b..71ad069fb8d06 100644
--- a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
+++ b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1
-S | FileCheck %s --check-prefixes=NORMAL,BASELINE
; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1
-S -bonus-inst-threshold=2 | FileCheck %s --check-
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
@@ -4058,7 +4068,7 @@ static bool performBranchToCommonDestFolding(BranchInst *BI, BranchInst *PBI, // Halve the weights if any of them cannot fit in an uint32_t fitWeights(NewWeights); -SmallVector MDWeights(NewWeights.begin(), NewWeights.end()); +append_range(MDWeights, NewWeights); mtrofin wrote: I need `MDWeights` in the newly introduced code. https://github.com/llvm/llvm-project/pull/154426 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NFC] Leave a comment in `Local.cpp` about debug info & sample profiling (PR #155296)
https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/155296 >From d8edb04b381fa8d955d23bfee0d3b322d359bf8a Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Mon, 25 Aug 2025 21:04:05 + Subject: [PATCH] [NFC] Leave a comment in `Local.cpp` about debug info & sample profiling --- llvm/lib/Transforms/Utils/Local.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 2cfd70a1746c8..57dc1b38b8ec3 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -3342,8 +3342,11 @@ void llvm::hoistAllInstructionsInto(BasicBlock *DomBlock, Instruction *InsertPt, // retain their original debug locations (DILocations) and debug intrinsic // instructions. // - // Doing so would degrade the debugging experience and adversely affect the - // accuracy of profiling information. + // Doing so would degrade the debugging experience. + // + // FIXME: Issue #152767: debug info should also be the same as the + // original branch, **if** the user explicitly indicated that (for sampling + // PGO) // // Currently, when hoisting the instructions, we take the following actions: // - Remove their debug intrinsic instructions. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
https://github.com/david-xl approved this pull request. https://github.com/llvm/llvm-project/pull/154426 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Clang] Introduce -fsanitize=alloc-token (PR #156844)
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Marco Elver (melver)
Changes
Introduce the `-fsanitize=alloc-token` command-line option, hooking up
the AllocToken pass -- it provides allocation tokens to compatible
runtime allocators, enabling different heap organization strategies,
e.g. hardening schemes based on heap partitioning.
The instrumentation rewrites standard allocation calls into variants
that accept an additional `uint64_t token_id` argument. For example,
calls to `malloc(size)` become `__alloc_token_malloc(size, token_id)`,
and a C++ `new MyType` expression will call `__alloc_token_Znwm(size,
token_id)`.
Currently untyped allocation calls do not yet have `!alloc_token_hint`
metadata, and therefore receive the fallback token only. This will be
fixed in subsequent changes through best-effort type-inference.
One benefit of the instrumentation approach is that it can be applied
transparently to large codebases, and scales in deployment as other
sanitizers.
Similarly to other sanitizers, instrumentation can selectively be
controlled using `__attribute__((no_sanitize("alloc-token")))`. Support
for sanitizer ignorelists to disable instrumentation for specific
functions or source files is implemented.
See clang/docs/AllocToken.rst for more usage instructions.
Link:
https://discourse.llvm.org/t/rfc-a-framework-for-allocator-partitioning-hints/87434
---
Patch is 40.74 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/156844.diff
25 Files Affected:
- (added) clang/docs/AllocToken.rst (+172)
- (modified) clang/docs/ReleaseNotes.rst (+4)
- (modified) clang/docs/UsersManual.rst (+2)
- (modified) clang/docs/index.rst (+1)
- (modified) clang/include/clang/Basic/CodeGenOptions.def (+2)
- (modified) clang/include/clang/Basic/CodeGenOptions.h (+3)
- (modified) clang/include/clang/Basic/Sanitizers.def (+3)
- (modified) clang/include/clang/Driver/Options.td (+17)
- (modified) clang/include/clang/Driver/SanitizerArgs.h (+3-1)
- (modified) clang/lib/CodeGen/BackendUtil.cpp (+20)
- (modified) clang/lib/CodeGen/CGExpr.cpp (+16)
- (modified) clang/lib/CodeGen/CGExprCXX.cpp (+10-5)
- (modified) clang/lib/CodeGen/CodeGenFunction.cpp (+2)
- (modified) clang/lib/CodeGen/CodeGenFunction.h (+3)
- (modified) clang/lib/Driver/SanitizerArgs.cpp (+27-4)
- (modified) clang/lib/Driver/ToolChains/BareMetal.cpp (+1)
- (modified) clang/lib/Driver/ToolChains/Clang.cpp (+2)
- (modified) clang/lib/Driver/ToolChains/Linux.cpp (+1)
- (modified) clang/lib/Frontend/CompilerInvocation.cpp (+14)
- (modified) clang/lib/Frontend/InitPreprocessor.cpp (+2)
- (added) clang/test/CodeGen/alloc-token-ignorelist.c (+27)
- (added) clang/test/CodeGen/alloc-token.c (+45)
- (added) clang/test/CodeGenCXX/alloc-token.cpp (+157)
- (added) clang/test/Driver/fsanitize-alloc-token.c (+43)
- (added) clang/test/Preprocessor/alloc_token.cpp (+10)
``diff
diff --git a/clang/docs/AllocToken.rst b/clang/docs/AllocToken.rst
new file mode 100644
index 0..a7bb8877f371b
--- /dev/null
+++ b/clang/docs/AllocToken.rst
@@ -0,0 +1,172 @@
+=
+Allocation Tokens
+=
+
+.. contents::
+ :local:
+
+Introduction
+
+
+Clang provides support for allocation tokens to enable allocator-level heap
+organization strategies. Clang assigns mode-dependent token IDs to allocation
+calls; the runtime behavior depends entirely on the implementation of a
+compatible memory allocator.
+
+Possible allocator strategies include:
+
+* **Security Hardening**: Placing allocations into separate, isolated heap
+ partitions. For example, separating pointer-containing types from raw data
+ can mitigate exploits that rely on overflowing a primitive buffer to corrupt
+ object metadata.
+
+* **Memory Layout Optimization**: Grouping related allocations to improve data
+ locality and cache utilization.
+
+* **Custom Allocation Policies**: Applying different management strategies to
+ different partitions.
+
+Token Assignment Mode
+=
+
+The default mode to calculate tokens is:
+
+* *TypeHash* (mode=2): This mode assigns a token ID based on the hash of
+ the allocated type's name.
+
+Other token ID assignment modes are supported, but they may be subject to
+change or removal. These may (experimentally) be selected with ``-mllvm
+-alloc-token-mode=``:
+
+* *Random* (mode=1): This mode assigns a statically-determined random token ID
+ to each allocation site.
+
+* *Increment* (mode=0): This mode assigns a simple, incrementally increasing
+ token ID to each allocation site.
+
+Allocation Token Instrumentation
+
+
+To enable instrumentation of allocation functions, code can be compiled with
+the ``-fsanitize=alloc-token`` flag:
+
+.. code-block:: console
+
+% clang++ -fsanitize=alloc-token example.cc
+
+The instrumentation transforms allocation calls to include a token ID. For
+example:
+
+..
[llvm-branch-commits] [llvm] [IR] Add `MD_prof` to the `Keep` list of `dropUBImplyingAttrsAndMetadata` (PR #154635)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/154635
>From 03284b69e33a088dd7505f7160cb5e7fd0a8928a Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Wed, 20 Aug 2025 15:04:49 -0700
Subject: [PATCH] [Local] preserve `MD_prof` in `hoistAllInstructionsInto`
---
llvm/lib/IR/Instruction.cpp | 7 ---
llvm/lib/Transforms/Scalar/LICM.cpp | 5 +
.../Transforms/SimplifyCFG/PhiBlockMerge.ll | 21 ---
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp
index 5e87b5ff941ad..c1fafd759b5ab 100644
--- a/llvm/lib/IR/Instruction.cpp
+++ b/llvm/lib/IR/Instruction.cpp
@@ -553,16 +553,17 @@ void Instruction::dropUBImplyingAttrsAndUnknownMetadata(
}
void Instruction::dropUBImplyingAttrsAndMetadata(ArrayRef Keep) {
- // !annotation metadata does not impact semantics.
+ // !annotation and !prof metadata does not impact semantics.
// !range, !nonnull and !align produce poison, so they are safe to speculate.
// !noundef and various AA metadata must be dropped, as it generally produces
// immediate undefined behavior.
static const unsigned KnownIDs[] = {
LLVMContext::MD_annotation, LLVMContext::MD_range,
- LLVMContext::MD_nonnull, LLVMContext::MD_align};
+ LLVMContext::MD_nonnull, LLVMContext::MD_align, LLVMContext::MD_prof};
SmallVector KeepIDs;
KeepIDs.reserve(Keep.size() + std::size(KnownIDs));
- append_range(KeepIDs, KnownIDs);
+ append_range(KeepIDs, (!ProfcheckDisableMetadataFixes ? KnownIDs
+: drop_end(KnownIDs)));
append_range(KeepIDs, Keep);
dropUBImplyingAttrsAndUnknownMetadata(KeepIDs);
}
diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp
b/llvm/lib/Transforms/Scalar/LICM.cpp
index e157cc9212769..973a8aa0002c2 100644
--- a/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -1705,10 +1705,7 @@ static void hoist(Instruction &I, const DominatorTree
*DT, const Loop *CurLoop,
// time in isGuaranteedToExecute if we don't actually have anything to
// drop. It is a compile time optimization, not required for
correctness.
!SafetyInfo->isGuaranteedToExecute(I, DT, CurLoop)) {
-if (ProfcheckDisableMetadataFixes)
- I.dropUBImplyingAttrsAndMetadata();
-else
- I.dropUBImplyingAttrsAndMetadata({LLVMContext::MD_prof});
+I.dropUBImplyingAttrsAndMetadata();
}
if (isa(I))
diff --git a/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
b/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
index 2c5889a981db2..08397b5755a3f 100644
--- a/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
+++ b/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
@@ -1,20 +1,21 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
; Test merging of blocks that only have PHI nodes in them
;
; RUN: opt < %s -passes=simplifycfg
-simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
;
define i32 @test(i1 %a, i1 %b) {
-; CHECK-LABEL: @test(
-; CHECK: M:
-; CHECK-NEXT:[[DOT:%.*]] = select i1 %b, i32 0, i32 1
-; CHECK-NEXT:[[W:%.*]] = select i1 %a, i32 2, i32 [[DOT]]
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {
+; CHECK-NEXT: [[M:.*:]]
+; CHECK-NEXT:[[SPEC_SELECT:%.*]] = select i1 [[B]], i32 0, i32 1, !prof
[[PROF0:![0-9]+]]
+; CHECK-NEXT:[[W:%.*]] = select i1 [[A]], i32 2, i32 [[SPEC_SELECT]],
!prof [[PROF1:![0-9]+]]
; CHECK-NEXT:[[R:%.*]] = add i32 [[W]], 1
; CHECK-NEXT:ret i32 [[R]]
;
- br i1 %a, label %M, label %O
+ br i1 %a, label %M, label %O, !prof !0
O: ; preds = %0
- br i1 %b, label %N, label %Q
+ br i1 %b, label %N, label %Q, !prof !1
Q: ; preds = %O
br label %N
N: ; preds = %Q, %O
@@ -27,3 +28,9 @@ M: ; preds = %N, %0
ret i32 %R
}
+!0 = !{!"branch_weights", i32 11, i32 7}
+!1 = !{!"branch_weights", i32 3, i32 5}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 3, i32 5}
+; CHECK: [[PROF1]] = !{!"branch_weights", i32 11, i32 7}
+;.
___
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[llvm-branch-commits] [llvm] [IR] Add `MD_prof` to the `Keep` list of `dropUBImplyingAttrsAndMetadata` (PR #154635)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/154635
>From 03284b69e33a088dd7505f7160cb5e7fd0a8928a Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Wed, 20 Aug 2025 15:04:49 -0700
Subject: [PATCH] [Local] preserve `MD_prof` in `hoistAllInstructionsInto`
---
llvm/lib/IR/Instruction.cpp | 7 ---
llvm/lib/Transforms/Scalar/LICM.cpp | 5 +
.../Transforms/SimplifyCFG/PhiBlockMerge.ll | 21 ---
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp
index 5e87b5ff941ad..c1fafd759b5ab 100644
--- a/llvm/lib/IR/Instruction.cpp
+++ b/llvm/lib/IR/Instruction.cpp
@@ -553,16 +553,17 @@ void Instruction::dropUBImplyingAttrsAndUnknownMetadata(
}
void Instruction::dropUBImplyingAttrsAndMetadata(ArrayRef Keep) {
- // !annotation metadata does not impact semantics.
+ // !annotation and !prof metadata does not impact semantics.
// !range, !nonnull and !align produce poison, so they are safe to speculate.
// !noundef and various AA metadata must be dropped, as it generally produces
// immediate undefined behavior.
static const unsigned KnownIDs[] = {
LLVMContext::MD_annotation, LLVMContext::MD_range,
- LLVMContext::MD_nonnull, LLVMContext::MD_align};
+ LLVMContext::MD_nonnull, LLVMContext::MD_align, LLVMContext::MD_prof};
SmallVector KeepIDs;
KeepIDs.reserve(Keep.size() + std::size(KnownIDs));
- append_range(KeepIDs, KnownIDs);
+ append_range(KeepIDs, (!ProfcheckDisableMetadataFixes ? KnownIDs
+: drop_end(KnownIDs)));
append_range(KeepIDs, Keep);
dropUBImplyingAttrsAndUnknownMetadata(KeepIDs);
}
diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp
b/llvm/lib/Transforms/Scalar/LICM.cpp
index e157cc9212769..973a8aa0002c2 100644
--- a/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -1705,10 +1705,7 @@ static void hoist(Instruction &I, const DominatorTree
*DT, const Loop *CurLoop,
// time in isGuaranteedToExecute if we don't actually have anything to
// drop. It is a compile time optimization, not required for
correctness.
!SafetyInfo->isGuaranteedToExecute(I, DT, CurLoop)) {
-if (ProfcheckDisableMetadataFixes)
- I.dropUBImplyingAttrsAndMetadata();
-else
- I.dropUBImplyingAttrsAndMetadata({LLVMContext::MD_prof});
+I.dropUBImplyingAttrsAndMetadata();
}
if (isa(I))
diff --git a/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
b/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
index 2c5889a981db2..08397b5755a3f 100644
--- a/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
+++ b/llvm/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
@@ -1,20 +1,21 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
; Test merging of blocks that only have PHI nodes in them
;
; RUN: opt < %s -passes=simplifycfg
-simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
;
define i32 @test(i1 %a, i1 %b) {
-; CHECK-LABEL: @test(
-; CHECK: M:
-; CHECK-NEXT:[[DOT:%.*]] = select i1 %b, i32 0, i32 1
-; CHECK-NEXT:[[W:%.*]] = select i1 %a, i32 2, i32 [[DOT]]
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {
+; CHECK-NEXT: [[M:.*:]]
+; CHECK-NEXT:[[SPEC_SELECT:%.*]] = select i1 [[B]], i32 0, i32 1, !prof
[[PROF0:![0-9]+]]
+; CHECK-NEXT:[[W:%.*]] = select i1 [[A]], i32 2, i32 [[SPEC_SELECT]],
!prof [[PROF1:![0-9]+]]
; CHECK-NEXT:[[R:%.*]] = add i32 [[W]], 1
; CHECK-NEXT:ret i32 [[R]]
;
- br i1 %a, label %M, label %O
+ br i1 %a, label %M, label %O, !prof !0
O: ; preds = %0
- br i1 %b, label %N, label %Q
+ br i1 %b, label %N, label %Q, !prof !1
Q: ; preds = %O
br label %N
N: ; preds = %Q, %O
@@ -27,3 +28,9 @@ M: ; preds = %N, %0
ret i32 %R
}
+!0 = !{!"branch_weights", i32 11, i32 7}
+!1 = !{!"branch_weights", i32 3, i32 5}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 3, i32 5}
+; CHECK: [[PROF1]] = !{!"branch_weights", i32 11, i32 7}
+;.
___
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[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov ready_for_review https://github.com/llvm/llvm-project/pull/156359 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/154426
>From 1f876ac5aa21df6856129f60d22808b2c64620b2 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 19 Aug 2025 14:35:01 -0700
Subject: [PATCH] [SimplfyCFG] Set `MD_prof` for `select` used for certain
conditional simplifications
---
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 34 ++-
.../SimplifyCFG/branch-fold-threshold.ll | 29 +++-
.../Transforms/SimplifyCFG/branch-fold.ll | 18 +++---
3 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 86d4750f6f000..66d6dbac8e90b 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -203,6 +203,8 @@ static cl::opt MaxJumpThreadingLiveBlocks(
cl::desc("Limit number of blocks a define in a threaded block is allowed "
"to be live in"));
+extern cl::opt ProfcheckDisableMetadataFixes;
+
STATISTIC(NumBitMaps, "Number of switch instructions turned into bitmaps");
STATISTIC(NumLinearMaps,
"Number of switch instructions turned into linear mapping");
@@ -330,6 +332,16 @@ class SimplifyCFGOpt {
}
};
+// we synthesize a || b as select a, true, b
+// we synthesize a && b as select a, b, false
+// this function determines if SI is playing one of those roles.
+bool isSelectInRoleOfConjunctionOrDisjunction(const SelectInst *SI) {
+ return ((isa(SI->getTrueValue()) &&
+ (dyn_cast(SI->getTrueValue())->isOne())) ||
+ (isa(SI->getFalseValue()) &&
+ (dyn_cast(SI->getFalseValue())->isNullValue(;
+}
+
} // end anonymous namespace
/// Return true if all the PHI nodes in the basic block \p BB
@@ -4028,6 +4040,7 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
// Try to update branch weights.
uint64_t PredTrueWeight, PredFalseWeight, SuccTrueWeight, SuccFalseWeight;
+ SmallVector MDWeights;
if (extractPredSuccWeights(PBI, BI, PredTrueWeight, PredFalseWeight,
SuccTrueWeight, SuccFalseWeight)) {
SmallVector NewWeights;
@@ -4058,7 +4071,7 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
// Halve the weights if any of them cannot fit in an uint32_t
fitWeights(NewWeights);
-SmallVector MDWeights(NewWeights.begin(), NewWeights.end());
+append_range(MDWeights, NewWeights);
setBranchWeights(PBI, MDWeights[0], MDWeights[1], /*IsExpected=*/false);
// TODO: If BB is reachable from all paths through PredBlock, then we
@@ -4095,6 +4108,13 @@ static bool performBranchToCommonDestFolding(BranchInst
*BI, BranchInst *PBI,
Value *BICond = VMap[BI->getCondition()];
PBI->setCondition(
createLogicalOp(Builder, Opc, PBI->getCondition(), BICond, "or.cond"));
+ if (!ProfcheckDisableMetadataFixes)
+if (auto *SI = dyn_cast(PBI->getCondition()))
+ if (!MDWeights.empty()) {
+assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
+setBranchWeights(SI, MDWeights[0], MDWeights[1],
+ /*IsExpected=*/false);
+ }
++NumFoldBranchToCommonDest;
return true;
@@ -4793,6 +4813,18 @@ static bool SimplifyCondBranchToCondBranch(BranchInst
*PBI, BranchInst *BI,
fitWeights(NewWeights);
setBranchWeights(PBI, NewWeights[0], NewWeights[1], /*IsExpected=*/false);
+// Cond may be a select instruction with the first operand set to "true",
or
+// the second to "false" (see how createLogicalOp works for `and` and `or`)
+if (!ProfcheckDisableMetadataFixes)
+ if (auto *SI = dyn_cast(Cond)) {
+assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
+// The select is predicated on PBICond
+assert(dyn_cast(SI)->getCondition() == PBICond);
+// The corresponding probabilities are what was referred to above as
+// PredCommon and PredOther.
+setBranchWeights(SI, PredCommon, PredOther,
+ /*IsExpected=*/false);
+ }
}
// OtherDest may have phi nodes. If so, add an entry from PBI's
diff --git a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
index 4384847ce156b..71ad069fb8d06 100644
--- a/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
+++ b/llvm/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1
-S | FileCheck %s --check-prefixes=NORMAL,BASELINE
; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1
-S -bonus-inst-threshold=2 | FileCheck %s --check-
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
@@ -4058,7 +4068,7 @@ static bool performBranchToCommonDestFolding(BranchInst *BI, BranchInst *PBI, // Halve the weights if any of them cannot fit in an uint32_t fitWeights(NewWeights); -SmallVector MDWeights(NewWeights.begin(), NewWeights.end()); +append_range(MDWeights, NewWeights); david-xl wrote: Why this change? https://github.com/llvm/llvm-project/pull/154426 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SimplfyCFG] Set `MD_prof` for `select` used for certain conditional simplifications (PR #154426)
@@ -330,6 +332,13 @@ class SimplifyCFGOpt {
}
};
+bool isSelectInRoleOfConjunctionOrDisjunction(const SelectInst *SI) {
david-xl wrote:
Add a comment for the method.
https://github.com/llvm/llvm-project/pull/154426
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[llvm-branch-commits] [compiler-rt] release/21.x: [rtsan] Add versioned pthread_cond interceptors (#155970) (PR #156196)
cjappl wrote: Closing - the original reporter has a viable workaround and is OK waiting until 22. https://github.com/llvm/llvm-project/pull/156196 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/21.x: [rtsan] Add versioned pthread_cond interceptors (#155970) (PR #156196)
https://github.com/cjappl closed https://github.com/llvm/llvm-project/pull/156196 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] X86: Stop using MachineFunction in getPointerRegClass (PR #156880)
https://github.com/KanRobert approved this pull request. https://github.com/llvm/llvm-project/pull/156880 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Add more tests for flat/global atomicrmw with agprs (PR #156874)
@@ -1,381 +1,633 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -check-prefixes=CHECK,GFX90A %s arsenm wrote: It doesn't really matter, these aren't even testing different entry points https://github.com/llvm/llvm-project/pull/156874 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ARM] Remove most post-decoding instruction adjustments (PR #156540)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From 408cfbc73717240b713f59a393dcc609004dd6ff Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
---
llvm/lib/Target/ARM/ARMInstrCDE.td| 4 +
llvm/lib/Target/ARM/ARMInstrFormats.td| 9 +-
llvm/lib/Target/ARM/ARMInstrMVE.td| 1 +
llvm/lib/Target/ARM/ARMInstrThumb.td | 10 +
llvm/lib/Target/ARM/ARMInstrThumb2.td | 23 +-
llvm/lib/Target/ARM/CMakeLists.txt| 3 +-
.../ARM/Disassembler/ARMDisassembler.cpp | 364 +++---
llvm/test/MC/Disassembler/ARM/arm-tests.txt | 2 +-
8 files changed, 267 insertions(+), 149 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrCDE.td
b/llvm/lib/Target/ARM/ARMInstrCDE.td
index 54e27a6be5583..5d4e3acf5b581 100644
--- a/llvm/lib/Target/ARM/ARMInstrCDE.td
+++ b/llvm/lib/Target/ARM/ARMInstrCDE.td
@@ -115,6 +115,7 @@ class CDE_CX1_Instr
!con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
params.Cstr> {
+ bits<0> p;
bits<13> imm;
bits<4> Rd;
@@ -131,6 +132,7 @@ class CDE_CX2_Instr
!con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
params.Cstr> {
+ bits<0> p;
bits<9> imm;
bits<4> Rd;
bits<4> Rn;
@@ -149,6 +151,7 @@ class CDE_CX3_Instr
!con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm,
$imm"),
params.Cstr> {
+ bits<0> p;
bits<6> imm;
bits<4> Rd;
bits<4> Rn;
@@ -268,6 +271,7 @@ class CDE_Vec_Instr,
CDE_RequiresQReg {
+ bits<0> vp;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td
b/llvm/lib/Target/ARM/ARMInstrFormats.td
index e50740f7d57c5..dc815e1124fa5 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -1219,6 +1219,8 @@ class Thumb1sI pattern>
: InstThumb {
+ bits<0> s;
+ bits<0> p;
let OutOperandList = !con(oops, (outs s_cc_out:$s));
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${s}${p}", asm);
@@ -1243,6 +1245,7 @@ class Thumb1pI pattern>
: InstThumb {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1341,7 +1344,8 @@ class T1Misc opcode> : Encoding16 {
class Thumb2I pattern>
- : InstARM {
+: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1360,6 +1364,7 @@ class Thumb2sI pattern>
: InstARM {
+ bits<0> p;
bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
let Inst{20} = s;
@@ -2220,6 +2225,7 @@ class NeonI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
@@ -2233,6 +2239,7 @@ class NeonXI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", "\t", asm);
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td
b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 9dffd945d5baa..e24413465799f 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -409,6 +409,7 @@ class MVE_p {
+ bits<0> vp;
let Inst{31-29} = 0b111;
let Inst{27-26} = 0b11;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td
b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 0c5ea3e0fa8d5..bc1b34c691e39 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -483,6 +483,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
// A6.2.3 & A8.6.25
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b000;
@@ -491,6 +492,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
Requires<[IsThumb, Has8MSecExt]>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b100;
@@ -523,6 +525,7 @@ let isCall = 1,
"bl${p}\t$func",
[(ARMcall tglobaladdr:$func)]>,
Requires<[IsThumb]>, Sched<[WriteBrL]> {
+bits<0> p;
bits<24> func;
let Inst{26} = func{23};
[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 32e1a07943e330424c87c405e9021b61af005d73 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 ++-
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 --
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4 +++
5 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 720361dc3da5b..531238ae85029 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc
-gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- --specialize-decoders-per-bitwidth
- -ignore-non-decodable-operands)
+ --specialize-decoders-per-bitwidth)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b1b7ea5246fda..89df9d82f8780 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,12 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +604,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -774,12 +769,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bit
[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 54a58aba634a49079976dd9733a320b522f483aa Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
These instructions can now be fully decoded automatically.
---
llvm/lib/Target/Hexagon/CMakeLists.txt| 3 +-
.../Disassembler/HexagonDisassembler.cpp | 65 ++---
.../Target/Hexagon/HexagonDepInstrFormats.td | 129 --
llvm/lib/Target/Hexagon/HexagonOperands.td| 10 +-
4 files changed, 49 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt
b/llvm/lib/Target/Hexagon/CMakeLists.txt
index b615536af03be..d758260a8ab5d 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de10092cbe3c8..0639878c1256f 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -173,6 +173,19 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned
tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);
+
+static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MCContext &Ctx = Decoder->getContext();
+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
+ return DecodeStatus::Success;
+}
+
+static DecodeStatus sgp10ConstDecoder(MCInst &MI,
+ const MCDisassembler *Decoder) {
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ return DecodeStatus::Success;
+}
+
#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"
@@ -349,21 +362,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr)
const {
}
}
-static void adjustDuplex(MCInst &MI, MCContext &Context) {
- switch (MI.getOpcode()) {
- case Hexagon::SA1_setin1:
-MI.insert(MI.begin() + 1,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- case Hexagon::SA1_dec:
-MI.insert(MI.begin() + 2,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- default:
-break;
- }
-}
-
DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef Bytes,
uint64_t Address,
@@ -468,12 +466,10 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
@@ -499,41 +495,6 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
}
- switch (MI.getOpcode()) {
- case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_f_jumpnv_t:
- case Hexagon::J4_cmpeqn1_fp0_jump_nt:
- case Hexagon::J4_cmpeqn1_fp0_jump_t:
- case Hexagon::J4_cmpeqn1_fp1_jump_nt:
- case Hexagon::J4_cmpeqn1_fp1_jump_t:
- case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_t_jumpnv_t:
- case Hexagon::J4_cmpeqn1_tp0_jump_nt:
- case Hexagon::J4_cmpeqn1_tp0_jump_t:
- case Hexagon::J4_cmpeqn1_tp1_jump_nt:
- case Hexagon::J4_cmpeqn1_tp1_jump_t:
- case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_f_jumpnv_t:
- case Hexagon::J4_cmpgtn1_fp0_jump_nt:
- case Hexagon::J4_cmpgtn1_fp0_jump_t:
- case Hexagon::J4_cmpgtn1_fp1_jump_nt:
- case Hexagon::J4_cmpgtn1_fp1_jump_t:
- case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_t_jumpnv_t:
- case Hexagon::J4_cmpgtn1_tp0_jump_nt:
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From ff4fc2343a93ab8f0592d115f839ff7e36fc063e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 6 ++
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..d874697185fac 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ARM] Remove most post-decoding instruction adjustments (PR #156540)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From 408cfbc73717240b713f59a393dcc609004dd6ff Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
---
llvm/lib/Target/ARM/ARMInstrCDE.td| 4 +
llvm/lib/Target/ARM/ARMInstrFormats.td| 9 +-
llvm/lib/Target/ARM/ARMInstrMVE.td| 1 +
llvm/lib/Target/ARM/ARMInstrThumb.td | 10 +
llvm/lib/Target/ARM/ARMInstrThumb2.td | 23 +-
llvm/lib/Target/ARM/CMakeLists.txt| 3 +-
.../ARM/Disassembler/ARMDisassembler.cpp | 364 +++---
llvm/test/MC/Disassembler/ARM/arm-tests.txt | 2 +-
8 files changed, 267 insertions(+), 149 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrCDE.td
b/llvm/lib/Target/ARM/ARMInstrCDE.td
index 54e27a6be5583..5d4e3acf5b581 100644
--- a/llvm/lib/Target/ARM/ARMInstrCDE.td
+++ b/llvm/lib/Target/ARM/ARMInstrCDE.td
@@ -115,6 +115,7 @@ class CDE_CX1_Instr
!con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
params.Cstr> {
+ bits<0> p;
bits<13> imm;
bits<4> Rd;
@@ -131,6 +132,7 @@ class CDE_CX2_Instr
!con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
params.Cstr> {
+ bits<0> p;
bits<9> imm;
bits<4> Rd;
bits<4> Rn;
@@ -149,6 +151,7 @@ class CDE_CX3_Instr
!con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm,
$imm"),
params.Cstr> {
+ bits<0> p;
bits<6> imm;
bits<4> Rd;
bits<4> Rn;
@@ -268,6 +271,7 @@ class CDE_Vec_Instr,
CDE_RequiresQReg {
+ bits<0> vp;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td
b/llvm/lib/Target/ARM/ARMInstrFormats.td
index e50740f7d57c5..dc815e1124fa5 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -1219,6 +1219,8 @@ class Thumb1sI pattern>
: InstThumb {
+ bits<0> s;
+ bits<0> p;
let OutOperandList = !con(oops, (outs s_cc_out:$s));
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${s}${p}", asm);
@@ -1243,6 +1245,7 @@ class Thumb1pI pattern>
: InstThumb {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1341,7 +1344,8 @@ class T1Misc opcode> : Encoding16 {
class Thumb2I pattern>
- : InstARM {
+: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1360,6 +1364,7 @@ class Thumb2sI pattern>
: InstARM {
+ bits<0> p;
bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
let Inst{20} = s;
@@ -2220,6 +2225,7 @@ class NeonI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
@@ -2233,6 +2239,7 @@ class NeonXI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", "\t", asm);
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td
b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 9dffd945d5baa..e24413465799f 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -409,6 +409,7 @@ class MVE_p {
+ bits<0> vp;
let Inst{31-29} = 0b111;
let Inst{27-26} = 0b11;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td
b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 0c5ea3e0fa8d5..bc1b34c691e39 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -483,6 +483,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
// A6.2.3 & A8.6.25
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b000;
@@ -491,6 +492,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
Requires<[IsThumb, Has8MSecExt]>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b100;
@@ -523,6 +525,7 @@ let isCall = 1,
"bl${p}\t$func",
[(ARMcall tglobaladdr:$func)]>,
Requires<[IsThumb]>, Sched<[WriteBrL]> {
+bits<0> p;
bits<24> func;
let Inst{26} = func{23};
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From f31a7b8ff6fc270b402ee998b8f7286736762b4b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 25 ++---
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 54 +-
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
5 files changed, 107 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 8958ad129269c..78d683a4b4256 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1561,13 +1561,12 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let OperandNamespace = "AArch64", OperandType = "OPERAND_IMPLICIT_IMM_0",
+DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1620,6 +1619,7 @@ def sme_elm_idx0_0 : Operand, TImmLeaf, TImmLeaf, ImmLeaf, ImmLeaf, ImmLeaf, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8267,15 +8274,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 8c1e9f61693fb..647a6a3d76ef8 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AArch64::ZA));
+ return Success;
+}
+
+static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AArch64::ZT0));
+ return Success;
+}
+
static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
{AArch64::ZAB0},
{AArch64::ZAH0, AArch64::ZAH1},
@@ -141,10 +153,19 @@ static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
AArch64::ZAQ14, AArch64::ZAQ15}};
+template
+static DecodeStatus DecodeMatrixTile(MCInst &Inst,
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From f31a7b8ff6fc270b402ee998b8f7286736762b4b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 25 ++---
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 54 +-
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
5 files changed, 107 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 8958ad129269c..78d683a4b4256 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1561,13 +1561,12 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let OperandNamespace = "AArch64", OperandType = "OPERAND_IMPLICIT_IMM_0",
+DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1620,6 +1619,7 @@ def sme_elm_idx0_0 : Operand, TImmLeaf, TImmLeaf, ImmLeaf, ImmLeaf, ImmLeaf, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8267,15 +8274,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 8c1e9f61693fb..647a6a3d76ef8 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AArch64::ZA));
+ return Success;
+}
+
+static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AArch64::ZT0));
+ return Success;
+}
+
static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
{AArch64::ZAB0},
{AArch64::ZAH0, AArch64::ZAH1},
@@ -141,10 +153,19 @@ static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
AArch64::ZAQ14, AArch64::ZAQ15}};
+template
+static DecodeStatus DecodeMatrixTile(MCInst &Inst,
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From ff4fc2343a93ab8f0592d115f839ff7e36fc063e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 6 ++
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..d874697185fac 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
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[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
https://github.com/usx95 ready_for_review https://github.com/llvm/llvm-project/pull/156896 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
llvmbot wrote:
@llvm/pr-subscribers-clang-temporal-safety
Author: Utkarsh Saxena (usx95)
Changes
This patch refactors the C++ lifetime safety analysis to implement a more
consistent model for tracking borrows. The central idea is to make loan
creation a consequence of referencing a variable, while making loan propagation
dependent on the type's semantics.
This change introduces a more uniform model for tracking borrows from
non-pointer types:
* Centralised Loan Creation: A Loan is now created for every `DeclRefExpr` that
refers to a **non-pointer type** (e.g., `std::string`, `int`). This correctly
models that any use of an **gl-value** is a borrow of its storage, replacing
the previous heuristic-based loan creation.
* The address-of operator (&) no longer creates loans. Instead, it
propagates the origin (and thus the loans) of its sub-expression. This is
guarded to exclude expressions that are already pointer types, deferring the
complexity of pointers-to-pointers.
**Future Work: Multi-Origin Model**
This patch deliberately defers support for creating loans on references to
pointer-type expressions (e.g., `&my_pointer`). The current single-origin
model is unable to distinguish between a loan to the pointer variable itself
(its storage) and a loan to the object it points to. The future plan is to move
to a multi-origin model where a type has a "list of origins" governed by its
level of indirection, which will allow the analysis to track these distinct
lifetimes separately. Once this more advanced model is in place, the
restriction can be lifted, and all `DeclRefExpr` nodes, regardless of type, can
uniformly create a loan, making the analysis even more powerful and consistent.
---
Patch is 36.93 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/156896.diff
2 Files Affected:
- (modified) clang/lib/Analysis/LifetimeSafety.cpp (+110-62)
- (modified) clang/test/Sema/warn-lifetime-safety-dataflow.cpp (+156-104)
``diff
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index dbbf7f3cc14b1..1b5837ff0004d 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -50,6 +50,11 @@ struct Loan {
Loan(LoanID id, AccessPath path, const Expr *IssueExpr)
: ID(id), Path(path), IssueExpr(IssueExpr) {}
+
+ void dump(llvm::raw_ostream &OS) const {
+OS << ID << " (Path: ";
+OS << Path.D->getNameAsString() << ")";
+ }
};
/// An Origin is a symbolic identifier that represents the set of possible
@@ -120,17 +125,19 @@ class OriginManager {
// TODO: Mark this method as const once we remove the call to getOrCreate.
OriginID get(const Expr &E) {
-// Origin of DeclRefExpr is that of the declaration it refers to.
+auto It = ExprToOriginID.find(&E);
+if (It != ExprToOriginID.end())
+ return It->second;
+// If the expression itself has no specific origin, and it's a reference
+// to a declaration, its origin is that of the declaration it refers to.
+// For pointer types, where we don't pre-emptively create an origin for the
+// DeclRefExpr itself.
if (const auto *DRE = dyn_cast(&E))
return get(*DRE->getDecl());
-auto It = ExprToOriginID.find(&E);
// TODO: This should be an assert(It != ExprToOriginID.end()). The current
// implementation falls back to getOrCreate to avoid crashing on
// yet-unhandled pointer expressions, creating an empty origin for them.
-if (It == ExprToOriginID.end())
- return getOrCreate(E);
-
-return It->second;
+return getOrCreate(E);
}
OriginID get(const ValueDecl &D) {
@@ -149,10 +156,6 @@ class OriginManager {
if (It != ExprToOriginID.end())
return It->second;
-if (const auto *DRE = dyn_cast(&E)) {
- // Origin of DeclRefExpr is that of the declaration it refers to.
- return getOrCreate(*DRE->getDecl());
-}
OriginID NewID = getNextOriginID();
addOrigin(NewID, E);
ExprToOriginID[&E] = NewID;
@@ -235,7 +238,8 @@ class Fact {
return nullptr;
}
- virtual void dump(llvm::raw_ostream &OS, const OriginManager &) const {
+ virtual void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &) const {
OS << "Fact (Kind: " << static_cast(K) << ")\n";
}
};
@@ -250,8 +254,11 @@ class IssueFact : public Fact {
IssueFact(LoanID LID, OriginID OID) : Fact(Kind::Issue), LID(LID), OID(OID)
{}
LoanID getLoanID() const { return LID; }
OriginID getOriginID() const { return OID; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
-OS << "Issue (LoanID: " << getLoanID() << ", ToOrigin: ";
+ void dump(llvm::raw_ostream &OS, const LoanManager &LM,
+const OriginManager &OM) const override {
+OS << "Issue (";
+LM.getLoan(getLoanID()).dump(OS);
+OS << ", ToOrigin: ";
OM.dump(get
[llvm-branch-commits] [llvm] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (PR #156363)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From d2968852e5e5a25c2b620b4fc54d9f246e4ce8fc Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
These are the only instructions that encode two operands in the same
field. Instead of fixing them after they have been incorrectly decoded,
provide a custom decoder.
---
.../Disassembler/AArch64Disassembler.cpp | 29 ---
llvm/lib/Target/AArch64/SMEInstrFormats.td| 4 +++
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 23e46b84f6278..8c1e9f61693fb 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1563,6 +1563,25 @@ static DecodeStatus DecodePRFMRegInstruction(MCInst
&Inst, uint32_t insn,
return Success;
}
+static DecodeStatus
+DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
+ const MCDisassembler *Decoder) {
+ unsigned RvBits = fieldFromInstruction(Bits, 13, 2);
+ unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
+ unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
+
+ DecodeSimpleRegisterClass(
+ Inst, RvBits, Addr, Decoder);
+ Inst.addOperand(MCOperand::createImm(Imm4Bits));
+ DecodeSimpleRegisterClass(Inst, RnBits,
+ Addr, Decoder);
+ // Spill and fill instructions have a single immediate used for both
+ // the vector select offset and optional memory offset. Replicate
+ // the decoded immediate.
+ Inst.addOperand(MCOperand::createImm(Imm4Bits));
+ return Success;
+}
+
#include "AArch64GenDisassemblerTables.inc"
#include "AArch64GenInstrInfo.inc"
@@ -1621,16 +1640,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst
&MI, uint64_t &Size,
}
}
-if (MI.getOpcode() == AArch64::LDR_ZA ||
-MI.getOpcode() == AArch64::STR_ZA) {
- // Spill and fill instructions have a single immediate used for both
- // the vector select offset and optional memory offset. Replicate
- // the decoded immediate.
- const MCOperand &Imm4Op = MI.getOperand(2);
- assert(Imm4Op.isImm() && "Unexpected operand type!");
- MI.addOperand(Imm4Op);
-}
-
if (Result != MCDisassembler::Fail)
return Result;
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td
b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index b3005d5120229..40ec371fe79d3 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1108,6 +1108,10 @@ class sme_spill_fill_base
: I,
Sched<[]> {
+ // 'offset' operand is encoded in the same bits as 'imm4'. There is currently
+ // no way to tell TableGen about this.
+ let DecoderMethod = "DecodeSMESpillFillInstruction";
+ bits<0> ZAt;
bits<2> Rv;
bits<5> Rn;
bits<4> imm4;
___
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[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From e48805779b288d87477d2e7f9c8fcedcf3850511 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 6 ++
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..d874697185fac 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
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[llvm-branch-commits] [llvm] [AArch64] Correctly disassemble TSB instruction (PR #156362)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From a233e69f26b660bb800f519b773b96f5f2d7b07e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.
This instruction can now be disassembled correctly.
---
llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 3 +--
.../lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 7 ---
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1b0e90b0e0dc3..65b752ed40c90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex {
let Key = ["Name"];
}
-def : TSB<"csync", 0>;
+def : TSB<"csync", 2>;
//===--===//
// PRFM (prefetch) instruction options.
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 833ce48ea1d7a..79b56ea9cf850 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer
-asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands
- -ignore-fully-defined-operands)
+ -ignore-non-decodable-operands)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 54b58e948daf2..2552ee3009338 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI,
uint64_t Address,
return;
}
- // Instruction TSB is specified as a one operand instruction, but 'csync' is
- // not encoded, so for printing it is treated as a special case here:
- if (Opcode == AArch64::TSB) {
-O << "\ttsb\tcsync";
-return;
- }
-
if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
printInstruction(MI, Address, STI, O);
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[llvm-branch-commits] [clang] Remove shell requirements from tests (PR #156905)
llvmbot wrote: @llvm/pr-subscribers-clang Author: Aiden Grossman (boomanaiden154) Changes Most of these tests do not actually have a shell requirement. The shell requirement ended up in the test either from cargo culting (from what I can tell) or because the test authors actually meant to mark Windows as unsupported. This prevents enablement of lit's internal shell within clang. Towards #102699. --- Patch is 28.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/156905.diff 61 Files Affected: - (modified) clang/test/Analysis/scan-build/cxx-name.test (-2) - (modified) clang/test/Analysis/scan-build/deduplication.test (-2) - (modified) clang/test/Analysis/scan-build/html_output.test (-2) - (modified) clang/test/Analysis/scan-build/plist_html_output.test (-2) - (modified) clang/test/Analysis/scan-build/plist_output.test (-2) - (modified) clang/test/ClangScanDeps/module-format.c (-2) - (modified) clang/test/ClangScanDeps/modules-context-hash-cwd.c (-2) - (modified) clang/test/ClangScanDeps/modules-file-path-isolation.c (+2-1) - (modified) clang/test/ClangScanDeps/modules-in-stable-dirs.c (-1) - (modified) clang/test/ClangScanDeps/modules-symlink-dir-from-module.c (+2-1) - (modified) clang/test/ClangScanDeps/modules-symlink-dir-vfs.c (+2-1) - (modified) clang/test/ClangScanDeps/modules-symlink-dir.c (-2) - (modified) clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c (+1-2) - (modified) clang/test/ClangScanDeps/subframework_header_dir_symlink.m (+2-1) - (modified) clang/test/ClangScanDeps/symlink.cpp (+3-1) - (modified) clang/test/CodeCompletion/included-symlinks.cpp (+2-1) - (modified) clang/test/Driver/aarch64-toolchain-extra.c (+1-2) - (modified) clang/test/Driver/amdgpu-hip-system-arch.c (+2-1) - (modified) clang/test/Driver/amdgpu-openmp-system-arch-fail.c (+2-1) - (modified) clang/test/Driver/arm-toolchain-extra.c (-1) - (modified) clang/test/Driver/baremetal-multilib-layered.yaml (-1) - (modified) clang/test/Driver/baremetal-multilib.yaml (-1) - (modified) clang/test/Driver/baremetal-sysroot.cpp (-1) - (modified) clang/test/Driver/darwin-ld-demangle-lld.c (-1) - (modified) clang/test/Driver/darwin-ld-lto-lld.c (-2) - (modified) clang/test/Driver/mingw-sysroot.cpp (-1) - (modified) clang/test/Driver/no-canonical-prefixes.c (+1-1) - (modified) clang/test/Driver/nvptx-cuda-system-arch.c (-1) - (modified) clang/test/Driver/openmp-system-arch.c (+2-1) - (modified) clang/test/Driver/parse-progname.c (+2-1) - (modified) clang/test/Driver/riscv32-toolchain-extra.c (+1-2) - (modified) clang/test/Driver/riscv64-toolchain-extra.c (-1) - (modified) clang/test/Driver/sigpipe-handling.c (+1-1) - (modified) clang/test/Driver/target-override.c (+2-1) - (modified) clang/test/Driver/verbose-output-quoting.c (-1) - (modified) clang/test/Frontend/dependency-gen-symlink.c (-2) - (modified) clang/test/Index/preamble-reparse-changed-module.m (-2) - (modified) clang/test/InterfaceStubs/driver-test.c (-1) - (modified) clang/test/InterfaceStubs/driver-test2.c (-1) - (modified) clang/test/InterfaceStubs/driver-test3.c (-1) - (modified) clang/test/Modules/crash-vfs-headermaps.m (+1-1) - (modified) clang/test/Modules/crash-vfs-include-pch.m (+1-1) - (modified) clang/test/Modules/crash-vfs-path-emptydir-entries.m (+1-1) - (modified) clang/test/Modules/crash-vfs-path-symlink-topheader.m (+1-1) - (modified) clang/test/Modules/embed-files-compressed.cpp (-1) - (modified) clang/test/Modules/embed-files.cpp (+1-1) - (modified) clang/test/Modules/exponential-paths.cpp (-2) - (modified) clang/test/Modules/framework-name.m (-1) - (modified) clang/test/Modules/implicit-private-without-public.m (-1) - (modified) clang/test/Modules/inferred-framework-case.m (+1-1) - (modified) clang/test/Modules/module-file-modified.c (-1) - (modified) clang/test/Modules/module-symlink.m (-2) - (modified) clang/test/Modules/modulemap-collision.m (-2) - (modified) clang/test/Modules/validate-file-content.m (-2) - (modified) clang/test/PCH/validate-file-content.m (-2) - (modified) clang/test/Preprocessor/embed_zos.c (+1-1) - (modified) clang/test/Preprocessor/nonportable-include-with-hmap.c (-1) - (modified) clang/test/Profile/cxx-hash-v2.cpp (-2) - (modified) clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/warn-unsafe-buffer-usage-debug-unclaimed.cpp (-1) - (modified) clang/test/Tooling/auto-detect-from-source-parent-of-cwd.cpp (+3-2) - (modified) clang/test/Tooling/clang-check-pwd.cpp (+3) ``diff diff --git a/clang/test/Analysis/scan-build/cxx-name.test b/clang/test/Analysis/scan-build/cxx-name.test index 483762d619d17..b602cb5c5231c 100644 --- a/clang/test/Analysis/scan-build/cxx-name.test +++ b/clang/test/Analysis/scan-build/cxx-name.test @@ -1,5 +1,3 @@ -REQUIRES: shell - RUN: %scan-build sh -c 'echo "CLANG_CXX=/$(basename "$CLANG_CXX")/"' | FileCheck %s Check that scan-build sets the CLANG_CXX environ
[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d19b8cd451544e87424c1954156a1aaeafa9a7b7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 ++-
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 --
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4 +++
5 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 720361dc3da5b..531238ae85029 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc
-gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- --specialize-decoders-per-bitwidth
- -ignore-non-decodable-operands)
+ --specialize-decoders-per-bitwidth)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b1b7ea5246fda..89df9d82f8780 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,12 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +604,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -774,12 +769,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bit
[llvm-branch-commits] [clang] all-lvalues-have-origin (PR #156896)
https://github.com/usx95 created
https://github.com/llvm/llvm-project/pull/156896
None
>From 2f0c4c10dc8295f4eb3f323c5129f1ef0b3ac2a1 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Thu, 4 Sep 2025 14:27:37 +
Subject: [PATCH] all-lvalues-have-origin
---
clang/lib/Analysis/LifetimeSafety.cpp | 172 +++-
.../Sema/warn-lifetime-safety-dataflow.cpp| 260 +++---
2 files changed, 266 insertions(+), 166 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index dbbf7f3cc14b1..1b5837ff0004d 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -50,6 +50,11 @@ struct Loan {
Loan(LoanID id, AccessPath path, const Expr *IssueExpr)
: ID(id), Path(path), IssueExpr(IssueExpr) {}
+
+ void dump(llvm::raw_ostream &OS) const {
+OS << ID << " (Path: ";
+OS << Path.D->getNameAsString() << ")";
+ }
};
/// An Origin is a symbolic identifier that represents the set of possible
@@ -120,17 +125,19 @@ class OriginManager {
// TODO: Mark this method as const once we remove the call to getOrCreate.
OriginID get(const Expr &E) {
-// Origin of DeclRefExpr is that of the declaration it refers to.
+auto It = ExprToOriginID.find(&E);
+if (It != ExprToOriginID.end())
+ return It->second;
+// If the expression itself has no specific origin, and it's a reference
+// to a declaration, its origin is that of the declaration it refers to.
+// For pointer types, where we don't pre-emptively create an origin for the
+// DeclRefExpr itself.
if (const auto *DRE = dyn_cast(&E))
return get(*DRE->getDecl());
-auto It = ExprToOriginID.find(&E);
// TODO: This should be an assert(It != ExprToOriginID.end()). The current
// implementation falls back to getOrCreate to avoid crashing on
// yet-unhandled pointer expressions, creating an empty origin for them.
-if (It == ExprToOriginID.end())
- return getOrCreate(E);
-
-return It->second;
+return getOrCreate(E);
}
OriginID get(const ValueDecl &D) {
@@ -149,10 +156,6 @@ class OriginManager {
if (It != ExprToOriginID.end())
return It->second;
-if (const auto *DRE = dyn_cast(&E)) {
- // Origin of DeclRefExpr is that of the declaration it refers to.
- return getOrCreate(*DRE->getDecl());
-}
OriginID NewID = getNextOriginID();
addOrigin(NewID, E);
ExprToOriginID[&E] = NewID;
@@ -235,7 +238,8 @@ class Fact {
return nullptr;
}
- virtual void dump(llvm::raw_ostream &OS, const OriginManager &) const {
+ virtual void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &) const {
OS << "Fact (Kind: " << static_cast(K) << ")\n";
}
};
@@ -250,8 +254,11 @@ class IssueFact : public Fact {
IssueFact(LoanID LID, OriginID OID) : Fact(Kind::Issue), LID(LID), OID(OID)
{}
LoanID getLoanID() const { return LID; }
OriginID getOriginID() const { return OID; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
-OS << "Issue (LoanID: " << getLoanID() << ", ToOrigin: ";
+ void dump(llvm::raw_ostream &OS, const LoanManager &LM,
+const OriginManager &OM) const override {
+OS << "Issue (";
+LM.getLoan(getLoanID()).dump(OS);
+OS << ", ToOrigin: ";
OM.dump(getOriginID(), OS);
OS << ")\n";
}
@@ -270,8 +277,11 @@ class ExpireFact : public Fact {
LoanID getLoanID() const { return LID; }
SourceLocation getExpiryLoc() const { return ExpiryLoc; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
-OS << "Expire (LoanID: " << getLoanID() << ")\n";
+ void dump(llvm::raw_ostream &OS, const LoanManager &LM,
+const OriginManager &) const override {
+OS << "Expire (";
+LM.getLoan(getLoanID()).dump(OS);
+OS << ")\n";
}
};
@@ -288,7 +298,8 @@ class AssignOriginFact : public Fact {
: Fact(Kind::AssignOrigin), OIDDest(OIDDest), OIDSrc(OIDSrc) {}
OriginID getDestOriginID() const { return OIDDest; }
OriginID getSrcOriginID() const { return OIDSrc; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
+ void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &OM) const override {
OS << "AssignOrigin (Dest: ";
OM.dump(getDestOriginID(), OS);
OS << ", Src: ";
@@ -307,7 +318,8 @@ class ReturnOfOriginFact : public Fact {
ReturnOfOriginFact(OriginID OID) : Fact(Kind::ReturnOfOrigin), OID(OID) {}
OriginID getReturnedOriginID() const { return OID; }
- void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
+ void dump(llvm::raw_ostream &OS, const LoanManager &,
+const OriginManager &OM) const override {
OS << "ReturnOfOrigin (";
OM.dump(getReturnedOriginID(), OS);
OS << ")\n";
@@ -333,10 +345,11 @@ class UseFact : p
[llvm-branch-commits] [llvm] AMDGPU: Add agpr versions of global return atomics (PR #156890)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156890
Incremental step towards removing the special case hack
in TargetInstrInfo::getRegClass.
>From c0b9ff92d356aca252e8dc2e82f5e31be676316b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 13:08:07 +0900
Subject: [PATCH] AMDGPU: Add agpr versions of global return atomics
Incremental step towards removing the special case hack
in TargetInstrInfo::getRegClass.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 24 +++--
llvm/lib/Target/AMDGPU/FLATInstructions.td | 41 --
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 24 +
3 files changed, 67 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index bec920380e081..f2e432fa8d7f5 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -51,22 +51,6 @@ class DS_Pseudo patt
let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
}
-class DstOperandIsAV {
- bit ret = OperandIsAV(OperandList, "vdst")>.ret;
-}
-
-class DstOperandIsAGPR {
- bit ret = OperandIsAGPR(OperandList, "vdst")>.ret;
-}
-
-class DataOperandIsAV {
- bit ret = OperandIsAV(OperandList, "data0")>.ret;
-}
-
-class DataOperandIsAGPR {
- bit ret = OperandIsAGPR(OperandList, "data0")>.ret;
-}
-
class DS_Real :
InstSI ,
Enc64 {
@@ -115,13 +99,13 @@ class DS_Real :
// register fields are only 8-bit, so data operands must all be AGPR
// or VGPR.
defvar DstOpIsAV = !if(ps.has_vdst,
- DstOperandIsAV.ret, 0);
+ VDstOperandIsAV.ret, 0);
defvar DstOpIsAGPR = !if(ps.has_vdst,
- DstOperandIsAGPR.ret, 0);
+ VDstOperandIsAGPR.ret, 0);
defvar DataOpIsAV = !if(!or(ps.has_data0, ps.has_gws_data0),
- DataOperandIsAV.ret, 0);
+ Data0OperandIsAV.ret, 0);
defvar DataOpIsAGPR = !if(!or(ps.has_data0, ps.has_gws_data0),
-DataOperandIsAGPR.ret, 0);
+Data0OperandIsAGPR.ret, 0);
bits<1> acc = !if(ps.has_vdst,
!if(DstOpIsAV, vdst{9}, DstOpIsAGPR),
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td
b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 0ac5f3d50f1b5..fd7c9a741c301 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -137,7 +137,18 @@ class FLAT_Real op, FLAT_Pseudo ps, string opName
= ps.Mnemonic> :
// unsigned for flat accesses.
bits<13> offset;
// GFX90A+ only: instruction uses AccVGPR for data
- bits<1> acc = !if(ps.has_vdst, vdst{9}, !if(ps.has_data, vdata{9}, 0));
+ defvar DstOpIsAV = !if(ps.has_vdst,
+ VDstOperandIsAV.ret, 0);
+ defvar DstOpIsAGPR = !if(ps.has_vdst,
+ VDstOperandIsAGPR.ret, 0);
+ defvar DataOpIsAV = !if(ps.has_data,
+ VDataOperandIsAV.ret, 0);
+ defvar DataOpIsAGPR = !if(ps.has_data,
+VDataOperandIsAGPR.ret, 0);
+
+ bits<1> acc = !if(ps.has_vdst,
+!if(DstOpIsAV, vdst{9}, DstOpIsAGPR),
+!if(DataOpIsAV, vdata{9}, DataOpIsAGPR));
// We don't use tfe right now, and it was removed in gfx9.
bits<1> tfe = 0;
@@ -860,6 +871,30 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
let enabled_saddr = 1;
let FPAtomic = data_vt.isFP;
}
+
+defvar vdst_op_agpr = getEquivalentAGPROperand.ret;
+defvar data_op_agpr = getEquivalentAGPROperand.ret;
+
+let SubtargetPredicate = isGFX90APlus in {
+ def _RTN_agpr : FLAT_AtomicRet_Pseudo ,
+GlobalSaddrTable<0, opName#"_rtn_agpr"> {
+let has_saddr = 1;
+let FPAtomic = data_vt.isFP;
+ }
+
+ def _SADDR_RTN_agpr : FLAT_AtomicRet_Pseudo ,
+GlobalSaddrTable<1, opName#"_rtn_agpr"> {
+ let has_saddr = 1;
+ let enabled_saddr = 1;
+ let FPAtomic = data_vt.isFP;
+ }
+}
}
}
@@ -2637,8 +2672,10 @@ multiclass FLAT_Global_Real_Atomics_vi op,
FLAT_Real_AllAddr_vi {
def _RTN_vi : FLAT_Real_vi (NAME#"_RTN"), has_sccb>;
def _SADDR_RTN_vi : FLAT_Real_vi (NAME#"_SADDR_RTN"),
has_sccb>;
-}
+ def _RTN_agpr_vi : FLAT_Real_vi (NAME#"_RTN_agpr"),
has_sccb>;
+ def _SADDR_RTN_agpr_vi : FLAT_Real_vi (NAME#"_SADDR_RTN_agpr"), has_sccb>;
+}
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40>;
defm FLAT_ATOMIC_CMPSWAP: FLAT_Real_Atomics_vi <0x41>;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 8c2bd3d3962ce..d9746a17e75eb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1492,3 +1492,27 @@ class OperandIsVGPR {
defvar reg_class = getRegClassFromOp.ret;
bit ret = !and(reg_class.HasVGPR, !not(reg_cla
[llvm-branch-commits] [clang] all-lvalues-have-origin (PR #156896)
usx95 wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156896?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#156896** https://app.graphite.dev/github/pr/llvm/llvm-project/156896?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/156896?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#154316** https://app.graphite.dev/github/pr/llvm/llvm-project/154316?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 1 other dependent PR ([#154009](https://github.com/llvm/llvm-project/pull/154009) https://app.graphite.dev/github/pr/llvm/llvm-project/154009?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * **#153661** https://app.graphite.dev/github/pr/llvm/llvm-project/153661?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 2 other dependent PRs ([#153669](https://github.com/llvm/llvm-project/pull/153669) https://app.graphite.dev/github/pr/llvm/llvm-project/153669?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>, [#153951](https://github.com/llvm/llvm-project/pull/153951) https://app.graphite.dev/github/pr/llvm/llvm-project/153951?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * **#149731** https://app.graphite.dev/github/pr/llvm/llvm-project/149731?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#148712** https://app.graphite.dev/github/pr/llvm/llvm-project/148712?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 1 other dependent PR ([#148976](https://github.com/llvm/llvm-project/pull/148976) https://app.graphite.dev/github/pr/llvm/llvm-project/148976?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * **#149158** https://app.graphite.dev/github/pr/llvm/llvm-project/149158?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#149199** https://app.graphite.dev/github/pr/llvm/llvm-project/149199?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/156896 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
@@ -438,12 +452,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclStmt(const DeclStmt *DS) {
for (const Decl *D : DS->decls())
if (const auto *VD = dyn_cast(D))
-if (hasOrigin(VD->getType()))
+if (hasOrigin(VD))
if (const Expr *InitExpr = VD->getInit())
addAssignOriginFact(*VD, *InitExpr);
}
- void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) {
+handleUse(DRE);
+// For non-pointer/non-view types, a reference to the variable's storage
+// is a borrow. We create a loan for it.
+// For pointer/view types, we stick to the existing model for now and do
+// not create an extra origin for the l-value expression itself.
+
+// FIXME: A loan to `DeclRefExpr` for a pointer or view type can be
Xazax-hun wrote:
We could potentially optimize by ignoring DREs under such conversions but I am
fine not doing that for now.
https://github.com/llvm/llvm-project/pull/156896
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[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
@@ -438,12 +452,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclStmt(const DeclStmt *DS) {
for (const Decl *D : DS->decls())
if (const auto *VD = dyn_cast(D))
-if (hasOrigin(VD->getType()))
+if (hasOrigin(VD))
if (const Expr *InitExpr = VD->getInit())
addAssignOriginFact(*VD, *InitExpr);
}
- void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) {
+handleUse(DRE);
+// For non-pointer/non-view types, a reference to the variable's storage
+// is a borrow. We create a loan for it.
+// For pointer/view types, we stick to the existing model for now and do
+// not create an extra origin for the l-value expression itself.
+
+// FIXME: A loan to `DeclRefExpr` for a pointer or view type can be
usx95 wrote:
Yes.
This is to not create loans to pointer types/view types which will need
multi-origin modelling.
```
std::string_view s;
std::string_view t = s; // RHS is essentially a reference to view needing two
origins (Only the inner origin makes it to the LHS t)
```
https://github.com/llvm/llvm-project/pull/156896
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[llvm-branch-commits] [clang] [LifetimeSafety] Associate origins to all l-valued expressions (PR #156896)
@@ -438,12 +452,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclStmt(const DeclStmt *DS) {
for (const Decl *D : DS->decls())
if (const auto *VD = dyn_cast(D))
-if (hasOrigin(VD->getType()))
+if (hasOrigin(VD))
if (const Expr *InitExpr = VD->getInit())
addAssignOriginFact(*VD, *InitExpr);
}
- void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) {
+handleUse(DRE);
+// For non-pointer/non-view types, a reference to the variable's storage
+// is a borrow. We create a loan for it.
+// For pointer/view types, we stick to the existing model for now and do
+// not create an extra origin for the l-value expression itself.
+
+// FIXME: A loan to `DeclRefExpr` for a pointer or view type can be
Xazax-hun wrote:
Except for opaque function calls. We need to rely on annotations for those.
https://github.com/llvm/llvm-project/pull/156896
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[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov ready_for_review https://github.com/llvm/llvm-project/pull/156364 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
s-barannikov wrote:
Those have a custom DecoderMethod, and this field currently only affects the
*generated decoders*. If they didn't have a custom DecoderMethod, TableGen
would complain about missing operand encoding for "$z" operand.
I think I can remove some custom decoder methods in a follow-up PR.
https://github.com/llvm/llvm-project/pull/156361
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[llvm-branch-commits] [clang] Remove shell requirements from tests (PR #156905)
https://github.com/boomanaiden154 created https://github.com/llvm/llvm-project/pull/156905 Most of these tests do not actually have a shell requirement. The shell requirement ended up in the test either from cargo culting (from what I can tell) or because the test authors actually meant to mark Windows as unsupported. This prevents enablement of lit's internal shell within clang. Towards #102699. ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Remove shell requirements from tests (PR #156905)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/156905
>From f6a61c9ba23ff3139dedbc0b81e7133bc2e07345 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Thu, 4 Sep 2025 16:12:07 +
Subject: [PATCH] fix
Created using spr 1.3.6
---
clang/test/ClangScanDeps/modules-context-hash-cwd.c| 2 ++
clang/test/ClangScanDeps/modules-in-stable-dirs.c | 3 +++
clang/test/ClangScanDeps/modules-symlink-dir.c | 3 +++
clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c | 3 +++
clang/test/Driver/config-file3.c | 2 ++
clang/test/Driver/config-zos.c | 2 ++
clang/test/Driver/config-zos1.c| 1 +
clang/test/Driver/nvptx-cuda-system-arch.c | 1 +
clang/test/Frontend/dependency-gen-symlink.c | 3 +++
clang/test/Index/preamble-reparse-changed-module.m | 2 ++
clang/test/Modules/crash-vfs-path-emptydir-entries.m | 1 +
clang/test/Modules/crash-vfs-path-symlink-component.m | 2 ++
clang/test/Modules/crash-vfs-path-symlink-topheader.m | 2 ++
clang/test/Modules/crash-vfs-relative-overlay.m| 1 +
clang/test/Modules/framework-name.m| 3 +++
clang/test/Modules/module-symlink.m| 3 +++
clang/test/Modules/modulemap-collision.m | 3 +++
clang/test/Preprocessor/nonportable-include-with-hmap.c| 2 ++
18 files changed, 39 insertions(+)
diff --git a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
index e631b7b897eec..b5086ed409223 100644
--- a/clang/test/ClangScanDeps/modules-context-hash-cwd.c
+++ b/clang/test/ClangScanDeps/modules-context-hash-cwd.c
@@ -1,3 +1,5 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
// Test current directory pruning when computing the context hash.
// RUN: rm -rf %t
diff --git a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
index 0a7b732e5d8ac..f54e09fecee94 100644
--- a/clang/test/ClangScanDeps/modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
// This test verifies modules that are entirely comprised from stable
directory inputs are captured in
// dependency information.
diff --git a/clang/test/ClangScanDeps/modules-symlink-dir.c
b/clang/test/ClangScanDeps/modules-symlink-dir.c
index da3cf23ce6257..cf4a0998a80f9 100644
--- a/clang/test/ClangScanDeps/modules-symlink-dir.c
+++ b/clang/test/ClangScanDeps/modules-symlink-dir.c
@@ -1,3 +1,6 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
+
// Check that we canonicalize the module map path without changing the module
// directory, which would break header lookup.
diff --git a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
index 74be4a97001fe..39b2863d966c3 100644
--- a/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
+++ b/clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
@@ -1,3 +1,6 @@
+/// Most likely platform specific sed differences
+// UNSUPPORTED: system-windows
+
/// This test validates that modules that depend on prebuilt modules
/// resolve `is-in-stable-directories` correctly.
/// The steps are:
diff --git a/clang/test/Driver/config-file3.c b/clang/test/Driver/config-file3.c
index 9ba807da84414..7de77af330f6d 100644
--- a/clang/test/Driver/config-file3.c
+++ b/clang/test/Driver/config-file3.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: x86-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos.c b/clang/test/Driver/config-zos.c
index dbed97adaf5d5..055c4c981977b 100644
--- a/clang/test/Driver/config-zos.c
+++ b/clang/test/Driver/config-zos.c
@@ -1,3 +1,5 @@
+// Needs symlinks
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: rm -rf %t && mkdir %t
diff --git a/clang/test/Driver/config-zos1.c b/clang/test/Driver/config-zos1.c
index 6a4c17a660999..cf4f13b3879df 100644
--- a/clang/test/Driver/config-zos1.c
+++ b/clang/test/Driver/config-zos1.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// REQUIRES: systemz-registered-target
// RUN: export CLANG_CONFIG_PATH=%S/Inputs/config-zos
diff --git a/clang/test/Driver/nvptx-cuda-system-arch.c
b/clang/test/Driver/nvptx-cuda-system-arch.c
index d5ce60fa6c0eb..675d15bf22cc0 100644
--- a/clang/test/Driver/nvptx-cuda-system-arch.c
+++ b/clang/test/Driver/nvptx-cuda-system-arch.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
// XFAIL: target={{.*}}-zos{{.*}}
// RUN: mkdir -p %t
diff --git a/clang/test/Frontend/dependency-gen-symlink.c
b/clang/test/Frontend/dependency-gen-symlink.c
index 34b1a74a628a5..39a976a1617d
[llvm-branch-commits] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)
https://github.com/melver edited https://github.com/llvm/llvm-project/pull/156840 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)
https://github.com/melver edited https://github.com/llvm/llvm-project/pull/156839 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Remove shell requirements from tests (PR #156905)
llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Aiden Grossman (boomanaiden154) Changes Most of these tests do not actually have a shell requirement. The shell requirement ended up in the test either from cargo culting (from what I can tell) or because the test authors actually meant to mark Windows as unsupported. This prevents enablement of lit's internal shell within clang. Towards #102699. --- Patch is 28.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/156905.diff 61 Files Affected: - (modified) clang/test/Analysis/scan-build/cxx-name.test (-2) - (modified) clang/test/Analysis/scan-build/deduplication.test (-2) - (modified) clang/test/Analysis/scan-build/html_output.test (-2) - (modified) clang/test/Analysis/scan-build/plist_html_output.test (-2) - (modified) clang/test/Analysis/scan-build/plist_output.test (-2) - (modified) clang/test/ClangScanDeps/module-format.c (-2) - (modified) clang/test/ClangScanDeps/modules-context-hash-cwd.c (-2) - (modified) clang/test/ClangScanDeps/modules-file-path-isolation.c (+2-1) - (modified) clang/test/ClangScanDeps/modules-in-stable-dirs.c (-1) - (modified) clang/test/ClangScanDeps/modules-symlink-dir-from-module.c (+2-1) - (modified) clang/test/ClangScanDeps/modules-symlink-dir-vfs.c (+2-1) - (modified) clang/test/ClangScanDeps/modules-symlink-dir.c (-2) - (modified) clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c (+1-2) - (modified) clang/test/ClangScanDeps/subframework_header_dir_symlink.m (+2-1) - (modified) clang/test/ClangScanDeps/symlink.cpp (+3-1) - (modified) clang/test/CodeCompletion/included-symlinks.cpp (+2-1) - (modified) clang/test/Driver/aarch64-toolchain-extra.c (+1-2) - (modified) clang/test/Driver/amdgpu-hip-system-arch.c (+2-1) - (modified) clang/test/Driver/amdgpu-openmp-system-arch-fail.c (+2-1) - (modified) clang/test/Driver/arm-toolchain-extra.c (-1) - (modified) clang/test/Driver/baremetal-multilib-layered.yaml (-1) - (modified) clang/test/Driver/baremetal-multilib.yaml (-1) - (modified) clang/test/Driver/baremetal-sysroot.cpp (-1) - (modified) clang/test/Driver/darwin-ld-demangle-lld.c (-1) - (modified) clang/test/Driver/darwin-ld-lto-lld.c (-2) - (modified) clang/test/Driver/mingw-sysroot.cpp (-1) - (modified) clang/test/Driver/no-canonical-prefixes.c (+1-1) - (modified) clang/test/Driver/nvptx-cuda-system-arch.c (-1) - (modified) clang/test/Driver/openmp-system-arch.c (+2-1) - (modified) clang/test/Driver/parse-progname.c (+2-1) - (modified) clang/test/Driver/riscv32-toolchain-extra.c (+1-2) - (modified) clang/test/Driver/riscv64-toolchain-extra.c (-1) - (modified) clang/test/Driver/sigpipe-handling.c (+1-1) - (modified) clang/test/Driver/target-override.c (+2-1) - (modified) clang/test/Driver/verbose-output-quoting.c (-1) - (modified) clang/test/Frontend/dependency-gen-symlink.c (-2) - (modified) clang/test/Index/preamble-reparse-changed-module.m (-2) - (modified) clang/test/InterfaceStubs/driver-test.c (-1) - (modified) clang/test/InterfaceStubs/driver-test2.c (-1) - (modified) clang/test/InterfaceStubs/driver-test3.c (-1) - (modified) clang/test/Modules/crash-vfs-headermaps.m (+1-1) - (modified) clang/test/Modules/crash-vfs-include-pch.m (+1-1) - (modified) clang/test/Modules/crash-vfs-path-emptydir-entries.m (+1-1) - (modified) clang/test/Modules/crash-vfs-path-symlink-topheader.m (+1-1) - (modified) clang/test/Modules/embed-files-compressed.cpp (-1) - (modified) clang/test/Modules/embed-files.cpp (+1-1) - (modified) clang/test/Modules/exponential-paths.cpp (-2) - (modified) clang/test/Modules/framework-name.m (-1) - (modified) clang/test/Modules/implicit-private-without-public.m (-1) - (modified) clang/test/Modules/inferred-framework-case.m (+1-1) - (modified) clang/test/Modules/module-file-modified.c (-1) - (modified) clang/test/Modules/module-symlink.m (-2) - (modified) clang/test/Modules/modulemap-collision.m (-2) - (modified) clang/test/Modules/validate-file-content.m (-2) - (modified) clang/test/PCH/validate-file-content.m (-2) - (modified) clang/test/Preprocessor/embed_zos.c (+1-1) - (modified) clang/test/Preprocessor/nonportable-include-with-hmap.c (-1) - (modified) clang/test/Profile/cxx-hash-v2.cpp (-2) - (modified) clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/warn-unsafe-buffer-usage-debug-unclaimed.cpp (-1) - (modified) clang/test/Tooling/auto-detect-from-source-parent-of-cwd.cpp (+3-2) - (modified) clang/test/Tooling/clang-check-pwd.cpp (+3) ``diff diff --git a/clang/test/Analysis/scan-build/cxx-name.test b/clang/test/Analysis/scan-build/cxx-name.test index 483762d619d17..b602cb5c5231c 100644 --- a/clang/test/Analysis/scan-build/cxx-name.test +++ b/clang/test/Analysis/scan-build/cxx-name.test @@ -1,5 +1,3 @@ -REQUIRES: shell - RUN: %scan-build sh -c 'echo "CLANG_CXX=/$(basename "$CLANG_CXX")/"' | FileCheck %s Check that scan-build sets the CLANG_CX
