[llvm-branch-commits] [flang] [flang][OpenMP] `do concurrent`: support `reduce` on device (PR #156610)
https://github.com/ergawy created
https://github.com/llvm/llvm-project/pull/156610
Extends `do concurrent` to OpenMP device mapping by adding support for mapping
`reduce` specifiers to omp `reduction` clauses. The changes attach 2
`reduction` clauses to the mapped OpenMP construct: one on the `teams` part of
the construct and one on the `wloop` part.
>From f748bd2e10415fc11f55bde946cab3a72e33ab2f Mon Sep 17 00:00:00 2001
From: ergawy
Date: Tue, 2 Sep 2025 08:36:34 -0500
Subject: [PATCH] [flang][OpenMP] `do concurrent`: support `reduce` on device
Extends `do concurrent` to OpenMP device mapping by adding support for
mapping `reduce` specifiers to omp `reduction` clauses. The changes
attach 2 `reduction` clauses to the mapped OpenMP construct: one on the
`teams` part of the construct and one on the `wloop` part.
---
.../OpenMP/DoConcurrentConversion.cpp | 117 ++
.../DoConcurrent/reduce_device.mlir | 53
2 files changed, 121 insertions(+), 49 deletions(-)
create mode 100644 flang/test/Transforms/DoConcurrent/reduce_device.mlir
diff --git a/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
b/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
index 66b778fecc208..135382abb0227 100644
--- a/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+++ b/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
@@ -140,6 +140,9 @@ void collectLoopLiveIns(fir::DoConcurrentLoopOp loop,
for (mlir::Value local : loop.getLocalVars())
liveIns.push_back(local);
+
+ for (mlir::Value reduce : loop.getReduceVars())
+liveIns.push_back(reduce);
}
/// Collects values that are local to a loop: "loop-local values". A loop-local
@@ -272,7 +275,7 @@ class DoConcurrentConversion
targetOp =
genTargetOp(doLoop.getLoc(), rewriter, mapper, loopNestLiveIns,
targetClauseOps, loopNestClauseOps, liveInShapeInfoMap);
- genTeamsOp(doLoop.getLoc(), rewriter);
+ genTeamsOp(rewriter, loop, mapper);
}
mlir::omp::ParallelOp parallelOp =
@@ -488,46 +491,7 @@ class DoConcurrentConversion
if (!mapToDevice)
genPrivatizers(rewriter, mapper, loop, wsloopClauseOps);
-if (!loop.getReduceVars().empty()) {
- for (auto [op, byRef, sym, arg] : llvm::zip_equal(
- loop.getReduceVars(), loop.getReduceByrefAttr().asArrayRef(),
- loop.getReduceSymsAttr().getAsRange(),
- loop.getRegionReduceArgs())) {
-auto firReducer = moduleSymbolTable.lookup(
-sym.getLeafReference());
-
-mlir::OpBuilder::InsertionGuard guard(rewriter);
-rewriter.setInsertionPointAfter(firReducer);
-std::string ompReducerName = sym.getLeafReference().str() + ".omp";
-
-auto ompReducer =
-moduleSymbolTable.lookup(
-rewriter.getStringAttr(ompReducerName));
-
-if (!ompReducer) {
- ompReducer = mlir::omp::DeclareReductionOp::create(
- rewriter, firReducer.getLoc(), ompReducerName,
- firReducer.getTypeAttr().getValue());
-
- cloneFIRRegionToOMP(rewriter, firReducer.getAllocRegion(),
- ompReducer.getAllocRegion());
- cloneFIRRegionToOMP(rewriter, firReducer.getInitializerRegion(),
- ompReducer.getInitializerRegion());
- cloneFIRRegionToOMP(rewriter, firReducer.getReductionRegion(),
- ompReducer.getReductionRegion());
- cloneFIRRegionToOMP(rewriter, firReducer.getAtomicReductionRegion(),
- ompReducer.getAtomicReductionRegion());
- cloneFIRRegionToOMP(rewriter, firReducer.getCleanupRegion(),
- ompReducer.getCleanupRegion());
- moduleSymbolTable.insert(ompReducer);
-}
-
-wsloopClauseOps.reductionVars.push_back(op);
-wsloopClauseOps.reductionByref.push_back(byRef);
-wsloopClauseOps.reductionSyms.push_back(
-mlir::SymbolRefAttr::get(ompReducer));
- }
-}
+genReductions(rewriter, mapper, loop, wsloopClauseOps);
auto wsloopOp =
mlir::omp::WsloopOp::create(rewriter, loop.getLoc(), wsloopClauseOps);
@@ -549,8 +513,6 @@ class DoConcurrentConversion
rewriter.setInsertionPointToEnd(&loopNestOp.getRegion().back());
mlir::omp::YieldOp::create(rewriter, loop->getLoc());
-loop->getParentOfType().print(
-llvm::errs(), mlir::OpPrintingFlags().assumeVerified());
return {loopNestOp, wsloopOp};
}
@@ -771,15 +733,26 @@ class DoConcurrentConversion
liveInName, shape);
}
- mlir::omp::TeamsOp
- genTeamsOp(mlir::Location loc,
- mlir::ConversionPatternRewriter &rewriter) const {
-auto teamsOp = rewriter.create(
-loc, /*clauses=*/mlir::omp::TeamsOperands{});
+ mlir::omp::TeamsOp genTeamsOp(mlir::ConversionPatternRewriter &rewriter,
[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov created
https://github.com/llvm/llvm-project/pull/156359
These instructions can now be fully decoded automatically.
>From eb4a0870f4a96eddc73d3ae4aaa9dd987c06b832 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
These instructions can now be fully decoded automatically.
---
llvm/lib/Target/Hexagon/CMakeLists.txt| 3 +-
.../Disassembler/HexagonDisassembler.cpp | 62 ++---
.../Target/Hexagon/HexagonDepInstrFormats.td | 129 --
llvm/lib/Target/Hexagon/HexagonOperands.td| 10 +-
4 files changed, 46 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt
b/llvm/lib/Target/Hexagon/CMakeLists.txt
index b615536af03be..d758260a8ab5d 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de10092cbe3c8..f22afd1e15d74 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -173,6 +173,16 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned
tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);
+
+static void n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MCContext &Ctx = Decoder->getContext();
+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
+}
+
+static void sgp10ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+}
+
#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"
@@ -349,21 +359,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr)
const {
}
}
-static void adjustDuplex(MCInst &MI, MCContext &Context) {
- switch (MI.getOpcode()) {
- case Hexagon::SA1_setin1:
-MI.insert(MI.begin() + 1,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- case Hexagon::SA1_dec:
-MI.insert(MI.begin() + 2,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- default:
-break;
- }
-}
-
DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef Bytes,
uint64_t Address,
@@ -468,12 +463,10 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
@@ -499,41 +492,6 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
}
- switch (MI.getOpcode()) {
- case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_f_jumpnv_t:
- case Hexagon::J4_cmpeqn1_fp0_jump_nt:
- case Hexagon::J4_cmpeqn1_fp0_jump_t:
- case Hexagon::J4_cmpeqn1_fp1_jump_nt:
- case Hexagon::J4_cmpeqn1_fp1_jump_t:
- case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_t_jumpnv_t:
- case Hexagon::J4_cmpeqn1_tp0_jump_nt:
- case Hexagon::J4_cmpeqn1_tp0_jump_t:
- case Hexagon::J4_cmpeqn1_tp1_jump_nt:
- case Hexagon::J4_cmpeqn1_tp1_jump_t:
- case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_f_jumpnv_t:
- case Hexagon::J4_cmpgtn1_fp0_jump_nt:
- case Hexagon::J4_cmpgtn1_fp0_jump_t:
- case Hexagon::J4_cmpgtn1_fp1_jump_nt:
- case Hexagon::J4_cmpgtn1_fp1_jump_t:
- case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_t_jumpnv_t:
- case Hexagon::J4_cmpgtn1_tp0_jump_nt:
- case Hexagon::J4_cmpgtn1_tp0_jump_t:
- case Hexagon::J4_
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ed2916521d54928b73305de69b1556d1d8a50f5b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 30 +-
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 48 +++-
.../MCTargetDesc/AArch64MCTargetDesc.h| 7 ---
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
6 files changed, 99 insertions(+), 53 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 8958ad129269c..b0b012214813d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1561,13 +1561,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1617,9 +1615,8 @@ def sme_elm_idx0_0 : Operand, TImmLeaf {
let ParserMatchClass = Imm0_0Operand;
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printMatrixIndex";
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def sme_elm_idx0_1 : Operand, TImmLeaf;
def uimm0s2range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<2, 1>";
let ParserMatchClass = UImm0s2RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm0s4range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<4, 3>";
let ParserMatchClass = UImm0s4RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm1s2range : Operand, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8267,15 +8267,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 96ab999e90dba..52cd681734396 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,14 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static void DecodeMPRRegisterClass(MCInst &Inst, c
[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 4188fa46342e6747f985d232677f6a690fa9972c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 ++-
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 --
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4 +++
5 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 720361dc3da5b..531238ae85029 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc
-gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- --specialize-decoders-per-bitwidth
- -ignore-non-decodable-operands)
+ --specialize-decoders-per-bitwidth)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b1b7ea5246fda..89df9d82f8780 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,12 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +604,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -774,12 +769,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bit
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From b1cd999acbb29fc53f9eb33284a3e5d2bc72bb11 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 5 +
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..98fd0ac3d44ee 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,11 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static void DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Refactor isImmOperandLegal (PR #155607)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155607
>From 20442f6adbd765db0493edabef85228b56b0a1ef Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more variants that can operate without
preconstructed MachineInstrs or MachineOperands.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 38 ---
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 6 +++
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 7
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 9 -
4 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d3bda9f3875e3..887092182f7d1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4572,19 +4572,24 @@ static bool compareMachineOp(const MachineOperand &Op0,
}
}
-bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
-const MachineOperand &MO) const {
- const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
-
- assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
-
+bool SIInstrInfo::isLiteralOperandLegal(const MCInstrDesc &InstDesc,
+const MCOperandInfo &OpInfo) const {
if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
return true;
- if (OpInfo.RegClass < 0)
+ if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
return false;
- if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
+ if (!isVOP3(InstDesc) || !AMDGPU::isSISrcOperand(OpInfo))
+return true;
+
+ return ST.hasVOP3Literal();
+}
+
+bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
+int64_t ImmVal) const {
+ const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
+ if (isInlineConstant(ImmVal, OpInfo.OperandType)) {
if (isMAI(InstDesc) && ST.hasMFMAInlineLiteralBug() &&
OpNo == (unsigned)AMDGPU::getNamedOperandIdx(InstDesc.getOpcode(),
AMDGPU::OpName::src2))
@@ -4592,13 +4597,18 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc
&InstDesc, unsigned OpNo,
return RI.opCanUseInlineConstant(OpInfo.OperandType);
}
- if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
-return false;
+ return isLiteralOperandLegal(InstDesc, OpInfo);
+}
- if (!isVOP3(InstDesc) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
-return true;
+bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
+const MachineOperand &MO) const {
+ if (MO.isImm())
+return isImmOperandLegal(InstDesc, OpNo, MO.getImm());
- return ST.hasVOP3Literal();
+ assert((MO.isTargetIndex() || MO.isFI() || MO.isGlobal()) &&
+ "unexpected imm-like operand kind");
+ const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
+ return isLiteralOperandLegal(InstDesc, OpInfo);
}
bool SIInstrInfo::isLegalAV64PseudoImm(uint64_t Imm) const {
@@ -6268,7 +6278,7 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI,
unsigned OpIdx,
return false;
}
}
- } else if (AMDGPU::isSISrcOperand(InstDesc, i) &&
+ } else if (AMDGPU::isSISrcOperand(InstDesc.operands()[i]) &&
!isInlineConstant(Op, InstDesc.operands()[i])) {
// The same literal may be used multiple times.
if (!UsedLiteral)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 2f9f5c54406a3..1070d4824aa14 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1183,6 +1183,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
const MachineOperand &MO) const;
+ bool isLiteralOperandLegal(const MCInstrDesc &InstDesc,
+ const MCOperandInfo &OpInfo) const;
+
+ bool isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
+ int64_t ImmVal) const;
+
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
const MachineOperand &MO) const {
return isImmOperandLegal(MI.getDesc(), OpNo, MO);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 18ee9c16b3ff9..da19a6faa9e0f 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2720,13 +2720,6 @@ bool isInlineValue(unsigned Reg) {
#undef CASE_GFXPRE11_GFX11PLUS_TO
#undef MAP_REG2REG
-bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
- assert(OpNo < Desc.NumOperands);
- unsigned OpType = Desc.operands()[OpNo].Oper
[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 9f30122b180122b518a4dca079145846bb87e428 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 23 +--
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 +--
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4
5 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 9713d623ea614..47329b2c2f4d2 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index de1bdb4a8811c..084fb43756efc 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,10 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static void DecodeSPRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
{
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +602,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -770,12 +763,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 1, mayStore = 0
[llvm-branch-commits] [llvm] [flang][do concurent] Add saxpy offload tests for OpenMP mapping (PR #155993)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/155993 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][ptr] Extend `ptr_add` operation to support shaped operands (PR #156374)
https://github.com/fabianmcg created
https://github.com/llvm/llvm-project/pull/156374
This patch extends `ptr_add` to work with shaped types with value semantics,
both for the offsets and base.
Concretely this patch makes the following changes:
- Supports scalar-to-scalar, scalar-to-shaped, shaped-to-scalar, and
shaped-to-shaped combinations
- Adds InferTypeOpInterface for automatic result type deduction
- Adds tests for LLVM IR translation with vector operands
Example:
```mlir
func.func @ptr_add_tensor_2d(%ptrs: tensor<4x8x!ptr.ptr<#ptr.generic_space>>,
%offsets: tensor<4x8xindex>) -> tensor<4x8x!ptr.ptr<#ptr.generic_space>> {
%res = ptr.ptr_add %ptrs, %offsets :
tensor<4x8x!ptr.ptr<#ptr.generic_space>>, tensor<4x8xindex>
%res1 = ptr.ptr_add nuw %ptrs, %offsets :
tensor<4x8x!ptr.ptr<#ptr.generic_space>>, tensor<4x8xindex>
return %res : tensor<4x8x!ptr.ptr<#ptr.generic_space>>
}
```
The motivation behind this patch is to lay the groundwork for enabling `triton`
styled loads and stores, and their variants.
>From 6b3215582cde39f2c381933b2634029f72b6274a Mon Sep 17 00:00:00 2001
From: Fabian Mora <[email protected]>
Date: Mon, 1 Sep 2025 21:05:55 +
Subject: [PATCH] extend ptr_add op
---
mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h | 1 +
mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td| 103 +++---
mlir/lib/Dialect/Ptr/IR/CMakeLists.txt| 1 +
mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp| 40 +++
.../Conversion/PtrToLLVM/ptr-to-llvm.mlir | 12 +-
mlir/test/Dialect/Ptr/invalid.mlir| 16 +++
mlir/test/Dialect/Ptr/ops.mlir| 65 +++
mlir/test/Target/LLVMIR/ptr.mlir | 30 +
8 files changed, 225 insertions(+), 43 deletions(-)
diff --git a/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
b/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
index 8686cc7d316d4..eaf1e6243a74d 100644
--- a/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
+++ b/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
@@ -18,6 +18,7 @@
#include "mlir/Dialect/Ptr/IR/PtrDialect.h"
#include "mlir/Dialect/Ptr/IR/PtrTypes.h"
#include "mlir/IR/OpDefinition.h"
+#include "mlir/Interfaces/InferTypeOpInterface.h"
#include "mlir/Interfaces/SideEffectInterfaces.h"
#include "mlir/Interfaces/ViewLikeInterface.h"
diff --git a/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
b/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
index 59eaaf7c55cce..43e19d0e2917c 100644
--- a/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
+++ b/mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
@@ -13,6 +13,7 @@ include "mlir/Dialect/Ptr/IR/PtrDialect.td"
include "mlir/Dialect/Ptr/IR/PtrAttrDefs.td"
include "mlir/Dialect/Ptr/IR/PtrEnums.td"
include "mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td"
+include "mlir/Interfaces/InferTypeOpInterface.td"
include "mlir/Interfaces/SideEffectInterfaces.td"
include "mlir/Interfaces/ViewLikeInterface.td"
include "mlir/IR/OpAsmInterface.td"
@@ -34,8 +35,15 @@ class Ptr_ShapedValueType allowedTypes,
list preds = []> :
/*descr=*/[{A shaped type with value semantics and rank.}],
/*cppType=*/"::mlir::ShapedType">;
-// A shaped pointer type with value semantics and rank.
-class Ptr_ShapedPtrType : Ptr_ShapedValueType<[Ptr_PtrType], [HasRankPred]>;
+// A ptr-like type, either scalar or shaped type with value semantics.
+def Ptr_PtrLikeType :
+ AnyTypeOf<[Ptr_ShapedValueType<[Ptr_PtrType], [HasRankPred]>, Ptr_PtrType]>;
+
+// An int-like type, either scalar or shaped type with value semantics.
+def Ptr_IntLikeType :AnyTypeOf<[
+ Ptr_ShapedValueType<[AnySignlessIntegerOrIndex], [HasRankPred]>,
+ AnySignlessIntegerOrIndex
+]>;
// A shaped value type of rank 1 of any element type.
def Ptr_Any1DType :
@@ -175,41 +183,6 @@ def Ptr_GetMetadataOp : Pointer_Op<"get_metadata", [
}];
}
-//===--===//
-// PtrAddOp
-//===--===//
-
-def Ptr_PtrAddOp : Pointer_Op<"ptr_add", [
-Pure, AllTypesMatch<["base", "result"]>, ViewLikeOpInterface
- ]> {
- let summary = "Pointer add operation";
- let description = [{
-The `ptr_add` operation adds an integer offset to a pointer to produce a
new
-pointer. The input and output pointer types are always the same.
-
-Example:
-
-```mlir
-%x_off = ptr.ptr_add %x, %off : !ptr.ptr<#ptr.generic_space>, i32
-%x_off0 = ptr.ptr_add nusw %x, %off : !ptr.ptr<#ptr.generic_space>, i32
-```
- }];
-
- let arguments = (ins
-Ptr_PtrType:$base,
-AnySignlessIntegerOrIndex:$offset,
-DefaultValuedProp, "PtrAddFlags::none">:$flags);
- let results = (outs Ptr_PtrType:$result);
- let assemblyFormat = [{
-($flags^)? $base `,` $offset attr-dict `:` type($base) `,` type($offset)
- }];
- let hasFolder = 1;
- let extraClassDeclaration = [{
-/// `ViewLikeOp::getViewSource` method.
-Value getViewSource() { return getBase(); }
- }];
-}
[llvm-branch-commits] [mlir] [mlir][ptr] Add translations to LLVMIR for ptr ops. (PR #156355)
llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
Author: Fabian Mora (fabianmcg)
Changes
Implements translation from ptr dialect to LLVM IR for core pointer operations:
- `ptr.ptr_add` -> `getelementptr`
- `ptr.load` -> `load` with atomic ordering, volatility, and metadata support
- `ptr.store` -> `store` with atomic ordering, volatility, and metadata
support
- `ptr.type_offset` -> GEP-based size computation
Example:
```mlir
llvm.func @test(%arg0: !ptr.ptr<#llvm.address_space<0>>) {
%0 = ptr.type_offset f64 : i32
%1 = ptr.ptr_add inbounds %arg0, %0 :
!ptr.ptr<#llvm.address_space<0>>, i32
%2 = ptr.load volatile %1 : !ptr.ptr<#llvm.address_space<0>>
-> f64
ptr.store %2, %arg0 : f64, !ptr.ptr<#llvm.address_space<0>>
llvm.return
}
```
Translates to:
```llvm
define void @test(ptr %0) {
%2 = getelementptr inbounds i8, ptr %0, i32 8
%3 = load volatile double, ptr %2, align 8
store double %3, ptr %0, align 8
ret void
}
```
---
Full diff: https://github.com/llvm/llvm-project/pull/156355.diff
3 Files Affected:
- (modified) mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td (+1-2)
- (modified) mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
(+202-8)
- (modified) mlir/test/Target/LLVMIR/ptr.mlir (+75)
``diff
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
index d6aa9580870a8..bd59319c79ad3 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
@@ -95,8 +95,7 @@ def LLVM_NonLoadableTargetExtType : Type<
// type that has size (not void, function, opaque struct type or target
// extension type which does not support memory operations).
def LLVM_LoadableType : Type<
- Or<[And<[LLVM_PrimitiveType.predicate, Neg,
- Neg]>,
+ Or<[CPred<"mlir::LLVM::isLoadableType($_self)">,
LLVM_PointerElementTypeInterface.predicate]>,
"LLVM type with size">;
diff --git a/mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
b/mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
index 7b89ec8fcbffb..e3ccf728f25db 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
@@ -16,11 +16,193 @@
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/Operation.h"
#include "mlir/Target/LLVMIR/ModuleTranslation.h"
+#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
using namespace mlir;
using namespace mlir::ptr;
namespace {
+
+/// Converts ptr::AtomicOrdering to llvm::AtomicOrdering
+static llvm::AtomicOrdering
+convertAtomicOrdering(ptr::AtomicOrdering ordering) {
+ switch (ordering) {
+ case ptr::AtomicOrdering::not_atomic:
+return llvm::AtomicOrdering::NotAtomic;
+ case ptr::AtomicOrdering::unordered:
+return llvm::AtomicOrdering::Unordered;
+ case ptr::AtomicOrdering::monotonic:
+return llvm::AtomicOrdering::Monotonic;
+ case ptr::AtomicOrdering::acquire:
+return llvm::AtomicOrdering::Acquire;
+ case ptr::AtomicOrdering::release:
+return llvm::AtomicOrdering::Release;
+ case ptr::AtomicOrdering::acq_rel:
+return llvm::AtomicOrdering::AcquireRelease;
+ case ptr::AtomicOrdering::seq_cst:
+return llvm::AtomicOrdering::SequentiallyConsistent;
+ }
+ llvm_unreachable("Unknown atomic ordering");
+}
+
+/// Convert ptr.ptr_add operation
+static LogicalResult
+convertPtrAddOp(PtrAddOp ptrAddOp, llvm::IRBuilderBase &builder,
+LLVM::ModuleTranslation &moduleTranslation) {
+ llvm::Value *basePtr = moduleTranslation.lookupValue(ptrAddOp.getBase());
+ llvm::Value *offset = moduleTranslation.lookupValue(ptrAddOp.getOffset());
+
+ if (!basePtr || !offset)
+return ptrAddOp.emitError("Failed to lookup operands");
+
+ // Create GEP instruction for pointer arithmetic
+ llvm::GetElementPtrInst *gep = llvm::GetElementPtrInst::Create(
+ builder.getInt8Ty(), basePtr, {offset}, "", builder.GetInsertBlock());
+
+ // Set the appropriate flags
+ switch (ptrAddOp.getFlags()) {
+ case ptr::PtrAddFlags::none:
+break;
+ case ptr::PtrAddFlags::nusw:
+gep->setNoWrapFlags(llvm::GEPNoWrapFlags::noUnsignedSignedWrap());
+break;
+ case ptr::PtrAddFlags::nuw:
+gep->setNoWrapFlags(llvm::GEPNoWrapFlags::noUnsignedWrap());
+break;
+ case ptr::PtrAddFlags::inbounds:
+gep->setNoWrapFlags(llvm::GEPNoWrapFlags::inBounds());
+break;
+ }
+
+ moduleTranslation.mapValue(ptrAddOp.getResult(), gep);
+ return success();
+}
+
+/// Convert ptr.load operation
+static LogicalResult convertLoadOp(LoadOp loadOp, llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation)
{
+ llvm::Value *ptr = moduleTranslation.lookupValue(loadOp.getPtr());
+ if (!ptr)
+return loadOp.emitError("Failed to lookup pointer operand");
+
+ // Convert
[llvm-branch-commits] [llvm] release/21.x: [LoongArch] Fix broadcast load with extension. (#155960) (PR #156384)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156384
Backport 2320529ff77338cd0cb9786b8f195d611edcae77
Requested by: @tangaac
>From f557b56527c19e6209d8bb24a7039a1084822754 Mon Sep 17 00:00:00 2001
From: tangaac
Date: Mon, 1 Sep 2025 18:28:17 +0800
Subject: [PATCH] [LoongArch] Fix broadcast load with extension. (#155960)
PR #135896 introduces [x]vldrepl instructions without handling
extension.
This patch will fix that.
(cherry picked from commit 2320529ff77338cd0cb9786b8f195d611edcae77)
---
.../LoongArch/LoongArchISelLowering.cpp | 9 --
.../CodeGen/LoongArch/lasx/broadcast-load.ll | 26 +
.../CodeGen/LoongArch/lsx/broadcast-load.ll | 28 +--
3 files changed, 58 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 12cf04bbbab56..d6adcf37f06f9 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2430,11 +2430,14 @@ static SDValue
lowerBUILD_VECTORAsBroadCastLoad(BuildVectorSDNode *BVOp,
}
// make sure that this load is valid and only has one user.
- if (!IdentitySrc || !BVOp->isOnlyUserOf(IdentitySrc.getNode()))
+ if (!IsIdeneity || !IdentitySrc ||
!BVOp->isOnlyUserOf(IdentitySrc.getNode()))
return SDValue();
- if (IsIdeneity) {
-auto *LN = cast(IdentitySrc);
+ auto *LN = cast(IdentitySrc);
+ auto ExtType = LN->getExtensionType();
+
+ if ((ExtType == ISD::EXTLOAD || ExtType == ISD::NON_EXTLOAD) &&
+ VT.getScalarSizeInBits() == LN->getMemoryVT().getScalarSizeInBits()) {
SDVTList Tys =
LN->isIndexed()
? DAG.getVTList(VT, LN->getBasePtr().getValueType(), MVT::Other)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
index 976924bdca686..6035b8822cef7 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
@@ -18,6 +18,32 @@ define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr
%dst) {
ret <4 x i64> %tmp2
}
+define <16 x i16> @should_not_be_optimized_sext_load(ptr %ptr) {
+; CHECK-LABEL: should_not_be_optimized_sext_load:
+; CHECK: # %bb.0:
+; CHECK-NEXT:ld.b $a0, $a0, 0
+; CHECK-NEXT:xvreplgr2vr.h $xr0, $a0
+; CHECK-NEXT:ret
+ %tmp = load i8, ptr %ptr
+ %tmp1 = sext i8 %tmp to i16
+ %tmp2 = insertelement <16 x i16> zeroinitializer, i16 %tmp1, i32 0
+ %tmp3 = shufflevector <16 x i16> %tmp2, <16 x i16> poison, <16 x i32>
zeroinitializer
+ ret <16 x i16> %tmp3
+}
+
+define <16 x i16> @should_not_be_optimized_zext_load(ptr %ptr) {
+; CHECK-LABEL: should_not_be_optimized_zext_load:
+; CHECK: # %bb.0:
+; CHECK-NEXT:ld.bu $a0, $a0, 0
+; CHECK-NEXT:xvreplgr2vr.h $xr0, $a0
+; CHECK-NEXT:ret
+ %tmp = load i8, ptr %ptr
+ %tmp1 = zext i8 %tmp to i16
+ %tmp2 = insertelement <16 x i16> zeroinitializer, i16 %tmp1, i32 0
+ %tmp3 = shufflevector <16 x i16> %tmp2, <16 x i16> poison, <16 x i32>
zeroinitializer
+ ret <16 x i16> %tmp3
+}
+
define <4 x i64> @xvldrepl_d_unaligned_offset(ptr %ptr) {
; CHECK-LABEL: xvldrepl_d_unaligned_offset:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
index c46747ef30509..f058acf5e45e5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
-; TODO: Load a element and splat it to a vector could be lowerd to vldrepl
-
; A load has more than one user shouldn't be lowered to vldrepl
define <2 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst){
; CHECK-LABEL: should_not_be_optimized:
@@ -18,6 +16,32 @@ define <2 x i64> @should_not_be_optimized(ptr %ptr, ptr
%dst){
ret <2 x i64> %tmp2
}
+define <8 x i16> @should_not_be_optimized_sext_load(ptr %ptr) {
+; CHECK-LABEL: should_not_be_optimized_sext_load:
+; CHECK: # %bb.0:
+; CHECK-NEXT:ld.b $a0, $a0, 0
+; CHECK-NEXT:vreplgr2vr.h $vr0, $a0
+; CHECK-NEXT:ret
+ %tmp = load i8, ptr %ptr
+ %tmp1 = sext i8 %tmp to i16
+ %tmp2 = insertelement <8 x i16> zeroinitializer, i16 %tmp1, i32 0
+ %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> poison, <8 x i32>
zeroinitializer
+ ret <8 x i16> %tmp3
+}
+
+define <8 x i16> @should_not_be_optimized_zext_load(ptr %ptr) {
+; CHECK-LABEL: should_not_be_optimized_zext_load:
+; CHECK: # %bb.0:
+; CHECK-NEXT:ld.bu $a0, $a0, 0
+; CHECK-NEXT:vreplgr2vr.h $vr0, $a0
+; CHECK-NEXT:ret
+ %tmp = load i8, ptr %ptr
+ %tmp1 = zext i8 %tmp to i16
+ %tmp2 = insertelement <8 x i16> zeroinitializer, i16 %tmp1, i32 0
+ %tmp3 = shufflevector <8 x
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 2237e5a7ed147c1a1f279d1549c6e56c24a55d7e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 30 +-
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 48 +++-
.../MCTargetDesc/AArch64MCTargetDesc.h| 7 ---
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
6 files changed, 99 insertions(+), 53 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 8958ad129269c..b0b012214813d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1561,13 +1561,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1617,9 +1615,8 @@ def sme_elm_idx0_0 : Operand, TImmLeaf {
let ParserMatchClass = Imm0_0Operand;
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printMatrixIndex";
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def sme_elm_idx0_1 : Operand, TImmLeaf;
def uimm0s2range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<2, 1>";
let ParserMatchClass = UImm0s2RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm0s4range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<4, 3>";
let ParserMatchClass = UImm0s4RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm1s2range : Operand, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8267,15 +8267,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 96ab999e90dba..52cd681734396 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,14 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static void DecodeMPRRegisterClass(MCInst &Inst, c
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
s-barannikov wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156361?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#156364** https://app.graphite.dev/github/pr/llvm/llvm-project/156364?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156363** https://app.graphite.dev/github/pr/llvm/llvm-project/156363?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156362** https://app.graphite.dev/github/pr/llvm/llvm-project/156362?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156361** https://app.graphite.dev/github/pr/llvm/llvm-project/156361?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/156361?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#156360** https://app.graphite.dev/github/pr/llvm/llvm-project/156360?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156359** https://app.graphite.dev/github/pr/llvm/llvm-project/156359?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156358** https://app.graphite.dev/github/pr/llvm/llvm-project/156358?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/156361 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Fix adding m0 uses to gfx94/gfx12 ds atomics (PR #156402)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156402
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid trying
to match the nonexistent m0-having form.
>From 2bb4e1ea00da3f337b7daefe08c71faea0f2a919 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 2 Sep 2025 13:40:13 +0900
Subject: [PATCH] AMDGPU: Fix adding m0 uses to gfx94/gfx12 ds atomics
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid trying
to match the nonexistent m0-having form.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 108 ---
1 file changed, 57 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 611695bd26d3a..2de89e1262e9c 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -468,6 +468,56 @@ class DSAtomicRetPat {
+ let OtherPredicates = [LDSRequiresM0Init] in {
+def : DSAtomicRetPat(frag#"_local_m0_"#vt)>;
+ }
+
+ let OtherPredicates = [NotLDSRequiresM0Init] in {
+def : DSAtomicRetPat(!cast(inst)#"_gfx9"), vt,
+ !cast(frag#"_local_"#vt)>;
+ }
+
+ let OtherPredicates = [HasGDS] in {
+def : DSAtomicRetPat(frag#"_region_m0_"#vt),
+ /* complexity */ 0, /* gds */ 1>;
+ }
+}
+
+multiclass DSAtomicRetNoRetPat_NoM0_mc {
+ def : DSAtomicRetPat(frag#"_local_"#vt)>;
+ def : DSAtomicRetPat(frag#"_local_noret_"#vt), /* complexity
*/ 1>;
+}
+
+multiclass DSAtomicRetNoRetPat_mc {
+ let OtherPredicates = [LDSRequiresM0Init] in {
+def : DSAtomicRetPat(frag#"_local_m0_"#vt)>;
+def : DSAtomicRetPat(frag#"_local_m0_noret_"#vt), /*
complexity */ 1>;
+ }
+
+ let OtherPredicates = [NotLDSRequiresM0Init] in {
+defm : DSAtomicRetNoRetPat_NoM0_mc<
+ !cast(!cast(inst)#"_gfx9"),
+ !cast(!cast(noRetInst)#"_gfx9"),
+ vt, frag>;
+ }
+
+ let OtherPredicates = [HasGDS] in {
+def : DSAtomicRetPat(frag#"_region_m0_"#vt),
+ /* complexity */ 0, /* gds */ 1>;
+def : DSAtomicRetPat(frag#"_region_m0_noret_"#vt),
+ /* complexity */ 1, /* gds */ 1>;
+ }
+}
+
defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">;
defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">;
defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">;
@@ -518,10 +568,10 @@ let SubtargetPredicate = HasLdsAtomicAddF64 in {
} // End SubtargetPredicate = HasLdsAtomicAddF64
let SubtargetPredicate = HasAtomicDsPkAdd16Insts in {
- defm DS_PK_ADD_F16 : DS_1A1D_NORET_mc<"ds_pk_add_f16">;
- defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_f16", VGPR_32>;
- defm DS_PK_ADD_BF16 : DS_1A1D_NORET_mc<"ds_pk_add_bf16">;
- defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_bf16", VGPR_32>;
+ defm DS_PK_ADD_F16 : DS_1A1D_NORET_mc_gfx9<"ds_pk_add_f16">;
+ defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc_gfx9<"ds_pk_add_rtn_f16", VGPR_32>;
+ defm DS_PK_ADD_BF16 : DS_1A1D_NORET_mc_gfx9<"ds_pk_add_bf16">;
+ defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc_gfx9<"ds_pk_add_rtn_bf16", VGPR_32>;
} // End SubtargetPredicate = HasAtomicDsPkAdd16Insts
defm DS_CMPSTORE_B32 : DS_1A2D_NORET_mc<"ds_cmpstore_b32">;
@@ -1088,50 +1138,6 @@ defm : DSWritePat_mc ;
} // End AddedComplexity = 100
-multiclass DSAtomicRetPat_mc {
- let OtherPredicates = [LDSRequiresM0Init] in {
-def : DSAtomicRetPat(frag#"_local_m0_"#vt)>;
- }
-
- let OtherPredicates = [NotLDSRequiresM0Init] in {
-def : DSAtomicRetPat(!cast(inst)#"_gfx9"), vt,
- !cast(frag#"_local_"#vt)>;
- }
-
- let OtherPredicates = [HasGDS] in {
-def : DSAtomicRetPat(frag#"_region_m0_"#vt),
- /* complexity */ 0, /* gds */ 1>;
- }
-}
-
-multiclass DSAtomicRetNoRetPat_mc {
- let OtherPredicates = [LDSRequiresM0Init] in {
-def : DSAtomicRetPat(frag#"_local_m0_"#vt)>;
-def : DSAtomicRetPat(frag#"_local_m0_noret_"#vt), /*
complexity */ 1>;
- }
-
- let OtherPredicates = [NotLDSRequiresM0Init] in {
-def : DSAtomicRetPat(!cast(inst)#"_gfx9"), vt,
- !cast(frag#"_local_"#vt)>;
-def : DSAtomicRetPat(!cast(noRetInst)#"_gfx9"),
vt,
- !cast(frag#"_local_noret_"#vt), /*
complexity */ 1>;
- }
-
- let OtherPredicates = [HasGDS] in {
-def : DSAtomicRetPat(frag#"_region_m0_"#vt),
- /* complexity */ 0, /* gds */ 1>;
-def : DSAtomicRetPat(frag#"_region_m0_noret_"#vt),
- /* complexity */ 1, /* gds */ 1>;
- }
-}
-
-
-
let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
// Caution, the order of src and cmp is the *opposite* of the
BUFF
[llvm-branch-commits] Frontend: Adopt llvm::vfs::OutputBackend in CompilerInstance (PR #113364)
cachemeifyoucan wrote: > This seems good, perhaps after #113363 lands, it'd be interesting to rebase > and run some build-time tests, just to ensure it doesn't introduce > regressions. Yup! We don't see anything on our end but it will be good to double check. https://github.com/llvm/llvm-project/pull/113364 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Remarks] BitstreamRemarkParser: Refactor error handling (PR #156511)
https://github.com/tobias-stadler created https://github.com/llvm/llvm-project/pull/156511 In preparation of larger changes to the bitstream remark format, refactor the error handling code in the BitstreamRemarkParser. Main change: move the various static helper methods into the parser helper classes, so we don't need to pass around as many args. Calling `error(...)` inside the helper classes now automatically prepends the current block being parsed to the error message. NFCI (except for error messages on invalid bitstream files). ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 235b15d6a19c5810cdbbb2d111b5f614a86082a0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 5 +
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..98fd0ac3d44ee 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,11 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static void DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
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[llvm-branch-commits] [llvm] AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check (PR #155603)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155603
>From 5c284f46a1063d5d0788c25a0d37ba019c171d54 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 16:19:23 +0900
Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in
usesConstantBus check
This loop over all the operands in the MachineInstr will eventually
go past the end of the MCInstrDesc's explicit operands. We don't
need the instr desc to compute the constant bus usage, just the
register and whether it's implicit or not. The check here is slightly
conservative. e.g. a random vcc implicit use appended to an instruction
will falsely report a constant bus use.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 62 --
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 ++
2 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c5e8f95748cf1..4cf8fd5eb594f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4758,6 +4758,35 @@ MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr
&MI,
return Inst32;
}
+bool SIInstrInfo::physRegUsesConstantBus(const MachineOperand &RegOp) const {
+ // Null is free
+ Register Reg = RegOp.getReg();
+ if (Reg == AMDGPU::SGPR_NULL || Reg == AMDGPU::SGPR_NULL64)
+return false;
+
+ // SGPRs use the constant bus
+
+ // FIXME: implicit registers that are not part of the MCInstrDesc's implicit
+ // physical register operands should also count.
+ if (RegOp.isImplicit())
+return Reg == AMDGPU::VCC || Reg == AMDGPU::VCC_LO || Reg == AMDGPU::M0;
+
+ // Normal exec read does not count.
+ if ((Reg == AMDGPU::EXEC || Reg == AMDGPU::EXEC_LO) && RegOp.isImplicit())
+return false;
+
+ // SGPRs use the constant bus
+ return AMDGPU::SReg_32RegClass.contains(Reg) ||
+ AMDGPU::SReg_64RegClass.contains(Reg);
+}
+
+bool SIInstrInfo::regUsesConstantBus(const MachineOperand &RegOp,
+ const MachineRegisterInfo &MRI) const {
+ Register Reg = RegOp.getReg();
+ return Reg.isVirtual() ? RI.isSGPRClass(MRI.getRegClass(Reg))
+ : physRegUsesConstantBus(RegOp);
+}
+
bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
const MachineOperand &MO,
const MCOperandInfo &OpInfo) const {
@@ -4765,23 +4794,9 @@ bool SIInstrInfo::usesConstantBus(const
MachineRegisterInfo &MRI,
if (!MO.isReg())
return !isInlineConstant(MO, OpInfo);
- if (!MO.isUse())
-return false;
-
- if (MO.getReg().isVirtual())
-return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
-
- // Null is free
- if (MO.getReg() == AMDGPU::SGPR_NULL || MO.getReg() == AMDGPU::SGPR_NULL64)
-return false;
-
- // SGPRs use the constant bus
- if (MO.isImplicit()) {
-return MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
- MO.getReg() == AMDGPU::VCC_LO;
- }
- return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
- AMDGPU::SReg_64RegClass.contains(MO.getReg());
+ Register Reg = MO.getReg();
+ return Reg.isVirtual() ? RI.isSGPRClass(MRI.getRegClass(Reg))
+ : physRegUsesConstantBus(MO);
}
static Register findImplicitSGPRRead(const MachineInstr &MI) {
@@ -6250,13 +6265,12 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr
&MI, unsigned OpIdx,
continue;
const MachineOperand &Op = MI.getOperand(i);
if (Op.isReg()) {
-RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
-if (!SGPRsUsed.count(SGPR) &&
-// FIXME: This can access off the end of the operands() array.
-usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) {
- if (--ConstantBusLimit <= 0)
-return false;
- SGPRsUsed.insert(SGPR);
+if (Op.isUse()) {
+ RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
+ if (regUsesConstantBus(Op, MRI) && SGPRsUsed.insert(SGPR).second) {
+if (--ConstantBusLimit <= 0)
+ return false;
+ }
}
} else if (AMDGPU::isSISrcOperand(InstDesc, i) &&
!isInlineConstant(Op, InstDesc.operands()[i])) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 958af0ff1147f..2f9f5c54406a3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1195,6 +1195,10 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// This function will return false if you pass it a 32-bit instruction.
bool hasVALU32BitEncoding(unsigned Opcode) const;
+ bool physRegUsesConstantBus(const MachineOperand &Reg) const;
+ bool regUsesConstantBus(const MachineOperand &Reg,
+ const MachineRegisterInfo &MRI) const;
+
/// Returns true if this operand uses the constant bus.
[llvm-branch-commits] [clang] [LifetimeSafety] Mark all DeclRefExpr as usages of the corresp. origin (PR #154316)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From 34480e096c560bdc47b66febda32a95854ed619a Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analysis/LifetimeSafety.cpp | 90 +--
.../Sema/warn-lifetime-safety-dataflow.cpp| 25 ++
2 files changed, 89 insertions(+), 26 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index f493fcf32f61e..94e0b734db09a 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -119,6 +119,7 @@ class OriginManager {
return AllOrigins.back();
}
+ // TODO: Mark this method as const once we remove the call to getOrCreate.
OriginID get(const Expr &E) {
// Origin of DeclRefExpr is that of the declaration it refers to.
if (const auto *DRE = dyn_cast(&E))
@@ -315,22 +316,28 @@ class ReturnOfOriginFact : public Fact {
};
class UseFact : public Fact {
- OriginID UsedOrigin;
const Expr *UseExpr;
+ // True if this use is a write operation (e.g., left-hand side of
assignment).
+ // Write operations are exempted from use-after-free checks.
+ bool IsWritten = false;
public:
static bool classof(const Fact *F) { return F->getKind() == Kind::Use; }
- UseFact(OriginID UsedOrigin, const Expr *UseExpr)
- : Fact(Kind::Use), UsedOrigin(UsedOrigin), UseExpr(UseExpr) {}
+ UseFact(const Expr *UseExpr) : Fact(Kind::Use), UseExpr(UseExpr) {}
- OriginID getUsedOrigin() const { return UsedOrigin; }
+ OriginID getUsedOrigin(const OriginManager &OM) const {
+// TODO: Remove const cast and make OriginManager::get as const.
+return const_cast(OM).get(*UseExpr);
+ }
const Expr *getUseExpr() const { return UseExpr; }
+ void markAsWritten() { IsWritten = true; }
+ bool isWritten() const { return IsWritten; }
void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
OS << "Use (";
-OM.dump(getUsedOrigin(), OS);
-OS << ")\n";
+OM.dump(getUsedOrigin(OM), OS);
+OS << " " << (isWritten() ? "Write" : "Read") << ")\n";
}
};
@@ -425,6 +432,8 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
addAssignOriginFact(*VD, *InitExpr);
}
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+
void VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *N) {
/// TODO: Handle nullptr expr as a special 'null' loan. Uninitialized
/// pointers can use the same type of loan.
@@ -458,10 +467,6 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
}
}
}
-} else if (UO->getOpcode() == UO_Deref) {
- // This is a pointer use, like '*p'.
- OriginID OID = FactMgr.getOriginMgr().get(*UO->getSubExpr());
- CurrentBlockFacts.push_back(FactMgr.createFact(OID, UO));
}
}
@@ -476,20 +481,13 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
}
void VisitBinaryOperator(const BinaryOperator *BO) {
-if (BO->isAssignmentOp()) {
- const Expr *LHSExpr = BO->getLHS();
- const Expr *RHSExpr = BO->getRHS();
-
- // We are interested in assignments like `ptr1 = ptr2` or `ptr = &var`
- // LHS must be a pointer/reference type that can be an origin.
- // RHS must also represent an origin (either another pointer/ref or an
- // address-of).
- if (const auto *DRE_LHS = dyn_cast(LHSExpr))
-if (const auto *VD_LHS =
-dyn_cast(DRE_LHS->getDecl()->getCanonicalDecl());
-VD_LHS && hasOrigin(VD_LHS->getType()))
- addAssignOriginFact(*VD_LHS, *RHSExpr);
-}
+if (BO->isAssignmentOp())
+ handleAssignment(BO->getLHS(), BO->getRHS());
+ }
+
+ void VisitCXXOperatorCallExpr(const CXXOperatorCallExpr *OCE) {
+if (OCE->isAssignmentOp() && OCE->getNumArgs() == 2)
+ handleAssignment(OCE->getArg(0), OCE->getArg(1));
}
void VisitCXXFunctionalCastExpr(const CXXFunctionalCastExpr *FCE) {
@@ -556,8 +554,47 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+dyn_cast(LHSExpr->IgnoreParenImpCasts())) {
+ markUseAsWrite(DRE_LHS);
+ if (const auto *VD_LHS = dyn_cast(DRE_LHS->getDecl()))
+if (hasOrigin(VD_LHS->getType()))
+ // We are interested in assignments like `ptr1 = ptr2` or `ptr =
&var`
+ // LHS must be a pointer/reference type that can be an origin.
+ // RHS must also represent an origin (either another pointer/ref or
an
+ // address-of).
+ addAssignOriginFact(*VD_LHS, *RHSExpr);
+}
+ }
+
+ // A DeclRefExpr is a use of the referenced decl. It is checked for
+ // use-aft
[llvm-branch-commits] [clang-tools-extra] [clangd] Show type hint for simple cases of dependent 'auto' (PR #156284)
llvmbot wrote:
@llvm/pr-subscribers-clangd
Author: Nathan Ridge (HighCommander4)
Changes
Fixes https://github.com/clangd/clangd/issues/2275
---
Full diff: https://github.com/llvm/llvm-project/pull/156284.diff
2 Files Affected:
- (modified) clang-tools-extra/clangd/InlayHints.cpp (+24-7)
- (modified) clang-tools-extra/clangd/unittests/InlayHintTests.cpp (+2-1)
``diff
diff --git a/clang-tools-extra/clangd/InlayHints.cpp
b/clang-tools-extra/clangd/InlayHints.cpp
index cd479e1b7c9bc..d56b93e5f36dc 100644
--- a/clang-tools-extra/clangd/InlayHints.cpp
+++ b/clang-tools-extra/clangd/InlayHints.cpp
@@ -633,13 +633,30 @@ class InlayHintVisitor : public
RecursiveASTVisitor {
}
if (auto *AT = D->getType()->getContainedAutoType()) {
- if (AT->isDeduced() && !D->getType()->isDependentType()) {
-// Our current approach is to place the hint on the variable
-// and accordingly print the full type
-// (e.g. for `const auto& x = 42`, print `const int&`).
-// Alternatively, we could place the hint on the `auto`
-// (and then just print the type deduced for the `auto`).
-addTypeHint(D->getLocation(), D->getType(), /*Prefix=*/": ");
+ if (AT->isDeduced()) {
+QualType T;
+// If the type is dependent, HeuristicResolver *may* be able to
+// resolve it to something that's useful to print. In other
+// cases, it can't, and the resultng type would just be printed
+// as "", in which case don't hint it at all.
+if (D->getType()->isDependentType()) {
+ if (D->hasInit()) {
+QualType Resolved = Resolver->resolveExprToType(D->getInit());
+if (Resolved != AST.DependentTy) {
+ T = Resolved;
+}
+ }
+} else {
+ T = D->getType();
+}
+if (!T.isNull()) {
+ // Our current approach is to place the hint on the variable
+ // and accordingly print the full type
+ // (e.g. for `const auto& x = 42`, print `const int&`).
+ // Alternatively, we could place the hint on the `auto`
+ // (and then just print the type deduced for the `auto`).
+ addTypeHint(D->getLocation(), T, /*Prefix=*/": ");
+}
}
}
diff --git a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
index 99e728c40063d..feb4404b3d2bf 100644
--- a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
+++ b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
@@ -1441,7 +1441,8 @@ TEST(TypeHints, DependentType) {
void bar(T arg) {
auto [a, b] = arg;
}
- )cpp");
+ )cpp",
+ ExpectedHint{": T", "var2"});
}
TEST(TypeHints, LongTypeName) {
``
https://github.com/llvm/llvm-project/pull/156284
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[llvm-branch-commits] [flang] [flang][OpenMP] `do concurrent`: support `local` on device (PR #156589)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/156589 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LV] Bundle partial reductions inside VPExpressionRecipe (PR #147302)
https://github.com/SamTebbs33 closed https://github.com/llvm/llvm-project/pull/147302 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 95a0d748eae948d6c520dd4706cac52cc830ecfd Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
These instructions can now be fully decoded automatically.
---
llvm/lib/Target/Hexagon/CMakeLists.txt| 3 +-
.../Disassembler/HexagonDisassembler.cpp | 65 ++---
.../Target/Hexagon/HexagonDepInstrFormats.td | 129 --
llvm/lib/Target/Hexagon/HexagonOperands.td| 10 +-
4 files changed, 49 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt
b/llvm/lib/Target/Hexagon/CMakeLists.txt
index b615536af03be..d758260a8ab5d 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de10092cbe3c8..0639878c1256f 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -173,6 +173,19 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned
tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);
+
+static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MCContext &Ctx = Decoder->getContext();
+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
+ return DecodeStatus::Success;
+}
+
+static DecodeStatus sgp10ConstDecoder(MCInst &MI,
+ const MCDisassembler *Decoder) {
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ return DecodeStatus::Success;
+}
+
#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"
@@ -349,21 +362,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr)
const {
}
}
-static void adjustDuplex(MCInst &MI, MCContext &Context) {
- switch (MI.getOpcode()) {
- case Hexagon::SA1_setin1:
-MI.insert(MI.begin() + 1,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- case Hexagon::SA1_dec:
-MI.insert(MI.begin() + 2,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- default:
-break;
- }
-}
-
DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef Bytes,
uint64_t Address,
@@ -468,12 +466,10 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
@@ -499,41 +495,6 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
}
- switch (MI.getOpcode()) {
- case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_f_jumpnv_t:
- case Hexagon::J4_cmpeqn1_fp0_jump_nt:
- case Hexagon::J4_cmpeqn1_fp0_jump_t:
- case Hexagon::J4_cmpeqn1_fp1_jump_nt:
- case Hexagon::J4_cmpeqn1_fp1_jump_t:
- case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_t_jumpnv_t:
- case Hexagon::J4_cmpeqn1_tp0_jump_nt:
- case Hexagon::J4_cmpeqn1_tp0_jump_t:
- case Hexagon::J4_cmpeqn1_tp1_jump_nt:
- case Hexagon::J4_cmpeqn1_tp1_jump_t:
- case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_f_jumpnv_t:
- case Hexagon::J4_cmpgtn1_fp0_jump_nt:
- case Hexagon::J4_cmpgtn1_fp0_jump_t:
- case Hexagon::J4_cmpgtn1_fp1_jump_nt:
- case Hexagon::J4_cmpgtn1_fp1_jump_t:
- case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_t_jumpnv_t:
- case Hexagon::J4_cmpgtn1_tp0_jump_nt:
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 6ff221b947f637f100c1e8db3d2df2651beff3af Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 5 +
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..98fd0ac3d44ee 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,11 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static void DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
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[llvm-branch-commits] [llvm] AMDGPU: Handle true16 disassembly of ds_write_b8/b16 (PR #156406)
@@ -4447,76 +4447,76 @@ # GFX11: ds_store_b128 v255, v[2:5] offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00] 0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00 -# GFX11: ds_store_b16 v0, v1 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00] +# GFX11: ds_store_b16 v0, v1.l ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00] jayfoad wrote: Using the `.l` syntax is not right here. This is not a true16 operand, cos you can't specify v0.h but you can specify v255.l (with an 8-bit instruction field). So it's a normal 32-bit operand but the instruction happens to only use the low 16 bits of data from it. https://github.com/llvm/llvm-project/pull/156406 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][ptr] Extend `ptr_add` operation to support shaped operands (PR #156374)
github-actions[bot] wrote: ⚠️ We detected that you are using a GitHub private e-mail address to contribute to the repo. Please turn off [Keep my email addresses private](https://github.com/settings/emails) setting in your account. See [LLVM Developer Policy](https://llvm.org/docs/DeveloperPolicy.html#email-addresses) and [LLVM Discourse](https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it) for more information. https://github.com/llvm/llvm-project/pull/156374 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] `do concurrent`: support `local` on device (PR #156589)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/156589 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] Make lld tests use lit internal shell by default (PR #156538)
https://github.com/petrhosek approved this pull request. https://github.com/llvm/llvm-project/pull/156538 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [lld] Update tests redirecting multiple commands to FileCheck (PR #156526)
https://github.com/cmtice approved this pull request. https://github.com/llvm/llvm-project/pull/156526 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From fd7e685e86a7f20048293d8bb9f5a60b613b3737 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 23 +--
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 +--
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4
5 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 720361dc3da5b..531238ae85029 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc
-gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- --specialize-decoders-per-bitwidth
- -ignore-non-decodable-operands)
+ --specialize-decoders-per-bitwidth)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b1b7ea5246fda..e31b826d8e22a 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,10 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static void DecodeSPRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
{
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +602,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -774,12 +767,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CLoad_r
[llvm-branch-commits] [llvm] [AArch64][SME] Support agnostic ZA functions in the MachineSMEABIPass (PR #149064)
@@ -250,6 +286,9 @@ struct MachineSMEABI : public MachineFunctionPass {
SmallVector BundleStates;
std::optional TPIDR2Block;
std::optional AfterSMEProloguePt;
+Register AgnosticZABufferPtr = AArch64::NoRegister;
+LiveRegs PhysLiveRegsAfterSMEPrologue = LiveRegs::None;
+bool HasFullZASaveRestore = false;
gbossu wrote:
Could you document what a "full ZA save/restore" is? How does this differ from
the "plain" save/restore?
https://github.com/llvm/llvm-project/pull/149064
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[llvm-branch-commits] [llvm] [AArch64] Correctly disassemble TSB instruction (PR #156362)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From c82858d3ba2267af6638e29d2601715b582a2968 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.
This instruction can now be disassembled correctly.
---
llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 3 +--
.../lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 7 ---
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1b0e90b0e0dc3..65b752ed40c90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex {
let Key = ["Name"];
}
-def : TSB<"csync", 0>;
+def : TSB<"csync", 2>;
//===--===//
// PRFM (prefetch) instruction options.
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 833ce48ea1d7a..79b56ea9cf850 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer
-asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands
- -ignore-fully-defined-operands)
+ -ignore-non-decodable-operands)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 54b58e948daf2..2552ee3009338 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI,
uint64_t Address,
return;
}
- // Instruction TSB is specified as a one operand instruction, but 'csync' is
- // not encoded, so for printing it is treated as a special case here:
- if (Opcode == AArch64::TSB) {
-O << "\ttsb\tcsync";
-return;
- }
-
if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
printInstruction(MI, Address, STI, O);
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[llvm-branch-commits] [llvm] release/21.x: [CMake][AIX] Enable CMP0182: Create shared library archives by default (#155686) (PR #156504)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/156504 Backport 94738ddaf42a0fa1981dc083f9ed94ba11943458 Requested by: @amy-kwan >From 58a31b4aa15cfa88cade7a0ebe66a14396a7e007 Mon Sep 17 00:00:00 2001 From: David Tenty Date: Thu, 28 Aug 2025 09:29:27 -0400 Subject: [PATCH] [CMake][AIX] Enable CMP0182: Create shared library archives by default (#155686) On AIX we prefer to create shared libraries as shared library archives (i.e. we archive the shared object in a big AR archive) as this is the standard format on the platform. There is now a CMake policy that allows us to do this by default, so opt-in to that behaviour. - Co-authored-by: Hubert Tong (cherry picked from commit 94738ddaf42a0fa1981dc083f9ed94ba11943458) --- cmake/Modules/CMakePolicy.cmake | 6 ++ 1 file changed, 6 insertions(+) diff --git a/cmake/Modules/CMakePolicy.cmake b/cmake/Modules/CMakePolicy.cmake index 421f5a4dda6c6..cf986331707b6 100644 --- a/cmake/Modules/CMakePolicy.cmake +++ b/cmake/Modules/CMakePolicy.cmake @@ -41,3 +41,9 @@ if(POLICY CMP0156) cmake_policy(SET CMP0179 NEW) endif() endif() + +# CMP0182: Create shared library archives by default on AIX. +# New in CMake 4.0: https://cmake.org/cmake/help/latest/policy/CMP0182.html +if(POLICY CMP0182) + cmake_policy(SET CMP0182 NEW) +endif() ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][ptr] Add `gather`, `masked_load`, `masked_store`, and `scatter` ops (PR #156368)
@@ -17,6 +17,46 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
include "mlir/Interfaces/ViewLikeInterface.td"
include "mlir/IR/OpAsmInterface.td"
+//===--===//
+// Common props
+//===--===//
+
+def AlignmentProp : OptionalProp;
+
+//===--===//
+// Common types
+//===--===//
+
+// A shaped value type with value semantics and rank.
+class Ptr_ShapedValueType allowedTypes, list preds = []> :
+ ShapedContainerType,
+/*descr=*/[{A shaped type with value semantics and rank.}],
+/*cppType=*/"::mlir::ShapedType">;
+
+// A shaped pointer type with value semantics and rank.
+class Ptr_ShapedPtrType : Ptr_ShapedValueType<[Ptr_PtrType], [HasRankPred]>;
+
+// A shaped value type of rank 1 of any element type.
+def Ptr_Any1DType :
+ Ptr_ShapedValueType<[AnyType], [HasAnyRankOfPred<[1]>]>;
+
+// A shaped value type of rank 1 of `i1` element type.
+def Ptr_Mask1DType :
+ Ptr_ShapedValueType<[I1], [HasAnyRankOfPred<[1]>]>;
+
+// A shaped value type of rank 1 of `i1` element type.
+def Ptr_Ptr1DType :
+ Ptr_ShapedValueType<[Ptr_PtrType], [HasAnyRankOfPred<[1]>]>;
+
+// Gets the type ID of a type.
+class TypeIDType :
+StrFunc<"$" # name # ".getType().getTypeID()">;
+
+// Checks that all type IDs match.
+class AllTypeIDsMatch names> :
fabianmcg wrote:
I didn't add it to `OpBase.td` because this is the only consumer. I'll move it
to `OpBase.td`.
https://github.com/llvm/llvm-project/pull/156368
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[llvm-branch-commits] [llvm] release/21.x: [SLP]Do not to try to revectorize previously vectorized phis in loops (PR #156297)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-vectorizers
Author: None (llvmbot)
Changes
Backport 7730ebce8e8fa84db4da04a7d8fe1977ccbf28ff
Requested by: @nikic
---
Patch is 23.11 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/156297.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (+4-1)
- (added) llvm/test/Transforms/SLPVectorizer/X86/revectorize-phis.ll (+193)
``diff
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index f6610ea5b333f..2d50981690f41 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -9968,7 +9968,10 @@ BoUpSLP::getScalarsVectorizationLegality(ArrayRef VL, unsigned Depth,
}
SmallPtrSet Values(llvm::from_range, E->Scalars);
if (all_of(VL, [&](Value *V) {
-return isa(V) || Values.contains(V);
+return isa(V) || Values.contains(V) ||
+ (S.getOpcode() == Instruction::PHI && isa(V) &&
+LI->getLoopFor(S.getMainOp()->getParent()) &&
+isVectorized(V));
})) {
LLVM_DEBUG(dbgs() << "SLP: Gathering due to full overlap.\n");
return ScalarsVectorizationLegality(S, /*IsLegal=*/false);
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revectorize-phis.ll
b/llvm/test/Transforms/SLPVectorizer/X86/revectorize-phis.ll
new file mode 100644
index 0..9eec3074b5345
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/revectorize-phis.ll
@@ -0,0 +1,193 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s |
FileCheck %s
+
+define void @test() {
+; CHECK-LABEL: define void @test() {
+; CHECK-NEXT: [[BB:.*]]:
+; CHECK-NEXT:br label %[[BB1:.*]]
+; CHECK: [[BB1]]:
+; CHECK-NEXT:[[PHI:%.*]] = phi i64 [ 0, %[[BB]] ], [ [[PHI]], %[[BB31:.*]]
], [ [[PHI]], %[[BB32:.*]] ], [ [[PHI]], %[[BB33:.*]] ], [ [[PHI]],
%[[BB36:.*]] ], [ [[PHI]], %[[BB39:.*]] ], [ [[PHI]], %[[BB40:.*]] ], [
[[PHI]], %[[BB41:.*]] ], [ [[PHI]], %[[BB42:.*]] ], [ [[PHI]], %[[BB43:.*]] ],
[ 0, %[[BB45:.*]] ], [ [[PHI]], %[[BB21:.*]] ], [ [[PHI]], %[[BB22:.*]] ], [
[[PHI]], %[[BB23:.*]] ], [ [[PHI]], %[[BB24:.*]] ], [ [[PHI]], %[[BB25:.*]] ],
[ [[PHI]], %[[BB26:.*]] ], [ [[PHI]], %[[BB27:.*]] ], [ [[PHI]], %[[BB28:.*]]
], [ [[PHI]], %[[BB29:.*]] ], [ 0, %[[BB30:.*]] ]
+; CHECK-NEXT:[[PHI2:%.*]] = phi i64 [ undef, %[[BB]] ], [ [[PHI2]],
%[[BB31]] ], [ [[PHI2]], %[[BB32]] ], [ [[PHI2]], %[[BB33]] ], [ [[PHI2]],
%[[BB36]] ], [ [[PHI2]], %[[BB39]] ], [ [[PHI2]], %[[BB40]] ], [ [[PHI2]],
%[[BB41]] ], [ [[PHI2]], %[[BB42]] ], [ [[LOAD44:%.*]], %[[BB43]] ], [
[[PHI2]], %[[BB45]] ], [ [[PHI2]], %[[BB21]] ], [ 0, %[[BB22]] ], [ [[PHI2]],
%[[BB23]] ], [ [[PHI2]], %[[BB24]] ], [ [[PHI2]], %[[BB25]] ], [ [[PHI2]],
%[[BB26]] ], [ [[PHI2]], %[[BB27]] ], [ [[PHI2]], %[[BB28]] ], [ [[PHI2]],
%[[BB29]] ], [ [[PHI2]], %[[BB30]] ]
+; CHECK-NEXT:[[PHI3:%.*]] = phi i64 [ 0, %[[BB]] ], [ 0, %[[BB31]] ], [
[[PHI3]], %[[BB32]] ], [ [[PHI3]], %[[BB33]] ], [ [[PHI3]], %[[BB36]] ], [
[[PHI3]], %[[BB39]] ], [ [[PHI3]], %[[BB40]] ], [ [[PHI3]], %[[BB41]] ], [ 0,
%[[BB42]] ], [ [[PHI3]], %[[BB43]] ], [ [[PHI3]], %[[BB45]] ], [ [[PHI3]],
%[[BB21]] ], [ [[PHI3]], %[[BB22]] ], [ [[PHI3]], %[[BB23]] ], [ [[PHI3]],
%[[BB24]] ], [ [[PHI3]], %[[BB25]] ], [ [[PHI3]], %[[BB26]] ], [ [[PHI3]],
%[[BB27]] ], [ [[PHI3]], %[[BB28]] ], [ [[PHI3]], %[[BB29]] ], [ [[PHI3]],
%[[BB30]] ]
+; CHECK-NEXT:[[PHI4:%.*]] = phi i64 [ 0, %[[BB]] ], [ [[PHI4]], %[[BB31]]
], [ [[PHI4]], %[[BB32]] ], [ [[PHI4]], %[[BB33]] ], [ [[PHI4]], %[[BB36]] ], [
[[PHI4]], %[[BB39]] ], [ [[PHI4]], %[[BB40]] ], [ [[PHI4]], %[[BB41]] ], [
[[PHI4]], %[[BB42]] ], [ [[PHI4]], %[[BB43]] ], [ [[PHI4]], %[[BB45]] ], [
[[PHI4]], %[[BB21]] ], [ [[PHI4]], %[[BB22]] ], [ [[PHI4]], %[[BB23]] ], [
[[PHI4]], %[[BB24]] ], [ [[PHI4]], %[[BB25]] ], [ [[PHI4]], %[[BB26]] ], [ 0,
%[[BB27]] ], [ [[PHI4]], %[[BB28]] ], [ [[PHI4]], %[[BB29]] ], [ [[PHI4]],
%[[BB30]] ]
+; CHECK-NEXT:[[PHI5:%.*]] = phi i64 [ undef, %[[BB]] ], [ [[PHI5]],
%[[BB31]] ], [ [[PHI5]], %[[BB32]] ], [ [[PHI5]], %[[BB33]] ], [ [[PHI5]],
%[[BB36]] ], [ 0, %[[BB39]] ], [ [[PHI5]], %[[BB40]] ], [ [[PHI5]], %[[BB41]]
], [ [[PHI5]], %[[BB42]] ], [ [[PHI5]], %[[BB43]] ], [ [[PHI5]], %[[BB45]] ], [
0, %[[BB21]] ], [ [[PHI5]], %[[BB22]] ], [ [[PHI5]], %[[BB23]] ], [ [[PHI5]],
%[[BB24]] ], [ [[PHI5]], %[[BB25]] ], [ [[PHI5]], %[[BB26]] ], [ [[PHI5]],
%[[BB27]] ], [ [[PHI5]], %[[BB28]] ], [ [[PHI5]], %[[BB29]] ], [ [[PHI5]],
%[[BB30]] ]
+; CHECK-NEXT:[[PHI6:%.*]] = phi i64 [ undef, %[[BB]] ], [ [[PHI6]],
%[[BB31]] ], [ 0, %[[BB32]] ], [ 0, %[[BB33]] ], [ [[LOAD38:%.*]], %[[BB36]] ],
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From c66fd0b127a34082ebc277ede621073c121ce0dd Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 30 +-
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 50 -
.../MCTargetDesc/AArch64MCTargetDesc.h| 3 +-
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
6 files changed, 102 insertions(+), 48 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 8958ad129269c..b0b012214813d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1561,13 +1561,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1617,9 +1615,8 @@ def sme_elm_idx0_0 : Operand, TImmLeaf {
let ParserMatchClass = Imm0_0Operand;
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printMatrixIndex";
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def sme_elm_idx0_1 : Operand, TImmLeaf;
def uimm0s2range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<2, 1>";
let ParserMatchClass = UImm0s2RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm0s4range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<4, 3>";
let ParserMatchClass = UImm0s4RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm1s2range : Operand, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8267,15 +8267,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 96ab999e90dba..fb4930ea1a755 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,16 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static void DecodeMPRRegisterClass(MCInst &Inst,
[llvm-branch-commits] [clang-tools-extra] [clangd] Show type hint for simple cases of dependent 'auto' (PR #156284)
@@ -633,13 +633,30 @@ class InlayHintVisitor : public
RecursiveASTVisitor {
}
if (auto *AT = D->getType()->getContainedAutoType()) {
- if (AT->isDeduced() && !D->getType()->isDependentType()) {
-// Our current approach is to place the hint on the variable
-// and accordingly print the full type
-// (e.g. for `const auto& x = 42`, print `const int&`).
-// Alternatively, we could place the hint on the `auto`
-// (and then just print the type deduced for the `auto`).
-addTypeHint(D->getLocation(), D->getType(), /*Prefix=*/": ");
+ if (AT->isDeduced()) {
+QualType T;
+// If the type is dependent, HeuristicResolver *may* be able to
+// resolve it to something that's useful to print. In other
+// cases, it can't, and the resultng type would just be printed
+// as "", in which case don't hint it at all.
+if (D->getType()->isDependentType()) {
+ if (D->hasInit()) {
+QualType Resolved = Resolver->resolveExprToType(D->getInit());
+if (Resolved != AST.DependentTy) {
zyn0217 wrote:
Yes, but my question was why we don't call isDependentType instead, is there
any specific issue that we have to compare with the builtin type?
https://github.com/llvm/llvm-project/pull/156284
___
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[llvm-branch-commits] [clang] [LifetimeSafety] Add support for GSL Pointer types (PR #154009)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From aa5c2209c8358e5716182e9db2a66a5ddfb4fcfe Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 17 Aug 2025 10:10:18 +
Subject: [PATCH] [LifetimeSafety] Track gsl::Pointer types
---
clang/lib/Analysis/LifetimeSafety.cpp | 137 +++--
clang/test/Sema/warn-lifetime-safety.cpp | 120 +++-
.../unittests/Analysis/LifetimeSafetyTest.cpp | 182 +-
3 files changed, 411 insertions(+), 28 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 94e0b734db09a..b96680f952695 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -434,6 +434,31 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitCXXConstructExpr(const CXXConstructExpr *CCE) {
+if (!isGslPointerType(CCE->getType()))
+ return;
+if (CCE->getNumArgs() != 1)
+ return;
+if (hasOrigin(CCE->getArg(0)->getType()))
+ addAssignOriginFact(*CCE, *CCE->getArg(0));
+else
+ // This could be a new borrow.
+ handleFucntionCall(CCE, CCE->getConstructor(),
+ {CCE->getArgs(), CCE->getNumArgs()});
+ }
+
+ void VisitCXXMemberCallExpr(const CXXMemberCallExpr *MCE) {
+// Specifically for conversion operators,
+// like `std::string_view p = std::string{};`
+if (isGslPointerType(MCE->getType()) &&
+isa(MCE->getCalleeDecl())) {
+ // The argument is the implicit object itself.
+ handleFucntionCall(MCE, MCE->getMethodDecl(),
+ {MCE->getImplicitObjectArgument()});
+}
+// FIXME: A more general VisitCallExpr could also be used here.
+ }
+
void VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *N) {
/// TODO: Handle nullptr expr as a special 'null' loan. Uninitialized
/// pointers can use the same type of loan.
@@ -454,18 +479,9 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
void VisitUnaryOperator(const UnaryOperator *UO) {
if (UO->getOpcode() == UO_AddrOf) {
const Expr *SubExpr = UO->getSubExpr();
- if (const auto *DRE = dyn_cast(SubExpr)) {
-if (const auto *VD = dyn_cast(DRE->getDecl())) {
- // Check if it's a local variable.
- if (VD->hasLocalStorage()) {
-OriginID OID = FactMgr.getOriginMgr().getOrCreate(*UO);
-AccessPath AddrOfLocalVarPath(VD);
-const Loan &L =
-FactMgr.getLoanMgr().addLoan(AddrOfLocalVarPath, UO);
-CurrentBlockFacts.push_back(
-FactMgr.createFact(L.ID, OID));
- }
-}
+ if (const Loan *L = createLoanFrom(SubExpr, UO)) {
+OriginID OID = FactMgr.getOriginMgr().getOrCreate(*UO);
+CurrentBlockFacts.push_back(FactMgr.createFact(L->ID, OID));
}
}
}
@@ -493,10 +509,27 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
void VisitCXXFunctionalCastExpr(const CXXFunctionalCastExpr *FCE) {
// Check if this is a test point marker. If so, we are done with this
// expression.
-if (VisitTestPoint(FCE))
+if (handleTestPoint(FCE))
return;
-// Visit as normal otherwise.
-Base::VisitCXXFunctionalCastExpr(FCE);
+if (isGslPointerType(FCE->getType()))
+ addAssignOriginFact(*FCE, *FCE->getSubExpr());
+ }
+
+ void VisitInitListExpr(const InitListExpr *ILE) {
+if (!hasOrigin(ILE->getType()))
+ return;
+// For list initialization with a single element, like `View{...}`, the
+// origin of the list itself is the origin of its single element.
+if (ILE->getNumInits() == 1)
+ addAssignOriginFact(*ILE, *ILE->getInit(0));
+ }
+
+ void VisitMaterializeTemporaryExpr(const MaterializeTemporaryExpr *MTE) {
+if (!hasOrigin(MTE->getType()))
+ return;
+// A temporary object's origin is the same as the origin of the
+// expression that initializes it.
+addAssignOriginFact(*MTE, *MTE->getSubExpr());
}
void handleDestructor(const CFGAutomaticObjDtor &DtorOpt) {
@@ -522,8 +555,78 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
}
private:
+ static bool isGslPointerType(QualType QT) {
+if (const auto *RD = QT->getAsCXXRecordDecl()) {
+ // We need to check the template definition for specializations.
+ if (auto *CTSD = dyn_cast(RD))
+return CTSD->getSpecializedTemplate()
+->getTemplatedDecl()
+->hasAttr();
+ return RD->hasAttr();
+}
+return false;
+ }
+
// Check if a type has an origin.
- bool hasOrigin(QualType QT) { return QT->isPointerOrReferenceType(); }
+ static bool hasOrigin(QualType QT) {
+if (QT->isFunctionPointerType())
+ return false;
+return QT->isPointerOrReferenceType() || isGslPointerType(QT);
+ }
+
+ /// Checks if a call-like ex
[llvm-branch-commits] [mlir] [mlir][ptr] Add `gather`, `masked_load`, `masked_store`, and `scatter` ops (PR #156368)
github-actions[bot] wrote: ⚠️ We detected that you are using a GitHub private e-mail address to contribute to the repo. Please turn off [Keep my email addresses private](https://github.com/settings/emails) setting in your account. See [LLVM Developer Policy](https://llvm.org/docs/DeveloperPolicy.html#email-addresses) and [LLVM Discourse](https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it) for more information. https://github.com/llvm/llvm-project/pull/156368 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] `do concurrent`: support `local` on device (PR #156589)
https://github.com/ergawy created
https://github.com/llvm/llvm-project/pull/156589
Extends support for mapping `do concurrent` on the device by adding support for
`local` specifiers. The changes in this PR map the local variable to the
`omp.target` op and uses the mapped value as the `private` clause operand in
the nested `omp.parallel` op.
>From 78fc5ed0cbe7211bf89c744b0e8301bfe1722295 Mon Sep 17 00:00:00 2001
From: ergawy
Date: Tue, 2 Sep 2025 05:54:00 -0500
Subject: [PATCH] [flang][OpenMP] `do concurrent`: support `local` on device
Extends support for mapping `do concurrent` on the device by adding
support for `local` specifiers. The changes in this PR map the local
variable to the `omp.target` op and uses the mapped value as the
`private` clause operand in the nested `omp.parallel` op.
---
.../include/flang/Optimizer/Dialect/FIROps.td | 12 ++
.../OpenMP/DoConcurrentConversion.cpp | 192 +++---
.../Transforms/DoConcurrent/local_device.mlir | 49 +
3 files changed, 175 insertions(+), 78 deletions(-)
create mode 100644 flang/test/Transforms/DoConcurrent/local_device.mlir
diff --git a/flang/include/flang/Optimizer/Dialect/FIROps.td
b/flang/include/flang/Optimizer/Dialect/FIROps.td
index bc971e8fd6600..fc6eedc6ed4c6 100644
--- a/flang/include/flang/Optimizer/Dialect/FIROps.td
+++ b/flang/include/flang/Optimizer/Dialect/FIROps.td
@@ -3894,6 +3894,18 @@ def fir_DoConcurrentLoopOp : fir_Op<"do_concurrent.loop",
return getReduceVars().size();
}
+unsigned getInductionVarsStart() {
+ return 0;
+}
+
+unsigned getLocalOperandsStart() {
+ return getNumInductionVars();
+}
+
+unsigned getReduceOperandsStart() {
+ return getLocalOperandsStart() + getNumLocalOperands();
+}
+
mlir::Block::BlockArgListType getInductionVars() {
return getBody()->getArguments().slice(0, getNumInductionVars());
}
diff --git a/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
b/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
index a800a20129abe..66b778fecc208 100644
--- a/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+++ b/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
@@ -137,6 +137,9 @@ void collectLoopLiveIns(fir::DoConcurrentLoopOp loop,
liveIns.push_back(operand->get());
});
+
+ for (mlir::Value local : loop.getLocalVars())
+liveIns.push_back(local);
}
/// Collects values that are local to a loop: "loop-local values". A loop-local
@@ -251,8 +254,7 @@ class DoConcurrentConversion
.getIsTargetDevice();
mlir::omp::TargetOperands targetClauseOps;
- genLoopNestClauseOps(doLoop.getLoc(), rewriter, loop, mapper,
- loopNestClauseOps,
+ genLoopNestClauseOps(doLoop.getLoc(), rewriter, loop, loopNestClauseOps,
isTargetDevice ? nullptr : &targetClauseOps);
LiveInShapeInfoMap liveInShapeInfoMap;
@@ -274,14 +276,13 @@ class DoConcurrentConversion
}
mlir::omp::ParallelOp parallelOp =
-genParallelOp(doLoop.getLoc(), rewriter, ivInfos, mapper);
+genParallelOp(rewriter, loop, ivInfos, mapper);
// Only set as composite when part of `distribute parallel do`.
parallelOp.setComposite(mapToDevice);
if (!mapToDevice)
- genLoopNestClauseOps(doLoop.getLoc(), rewriter, loop, mapper,
- loopNestClauseOps);
+ genLoopNestClauseOps(doLoop.getLoc(), rewriter, loop, loopNestClauseOps);
for (mlir::Value local : locals)
looputils::localizeLoopLocalValue(local, parallelOp.getRegion(),
@@ -290,10 +291,38 @@ class DoConcurrentConversion
if (mapToDevice)
genDistributeOp(doLoop.getLoc(), rewriter).setComposite(/*val=*/true);
-mlir::omp::LoopNestOp ompLoopNest =
+auto [loopNestOp, wsLoopOp] =
genWsLoopOp(rewriter, loop, mapper, loopNestClauseOps,
/*isComposite=*/mapToDevice);
+// `local` region arguments are transferred/cloned from the `do concurrent`
+// loop to the loopnest op when the region is cloned above. Instead, these
+// region arguments should be on the workshare loop's region.
+if (mapToDevice) {
+ for (auto [parallelArg, loopNestArg] : llvm::zip_equal(
+ parallelOp.getRegion().getArguments(),
+ loopNestOp.getRegion().getArguments().slice(
+ loop.getLocalOperandsStart(), loop.getNumLocalOperands(
+rewriter.replaceAllUsesWith(loopNestArg, parallelArg);
+
+ for (auto [wsloopArg, loopNestArg] : llvm::zip_equal(
+ wsLoopOp.getRegion().getArguments(),
+ loopNestOp.getRegion().getArguments().slice(
+ loop.getReduceOperandsStart(),
loop.getNumReduceOperands(
+rewriter.replaceAllUsesWith(loopNestArg, wsloopArg);
+} else {
+ for (auto [wsloopArg, loopNestArg] :
+ llvm::zip_equal(wsLoopOp.getRegion().getArguments(),
[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d01399ac76d639e7474a8ae382395d1985e64ff7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 ++-
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 --
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4 +++
5 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 720361dc3da5b..531238ae85029 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc
-gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- --specialize-decoders-per-bitwidth
- -ignore-non-decodable-operands)
+ --specialize-decoders-per-bitwidth)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b1b7ea5246fda..89df9d82f8780 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,12 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +604,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -774,12 +769,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bit
[llvm-branch-commits] [llvm] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (PR #156363)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From f3b4f276760009154caa8140dc5b92651dfbe4db Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
These are the only instructions that encode two operands in the same
field. Instead of fixing them after they have been incorrectly decoded,
provide a custom decoder.
---
.../Disassembler/AArch64Disassembler.cpp | 29 ---
llvm/lib/Target/AArch64/SMEInstrFormats.td| 4 +++
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 23e46b84f6278..8c1e9f61693fb 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1563,6 +1563,25 @@ static DecodeStatus DecodePRFMRegInstruction(MCInst
&Inst, uint32_t insn,
return Success;
}
+static DecodeStatus
+DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
+ const MCDisassembler *Decoder) {
+ unsigned RvBits = fieldFromInstruction(Bits, 13, 2);
+ unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
+ unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
+
+ DecodeSimpleRegisterClass(
+ Inst, RvBits, Addr, Decoder);
+ Inst.addOperand(MCOperand::createImm(Imm4Bits));
+ DecodeSimpleRegisterClass(Inst, RnBits,
+ Addr, Decoder);
+ // Spill and fill instructions have a single immediate used for both
+ // the vector select offset and optional memory offset. Replicate
+ // the decoded immediate.
+ Inst.addOperand(MCOperand::createImm(Imm4Bits));
+ return Success;
+}
+
#include "AArch64GenDisassemblerTables.inc"
#include "AArch64GenInstrInfo.inc"
@@ -1621,16 +1640,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst
&MI, uint64_t &Size,
}
}
-if (MI.getOpcode() == AArch64::LDR_ZA ||
-MI.getOpcode() == AArch64::STR_ZA) {
- // Spill and fill instructions have a single immediate used for both
- // the vector select offset and optional memory offset. Replicate
- // the decoded immediate.
- const MCOperand &Imm4Op = MI.getOperand(2);
- assert(Imm4Op.isImm() && "Unexpected operand type!");
- MI.addOperand(Imm4Op);
-}
-
if (Result != MCDisassembler::Fail)
return Result;
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td
b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index b3005d5120229..40ec371fe79d3 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1108,6 +1108,10 @@ class sme_spill_fill_base
: I,
Sched<[]> {
+ // 'offset' operand is encoded in the same bits as 'imm4'. There is currently
+ // no way to tell TableGen about this.
+ let DecoderMethod = "DecodeSMESpillFillInstruction";
+ bits<0> ZAt;
bits<2> Rv;
bits<5> Rn;
bits<4> imm4;
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 01a8d9d7026b94f1cf060a8f12ad27df6e70ee2b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
These instructions can now be fully decoded automatically.
---
llvm/lib/Target/Hexagon/CMakeLists.txt| 3 +-
.../Disassembler/HexagonDisassembler.cpp | 65 ++---
.../Target/Hexagon/HexagonDepInstrFormats.td | 129 --
llvm/lib/Target/Hexagon/HexagonOperands.td| 10 +-
4 files changed, 49 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt
b/llvm/lib/Target/Hexagon/CMakeLists.txt
index b615536af03be..d758260a8ab5d 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de10092cbe3c8..0639878c1256f 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -173,6 +173,19 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned
tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);
+
+static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MCContext &Ctx = Decoder->getContext();
+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
+ return DecodeStatus::Success;
+}
+
+static DecodeStatus sgp10ConstDecoder(MCInst &MI,
+ const MCDisassembler *Decoder) {
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ return DecodeStatus::Success;
+}
+
#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"
@@ -349,21 +362,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr)
const {
}
}
-static void adjustDuplex(MCInst &MI, MCContext &Context) {
- switch (MI.getOpcode()) {
- case Hexagon::SA1_setin1:
-MI.insert(MI.begin() + 1,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- case Hexagon::SA1_dec:
-MI.insert(MI.begin() + 2,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- default:
-break;
- }
-}
-
DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef Bytes,
uint64_t Address,
@@ -468,12 +466,10 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
@@ -499,41 +495,6 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
}
- switch (MI.getOpcode()) {
- case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_f_jumpnv_t:
- case Hexagon::J4_cmpeqn1_fp0_jump_nt:
- case Hexagon::J4_cmpeqn1_fp0_jump_t:
- case Hexagon::J4_cmpeqn1_fp1_jump_nt:
- case Hexagon::J4_cmpeqn1_fp1_jump_t:
- case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_t_jumpnv_t:
- case Hexagon::J4_cmpeqn1_tp0_jump_nt:
- case Hexagon::J4_cmpeqn1_tp0_jump_t:
- case Hexagon::J4_cmpeqn1_tp1_jump_nt:
- case Hexagon::J4_cmpeqn1_tp1_jump_t:
- case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_f_jumpnv_t:
- case Hexagon::J4_cmpgtn1_fp0_jump_nt:
- case Hexagon::J4_cmpgtn1_fp0_jump_t:
- case Hexagon::J4_cmpgtn1_fp1_jump_nt:
- case Hexagon::J4_cmpgtn1_fp1_jump_t:
- case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_t_jumpnv_t:
- case Hexagon::J4_cmpgtn1_tp0_jump_nt:
[llvm-branch-commits] [llvm] [ARM] Remove most post-decoding instruction adjustments (PR #156540)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From a4b01316df9cc4cbaddb92c6f62d3803f5b4600d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
---
llvm/lib/Target/ARM/ARMInstrCDE.td| 4 +
llvm/lib/Target/ARM/ARMInstrFormats.td| 9 +-
llvm/lib/Target/ARM/ARMInstrMVE.td| 1 +
llvm/lib/Target/ARM/ARMInstrThumb.td | 10 +
llvm/lib/Target/ARM/ARMInstrThumb2.td | 23 +-
llvm/lib/Target/ARM/CMakeLists.txt| 3 +-
.../ARM/Disassembler/ARMDisassembler.cpp | 370 +++---
llvm/test/MC/Disassembler/ARM/arm-tests.txt | 2 +-
8 files changed, 269 insertions(+), 153 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrCDE.td
b/llvm/lib/Target/ARM/ARMInstrCDE.td
index 54e27a6be5583..5d4e3acf5b581 100644
--- a/llvm/lib/Target/ARM/ARMInstrCDE.td
+++ b/llvm/lib/Target/ARM/ARMInstrCDE.td
@@ -115,6 +115,7 @@ class CDE_CX1_Instr
!con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
params.Cstr> {
+ bits<0> p;
bits<13> imm;
bits<4> Rd;
@@ -131,6 +132,7 @@ class CDE_CX2_Instr
!con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
params.Cstr> {
+ bits<0> p;
bits<9> imm;
bits<4> Rd;
bits<4> Rn;
@@ -149,6 +151,7 @@ class CDE_CX3_Instr
!con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm,
$imm"),
params.Cstr> {
+ bits<0> p;
bits<6> imm;
bits<4> Rd;
bits<4> Rn;
@@ -268,6 +271,7 @@ class CDE_Vec_Instr,
CDE_RequiresQReg {
+ bits<0> vp;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td
b/llvm/lib/Target/ARM/ARMInstrFormats.td
index e50740f7d57c5..dc815e1124fa5 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -1219,6 +1219,8 @@ class Thumb1sI pattern>
: InstThumb {
+ bits<0> s;
+ bits<0> p;
let OutOperandList = !con(oops, (outs s_cc_out:$s));
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${s}${p}", asm);
@@ -1243,6 +1245,7 @@ class Thumb1pI pattern>
: InstThumb {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1341,7 +1344,8 @@ class T1Misc opcode> : Encoding16 {
class Thumb2I pattern>
- : InstARM {
+: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1360,6 +1364,7 @@ class Thumb2sI pattern>
: InstARM {
+ bits<0> p;
bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
let Inst{20} = s;
@@ -2220,6 +2225,7 @@ class NeonI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
@@ -2233,6 +2239,7 @@ class NeonXI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", "\t", asm);
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td
b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 9dffd945d5baa..e24413465799f 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -409,6 +409,7 @@ class MVE_p {
+ bits<0> vp;
let Inst{31-29} = 0b111;
let Inst{27-26} = 0b11;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td
b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 0c5ea3e0fa8d5..bc1b34c691e39 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -483,6 +483,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
// A6.2.3 & A8.6.25
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b000;
@@ -491,6 +492,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
Requires<[IsThumb, Has8MSecExt]>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b100;
@@ -523,6 +525,7 @@ let isCall = 1,
"bl${p}\t$func",
[(ARMcall tglobaladdr:$func)]>,
Requires<[IsThumb]>, Sched<[WriteBrL]> {
+bits<0> p;
bits<24> func;
let Inst{26} = func{23};
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ee67c361e4f40b314cd8e2ef4b262f5059c2c40d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 30 +-
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 54 +-
.../MCTargetDesc/AArch64MCTargetDesc.h| 6 --
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
6 files changed, 106 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index feff59061aa16..e0e299cf4afdf 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1559,13 +1559,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1615,9 +1613,8 @@ def sme_elm_idx0_0 : Operand, TImmLeaf {
let ParserMatchClass = Imm0_0Operand;
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printMatrixIndex";
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def sme_elm_idx0_1 : Operand, TImmLeaf;
def uimm0s2range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<2, 1>";
let ParserMatchClass = UImm0s2RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm0s4range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<4, 3>";
let ParserMatchClass = UImm0s4RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm1s2range : Operand, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8265,15 +8265,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 8c1e9f61693fb..647a6a3d76ef8 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static DecodeStatus DecodeMPRRegisterClass(MCIns
[llvm-branch-commits] [llvm] [ARM] Remove most post-decoding instruction adjustments (PR #156540)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From a4b01316df9cc4cbaddb92c6f62d3803f5b4600d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
---
llvm/lib/Target/ARM/ARMInstrCDE.td| 4 +
llvm/lib/Target/ARM/ARMInstrFormats.td| 9 +-
llvm/lib/Target/ARM/ARMInstrMVE.td| 1 +
llvm/lib/Target/ARM/ARMInstrThumb.td | 10 +
llvm/lib/Target/ARM/ARMInstrThumb2.td | 23 +-
llvm/lib/Target/ARM/CMakeLists.txt| 3 +-
.../ARM/Disassembler/ARMDisassembler.cpp | 370 +++---
llvm/test/MC/Disassembler/ARM/arm-tests.txt | 2 +-
8 files changed, 269 insertions(+), 153 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrCDE.td
b/llvm/lib/Target/ARM/ARMInstrCDE.td
index 54e27a6be5583..5d4e3acf5b581 100644
--- a/llvm/lib/Target/ARM/ARMInstrCDE.td
+++ b/llvm/lib/Target/ARM/ARMInstrCDE.td
@@ -115,6 +115,7 @@ class CDE_CX1_Instr
!con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
params.Cstr> {
+ bits<0> p;
bits<13> imm;
bits<4> Rd;
@@ -131,6 +132,7 @@ class CDE_CX2_Instr
!con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
params.Cstr> {
+ bits<0> p;
bits<9> imm;
bits<4> Rd;
bits<4> Rn;
@@ -149,6 +151,7 @@ class CDE_CX3_Instr
!con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm,
$imm"),
params.Cstr> {
+ bits<0> p;
bits<6> imm;
bits<4> Rd;
bits<4> Rn;
@@ -268,6 +271,7 @@ class CDE_Vec_Instr,
CDE_RequiresQReg {
+ bits<0> vp;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td
b/llvm/lib/Target/ARM/ARMInstrFormats.td
index e50740f7d57c5..dc815e1124fa5 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -1219,6 +1219,8 @@ class Thumb1sI pattern>
: InstThumb {
+ bits<0> s;
+ bits<0> p;
let OutOperandList = !con(oops, (outs s_cc_out:$s));
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${s}${p}", asm);
@@ -1243,6 +1245,7 @@ class Thumb1pI pattern>
: InstThumb {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1341,7 +1344,8 @@ class T1Misc opcode> : Encoding16 {
class Thumb2I pattern>
- : InstARM {
+: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1360,6 +1364,7 @@ class Thumb2sI pattern>
: InstARM {
+ bits<0> p;
bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
let Inst{20} = s;
@@ -2220,6 +2225,7 @@ class NeonI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
@@ -2233,6 +2239,7 @@ class NeonXI pattern>
: InstARM {
+ bits<0> p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", "\t", asm);
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td
b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 9dffd945d5baa..e24413465799f 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -409,6 +409,7 @@ class MVE_p {
+ bits<0> vp;
let Inst{31-29} = 0b111;
let Inst{27-26} = 0b11;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td
b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 0c5ea3e0fa8d5..bc1b34c691e39 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -483,6 +483,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
// A6.2.3 & A8.6.25
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b000;
@@ -491,6 +492,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
isIndirectBranch = 1 in {
def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
Requires<[IsThumb, Has8MSecExt]>,
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
+bits<0> p;
bits<4> Rm;
let Inst{6-3} = Rm;
let Inst{2-0} = 0b100;
@@ -523,6 +525,7 @@ let isCall = 1,
"bl${p}\t$func",
[(ARMcall tglobaladdr:$func)]>,
Requires<[IsThumb]>, Sched<[WriteBrL]> {
+bits<0> p;
bits<24> func;
let Inst{26} = func{23};
[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ee67c361e4f40b314cd8e2ef4b262f5059c2c40d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 30 +-
llvm/lib/Target/AArch64/CMakeLists.txt| 3 +-
.../Disassembler/AArch64Disassembler.cpp | 54 +-
.../MCTargetDesc/AArch64MCTargetDesc.h| 6 --
llvm/lib/Target/AArch64/SMEInstrFormats.td| 56 ++-
llvm/lib/Target/AArch64/SVEInstrFormats.td| 8 ++-
6 files changed, 106 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index feff59061aa16..e0e299cf4afdf 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1559,13 +1559,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
-let OperandNamespace = "AArch64" in {
- let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
-defm VectorIndex0 : VectorIndex;
-defm VectorIndex032b : VectorIndex;
- }
+let DecoderMethod = "DecodeZeroImm" in {
+ defm VectorIndex0 : VectorIndex;
+ defm VectorIndex032b : VectorIndex;
}
defm VectorIndex1 : VectorIndex;
@@ -1615,9 +1613,8 @@ def sme_elm_idx0_0 : Operand, TImmLeaf {
let ParserMatchClass = Imm0_0Operand;
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printMatrixIndex";
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def sme_elm_idx0_1 : Operand, TImmLeaf;
def uimm0s2range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<2, 1>";
let ParserMatchClass = UImm0s2RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm0s4range : Operand, ImmLeaf {
+ let DecoderMethod = "DecodeZeroImm";
let PrintMethod = "printImmRangeScale<4, 3>";
let ParserMatchClass = UImm0s4RangeOperand;
- let OperandNamespace = "AArch64";
- let OperandType = "OPERAND_IMPLICIT_IMM_0";
}
def uimm1s2range : Operand, ImmLeaf {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
}
@@ -8265,15 +8265,19 @@ multiclass UMov {
// streaming mode.
let Predicates = [HasNEONandIsStreamingSafe] in {
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b1;
}
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00010;
}
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b00100;
}
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
+ bits<0> idx;
let Inst{20-16} = 0b01000;
}
def : SIMDMovAlias<"mov", ".s",
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 79b56ea9cf850..803943fd57c4d 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 8c1e9f61693fb..647a6a3d76ef8 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned
RegMask,
return Success;
}
+static DecodeStatus DecodeMPRRegisterClass(MCIns
[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 01a8d9d7026b94f1cf060a8f12ad27df6e70ee2b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
These instructions can now be fully decoded automatically.
---
llvm/lib/Target/Hexagon/CMakeLists.txt| 3 +-
.../Disassembler/HexagonDisassembler.cpp | 65 ++---
.../Target/Hexagon/HexagonDepInstrFormats.td | 129 --
llvm/lib/Target/Hexagon/HexagonOperands.td| 10 +-
4 files changed, 49 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt
b/llvm/lib/Target/Hexagon/CMakeLists.txt
index b615536af03be..d758260a8ab5d 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de10092cbe3c8..0639878c1256f 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -173,6 +173,19 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned
tmp,
const MCDisassembler *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const MCDisassembler *Decoder);
+
+static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
+ MCContext &Ctx = Decoder->getContext();
+ MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
+ return DecodeStatus::Success;
+}
+
+static DecodeStatus sgp10ConstDecoder(MCInst &MI,
+ const MCDisassembler *Decoder) {
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ return DecodeStatus::Success;
+}
+
#include "HexagonDepDecoders.inc"
#include "HexagonGenDisassemblerTables.inc"
@@ -349,21 +362,6 @@ void HexagonDisassembler::remapInstruction(MCInst &Instr)
const {
}
}
-static void adjustDuplex(MCInst &MI, MCContext &Context) {
- switch (MI.getOpcode()) {
- case Hexagon::SA1_setin1:
-MI.insert(MI.begin() + 1,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- case Hexagon::SA1_dec:
-MI.insert(MI.begin() + 2,
- MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
-break;
- default:
-break;
- }
-}
-
DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
ArrayRef Bytes,
uint64_t Address,
@@ -468,12 +466,10 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MILow, getContext());
Result = decodeInstruction(
DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
-adjustDuplex(*MIHigh, getContext());
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
@@ -499,41 +495,6 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
}
- switch (MI.getOpcode()) {
- case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_f_jumpnv_t:
- case Hexagon::J4_cmpeqn1_fp0_jump_nt:
- case Hexagon::J4_cmpeqn1_fp0_jump_t:
- case Hexagon::J4_cmpeqn1_fp1_jump_nt:
- case Hexagon::J4_cmpeqn1_fp1_jump_t:
- case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
- case Hexagon::J4_cmpeqn1_t_jumpnv_t:
- case Hexagon::J4_cmpeqn1_tp0_jump_nt:
- case Hexagon::J4_cmpeqn1_tp0_jump_t:
- case Hexagon::J4_cmpeqn1_tp1_jump_nt:
- case Hexagon::J4_cmpeqn1_tp1_jump_t:
- case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_f_jumpnv_t:
- case Hexagon::J4_cmpgtn1_fp0_jump_nt:
- case Hexagon::J4_cmpgtn1_fp0_jump_t:
- case Hexagon::J4_cmpgtn1_fp1_jump_nt:
- case Hexagon::J4_cmpgtn1_fp1_jump_t:
- case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
- case Hexagon::J4_cmpgtn1_t_jumpnv_t:
- case Hexagon::J4_cmpgtn1_tp0_jump_nt:
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 1346d77cc53c6a4152eff9a885244daa360254f7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 6 ++
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..d874697185fac 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
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[llvm-branch-commits] [llvm] [RISCV] Remove post-decoding instruction adjustments (PR #156360)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d01399ac76d639e7474a8ae382395d1985e64ff7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
---
llvm/lib/Target/RISCV/CMakeLists.txt | 3 +--
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 ++-
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 8 --
llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td | 4 +++
5 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt
b/llvm/lib/Target/RISCV/CMakeLists.txt
index 720361dc3da5b..531238ae85029 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc
-gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
- --specialize-decoders-per-bitwidth
- -ignore-non-decodable-operands)
+ --specialize-decoders-per-bitwidth)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index b1b7ea5246fda..89df9d82f8780 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -46,8 +46,6 @@ class RISCVDisassembler : public MCDisassembler {
raw_ostream &CStream) const override;
private:
- void addSPOperands(MCInst &MI) const;
-
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
ArrayRef Bytes, uint64_t Address,
raw_ostream &CStream) const;
@@ -196,6 +194,12 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X2));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -600,15 +604,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst,
uint32_t Insn,
#include "RISCVGenDisassemblerTables.inc"
-// Add implied SP operand for C.*SP compressed instructions. The SP operand
-// isn't explicitly encoded in the instruction.
-void RISCVDisassembler::addSPOperands(MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.getNumOperands(); i++)
-if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
- MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
-}
-
namespace {
struct DecoderListEntry {
@@ -774,12 +769,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst
&MI, uint64_t &Size,
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
-if (Result == MCDisassembler::Fail)
- continue;
-
-addSPOperands(MI);
-
-return Result;
+if (Result != MCDisassembler::Fail)
+ return Result;
}
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 209c3fae63f45..4c7cd05723ac8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -54,7 +54,6 @@ class RVInst16CSS funct3, bits<2> opcode, dag outs,
dag ins,
: RVInst16 {
bits<10> imm;
bits<5> rs2;
- bits<5> rs1;
let Inst{15-13} = funct3;
let Inst{12-7} = imm{5-0};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index bfc766dfc27e5..9fc73662d9704 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -230,13 +230,17 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CStackLoad funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CI;
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<0> rs1;
+}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStackStore funct3, string OpcodeStr,
DAGOperand cls, DAGOperand opnd>
: RVInst16CSS;
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bit
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 1346d77cc53c6a4152eff9a885244daa360254f7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z register
The generated disassembler can now correctly decode these instructions.
---
llvm/lib/Target/AVR/AVRInstrFormats.td | 1 +
llvm/lib/Target/AVR/AVRInstrInfo.td | 4 +++-
llvm/lib/Target/AVR/CMakeLists.txt | 3 +--
.../Target/AVR/Disassembler/AVRDisassembler.cpp | 6 ++
.../Target/AVR/MCTargetDesc/AVRInstPrinter.cpp | 17 -
5 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td
b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b56370cc..eb4daf74545b0 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@ class FRdRr opcode, bits<2> f, dag outs, dag ins,
string asmstr,
//===--===//
class FZRd t, dag outs, dag ins, string asmstr, list pattern>
: AVRInst16 {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e1383acef2..70efda46093c4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt
b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e048778..a31c545f48ba3 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7f88e2a..d874697185fac 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst,
unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 481219164a0f9..5adffeed04bda 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@ const char
*AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
-// Special case for the Z register, which sometimes doesn't have an operand
-// in the MCInst.
-O << "Z";
-return;
- }
-
- if (OpNo >= MI->size()) {
-// Not all operands are correctly disassembled at the moment. This means
-// that some machine instructions won't have all the necessary operands
-// set.
-// To avoid asserting, print instead until the necessary support
-// has been implemented.
-O << "";
-return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
___
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[llvm-branch-commits] [llvm] [AArch64] Correctly disassemble TSB instruction (PR #156362)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From d80acf2607cbe3bdc8beedbad108ddba1f174541 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.
This instruction can now be disassembled correctly.
---
llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 3 +--
.../lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 7 ---
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1b0e90b0e0dc3..65b752ed40c90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex {
let Key = ["Name"];
}
-def : TSB<"csync", 0>;
+def : TSB<"csync", 2>;
//===--===//
// PRFM (prefetch) instruction options.
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 833ce48ea1d7a..79b56ea9cf850 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer
-asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands
- -ignore-fully-defined-operands)
+ -ignore-non-decodable-operands)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 54b58e948daf2..2552ee3009338 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI,
uint64_t Address,
return;
}
- // Instruction TSB is specified as a one operand instruction, but 'csync' is
- // not encoded, so for printing it is treated as a special case here:
- if (Opcode == AArch64::TSB) {
-O << "\ttsb\tcsync";
-return;
- }
-
if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
printInstruction(MI, Address, STI, O);
___
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[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)
@@ -38,11 +38,7 @@ class Enc_041d7b : OpcodeHexagon {
let Inst{7-1} = Ii{8-2};
bits <4> Rs16;
let Inst{19-16} = Rs16{3-0};
- bits <5> n1;
- let Inst{28-28} = n1{4-4};
- let Inst{24-23} = n1{3-2};
- let Inst{13-13} = n1{1-1};
- let Inst{8-8} = n1{0-0};
s-barannikov wrote:
These bits are all overwritten in the derived record. Same for all other
encodings.
https://github.com/llvm/llvm-project/pull/156359
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[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/156361 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/s-barannikov ready_for_review https://github.com/llvm/llvm-project/pull/156361 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64] Correctly disassemble TSB instruction (PR #156362)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From d80acf2607cbe3bdc8beedbad108ddba1f174541 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.
This instruction can now be disassembled correctly.
---
llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 3 +--
.../lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 7 ---
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1b0e90b0e0dc3..65b752ed40c90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex {
let Key = ["Name"];
}
-def : TSB<"csync", 0>;
+def : TSB<"csync", 2>;
//===--===//
// PRFM (prefetch) instruction options.
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 833ce48ea1d7a..79b56ea9cf850 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer
-asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands
- -ignore-fully-defined-operands)
+ -ignore-non-decodable-operands)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 54b58e948daf2..2552ee3009338 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI,
uint64_t Address,
return;
}
- // Instruction TSB is specified as a one operand instruction, but 'csync' is
- // not encoded, so for printing it is treated as a special case here:
- if (Opcode == AArch64::TSB) {
-O << "\ttsb\tcsync";
-return;
- }
-
if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
printInstruction(MI, Address, STI, O);
___
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[llvm-branch-commits] [lldb] release/21.x: [lldb][DWARFASTParserClang] Don't complete conflicting Objective-C++ types (#156681) (PR #156764)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156764
Backport a862225813c251c28b085603b7d32d4b111dbc57
Requested by: @Michael137
>From 4afd084013a57eb6ae27f46458d9e4115599a6a9 Mon Sep 17 00:00:00 2001
From: Michael Buch
Date: Wed, 3 Sep 2025 20:04:53 +0100
Subject: [PATCH] [lldb][DWARFASTParserClang] Don't complete conflicting
Objective-C++ types (#156681)
This upstreams https://github.com/swiftlang/llvm-project/pull/10313.
If we detect a situation where a forward declaration is C++ and the
definition DIE is Objective-C, then just don't try to complete the type
(it would crash otherwise). In the long term we might want to add
support for completing such types.
We've seen real world crashes when debugging WebKit and wxWidgets
because of this. Both projects forward declare ObjC++ decls in the way
shown in the test.
rdar://145959981
(cherry picked from commit a862225813c251c28b085603b7d32d4b111dbc57)
---
.../SymbolFile/DWARF/DWARFASTParserClang.cpp | 12
.../DWARF/objcxx-forward-decls.test | 70 +++
2 files changed, 82 insertions(+)
create mode 100644 lldb/test/Shell/SymbolFile/DWARF/objcxx-forward-decls.test
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
index c76d67b47b336..8916c58beec0f 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
@@ -2201,6 +2201,18 @@ bool DWARFASTParserClang::CompleteRecordType(const
DWARFDIE &die,
for (DelayedAddObjCClassProperty &property : delayed_properties)
property.Finalize();
}
+ } else if (Language::LanguageIsObjC(
+ static_cast(die.GetAttributeValueAsUnsigned(
+ DW_AT_APPLE_runtime_class, eLanguageTypeUnknown {
+/// The forward declaration was C++ but the definition is Objective-C.
+/// We currently don't handle such situations. In such cases, keep the
+/// forward declaration without a definition to avoid violating Clang AST
+/// invariants.
+LLDB_LOG(GetLog(LLDBLog::Expressions),
+ "WARNING: Type completion aborted because forward declaration for
"
+ "'{0}' is C++ while definition is Objective-C.",
+ llvm::StringRef(die.GetName()));
+return {};
}
if (!bases.empty()) {
diff --git a/lldb/test/Shell/SymbolFile/DWARF/objcxx-forward-decls.test
b/lldb/test/Shell/SymbolFile/DWARF/objcxx-forward-decls.test
new file mode 100644
index 0..30109c2943c9b
--- /dev/null
+++ b/lldb/test/Shell/SymbolFile/DWARF/objcxx-forward-decls.test
@@ -0,0 +1,70 @@
+# REQUIRES: system-darwin
+
+# In this test we have two CUs with conflicting forward declaration
+# depending on the CU language (one is C++ and the other is Objective-C++).
+# We are then stopped in the C++ CU and try to print the type, at which
+# point LLDB will try to make it into an Clang AST node. If LLDB were to
+# interpret the type as C++ instead of Objective-C, we'd violate Clang
+# invariants and crash.
+#
+# RUN: split-file %s %t
+# RUN: %clangxx_host -c -g -x objective-c++ %t/request.m -o %t/request_objc.o
+# RUN: %clangxx_host -c -g %t/main.cpp -o %t/main.o
+# RUN: %clangxx_host %t/main.o %t/request_objc.o -framework Foundation -o
%t/a.out
+#
+# RUN: %lldb %t/a.out \
+# RUN:-o "breakpoint set -p return -X main" \
+# RUN:-o run \
+# RUN:-o "frame variable r" \
+# RUN:-o exit | FileCheck %s
+#
+# RUN: dsymutil %t/a.out
+#
+# RUN: %lldb %t/a.out \
+# RUN:-o "breakpoint set -p return -X main" \
+# RUN:-o run \
+# RUN:-o "frame variable r" \
+# RUN:-o exit | FileCheck %s --check-prefix=CHECK-DSYM
+
+# CHECK: (lldb) frame variable r
+# CHECK-NEXT: (Request) ::r = (m_request = "Hello, World!")
+
+# CHECK-DSYM: (lldb) frame variable r
+# CHECK-DSYM-NEXT: (Request) ::r = (m_request = "Hello, World!")
+
+#--- lib.h
+#ifndef LIB_H_IN
+#define LIB_H_IN
+
+#ifdef __OBJC__
+@class NSString;
+#else
+class NSString;
+#endif
+
+struct Request {
+ NSString * m_request = nullptr;
+};
+
+#endif // _H_IN
+
+#--- main.cpp
+#include "lib.h"
+
+void process(Request *);
+
+Request r;
+
+int main() {
+process(&r);
+return 0;
+}
+
+#--- request.m
+#import
+
+#include "lib.h"
+
+void process(Request * r) {
+ r->m_request = @"Hello, World!";
+}
___
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[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
https://github.com/benshi001 edited https://github.com/llvm/llvm-project/pull/156361 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Change FLAT classes to use RegisterOperand parameters (PR #156581)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From a09ada3d217bcf5728f32d7a16c334fb0330e617 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
This will make it easier to precisely express operand constraints
without having the implicit getLdStRegisterOperand at the bottom.
Also prunes out using AV classes in some instructions where AGPRs
are not relevant.
---
llvm/lib/Target/AMDGPU/FLATInstructions.td | 421 ++---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 2 +-
2 files changed, 208 insertions(+), 215 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td
b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index dcb4f506dfbd2..69aef421bba45 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -216,11 +216,10 @@ class GlobalSaddrTable {
// same encoding value as exec_hi, so it isn't possible to use that if
// saddr is 32-bit (which isn't handled here yet).
class FLAT_Load_Pseudo<
-string opName, RegisterClass regClass, bit HasTiedOutput = 0,
+string opName, RegisterOperand vdata_op, bit HasTiedOutput = 0,
bit HasSaddr = 0, bit EnableSaddr = 0>
: FLAT_Pseudo {
- defvar vdata_op = getLdStRegisterOperand.ret;
let OutOperandList = (outs vdata_op:$vdst);
let InOperandList = !con(
!if(EnableSaddr,
@@ -243,7 +242,7 @@ class FLAT_Load_Pseudo<
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
}
-multiclass FLAT_Flat_Load_Pseudo {
+multiclass FLAT_Flat_Load_Pseudo {
def "" : FLAT_Load_Pseudo,
GlobalSaddrTable<0, opName>;
let OtherPredicates = [HasFlatGVSMode] in
@@ -252,19 +251,19 @@ multiclass FLAT_Flat_Load_Pseudo {
- defm "" : FLAT_Flat_Load_Pseudo;
+ defm "" : FLAT_Flat_Load_Pseudo;
let True16Predicate = UseRealTrue16Insts in
-defm _t16 : FLAT_Flat_Load_Pseudo,
True16D16Table;
+defm _t16 : FLAT_Flat_Load_Pseudo,
True16D16Table;
}
-class FLAT_Store_Pseudo : FLAT_Pseudo<
opName,
(outs),
!con(
!if(EnableSaddr,
- (ins VGPR_32:$vaddr, getLdStRegisterOperand.ret:$vdata,
SReg_64_XEXEC_XNULL:$saddr),
- (ins VReg_64:$vaddr, getLdStRegisterOperand.ret:$vdata)),
+ (ins VGPR_32:$vaddr, vdataClass:$vdata, SReg_64_XEXEC_XNULL:$saddr),
+ (ins VReg_64:$vaddr, vdataClass:$vdata)),
(ins flat_offset:$offset, CPol_0:$cpol)),
" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"),
"")#"$offset$cpol"> {
let mayLoad = 0;
@@ -274,7 +273,7 @@ class FLAT_Store_Pseudo {
+multiclass FLAT_Flat_Store_Pseudo {
def "" : FLAT_Store_Pseudo,
GlobalSaddrTable<0, opName>;
let OtherPredicates = [HasFlatGVSMode] in
@@ -283,20 +282,21 @@ multiclass FLAT_Flat_Store_Pseudo {
}
multiclass FLAT_Flat_Store_Pseudo_t16 {
- defm "" : FLAT_Flat_Store_Pseudo;
+ defm "" : FLAT_Flat_Store_Pseudo;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasFlatGVSMode, HasTrue16BitInsts] in {
-def _t16 : FLAT_Store_Pseudo,
+def _t16 : FLAT_Store_Pseudo,
GlobalSaddrTable<0, Name16>,
True16D16Table;
- def _SADDR_t16 : FLAT_Store_Pseudo,
+ def _SADDR_t16 : FLAT_Store_Pseudo,
GlobalSaddrTable<1, Name16>,
True16D16Table;
}
}
-multiclass FLAT_Global_Load_Pseudo {
+multiclass FLAT_Global_Load_Pseudo {
let is_flat_global = 1 in {
def "" : FLAT_Load_Pseudo,
GlobalSaddrTable<0, opName>;
@@ -306,21 +306,21 @@ multiclass FLAT_Global_Load_Pseudo {
- defm "" : FLAT_Global_Load_Pseudo;
+ defm "" : FLAT_Global_Load_Pseudo;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts],
SubtargetPredicate = HasFlatGlobalInsts, is_flat_global = 1 in {
-def _t16 : FLAT_Load_Pseudo,
+def _t16 : FLAT_Load_Pseudo,
GlobalSaddrTable<0, Name16>,
True16D16Table;
-def _SADDR_t16 : FLAT_Load_Pseudo,
+def _SADDR_t16 : FLAT_Load_Pseudo,
GlobalSaddrTable<1, Name16>,
True16D16Table;
}
}
-class FLAT_Global_Load_AddTid_Pseudo : FLAT_Pseudo<
opName,
(outs regClass:$vdst),
@@ -338,7 +338,7 @@ class FLAT_Global_Load_AddTid_Pseudo {
def "" : FLAT_Global_Load_AddTid_Pseudo,
GlobalSaddrTable<0, opName>;
@@ -346,7 +346,7 @@ multiclass FLAT_Global_Load_AddTid_Pseudo;
}
-multiclass FLAT_Global_Store_Pseudo {
+multiclass FLAT_Global_Store_Pseudo {
let is_flat_global = 1 in {
def "" : FLAT_Store_Pseudo,
GlobalSaddrTable<0, opName>;
@@ -356,15 +356,15 @@ multiclass FLAT_Global_Store_Pseudo {
}
multiclass FLAT_Global_Store_Pseudo_t16 {
- defm "" : FLAT_Global_Store_Pseudo;
+ defm "" : FLAT_Global_Store_Pseudo;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts],
SubtargetPredicate = HasFlatGlobalInsts, is_flat_global = 1 in {
-def _t16 : FLAT_Store_Pseudo,
+def _t16 : FLAT_Store_Ps
[llvm-branch-commits] [llvm] AMDGPU: Define agpr versions of ds permute instructions (PR #156695)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 25ff1b6a8940230deaa680241f9ce67d7896ab5d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctly model these without AV_* operands. This is another
step towards removing the special casing in
TargetInstrInfo::getRegClass. Also add some tests for this.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 21 +-
llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll | 334 +
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s | 28 +-
3 files changed, 365 insertions(+), 18 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 23dd660c3e57e..bec920380e081 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -520,6 +520,19 @@ class DS_1A1D_PERMUTE {
+ assert OperandIsVGPR.ret,
+ "DS with 2 data operands should be declared with VGPRs";
+ def "" : DS_1A1D_PERMUTE;
+
+ let SubtargetPredicate = isGFX90APlus in {
+def _agpr : DS_1A1D_PERMUTE.ret>;
+ }
+}
+
+
class DSAtomicRetPat : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset),
vt:$value),
(inst $ptr, getVregSrcForVT.ret:$value, Offset:$offset, (i1 gds))> {
@@ -837,10 +850,10 @@ def DS_NOP : DS_VOID<"ds_nop">;
let SubtargetPredicate = isGFX8Plus in {
let Uses = [EXEC] in {
-def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
- int_amdgcn_ds_permute>;
-def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
- int_amdgcn_ds_bpermute>;
+defm DS_PERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_permute_b32",
+ int_amdgcn_ds_permute>;
+defm DS_BPERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_bpermute_b32",
+ int_amdgcn_ds_bpermute>;
}
} // let SubtargetPredicate = isGFX8Plus
diff --git a/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
new file mode 100644
index 0..5cd798d4f6db1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s
+
+; Try to stress ds.bpermute and ds.permute instructions with AGPR/AV
+; inputs. It's not permissible to mix AGPRs and VGPR data operands.
+
+define void @ds_bpermute_b32_a_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a1
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=a"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_v_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_v_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=v"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_a_v__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_v__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v1, v0
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a
[llvm-branch-commits] [llvm] AMDGPU: Fix definitions of DS ret atomics with AGPRs (PR #156655)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156655
>From 61b4ecaf9130602ed184ed505be6ed76d7e13f2e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 20:08:48 +0900
Subject: [PATCH] AMDGPU: Fix definitions of DS ret atomics with AGPRs
These are 2-data operations that need to use all-AGPR or all-VGPR
inputs. Stop defining them with AVLdSt data operands, and add _agpr
variants.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 249 +++--
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s| 448 +++
2 files changed, 352 insertions(+), 345 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 960f3282fb6f6..23dd660c3e57e 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -253,17 +253,22 @@ class DS_1A1D_RET
let IsAtomicRet = 1;
}
-multiclass DS_1A1D_RET_mc {
+multiclass DS_1A1D_RET_mc {
+ assert OperandIsVGPR.ret,
+ "DS with 2 data operands should be declared with VGPRs";
+
def "" : DS_1A1D_RET;
let has_m0_read = 0 in {
def _gfx9 : DS_1A1D_RET;
+def _agpr : DS_1A1D_RET.ret>;
}
}
-multiclass DS_1A1D_RET_mc_gfx9
{
+multiclass DS_1A1D_RET_mc_gfx9
{
let has_m0_read = 0 in {
def "" : DS_1A1D_RET;
+def _agpr : DS_1A1D_RET.ret>;
}
}
@@ -617,7 +622,7 @@ def DS_WRITE_ADDTID_B32 :
DS_0A1D_NORET<"ds_write_addtid_b32">;
let SubtargetPredicate = HasLdsAtomicAddF64 in {
defm DS_ADD_F64 : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", AVLdSt_64>;
- defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", AVLdSt_64>;
+ defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VGPROp_64>;
} // End SubtargetPredicate = HasLdsAtomicAddF64
let SubtargetPredicate = HasAtomicDsPkAdd16Insts in {
@@ -689,25 +694,25 @@ defm DS_WRXCHG_RTN_B32 :
DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VGPROp_64,
VGPROp_32>;
defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32",
VGPROp_64, VGPROp_32>;
-defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", AVLdSt_64>;
-defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", AVLdSt_64>;
-defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", AVLdSt_64>;
-defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", AVLdSt_64>;
-defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", AVLdSt_64>;
-defm DS_MIN_RTN_I64: DS_1A1D_RET_mc<"ds_min_rtn_i64", AVLdSt_64>;
-defm DS_MAX_RTN_I64: DS_1A1D_RET_mc<"ds_max_rtn_i64", AVLdSt_64>;
-defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", AVLdSt_64>;
-defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", AVLdSt_64>;
-defm DS_AND_RTN_B64: DS_1A1D_RET_mc<"ds_and_rtn_b64", AVLdSt_64>;
-defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", AVLdSt_64>;
-defm DS_XOR_RTN_B64: DS_1A1D_RET_mc<"ds_xor_rtn_b64", AVLdSt_64>;
+defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VGPROp_64>;
+defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VGPROp_64>;
+defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VGPROp_64>;
+defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VGPROp_64>;
+defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VGPROp_64>;
+defm DS_MIN_RTN_I64: DS_1A1D_RET_mc<"ds_min_rtn_i64", VGPROp_64>;
+defm DS_MAX_RTN_I64: DS_1A1D_RET_mc<"ds_max_rtn_i64", VGPROp_64>;
+defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VGPROp_64>;
+defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VGPROp_64>;
+defm DS_AND_RTN_B64: DS_1A1D_RET_mc<"ds_and_rtn_b64", VGPROp_64>;
+defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VGPROp_64>;
+defm DS_XOR_RTN_B64: DS_1A1D_RET_mc<"ds_xor_rtn_b64", VGPROp_64>;
defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VGPROp_64>;
defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VGPROp_64>;
defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VGPROp_64>;
-defm DS_MIN_RTN_F64: DS_1A1D_RET_mc<"ds_min_rtn_f64", AVLdSt_64>;
-defm DS_MAX_RTN_F64: DS_1A1D_RET_mc<"ds_max_rtn_f64", AVLdSt_64>;
+defm DS_MIN_RTN_F64: DS_1A1D_RET_mc<"ds_min_rtn_f64", VGPROp_64>;
+defm DS_MAX_RTN_F64: DS_1A1D_RET_mc<"ds_max_rtn_f64", VGPROp_64>;
-defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", AVLdSt_64>;
+defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VGPROp_64>;
defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64",
VGPROp_128, VGPROp_64>;
defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64",
VGPROp_128, VGPROp_64>;
@@ -805,7 +810,7 @@ def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
let SubtargetPredicate = isGFX7Plus in {
defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPROp_32>;
-defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64",
AVLdSt_64>;
+defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_c
[llvm-branch-commits] [llvm] AMDGPU: Remove the DS special case in getRegClass (PR #156696)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From 1b6877bd4a0ef4a30fcd0728b6e1864200969bc8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instructions should now have proper representation
with separate instructions for operands which must be paired.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 946917f675318..44d819258da67 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5960,7 +5960,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const
SIRegisterInfo &RI,
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
- (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG {
+ (TID.TSFlags & SIInstrFlags::MIMG))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
@@ -5996,23 +5996,18 @@ const TargetRegisterClass
*SIInstrInfo::getRegClass(const MCInstrDesc &TID,
return nullptr;
auto RegClass = TID.operands()[OpNum].RegClass;
bool IsAllocatable = false;
- if (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::FLAT)) {
+ if (TID.TSFlags & SIInstrFlags::FLAT) {
// vdst and vdata should be both VGPR or AGPR, same for the DS instructions
// with two data operands. Request register class constrained to VGPR only
// of both operands present as Machine Copy Propagation can not check this
// constraint and possibly other passes too.
//
-// The check is limited to FLAT and DS because atomics in non-flat encoding
-// have their vdst and vdata tied to be the same register.
-const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
- AMDGPU::OpName::vdst);
-const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
-(TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata);
-if (DataIdx != -1) {
- IsAllocatable = VDstIdx != -1 || AMDGPU::hasNamedOperand(
- TID.Opcode, AMDGPU::OpName::data1);
-}
+// The check is limited to FLAT because atomics in non-flat encoding have
+// their vdst and vdata tied to be the same register, and DS instructions
+// have separate instruction definitions with AGPR and VGPR operand lists.
+IsAllocatable =
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdata) &&
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdst);
} else if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO) {
// Special pseudos have no alignment requirement
return RI.getRegClass(RegClass);
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Remove the DS special case in getRegClass (PR #156696)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From 1b6877bd4a0ef4a30fcd0728b6e1864200969bc8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instructions should now have proper representation
with separate instructions for operands which must be paired.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 946917f675318..44d819258da67 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5960,7 +5960,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const
SIRegisterInfo &RI,
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
- (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG {
+ (TID.TSFlags & SIInstrFlags::MIMG))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
@@ -5996,23 +5996,18 @@ const TargetRegisterClass
*SIInstrInfo::getRegClass(const MCInstrDesc &TID,
return nullptr;
auto RegClass = TID.operands()[OpNum].RegClass;
bool IsAllocatable = false;
- if (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::FLAT)) {
+ if (TID.TSFlags & SIInstrFlags::FLAT) {
// vdst and vdata should be both VGPR or AGPR, same for the DS instructions
// with two data operands. Request register class constrained to VGPR only
// of both operands present as Machine Copy Propagation can not check this
// constraint and possibly other passes too.
//
-// The check is limited to FLAT and DS because atomics in non-flat encoding
-// have their vdst and vdata tied to be the same register.
-const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
- AMDGPU::OpName::vdst);
-const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
-(TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata);
-if (DataIdx != -1) {
- IsAllocatable = VDstIdx != -1 || AMDGPU::hasNamedOperand(
- TID.Opcode, AMDGPU::OpName::data1);
-}
+// The check is limited to FLAT because atomics in non-flat encoding have
+// their vdst and vdata tied to be the same register, and DS instructions
+// have separate instruction definitions with AGPR and VGPR operand lists.
+IsAllocatable =
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdata) &&
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdst);
} else if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO) {
// Special pseudos have no alignment requirement
return RI.getRegClass(RegClass);
___
llvm-branch-commits mailing list
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https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Define agpr versions of ds permute instructions (PR #156695)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 25ff1b6a8940230deaa680241f9ce67d7896ab5d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctly model these without AV_* operands. This is another
step towards removing the special casing in
TargetInstrInfo::getRegClass. Also add some tests for this.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 21 +-
llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll | 334 +
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s | 28 +-
3 files changed, 365 insertions(+), 18 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 23dd660c3e57e..bec920380e081 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -520,6 +520,19 @@ class DS_1A1D_PERMUTE {
+ assert OperandIsVGPR.ret,
+ "DS with 2 data operands should be declared with VGPRs";
+ def "" : DS_1A1D_PERMUTE;
+
+ let SubtargetPredicate = isGFX90APlus in {
+def _agpr : DS_1A1D_PERMUTE.ret>;
+ }
+}
+
+
class DSAtomicRetPat : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset),
vt:$value),
(inst $ptr, getVregSrcForVT.ret:$value, Offset:$offset, (i1 gds))> {
@@ -837,10 +850,10 @@ def DS_NOP : DS_VOID<"ds_nop">;
let SubtargetPredicate = isGFX8Plus in {
let Uses = [EXEC] in {
-def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
- int_amdgcn_ds_permute>;
-def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
- int_amdgcn_ds_bpermute>;
+defm DS_PERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_permute_b32",
+ int_amdgcn_ds_permute>;
+defm DS_BPERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_bpermute_b32",
+ int_amdgcn_ds_bpermute>;
}
} // let SubtargetPredicate = isGFX8Plus
diff --git a/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
new file mode 100644
index 0..5cd798d4f6db1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s
+
+; Try to stress ds.bpermute and ds.permute instructions with AGPR/AV
+; inputs. It's not permissible to mix AGPRs and VGPR data operands.
+
+define void @ds_bpermute_b32_a_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a1
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=a"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_v_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_v_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=v"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_a_v__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_v__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v1, v0
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a
[llvm-branch-commits] [clang] [llvm] [HLSL] Use static create methods to initialize individual resources (PR #156544)
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/156544
>From 02342c922d0feec12b980528eb4a75e8d6676ebe Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Tue, 2 Sep 2025 15:03:11 -0700
Subject: [PATCH 1/3] [HLSL] Use static create methods to initialize individual
resources
---
clang/lib/Sema/SemaHLSL.cpp | 128 +++--
.../test/AST/HLSL/ByteAddressBuffers-AST.hlsl | 2 +-
clang/test/AST/HLSL/vk_binding_attr.hlsl | 48 +++-
.../CodeGenHLSL/GlobalConstructorLib.hlsl | 6 +-
.../debug/rwbuffer_debug_info.hlsl| 5 +-
.../ByteAddressBuffers-constructors.hlsl | 66 ++---
.../resources/RWBuffer-constructor.hlsl | 76 +++---
.../StructuredBuffers-constructors.hlsl | 69 +++--
.../resources/resource-bindings.hlsl | 20 +-
clang/test/CodeGenHLSL/static-local-ctor.hlsl | 2 +-
out.ll| 251 ++
11 files changed, 508 insertions(+), 165 deletions(-)
create mode 100644 out.ll
diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp
index c12b35308e127..88334908073a0 100644
--- a/clang/lib/Sema/SemaHLSL.cpp
+++ b/clang/lib/Sema/SemaHLSL.cpp
@@ -1201,6 +1201,14 @@ struct PerVisibilityBindingChecker {
}
};
+static CXXMethodDecl *lookupMethod(CXXRecordDecl *Record, StringRef Name,
+ StorageClass SC = SC_None) {
+ for (auto *Method : Record->methods())
+if (Method->getStorageClass() == SC && Method->getName() == Name)
+ return Method;
+ return nullptr;
+}
+
} // end anonymous namespace
bool SemaHLSL::handleRootSignatureElements(
@@ -3689,26 +3697,6 @@ void SemaHLSL::ActOnVariableDeclarator(VarDecl *VD) {
deduceAddressSpace(VD);
}
-static bool initVarDeclWithCtor(Sema &S, VarDecl *VD,
-MutableArrayRef Args) {
- InitializedEntity Entity = InitializedEntity::InitializeVariable(VD);
- InitializationKind Kind = InitializationKind::CreateDirect(
- VD->getLocation(), SourceLocation(), SourceLocation());
-
- InitializationSequence InitSeq(S, Entity, Kind, Args);
- if (InitSeq.Failed())
-return false;
-
- ExprResult Init = InitSeq.Perform(S, Entity, Kind, Args);
- if (!Init.get())
-return false;
-
- VD->setInit(S.MaybeCreateExprWithCleanups(Init.get()));
- VD->setInitStyle(VarDecl::CallInit);
- S.CheckCompleteVariableDeclaration(VD);
- return true;
-}
-
void SemaHLSL::createResourceRecordCtorArgs(
const Type *ResourceTy, StringRef VarName, HLSLResourceBindingAttr *RBA,
HLSLVkBindingAttr *VkBinding, uint32_t ArrayIndex,
@@ -3759,11 +3747,101 @@ void SemaHLSL::createResourceRecordCtorArgs(
}
bool SemaHLSL::initGlobalResourceDecl(VarDecl *VD) {
- SmallVector Args;
- createResourceRecordCtorArgs(VD->getType().getTypePtr(), VD->getName(),
- VD->getAttr(),
- VD->getAttr(), 0, Args);
- return initVarDeclWithCtor(SemaRef, VD, Args);
+ assert(VD->getType()->isHLSLResourceRecord() &&
+ "expected resource record type");
+
+ ASTContext &AST = SemaRef.getASTContext();
+ uint64_t UIntTySize = AST.getTypeSize(AST.UnsignedIntTy);
+ uint64_t IntTySize = AST.getTypeSize(AST.IntTy);
+
+ // Gather resource binding information from attributes.
+ HLSLResourceBindingAttr *RBA = VD->getAttr();
+ HLSLVkBindingAttr *VkBinding = VD->getAttr();
+ std::optional RegisterSlot;
+ uint32_t SpaceNo = 0;
+ if (VkBinding) {
+RegisterSlot = VkBinding->getBinding();
+SpaceNo = VkBinding->getSet();
+ } else if (RBA) {
+if (RBA->hasRegisterSlot())
+ RegisterSlot = RBA->getSlotNumber();
+SpaceNo = RBA->getSpaceNumber();
+ }
+
+ // Find correct initialization method and create its argumentss.
+ QualType ResourceTy = VD->getType();
+ CXXRecordDecl *ResourceDecl = ResourceTy->getAsCXXRecordDecl();
+ CXXMethodDecl *CreateMethod = nullptr;
+ llvm::SmallVector Args;
+
+ if (RegisterSlot.has_value()) {
+// The resource has explicit binding.
+CreateMethod = lookupMethod(ResourceDecl, "__createFromBinding",
SC_Static);
+IntegerLiteral *RegSlot = IntegerLiteral::Create(
+AST, llvm::APInt(UIntTySize, RegisterSlot.value()), AST.UnsignedIntTy,
+SourceLocation());
+Args.push_back(RegSlot);
+ } else {
+// The resource has implicit binding.
+CreateMethod =
+lookupMethod(ResourceDecl, "__createFromImplicitBinding", SC_Static);
+uint32_t OrderID = (RBA && RBA->hasImplicitBindingOrderID())
+ ? RBA->getImplicitBindingOrderID()
+ : getNextImplicitBindingOrderID();
+IntegerLiteral *OrderId =
+IntegerLiteral::Create(AST, llvm::APInt(UIntTySize, OrderID),
+ AST.UnsignedIntTy, SourceLocation());
+Args.push_back(OrderId);
+ }
+
+ if (!CreateMethod)
+return false;
+
+ IntegerLiteral *Space =
+ IntegerLiteral::Create(AST, ll
[llvm-branch-commits] [clang] [llvm] [HLSL] Use static create methods to initialize individual resources (PR #156544)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Helena Kotas (hekota)
Changes
Use static methods `__createFromBinding` and `__createFromImplicitBinding` to
initialize individual resources in Sema HLSL. Resources in arrays will be
handles in a separate change.
Depends on #155866
Part 2 of #154221
---
Patch is 44.16 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/156544.diff
10 Files Affected:
- (modified) clang/lib/Sema/SemaHLSL.cpp (+103-25)
- (modified) clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl (+1-1)
- (modified) clang/test/AST/HLSL/vk_binding_attr.hlsl (+37-11)
- (modified) clang/test/CodeGenHLSL/GlobalConstructorLib.hlsl (+5-2)
- (modified) clang/test/CodeGenHLSL/debug/rwbuffer_debug_info.hlsl (+2-3)
- (modified)
clang/test/CodeGenHLSL/resources/ByteAddressBuffers-constructors.hlsl (+27-35)
- (modified) clang/test/CodeGenHLSL/resources/RWBuffer-constructor.hlsl
(+31-39)
- (modified)
clang/test/CodeGenHLSL/resources/StructuredBuffers-constructors.hlsl (+31-40)
- (modified) clang/test/CodeGenHLSL/resources/resource-bindings.hlsl (+4-16)
- (modified) clang/test/CodeGenHLSL/static-local-ctor.hlsl (+1-1)
``diff
diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp
index 722e804632a61..63ca46583a59b 100644
--- a/clang/lib/Sema/SemaHLSL.cpp
+++ b/clang/lib/Sema/SemaHLSL.cpp
@@ -1200,6 +1200,14 @@ struct PerVisibilityBindingChecker {
}
};
+static CXXMethodDecl *lookupMethod(CXXRecordDecl *Record, StringRef Name,
+ StorageClass SC = SC_None) {
+ for (auto *Method : Record->methods())
+if (Method->getStorageClass() == SC && Method->getName() == Name)
+ return Method;
+ return nullptr;
+}
+
} // end anonymous namespace
bool SemaHLSL::handleRootSignatureElements(
@@ -3688,26 +3696,6 @@ void SemaHLSL::ActOnVariableDeclarator(VarDecl *VD) {
deduceAddressSpace(VD);
}
-static bool initVarDeclWithCtor(Sema &S, VarDecl *VD,
-MutableArrayRef Args) {
- InitializedEntity Entity = InitializedEntity::InitializeVariable(VD);
- InitializationKind Kind = InitializationKind::CreateDirect(
- VD->getLocation(), SourceLocation(), SourceLocation());
-
- InitializationSequence InitSeq(S, Entity, Kind, Args);
- if (InitSeq.Failed())
-return false;
-
- ExprResult Init = InitSeq.Perform(S, Entity, Kind, Args);
- if (!Init.get())
-return false;
-
- VD->setInit(S.MaybeCreateExprWithCleanups(Init.get()));
- VD->setInitStyle(VarDecl::CallInit);
- S.CheckCompleteVariableDeclaration(VD);
- return true;
-}
-
void SemaHLSL::createResourceRecordCtorArgs(
const Type *ResourceTy, StringRef VarName, HLSLResourceBindingAttr *RBA,
HLSLVkBindingAttr *VkBinding, uint32_t ArrayIndex,
@@ -3758,11 +3746,101 @@ void SemaHLSL::createResourceRecordCtorArgs(
}
bool SemaHLSL::initGlobalResourceDecl(VarDecl *VD) {
- SmallVector Args;
- createResourceRecordCtorArgs(VD->getType().getTypePtr(), VD->getName(),
- VD->getAttr(),
- VD->getAttr(), 0, Args);
- return initVarDeclWithCtor(SemaRef, VD, Args);
+ assert(VD->getType()->isHLSLResourceRecord() &&
+ "expected resource record type");
+
+ ASTContext &AST = SemaRef.getASTContext();
+ uint64_t UIntTySize = AST.getTypeSize(AST.UnsignedIntTy);
+ uint64_t IntTySize = AST.getTypeSize(AST.IntTy);
+
+ // Gather resource binding information from attributes.
+ HLSLResourceBindingAttr *RBA = VD->getAttr();
+ HLSLVkBindingAttr *VkBinding = VD->getAttr();
+ std::optional RegisterSlot;
+ uint32_t SpaceNo = 0;
+ if (VkBinding) {
+RegisterSlot = VkBinding->getBinding();
+SpaceNo = VkBinding->getSet();
+ } else if (RBA) {
+if (RBA->hasRegisterSlot())
+ RegisterSlot = RBA->getSlotNumber();
+SpaceNo = RBA->getSpaceNumber();
+ }
+
+ // Find correct initialization method and create its argumentss.
+ QualType ResourceTy = VD->getType();
+ CXXRecordDecl *ResourceDecl = ResourceTy->getAsCXXRecordDecl();
+ CXXMethodDecl *CreateMethod = nullptr;
+ llvm::SmallVector Args;
+
+ if (RegisterSlot.has_value()) {
+// The resource has explicit binding.
+CreateMethod = lookupMethod(ResourceDecl, "__createFromBinding",
SC_Static);
+IntegerLiteral *RegSlot = IntegerLiteral::Create(
+AST, llvm::APInt(UIntTySize, RegisterSlot.value()), AST.UnsignedIntTy,
+SourceLocation());
+Args.push_back(RegSlot);
+ } else {
+// The resource has implicit binding.
+CreateMethod =
+lookupMethod(ResourceDecl, "__createFromImplicitBinding", SC_Static);
+uint32_t OrderID = (RBA && RBA->hasImplicitBindingOrderID())
+ ? RBA->getImplicitBindingOrderID()
+ : getNextImplicitBindingOrderID();
+IntegerLiteral *OrderId =
+IntegerLiteral::Create(AST, llvm::APInt(UIntTySize, OrderID),
+ AST.U
[llvm-branch-commits] [clang] [llvm] [HLSL] Use static create methods to initialize individual resources (PR #156544)
llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Helena Kotas (hekota)
Changes
Use static methods `__createFromBinding` and `__createFromImplicitBinding` to
initialize individual resources in Sema HLSL. Resources in arrays will be
handles in a separate change.
Depends on #155866
Part 2 of #154221
---
Patch is 44.16 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/156544.diff
10 Files Affected:
- (modified) clang/lib/Sema/SemaHLSL.cpp (+103-25)
- (modified) clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl (+1-1)
- (modified) clang/test/AST/HLSL/vk_binding_attr.hlsl (+37-11)
- (modified) clang/test/CodeGenHLSL/GlobalConstructorLib.hlsl (+5-2)
- (modified) clang/test/CodeGenHLSL/debug/rwbuffer_debug_info.hlsl (+2-3)
- (modified)
clang/test/CodeGenHLSL/resources/ByteAddressBuffers-constructors.hlsl (+27-35)
- (modified) clang/test/CodeGenHLSL/resources/RWBuffer-constructor.hlsl
(+31-39)
- (modified)
clang/test/CodeGenHLSL/resources/StructuredBuffers-constructors.hlsl (+31-40)
- (modified) clang/test/CodeGenHLSL/resources/resource-bindings.hlsl (+4-16)
- (modified) clang/test/CodeGenHLSL/static-local-ctor.hlsl (+1-1)
``diff
diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp
index 722e804632a61..63ca46583a59b 100644
--- a/clang/lib/Sema/SemaHLSL.cpp
+++ b/clang/lib/Sema/SemaHLSL.cpp
@@ -1200,6 +1200,14 @@ struct PerVisibilityBindingChecker {
}
};
+static CXXMethodDecl *lookupMethod(CXXRecordDecl *Record, StringRef Name,
+ StorageClass SC = SC_None) {
+ for (auto *Method : Record->methods())
+if (Method->getStorageClass() == SC && Method->getName() == Name)
+ return Method;
+ return nullptr;
+}
+
} // end anonymous namespace
bool SemaHLSL::handleRootSignatureElements(
@@ -3688,26 +3696,6 @@ void SemaHLSL::ActOnVariableDeclarator(VarDecl *VD) {
deduceAddressSpace(VD);
}
-static bool initVarDeclWithCtor(Sema &S, VarDecl *VD,
-MutableArrayRef Args) {
- InitializedEntity Entity = InitializedEntity::InitializeVariable(VD);
- InitializationKind Kind = InitializationKind::CreateDirect(
- VD->getLocation(), SourceLocation(), SourceLocation());
-
- InitializationSequence InitSeq(S, Entity, Kind, Args);
- if (InitSeq.Failed())
-return false;
-
- ExprResult Init = InitSeq.Perform(S, Entity, Kind, Args);
- if (!Init.get())
-return false;
-
- VD->setInit(S.MaybeCreateExprWithCleanups(Init.get()));
- VD->setInitStyle(VarDecl::CallInit);
- S.CheckCompleteVariableDeclaration(VD);
- return true;
-}
-
void SemaHLSL::createResourceRecordCtorArgs(
const Type *ResourceTy, StringRef VarName, HLSLResourceBindingAttr *RBA,
HLSLVkBindingAttr *VkBinding, uint32_t ArrayIndex,
@@ -3758,11 +3746,101 @@ void SemaHLSL::createResourceRecordCtorArgs(
}
bool SemaHLSL::initGlobalResourceDecl(VarDecl *VD) {
- SmallVector Args;
- createResourceRecordCtorArgs(VD->getType().getTypePtr(), VD->getName(),
- VD->getAttr(),
- VD->getAttr(), 0, Args);
- return initVarDeclWithCtor(SemaRef, VD, Args);
+ assert(VD->getType()->isHLSLResourceRecord() &&
+ "expected resource record type");
+
+ ASTContext &AST = SemaRef.getASTContext();
+ uint64_t UIntTySize = AST.getTypeSize(AST.UnsignedIntTy);
+ uint64_t IntTySize = AST.getTypeSize(AST.IntTy);
+
+ // Gather resource binding information from attributes.
+ HLSLResourceBindingAttr *RBA = VD->getAttr();
+ HLSLVkBindingAttr *VkBinding = VD->getAttr();
+ std::optional RegisterSlot;
+ uint32_t SpaceNo = 0;
+ if (VkBinding) {
+RegisterSlot = VkBinding->getBinding();
+SpaceNo = VkBinding->getSet();
+ } else if (RBA) {
+if (RBA->hasRegisterSlot())
+ RegisterSlot = RBA->getSlotNumber();
+SpaceNo = RBA->getSpaceNumber();
+ }
+
+ // Find correct initialization method and create its argumentss.
+ QualType ResourceTy = VD->getType();
+ CXXRecordDecl *ResourceDecl = ResourceTy->getAsCXXRecordDecl();
+ CXXMethodDecl *CreateMethod = nullptr;
+ llvm::SmallVector Args;
+
+ if (RegisterSlot.has_value()) {
+// The resource has explicit binding.
+CreateMethod = lookupMethod(ResourceDecl, "__createFromBinding",
SC_Static);
+IntegerLiteral *RegSlot = IntegerLiteral::Create(
+AST, llvm::APInt(UIntTySize, RegisterSlot.value()), AST.UnsignedIntTy,
+SourceLocation());
+Args.push_back(RegSlot);
+ } else {
+// The resource has implicit binding.
+CreateMethod =
+lookupMethod(ResourceDecl, "__createFromImplicitBinding", SC_Static);
+uint32_t OrderID = (RBA && RBA->hasImplicitBindingOrderID())
+ ? RBA->getImplicitBindingOrderID()
+ : getNextImplicitBindingOrderID();
+IntegerLiteral *OrderId =
+IntegerLiteral::Create(AST, llvm::APInt(UIntTySize, OrderID),
+ AST.Un
[llvm-branch-commits] Frontend: Adopt llvm::vfs::OutputBackend in CompilerInstance (PR #113364)
cachemeifyoucan wrote: Before landing the other change and rebase this, I created a branch to benchmark compile time: https://llvm-compile-time-tracker.com/compare.php?from=3b3fc701d8f83d4ca30ee1c818fb7687336ac178&to=e5febfb1d9d880b4f7af5dc32194f479ee2adcd6&stat=instructions%3Au Nothing stands out as regression. https://github.com/llvm/llvm-project/pull/113364 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/21.x: [rtsan] Add versioned pthread_cond interceptors (#155970) (PR #156196)
cjappl wrote: Sounds good, and totally understood. Thanks for helping us understand the general process and precedent @tru We have reached out to the original bug reporter and are going to ask if some proposed workarounds will service until LLVM 22. I will ping you on here when I have an idea of what we want to do. https://github.com/llvm/llvm-project/pull/156196 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Define agpr versions of ds permute instructions (PR #156695)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 22f1911b5b5f7a25d5d9cb74feb864341ef9a782 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctly model these without AV_* operands. This is another
step towards removing the special casing in
TargetInstrInfo::getRegClass. Also add some tests for this.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 21 +-
llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll | 334 +
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s | 28 +-
3 files changed, 365 insertions(+), 18 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 23dd660c3e57e..bec920380e081 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -520,6 +520,19 @@ class DS_1A1D_PERMUTE {
+ assert OperandIsVGPR.ret,
+ "DS with 2 data operands should be declared with VGPRs";
+ def "" : DS_1A1D_PERMUTE;
+
+ let SubtargetPredicate = isGFX90APlus in {
+def _agpr : DS_1A1D_PERMUTE.ret>;
+ }
+}
+
+
class DSAtomicRetPat : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset),
vt:$value),
(inst $ptr, getVregSrcForVT.ret:$value, Offset:$offset, (i1 gds))> {
@@ -837,10 +850,10 @@ def DS_NOP : DS_VOID<"ds_nop">;
let SubtargetPredicate = isGFX8Plus in {
let Uses = [EXEC] in {
-def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
- int_amdgcn_ds_permute>;
-def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
- int_amdgcn_ds_bpermute>;
+defm DS_PERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_permute_b32",
+ int_amdgcn_ds_permute>;
+defm DS_BPERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_bpermute_b32",
+ int_amdgcn_ds_bpermute>;
}
} // let SubtargetPredicate = isGFX8Plus
diff --git a/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
new file mode 100644
index 0..5cd798d4f6db1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s
+
+; Try to stress ds.bpermute and ds.permute instructions with AGPR/AV
+; inputs. It's not permissible to mix AGPRs and VGPR data operands.
+
+define void @ds_bpermute_b32_a_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a1
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=a"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_v_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_v_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=v"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_a_v__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_v__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v1, v0
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a
[llvm-branch-commits] [llvm] AMDGPU: Remove the DS special case in getRegClass (PR #156696)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From c7238cff2feb2f7e1e7d7b0f55ae5b9917a682a2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instructions should now have proper representation
with separate instructions for operands which must be paired.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 946917f675318..44d819258da67 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5960,7 +5960,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const
SIRegisterInfo &RI,
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
- (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG {
+ (TID.TSFlags & SIInstrFlags::MIMG))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
@@ -5996,23 +5996,18 @@ const TargetRegisterClass
*SIInstrInfo::getRegClass(const MCInstrDesc &TID,
return nullptr;
auto RegClass = TID.operands()[OpNum].RegClass;
bool IsAllocatable = false;
- if (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::FLAT)) {
+ if (TID.TSFlags & SIInstrFlags::FLAT) {
// vdst and vdata should be both VGPR or AGPR, same for the DS instructions
// with two data operands. Request register class constrained to VGPR only
// of both operands present as Machine Copy Propagation can not check this
// constraint and possibly other passes too.
//
-// The check is limited to FLAT and DS because atomics in non-flat encoding
-// have their vdst and vdata tied to be the same register.
-const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
- AMDGPU::OpName::vdst);
-const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
-(TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata);
-if (DataIdx != -1) {
- IsAllocatable = VDstIdx != -1 || AMDGPU::hasNamedOperand(
- TID.Opcode, AMDGPU::OpName::data1);
-}
+// The check is limited to FLAT because atomics in non-flat encoding have
+// their vdst and vdata tied to be the same register, and DS instructions
+// have separate instruction definitions with AGPR and VGPR operand lists.
+IsAllocatable =
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdata) &&
+AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdst);
} else if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO) {
// Special pseudos have no alignment requirement
return RI.getRegClass(RegClass);
___
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[llvm-branch-commits] [clang] release/21.x: [clang][docs] Fix implicit-int-conversion-on-negation typos (PR #156815)
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[llvm-branch-commits] [clang] [llvm] [HLSL] Use static create methods to initialize individual resources (PR #156544)
https://github.com/hekota ready_for_review https://github.com/llvm/llvm-project/pull/156544 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Define agpr versions of ds permute instructions (PR #156695)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 22f1911b5b5f7a25d5d9cb74feb864341ef9a782 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctly model these without AV_* operands. This is another
step towards removing the special casing in
TargetInstrInfo::getRegClass. Also add some tests for this.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 21 +-
llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll | 334 +
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s | 28 +-
3 files changed, 365 insertions(+), 18 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td
b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 23dd660c3e57e..bec920380e081 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -520,6 +520,19 @@ class DS_1A1D_PERMUTE {
+ assert OperandIsVGPR.ret,
+ "DS with 2 data operands should be declared with VGPRs";
+ def "" : DS_1A1D_PERMUTE;
+
+ let SubtargetPredicate = isGFX90APlus in {
+def _agpr : DS_1A1D_PERMUTE.ret>;
+ }
+}
+
+
class DSAtomicRetPat : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset),
vt:$value),
(inst $ptr, getVregSrcForVT.ret:$value, Offset:$offset, (i1 gds))> {
@@ -837,10 +850,10 @@ def DS_NOP : DS_VOID<"ds_nop">;
let SubtargetPredicate = isGFX8Plus in {
let Uses = [EXEC] in {
-def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
- int_amdgcn_ds_permute>;
-def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
- int_amdgcn_ds_bpermute>;
+defm DS_PERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_permute_b32",
+ int_amdgcn_ds_permute>;
+defm DS_BPERMUTE_B32 : DS_1A1D_PERMUTE_mc<"ds_bpermute_b32",
+ int_amdgcn_ds_bpermute>;
}
} // let SubtargetPredicate = isGFX8Plus
diff --git a/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
new file mode 100644
index 0..5cd798d4f6db1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s
+
+; Try to stress ds.bpermute and ds.permute instructions with AGPR/AV
+; inputs. It's not permissible to mix AGPRs and VGPR data operands.
+
+define void @ds_bpermute_b32_a_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a1
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=a"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_v_a__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_v_a__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v0, v1
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a0, v0
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; use a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:s_setpc_b64 s[30:31]
+ %op0 = call i32 asm "; def $0", "=v"()
+ %op1 = call i32 asm "; def $0", "=a"()
+ %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %op0, i32 %op1)
+ call void asm sideeffect "; use $0", "a"(i32 %bpermute)
+ ret void
+}
+
+define void @ds_bpermute_b32_a_v__use_a(ptr addrspace(3) %lds) #0 {
+; CHECK-LABEL: ds_bpermute_b32_a_v__use_a:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def a0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:;;#ASMSTART
+; CHECK-NEXT:; def v0
+; CHECK-NEXT:;;#ASMEND
+; CHECK-NEXT:v_accvgpr_read_b32 v1, a0
+; CHECK-NEXT:ds_bpermute_b32 v0, v1, v0
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:v_accvgpr_write_b32 a
[llvm-branch-commits] [libcxx] [lldb] release/21.x: [libc++] Ensure that we restore invariants in basic_filebuf::overflow (#147389) (PR #155712)
tru wrote: Are we happy / confident with this one now? @philnik777 @ldionne ? https://github.com/llvm/llvm-project/pull/155712 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (PR #156363)
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From f3b4f276760009154caa8140dc5b92651dfbe4db Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
These are the only instructions that encode two operands in the same
field. Instead of fixing them after they have been incorrectly decoded,
provide a custom decoder.
---
.../Disassembler/AArch64Disassembler.cpp | 29 ---
llvm/lib/Target/AArch64/SMEInstrFormats.td| 4 +++
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 23e46b84f6278..8c1e9f61693fb 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1563,6 +1563,25 @@ static DecodeStatus DecodePRFMRegInstruction(MCInst
&Inst, uint32_t insn,
return Success;
}
+static DecodeStatus
+DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
+ const MCDisassembler *Decoder) {
+ unsigned RvBits = fieldFromInstruction(Bits, 13, 2);
+ unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
+ unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
+
+ DecodeSimpleRegisterClass(
+ Inst, RvBits, Addr, Decoder);
+ Inst.addOperand(MCOperand::createImm(Imm4Bits));
+ DecodeSimpleRegisterClass(Inst, RnBits,
+ Addr, Decoder);
+ // Spill and fill instructions have a single immediate used for both
+ // the vector select offset and optional memory offset. Replicate
+ // the decoded immediate.
+ Inst.addOperand(MCOperand::createImm(Imm4Bits));
+ return Success;
+}
+
#include "AArch64GenDisassemblerTables.inc"
#include "AArch64GenInstrInfo.inc"
@@ -1621,16 +1640,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst
&MI, uint64_t &Size,
}
}
-if (MI.getOpcode() == AArch64::LDR_ZA ||
-MI.getOpcode() == AArch64::STR_ZA) {
- // Spill and fill instructions have a single immediate used for both
- // the vector select offset and optional memory offset. Replicate
- // the decoded immediate.
- const MCOperand &Imm4Op = MI.getOperand(2);
- assert(Imm4Op.isImm() && "Unexpected operand type!");
- MI.addOperand(Imm4Op);
-}
-
if (Result != MCDisassembler::Fail)
return Result;
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td
b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index b3005d5120229..40ec371fe79d3 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1108,6 +1108,10 @@ class sme_spill_fill_base
: I,
Sched<[]> {
+ // 'offset' operand is encoded in the same bits as 'imm4'. There is currently
+ // no way to tell TableGen about this.
+ let DecoderMethod = "DecodeSMESpillFillInstruction";
+ bits<0> ZAt;
bits<2> Rv;
bits<5> Rn;
bits<4> imm4;
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[llvm-branch-commits] [llvm] AMDGPU: Define agpr versions of ds permute instructions (PR #156695)
@@ -0,0 +1,334 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 arsenm wrote: No. This needs new support in AMDGPURewriteAGPRCopyMFMA (which will also need a renaming...) https://github.com/llvm/llvm-project/pull/156695 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (PR #156361)
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
benshi001 wrote:
Is `bits<0> z;` also needed by `LPMRdZ`/`LPMRdZPi`/`ELPMRdZ`/`ELPMRdZ` ?
https://github.com/llvm/llvm-project/pull/156361
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[llvm-branch-commits] [clang] [llvm] [HLSL] Use static create methods to initialize individual resources (PR #156544)
https://github.com/hekota converted_to_draft https://github.com/llvm/llvm-project/pull/156544 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] bbbe538 - Revert "[llvm-exegesis] Exclude loads/stores from aliasing instruction set (#…"
Author: Sjoerd Meijer
Date: 2025-09-03T20:00:34+01:00
New Revision: bbbe5384f1f231d7e206a37d43f30dc3b4975f96
URL:
https://github.com/llvm/llvm-project/commit/bbbe5384f1f231d7e206a37d43f30dc3b4975f96
DIFF:
https://github.com/llvm/llvm-project/commit/bbbe5384f1f231d7e206a37d43f30dc3b4975f96.diff
LOG: Revert "[llvm-exegesis] Exclude loads/stores from aliasing instruction set
(#…"
This reverts commit 899ee375e99c04ef2c4a67dc70b266c929ad43f4.
Added:
Modified:
llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
Removed:
llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
diff --git a/llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
b/llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
deleted file mode 100644
index 65e1203bb275d..0
--- a/llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
+++ /dev/null
@@ -1,8 +0,0 @@
-REQUIRES: aarch64-registered-target
-
-RUN: llvm-exegesis -mtriple=aarch64 -mcpu=neoverse-v2 -mode=latency
--dump-object-to-disk=%d --opcode-name=FMOVWSr
--benchmark-phase=assemble-measured-code 2>&1
-RUN: llvm-objdump -d %d > %t.s
-RUN: FileCheck %s < %t.s
-
-CHECK-NOT: ld{{[1-4]}}
-CHECK-NOT: st{{[1-4]}}
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index d2d9b31df5197..66c770d9ca86b 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -206,8 +206,6 @@ const Operand &Instruction::getPrimaryOperand(const
Variable &Var) const {
}
bool Instruction::hasMemoryOperands() const {
- if (Description.mayLoad() || Description.mayStore())
-return true;
return any_of(Operands, [](const Operand &Op) {
return Op.isReg() && Op.isExplicit() && Op.isMemory();
});
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[llvm-branch-commits] [llvm] release/21.x: [AArch64][BTI] Add BTI at EH entries. (#155308) (PR #156170)
davemgreen wrote: I managed to reproduce the original error and check that this fixes it. The extra EH_LABELS that needed to be removed were added in b933f0c376c9. https://github.com/llvm/llvm-project/pull/156170 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/21.x: [AArch64][BTI] Add BTI at EH entries. (#155308) (PR #156170)
https://github.com/davemgreen approved this pull request. https://github.com/llvm/llvm-project/pull/156170 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] ELF: Introduce R_AARCH64_FUNCINIT64 relocation type. (PR #133531)
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133531
>From 96e7da9a083888683c2ba00d97f886fd748ea10b Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Wed, 9 Apr 2025 20:30:57 -0700
Subject: [PATCH 1/2] Undo unnecessary change
Created using spr 1.3.6-beta.1
---
lld/ELF/SyntheticSections.cpp | 2 +-
lld/ELF/SyntheticSections.h | 2 +-
lld/ELF/Writer.cpp| 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp
index 8cab71c4c8d94..106749e90a82b 100644
--- a/lld/ELF/SyntheticSections.cpp
+++ b/lld/ELF/SyntheticSections.cpp
@@ -1696,7 +1696,7 @@ void
RelocationBaseSection::addAddendOnlyRelocIfNonPreemptible(
sym, 0, R_ABS, addendRelType);
}
-void RelocationBaseSection::mergeRels(Ctx &ctx) {
+void RelocationBaseSection::mergeRels() {
size_t newSize = relocs.size();
for (const auto &v : relocsVec)
newSize += v.size();
diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h
index 7a85906e8601d..2dd4b80eb85bf 100644
--- a/lld/ELF/SyntheticSections.h
+++ b/lld/ELF/SyntheticSections.h
@@ -553,7 +553,7 @@ class RelocationBaseSection : public SyntheticSection {
}
size_t getSize() const override { return relocs.size() * this->entsize; }
size_t getRelativeRelocCount() const { return numRelativeRelocs; }
- void mergeRels(Ctx &ctx);
+ void mergeRels();
void partitionRels();
void finalizeContents() override;
diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp
index 67004055f1af5..28b24f90716b8 100644
--- a/lld/ELF/Writer.cpp
+++ b/lld/ELF/Writer.cpp
@@ -2076,7 +2076,7 @@ template void
Writer::finalizeSections() {
// symbol table section (dynSymTab) must be the first one.
for (Partition &part : ctx.partitions) {
if (part.relaDyn) {
-part.relaDyn->mergeRels(ctx);
+part.relaDyn->mergeRels();
// Compute DT_RELACOUNT to be used by part.dynamic.
part.relaDyn->partitionRels();
finalizeSynthetic(ctx, part.relaDyn.get());
>From b33113cee03cd0b68b7e8c7e98bfa56dfbe02a46 Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Fri, 1 Aug 2025 14:03:45 -0700
Subject: [PATCH 2/2] Fix build
Created using spr 1.3.6-beta.1
---
lld/ELF/Relocations.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 2573cf5c9fbbf..e2f594f3d2bba 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1175,9 +1175,8 @@ void RelocationScanner::processAux(RelExpr expr, RelType
type, uint64_t offset,
<< " cannot be used against ifunc symbol '" << &sym << "'";
printLocation(diag, *sec, sym, offset);
} else {
- part.relaDyn->addReloc({ctx.target->iRelativeRel, sec, offset,
- DynamicReloc::AddendOnlyWithTargetVA, sym,
- addend, R_ABS});
+ part.relaDyn->addReloc({ctx.target->iRelativeRel, sec, offset, false,
+ sym, addend, R_ABS});
return;
}
}
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[llvm-branch-commits] [clang-tools-extra] [clangd] Show type hint for simple cases of dependent 'auto' (PR #156284)
https://github.com/HighCommander4 updated
https://github.com/llvm/llvm-project/pull/156284
>From 6791b7af77579242a7a0dd6a35929c0a648835d0 Mon Sep 17 00:00:00 2001
From: Nathan Ridge
Date: Mon, 1 Sep 2025 02:48:44 -0400
Subject: [PATCH] [clangd] Show type hint for simple cases of dependent 'auto'
Fixes https://github.com/clangd/clangd/issues/2275
---
clang-tools-extra/clangd/InlayHints.cpp | 31 ++-
.../clangd/unittests/InlayHintTests.cpp | 3 +-
2 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/clang-tools-extra/clangd/InlayHints.cpp
b/clang-tools-extra/clangd/InlayHints.cpp
index cd479e1b7c9bc..d56b93e5f36dc 100644
--- a/clang-tools-extra/clangd/InlayHints.cpp
+++ b/clang-tools-extra/clangd/InlayHints.cpp
@@ -633,13 +633,30 @@ class InlayHintVisitor : public
RecursiveASTVisitor {
}
if (auto *AT = D->getType()->getContainedAutoType()) {
- if (AT->isDeduced() && !D->getType()->isDependentType()) {
-// Our current approach is to place the hint on the variable
-// and accordingly print the full type
-// (e.g. for `const auto& x = 42`, print `const int&`).
-// Alternatively, we could place the hint on the `auto`
-// (and then just print the type deduced for the `auto`).
-addTypeHint(D->getLocation(), D->getType(), /*Prefix=*/": ");
+ if (AT->isDeduced()) {
+QualType T;
+// If the type is dependent, HeuristicResolver *may* be able to
+// resolve it to something that's useful to print. In other
+// cases, it can't, and the resultng type would just be printed
+// as "", in which case don't hint it at all.
+if (D->getType()->isDependentType()) {
+ if (D->hasInit()) {
+QualType Resolved = Resolver->resolveExprToType(D->getInit());
+if (Resolved != AST.DependentTy) {
+ T = Resolved;
+}
+ }
+} else {
+ T = D->getType();
+}
+if (!T.isNull()) {
+ // Our current approach is to place the hint on the variable
+ // and accordingly print the full type
+ // (e.g. for `const auto& x = 42`, print `const int&`).
+ // Alternatively, we could place the hint on the `auto`
+ // (and then just print the type deduced for the `auto`).
+ addTypeHint(D->getLocation(), T, /*Prefix=*/": ");
+}
}
}
diff --git a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
index 99e728c40063d..feb4404b3d2bf 100644
--- a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
+++ b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
@@ -1441,7 +1441,8 @@ TEST(TypeHints, DependentType) {
void bar(T arg) {
auto [a, b] = arg;
}
- )cpp");
+ )cpp",
+ ExpectedHint{": T", "var2"});
}
TEST(TypeHints, LongTypeName) {
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[llvm-branch-commits] [llvm] AMDGPU: Handle true16 disassembly of ds_write_b8/b16 (PR #156406)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156406?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#156406** https://app.graphite.dev/github/pr/llvm/llvm-project/156406?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/156406?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#156405** https://app.graphite.dev/github/pr/llvm/llvm-project/156405?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156402** https://app.graphite.dev/github/pr/llvm/llvm-project/156402?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#156399** https://app.graphite.dev/github/pr/llvm/llvm-project/156399?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/156406 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [lldb] release/21.x: [libc++] Ensure that we restore invariants in basic_filebuf::overflow (#147389) (PR #155712)
DavidSpickett wrote: Actually the problem is that there is a pipeline wide timeout of 2 hours. This is reasonable most of the time but sometimes our AArch64 builds are taking > 2h. I will address this on our side. Could that be due to a test taking ages, maybe, but probably not given we've had reports of this on other changes. Also I was looking around and found https://buildkite.com/llvm-project/libcxx-ci/builds/67243/steps/canvas?sid=0198e5cb-a69a-43e1-944b-67d4402c4253 which looks exactly like the AIX failure seen on this PR. https://github.com/llvm/llvm-project/pull/155712 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP] Refactor MachineSMEABIPass state (PR #156674)
https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/156674
None
>From c36bbc21aa552fb3c4c63df76df5f5de3610c46b Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Tue, 2 Sep 2025 17:14:25 +
Subject: [PATCH] [WIP] Refactor MachineSMEABIPass state
Change-Id: I3ec3dcb65a0ff77c59b0741ca7240d80f44e62a3
---
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp | 268 ++
1 file changed, 148 insertions(+), 120 deletions(-)
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index e460e7a1e774f..f49042a1fd6d0 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -110,6 +110,66 @@ struct PhysRegSave {
Register X0Save = AArch64::NoRegister;
};
+/// Contains the needed ZA state (and live registers) at an instruction.
+struct InstInfo {
+ ZAState NeededState{ZAState::ANY};
+ MachineBasicBlock::iterator InsertPt;
+ LiveRegs PhysLiveRegs = LiveRegs::None;
+};
+
+/// Contains the needed ZA state for each instruction in a block. Instructions
+/// that do not require a ZA state are not recorded.
+struct BlockInfo {
+ ZAState FixedEntryState{ZAState::ANY};
+ SmallVector Insts;
+ LiveRegs PhysLiveRegsAtEntry = LiveRegs::None;
+ LiveRegs PhysLiveRegsAtExit = LiveRegs::None;
+};
+
+/// Contains the needed ZA state information for all blocks within a function.
+struct FunctionInfo {
+ SmallVector Blocks;
+ std::optional AfterSMEProloguePt;
+ LiveRegs PhysLiveRegsAfterSMEPrologue = LiveRegs::None;
+};
+
+/// State/helpers that is only needed when emitting code to handle
+/// saving/restoring ZA.
+struct EmitContext {
+ EmitContext() = default;
+
+ /// Get or create a TPIDR2 block in \p MF.
+ int getTPIDR2Block(MachineFunction &MF) {
+if (TPIDR2BlockFI)
+ return *TPIDR2BlockFI;
+MachineFrameInfo &MFI = MF.getFrameInfo();
+TPIDR2BlockFI = MFI.CreateStackObject(16, Align(16), false);
+return *TPIDR2BlockFI;
+ }
+
+ /// Get or create agnostic ZA buffer pointer in \p MF.
+ Register getAgnosticZABufferPtr(MachineFunction &MF) {
+if (AgnosticZABufferPtr != AArch64::NoRegister)
+ return AgnosticZABufferPtr;
+if (auto BufferPtr =
+MF.getInfo()->getEarlyAllocSMESaveBuffer();
+BufferPtr != AArch64::NoRegister)
+ AgnosticZABufferPtr = BufferPtr;
+else
+ AgnosticZABufferPtr =
+ MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
+return AgnosticZABufferPtr;
+ }
+
+ bool needsSaveBuffer() const {
+return TPIDR2BlockFI || AgnosticZABufferPtr != AArch64::NoRegister;
+ }
+
+private:
+ std::optional TPIDR2BlockFI;
+ Register AgnosticZABufferPtr = AArch64::NoRegister;
+};
+
static bool isLegalEdgeBundleZAState(ZAState State) {
switch (State) {
case ZAState::ACTIVE:
@@ -119,9 +179,6 @@ static bool isLegalEdgeBundleZAState(ZAState State) {
return false;
}
}
-struct TPIDR2State {
- int FrameIndex = -1;
-};
StringRef getZAStateString(ZAState State) {
#define MAKE_CASE(V)
\
@@ -192,25 +249,26 @@ struct MachineSMEABI : public MachineFunctionPass {
/// Collects the needed ZA state (and live registers) before each instruction
/// within the machine function.
- void collectNeededZAStates(SMEAttrs);
+ FunctionInfo collectNeededZAStates(SMEAttrs SMEFnAttrs);
/// Assigns each edge bundle a ZA state based on the needed states of blocks
/// that have incoming or outgoing edges in that bundle.
- void assignBundleZAStates();
+ SmallVector assignBundleZAStates(FunctionInfo const &FnInfo);
/// Inserts code to handle changes between ZA states within the function.
/// E.g., ACTIVE -> LOCAL_SAVED will insert code required to save ZA.
- void insertStateChanges();
+ void insertStateChanges(EmitContext &, FunctionInfo const &FnInfo,
+ ArrayRef BundleStates);
// Emission routines for private and shared ZA functions (using lazy saves).
void emitNewZAPrologue(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
- void emitRestoreLazySave(MachineBasicBlock &MBB,
+ void emitRestoreLazySave(EmitContext &, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
LiveRegs PhysLiveRegs);
- void emitSetupLazySave(MachineBasicBlock &MBB,
+ void emitSetupLazySave(EmitContext &, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
- void emitAllocateLazySaveBuffer(MachineBasicBlock &MBB,
+ void emitAllocateLazySaveBuffer(EmitContext &, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
void emitZAOff(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
bool ClearTPIDR2);
@@ -222,35 +280,38 @@ struct MachineSMEABI : public MachineFunctionPass {
// Emit a "full" ZA save
[llvm-branch-commits] [clang] [LifetimeSafety] Mark all DeclRefExpr as usages of the corresp. origin (PR #154316)
github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff HEAD~1 HEAD --extensions cpp -- clang/lib/Analysis/LifetimeSafety.cpp clang/test/Sema/warn-lifetime-safety-dataflow.cpp `` View the diff from clang-format here. ``diff diff --git a/clang/lib/Analysis/LifetimeSafety.cpp b/clang/lib/Analysis/LifetimeSafety.cpp index 947645852..dbbf7f3cc 100644 --- a/clang/lib/Analysis/LifetimeSafety.cpp +++ b/clang/lib/Analysis/LifetimeSafety.cpp @@ -598,7 +598,7 @@ private: } FactManager &FactMgr; - AnalysisDeclContext& AC; + AnalysisDeclContext &AC; llvm::SmallVector CurrentBlockFacts; // To distinguish between reads and writes for use-after-free checks, this map // stores the `UseFact` for each `DeclRefExpr`. We initially identify all `` https://github.com/llvm/llvm-project/pull/154316 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Mark all DeclRefExpr as usages of the corresp. origin (PR #154316)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From 613942a19bbde5b905adb9552fa7dc106f76152c Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analysis/LifetimeSafety.cpp | 89 +--
.../Sema/warn-lifetime-safety-dataflow.cpp| 26 ++
2 files changed, 89 insertions(+), 26 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 3c9ac9c48b2e5..dbbf7f3cc14b1 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -118,6 +118,7 @@ class OriginManager {
return AllOrigins.back();
}
+ // TODO: Mark this method as const once we remove the call to getOrCreate.
OriginID get(const Expr &E) {
// Origin of DeclRefExpr is that of the declaration it refers to.
if (const auto *DRE = dyn_cast(&E))
@@ -314,22 +315,28 @@ class ReturnOfOriginFact : public Fact {
};
class UseFact : public Fact {
- OriginID UsedOrigin;
const Expr *UseExpr;
+ // True if this use is a write operation (e.g., left-hand side of
assignment).
+ // Write operations are exempted from use-after-free checks.
+ bool IsWritten = false;
public:
static bool classof(const Fact *F) { return F->getKind() == Kind::Use; }
- UseFact(OriginID UsedOrigin, const Expr *UseExpr)
- : Fact(Kind::Use), UsedOrigin(UsedOrigin), UseExpr(UseExpr) {}
+ UseFact(const Expr *UseExpr) : Fact(Kind::Use), UseExpr(UseExpr) {}
- OriginID getUsedOrigin() const { return UsedOrigin; }
+ OriginID getUsedOrigin(const OriginManager &OM) const {
+// TODO: Remove const cast and make OriginManager::get as const.
+return const_cast(OM).get(*UseExpr);
+ }
const Expr *getUseExpr() const { return UseExpr; }
+ void markAsWritten() { IsWritten = true; }
+ bool isWritten() const { return IsWritten; }
void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
OS << "Use (";
-OM.dump(getUsedOrigin(), OS);
-OS << ")\n";
+OM.dump(getUsedOrigin(OM), OS);
+OS << " " << (isWritten() ? "Write" : "Read") << ")\n";
}
};
@@ -436,6 +443,8 @@ class FactGenerator : public
ConstStmtVisitor {
addAssignOriginFact(*VD, *InitExpr);
}
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+
void VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *N) {
/// TODO: Handle nullptr expr as a special 'null' loan. Uninitialized
/// pointers can use the same type of loan.
@@ -469,10 +478,6 @@ class FactGenerator : public
ConstStmtVisitor {
}
}
}
-} else if (UO->getOpcode() == UO_Deref) {
- // This is a pointer use, like '*p'.
- OriginID OID = FactMgr.getOriginMgr().get(*UO->getSubExpr());
- CurrentBlockFacts.push_back(FactMgr.createFact(OID, UO));
}
}
@@ -487,20 +492,13 @@ class FactGenerator : public
ConstStmtVisitor {
}
void VisitBinaryOperator(const BinaryOperator *BO) {
-if (BO->isAssignmentOp()) {
- const Expr *LHSExpr = BO->getLHS();
- const Expr *RHSExpr = BO->getRHS();
-
- // We are interested in assignments like `ptr1 = ptr2` or `ptr = &var`
- // LHS must be a pointer/reference type that can be an origin.
- // RHS must also represent an origin (either another pointer/ref or an
- // address-of).
- if (const auto *DRE_LHS = dyn_cast(LHSExpr))
-if (const auto *VD_LHS =
-dyn_cast(DRE_LHS->getDecl()->getCanonicalDecl());
-VD_LHS && hasOrigin(VD_LHS->getType()))
- addAssignOriginFact(*VD_LHS, *RHSExpr);
-}
+if (BO->isAssignmentOp())
+ handleAssignment(BO->getLHS(), BO->getRHS());
+ }
+
+ void VisitCXXOperatorCallExpr(const CXXOperatorCallExpr *OCE) {
+if (OCE->isAssignmentOp() && OCE->getNumArgs() == 2)
+ handleAssignment(OCE->getArg(0), OCE->getArg(1));
}
void VisitCXXFunctionalCastExpr(const CXXFunctionalCastExpr *FCE) {
@@ -567,9 +565,47 @@ class FactGenerator : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+dyn_cast(LHSExpr->IgnoreParenImpCasts())) {
+ markUseAsWrite(DRE_LHS);
+ if (const auto *VD_LHS = dyn_cast(DRE_LHS->getDecl()))
+if (hasOrigin(LHSExpr->getType()))
+ // We are interested in assignments like `ptr1 = ptr2` or `ptr =
&var`
+ // LHS must be a pointer/reference type that can be an origin.
+ // RHS must also represent an origin (either another pointer/ref or
an
+ // address-of).
+ addAssignOriginFact(*VD_LHS, *RHSExpr);
+}
+ }
+
+ // A DeclRefExpr is a use of the referenced decl. It is checked for
+ // use-after-free unless it is being
[llvm-branch-commits] [llvm] [LoopUnroll] Skip remainder loop guard if skip unrolled loop (PR #156549)
@@ -271,35 +276,51 @@ static void ConnectEpilog(Loop *L, Value *ModVal,
BasicBlock *NewExit,
NewExit);
// Now PHIs should look like:
// NewExit:
-// PN = PHI [I, Latch], [poison, PreHeader]
+// PN = PHI [I, Latch]
// ...
// Exit:
// EpilogPN = PHI [PN, NewExit], [VMap[I], EpilogLatch]
}
- // Create PHI nodes at NewExit (from the unrolling loop Latch and PreHeader).
- // Update corresponding PHI nodes in epilog loop.
+ // Create PHI nodes at NewExit (from the unrolling loop Latch) and at
+ // EpilogPreHeader (from PreHeader and NewExit). Update corresponding PHI
+ // nodes in epilog loop.
for (BasicBlock *Succ : successors(Latch)) {
// Skip this as we already updated phis in exit blocks.
if (!L->contains(Succ))
continue;
+
+// Succ here appears to always be just L->getHeader(). Otherwise, how do
we
+// know its corresponding epilog block (from VMap) is EpilogHeader and thus
+// EpilogPreHeader is the right incoming block for VPN, as set below?
+// TODO: Can we thus avoid the enclosing loop over successors?
+assert(Succ == L->getHeader() &&
+ "Expect only non-loop successor of latch to be header");
+
for (PHINode &PN : Succ->phis()) {
- // Add new PHI nodes to the loop exit block and update epilog
- // PHIs with the new PHI values.
- PHINode *NewPN = PHINode::Create(PN.getType(), 2, PN.getName() + ".unr");
- NewPN->insertBefore(NewExit->getFirstNonPHIIt());
- // Adding a value to the new PHI node from the unrolling loop preheader.
- NewPN->addIncoming(PN.getIncomingValueForBlock(NewPreHeader), PreHeader);
- // Adding a value to the new PHI node from the unrolling loop latch.
- NewPN->addIncoming(PN.getIncomingValueForBlock(Latch), Latch);
+ // Add new PHI nodes to the loop exit block.
+ PHINode *NewPN0 = PHINode::Create(PN.getType(), 1, PN.getName() +
".unr");
mtrofin wrote:
do you need a phi if all you have is 1 incoming value?
also, a nit: could you please add an argument comment for what `1` and then
further below, `2`, are?
https://github.com/llvm/llvm-project/pull/156549
___
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[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][SME] Support agnostic ZA functions in the MachineSMEABIPass (PR #149064)
@@ -250,6 +286,9 @@ struct MachineSMEABI : public MachineFunctionPass {
SmallVector BundleStates;
MacDue wrote:
Here's a WIP patch that implements the scheme I mentioned previously:
https://github.com/llvm/llvm-project/pull/156674
https://github.com/llvm/llvm-project/pull/149064
___
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[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Mark all DeclRefExpr as usages of the corresp. origin (PR #154316)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From fffc8d6575370ff5f59379dca01b2c1396b52c50 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analysis/LifetimeSafety.cpp | 91 +--
.../Sema/warn-lifetime-safety-dataflow.cpp| 26 ++
2 files changed, 90 insertions(+), 27 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index 3c9ac9c48b2e5..947645852be36 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -118,6 +118,7 @@ class OriginManager {
return AllOrigins.back();
}
+ // TODO: Mark this method as const once we remove the call to getOrCreate.
OriginID get(const Expr &E) {
// Origin of DeclRefExpr is that of the declaration it refers to.
if (const auto *DRE = dyn_cast(&E))
@@ -314,22 +315,28 @@ class ReturnOfOriginFact : public Fact {
};
class UseFact : public Fact {
- OriginID UsedOrigin;
const Expr *UseExpr;
+ // True if this use is a write operation (e.g., left-hand side of
assignment).
+ // Write operations are exempted from use-after-free checks.
+ bool IsWritten = false;
public:
static bool classof(const Fact *F) { return F->getKind() == Kind::Use; }
- UseFact(OriginID UsedOrigin, const Expr *UseExpr)
- : Fact(Kind::Use), UsedOrigin(UsedOrigin), UseExpr(UseExpr) {}
+ UseFact(const Expr *UseExpr) : Fact(Kind::Use), UseExpr(UseExpr) {}
- OriginID getUsedOrigin() const { return UsedOrigin; }
+ OriginID getUsedOrigin(const OriginManager &OM) const {
+// TODO: Remove const cast and make OriginManager::get as const.
+return const_cast(OM).get(*UseExpr);
+ }
const Expr *getUseExpr() const { return UseExpr; }
+ void markAsWritten() { IsWritten = true; }
+ bool isWritten() const { return IsWritten; }
void dump(llvm::raw_ostream &OS, const OriginManager &OM) const override {
OS << "Use (";
-OM.dump(getUsedOrigin(), OS);
-OS << ")\n";
+OM.dump(getUsedOrigin(OM), OS);
+OS << " " << (isWritten() ? "Write" : "Read") << ")\n";
}
};
@@ -436,6 +443,8 @@ class FactGenerator : public
ConstStmtVisitor {
addAssignOriginFact(*VD, *InitExpr);
}
+ void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+
void VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *N) {
/// TODO: Handle nullptr expr as a special 'null' loan. Uninitialized
/// pointers can use the same type of loan.
@@ -469,10 +478,6 @@ class FactGenerator : public
ConstStmtVisitor {
}
}
}
-} else if (UO->getOpcode() == UO_Deref) {
- // This is a pointer use, like '*p'.
- OriginID OID = FactMgr.getOriginMgr().get(*UO->getSubExpr());
- CurrentBlockFacts.push_back(FactMgr.createFact(OID, UO));
}
}
@@ -487,20 +492,13 @@ class FactGenerator : public
ConstStmtVisitor {
}
void VisitBinaryOperator(const BinaryOperator *BO) {
-if (BO->isAssignmentOp()) {
- const Expr *LHSExpr = BO->getLHS();
- const Expr *RHSExpr = BO->getRHS();
-
- // We are interested in assignments like `ptr1 = ptr2` or `ptr = &var`
- // LHS must be a pointer/reference type that can be an origin.
- // RHS must also represent an origin (either another pointer/ref or an
- // address-of).
- if (const auto *DRE_LHS = dyn_cast(LHSExpr))
-if (const auto *VD_LHS =
-dyn_cast(DRE_LHS->getDecl()->getCanonicalDecl());
-VD_LHS && hasOrigin(VD_LHS->getType()))
- addAssignOriginFact(*VD_LHS, *RHSExpr);
-}
+if (BO->isAssignmentOp())
+ handleAssignment(BO->getLHS(), BO->getRHS());
+ }
+
+ void VisitCXXOperatorCallExpr(const CXXOperatorCallExpr *OCE) {
+if (OCE->isAssignmentOp() && OCE->getNumArgs() == 2)
+ handleAssignment(OCE->getArg(0), OCE->getArg(1));
}
void VisitCXXFunctionalCastExpr(const CXXFunctionalCastExpr *FCE) {
@@ -567,9 +565,47 @@ class FactGenerator : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+dyn_cast(LHSExpr->IgnoreParenImpCasts())) {
+ markUseAsWrite(DRE_LHS);
+ if (const auto *VD_LHS = dyn_cast(DRE_LHS->getDecl()))
+if (hasOrigin(LHSExpr->getType()))
+ // We are interested in assignments like `ptr1 = ptr2` or `ptr =
&var`
+ // LHS must be a pointer/reference type that can be an origin.
+ // RHS must also represent an origin (either another pointer/ref or
an
+ // address-of).
+ addAssignOriginFact(*VD_LHS, *RHSExpr);
+}
+ }
+
+ // A DeclRefExpr is a use of the referenced decl. It is checked for
+ // use-after-free unless it is being
[llvm-branch-commits] [llvm] [LoopUnroll] Skip remainder loop guard if skip unrolled loop (PR #156549)
https://github.com/mtrofin approved this pull request. https://github.com/llvm/llvm-project/pull/156549 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [LifetimeSafety] Add support for GSL Pointer types (PR #154009)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From ab16e9aa72482026ed1ca48cd9e245fd4eaade9a Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 17 Aug 2025 10:10:18 +
Subject: [PATCH] [LifetimeSafety] Track gsl::Pointer types
---
clang/lib/Analysis/LifetimeSafety.cpp | 153 ---
clang/test/Sema/warn-lifetime-safety.cpp | 120 +++-
.../unittests/Analysis/LifetimeSafetyTest.cpp | 182 +-
3 files changed, 419 insertions(+), 36 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index dbbf7f3cc14b1..875e08431fe02 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -445,6 +445,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitCXXConstructExpr(const CXXConstructExpr *CCE) {
+if (!isGslPointerType(CCE->getType()))
+ return;
+if (CCE->getNumArgs() != 1)
+ return;
+if (hasOrigin(CCE->getArg(0)->getType()))
+ addAssignOriginFact(*CCE, *CCE->getArg(0));
+else
+ // This could be a new borrow.
+ handleFucntionCall(CCE, CCE->getConstructor(),
+ {CCE->getArgs(), CCE->getNumArgs()});
+ }
+
+ void VisitCXXMemberCallExpr(const CXXMemberCallExpr *MCE) {
+// Specifically for conversion operators,
+// like `std::string_view p = std::string{};`
+if (isGslPointerType(MCE->getType()) &&
+isa(MCE->getCalleeDecl())) {
+ // The argument is the implicit object itself.
+ handleFucntionCall(MCE, MCE->getMethodDecl(),
+ {MCE->getImplicitObjectArgument()});
+}
+// FIXME: A more general VisitCallExpr could also be used here.
+ }
+
void VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *N) {
/// TODO: Handle nullptr expr as a special 'null' loan. Uninitialized
/// pointers can use the same type of loan.
@@ -465,18 +490,9 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitUnaryOperator(const UnaryOperator *UO) {
if (UO->getOpcode() == UO_AddrOf) {
const Expr *SubExpr = UO->getSubExpr();
- if (const auto *DRE = dyn_cast(SubExpr)) {
-if (const auto *VD = dyn_cast(DRE->getDecl())) {
- // Check if it's a local variable.
- if (VD->hasLocalStorage()) {
-OriginID OID = FactMgr.getOriginMgr().getOrCreate(*UO);
-AccessPath AddrOfLocalVarPath(VD);
-const Loan &L =
-FactMgr.getLoanMgr().addLoan(AddrOfLocalVarPath, UO);
-CurrentBlockFacts.push_back(
-FactMgr.createFact(L.ID, OID));
- }
-}
+ if (const Loan *L = createLoanFrom(SubExpr, UO)) {
+OriginID OID = FactMgr.getOriginMgr().getOrCreate(*UO);
+CurrentBlockFacts.push_back(FactMgr.createFact(L->ID, OID));
}
}
}
@@ -504,22 +520,27 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitCXXFunctionalCastExpr(const CXXFunctionalCastExpr *FCE) {
// Check if this is a test point marker. If so, we are done with this
// expression.
-if (VisitTestPoint(FCE))
+if (handleTestPoint(FCE))
return;
-// Visit as normal otherwise.
-Base::VisitCXXFunctionalCastExpr(FCE);
+if (isGslPointerType(FCE->getType()))
+ addAssignOriginFact(*FCE, *FCE->getSubExpr());
}
-private:
- // Check if a type has an origin.
- bool hasOrigin(QualType QT) { return QT->isPointerOrReferenceType(); }
+ void VisitInitListExpr(const InitListExpr *ILE) {
+if (!hasOrigin(ILE->getType()))
+ return;
+// For list initialization with a single element, like `View{...}`, the
+// origin of the list itself is the origin of its single element.
+if (ILE->getNumInits() == 1)
+ addAssignOriginFact(*ILE, *ILE->getInit(0));
+ }
- template
- void addAssignOriginFact(const Destination &D, const Source &S) {
-OriginID DestOID = FactMgr.getOriginMgr().getOrCreate(D);
-OriginID SrcOID = FactMgr.getOriginMgr().get(S);
-CurrentBlockFacts.push_back(
-FactMgr.createFact(DestOID, SrcOID));
+ void VisitMaterializeTemporaryExpr(const MaterializeTemporaryExpr *MTE) {
+if (!hasOrigin(MTE->getType()))
+ return;
+// A temporary object's origin is the same as the origin of the
+// expression that initializes it.
+addAssignOriginFact(*MTE, *MTE->getSubExpr());
}
void handleDestructor(const CFGAutomaticObjDtor &DtorOpt) {
@@ -544,9 +565,91 @@ class FactGenerator : public
ConstStmtVisitor {
}
}
+private:
+ static bool isGslPointerType(QualType QT) {
+if (const auto *RD = QT->getAsCXXRecordDecl()) {
+ // We need to check the template definition for specializations.
+ if (auto *CTSD = dyn_cast(RD))
+return CTSD->getSpecializedTemplate()
+->getTemplatedDecl()
+->hasAttr
[llvm-branch-commits] [llvm] [LoopUnroll] Skip remainder loop guard if skip unrolled loop (PR #156549)
@@ -271,35 +276,51 @@ static void ConnectEpilog(Loop *L, Value *ModVal,
BasicBlock *NewExit,
NewExit);
// Now PHIs should look like:
// NewExit:
-// PN = PHI [I, Latch], [poison, PreHeader]
+// PN = PHI [I, Latch]
// ...
// Exit:
// EpilogPN = PHI [PN, NewExit], [VMap[I], EpilogLatch]
}
- // Create PHI nodes at NewExit (from the unrolling loop Latch and PreHeader).
- // Update corresponding PHI nodes in epilog loop.
+ // Create PHI nodes at NewExit (from the unrolling loop Latch) and at
+ // EpilogPreHeader (from PreHeader and NewExit). Update corresponding PHI
+ // nodes in epilog loop.
for (BasicBlock *Succ : successors(Latch)) {
// Skip this as we already updated phis in exit blocks.
if (!L->contains(Succ))
continue;
+
+// Succ here appears to always be just L->getHeader(). Otherwise, how do
we
+// know its corresponding epilog block (from VMap) is EpilogHeader and thus
+// EpilogPreHeader is the right incoming block for VPN, as set below?
+// TODO: Can we thus avoid the enclosing loop over successors?
+assert(Succ == L->getHeader() &&
+ "Expect only non-loop successor of latch to be header");
+
for (PHINode &PN : Succ->phis()) {
- // Add new PHI nodes to the loop exit block and update epilog
- // PHIs with the new PHI values.
- PHINode *NewPN = PHINode::Create(PN.getType(), 2, PN.getName() + ".unr");
- NewPN->insertBefore(NewExit->getFirstNonPHIIt());
- // Adding a value to the new PHI node from the unrolling loop preheader.
- NewPN->addIncoming(PN.getIncomingValueForBlock(NewPreHeader), PreHeader);
- // Adding a value to the new PHI node from the unrolling loop latch.
- NewPN->addIncoming(PN.getIncomingValueForBlock(Latch), Latch);
+ // Add new PHI nodes to the loop exit block.
+ PHINode *NewPN0 = PHINode::Create(PN.getType(), 1, PN.getName() +
".unr");
jdenny-ornl wrote:
> do you need a phi if all you have is 1 incoming value?
I believe that is [required for LCSSA
form](https://llvm.org/docs/LoopTerminology.html#loop-closed-ssa-lcssa) given
that the incoming value is the latch (in the loop) and the phi is on an exiting
edge.
>
> also, a nit: could you please add an argument comment for what `1` and then
> further below, `2`, are?
Will do.
https://github.com/llvm/llvm-project/pull/156549
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[llvm-branch-commits] [clang] [LifetimeSafety] Add support for GSL Pointer types (PR #154009)
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From 447c9ba2cc7d4a886a3c5c40d54bb1b3bcab2255 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 17 Aug 2025 10:10:18 +
Subject: [PATCH] [LifetimeSafety] Track gsl::Pointer types
---
clang/lib/Analysis/LifetimeSafety.cpp | 153 ---
clang/test/Sema/warn-lifetime-safety.cpp | 120 +++-
.../unittests/Analysis/LifetimeSafetyTest.cpp | 182 +-
3 files changed, 419 insertions(+), 36 deletions(-)
diff --git a/clang/lib/Analysis/LifetimeSafety.cpp
b/clang/lib/Analysis/LifetimeSafety.cpp
index dbbf7f3cc14b1..875e08431fe02 100644
--- a/clang/lib/Analysis/LifetimeSafety.cpp
+++ b/clang/lib/Analysis/LifetimeSafety.cpp
@@ -445,6 +445,31 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitDeclRefExpr(const DeclRefExpr *DRE) { handleUse(DRE); }
+ void VisitCXXConstructExpr(const CXXConstructExpr *CCE) {
+if (!isGslPointerType(CCE->getType()))
+ return;
+if (CCE->getNumArgs() != 1)
+ return;
+if (hasOrigin(CCE->getArg(0)->getType()))
+ addAssignOriginFact(*CCE, *CCE->getArg(0));
+else
+ // This could be a new borrow.
+ handleFucntionCall(CCE, CCE->getConstructor(),
+ {CCE->getArgs(), CCE->getNumArgs()});
+ }
+
+ void VisitCXXMemberCallExpr(const CXXMemberCallExpr *MCE) {
+// Specifically for conversion operators,
+// like `std::string_view p = std::string{};`
+if (isGslPointerType(MCE->getType()) &&
+isa(MCE->getCalleeDecl())) {
+ // The argument is the implicit object itself.
+ handleFucntionCall(MCE, MCE->getMethodDecl(),
+ {MCE->getImplicitObjectArgument()});
+}
+// FIXME: A more general VisitCallExpr could also be used here.
+ }
+
void VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *N) {
/// TODO: Handle nullptr expr as a special 'null' loan. Uninitialized
/// pointers can use the same type of loan.
@@ -465,18 +490,9 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitUnaryOperator(const UnaryOperator *UO) {
if (UO->getOpcode() == UO_AddrOf) {
const Expr *SubExpr = UO->getSubExpr();
- if (const auto *DRE = dyn_cast(SubExpr)) {
-if (const auto *VD = dyn_cast(DRE->getDecl())) {
- // Check if it's a local variable.
- if (VD->hasLocalStorage()) {
-OriginID OID = FactMgr.getOriginMgr().getOrCreate(*UO);
-AccessPath AddrOfLocalVarPath(VD);
-const Loan &L =
-FactMgr.getLoanMgr().addLoan(AddrOfLocalVarPath, UO);
-CurrentBlockFacts.push_back(
-FactMgr.createFact(L.ID, OID));
- }
-}
+ if (const Loan *L = createLoanFrom(SubExpr, UO)) {
+OriginID OID = FactMgr.getOriginMgr().getOrCreate(*UO);
+CurrentBlockFacts.push_back(FactMgr.createFact(L->ID, OID));
}
}
}
@@ -504,22 +520,27 @@ class FactGenerator : public
ConstStmtVisitor {
void VisitCXXFunctionalCastExpr(const CXXFunctionalCastExpr *FCE) {
// Check if this is a test point marker. If so, we are done with this
// expression.
-if (VisitTestPoint(FCE))
+if (handleTestPoint(FCE))
return;
-// Visit as normal otherwise.
-Base::VisitCXXFunctionalCastExpr(FCE);
+if (isGslPointerType(FCE->getType()))
+ addAssignOriginFact(*FCE, *FCE->getSubExpr());
}
-private:
- // Check if a type has an origin.
- bool hasOrigin(QualType QT) { return QT->isPointerOrReferenceType(); }
+ void VisitInitListExpr(const InitListExpr *ILE) {
+if (!hasOrigin(ILE->getType()))
+ return;
+// For list initialization with a single element, like `View{...}`, the
+// origin of the list itself is the origin of its single element.
+if (ILE->getNumInits() == 1)
+ addAssignOriginFact(*ILE, *ILE->getInit(0));
+ }
- template
- void addAssignOriginFact(const Destination &D, const Source &S) {
-OriginID DestOID = FactMgr.getOriginMgr().getOrCreate(D);
-OriginID SrcOID = FactMgr.getOriginMgr().get(S);
-CurrentBlockFacts.push_back(
-FactMgr.createFact(DestOID, SrcOID));
+ void VisitMaterializeTemporaryExpr(const MaterializeTemporaryExpr *MTE) {
+if (!hasOrigin(MTE->getType()))
+ return;
+// A temporary object's origin is the same as the origin of the
+// expression that initializes it.
+addAssignOriginFact(*MTE, *MTE->getSubExpr());
}
void handleDestructor(const CFGAutomaticObjDtor &DtorOpt) {
@@ -544,9 +565,91 @@ class FactGenerator : public
ConstStmtVisitor {
}
}
+private:
+ static bool isGslPointerType(QualType QT) {
+if (const auto *RD = QT->getAsCXXRecordDecl()) {
+ // We need to check the template definition for specializations.
+ if (auto *CTSD = dyn_cast(RD))
+return CTSD->getSpecializedTemplate()
+->getTemplatedDecl()
+->hasAttr
[llvm-branch-commits] [mlir] [mlir][ptr] Extend `ptr_add` operation to support shaped operands (PR #156374)
@@ -23,6 +24,41 @@ class LLVM_Attrhttps://github.com/llvm/llvm-project/pull/156374 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][ptr] Extend `ptr_add` operation to support shaped operands (PR #156374)
@@ -23,6 +24,41 @@ class LLVM_Attrhttps://github.com/llvm/llvm-project/pull/156374 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][ptr] Extend `ptr_add` operation to support shaped operands (PR #156374)
@@ -23,6 +24,41 @@ class LLVM_Attrhttps://github.com/llvm/llvm-project/pull/156374 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] Update cgdata-* tests to not use subshells (PR #156533)
llvmbot wrote: @llvm/pr-subscribers-lld-macho Author: Aiden Grossman (boomanaiden154) Changes Subshells are not supported in the lit internal shell. We can remove them by constructing sed commands directly inside of a separate file. Towards #102700. --- Full diff: https://github.com/llvm/llvm-project/pull/156533.diff 2 Files Affected: - (modified) lld/test/MachO/cgdata-generate-merge.s (+8-4) - (modified) lld/test/MachO/cgdata-generate.s (+8-4) ``diff diff --git a/lld/test/MachO/cgdata-generate-merge.s b/lld/test/MachO/cgdata-generate-merge.s index 3f7fb6777bc3c..4b6d4a5d824cb 100644 --- a/lld/test/MachO/cgdata-generate-merge.s +++ b/lld/test/MachO/cgdata-generate-merge.s @@ -5,11 +5,15 @@ # Synthesize raw cgdata without the header (32 byte) from the indexed cgdata. # RUN: llvm-cgdata --convert --format binary %t/raw-1.cgtext -o %t/raw-1.cgdata -# RUN: od -t x1 -j 32 -An %t/raw-1.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' > %t/raw-1-bytes.txt -# RUN: sed "s//$(cat %t/raw-1-bytes.txt)/g" %t/merge-template.s > %t/merge-1.s +# RUN: echo -n "s//" > %t/raw-1-sed.txt +# RUN: od -t x1 -j 32 -An %t/raw-1.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' >> %t/raw-1-sed.txt +# RUN: echo "/g" >> %t/raw-1-sed.txt +# RUN: sed -f %t/raw-1-sed.txt %t/merge-template.s > %t/merge-1.s # RUN: llvm-cgdata --convert --format binary %t/raw-2.cgtext -o %t/raw-2.cgdata -# RUN: od -t x1 -j 32 -An %t/raw-2.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' > %t/raw-2-bytes.txt -# RUN: sed "s//$(cat %t/raw-2-bytes.txt)/g" %t/merge-template.s > %t/merge-2.s +# RUN: echo -n "s//" > %t/raw-2-sed.txt +# RUN: od -t x1 -j 32 -An %t/raw-2.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' >> %t/raw-2-sed.txt +# RUN: echo "/g" >> %t/raw-2-sed.txt +# RUN: sed -f %t/raw-2-sed.txt %t/merge-template.s > %t/merge-2.s # RUN: llvm-mc -filetype obj -triple arm64-apple-darwin %t/merge-1.s -o %t/merge-1.o # RUN: llvm-mc -filetype obj -triple arm64-apple-darwin %t/merge-2.s -o %t/merge-2.o diff --git a/lld/test/MachO/cgdata-generate.s b/lld/test/MachO/cgdata-generate.s index f942ae07f64e0..63efc81cda179 100644 --- a/lld/test/MachO/cgdata-generate.s +++ b/lld/test/MachO/cgdata-generate.s @@ -5,11 +5,15 @@ # Synthesize raw cgdata without the header (32 byte) from the indexed cgdata. # RUN: llvm-cgdata --convert --format binary %t/raw-1.cgtext -o %t/raw-1.cgdata -# RUN: od -t x1 -j 32 -An %t/raw-1.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' > %t/raw-1-bytes.txt -# RUN: sed "s//$(cat %t/raw-1-bytes.txt)/g" %t/merge-template.s > %t/merge-1.s +# RUN: echo -n "s//" > %t/raw-1-sed.txt +# RUN: od -t x1 -j 32 -An %t/raw-1.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' >> %t/raw-1-sed.txt +# RUN: echo "/g" >> %t/raw-1-sed.txt +# RUN: sed -f %t/raw-1-sed.txt %t/merge-template.s > %t/merge-1.s # RUN: llvm-cgdata --convert --format binary %t/raw-2.cgtext -o %t/raw-2.cgdata -# RUN: od -t x1 -j 32 -An %t/raw-2.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' > %t/raw-2-bytes.txt -# RUN: sed "s//$(cat %t/raw-2-bytes.txt)/g" %t/merge-template.s > %t/merge-2.s +# RUN: echo -n "s//" > %t/raw-2-sed.txt +# RUN: od -t x1 -j 32 -An %t/raw-2.cgdata | tr -d '\n\r\t' | sed 's/[ ][ ]*/ /g; s/^[ ]*//; s/[ ]*$//; s/[ ]/,0x/g; s/^/0x/' >> %t/raw-2-sed.txt +# RUN: echo "/g" >> %t/raw-2-sed.txt +# RUN: sed -f %t/raw-2-sed.txt %t/merge-template.s > %t/merge-2.s # RUN: llvm-mc -filetype obj -triple arm64-apple-darwin %t/merge-1.s -o %t/merge-1.o # RUN: llvm-mc -filetype obj -triple arm64-apple-darwin %t/merge-2.s -o %t/merge-2.o `` https://github.com/llvm/llvm-project/pull/156533 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
