[llvm-branch-commits] [clang] 61529d9 - [RISCV] Remove implied extension Zvfhmin for XAndesVPackFPH (#146861)
Author: Jim Lin
Date: 2025-07-04T10:16:20+08:00
New Revision: 61529d9e36fa86782a2458e6bdeedf7f376ef4b5
URL:
https://github.com/llvm/llvm-project/commit/61529d9e36fa86782a2458e6bdeedf7f376ef4b5
DIFF:
https://github.com/llvm/llvm-project/commit/61529d9e36fa86782a2458e6bdeedf7f376ef4b5.diff
LOG: [RISCV] Remove implied extension Zvfhmin for XAndesVPackFPH (#146861)
XAndesVPackFPH can actually be used independently without requiring
Zvfhmin. Therefore, we remove the implicitly required Zvfhmin extension
from XAndesVPackFPH and imply that the f extension is sufficient.
Added:
Modified:
clang/lib/Sema/SemaRISCV.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadt.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadb.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadt.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadb.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadt.c
clang/test/Sema/rvv-andes-required-features-invalid.c
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 37e7468103752..cc110e1115ed5 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -1435,9 +1435,15 @@ void SemaRISCV::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D,
!FeatureMap.lookup("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !FeatureMap.lookup("zvfh") &&
- !FeatureMap.lookup("zvfhmin"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D)
-<< Ty << "zvfh or zvfhmin";
+ !FeatureMap.lookup("zvfhmin") &&
+ !FeatureMap.lookup("xandesvpackfph"))
+if (DeclareAndesVectorBuiltins) {
+ Diag(Loc, diag::err_riscv_type_requires_extension, D)
+ << Ty << "zvfh, zvfhmin or xandesvpackfph";
+} else {
+ Diag(Loc, diag::err_riscv_type_requires_extension, D)
+ << Ty << "zvfh or zvfhmin";
+}
else if (Info.ElementType->isBFloat16Type() &&
!FeatureMap.lookup("zvfbfmin") &&
!FeatureMap.lookup("xandesvbfhcvt"))
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
index 48e3a1b0fc295..ec0ad7d23ac8b 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
index e435a31eb3314..e0627b3e0f6cc 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
index 46c6648bc7a82..686b476b0d594 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
@@ -1,7 +1,6 @@
[llvm-branch-commits] [clang] 724dfdc - [OpenCL] Add declarations for version 1.1 of cl_intel_subgroups_short (#146647)
Author: Mészáros Gergely Date: 2025-07-04T06:23:31+02:00 New Revision: 724dfdc948a894a7aec21c1c5da0f5736c14bc2f URL: https://github.com/llvm/llvm-project/commit/724dfdc948a894a7aec21c1c5da0f5736c14bc2f DIFF: https://github.com/llvm/llvm-project/commit/724dfdc948a894a7aec21c1c5da0f5736c14bc2f.diff LOG: [OpenCL] Add declarations for version 1.1 of cl_intel_subgroups_short (#146647) `cl_intel_subgroups_short` version 1.1 adds vec16 types for block reads and writes. Ref: https://github.com/KhronosGroup/OpenCL-Docs/pull/906 Co-authored-by: Victor Mustya Added: Modified: clang/lib/Headers/opencl-c.h Removed: diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h index 8d8ef497cec49..19ce6999a0fde 100644 --- a/clang/lib/Headers/opencl-c.h +++ b/clang/lib/Headers/opencl-c.h @@ -17617,6 +17617,7 @@ ushort __ovld __conv intel_sub_group_block_read_us(read_only image2d_t, int ushort2 __ovld __conv intel_sub_group_block_read_us2(read_only image2d_t, int2); ushort4 __ovld __conv intel_sub_group_block_read_us4(read_only image2d_t, int2); ushort8 __ovld __conv intel_sub_group_block_read_us8(read_only image2d_t, int2); +ushort16__ovld __conv intel_sub_group_block_read_us16(read_only image2d_t, int2); #endif // defined(__opencl_c_images) #if defined(__opencl_c_read_write_images) @@ -17624,18 +17625,21 @@ ushort __ovld __conv intel_sub_group_block_read_us(read_write image2d_t, in ushort2 __ovld __conv intel_sub_group_block_read_us2(read_write image2d_t, int2); ushort4 __ovld __conv intel_sub_group_block_read_us4(read_write image2d_t, int2); ushort8 __ovld __conv intel_sub_group_block_read_us8(read_write image2d_t, int2); +ushort16__ovld __conv intel_sub_group_block_read_us16(read_write image2d_t, int2); #endif // defined(__opencl_c_read_write_images) ushort __ovld __conv intel_sub_group_block_read_us( const __global ushort* p ); ushort2 __ovld __conv intel_sub_group_block_read_us2( const __global ushort* p ); ushort4 __ovld __conv intel_sub_group_block_read_us4( const __global ushort* p ); ushort8 __ovld __conv intel_sub_group_block_read_us8( const __global ushort* p ); +ushort16__ovld __conv intel_sub_group_block_read_us16(const __global ushort* p); #if defined(__opencl_c_images) void__ovld __conv intel_sub_group_block_write_us(write_only image2d_t, int2, ushort); void__ovld __conv intel_sub_group_block_write_us2(write_only image2d_t, int2, ushort2); void__ovld __conv intel_sub_group_block_write_us4(write_only image2d_t, int2, ushort4); void__ovld __conv intel_sub_group_block_write_us8(write_only image2d_t, int2, ushort8); +void__ovld __conv intel_sub_group_block_write_us16(write_only image2d_t, int2, ushort16); #endif // defined(__opencl_c_images) #if defined(__opencl_c_read_write_images) @@ -17643,12 +17647,14 @@ void__ovld __conv intel_sub_group_block_write_us(read_write image2d_t, i void__ovld __conv intel_sub_group_block_write_us2(read_write image2d_t, int2, ushort2); void__ovld __conv intel_sub_group_block_write_us4(read_write image2d_t, int2, ushort4); void__ovld __conv intel_sub_group_block_write_us8(read_write image2d_t, int2, ushort8); +void__ovld __conv intel_sub_group_block_write_us16(read_write image2d_t, int2, ushort16); #endif // defined(__opencl_c_read_write_images) void__ovld __conv intel_sub_group_block_write_us( __global ushort* p, ushort data ); void__ovld __conv intel_sub_group_block_write_us2( __global ushort* p, ushort2 data ); void__ovld __conv intel_sub_group_block_write_us4( __global ushort* p, ushort4 data ); void__ovld __conv intel_sub_group_block_write_us8( __global ushort* p, ushort8 data ); +void__ovld __conv intel_sub_group_block_write_us16( __global ushort* p, ushort16 data ); #endif // cl_intel_subgroups_short #ifdef cl_intel_device_side_avc_motion_estimation ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 0612c4b - [Driver][Test] pgo-sample-use-profi.c: Specify targets to fix test (#146996)
Author: Nilanjana Basu Date: 2025-07-03T22:10:29-07:00 New Revision: 0612c4bbd336dc4e206605fc380ac0af58c2df69 URL: https://github.com/llvm/llvm-project/commit/0612c4bbd336dc4e206605fc380ac0af58c2df69 DIFF: https://github.com/llvm/llvm-project/commit/0612c4bbd336dc4e206605fc380ac0af58c2df69.diff LOG: [Driver][Test] pgo-sample-use-profi.c: Specify targets to fix test (#146996) This test that got updated in https://github.com/llvm/llvm-project/pull/145957, reportedly fails for some targets (e.g. AIX). Specifying targets to fix it. Added: Modified: clang/test/Driver/pgo-sample-use-profi.c Removed: diff --git a/clang/test/Driver/pgo-sample-use-profi.c b/clang/test/Driver/pgo-sample-use-profi.c index a8c8e81f96dcb..aef00724f8687 100644 --- a/clang/test/Driver/pgo-sample-use-profi.c +++ b/clang/test/Driver/pgo-sample-use-profi.c @@ -1,19 +1,22 @@ /// Test if profi flag is enabled/disabled correctly based on user-specified configuration. /// Ensure that profi flag is disabled by default -// Target specific checks: // RUN: %clang --target=x86_64 -c -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI -// RUN: %clang --target=AArch64 -c -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=x86_64 -c -fsample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s +// RUN: %clang --target=x86_64 -c -fno-sample-profile-use-profi -fsample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s -// Target agnostic checks: -// RUN: %clang -c -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI -// RUN: %clang -c -fsample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s -// RUN: %clang -c -fno-sample-profile-use-profi -fsample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s +// RUN: %clang --target=AArch64 -c -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=AArch64 -c -fsample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s +// RUN: %clang --target=AArch64 -c -fno-sample-profile-use-profi -fsample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s // Cases where profi flag is explicitly disabled: -// RUN: %clang -c -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI -// RUN: %clang -c -fno-sample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI -// RUN: %clang -c -fsample-profile-use-profi -fno-sample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=x86_64 -c -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=x86_64 -c -fno-sample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=x86_64 -c -fsample-profile-use-profi -fno-sample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI + +// RUN: %clang --target=AArch64 -c -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=AArch64 -c -fno-sample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI +// RUN: %clang --target=AArch64 -c -fsample-profile-use-profi -fno-sample-profile-use-profi -fprofile-sample-use=/dev/null -### %s 2>&1 | FileCheck %s --check-prefixes=CHECK-NO-PROFI // CHECK: "-mllvm" "-sample-profile-use-profi" ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] a550fef - [llvm] Use llvm::fill instead of std::fill(NFC) (#146911)
Author: Austin
Date: 2025-07-04T14:10:28+08:00
New Revision: a550fef9061f3628e75825306759b13365cb50e3
URL:
https://github.com/llvm/llvm-project/commit/a550fef9061f3628e75825306759b13365cb50e3
DIFF:
https://github.com/llvm/llvm-project/commit/a550fef9061f3628e75825306759b13365cb50e3.diff
LOG: [llvm] Use llvm::fill instead of std::fill(NFC) (#146911)
Use llvm::fill instead of std::fill
Added:
Modified:
llvm/docs/CodingStandards.rst
llvm/include/llvm/ADT/BitVector.h
llvm/include/llvm/ADT/Bitset.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/include/llvm/TargetParser/SubtargetFeature.h
llvm/lib/CodeGen/MachineLICM.cpp
llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/ExecutionEngine/ExecutionEngine.cpp
llvm/lib/Transforms/Scalar/LoopDeletion.cpp
llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
llvm/lib/Transforms/Utils/LoopUtils.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
llvm/tools/llvm-mca/Views/RegisterFileStatistics.cpp
llvm/tools/llvm-mca/Views/TimelineView.cpp
llvm/unittests/Support/ParallelTest.cpp
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Removed:
diff --git a/llvm/docs/CodingStandards.rst b/llvm/docs/CodingStandards.rst
index 7d275a511de1a..c614a6d7ace9e 100644
--- a/llvm/docs/CodingStandards.rst
+++ b/llvm/docs/CodingStandards.rst
@@ -684,7 +684,7 @@ something notionally equivalent. Examples:
};
// The Foo constructor call is reading a file, don't use braces to call it.
- std::fill(foo.begin(), foo.end(), Foo("name"));
+ llvm::fill(foo, Foo("name"));
// The pair is being constructed like an aggregate, use braces.
bar_map.insert({my_key, my_value});
diff --git a/llvm/include/llvm/ADT/BitVector.h
b/llvm/include/llvm/ADT/BitVector.h
index 0eaa77b6dd81c..70de4c239c1c7 100644
--- a/llvm/include/llvm/ADT/BitVector.h
+++ b/llvm/include/llvm/ADT/BitVector.h
@@ -795,9 +795,7 @@ class BitVector {
set_unused_bits(false);
}
- void init_words(bool t) {
-std::fill(Bits.begin(), Bits.end(), 0 - (BitWord)t);
- }
+ void init_words(bool t) { llvm::fill(Bits, 0 - (BitWord)t); }
template
void applyMask(const uint32_t *Mask, unsigned MaskWords) {
diff --git a/llvm/include/llvm/ADT/Bitset.h b/llvm/include/llvm/ADT/Bitset.h
index 4ba5c63535b2d..55b96e47f2ed6 100644
--- a/llvm/include/llvm/ADT/Bitset.h
+++ b/llvm/include/llvm/ADT/Bitset.h
@@ -50,7 +50,7 @@ class Bitset {
}
Bitset &set() {
-std::fill(std::begin(Bits), std::end(Bits), -BitWord(0));
+llvm::fill(Bits, -BitWord(0));
return *this;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 84c53e1e45452..b07937c11b024 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1116,10 +1116,7 @@ class LLVM_ABI TargetLoweringBase {
LegalizeTypeAction ValueTypeActions[MVT::VALUETYPE_SIZE];
public:
-ValueTypeActionImpl() {
- std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
-TypeLegal);
-}
+ValueTypeActionImpl() { llvm::fill(ValueTypeActions, TypeLegal); }
LegalizeTypeAction getTypeAction(MVT VT) const {
return ValueTypeActions[VT.SimpleTy];
diff --git a/llvm/include/llvm/TargetParser/SubtargetFeature.h
b/llvm/include/llvm/TargetParser/SubtargetFeature.h
index cdcfcdd0e802e..a48b18745352a 100644
--- a/llvm/include/llvm/TargetParser/SubtargetFeature.h
+++ b/llvm/include/llvm/TargetParser/SubtargetFeature.h
@@ -56,7 +56,7 @@ class FeatureBitset {
}
FeatureBitset &set() {
-std::fill(std::begin(Bits), std::end(Bits), -1ULL);
+llvm::fill(Bits, -1ULL);
return *this;
}
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp
b/llvm/lib/CodeGen/MachineLICM.cpp
index c9079170ca575..699d7ab175568 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -400,7 +400,7 @@ bool MachineLICMImpl::run(MachineFunction &MF) {
// Estimate register pressure during pre-regalloc pass.
unsigned NumRPS = TRI->getNumRegPressureSets();
RegPressure.resize(NumRPS);
-std::fill(RegPressure.begin(), RegPressure.end(), 0);
+llvm::fill(RegPressure, 0);
RegLimit.resize(NumRPS);
for (unsigned i = 0, e = NumRPS; i != e; ++i)
RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
@@ -941,7 +941,7 @@ static bool isOperandKill(const MachineOperand &MO,
MachineRegisterInfo *MRI) {
/// initialize the starting "register pressure". Note this does not count live
/// through (livein but not used) registers.
void MachineLICMImpl::InitRegPressure(MachineBasicBlock *BB) {
-
[llvm-branch-commits] [llvm] 671870b - [RISCV] Fold funct7 into class for XAndesVBFHCvt instructions. NFC.
Author: Jim Lin
Date: 2025-07-04T14:36:18+08:00
New Revision: 671870be913234f13dac8cb8d2f8e36240c59046
URL:
https://github.com/llvm/llvm-project/commit/671870be913234f13dac8cb8d2f8e36240c59046
DIFF:
https://github.com/llvm/llvm-project/commit/671870be913234f13dac8cb8d2f8e36240c59046.diff
LOG: [RISCV] Fold funct7 into class for XAndesVBFHCvt instructions. NFC.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
index c7aa8cd5162b3..6954a955af6e2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
@@ -372,13 +372,13 @@ class NDSRVInstVD4DOT funct6, string opcodestr>
let RVVConstraint = VMConstraint;
}
-class NDSRVInstVBFHCvt funct7, bits<5> vs1, string opcodestr>
+class NDSRVInstVBFHCvt vs1, string opcodestr>
: RVInst<(outs VR:$vd), (ins VR:$vs2, VMaskOp:$vm),
opcodestr, "$vd, $vs2", [], InstFormatR> {
bits<5> vs2;
bits<5> vd;
- let Inst{31-25} = funct7;
+ let Inst{31-25} = 0b000;
let Inst{24-20} = vs2;
let Inst{19-15} = vs1;
let Inst{14-12} = 0b100;
@@ -537,9 +537,9 @@ def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;
let Predicates = [HasVendorXAndesVBFHCvt], Constraints = "@earlyclobber $vd",
mayRaiseFPException = true in {
let RVVConstraint = VS2Constraint, DestEEW = EEWSEWx2 in
-def NDS_VFWCVT_S_BF16 : NDSRVInstVBFHCvt<0b000, 0b0,
"nds.vfwcvt.s.bf16">;
+def NDS_VFWCVT_S_BF16 : NDSRVInstVBFHCvt<0b0, "nds.vfwcvt.s.bf16">;
let Uses = [FRM, VL, VTYPE] in
-def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b000, 0b1,
"nds.vfncvt.bf16.s">;
+def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b1, "nds.vfncvt.bf16.s">;
}
//===--===//
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[llvm-branch-commits] [clang] 872eac7 - [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC. (#146862)
Author: Jim Lin Date: 2025-07-04T13:27:51+08:00 New Revision: 872eac7af0050813062baba9662beb81093b6b55 URL: https://github.com/llvm/llvm-project/commit/872eac7af0050813062baba9662beb81093b6b55 DIFF: https://github.com/llvm/llvm-project/commit/872eac7af0050813062baba9662beb81093b6b55.diff LOG: [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC. (#146862) I'd like to ensure that the tests under clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/ only come from https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/auto-generated Added: clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c clang/test/CodeGe
[llvm-branch-commits] [flang] 8c9e0c6 - [flang][OpenMP] Allocate `reduction` init temps on the stack for GPUs (#146667)
Author: Kareem Ergawy
Date: 2025-07-04T06:29:34+02:00
New Revision: 8c9e0c6c61f653928a992422d534e4e7f976dd55
URL:
https://github.com/llvm/llvm-project/commit/8c9e0c6c61f653928a992422d534e4e7f976dd55
DIFF:
https://github.com/llvm/llvm-project/commit/8c9e0c6c61f653928a992422d534e4e7f976dd55.diff
LOG: [flang][OpenMP] Allocate `reduction` init temps on the stack for GPUs
(#146667)
Temps needed for the reduction init regions are now allocate on the heap
all the time. However, this is performance killer for GPUs since malloc
calls are prohibitively expensive. Therefore, we should do these
allocations on the stack for GPU reductions.
Added:
Modified:
flang/lib/Lower/Support/PrivateReductionUtils.cpp
flang/test/Lower/OpenMP/parallel-reduction-array.f90
mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Removed:
diff --git a/flang/lib/Lower/Support/PrivateReductionUtils.cpp
b/flang/lib/Lower/Support/PrivateReductionUtils.cpp
index e878041d37c03..c3a5b6101ce00 100644
--- a/flang/lib/Lower/Support/PrivateReductionUtils.cpp
+++ b/flang/lib/Lower/Support/PrivateReductionUtils.cpp
@@ -502,22 +502,37 @@ void
PopulateInitAndCleanupRegionsHelper::initAndCleanupBoxedArray(
// Allocating on the heap in case the whole reduction/privatization is nested
// inside of a loop
- auto [temp, needsDealloc] = createTempFromMold(loc, builder, source);
- // if needsDealloc isn't statically false, add cleanup region. Always
- // do this for allocatable boxes because they might have been re-allocated
- // in the body of the loop/parallel region
-
- std::optional cstNeedsDealloc = fir::getIntIfConstant(needsDealloc);
- assert(cstNeedsDealloc.has_value() &&
- "createTempFromMold decides this statically");
- if (cstNeedsDealloc.has_value() && *cstNeedsDealloc != false) {
-mlir::OpBuilder::InsertionGuard guard(builder);
-createCleanupRegion(converter, loc, argType, cleanupRegion, sym,
-isDoConcurrent);
- } else {
-assert(!isAllocatableOrPointer &&
- "Pointer-like arrays must be heap allocated");
- }
+ auto temp = [&]() {
+bool shouldAllocateOnStack = false;
+
+// On the GPU, always allocate on the stack since heap allocatins are very
+// expensive.
+if (auto offloadMod = llvm::dyn_cast(
+*builder.getModule()))
+ shouldAllocateOnStack = offloadMod.getIsGPU();
+
+if (shouldAllocateOnStack)
+ return createStackTempFromMold(loc, builder, source);
+
+auto [temp, needsDealloc] = createTempFromMold(loc, builder, source);
+// if needsDealloc isn't statically false, add cleanup region. Always
+// do this for allocatable boxes because they might have been re-allocated
+// in the body of the loop/parallel region
+
+std::optional cstNeedsDealloc =
+fir::getIntIfConstant(needsDealloc);
+assert(cstNeedsDealloc.has_value() &&
+ "createTempFromMold decides this statically");
+if (cstNeedsDealloc.has_value() && *cstNeedsDealloc != false) {
+ mlir::OpBuilder::InsertionGuard guard(builder);
+ createCleanupRegion(converter, loc, argType, cleanupRegion, sym,
+ isDoConcurrent);
+} else {
+ assert(!isAllocatableOrPointer &&
+ "Pointer-like arrays must be heap allocated");
+}
+return temp;
+ }();
// Put the temporary inside of a box:
// hlfir::genVariableBox doesn't handle non-default lower bounds
diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array.f90
b/flang/test/Lower/OpenMP/parallel-reduction-array.f90
index 8e3de498f59c1..4f889d9a4e77f 100644
--- a/flang/test/Lower/OpenMP/parallel-reduction-array.f90
+++ b/flang/test/Lower/OpenMP/parallel-reduction-array.f90
@@ -1,5 +1,8 @@
-! RUN: bbc -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s
-! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s
+! RUN: bbc -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s --check-prefix=CPU
+! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s
--check-prefix=CPU
+
+! RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device -fopenmp-is-gpu -o -
%s 2>&1 | FileCheck %s --check-prefix=GPU
+! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp
-fopenmp-is-target-device -o - %s 2>&1 | FileCheck %s --check-prefix=GPU
program reduce
integer, dimension(3) :: i = 0
@@ -13,81 +16,88 @@ program reduce
print *,i
end program
-! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_box_3xi32 :
!fir.ref>> alloc {
-! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box>
-! CHECK: omp.yield(%[[VAL_8]] :
!fir.ref>>)
-! CHECK-LABEL: } init {
-! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>,
%[[ALLOC:.*]]: !fir.ref>>):
-! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32
-! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_0]] :
!fir.ref>>
-! CHECK:
[llvm-branch-commits] [clang] ddcccc4 - [OpenCL] Add decls for cl_intel_subgroups_char, cl_intel_subgroups_long (#146655)
Author: Mészáros Gergely Date: 2025-07-04T06:25:45+02:00 New Revision: dd4afaff5de66b655caac997189157c34b82 URL: https://github.com/llvm/llvm-project/commit/dd4afaff5de66b655caac997189157c34b82 DIFF: https://github.com/llvm/llvm-project/commit/dd4afaff5de66b655caac997189157c34b82.diff LOG: [OpenCL] Add decls for cl_intel_subgroups_char, cl_intel_subgroups_long (#146655) These extensions add char and long support to the subgroup builtins. They are already supported by the Intel Graphics Compiler. Co-authored-by: Victor Mustya Added: Modified: clang/lib/Headers/opencl-c.h Removed: diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h index 19ce6999a0fde..6fca2e1a39122 100644 --- a/clang/lib/Headers/opencl-c.h +++ b/clang/lib/Headers/opencl-c.h @@ -17482,7 +17482,50 @@ double __ovld __conv intel_sub_group_shuffle_up( double prev, double cur, uint double __ovld __conv intel_sub_group_shuffle_xor( double, uint ); #endif -#endif //cl_intel_subgroups +#if defined(cl_intel_subgroups_char) || defined(cl_intel_subgroups_short) || \ +defined(cl_intel_subgroups_long) + +#if defined(__opencl_c_images) +uint __ovld __conv intel_sub_group_block_read_ui(read_only image2d_t, int2); +uint2 __ovld __conv intel_sub_group_block_read_ui2(read_only image2d_t, int2); +uint4 __ovld __conv intel_sub_group_block_read_ui4(read_only image2d_t, int2); +uint8 __ovld __conv intel_sub_group_block_read_ui8(read_only image2d_t, int2); +#endif // defined(__opencl_c_images) + +#if defined(__opencl_c_read_write_images) +uint __ovld __conv intel_sub_group_block_read_ui(read_write image2d_t, int2); +uint2 __ovld __conv intel_sub_group_block_read_ui2(read_write image2d_t, int2); +uint4 __ovld __conv intel_sub_group_block_read_ui4(read_write image2d_t, int2); +uint8 __ovld __conv intel_sub_group_block_read_ui8(read_write image2d_t, int2); +#endif // defined(__opencl_c_read_write_images) + +uint __ovld __conv intel_sub_group_block_read_ui( const __global uint* p ); +uint2 __ovld __conv intel_sub_group_block_read_ui2( const __global uint* p ); +uint4 __ovld __conv intel_sub_group_block_read_ui4( const __global uint* p ); +uint8 __ovld __conv intel_sub_group_block_read_ui8( const __global uint* p ); + +#if defined(__opencl_c_images) +void __ovld __conv intel_sub_group_block_write_ui(read_only image2d_t, int2, uint); +void __ovld __conv intel_sub_group_block_write_ui2(read_only image2d_t, int2, uint2); +void __ovld __conv intel_sub_group_block_write_ui4(read_only image2d_t, int2, uint4); +void __ovld __conv intel_sub_group_block_write_ui8(read_only image2d_t, int2, uint8); +#endif // defined(__opencl_c_images) + +#if defined(__opencl_c_read_write_images) +void __ovld __conv intel_sub_group_block_write_ui(read_write image2d_t, int2, uint); +void __ovld __conv intel_sub_group_block_write_ui2(read_write image2d_t, int2, uint2); +void __ovld __conv intel_sub_group_block_write_ui4(read_write image2d_t, int2, uint4); +void __ovld __conv intel_sub_group_block_write_ui8(read_write image2d_t, int2, uint8); +#endif // defined(__opencl_c_read_write_images) + +void __ovld __conv intel_sub_group_block_write_ui( __global uint* p, uint data ); +void __ovld __conv intel_sub_group_block_write_ui2( __global uint* p, uint2 data ); +void __ovld __conv intel_sub_group_block_write_ui4( __global uint* p, uint4 data ); +void __ovld __conv intel_sub_group_block_write_ui8( __global uint* p, uint8 data ); + +#endif // defined(cl_intel_subgroups_char) || defined(cl_intel_subgroups_short) || + // defined(cl_intel_subgroups_long) +#endif // cl_intel_subgroups #if defined(cl_intel_subgroups_short) short __ovld __conv intel_sub_group_broadcast( short , uint sub_group_local_id ); @@ -17574,44 +17617,6 @@ ushort __ovld __conv intel_sub_group_scan_inclusive_min( ushort x ); short __ovld __conv intel_sub_group_scan_inclusive_max( short x ); ushort __ovld __conv intel_sub_group_scan_inclusive_max( ushort x ); -#if defined(__opencl_c_images) -uint __ovld __conv intel_sub_group_block_read_ui(read_only image2d_t, int2); -uint2 __ovld __conv intel_sub_group_block_read_ui2(read_only image2d_t, int2); -uint4 __ovld __conv intel_sub_group_block_read_ui4(read_only image2d_t, int2); -uint8 __ovld __conv intel_sub_group_block_read_ui8(read_only image2d_t, int2); -#endif // defined(__opencl_c_images) - -#if defined(__opencl_c_read_write_images) -uint __ovld __conv intel_sub_group_block_read_ui(read_write image2d_t, int2); -uint2 __ovld __conv intel_sub_group_block_read_ui2(read_write image2d_t, int2); -uint4 __ovld __conv intel_sub_group_block_read_ui4(read_write image2d_t, int2); -uint8 __ovld __
[llvm-branch-commits] [clang] 85aaaf6 - [clang-tidy] EndSourceFile() for preprocessor before diagnostic client (#145784)
Author: Dave Bartolomeo
Date: 2025-07-04T12:36:57+08:00
New Revision: 85aaaf6e740842782f9fbcde3b5be4aa0c79
URL:
https://github.com/llvm/llvm-project/commit/85aaaf6e740842782f9fbcde3b5be4aa0c79
DIFF:
https://github.com/llvm/llvm-project/commit/85aaaf6e740842782f9fbcde3b5be4aa0c79.diff
LOG: [clang-tidy] EndSourceFile() for preprocessor before diagnostic client
(#145784)
The comment for `DiagnosticConsumer::BeginSourceFile()` states that
"diagnostics with source range information are required to only be
emitted in between BeginSourceFile() and EndSourceFile().". While
working on some upcoming changes to the static analyzer, we hit some
crashes when diagnostics were reported from the `EndOfMainFile` callback
in the preprocessor. This turned out to be because
`FrontEndAction::EndSourceFile()` notifies the diagnostic clients of the
end of the source file before it notifies the preprocessor. Thus, the
diagnostics from the preprocessor callback are reported when the
diagnostic client is no longer expecting any diagnostics.
The fix is to swap the order of the `EndSourceFile()` calls so that the
preprocessor is notified first.
I've added asserts to the `ClangTidyDiagnosticConsumer` to catch
unexpected diagnostics outside of a source file. Before swapping the
order of the calls as described above, this causes several failures in
the clang-tidy regression tests. With the swap, there are no failures in
`check-all`.
rdar://141230583
Added:
Modified:
clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.h
clang/lib/Frontend/FrontendAction.cpp
Removed:
diff --git a/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
b/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
index a71813a103df3..c35f0b941c600 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
+++ b/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
@@ -358,8 +358,27 @@ getFixIt(const tooling::Diagnostic &Diagnostic, bool
AnyFix) {
} // namespace clang::tidy
+void ClangTidyDiagnosticConsumer::BeginSourceFile(const LangOptions &LangOpts,
+ const Preprocessor *PP) {
+ DiagnosticConsumer::BeginSourceFile(LangOpts, PP);
+
+ assert(!InSourceFile);
+ InSourceFile = true;
+}
+
+void ClangTidyDiagnosticConsumer::EndSourceFile() {
+ assert(InSourceFile);
+ InSourceFile = false;
+
+ DiagnosticConsumer::EndSourceFile();
+}
+
void ClangTidyDiagnosticConsumer::HandleDiagnostic(
DiagnosticsEngine::Level DiagLevel, const Diagnostic &Info) {
+ // A diagnostic should not be reported outside of a
+ // BeginSourceFile()/EndSourceFile() pair if it has a source location.
+ assert(InSourceFile || Info.getLocation().isInvalid());
+
if (LastErrorWasIgnored && DiagLevel == DiagnosticsEngine::Note)
return;
diff --git a/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.h
b/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.h
index a8851e794f24b..6e7cb7bb10e57 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.h
+++ b/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.h
@@ -292,6 +292,11 @@ class ClangTidyDiagnosticConsumer : public
DiagnosticConsumer {
void HandleDiagnostic(DiagnosticsEngine::Level DiagLevel,
const Diagnostic &Info) override;
+ void BeginSourceFile(const LangOptions &LangOpts,
+ const Preprocessor *PP = nullptr) override;
+
+ void EndSourceFile() override;
+
// Retrieve the diagnostics that were captured.
std::vector take();
@@ -326,6 +331,11 @@ class ClangTidyDiagnosticConsumer : public
DiagnosticConsumer {
bool LastErrorRelatesToUserCode = false;
bool LastErrorPassesLineFilter = false;
bool LastErrorWasIgnored = false;
+ /// Tracks whether we're currently inside a
+ /// `BeginSourceFile()/EndSourceFile()` pair. Outside of a source file, we
+ /// should only receive diagnostics that have to source location, such as
+ /// command-line warnings.
+ bool InSourceFile = false;
};
} // end namespace tidy
diff --git a/clang/lib/Frontend/FrontendAction.cpp
b/clang/lib/Frontend/FrontendAction.cpp
index ef7ae27a2694a..f5996a8e1e88b 100644
--- a/clang/lib/Frontend/FrontendAction.cpp
+++ b/clang/lib/Frontend/FrontendAction.cpp
@@ -1243,13 +1243,15 @@ llvm::Error FrontendAction::Execute() {
void FrontendAction::EndSourceFile() {
CompilerInstance &CI = getCompilerInstance();
- // Inform the diagnostic client we are done with this source file.
- CI.getDiagnosticClient().EndSourceFile();
-
// Inform the preprocessor we are done.
if (CI.hasPreprocessor())
CI.getPreprocessor().EndSourceFile();
+ // Inform the diagnostic client we are done with this source file.
+ // Do this after notifying the preprocessor, so that end
[llvm-branch-commits] [clang] 8fe205d - [Serialization] Remove an unnecessary cast (NFC) (#146986)
Author: Kazu Hirata
Date: 2025-07-03T22:04:31-07:00
New Revision: 8fe205d31695e43b31f0d5334384cc297e440571
URL:
https://github.com/llvm/llvm-project/commit/8fe205d31695e43b31f0d5334384cc297e440571
DIFF:
https://github.com/llvm/llvm-project/commit/8fe205d31695e43b31f0d5334384cc297e440571.diff
LOG: [Serialization] Remove an unnecessary cast (NFC) (#146986)
Lambda is already of CXXRecordDecl *.
Added:
Modified:
clang/lib/Serialization/ASTReader.cpp
Removed:
diff --git a/clang/lib/Serialization/ASTReader.cpp
b/clang/lib/Serialization/ASTReader.cpp
index d380afd1ed1bd..6e03de87e587d 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -9463,8 +9463,7 @@ void ASTReader::AssignedLambdaNumbering(CXXRecordDecl
*Lambda) {
// Keep track of this lambda so it can be merged with another lambda that
// is loaded later.
- LambdaDeclarationsForMerging.insert(
- {LambdaInfo, const_cast(Lambda)});
+ LambdaDeclarationsForMerging.insert({LambdaInfo, Lambda});
}
void ASTReader::LoadSelector(Selector Sel) {
___
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[llvm-branch-commits] [clang] afd20aa - [clang-scan-deps] Fix "unterminated conditional directive" bug (#146645)
Author: Ziqing Luo
Date: 2025-07-04T12:53:23+08:00
New Revision: afd20aaca5fd89dd14992c3fe2f735c5e16ad986
URL:
https://github.com/llvm/llvm-project/commit/afd20aaca5fd89dd14992c3fe2f735c5e16ad986
DIFF:
https://github.com/llvm/llvm-project/commit/afd20aaca5fd89dd14992c3fe2f735c5e16ad986.diff
LOG: [clang-scan-deps] Fix "unterminated conditional directive" bug (#146645)
`clang-scan-deps` threw "unterminated conditional directive" error
falsely on the following example:
```
#ifndef __TEST
#define __TEST
#if defined(__TEST_DUMMY)
#if defined(__TEST_DUMMY2)
#pragma GCC warning \
"Hello!"
#else
#pragma GCC error\
"World!"
#endif // defined(__TEST_DUMMY2)
#endif // defined(__TEST_DUMMY)
#endif // #ifndef __TEST
```
The issue comes from PR #143950, where the flag `LastNonWhitespace` does
not correctly represent the state for the example above. The PR aimed to
support that a line-continuation can be followed by whitespaces.
This commit fixes the issue by moving the `LastNonWhitespace` variable
to the inner loop so that it will be correctly reset.
rdar://153742186
Added:
Modified:
clang/lib/Lex/DependencyDirectivesScanner.cpp
clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
Removed:
diff --git a/clang/lib/Lex/DependencyDirectivesScanner.cpp
b/clang/lib/Lex/DependencyDirectivesScanner.cpp
index a862abcc44b38..d894c265a07a2 100644
--- a/clang/lib/Lex/DependencyDirectivesScanner.cpp
+++ b/clang/lib/Lex/DependencyDirectivesScanner.cpp
@@ -419,7 +419,6 @@ static bool isQuoteCppDigitSeparator(const char *const
Start,
}
void Scanner::skipLine(const char *&First, const char *const End) {
- char LastNonWhitespace = ' ';
for (;;) {
assert(First <= End);
if (First == End)
@@ -430,6 +429,9 @@ void Scanner::skipLine(const char *&First, const char
*const End) {
return;
}
const char *Start = First;
+// Use `LastNonWhitespace`to track if a line-continuation has ever been
seen
+// before a new-line character:
+char LastNonWhitespace = ' ';
while (First != End && !isVerticalWhitespace(*First)) {
// Iterate over strings correctly to avoid comments and newlines.
if (*First == '"' ||
diff --git a/clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
b/clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
index 61f74929c1e98..d2ef27155df94 100644
--- a/clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
+++ b/clang/unittests/Lex/DependencyDirectivesScannerTest.cpp
@@ -880,6 +880,37 @@ TEST(MinimizeSourceToDependencyDirectivesTest,
EXPECT_EQ(pp_eof, Directives[22].Kind);
}
+TEST(MinimizeSourceToDependencyDirectivesTest,
+ TestFixedBugThatReportUnterminatedDirectiveFalsely) {
+ SmallVector Out;
+ SmallVector Tokens;
+ SmallVector Directives;
+
+ StringRef Input = "#ifndef __TEST \n"
+"#define __TEST \n"
+"#if defined(__TEST_DUMMY) \n"
+"#if defined(__TEST_DUMMY2) \n"
+"#pragma GCC warning\\ \n"
+"\"hello!\"\n"
+"#else\n"
+"#pragma GCC error \\ \n"
+"\"world!\" \n"
+"#endif // defined(__TEST_DUMMY2) \n"
+"#endif // defined(__TEST_DUMMY) \n"
+"#endif // #ifndef __TEST \n";
+ ASSERT_FALSE( // False on no error:
+ minimizeSourceToDependencyDirectives(Input, Out, Tokens, Directives));
+ ASSERT_TRUE(Directives.size() == 8);
+ EXPECT_EQ(pp_ifndef, Directives[0].Kind);
+ EXPECT_EQ(pp_define, Directives[1].Kind);
+ EXPECT_EQ(pp_if, Directives[2].Kind);
+ EXPECT_EQ(pp_if, Directives[3].Kind);
+ EXPECT_EQ(pp_endif, Directives[4].Kind);
+ EXPECT_EQ(pp_endif, Directives[5].Kind);
+ EXPECT_EQ(pp_endif, Directives[6].Kind);
+ EXPECT_EQ(pp_eof, Directives[7].Kind);
+}
+
TEST(MinimizeSourceToDependencyDirectivesTest, PoundWarningAndError) {
SmallVector Out;
___
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[llvm-branch-commits] [lldb] 59e812f - [lldb][test] Skip pointer to std::unordered_map formatter tests on older Clang versions
Author: Michael Buch
Date: 2025-07-04T07:39:13+01:00
New Revision: 59e812f2eed8be9674efa42cdbfe4a9d1fb57052
URL:
https://github.com/llvm/llvm-project/commit/59e812f2eed8be9674efa42cdbfe4a9d1fb57052
DIFF:
https://github.com/llvm/llvm-project/commit/59e812f2eed8be9674efa42cdbfe4a9d1fb57052.diff
LOG: [lldb][test] Skip pointer to std::unordered_map formatter tests on older
Clang versions
These only work after https://github.com/llvm/llvm-project/pull/143501 and
https://github.com/llvm/llvm-project/pull/144517. Skip on older compilers. This
currently fails on the macOS matrix bots that run the LLDB test-suite with
older Clang versions.
See https://github.com/llvm/llvm-project/issues/146040.
Added:
Modified:
lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/TestDataFormatterLibccUnorderedMap.py
lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/main.cpp
Removed:
diff --git
a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/TestDataFormatterLibccUnorderedMap.py
b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/TestDataFormatterLibccUnorderedMap.py
index bf103aa78baba..a338e3c12598e 100644
---
a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/TestDataFormatterLibccUnorderedMap.py
+++
b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/TestDataFormatterLibccUnorderedMap.py
@@ -105,7 +105,21 @@ def test_iterator_formatters(self):
type="const StringMapT *const &",
)
-lldbutil.continue_to_breakpoint(process, bkpt)
+@expectedFailureAll(
+bugnumber="https://github.com/llvm/llvm-project/issues/146040";,
+compiler="clang",
+compiler_version=["<", "21"],
+)
+@add_test_categories(["libc++"])
+def test_ptr_formatters(self):
+"""
+Test that pointers to std::unordered_map are formatted correctly.
+"""
+
+self.build()
+(self.target, process, thread, bkpt) =
lldbutil.run_to_source_breakpoint(
+self, "Stop here", lldb.SBFileSpec("main.cpp", False)
+)
self.check_ptr_or_ref("ptr1")
self.check_ptr_or_ref("ptr2")
diff --git
a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/main.cpp
b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/main.cpp
index 26cbb9476119d..5397e54d99545 100644
---
a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/main.cpp
+++
b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/unordered_map-iterator/main.cpp
@@ -16,7 +16,7 @@ static void check_references(const StringMapT &ref1,
StringMapT &ref2,
static void check_pointer(const StringMapT *ptr1, StringMapT *ptr2,
StringMapTPtr ptr3, StringMapTPtr *ptr4,
const StringMapT *const *ptr5, StringMapT **ptr6) {
- std::printf("Break here");
+ std::printf("Stop here");
}
int main() {
___
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[llvm-branch-commits] [llvm] 06c988c - [RISCV][VLOPT] Add support for vwsll.vx/vv. (#146998)
Author: Craig Topper
Date: 2025-07-04T00:07:47-07:00
New Revision: 06c988cefd9194891f16feeb320ec4ef2d0fb5fd
URL:
https://github.com/llvm/llvm-project/commit/06c988cefd9194891f16feeb320ec4ef2d0fb5fd
DIFF:
https://github.com/llvm/llvm-project/commit/06c988cefd9194891f16feeb320ec4ef2d0fb5fd.diff
LOG: [RISCV][VLOPT] Add support for vwsll.vx/vv. (#146998)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 1dd12ab396fd8..a406bada6b1e4 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -517,6 +517,8 @@ getOperandLog2EEW(const MachineOperand &MO, const
MachineRegisterInfo *MRI) {
case RISCV::VWSUB_VV:
case RISCV::VWSUB_VX:
case RISCV::VWSLL_VI:
+ case RISCV::VWSLL_VX:
+ case RISCV::VWSLL_VV:
// Vector Widening Integer Multiply Instructions
// Destination EEW=2*SEW. Source EEW=SEW.
case RISCV::VWMUL_VV:
@@ -1019,6 +1021,8 @@ static bool isSupportedInstr(const MachineInstr &MI) {
// Vector Crypto
case RISCV::VWSLL_VI:
+ case RISCV::VWSLL_VX:
+ case RISCV::VWSLL_VV:
// Vector Mask Instructions
// Vector Mask-Register Logical Instructions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index 4c15d8e3e7c2f..c272297b41c94 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -3081,24 +3081,66 @@ define @vmv_v_v( %a,
%b, %3
}
-define @vwsll_vi( %a,
%b, iXLen %vl) {
+define @vwsll_vi( %a, iXLen %vl) {
; NOVLOPT-LABEL: vwsll_vi:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT:vsetvli a1, zero, e16, m1, ta, ma
-; NOVLOPT-NEXT:vwsll.vi v12, v8, 1
+; NOVLOPT-NEXT:vwsll.vi v10, v8, 1
; NOVLOPT-NEXT:vsetvli zero, a0, e32, m2, ta, ma
-; NOVLOPT-NEXT:vadd.vv v8, v12, v10
+; NOVLOPT-NEXT:vadd.vv v8, v10, v10
; NOVLOPT-NEXT:ret
;
; VLOPT-LABEL: vwsll_vi:
; VLOPT: # %bb.0:
; VLOPT-NEXT:vsetvli zero, a0, e16, m1, ta, ma
-; VLOPT-NEXT:vwsll.vi v12, v8, 1
+; VLOPT-NEXT:vwsll.vi v10, v8, 1
; VLOPT-NEXT:vsetvli zero, zero, e32, m2, ta, ma
-; VLOPT-NEXT:vadd.vv v8, v12, v10
+; VLOPT-NEXT:vadd.vv v8, v10, v10
; VLOPT-NEXT:ret
- %1 = call @llvm.riscv.vwsll.nxv4i32.nxv4i16( poison, %a,iXLen 1, iXLen -1)
- %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl)
+ %1 = call @llvm.riscv.vwsll.nxv4i32.nxv4i16( poison, %a, iXLen 1, iXLen -1)
+ %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %1, iXLen %vl)
+ ret %2
+}
+
+define @vwsll_vx( %a, iXLen %b, iXLen
%vl) {
+; NOVLOPT-LABEL: vwsll_vx:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT:vsetvli a2, zero, e16, m1, ta, ma
+; NOVLOPT-NEXT:vwsll.vx v10, v8, a0
+; NOVLOPT-NEXT:vsetvli zero, a1, e32, m2, ta, ma
+; NOVLOPT-NEXT:vadd.vv v8, v10, v10
+; NOVLOPT-NEXT:ret
+;
+; VLOPT-LABEL: vwsll_vx:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT:vsetvli zero, a1, e16, m1, ta, ma
+; VLOPT-NEXT:vwsll.vx v10, v8, a0
+; VLOPT-NEXT:vsetvli zero, zero, e32, m2, ta, ma
+; VLOPT-NEXT:vadd.vv v8, v10, v10
+; VLOPT-NEXT:ret
+ %1 = call @llvm.riscv.vwsll.nxv4i32.nxv4i16( poison, %a, iXLen %b, iXLen -1)
+ %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %1, iXLen %vl)
+ ret %2
+}
+
+define @vwsll_vv( %a,
%b, iXLen %vl) {
+; NOVLOPT-LABEL: vwsll_vv:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT:vsetvli a1, zero, e16, m1, ta, ma
+; NOVLOPT-NEXT:vwsll.vv v10, v8, v9
+; NOVLOPT-NEXT:vsetvli zero, a0, e32, m2, ta, ma
+; NOVLOPT-NEXT:vadd.vv v8, v10, v10
+; NOVLOPT-NEXT:ret
+;
+; VLOPT-LABEL: vwsll_vv:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT:vsetvli zero, a0, e16, m1, ta, ma
+; VLOPT-NEXT:vwsll.vv v10, v8, v9
+; VLOPT-NEXT:vsetvli zero, zero, e32, m2, ta, ma
+; VLOPT-NEXT:vadd.vv v8, v10, v10
+; VLOPT-NEXT:ret
+ %1 = call @llvm.riscv.vwsll.nxv4i32.nxv4i16( poison, %a, %b, iXLen -1)
+ %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %1, iXLen %vl)
ret %2
}
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[llvm-branch-commits] [clang-tools-extra] 5a9e6ba - [clang-tidy] fix false negatives with type aliases in `cppcoreguidlines-pro-bounds-pointer-arithmetic` check (#139430)
Author: Baranov Victor
Date: 2025-07-04T09:49:26+03:00
New Revision: 5a9e6babd81f03b020d6dff8f150336aa0dc5a28
URL:
https://github.com/llvm/llvm-project/commit/5a9e6babd81f03b020d6dff8f150336aa0dc5a28
DIFF:
https://github.com/llvm/llvm-project/commit/5a9e6babd81f03b020d6dff8f150336aa0dc5a28.diff
LOG: [clang-tidy] fix false negatives with type aliases in
`cppcoreguidlines-pro-bounds-pointer-arithmetic` check (#139430)
Fixed false negatives with type aliases in
`cppcoreguidlines-pro-bounds-pointer-arithmetic` check.
Added tests with pointer arithmetic in template functions to make test
cases more robust.
Closes https://github.com/llvm/llvm-project/issues/139241.
Added:
Modified:
clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.cpp
clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.h
clang-tools-extra/docs/ReleaseNotes.rst
clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-bounds-pointer-arithmetic-pr36489.cpp
clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-bounds-pointer-arithmetic.cpp
Removed:
diff --git
a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.cpp
b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.cpp
index 0d68790349fb5..9ac7b9e057e35 100644
---
a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.cpp
+++
b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.cpp
@@ -15,16 +15,13 @@ using namespace clang::ast_matchers;
namespace clang::tidy::cppcoreguidelines {
void ProBoundsPointerArithmeticCheck::registerMatchers(MatchFinder *Finder) {
- if (!getLangOpts().CPlusPlus)
-return;
-
const auto AllPointerTypes =
- anyOf(hasType(pointerType()),
+ anyOf(hasType(hasUnqualifiedDesugaredType(pointerType())),
hasType(autoType(
hasDeducedType(hasUnqualifiedDesugaredType(pointerType(),
hasType(decltypeType(hasUnderlyingType(pointerType();
- // Flag all operators +, -, +=, -=, ++, -- that result in a pointer
+ // Flag all operators +, -, +=, -= that result in a pointer
Finder->addMatcher(
binaryOperator(
hasAnyOperatorName("+", "-", "+=", "-="), AllPointerTypes,
@@ -32,8 +29,12 @@ void
ProBoundsPointerArithmeticCheck::registerMatchers(MatchFinder *Finder) {
.bind("expr"),
this);
+ // Flag all operators ++, -- that result in a pointer
Finder->addMatcher(
- unaryOperator(hasAnyOperatorName("++", "--"), hasType(pointerType()))
+ unaryOperator(hasAnyOperatorName("++", "--"),
+hasType(hasUnqualifiedDesugaredType(pointerType())),
+unless(hasUnaryOperand(
+ignoringImpCasts(declRefExpr(to(isImplicit()))
.bind("expr"),
this);
diff --git
a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.h
b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.h
index 67f7d1bf9dd69..3466c72a769e9 100644
---
a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.h
+++
b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProBoundsPointerArithmeticCheck.h
@@ -23,6 +23,9 @@ class ProBoundsPointerArithmeticCheck : public ClangTidyCheck
{
public:
ProBoundsPointerArithmeticCheck(StringRef Name, ClangTidyContext *Context)
: ClangTidyCheck(Name, Context) {}
+ bool isLanguageVersionSupported(const LangOptions &LangOpts) const override {
+return LangOpts.CPlusPlus;
+ }
void registerMatchers(ast_matchers::MatchFinder *Finder) override;
void check(const ast_matchers::MatchFinder::MatchResult &Result) override;
};
diff --git a/clang-tools-extra/docs/ReleaseNotes.rst
b/clang-tools-extra/docs/ReleaseNotes.rst
index 198efee7754de..f8f183e9de1cc 100644
--- a/clang-tools-extra/docs/ReleaseNotes.rst
+++ b/clang-tools-extra/docs/ReleaseNotes.rst
@@ -219,7 +219,8 @@ Changes in existing checks
- Improved :doc:`cppcoreguidelines-pro-bounds-pointer-arithmetic
` check by
fixing false positives when calling indexing operators that do not perform
- pointer arithmetic in template, for example ``std::map::operator[]``.
+ pointer arithmetic in template, for example ``std::map::operator[]`` and
+ when pointer arithmetic was used through type aliases.
- Improved :doc:`cppcoreguidelines-rvalue-reference-param-not-moved
` check
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-bounds-pointer-arithmetic-pr36489.cpp
b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-bounds-pointer-arithmetic-pr36489.cpp
index faab2a1ccf0e1..b3d3fab9c5409 100644
---
a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-bounds-pointer-arithmetic-pr3648
[llvm-branch-commits] [llvm] 1d5d125 - [ConstantFolding] Consolidate poison propagation for intrinsics (#146878)
Author: Nikita Popov
Date: 2025-07-04T09:16:28+02:00
New Revision: 1d5d1256487c1574e5a8addcf27983fd569966e5
URL:
https://github.com/llvm/llvm-project/commit/1d5d1256487c1574e5a8addcf27983fd569966e5
DIFF:
https://github.com/llvm/llvm-project/commit/1d5d1256487c1574e5a8addcf27983fd569966e5.diff
LOG: [ConstantFolding] Consolidate poison propagation for intrinsics (#146878)
This consolidates the "fold poison arg to poison result" constant
folding logic for intrinsics, based on a common
intrinsicPropagatesPoison() helper, which is also used for poison
propagation reasoning in ValueTracking. This ensures that the set of
supported intrinsics is consistent.
This add ucmp, scmp, smul.fix, smul.fix.sat, canonicalize and sqrt to
the intrinsicPropagatesPoison list, as these were handled by
ConstantFolding but not ValueTracking. The ctpop test is an example of
the converse, where it was handled by ValueTracking but not
ConstantFolding.
Added:
Modified:
llvm/include/llvm/Analysis/ValueTracking.h
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/Analysis/ValueTracking.cpp
llvm/test/Transforms/InstSimplify/fold-intrinsics.ll
llvm/unittests/Analysis/ValueTrackingTest.cpp
Removed:
diff --git a/llvm/include/llvm/Analysis/ValueTracking.h
b/llvm/include/llvm/Analysis/ValueTracking.h
index 17c79790a69f2..02990a3cb44f7 100644
--- a/llvm/include/llvm/Analysis/ValueTracking.h
+++ b/llvm/include/llvm/Analysis/ValueTracking.h
@@ -727,6 +727,9 @@ LLVM_ABI bool isGuaranteedToExecuteForEveryIteration(const
Instruction *I,
/// getGuaranteedNonPoisonOp.
LLVM_ABI bool propagatesPoison(const Use &PoisonOp);
+/// Return whether this intrinsic propagates poison for all operands.
+LLVM_ABI bool intrinsicPropagatesPoison(Intrinsic::ID IID);
+
/// Return true if the given instruction must trigger undefined behavior
/// when I is executed with any operands which appear in KnownPoison holding
/// a poison value at the point of execution.
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp
b/llvm/lib/Analysis/ConstantFolding.cpp
index 9e3c271f7d93f..af955f202ac28 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -2229,17 +2229,6 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
return nullptr;
}
- if (isa(Operands[0])) {
-// TODO: All of these operations should probably propagate poison.
-switch (IntrinsicID) {
-case Intrinsic::canonicalize:
-case Intrinsic::sqrt:
- return PoisonValue::get(Ty);
-default:
- break;
-}
- }
-
if (isa(Operands[0])) {
// cosine(arg) is between -1 and 1. cosine(invalid arg) is NaN.
// ctpop() is between 0 and bitwidth, pick 0 for undef.
@@ -3228,11 +3217,6 @@ static Constant
*ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
case Intrinsic::smin:
case Intrinsic::umax:
case Intrinsic::umin:
- // This is the same as for binary ops - poison propagates.
- // TODO: Poison handling should be consolidated.
- if (isa(Operands[0]) || isa(Operands[1]))
-return PoisonValue::get(Ty);
-
if (!C0 && !C1)
return UndefValue::get(Ty);
if (!C0 || !C1)
@@ -3245,9 +3229,6 @@ static Constant *ConstantFoldIntrinsicCall2(Intrinsic::ID
IntrinsicID, Type *Ty,
case Intrinsic::scmp:
case Intrinsic::ucmp:
- if (isa(Operands[0]) || isa(Operands[1]))
-return PoisonValue::get(Ty);
-
if (!C0 || !C1)
return ConstantInt::get(Ty, 0);
@@ -3314,11 +3295,6 @@ static Constant
*ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
}
case Intrinsic::uadd_sat:
case Intrinsic::sadd_sat:
- // This is the same as for binary ops - poison propagates.
- // TODO: Poison handling should be consolidated.
- if (isa(Operands[0]) || isa(Operands[1]))
-return PoisonValue::get(Ty);
-
if (!C0 && !C1)
return UndefValue::get(Ty);
if (!C0 || !C1)
@@ -3329,11 +3305,6 @@ static Constant
*ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
return ConstantInt::get(Ty, C0->sadd_sat(*C1));
case Intrinsic::usub_sat:
case Intrinsic::ssub_sat:
- // This is the same as for binary ops - poison propagates.
- // TODO: Poison handling should be consolidated.
- if (isa(Operands[0]) || isa(Operands[1]))
-return PoisonValue::get(Ty);
-
if (!C0 && !C1)
return UndefValue::get(Ty);
if (!C0 || !C1)
@@ -3592,11 +3563,6 @@ static Constant *ConstantFoldScalarCall3(StringRef Name,
if (IntrinsicID == Intrinsic::smul_fix ||
IntrinsicID == Intrinsic::smul_fix_sat) {
-// poison * C -> poison
-// C * poison -> poison
-if (isa(Operands[0]) || isa(Operands[1]))
- return PoisonValue::get(Ty);
-
const APInt *C0, *C1;
if (!getConstIntOrUndef(Operands[0], C0) ||
[llvm-branch-commits] [llvm] 7ee2c72 - [AArch64] Mark aarch64_set_fpmr as IntrWriteMem (#146353)
Author: CarolineConcatto
Date: 2025-07-04T08:52:36+01:00
New Revision: 7ee2c72a8e5bbc8abd50f35e805d33006e4b0a4c
URL:
https://github.com/llvm/llvm-project/commit/7ee2c72a8e5bbc8abd50f35e805d33006e4b0a4c
DIFF:
https://github.com/llvm/llvm-project/commit/7ee2c72a8e5bbc8abd50f35e805d33006e4b0a4c.diff
LOG: [AArch64] Mark aarch64_set_fpmr as IntrWriteMem (#146353)
llvm.aarch64.set.fpmr only writes to inaccessible memory. Tag it with
the IntrWriteMem and IntrInaccessibleMemOnly properties so the optimiser
can treat it as a pure write.
The original patch did not add this property, causing the intrinsic to
be conservatively treated as readwrite. This commit fixes that.
Added:
clang/test/CodeGen/AArch64/attr-fp8-function.c
Modified:
llvm/include/llvm/IR/IntrinsicsAArch64.td
Removed:
diff --git a/clang/test/CodeGen/AArch64/attr-fp8-function.c
b/clang/test/CodeGen/AArch64/attr-fp8-function.c
new file mode 100644
index 0..54bfd177bd809
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/attr-fp8-function.c
@@ -0,0 +1,37 @@
+// Check memory attribute for FP8 function
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon
-target-feature +fp8 -target-feature +sve -target-feature +sme -target-feature
+sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -target-feature
+ssve-fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include
+#include
+
+
+// SIMD
+mfloat8x16_t test_vcvtq_mf8_f16_fpm(float16x8_t vn, float16x8_t vm, fpm_t fpm)
{
+ return vcvtq_mf8_f16_fpm(vn, vm, fpm);
+}
+
+// SVE
+svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) __arm_streaming {
+ return svcvtlt2_f16_mf8_fpm(zn, fpm);
+}
+
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR3:#.*]]
+// CHECK: declare
@llvm.aarch64.sve.fp8.cvtlt2.nxv8f16() [[ATTR4:#.*]]
+
+
+// SME
+svfloat32_t test_svmlalltt_lane_f32_mf8(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm) __arm_streaming {
+ return svmlalltt_lane_f32_mf8_fpm(zda, zn, zm, 7, fpm);
+}
+
+// CHECK: declare
@llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32(, , , i32 immarg) [[ATTR4]]
+
+// CHECK: declare <16 x i8> @llvm.aarch64.neon.fp8.fcvtn.v16i8.v8f16(<8 x
half>, <8 x half>) [[ATTR4]]
+
+// CHECK: attributes [[ATTR1:#.*]] = {{{.*}}}
+// CHECK: attributes [[ATTR2:#.*]] = {{{.*}}}
+// CHECK: attributes [[ATTR3]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
+// CHECK: attributes [[ATTR4]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: read) }
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td
b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 3606bbe29eb93..ca6e2128812f7 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -761,7 +761,7 @@ let TargetPrefix = "aarch64" in {
class RNDR_Intrinsic
: DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem,
IntrHasSideEffects]>;
class FPMR_Set_Intrinsic
-: DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrInaccessibleMemOnly]>;
+: DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrWriteMem,
IntrInaccessibleMemOnly]>;
}
// FP environment registers.
___
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[llvm-branch-commits] [flang] d84df61 - [flang] Fix x86 REQUIRES in a couple of tests (#146869)
Author: David Spickett
Date: 2025-07-04T08:43:57+01:00
New Revision: d84df61c001a9983bf445c2c0454edd581571a5f
URL:
https://github.com/llvm/llvm-project/commit/d84df61c001a9983bf445c2c0454edd581571a5f
DIFF:
https://github.com/llvm/llvm-project/commit/d84df61c001a9983bf445c2c0454edd581571a5f.diff
LOG: [flang] Fix x86 REQUIRES in a couple of tests (#146869)
Many tests in Flang are looking for x86_64-registered-target, but this
never exists because the target is just called x86.
These two pass with this corrected but the others I need to look into
why they fail.
Added:
Modified:
flang/test/Lower/Intrinsics/ieee_class_queries.f90
flang/test/Semantics/windows.f90
Removed:
diff --git a/flang/test/Lower/Intrinsics/ieee_class_queries.f90
b/flang/test/Lower/Intrinsics/ieee_class_queries.f90
index aae8071b6a8b5..8d20ff8f3178f 100644
--- a/flang/test/Lower/Intrinsics/ieee_class_queries.f90
+++ b/flang/test/Lower/Intrinsics/ieee_class_queries.f90
@@ -1,5 +1,5 @@
! REQUIRES: flang-supports-f128-math
-! REQUIRES: x86_64-registered-target
+! REQUIRES: x86-registered-target
! RUN: bbc -target x86_64-unknown-linux-gnu -emit-fir -o - %s | FileCheck %s
! CHECK-LABEL: func @_QQmain
diff --git a/flang/test/Semantics/windows.f90
b/flang/test/Semantics/windows.f90
index 705fb1b816895..799a34e6b89c5 100644
--- a/flang/test/Semantics/windows.f90
+++ b/flang/test/Semantics/windows.f90
@@ -1,4 +1,4 @@
-! RUN: %if x86_64-registered-target %{ %python %S/test_errors.py %s %flang
--target=x86_64-pc-windows-msvc -Werror %}
+! RUN: %if x86-registered-target %{ %python %S/test_errors.py %s %flang
--target=x86_64-pc-windows-msvc -Werror %}
! RUN: %if aarch64-registered-target %{ %python %S/test_errors.py %s %flang
--target=aarch64-pc-windows-msvc -Werror %}
subroutine uid
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[llvm-branch-commits] [llvm] f724d31 - [RISCV] Trim line to 80 chars in RISCVInstrInfoXAndes.td. NFC.
Author: Jim Lin
Date: 2025-07-04T14:36:18+08:00
New Revision: f724d31a37ee9d15d91c38b9e2fa7dba81db6155
URL:
https://github.com/llvm/llvm-project/commit/f724d31a37ee9d15d91c38b9e2fa7dba81db6155
DIFF:
https://github.com/llvm/llvm-project/commit/f724d31a37ee9d15d91c38b9e2fa7dba81db6155.diff
LOG: [RISCV] Trim line to 80 chars in RISCVInstrInfoXAndes.td. NFC.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
index 6954a955af6e2..f2a1866510ded 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
@@ -69,7 +69,8 @@ def Log2 : SDNodeXForm
-: RVInst<(outs), (ins GPR:$rs1, uimmlog2xlen:$cimm,
bare_simm11_lsb0:$imm10),
+: RVInst<(outs),
+ (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),
opcodestr, "$rs1, $cimm, $imm10", [], InstFormatNDS_BRANCH_10>,
Sched<[WriteJmp, ReadIALU]> {
bits<10> imm10;
@@ -117,7 +118,8 @@ class NDSRVInstBC funct3, string opcodestr>
}
class NDSRVInstBFO funct3, string opcodestr>
-: RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimmlog2xlen:$msb,
uimmlog2xlen:$lsb),
+: RVInst<(outs GPR:$rd),
+ (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>,
Sched<[WriteIALU, ReadIALU]> {
bits<5> rd;
@@ -409,7 +411,8 @@ multiclass VPseudoVNCVT_BF16_S {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
let VLMul = m.value, SEW=16 in
-def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode,
+def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode,
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX,
16,
forcePassthruRead=true>;
}
@@ -420,8 +423,10 @@ multiclass VPatConversionS_BF16 {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = [HasVendorXAndesVBFHCvt] in
-def : VPatUnaryNoMask;
+def : VPatUnaryNoMask;
}
}
@@ -430,8 +435,10 @@ multiclass VPatConversionBF16_S {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = [HasVendorXAndesVBFHCvt] in
-def : VPatUnaryNoMaskRoundingMode;
+def : VPatUnaryNoMaskRoundingMode;
}
}
@@ -451,7 +458,8 @@ multiclass VPatVFPMADBinaryV_VX_RM vtilist> {
foreach vti = vtilist in {
defvar kind = "V"#vti.ScalarSuffix;
-defm : VPatBinaryRoundingMode;
@@ -639,8 +647,10 @@ defm PseudoNDS_VFWCVT_S_BF16 : VPseudoVWCVT_S_BF16;
defm PseudoNDS_VFNCVT_BF16_S : VPseudoVNCVT_BF16_S;
} // Predicates = [HasVendorXAndesVBFHCvt]
-defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16",
"PseudoNDS_VFWCVT_S">;
-defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s",
"PseudoNDS_VFNCVT_BF16">;
+defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16",
+"PseudoNDS_VFWCVT_S">;
+defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s",
+"PseudoNDS_VFNCVT_BF16">;
let Predicates = [HasVendorXAndesVPackFPH],
mayRaiseFPException = true in {
@@ -648,8 +658,10 @@ defm PseudoNDS_VFPMADT : VPseudoVFPMAD_VF_RM;
defm PseudoNDS_VFPMADB : VPseudoVFPMAD_VF_RM;
} // Predicates = [HasVendorXAndesVPackFPH]
-defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT",
AllFP16Vectors>;
-defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB",
AllFP16Vectors>;
+defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT",
+ AllFP16Vectors>;
+defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB",
+ AllFP16Vectors>;
let Predicates = [HasVendorXAndesVDot] in {
defm PseudoNDS_VD4DOTS : VPseudoVD4DOT_VV;
@@ -669,9 +681,12 @@ defset list AllQuadWidenableVD4DOTVectors
= {
def : VTypeInfoToWide;
}
-defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS",
AllQuadWidenableVD4DOTVectors>;
-defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU",
AllQuadWidenableVD4DOTVectors>;
-defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU",
AllQuadWidenableVD4DOTVectors>;
+defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS",
+AllQuadWidenableVD4DOTVectors>;
+defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU",
+AllQuadWidenableVD4DOTVectors>;
+defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU",
+AllQuadWidenableVD4DOTVectors>;
//===--===//
// Pseudo-instructions for SFB (Short Forward Branch)
@@ -6
[llvm-branch-commits] [mlir] 25bf90e - [MLIR][Docs] Fix typo in addTypeAttributeConversion comment (#146977)
Author: Xiaomin Liu
Date: 2025-07-04T09:14:51+02:00
New Revision: 25bf90eaede41156e45f974c772e320758cbb3c8
URL:
https://github.com/llvm/llvm-project/commit/25bf90eaede41156e45f974c772e320758cbb3c8
DIFF:
https://github.com/llvm/llvm-project/commit/25bf90eaede41156e45f974c772e320758cbb3c8.diff
LOG: [MLIR][Docs] Fix typo in addTypeAttributeConversion comment (#146977)
Typo in
```
This result can either contan an `Attribute`,
```
to
```
This result can either contain an `Attribute`,
```
rest is clang-format
Signed-off-by: Xiaomin Liu
Added:
Modified:
mlir/include/mlir/Transforms/DialectConversion.h
Removed:
diff --git a/mlir/include/mlir/Transforms/DialectConversion.h
b/mlir/include/mlir/Transforms/DialectConversion.h
index 81858812d2623..f6437657c9a93 100644
--- a/mlir/include/mlir/Transforms/DialectConversion.h
+++ b/mlir/include/mlir/Transforms/DialectConversion.h
@@ -221,12 +221,13 @@ class TypeConverter {
///
/// The conversion functions take a non-null Type or subclass of Type and a
/// non-null Attribute (or subclass of Attribute), and returns a
- /// `AttributeConversionResult`. This result can either contan an
`Attribute`,
- /// which may be `nullptr`, representing the conversion's success,
- /// `AttributeConversionResult::na()` (the default empty value), indicating
- /// that the conversion function did not apply and that further conversion
- /// functions should be checked, or `AttributeConversionResult::abort()`
- /// indicating that the conversion process should be aborted.
+ /// `AttributeConversionResult`. This result can either contain an
+ /// `Attribute`, which may be `nullptr`, representing the conversion's
+ /// success, `AttributeConversionResult::na()` (the default empty value),
+ /// indicating that the conversion function did not apply and that further
+ /// conversion functions should be checked, or
+ /// `AttributeConversionResult::abort()` indicating that the conversion
+ /// process should be aborted.
///
/// Registered conversion functions are callled in the reverse of the order
in
/// which they were registered.
___
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[llvm-branch-commits] [llvm] 7e3e2e1 - MCParser: Add SMLoc to expressions
Author: Fangrui Song
Date: 2025-07-04T00:58:07-07:00
New Revision: 7e3e2e1b8c6ff21e68782a56164139cca334fcf3
URL:
https://github.com/llvm/llvm-project/commit/7e3e2e1b8c6ff21e68782a56164139cca334fcf3
DIFF:
https://github.com/llvm/llvm-project/commit/7e3e2e1b8c6ff21e68782a56164139cca334fcf3.diff
LOG: MCParser: Add SMLoc to expressions
The information will be used when we change MCFixup::getLoc to use the
MCExpr location, making MCFixup smaller.
Added:
Modified:
llvm/include/llvm/MC/MCExpr.h
llvm/lib/MC/ConstantPools.cpp
llvm/lib/MC/MCParser/AsmParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Removed:
diff --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h
index b3585693afa02..e460c95ea4dff 100644
--- a/llvm/include/llvm/MC/MCExpr.h
+++ b/llvm/include/llvm/MC/MCExpr.h
@@ -341,8 +341,8 @@ class MCBinaryExpr : public MCExpr {
SMLoc Loc = SMLoc());
static const MCBinaryExpr *createAdd(const MCExpr *LHS, const MCExpr *RHS,
- MCContext &Ctx) {
-return create(Add, LHS, RHS, Ctx);
+ MCContext &Ctx, SMLoc Loc = SMLoc()) {
+return create(Add, LHS, RHS, Ctx, Loc);
}
static const MCBinaryExpr *createAnd(const MCExpr *LHS, const MCExpr *RHS,
diff --git a/llvm/lib/MC/ConstantPools.cpp b/llvm/lib/MC/ConstantPools.cpp
index 824d2463f30fc..bf74ad42f91fd 100644
--- a/llvm/lib/MC/ConstantPools.cpp
+++ b/llvm/lib/MC/ConstantPools.cpp
@@ -59,7 +59,7 @@ const MCExpr *ConstantPool::addEntry(const MCExpr *Value,
MCContext &Context,
MCSymbol *CPEntryLabel = Context.createTempSymbol();
Entries.push_back(ConstantPoolEntry(CPEntryLabel, Value, Size, Loc));
- const auto SymRef = MCSymbolRefExpr::create(CPEntryLabel, Context);
+ const auto SymRef = MCSymbolRefExpr::create(CPEntryLabel, Context, Loc);
if (C)
CachedConstantEntries[std::make_pair(C->getValue(), Size)] = SymRef;
if (S)
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp
b/llvm/lib/MC/MCParser/AsmParser.cpp
index 91914d0cb3746..05771a5797635 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -1268,7 +1268,7 @@ bool AsmParser::parsePrimaryExpr(const MCExpr *&Res,
SMLoc &EndLoc,
if (IDVal == "f" || IDVal == "b") {
MCSymbol *Sym =
Ctx.getDirectionalLocalSymbol(IntVal, IDVal == "b");
-Res = MCSymbolRefExpr::create(Sym, Spec, getContext());
+Res = MCSymbolRefExpr::create(Sym, Spec, getContext(), Loc);
if (IDVal == "b" && Sym->isUndefined())
return Error(Loc, "directional label undefined");
DirLabels.push_back(std::make_tuple(Loc, CppHashInfo, Sym));
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index e989892b9e056..2ccae27f87a33 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3299,7 +3299,8 @@ ParseStatus
AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
if (DarwinSpec == AArch64::S_None && ELFSpec == AArch64::S_INVALID) {
// No modifier was specified at all; this is the syntax for an ELF basic
// ADRP relocation (unfortunately).
- Expr = MCSpecifierExpr::create(Expr, AArch64::S_ABS_PAGE, getContext());
+ Expr =
+ MCSpecifierExpr::create(Expr, AArch64::S_ABS_PAGE, getContext(), S);
} else if ((DarwinSpec == AArch64::S_MACHO_GOTPAGE ||
DarwinSpec == AArch64::S_MACHO_TLVPPAGE) &&
Addend != 0) {
@@ -3351,7 +3352,7 @@ ParseStatus
AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
if (DarwinSpec == AArch64::S_None && ELFSpec == AArch64::S_INVALID) {
// No modifier was specified at all; this is the syntax for an ELF basic
// ADR relocation (unfortunately).
- Expr = MCSpecifierExpr::create(Expr, AArch64::S_ABS, getContext());
+ Expr = MCSpecifierExpr::create(Expr, AArch64::S_ABS, getContext(), S);
} else if (ELFSpec != AArch64::S_GOT_AUTH_PAGE) {
// For tiny code model, we use :got_auth: operator to fill 21-bit imm of
// adr. It's not actually GOT entry page address but the GOT address
@@ -4394,7 +4395,7 @@ bool AArch64AsmParser::parseRegister(OperandVector
&Operands) {
bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
bool HasELFModifier = false;
AArch64::Specifier RefKind;
-
+ SMLoc Loc = getLexer().getLoc();
if (parseOptionalToken(AsmToken::Colon)) {
HasELFModifier = true;
@@ -4468,7 +4469,7 @@ bool AArch64AsmParser::parseSymbolicI
[llvm-branch-commits] [flang] 3e78aff - [flang] Fix Windows bot failure caused by #146667 (#147002)
Author: Kareem Ergawy
Date: 2025-07-04T08:41:29+01:00
New Revision: 3e78afff0d8e3d982e4bcdaad623cbb12dff01d8
URL:
https://github.com/llvm/llvm-project/commit/3e78afff0d8e3d982e4bcdaad623cbb12dff01d8
DIFF:
https://github.com/llvm/llvm-project/commit/3e78afff0d8e3d982e4bcdaad623cbb12dff01d8.diff
LOG: [flang] Fix Windows bot failure caused by #146667 (#147002)
Fixes a Windows bot failure caused by #146667. Just run the test if an
AMD GPU target is registered. Hopefully, the bot now passes.
Test coverage is not reduced since `bbc` is still run on all platforms.
Added:
Modified:
flang/test/Lower/OpenMP/parallel-reduction-array.f90
Removed:
diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array.f90
b/flang/test/Lower/OpenMP/parallel-reduction-array.f90
index 4f889d9a4e77f..d410714b1573e 100644
--- a/flang/test/Lower/OpenMP/parallel-reduction-array.f90
+++ b/flang/test/Lower/OpenMP/parallel-reduction-array.f90
@@ -2,7 +2,8 @@
! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s
--check-prefix=CPU
! RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device -fopenmp-is-gpu -o -
%s 2>&1 | FileCheck %s --check-prefix=GPU
-! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp
-fopenmp-is-target-device -o - %s 2>&1 | FileCheck %s --check-prefix=GPU
+! RUN: %if amdgpu-registered-target %{ %flang_fc1 -triple amdgcn-amd-amdhsa
-emit-hlfir -fopenmp -fopenmp-is-target-device -o - %s 2>&1 | \
+! RUN: FileCheck %s --check-prefix=GPU %}
program reduce
integer, dimension(3) :: i = 0
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[llvm-branch-commits] [llvm] AArch64: Fix some missing llvm.frexp test coverage (PR #146691)
arsenm wrote: ### Merge activity * **Jul 7, 1:05 AM UTC**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/146691). https://github.com/llvm/llvm-project/pull/146691 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Triple: Record default exception handling type (PR #147225)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/147225
Currently the default exception handling type is scattered
across the backends in MCAsmInfo constructors. Allow this
to be computed from the triple so the IR can centrally determine
the set of ABI calls.
>From 0c8cc6152ce45e8dc851e902dbb95cb597175462 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 30 Jun 2025 14:20:39 +0900
Subject: [PATCH] Triple: Record default exception handling type
Currently the default exception handling type is scattered
across the backends in MCAsmInfo constructors. Allow this
to be computed from the triple so the IR can centrally determine
the set of ABI calls.
---
llvm/include/llvm/TargetParser/Triple.h | 3 +
llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp | 4 +
llvm/lib/TargetParser/Triple.cpp | 50 ++
llvm/unittests/TargetParser/TripleTest.cpp| 146 ++
4 files changed, 203 insertions(+)
diff --git a/llvm/include/llvm/TargetParser/Triple.h
b/llvm/include/llvm/TargetParser/Triple.h
index cbf85b2ff74f5..657f4230379e8 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -20,6 +20,7 @@
#undef sparc
namespace llvm {
+enum class ExceptionHandling;
class Twine;
/// Triple - Helper class for working with autoconf configuration names. For
@@ -1321,6 +1322,8 @@ class Triple {
/// Returns whether an OS version is invalid and would not map to an Apple
OS.
LLVM_ABI static bool isValidVersionForOS(OSType OSKind,
const VersionTuple &Version);
+
+ LLVM_ABI ExceptionHandling getDefaultExceptionHandling() const;
};
} // End llvm namespace
diff --git a/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
b/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
index 125ffd597bf23..e54419758410a 100644
--- a/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
+++ b/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
@@ -80,6 +80,10 @@ void CodeGenTargetMachineImpl::initAsmInfo() {
TmpAsmInfo->setFullRegisterNames(Options.MCOptions.PPCUseFullRegisterNames);
+ assert(TmpAsmInfo->getExceptionHandlingType() ==
+ getTargetTriple().getDefaultExceptionHandling() &&
+ "MCAsmInfo and Triple disagree on default exception handling type");
+
if (Options.ExceptionModel != ExceptionHandling::None)
TmpAsmInfo->setExceptionsType(Options.ExceptionModel);
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index a348640d75f26..45ef8c1329759 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -11,6 +11,7 @@
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SwapByteOrder.h"
#include "llvm/Support/VersionTuple.h"
@@ -2255,6 +2256,55 @@ bool Triple::isValidVersionForOS(OSType OSKind, const
VersionTuple &Version) {
llvm_unreachable("unexpected or invalid os version");
}
+ExceptionHandling Triple::getDefaultExceptionHandling() const {
+ if (isOSBinFormatCOFF()) {
+if (getArch() == Triple::x86 &&
+(isOSCygMing() || isWindowsItaniumEnvironment()))
+ return ExceptionHandling::DwarfCFI;
+return ExceptionHandling::WinEH;
+ }
+
+ if (isOSBinFormatXCOFF())
+return ExceptionHandling::AIX;
+ if (isOSBinFormatGOFF())
+return ExceptionHandling::ZOS;
+
+ if (isARM() || isThumb()) {
+if (isOSBinFormatELF()) {
+ return getOS() == Triple::NetBSD ? ExceptionHandling::DwarfCFI
+ : ExceptionHandling::ARM;
+}
+
+return isOSDarwin() && !isWatchABI() ? ExceptionHandling::SjLj
+ : ExceptionHandling::DwarfCFI;
+ }
+
+ if (isAArch64() || isX86() || isPPC() || isMIPS() || isSPARC() || isBPF() ||
+ isRISCV() || isLoongArch())
+return ExceptionHandling::DwarfCFI;
+
+ switch (getArch()) {
+ case Triple::arc:
+ case Triple::csky:
+ case Triple::hexagon:
+ case Triple::lanai:
+ case Triple::msp430:
+ case Triple::systemz:
+ case Triple::xcore:
+ case Triple::xtensa:
+return ExceptionHandling::DwarfCFI;
+ default:
+break;
+ }
+
+ // Explicitly none targets.
+ if (isWasm() || isAMDGPU() || isNVPTX() || isSPIROrSPIRV())
+return ExceptionHandling::None;
+
+ // Default to none.
+ return ExceptionHandling::None;
+}
+
// HLSL triple environment orders are relied on in the front end
static_assert(Triple::Vertex - Triple::Pixel == 1,
"incorrect HLSL stage order");
diff --git a/llvm/unittests/TargetParser/TripleTest.cpp
b/llvm/unittests/TargetParser/TripleTest.cpp
index 4d547011c1568..4fa7438e5cfc6 100644
--- a/llvm/unittests/TargetParser/TripleTest.cpp
+++ b/llvm/unittests/TargetParser/TripleTest.cpp
@@ -7,6 +7,7 @@
//===---
[llvm-branch-commits] [llvm] ARM: Move sjlj libcall configuration to RuntimeLibcalls (PR #147227)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/147227
None
>From 1ea9863111f0335dbf31d0bdc862f857eddfe18b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Jul 2025 17:29:40 +0900
Subject: [PATCH] ARM: Move sjlj libcall configuration to RuntimeLibcalls
---
llvm/lib/IR/RuntimeLibcalls.cpp | 2 +-
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 712f1a48d0b7b..070131aead46b 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -362,7 +362,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
if (TT.isX86() && TT.isGNUEnvironment())
setLongDoubleIsF128Libm(*this, /*FiniteOnlyFuncs=*/true);
- if (TT.isX86() || TT.isVE()) {
+ if (TT.isX86() || TT.isVE() || TT.isARM() || TT.isThumb()) {
if (ExceptionModel == ExceptionHandling::SjLj)
setLibcallImpl(RTLIB::UNWIND_RESUME, RTLIB::_Unwind_SjLj_Resume);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 6be41a01e0696..a487654d7cad8 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1400,8 +1400,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
- if (Subtarget->useSjLjEH())
-setLibcallImpl(RTLIB::UNWIND_RESUME, RTLIB::_Unwind_SjLj_Resume);
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Expand);
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[llvm-branch-commits] [llvm] Triple: Record default exception handling type (PR #147225)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/147225 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Remove subtarget field tracking SjLj (PR #147226)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/147226
This is a module level property that needs to be globally
consistent, so it does not belong in the subtarget.
Now that the Triple knows the default exception handling type,
consolidate the interpretation of None as select target default
exception handling in TargetMachine and use that. This enables
moving the configuration of UNWIND_RESUME to RuntimeLibcalls.
>From 788fc0fae471dc2d7c8b8dcf57aea7cc54ab59d5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Jul 2025 17:13:55 +0900
Subject: [PATCH] ARM: Remove subtarget field tracking SjLj
This is a module level property that needs to be globally
consistent, so it does not belong in the subtarget.
Now that the Triple knows the default exception handling type,
consolidate the interpretation of None as select target default
exception handling in TargetMachine and use that. This enables
moving the configuration of UNWIND_RESUME to RuntimeLibcalls.
---
llvm/include/llvm/Target/TargetMachine.h | 9 +
llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 --
llvm/lib/Target/ARM/ARMSubtarget.cpp | 14 --
llvm/lib/Target/ARM/ARMSubtarget.h | 5 -
4 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetMachine.h
b/llvm/include/llvm/Target/TargetMachine.h
index 7a37eb7391b31..bf4e490554723 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -243,6 +243,15 @@ class LLVM_ABI TargetMachine {
const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
+ /// Return the ExceptionHandling to use, considering TargetOptions and the
+ /// Triple's default.
+ ExceptionHandling getExceptionModel() const {
+// FIXME: This interface fails to distinguish default from not supported.
+return Options.ExceptionModel == ExceptionHandling::None
+ ? TargetTriple.getDefaultExceptionHandling()
+ : Options.ExceptionModel;
+ }
+
bool requiresStructuredCFG() const { return RequireStructuredCFG; }
void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2d73725291d11..6be41a01e0696 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -21959,14 +21959,16 @@ Register
ARMTargetLowering::getExceptionPointerRegister(
const Constant *PersonalityFn) const {
// Platforms which do not use SjLj EH may return values in these registers
// via the personality function.
- return Subtarget->useSjLjEH() ? Register() : ARM::R0;
+ ExceptionHandling EM = getTargetMachine().getExceptionModel();
+ return EM == ExceptionHandling::SjLj ? Register() : ARM::R0;
}
Register ARMTargetLowering::getExceptionSelectorRegister(
const Constant *PersonalityFn) const {
// Platforms which do not use SjLj EH may return values in these registers
// via the personality function.
- return Subtarget->useSjLjEH() ? Register() : ARM::R1;
+ ExceptionHandling EM = getTargetMachine().getExceptionModel();
+ return EM == ExceptionHandling::SjLj ? Register() : ARM::R1;
}
void ARMTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp
b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index abca4bb947bc4..13185a7d797a3 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -72,7 +72,6 @@ ForceFastISel("arm-force-fast-isel",
/// so that we can use initializer lists for subtarget initialization.
ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
- initializeEnvironment();
initSubtargetFeatures(CPU, FS);
return *this;
}
@@ -137,19 +136,6 @@ bool ARMSubtarget::isXRaySupported() const {
return hasV6Ops() && hasARMOps() && !isTargetWindows();
}
-void ARMSubtarget::initializeEnvironment() {
- // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
- // directly from it, but we can try to make sure they're consistent when both
- // available.
- UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
- Options.ExceptionModel == ExceptionHandling::None) ||
- Options.ExceptionModel == ExceptionHandling::SjLj;
- assert((!TM.getMCAsmInfo() ||
- (TM.getMCAsmInfo()->getExceptionHandlingType() ==
- ExceptionHandling::SjLj) == UseSjLjEH) &&
- "inconsistent sjlj choice between CodeGen and MC");
-}
-
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (CPUString.empty()) {
CPUString = "generic";
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h
b/llvm/lib/Target/ARM/ARMSubtarget.h
index 3e131434956
[llvm-branch-commits] [llvm] Triple: Record default exception handling type (PR #147225)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147225?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#147227** https://app.graphite.dev/github/pr/llvm/llvm-project/147227?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#147226** https://app.graphite.dev/github/pr/llvm/llvm-project/147226?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#147225** https://app.graphite.dev/github/pr/llvm/llvm-project/147225?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/147225?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#147224** https://app.graphite.dev/github/pr/llvm/llvm-project/147224?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/147225 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Remove subtarget field tracking SjLj (PR #147226)
llvmbot wrote:
@llvm/pr-subscribers-backend-arm
Author: Matt Arsenault (arsenm)
Changes
This is a module level property that needs to be globally
consistent, so it does not belong in the subtarget.
Now that the Triple knows the default exception handling type,
consolidate the interpretation of None as select target default
exception handling in TargetMachine and use that. This enables
moving the configuration of UNWIND_RESUME to RuntimeLibcalls.
---
Full diff: https://github.com/llvm/llvm-project/pull/147226.diff
4 Files Affected:
- (modified) llvm/include/llvm/Target/TargetMachine.h (+9)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+4-2)
- (modified) llvm/lib/Target/ARM/ARMSubtarget.cpp (-14)
- (modified) llvm/lib/Target/ARM/ARMSubtarget.h (-5)
``diff
diff --git a/llvm/include/llvm/Target/TargetMachine.h
b/llvm/include/llvm/Target/TargetMachine.h
index 7a37eb7391b31..bf4e490554723 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -243,6 +243,15 @@ class LLVM_ABI TargetMachine {
const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
+ /// Return the ExceptionHandling to use, considering TargetOptions and the
+ /// Triple's default.
+ ExceptionHandling getExceptionModel() const {
+// FIXME: This interface fails to distinguish default from not supported.
+return Options.ExceptionModel == ExceptionHandling::None
+ ? TargetTriple.getDefaultExceptionHandling()
+ : Options.ExceptionModel;
+ }
+
bool requiresStructuredCFG() const { return RequireStructuredCFG; }
void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2d73725291d11..6be41a01e0696 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -21959,14 +21959,16 @@ Register
ARMTargetLowering::getExceptionPointerRegister(
const Constant *PersonalityFn) const {
// Platforms which do not use SjLj EH may return values in these registers
// via the personality function.
- return Subtarget->useSjLjEH() ? Register() : ARM::R0;
+ ExceptionHandling EM = getTargetMachine().getExceptionModel();
+ return EM == ExceptionHandling::SjLj ? Register() : ARM::R0;
}
Register ARMTargetLowering::getExceptionSelectorRegister(
const Constant *PersonalityFn) const {
// Platforms which do not use SjLj EH may return values in these registers
// via the personality function.
- return Subtarget->useSjLjEH() ? Register() : ARM::R1;
+ ExceptionHandling EM = getTargetMachine().getExceptionModel();
+ return EM == ExceptionHandling::SjLj ? Register() : ARM::R1;
}
void ARMTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp
b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index abca4bb947bc4..13185a7d797a3 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -72,7 +72,6 @@ ForceFastISel("arm-force-fast-isel",
/// so that we can use initializer lists for subtarget initialization.
ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
- initializeEnvironment();
initSubtargetFeatures(CPU, FS);
return *this;
}
@@ -137,19 +136,6 @@ bool ARMSubtarget::isXRaySupported() const {
return hasV6Ops() && hasARMOps() && !isTargetWindows();
}
-void ARMSubtarget::initializeEnvironment() {
- // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
- // directly from it, but we can try to make sure they're consistent when both
- // available.
- UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
- Options.ExceptionModel == ExceptionHandling::None) ||
- Options.ExceptionModel == ExceptionHandling::SjLj;
- assert((!TM.getMCAsmInfo() ||
- (TM.getMCAsmInfo()->getExceptionHandlingType() ==
- ExceptionHandling::SjLj) == UseSjLjEH) &&
- "inconsistent sjlj choice between CodeGen and MC");
-}
-
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (CPUString.empty()) {
CPUString = "generic";
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h
b/llvm/lib/Target/ARM/ARMSubtarget.h
index 3e1314349564c..beb1ff6447148 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -151,9 +151,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
/// blocks.
bool RestrictIT = false;
- /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
- bool UseSjLjEH = false;
-
/// stackAlignment - The minimum alignment known to hold of the stack frame
on
/// entry to the function and which must be maintained by every funct
[llvm-branch-commits] [llvm] ARM: Remove subtarget field tracking SjLj (PR #147226)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147226?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#147227** https://app.graphite.dev/github/pr/llvm/llvm-project/147227?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#147226** https://app.graphite.dev/github/pr/llvm/llvm-project/147226?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/147226?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#147225** https://app.graphite.dev/github/pr/llvm/llvm-project/147225?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#147224** https://app.graphite.dev/github/pr/llvm/llvm-project/147224?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/147226 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Move sjlj libcall configuration to RuntimeLibcalls (PR #147227)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147227?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#147227** https://app.graphite.dev/github/pr/llvm/llvm-project/147227?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/147227?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#147226** https://app.graphite.dev/github/pr/llvm/llvm-project/147226?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#147225** https://app.graphite.dev/github/pr/llvm/llvm-project/147225?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#147224** https://app.graphite.dev/github/pr/llvm/llvm-project/147224?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/147227 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Remove subtarget field tracking SjLj (PR #147226)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/147226 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Move sjlj libcall configuration to RuntimeLibcalls (PR #147227)
llvmbot wrote:
@llvm/pr-subscribers-backend-arm
Author: Matt Arsenault (arsenm)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/147227.diff
2 Files Affected:
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (-2)
``diff
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 712f1a48d0b7b..070131aead46b 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -362,7 +362,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
if (TT.isX86() && TT.isGNUEnvironment())
setLongDoubleIsF128Libm(*this, /*FiniteOnlyFuncs=*/true);
- if (TT.isX86() || TT.isVE()) {
+ if (TT.isX86() || TT.isVE() || TT.isARM() || TT.isThumb()) {
if (ExceptionModel == ExceptionHandling::SjLj)
setLibcallImpl(RTLIB::UNWIND_RESUME, RTLIB::_Unwind_SjLj_Resume);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 6be41a01e0696..a487654d7cad8 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1400,8 +1400,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
- if (Subtarget->useSjLjEH())
-setLibcallImpl(RTLIB::UNWIND_RESUME, RTLIB::_Unwind_SjLj_Resume);
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Expand);
``
https://github.com/llvm/llvm-project/pull/147227
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[llvm-branch-commits] [llvm] ARM: Move sjlj libcall configuration to RuntimeLibcalls (PR #147227)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/147227 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Move sjlj libcall configuration to RuntimeLibcalls (PR #147227)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/147227 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64] Ensure the LR is preserved if we must call __arm_get_current_vg (#145760) (PR #147171)
https://github.com/efriedma-quic approved this pull request. LGTM (Not sure if we're still doing point releases?) https://github.com/llvm/llvm-project/pull/147171 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64] Ensure the LR is preserved if we must call __arm_get_current_vg (#145760) (PR #147171)
MacDue wrote: There's going to be a 20.1.8 https://discourse.llvm.org/t/llvm-20-1-8-plans/87207 https://github.com/llvm/llvm-project/pull/147171 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)
https://github.com/clementval approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/146033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Instrumentor] Allow printing a runtime stub (PR #138978)
https://github.com/kevinsala updated
https://github.com/llvm/llvm-project/pull/138978
>From 371483a750a456459d054a56787b40e946ab2890 Mon Sep 17 00:00:00 2001
From: Kevin Sala
Date: Tue, 6 May 2025 22:48:41 -0700
Subject: [PATCH] [Instrumentor] Allow printing a runtime stub
---
.../llvm/Transforms/IPO/Instrumentor.h| 16 ++
.../Transforms/IPO/InstrumentorStubPrinter.h | 32 +++
llvm/lib/Transforms/IPO/CMakeLists.txt| 1 +
llvm/lib/Transforms/IPO/Instrumentor.cpp | 3 +
.../IPO/InstrumentorStubPrinter.cpp | 210 ++
.../Instrumentor/bad_rt_config.json | 105 +
.../Instrumentor/default_config.json | 2 +
.../Instrumentation/Instrumentor/default_rt | 37 +++
.../Instrumentor/generate_bad_rt.ll | 3 +
.../Instrumentor/generate_rt.ll | 2 +
.../Instrumentor/load_store_config.json | 2 +-
.../load_store_noreplace_config.json | 2 +-
.../Instrumentor/rt_config.json | 105 +
13 files changed, 518 insertions(+), 2 deletions(-)
create mode 100644 llvm/include/llvm/Transforms/IPO/InstrumentorStubPrinter.h
create mode 100644 llvm/lib/Transforms/IPO/InstrumentorStubPrinter.cpp
create mode 100644 llvm/test/Instrumentation/Instrumentor/bad_rt_config.json
create mode 100644 llvm/test/Instrumentation/Instrumentor/default_rt
create mode 100644 llvm/test/Instrumentation/Instrumentor/generate_bad_rt.ll
create mode 100644 llvm/test/Instrumentation/Instrumentor/generate_rt.ll
create mode 100644 llvm/test/Instrumentation/Instrumentor/rt_config.json
diff --git a/llvm/include/llvm/Transforms/IPO/Instrumentor.h
b/llvm/include/llvm/Transforms/IPO/Instrumentor.h
index 26445d221d00f..e6d5f717072a2 100644
--- a/llvm/include/llvm/Transforms/IPO/Instrumentor.h
+++ b/llvm/include/llvm/Transforms/IPO/Instrumentor.h
@@ -116,6 +116,18 @@ struct IRTCallDescription {
InstrumentorIRBuilderTy &IIRB, const DataLayout &DL,
InstrumentationCaches &ICaches);
+ /// Create a string representation of the function declaration in C. Two
+ /// strings are returned: the function definition with direct arguments and
+ /// the function with any indirect argument.
+ std::pair
+ createCSignature(const InstrumentationConfig &IConf) const;
+
+ /// Create a string representation of the function definition in C. The
+ /// function body implements a stub and only prints the passed arguments. Two
+ /// strings are returned: the function definition with direct arguments and
+ /// the function with any indirect argument.
+ std::pair createCBodies() const;
+
/// Return whether the \p IRTA argument can be replaced.
bool isReplacable(IRTArg &IRTA) const {
return (IRTA.Flags & (IRTArg::REPLACABLE | IRTArg::REPLACABLE_CUSTOM));
@@ -334,6 +346,9 @@ struct InstrumentationConfig {
InstrumentationConfig() : SS(StringAllocator) {
RuntimePrefix = BaseConfigurationOption::getStringOption(
*this, "runtime_prefix", "The runtime API prefix.", "__instrumentor_");
+RuntimeStubsFile = BaseConfigurationOption::getStringOption(
+*this, "runtime_stubs_file",
+"The file into which runtime stubs should be written.", "");
TargetRegex = BaseConfigurationOption::getStringOption(
*this, "target_regex",
"Regular expression to be matched against the module target. "
@@ -380,6 +395,7 @@ struct InstrumentationConfig {
/// The base configuration options.
BaseConfigurationOption *RuntimePrefix;
+ BaseConfigurationOption *RuntimeStubsFile;
BaseConfigurationOption *TargetRegex;
BaseConfigurationOption *HostEnabled;
BaseConfigurationOption *GPUEnabled;
diff --git a/llvm/include/llvm/Transforms/IPO/InstrumentorStubPrinter.h
b/llvm/include/llvm/Transforms/IPO/InstrumentorStubPrinter.h
new file mode 100644
index 0..6e1e24d5fef9e
--- /dev/null
+++ b/llvm/include/llvm/Transforms/IPO/InstrumentorStubPrinter.h
@@ -0,0 +1,32 @@
+//===- Transforms/IPO/InstrumentorStubPrinter.h
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// A generator of Instrumentor's runtime stubs.
+//
+//===--===//
+
+#ifndef LLVM_TRANSFORMS_IPO_INSTRUMENTOR_STUB_PRINTER_H
+#define LLVM_TRANSFORMS_IPO_INSTRUMENTOR_STUB_PRINTER_H
+
+#include "llvm/ADT/StringRef.h"
+#include "llvm/IR/Module.h"
+#include "llvm/Transforms/IPO/Instrumentor.h"
+
+namespace llvm {
+namespace instrumentor {
+
+/// Print a runtime stub file with the implementation of the instrumentation
+/// runtime functions corresponding to the instrumentation opportunities
+/// enabled.
+void printRu
[llvm-branch-commits] [llvm] [Instrumentor] Allow printing a runtime stub (PR #138978)
@@ -0,0 +1,212 @@
+//===-- InstrumentorStubPrinter.cpp
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+//===--===//
+
+#include "llvm/Transforms/IPO/Instrumentor.h"
+
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/IR/DiagnosticInfo.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/Support/raw_ostream.h"
+
+#include
+#include
+#include
+
+namespace llvm {
+namespace instrumentor {
+
+/// Get the string representation of an argument with type \p Ty. Two strings
+/// are returned: one for direct arguments and another for indirect arguments.
+/// The flags in \p Flags describe the properties of the argument. See
+/// IRTArg::IRArgFlagTy.
+static std::pair getAsCType(Type *Ty,
+ unsigned Flags) {
+ if (Ty->isIntegerTy()) {
+auto BW = Ty->getIntegerBitWidth();
+if (BW == 1)
+ return {"bool ", "bool *"};
+auto S = "int" + std::to_string(BW) + "_t ";
+return {S, S + "*"};
+ }
+ if (Ty->isPointerTy())
+return {Flags & IRTArg::STRING ? "char *" : "void *", "void **"};
+ if (Ty->isFloatTy())
+return {"float ", "float *"};
+ if (Ty->isDoubleTy())
+return {"double ", "double *"};
+ return {"<>", "<>"};
+}
+
+/// Get the string representation of the C printf format of an argument with
+/// type \p Ty. The flags in \p Flags describe the properties of the argument.
+/// See IRTArg::IRArgFlagTy.
+static std::string getPrintfFormatString(Type *Ty, unsigned Flags) {
+ if (Ty->isIntegerTy()) {
+if (Ty->getIntegerBitWidth() > 32) {
+ assert(Ty->getIntegerBitWidth() == 64);
+ return "%lli";
+}
+return "%i";
+ }
+ if (Ty->isPointerTy())
+return Flags & IRTArg::STRING ? "%s" : "%p";
+ if (Ty->isFloatTy())
+return "%f";
+ if (Ty->isDoubleTy())
+return "%lf";
+ return "<>";
+}
+
+std::pair IRTCallDescription::createCBodies() const {
+ std::string DirectFormat = "printf(\"" + IO.getName().str() +
+ (IO.IP.isPRE() ? " pre" : " post") + " -- ";
+ std::string IndirectFormat = DirectFormat;
+ std::string DirectArg, IndirectArg, DirectReturnValue, IndirectReturnValue;
+
+ auto AddToFormats = [&](Twine S) {
+DirectFormat += S.str();
+IndirectFormat += S.str();
+ };
+ auto AddToArgs = [&](Twine S) {
+DirectArg += S.str();
+IndirectArg += S.str();
+ };
+ bool First = true;
+ for (auto &IRArg : IO.IRTArgs) {
+if (!IRArg.Enabled)
+ continue;
+if (!First)
+ AddToFormats(", ");
+First = false;
+AddToArgs(", " + IRArg.Name);
+AddToFormats(IRArg.Name + ": ");
+if (NumReplaceableArgs == 1 && (IRArg.Flags & IRTArg::REPLACABLE)) {
+ DirectReturnValue = IRArg.Name;
+ if (!isPotentiallyIndirect(IRArg))
+IndirectReturnValue = IRArg.Name;
+}
+if (!isPotentiallyIndirect(IRArg)) {
+ AddToFormats(getPrintfFormatString(IRArg.Ty, IRArg.Flags));
+} else {
+ DirectFormat += getPrintfFormatString(IRArg.Ty, IRArg.Flags);
+ IndirectFormat += "%p";
+ IndirectArg += "_ptr";
+ // Add the indirect argument size
+ if (!(IRArg.Flags & IRTArg::INDIRECT_HAS_SIZE)) {
+IndirectFormat += ", " + IRArg.Name.str() + "_size: %i";
+IndirectArg += ", " + IRArg.Name.str() + "_size";
+ }
+}
+ }
+
+ std::string DirectBody = DirectFormat + "\\n\"" + DirectArg + ");\n";
+ std::string IndirectBody = IndirectFormat + "\\n\"" + IndirectArg + ");\n";
+ if (RetTy)
+IndirectReturnValue = DirectReturnValue = "0";
+ if (!DirectReturnValue.empty())
+DirectBody += " return " + DirectReturnValue + ";\n";
+ if (!IndirectReturnValue.empty())
+IndirectBody += " return " + IndirectReturnValue + ";\n";
+ return {DirectBody, IndirectBody};
+}
+
+std::pair
+IRTCallDescription::createCSignature(const InstrumentationConfig &IConf) const
{
+ SmallVector DirectArgs, IndirectArgs;
+ std::string DirectRetTy = "void ", IndirectRetTy = "void ";
+ for (auto &IRArg : IO.IRTArgs) {
+if (!IRArg.Enabled)
+ continue;
+const auto &[DirectArgTy, IndirectArgTy] =
+getAsCType(IRArg.Ty, IRArg.Flags);
+std::string DirectArg = DirectArgTy + IRArg.Name.str();
+std::string IndirectArg = IndirectArgTy + IRArg.Name.str() + "_ptr";
+std::string IndirectArgSize = "int32_t " + IRArg.Name.str() + "_size";
+DirectArgs.push_back(DirectArg);
+if (NumReplaceableArgs == 1 && (IRArg.Flags & IRTArg::REPLACABLE)) {
+ DirectRetTy = DirectArgTy;
+ if (!isPotentiallyIndirect(IRArg))
+IndirectRetTy = DirectA
[llvm-branch-commits] [llvm] [Instrumentor] Allow printing a runtime stub (PR #138978)
kevinsala wrote: The new version sets the default runtime stub file name as empty, so no runtime stub is printed by default. This approach is safer, as it prevents the Instrumentor from unintentionally generating a file and overwriting an existing one without the user noticing it. https://github.com/llvm/llvm-project/pull/138978 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
