[llvm-branch-commits] [llvm] [AMDGPU] Add BFX Formation Combines to RegBankCombiner (PR #141590)
Pierre-vh wrote: ping https://github.com/llvm/llvm-project/pull/141590 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 (PR #142602)
Pierre-vh wrote: @petar-avramovic If this is good, can you approve it so I can land it once all other patches are approved? Thanks :) https://github.com/llvm/llvm-project/pull/142602 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)
Pierre-vh wrote: ping https://github.com/llvm/llvm-project/pull/142601 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][Transforms][NFC] Dialect Conversion: Manually populate `unresolvedMaterializations` (PR #144664)
https://github.com/matthias-springer created
https://github.com/llvm/llvm-project/pull/144664
Manually populate the `unresolvedMaterializations` map instead of automatically
in the `UnresolvedMaterializationRewrite` constructor. This simplifies the
constructor a bit.
This commit is in preparation of the One-Shot Dialect Conversion refactoring:
`allowPatternRollback = false` will in the future trigger immediate
materialization of all IR changes.
Depends on #144254.
>From ede5b9e79c478ef45107c9249db6534427ee2cff Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Wed, 18 Jun 2025 09:50:40 +
Subject: [PATCH] [mlir][Transforms][NFC] Dialect Conversion: Manually push
rewrite onto stack
---
mlir/lib/Transforms/Utils/DialectConversion.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/mlir/lib/Transforms/Utils/DialectConversion.cpp
b/mlir/lib/Transforms/Utils/DialectConversion.cpp
index c4b85ec4f67d6..8b94bc564d169 100644
--- a/mlir/lib/Transforms/Utils/DialectConversion.cpp
+++ b/mlir/lib/Transforms/Utils/DialectConversion.cpp
@@ -869,9 +869,10 @@ struct ConversionPatternRewriterImpl : public
RewriterBase::Listener {
/// Append a rewrite. Rewrites are committed upon success and rolled back
upon
/// failure.
template
- void appendRewrite(Args &&...args) {
+ RewriteTy *appendRewrite(Args &&...args) {
rewrites.push_back(
std::make_unique(*this, std::forward(args)...));
+return static_cast(rewrites.back().get());
}
/// Undo the rewrites (motions, splits) one by one in reverse order until
@@ -1181,7 +1182,6 @@
UnresolvedMaterializationRewrite::UnresolvedMaterializationRewrite(
mappedValues(std::move(mappedValues)) {
assert((!originalType || kind == MaterializationKind::Target) &&
"original type is valid only for target materializations");
- rewriterImpl.unresolvedMaterializations[op] = this;
}
void UnresolvedMaterializationRewrite::rollback() {
@@ -1471,8 +1471,9 @@ ValueRange
ConversionPatternRewriterImpl::buildUnresolvedMaterialization(
mapping.map(valuesToMap, convertOp.getResults());
if (castOp)
*castOp = convertOp;
- appendRewrite(
- convertOp, converter, kind, originalType, std::move(valuesToMap));
+ unresolvedMaterializations[convertOp] =
+ appendRewrite(
+ convertOp, converter, kind, originalType, std::move(valuesToMap));
return convertOp.getResults();
}
___
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[llvm-branch-commits] [llvm] ARM: Avoid using isTarget wrappers around Triple predicates (PR #144705)
https://github.com/smithp35 commented: This looks reasonable to me. I can't see a way of changing those properties on a subtarget level with attributes. Added the ARM backend maintainers to see if they have anything to add. Would it be worth adding a comment to the function definitions in Subtarget https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/ARM/ARMSubtarget.h#L336 Something similar to the comment about the isCortexA5() in https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/ARM/ARMSubtarget.h#L285 ``` /// These properties are per-module, please use the TargetMachine TargetTriple. ``` https://github.com/llvm/llvm-project/pull/144705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] c8b03a7 - Revert "[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elem…"
Author: Robert Imschweiler
Date: 2025-06-18T09:49:06+02:00
New Revision: c8b03a7c094a1ff3bc715486af316ce3aab0c956
URL:
https://github.com/llvm/llvm-project/commit/c8b03a7c094a1ff3bc715486af316ce3aab0c956
DIFF:
https://github.com/llvm/llvm-project/commit/c8b03a7c094a1ff3bc715486af316ce3aab0c956.diff
LOG: Revert "[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different
elem…"
This reverts commit 4d71f20b287e398f10bbff55d52bec9683ef89d2.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Removed:
diff --git
a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 8f560c42082f9..22f6a5fde546a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -997,7 +997,6 @@ class LegalizationArtifactCombiner {
// Recognize UnmergeSrc that can be unmerged to DstTy directly.
// Types have to be either both vector or both non-vector types.
- // In case of vector types, the scalar elements need to match.
// Merge-like opcodes are combined one at the time. First one creates new
// unmerge, following should use the same unmerge (builder performs CSE).
//
@@ -1006,9 +1005,7 @@ class LegalizationArtifactCombiner {
// %AnotherDst:_(DstTy) = G_merge_like_opcode %2:_(EltTy), %3
//
// %Dst:_(DstTy), %AnotherDst = G_UNMERGE_VALUES %UnmergeSrc
- if (((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
- (DstTy.isVector() && UnmergeSrcTy.isVector() &&
-DstTy.getScalarType() == UnmergeSrcTy.getScalarType())) &&
+ if ((DstTy.isVector() == UnmergeSrcTy.isVector()) &&
(Elt0UnmergeIdx % NumMIElts == 0) &&
getCoverTy(UnmergeSrcTy, DstTy) == UnmergeSrcTy) {
if (!isSequenceFromUnmerge(MI, 0, Unmerge, Elt0UnmergeIdx, NumMIElts,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
index 132a89478c5fd..8134eb3ca2afc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
@@ -6506,58 +6506,3 @@ entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
}
-
-; Found by fuzzer, reduced with llvm-reduce.
-define amdgpu_kernel void @insert_very_small_from_very_large(<32 x i16> %L3,
ptr %ptr) {
-; GPRIDX-LABEL: insert_very_small_from_very_large:
-; GPRIDX: ; %bb.0: ; %bb
-; GPRIDX-NEXT:s_load_dwordx16 s[12:27], s[8:9], 0x0
-; GPRIDX-NEXT:s_load_dwordx2 s[0:1], s[8:9], 0x40
-; GPRIDX-NEXT:s_waitcnt lgkmcnt(0)
-; GPRIDX-NEXT:s_lshr_b32 s2, s12, 1
-; GPRIDX-NEXT:s_and_b32 s2, s2, 1
-; GPRIDX-NEXT:s_lshl_b32 s2, s2, 1
-; GPRIDX-NEXT:v_mov_b32_e32 v0, s0
-; GPRIDX-NEXT:v_mov_b32_e32 v2, s2
-; GPRIDX-NEXT:v_mov_b32_e32 v1, s1
-; GPRIDX-NEXT:flat_store_byte v[0:1], v2
-; GPRIDX-NEXT:s_endpgm
-;
-; GFX10-LABEL: insert_very_small_from_very_large:
-; GFX10: ; %bb.0: ; %bb
-; GFX10-NEXT:s_clause 0x1
-; GFX10-NEXT:s_load_dwordx16 s[12:27], s[8:9], 0x0
-; GFX10-NEXT:s_load_dwordx2 s[0:1], s[8:9], 0x40
-; GFX10-NEXT:s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:s_lshr_b32 s2, s12, 1
-; GFX10-NEXT:v_mov_b32_e32 v0, s0
-; GFX10-NEXT:s_and_b32 s2, s2, 1
-; GFX10-NEXT:v_mov_b32_e32 v1, s1
-; GFX10-NEXT:s_lshl_b32 s2, s2, 1
-; GFX10-NEXT:v_mov_b32_e32 v2, s2
-; GFX10-NEXT:flat_store_byte v[0:1], v2
-; GFX10-NEXT:s_endpgm
-;
-; GFX11-LABEL: insert_very_small_from_very_large:
-; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT:s_clause 0x1
-; GFX11-NEXT:s_load_b512 s[8:23], s[4:5], 0x0
-; GFX11-NEXT:s_load_b64 s[0:1], s[4:5], 0x40
-; GFX11-NEXT:s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:s_lshr_b32 s2, s8, 1
-; GFX11-NEXT:v_mov_b32_e32 v0, s0
-; GFX11-NEXT:s_and_b32 s2, s2, 1
-; GFX11-NEXT:v_mov_b32_e32 v1, s1
-; GFX11-NEXT:s_lshl_b32 s2, s2, 1
-; GFX11-NEXT:v_mov_b32_e32 v2, s2
-; GFX11-NEXT:flat_store_b8 v[0:1], v2
-; GFX11-NEXT:s_endpgm
-bb:
- %a = bitcast <32 x i16> %L3 to i512
- %b = trunc i512 %a to i8
- %c = trunc i8 %b to i2
- %d = bitcast i2 %c to <2 x i1>
- %insert = insertelement <2 x i1> %d, i1 false, i32 0
- store <2 x i1> %insert, ptr %ptr, align 1
- ret void
-}
___
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/5] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
Options.LoadSizes = {4, 2, 1};
if (IsZeroCmp && ST->hasVInstructions()) {
unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
}
>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/5] Change to XLen + 1
Created using spr 1.3.6-beta.1
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 4 +-
llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
3 files changed, 570 insertions(+), 82 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
if (IsZeroCmp && ST->hasVInstructions()) {
unsigned VLenB = ST->getRealMinVLen() / 8;
// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
for (unsigned Size = MinSize;
Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
; CHECK-ALIGNED-RV64-V-NEXT:ret
;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED: # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0
[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/5] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
Options.LoadSizes = {4, 2, 1};
if (IsZeroCmp && ST->hasVInstructions()) {
unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
}
>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/5] Change to XLen + 1
Created using spr 1.3.6-beta.1
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 4 +-
llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
3 files changed, 570 insertions(+), 82 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
if (IsZeroCmp && ST->hasVInstructions()) {
unsigned VLenB = ST->getRealMinVLen() / 8;
// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
for (unsigned Size = MinSize;
Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
; CHECK-ALIGNED-RV64-V-NEXT:ret
;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED: # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0
[llvm-branch-commits] [libcxx] [libc++][C++03] Fix a bunch of random tests (PR #144117)
https://github.com/ldionne approved this pull request. https://github.com/llvm/llvm-project/pull/144117 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [CodeGen][NFC] Fix quadratic c-t for large jump tables (PR #144108)
https://github.com/aengelke updated https://github.com/llvm/llvm-project/pull/144108 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 2ed0932 - Revert "Add missing intrinsics to cuda headers (#143664)"
Author: Artem Belevich
Date: 2025-06-18T10:06:56-07:00
New Revision: 2ed0932a540bb1a692fe442ab590d51674645f6c
URL:
https://github.com/llvm/llvm-project/commit/2ed0932a540bb1a692fe442ab590d51674645f6c
DIFF:
https://github.com/llvm/llvm-project/commit/2ed0932a540bb1a692fe442ab590d51674645f6c.diff
LOG: Revert "Add missing intrinsics to cuda headers (#143664)"
This reverts commit b876b3fa98cffd5b8755398f9a8218f667464d76.
Added:
Modified:
clang/lib/Headers/__clang_cuda_intrinsics.h
Removed:
diff --git a/clang/lib/Headers/__clang_cuda_intrinsics.h
b/clang/lib/Headers/__clang_cuda_intrinsics.h
index 5e13f3f78df70..8b230af6f6647 100644
--- a/clang/lib/Headers/__clang_cuda_intrinsics.h
+++ b/clang/lib/Headers/__clang_cuda_intrinsics.h
@@ -479,290 +479,6 @@ inline __device__ unsigned __funnelshift_rc(unsigned
low32, unsigned high32,
return ret;
}
-#pragma push_macro("__INTRINSIC_LOAD")
-#define __INTRINSIC_LOAD(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType,
\
- __Clobber)
\
- inline __device__ __DeclType __FnName(const __DeclType *__ptr) {
\
-__TmpType __ret;
\
-asm(__AsmOp " %0, [%1];" : __AsmType(__ret) : "l"(__ptr)__Clobber);
\
-return (__DeclType)__ret;
\
- }
-
-#pragma push_macro("__INTRINSIC_LOAD2")
-#define __INTRINSIC_LOAD2(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType,
\
- __Clobber)
\
- inline __device__ __DeclType __FnName(const __DeclType *__ptr) {
\
-__DeclType __ret;
\
-__TmpType __tmp;
\
-asm(__AsmOp " {%0,%1}, [%2];"
\
-: __AsmType(__tmp.x), __AsmType(__tmp.y)
\
-: "l"(__ptr)__Clobber);
\
-using __ElementType = decltype(__ret.x);
\
-__ret.x = (__ElementType)(__tmp.x);
\
-__ret.y = (__ElementType)__tmp.y;
\
-return __ret;
\
- }
-
-#pragma push_macro("__INTRINSIC_LOAD4")
-#define __INTRINSIC_LOAD4(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType,
\
- __Clobber)
\
- inline __device__ __DeclType __FnName(const __DeclType *__ptr) {
\
-__DeclType __ret;
\
-__TmpType __tmp;
\
-asm(__AsmOp " {%0,%1,%2,%3}, [%4];"
\
-: __AsmType(__tmp.x), __AsmType(__tmp.y), __AsmType(__tmp.z),
\
- __AsmType(__tmp.w)
\
-: "l"(__ptr)__Clobber);
\
-using __ElementType = decltype(__ret.x);
\
-__ret.x = (__ElementType)__tmp.x;
\
-__ret.y = (__ElementType)__tmp.y;
\
-__ret.z = (__ElementType)__tmp.z;
\
-__ret.w = (__ElementType)__tmp.w;
\
-return __ret;
\
- }
-
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.s8", char, unsigned int, "=r", );
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.s8", signed char, unsigned int, "=r", );
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.s16", short, unsigned short, "=h", );
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.s32", int, unsigned int, "=r", );
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.s64", long long, unsigned long long,
- "=l", );
-
-__INTRINSIC_LOAD2(__ldcg, "ld.global.cg.v2.s8", char2, int2, "=r", );
-__INTRINSIC_LOAD4(__ldcg, "ld.global.cg.v4.s8", char4, int4, "=r", );
-__INTRINSIC_LOAD2(__ldcg, "ld.global.cg.v2.s16", short2, short2, "=h", );
-__INTRINSIC_LOAD4(__ldcg, "ld.global.cg.v4.s16", short4, short4, "=h", );
-__INTRINSIC_LOAD2(__ldcg, "ld.global.cg.v2.s32", int2, int2, "=r", );
-__INTRINSIC_LOAD4(__ldcg, "ld.global.cg.v4.s32", int4, int4, "=r", );
-__INTRINSIC_LOAD2(__ldcg, "ld.global.cg.v2.s64 ", longlong2, longlong2, "=l",
);
-
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.u8", unsigned char, unsigned int,
- "=r", );
-__INTRINSIC_LOAD(__ldcg, "ld.global.cg.u16", unsigned short, unsigned short,
- "=h", );
-__INTRINSIC
[llvm-branch-commits] [libcxx] [libc++][C++03] Remove tests from libcxx-03 which aren't run in C++03 mode (PR #144094)
https://github.com/ldionne approved this pull request. LGTM with CI passing. https://github.com/llvm/llvm-project/pull/144094 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [libc++][C++03] Remove XFAILs from the non-frozen libc++-specific tests (PR #144101)
https://github.com/ldionne approved this pull request. https://github.com/llvm/llvm-project/pull/144101 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 6192df1 - Revert "[llvm-cov] Export decision coverage to output json (#144335)"
Author: Alan Phipps
Date: 2025-06-18T14:11:57-05:00
New Revision: 6192df16081fd36c7e4f947ee8956233cf02464b
URL:
https://github.com/llvm/llvm-project/commit/6192df16081fd36c7e4f947ee8956233cf02464b
DIFF:
https://github.com/llvm/llvm-project/commit/6192df16081fd36c7e4f947ee8956233cf02464b.diff
LOG: Revert "[llvm-cov] Export decision coverage to output json (#144335)"
This reverts commit ab6beeca9ccc1968661eea27c1a55e8734f7437b.
Added:
Modified:
llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
llvm/tools/llvm-cov/CoverageExporterJson.cpp
Removed:
diff --git a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
index 8e6180be25b51..d1230b0ba7c58 100644
--- a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
+++ b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
@@ -31,7 +31,6 @@
#include "llvm/Support/Endian.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/raw_ostream.h"
-#include
#include
#include
#include
@@ -495,17 +494,6 @@ struct MCDCRecord {
return TV[TestVectorIndex].first[PosToID[Condition]];
}
- /// Return the number of True and False decisions for all executed test
- /// vectors.
- std::pair getDecisions() const {
-const unsigned TrueDecisions =
-std::count_if(TV.begin(), TV.end(), [](const auto &TestVec) {
- return TestVec.second == CondState::MCDC_True;
-});
-
-return {TrueDecisions, TV.size() - TrueDecisions};
- }
-
/// Return the Result evaluation for an executed test vector.
/// See MCDCRecordProcessor::RecordTestVector().
CondState getTVResult(unsigned TestVectorIndex) {
diff --git a/llvm/tools/llvm-cov/CoverageExporterJson.cpp
b/llvm/tools/llvm-cov/CoverageExporterJson.cpp
index 024693a24cc23..4088c1b053aa8 100644
--- a/llvm/tools/llvm-cov/CoverageExporterJson.cpp
+++ b/llvm/tools/llvm-cov/CoverageExporterJson.cpp
@@ -62,7 +62,7 @@
#include
/// The semantic version combined as a string.
-#define LLVM_COVERAGE_EXPORT_JSON_STR "3.0.0"
+#define LLVM_COVERAGE_EXPORT_JSON_STR "2.0.1"
/// Unique type identifier for JSON coverage export.
#define LLVM_COVERAGE_EXPORT_JSON_TYPE_STR "llvm.coverage.json.export"
@@ -110,10 +110,8 @@ json::Array gatherConditions(const coverage::MCDCRecord
&Record) {
json::Array renderMCDCRecord(const coverage::MCDCRecord &Record) {
const llvm::coverage::CounterMappingRegion &CMR = Record.getDecisionRegion();
- const auto [TrueDecisions, FalseDecisions] = Record.getDecisions();
return json::Array({CMR.LineStart, CMR.ColumnStart, CMR.LineEnd,
- CMR.ColumnEnd, TrueDecisions, FalseDecisions,
- CMR.ExpandedFileID, int64_t(CMR.Kind),
+ CMR.ColumnEnd, CMR.ExpandedFileID, int64_t(CMR.Kind),
gatherConditions(Record)});
}
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[llvm-branch-commits] [llvm] ARM: Move ABI helpers from Subtarget to TargetMachine (PR #144680)
https://github.com/efriedma-quic approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/144680 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 9d77525 - Revert "[HLSL][SPIRV] Add vk::constant_id attribute. (#143544)"
Author: Steven Perron
Date: 2025-06-18T19:30:17-04:00
New Revision: 9d775256000726929f826ec164aa514d4a6e2288
URL:
https://github.com/llvm/llvm-project/commit/9d775256000726929f826ec164aa514d4a6e2288
DIFF:
https://github.com/llvm/llvm-project/commit/9d775256000726929f826ec164aa514d4a6e2288.diff
LOG: Revert "[HLSL][SPIRV] Add vk::constant_id attribute. (#143544)"
This reverts commit acde20b5605f3a3a8da2217e4526fc045e6603ed.
Added:
clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/Builtins.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/SemaHLSL.h
clang/lib/CodeGen/CGHLSLBuiltins.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/lib/Sema/SemaHLSL.cpp
Removed:
clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
clang/test/SemaHLSL/vk.spec-constant.error.hlsl
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 27fea7dea0a5e..f113cd2ba2fbf 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -5023,14 +5023,6 @@ def HLSLVkExtBuiltinInput : InheritableAttr {
let Documentation = [HLSLVkExtBuiltinInputDocs];
}
-def HLSLVkConstantId : InheritableAttr {
- let Spellings = [CXX11<"vk", "constant_id">];
- let Args = [IntArgument<"Id">];
- let Subjects = SubjectList<[ExternalGlobalVar]>;
- let LangOpts = [HLSL];
- let Documentation = [VkConstantIdDocs];
-}
-
def RandomizeLayout : InheritableAttr {
let Spellings = [GCC<"randomize_layout">];
let Subjects = SubjectList<[Record]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index 43442f177ab7b..6051e1fc45111 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -8252,21 +8252,6 @@ and
https://microsoft.github.io/hlsl-specs/proposals/0013-wave-size-range.html
}];
}
-def VkConstantIdDocs : Documentation {
- let Category = DocCatFunction;
- let Content = [{
-The ``vk::constant_id`` attribute specifies the id for a SPIR-V specialization
-constant. The attribute applies to const global scalar variables. The variable
must be initialized with a C++11 constexpr.
-In SPIR-V, the
-variable will be replaced with an `OpSpecConstant` with the given id.
-The syntax is:
-
-.. code-block:: text
-
- ``[[vk::constant_id()]] const T Name = ``
-}];
-}
-
def RootSignatureDocs : Documentation {
let Category = DocCatFunction;
let Content = [{
diff --git a/clang/include/clang/Basic/Builtins.td
b/clang/include/clang/Basic/Builtins.td
index d65b3a5d2f447..68cd3d790e78a 100644
--- a/clang/include/clang/Basic/Builtins.td
+++ b/clang/include/clang/Basic/Builtins.td
@@ -5065,19 +5065,6 @@ def HLSLGroupMemoryBarrierWithGroupSync:
LangBuiltin<"HLSL_LANG"> {
let Prototype = "void()";
}
-class HLSLScalarTemplate
-: Template<["bool", "char", "short", "int", "long long int",
-"unsigned short", "unsigned int", "unsigned long long int",
-"__fp16", "float", "double"],
- ["_bool", "_char", "_short", "_int", "_longlong", "_ushort",
-"_uint", "_ulonglong", "_half", "_float", "_double"]>;
-
-def HLSLGetSpirvSpecConstant : LangBuiltin<"HLSL_LANG">, HLSLScalarTemplate {
- let Spellings = ["__builtin_get_spirv_spec_constant"];
- let Attributes = [NoThrow, Const, Pure];
- let Prototype = "T(unsigned int, T)";
-}
-
// Builtins for XRay.
def XRayCustomEvent : Builtin {
let Spellings = ["__xray_customevent"];
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 34b798a09c216..979ff60b73b75 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12927,10 +12927,6 @@ def err_spirv_enum_not_int : Error<
def err_spirv_enum_not_valid : Error<
"invalid value for %select{storage class}0 argument">;
-def err_specialization_const
-: Error<"variable with 'vk::constant_id' attribute must be a const "
-"int/float/enum/bool and be initialized with a literal">;
-
// errors of expect.with.probability
def err_probability_not_constant_float : Error<
"probability argument to __builtin_expect_with_probability must be constant
"
diff --git a/clang/include/clang/Sema/SemaHLSL.h
b/clang/include/clang/Sema/SemaHLSL.h
index 97091792ba236..33c4b8d1568bf 100644
--- a/clang/include/clang/Sema/SemaHLSL.h
+++ b/clang/include/clang/Sema
[llvm-branch-commits] [llvm] ARM: Move ABI helpers from Subtarget to TargetMachine (PR #144680)
arsenm wrote: ### Merge activity * **Jun 19, 12:33 AM UTC**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/144680). https://github.com/llvm/llvm-project/pull/144680 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] add support for concepts (PR #144430)
https://github.com/evelez7 converted_to_draft https://github.com/llvm/llvm-project/pull/144430 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [libc++][C++03] Fix tests which only fail due to incorrect includes (PR #144110)
https://github.com/ldionne approved this pull request. https://github.com/llvm/llvm-project/pull/144110 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 (PR #142602)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/142602 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/142601 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [GOFF] Emit symbols for functions. (PR #144437)
@@ -41,6 +44,61 @@ void MCGOFFStreamer::changeSection(MCSection *Section,
uint32_t Subsection) {
MCObjectStreamer::changeSection(Section, Subsection);
}
+void MCGOFFStreamer::emitLabel(MCSymbol *Symbol, SMLoc Loc) {
+ MCObjectStreamer::emitLabel(Symbol, Loc);
+ cast(Symbol)->initAttributes();
+}
+
+bool MCGOFFStreamer::emitSymbolAttribute(MCSymbol *Sym,
+ MCSymbolAttr Attribute) {
+ auto *Symbol = cast(Sym);
+ switch (Attribute) {
+ case MCSA_Invalid:
+ case MCSA_Cold:
+ case MCSA_ELF_TypeFunction:
+ case MCSA_ELF_TypeIndFunction:
+ case MCSA_ELF_TypeObject:
+ case MCSA_ELF_TypeTLS:
+ case MCSA_ELF_TypeCommon:
+ case MCSA_ELF_TypeNoType:
+ case MCSA_ELF_TypeGnuUniqueObject:
+ case MCSA_LGlobal:
+ case MCSA_Extern:
+ case MCSA_Exported:
+ case MCSA_IndirectSymbol:
+ case MCSA_Internal:
+ case MCSA_LazyReference:
+ case MCSA_NoDeadStrip:
+ case MCSA_SymbolResolver:
+ case MCSA_AltEntry:
+ case MCSA_PrivateExtern:
+ case MCSA_Protected:
+ case MCSA_Reference:
+ case MCSA_WeakDefinition:
+ case MCSA_WeakDefAutoPrivate:
+ case MCSA_WeakAntiDep:
+ case MCSA_Memtag:
+return false;
+
+ case MCSA_Global:
+Symbol->setExternal(true);
+break;
+ case MCSA_Local:
+Symbol->setExternal(false);
MaskRay wrote:
Is local/global/weak tested?
https://github.com/llvm/llvm-project/pull/144437
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[llvm-branch-commits] [llvm] [GOFF] Emit symbols for functions. (PR #144437)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/144437 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [GOFF] Emit symbols for functions. (PR #144437)
https://github.com/MaskRay commented: LGTM! But I will delegated to a GOFF expert for approval... https://github.com/llvm/llvm-project/pull/144437 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Avoid using isTarget wrappers around Triple predicates (PR #144705)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144705
>From b6dc4685321a268bfd70e7c35770c4c57f1bdacf Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 22:24:53 +0900
Subject: [PATCH 1/3] ARM: Avoid using isTarget wrappers around Triple
predicates
These are module level properties, and querying them through
a function-level subtarget context is confusing. Plus we don't
need an aliased name. This doesn't avoid all the uses, just the
ones in the TargetLowering constructor.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 28 -
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 91fb7bc4578b3..f18bdde53cd5d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -515,7 +515,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
- if (Subtarget->isTargetMachO()) {
+ const Triple &TT = TM.getTargetTriple();
+
+ if (TT.isOSBinFormatMachO()) {
// Uses VFP for Thumb libfuncs if available.
if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
@@ -589,8 +591,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// RTLIB
if (TM.isAAPCS_ABI() &&
- (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
- Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
+ (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI() ||
+ TT.isAndroid())) {
// clang-format off
static const struct {
const RTLIB::Libcall Op;
@@ -712,7 +714,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// The half <-> float conversion functions are always soft-float on
// non-watchos platforms, but are needed for some targets which use a
// hard-float calling convention by default.
- if (!Subtarget->isTargetWatchABI()) {
+ if (!TT.isWatchABI()) {
if (TM.isAAPCS_ABI()) {
setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
@@ -726,7 +728,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
// a __gnu_ prefix (which is the default).
- if (Subtarget->isTargetAEABI()) {
+ if (TT.isTargetAEABI()) {
static const struct {
const RTLIB::Libcall Op;
const char * const Name;
@@ -741,7 +743,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setLibcallName(LC.Op, LC.Name);
setLibcallCallingConv(LC.Op, LC.CC);
}
- } else if (!Subtarget->isTargetMachO()) {
+ } else if (!TT.isOSBinFormatMachO()) {
setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
}
@@ -1227,7 +1229,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UDIV, MVT::i32, LibCall);
}
- if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
+ if (TT.isOSWindows() && !Subtarget->hasDivideInThumbMode()) {
setOperationAction(ISD::SDIV, MVT::i32, Custom);
setOperationAction(ISD::UDIV, MVT::i32, Custom);
@@ -1239,9 +1241,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UREM, MVT::i32, Expand);
// Register based DivRem for AEABI (RTABI 4.2)
- if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
- Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
- Subtarget->isTargetWindows()) {
+ if (TT.isTargetAEABI() || TT.isAndroid() || TT.isTargetGNUAEABI() ||
+ TT.isTargetMuslAEABI() || TT.isOSWindows()) {
setOperationAction(ISD::SREM, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
HasStandaloneRem = false;
@@ -1271,7 +1272,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- if (Subtarget->isTargetWindows())
+ if (TT.isOSWindows())
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
@@ -1326,8 +1327,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
}
// Compute supported atomic widths.
- if (Subtarget->isTargetLinux() ||
- (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
+ if (TT.isOSLinux() || (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
// For targets where __sync_* routines are reliably available, we use them
// if neces
[llvm-branch-commits] [llvm] ARM: Avoid using isTarget wrappers around Triple predicates (PR #144705)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144705
>From b6dc4685321a268bfd70e7c35770c4c57f1bdacf Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 22:24:53 +0900
Subject: [PATCH 1/2] ARM: Avoid using isTarget wrappers around Triple
predicates
These are module level properties, and querying them through
a function-level subtarget context is confusing. Plus we don't
need an aliased name. This doesn't avoid all the uses, just the
ones in the TargetLowering constructor.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 28 -
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 91fb7bc4578b3..f18bdde53cd5d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -515,7 +515,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
- if (Subtarget->isTargetMachO()) {
+ const Triple &TT = TM.getTargetTriple();
+
+ if (TT.isOSBinFormatMachO()) {
// Uses VFP for Thumb libfuncs if available.
if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
@@ -589,8 +591,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// RTLIB
if (TM.isAAPCS_ABI() &&
- (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
- Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
+ (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI() ||
+ TT.isAndroid())) {
// clang-format off
static const struct {
const RTLIB::Libcall Op;
@@ -712,7 +714,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// The half <-> float conversion functions are always soft-float on
// non-watchos platforms, but are needed for some targets which use a
// hard-float calling convention by default.
- if (!Subtarget->isTargetWatchABI()) {
+ if (!TT.isWatchABI()) {
if (TM.isAAPCS_ABI()) {
setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
@@ -726,7 +728,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
// a __gnu_ prefix (which is the default).
- if (Subtarget->isTargetAEABI()) {
+ if (TT.isTargetAEABI()) {
static const struct {
const RTLIB::Libcall Op;
const char * const Name;
@@ -741,7 +743,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setLibcallName(LC.Op, LC.Name);
setLibcallCallingConv(LC.Op, LC.CC);
}
- } else if (!Subtarget->isTargetMachO()) {
+ } else if (!TT.isOSBinFormatMachO()) {
setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
}
@@ -1227,7 +1229,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UDIV, MVT::i32, LibCall);
}
- if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
+ if (TT.isOSWindows() && !Subtarget->hasDivideInThumbMode()) {
setOperationAction(ISD::SDIV, MVT::i32, Custom);
setOperationAction(ISD::UDIV, MVT::i32, Custom);
@@ -1239,9 +1241,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UREM, MVT::i32, Expand);
// Register based DivRem for AEABI (RTABI 4.2)
- if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
- Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
- Subtarget->isTargetWindows()) {
+ if (TT.isTargetAEABI() || TT.isAndroid() || TT.isTargetGNUAEABI() ||
+ TT.isTargetMuslAEABI() || TT.isOSWindows()) {
setOperationAction(ISD::SREM, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
HasStandaloneRem = false;
@@ -1271,7 +1272,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- if (Subtarget->isTargetWindows())
+ if (TT.isOSWindows())
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
@@ -1326,8 +1327,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
}
// Compute supported atomic widths.
- if (Subtarget->isTargetLinux() ||
- (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
+ if (TT.isOSLinux() || (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
// For targets where __sync_* routines are reliably available, we use them
// if neces
[llvm-branch-commits] [llvm] ARM: Avoid using isTarget wrappers around Triple predicates (PR #144705)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144705
>From b6dc4685321a268bfd70e7c35770c4c57f1bdacf Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 22:24:53 +0900
Subject: [PATCH 1/2] ARM: Avoid using isTarget wrappers around Triple
predicates
These are module level properties, and querying them through
a function-level subtarget context is confusing. Plus we don't
need an aliased name. This doesn't avoid all the uses, just the
ones in the TargetLowering constructor.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 28 -
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 91fb7bc4578b3..f18bdde53cd5d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -515,7 +515,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
- if (Subtarget->isTargetMachO()) {
+ const Triple &TT = TM.getTargetTriple();
+
+ if (TT.isOSBinFormatMachO()) {
// Uses VFP for Thumb libfuncs if available.
if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
@@ -589,8 +591,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// RTLIB
if (TM.isAAPCS_ABI() &&
- (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
- Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
+ (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI() ||
+ TT.isAndroid())) {
// clang-format off
static const struct {
const RTLIB::Libcall Op;
@@ -712,7 +714,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// The half <-> float conversion functions are always soft-float on
// non-watchos platforms, but are needed for some targets which use a
// hard-float calling convention by default.
- if (!Subtarget->isTargetWatchABI()) {
+ if (!TT.isWatchABI()) {
if (TM.isAAPCS_ABI()) {
setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
@@ -726,7 +728,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
// a __gnu_ prefix (which is the default).
- if (Subtarget->isTargetAEABI()) {
+ if (TT.isTargetAEABI()) {
static const struct {
const RTLIB::Libcall Op;
const char * const Name;
@@ -741,7 +743,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setLibcallName(LC.Op, LC.Name);
setLibcallCallingConv(LC.Op, LC.CC);
}
- } else if (!Subtarget->isTargetMachO()) {
+ } else if (!TT.isOSBinFormatMachO()) {
setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
}
@@ -1227,7 +1229,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UDIV, MVT::i32, LibCall);
}
- if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
+ if (TT.isOSWindows() && !Subtarget->hasDivideInThumbMode()) {
setOperationAction(ISD::SDIV, MVT::i32, Custom);
setOperationAction(ISD::UDIV, MVT::i32, Custom);
@@ -1239,9 +1241,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UREM, MVT::i32, Expand);
// Register based DivRem for AEABI (RTABI 4.2)
- if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
- Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
- Subtarget->isTargetWindows()) {
+ if (TT.isTargetAEABI() || TT.isAndroid() || TT.isTargetGNUAEABI() ||
+ TT.isTargetMuslAEABI() || TT.isOSWindows()) {
setOperationAction(ISD::SREM, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
HasStandaloneRem = false;
@@ -1271,7 +1272,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- if (Subtarget->isTargetWindows())
+ if (TT.isOSWindows())
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
@@ -1326,8 +1327,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
}
// Compute supported atomic widths.
- if (Subtarget->isTargetLinux() ||
- (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
+ if (TT.isOSLinux() || (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
// For targets where __sync_* routines are reliably available, we use them
// if neces
[llvm-branch-commits] [llvm] MC: Move ExceptionHandling enum to Support (PR #144692)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144692
>From 762a6b42151430ec885fe28d8c2d195bd61d8db8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 21:42:59 +0900
Subject: [PATCH] MC: Move ExceptionHandling enum to Support
Similar to b5967264b0fbfd502b3a7edec27409e966fb68be, we need
to use this in RuntimeLibcalls to compute the set of library
calls.
---
llvm/include/llvm/MC/MCTargetOptions.h | 13 +
llvm/include/llvm/Support/CodeGen.h| 12
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h
b/llvm/include/llvm/MC/MCTargetOptions.h
index 3ee21d9cda4b7..d95adf92b9a83 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -10,6 +10,7 @@
#define LLVM_MC_MCTARGETOPTIONS_H
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Compression.h"
#include
@@ -17,18 +18,6 @@
namespace llvm {
-enum class ExceptionHandling {
- None, ///< No exception support
- DwarfCFI, ///< DWARF-like instruction based exceptions
- SjLj, ///< setjmp/longjmp based exceptions
- ARM, ///< ARM EHABI
- WinEH,///< Windows Exception Handling
- Wasm, ///< WebAssembly Exception Handling
- AIX, ///< AIX Exception Handling
- ZOS, ///< z/OS MVS Exception Handling. Very similar to DwarfCFI, but
the PPA1
-///< is used instead of an .eh_frame section.
-};
-
enum class EmitDwarfUnwindType {
Always, // Always emit dwarf unwind
NoCompactUnwind, // Only emit if compact unwind isn't available
diff --git a/llvm/include/llvm/Support/CodeGen.h
b/llvm/include/llvm/Support/CodeGen.h
index 90733b50385a9..cd1f9167b996d 100644
--- a/llvm/include/llvm/Support/CodeGen.h
+++ b/llvm/include/llvm/Support/CodeGen.h
@@ -50,6 +50,18 @@ namespace llvm {
};
}
+ enum class ExceptionHandling {
+None, ///< No exception support
+DwarfCFI, ///< DWARF-like instruction based exceptions
+SjLj, ///< setjmp/longjmp based exceptions
+ARM, ///< ARM EHABI
+WinEH,///< Windows Exception Handling
+Wasm, ///< WebAssembly Exception Handling
+AIX, ///< AIX Exception Handling
+ZOS, ///< z/OS MVS Exception Handling. Very similar to DwarfCFI, but the
+ ///< PPA1 is used instead of an .eh_frame section.
+ };
+
namespace FloatABI {
enum ABIType {
Default, // Target-specific (either soft or hard depending on triple, etc).
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] MC: Move ExceptionHandling enum to Support (PR #144692)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144692
>From 762a6b42151430ec885fe28d8c2d195bd61d8db8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 21:42:59 +0900
Subject: [PATCH] MC: Move ExceptionHandling enum to Support
Similar to b5967264b0fbfd502b3a7edec27409e966fb68be, we need
to use this in RuntimeLibcalls to compute the set of library
calls.
---
llvm/include/llvm/MC/MCTargetOptions.h | 13 +
llvm/include/llvm/Support/CodeGen.h| 12
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h
b/llvm/include/llvm/MC/MCTargetOptions.h
index 3ee21d9cda4b7..d95adf92b9a83 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -10,6 +10,7 @@
#define LLVM_MC_MCTARGETOPTIONS_H
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Compression.h"
#include
@@ -17,18 +18,6 @@
namespace llvm {
-enum class ExceptionHandling {
- None, ///< No exception support
- DwarfCFI, ///< DWARF-like instruction based exceptions
- SjLj, ///< setjmp/longjmp based exceptions
- ARM, ///< ARM EHABI
- WinEH,///< Windows Exception Handling
- Wasm, ///< WebAssembly Exception Handling
- AIX, ///< AIX Exception Handling
- ZOS, ///< z/OS MVS Exception Handling. Very similar to DwarfCFI, but
the PPA1
-///< is used instead of an .eh_frame section.
-};
-
enum class EmitDwarfUnwindType {
Always, // Always emit dwarf unwind
NoCompactUnwind, // Only emit if compact unwind isn't available
diff --git a/llvm/include/llvm/Support/CodeGen.h
b/llvm/include/llvm/Support/CodeGen.h
index 90733b50385a9..cd1f9167b996d 100644
--- a/llvm/include/llvm/Support/CodeGen.h
+++ b/llvm/include/llvm/Support/CodeGen.h
@@ -50,6 +50,18 @@ namespace llvm {
};
}
+ enum class ExceptionHandling {
+None, ///< No exception support
+DwarfCFI, ///< DWARF-like instruction based exceptions
+SjLj, ///< setjmp/longjmp based exceptions
+ARM, ///< ARM EHABI
+WinEH,///< Windows Exception Handling
+Wasm, ///< WebAssembly Exception Handling
+AIX, ///< AIX Exception Handling
+ZOS, ///< z/OS MVS Exception Handling. Very similar to DwarfCFI, but the
+ ///< PPA1 is used instead of an .eh_frame section.
+ };
+
namespace FloatABI {
enum ABIType {
Default, // Target-specific (either soft or hard depending on triple, etc).
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [llvm] ARM: Avoid using isTarget wrappers around Triple predicates (PR #144705)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h --
llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMSubtarget.h
``
View the diff from clang-format here.
``diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f18bdde53..4567081fe 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -590,9 +590,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
}
// RTLIB
- if (TM.isAAPCS_ABI() &&
- (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI() ||
- TT.isAndroid())) {
+ if (TM.isAAPCS_ABI() && (TT.isTargetAEABI() || TT.isTargetGNUAEABI() ||
+ TT.isTargetMuslAEABI() || TT.isAndroid())) {
// clang-format off
static const struct {
const RTLIB::Libcall Op;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h
b/llvm/lib/Target/ARM/ARMSubtarget.h
index 03c405e60..3e1314349 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -335,7 +335,8 @@ public:
const Triple &getTargetTriple() const { return TargetTriple; }
/// @{
- /// These properties are per-module, please use the TargetMachine
TargetTriple.
+ /// These properties are per-module, please use the TargetMachine
+ /// TargetTriple.
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetIOS() const { return TargetTriple.isiOS(); }
bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
``
https://github.com/llvm/llvm-project/pull/144705
___
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[llvm-branch-commits] [llvm] RuntimeLibcalls: Pass in exception handling type (PR #144696)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144696
>From 98101238be482a61591ec9e72376f2a7a75f19f3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 22:01:46 +0900
Subject: [PATCH] RuntimeLibcalls: Pass in exception handling type
All of the ABI options that influence libcall decisions need
to be passed in.
---
llvm/include/llvm/IR/RuntimeLibcalls.h | 14 --
llvm/lib/CodeGen/TargetLoweringBase.cpp | 4 ++--
llvm/lib/IR/RuntimeLibcalls.cpp | 6 ++
llvm/lib/Target/VE/VEISelLowering.cpp | 2 --
llvm/lib/Target/X86/X86ISelLowering.cpp | 4
5 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index a6a180f5ed8db..71f38bedf17e0 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -54,10 +54,12 @@ static inline auto libcalls() {
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
- explicit RuntimeLibcallsInfo(const Triple &TT,
- FloatABI::ABIType FloatABI = FloatABI::Default,
- EABI EABIVersion = EABI::Default) {
-initLibcalls(TT, FloatABI, EABIVersion);
+ explicit RuntimeLibcallsInfo(
+ const Triple &TT,
+ ExceptionHandling ExceptionModel = ExceptionHandling::None,
+ FloatABI::ABIType FloatABI = FloatABI::Default,
+ EABI EABIVersion = EABI::Default) {
+initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion);
}
/// Rename the default libcall routine name for the specified libcall.
@@ -147,8 +149,8 @@ struct RuntimeLibcallsInfo {
/// Set default libcall names. If a target wants to opt-out of a libcall it
/// should be placed here.
- LLVM_ABI void initLibcalls(const Triple &TT, FloatABI::ABIType FloatABI,
- EABI ABIType);
+ LLVM_ABI void initLibcalls(const Triple &TT, ExceptionHandling
ExceptionModel,
+ FloatABI::ABIType FloatABI, EABI ABIType);
};
} // namespace RTLIB
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp
b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 2b5087cd38f55..41e73b8530937 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -632,8 +632,8 @@ void RTLIB::initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs)
{
/// NOTE: The TargetMachine owns TLOF.
TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
-: TM(tm), Libcalls(TM.getTargetTriple(), TM.Options.FloatABIType,
- TM.Options.EABIVersion) {
+: TM(tm), Libcalls(TM.getTargetTriple(), TM.Options.ExceptionModel,
+ TM.Options.FloatABIType, TM.Options.EABIVersion) {
initActions();
// Perform these initializations only once.
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 74dccdf172d45..ad2904d6d2ea6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -357,6 +357,7 @@ static void setLongDoubleIsF128Libm(RuntimeLibcallsInfo
&Info,
/// Set default libcall names. If a target wants to opt-out of a libcall it
/// should be placed here.
void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
+ ExceptionHandling ExceptionModel,
FloatABI::ABIType FloatABI,
EABI EABIVersion) {
initSoftFloatCmpLibcallPredicates();
@@ -373,6 +374,11 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
if (TT.isX86() && TT.isGNUEnvironment())
setLongDoubleIsF128Libm(*this, /*FiniteOnlyFuncs=*/true);
+ if (TT.isX86() || TT.isVE()) {
+if (ExceptionModel == ExceptionHandling::SjLj)
+ setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
+ }
+
// For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
if (TT.isPPC()) {
setLibcallName(RTLIB::ADD_F128, "__addkf3");
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index b5a0d26abbf8e..98c5fdd138986 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -298,8 +298,6 @@ void VETargetLowering::initSPUActions() {
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
- if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
-setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
/// } SJLJ instructions
// Intrinsic instructions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4751361c71f2c..defb7730b4c7d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -513,10 +513,6 @
[llvm-branch-commits] [llvm] RuntimeLibcalls: Pass in exception handling type (PR #144696)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144696
>From 98101238be482a61591ec9e72376f2a7a75f19f3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 18 Jun 2025 22:01:46 +0900
Subject: [PATCH] RuntimeLibcalls: Pass in exception handling type
All of the ABI options that influence libcall decisions need
to be passed in.
---
llvm/include/llvm/IR/RuntimeLibcalls.h | 14 --
llvm/lib/CodeGen/TargetLoweringBase.cpp | 4 ++--
llvm/lib/IR/RuntimeLibcalls.cpp | 6 ++
llvm/lib/Target/VE/VEISelLowering.cpp | 2 --
llvm/lib/Target/X86/X86ISelLowering.cpp | 4
5 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index a6a180f5ed8db..71f38bedf17e0 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -54,10 +54,12 @@ static inline auto libcalls() {
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
- explicit RuntimeLibcallsInfo(const Triple &TT,
- FloatABI::ABIType FloatABI = FloatABI::Default,
- EABI EABIVersion = EABI::Default) {
-initLibcalls(TT, FloatABI, EABIVersion);
+ explicit RuntimeLibcallsInfo(
+ const Triple &TT,
+ ExceptionHandling ExceptionModel = ExceptionHandling::None,
+ FloatABI::ABIType FloatABI = FloatABI::Default,
+ EABI EABIVersion = EABI::Default) {
+initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion);
}
/// Rename the default libcall routine name for the specified libcall.
@@ -147,8 +149,8 @@ struct RuntimeLibcallsInfo {
/// Set default libcall names. If a target wants to opt-out of a libcall it
/// should be placed here.
- LLVM_ABI void initLibcalls(const Triple &TT, FloatABI::ABIType FloatABI,
- EABI ABIType);
+ LLVM_ABI void initLibcalls(const Triple &TT, ExceptionHandling
ExceptionModel,
+ FloatABI::ABIType FloatABI, EABI ABIType);
};
} // namespace RTLIB
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp
b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 2b5087cd38f55..41e73b8530937 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -632,8 +632,8 @@ void RTLIB::initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs)
{
/// NOTE: The TargetMachine owns TLOF.
TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
-: TM(tm), Libcalls(TM.getTargetTriple(), TM.Options.FloatABIType,
- TM.Options.EABIVersion) {
+: TM(tm), Libcalls(TM.getTargetTriple(), TM.Options.ExceptionModel,
+ TM.Options.FloatABIType, TM.Options.EABIVersion) {
initActions();
// Perform these initializations only once.
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 74dccdf172d45..ad2904d6d2ea6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -357,6 +357,7 @@ static void setLongDoubleIsF128Libm(RuntimeLibcallsInfo
&Info,
/// Set default libcall names. If a target wants to opt-out of a libcall it
/// should be placed here.
void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
+ ExceptionHandling ExceptionModel,
FloatABI::ABIType FloatABI,
EABI EABIVersion) {
initSoftFloatCmpLibcallPredicates();
@@ -373,6 +374,11 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
if (TT.isX86() && TT.isGNUEnvironment())
setLongDoubleIsF128Libm(*this, /*FiniteOnlyFuncs=*/true);
+ if (TT.isX86() || TT.isVE()) {
+if (ExceptionModel == ExceptionHandling::SjLj)
+ setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
+ }
+
// For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
if (TT.isPPC()) {
setLibcallName(RTLIB::ADD_F128, "__addkf3");
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index b5a0d26abbf8e..98c5fdd138986 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -298,8 +298,6 @@ void VETargetLowering::initSPUActions() {
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
- if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
-setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
/// } SJLJ instructions
// Intrinsic instructions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4751361c71f2c..defb7730b4c7d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -513,10 +513,6 @
