[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2], [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, - FeatureVIS2]>; + FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara2",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara3",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; def : Proc<"niagara4",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; koachan wrote: I usually refer to the supplement documents ([T1](https://www.oracle.com/docs/tech/systems/t1-09-ust1-uasuppl-draft-hp-ext.pdf) [T2](https://www.oracle.com/docs/tech/systems/t2-14-ust2-uasuppl-draft-hp-ext.pdf) [T3](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparct3-implem-supp-2516665.pdf) [T4](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/120214-t4-d04-p-ext-2305974.pdf) are the most relevant, there also exist [M5](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/140529-m5-d07-p-ext-2306120.pdf) and [M7](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-supplement-3093429.pdf) ones if we do get around to implement optimization/ISA extension support for those processors). https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -0,0 +1,36 @@
+//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===--===//
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
koachan wrote:
Yeah, it seems to be F3_1 but with anything past `op3` set to zero.
https://github.com/llvm/llvm-project/pull/138400
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[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)
@@ -19,3 +25,16 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
let Inst{18-0} = 0;
}
} // Predicates = [HasUA2005]
+
+// UltraSPARC Architecture 2007 Instructions
+let Predicates = [HasUA2007] in {
+def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
+def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
+def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
+def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
+
+def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
+def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
+def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
+def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
+} // Predicates = [HasUA2007]
koachan wrote:
I basically go by how Sun/Oracle classifies the extensions, meaning that
basically anything introduced in an ISA revision that isn't a VIS instruction
go here.
In case of FMAf, it sits in the weird spot in that it's introduced between VIS2
and VIS3, and since Sun doesn't classify it as a VIS instruction, that's also
the approach I took here.
This also goes for the one in the other PR, I suppose for crypto it makes sense
to separate it out since it is tagged separately in the documentations, but for
all others I think it's tidier if it's kept in this file?
https://github.com/llvm/llvm-project/pull/138401
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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #134033)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/134033
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[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #133050)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/133050 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #133050)
optimisan wrote: Stack updated manually: * #133050 * **#134033** https://app.graphite.dev/github/pr/llvm/llvm-project/134033?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#135752** https://app.graphite.dev/github/pr/llvm/llvm-project/135752?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/135752?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * `main` https://github.com/llvm/llvm-project/pull/133050 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [Clang] Fix the trailing comma regression (#136273) (PR #136283)
https://github.com/cor3ntin approved this pull request. Sorry, I was not near a computer last week. LGTM https://github.com/llvm/llvm-project/pull/136283 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -0,0 +1,36 @@
+//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===--===//
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
s-barannikov wrote:
Sparc instructions have well-defined formats, you should rarely need to use
`InstSP` as the base class, if ever.
`0b00010110001` should be broken down into `fcn=0b00010` (or decimal
equivalent) and `op3=0b110001`. `F3_1` looks the most appropriate base class of
all existing classes, but it may also make sense to introduce a new class for
this kind of instructions.
https://github.com/llvm/llvm-project/pull/138400
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[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2], [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, - FeatureVIS2]>; + FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara2",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara3",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; def : Proc<"niagara4",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; s-barannikov wrote: Can you point me to the documentation or other resources where I can make sure these processors support these instructions? https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)
@@ -19,3 +25,16 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
let Inst{18-0} = 0;
}
} // Predicates = [HasUA2005]
+
+// UltraSPARC Architecture 2007 Instructions
+let Predicates = [HasUA2007] in {
+def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
+def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
+def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
+def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
+
+def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
+def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
+def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
+def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
+} // Predicates = [HasUA2007]
s-barannikov wrote:
These are essentially VIS instructions, I would argue they should be placed in
`SparcInstrInfoVIS.td`.
I'm not sure I understand the motivation for putting this handful of
instructions into a separate file. What are the benefits?
They share encoding space with other related instructions, so it seems logical
to me to put them together with those instructions.
https://github.com/llvm/llvm-project/pull/138401
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[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)
@@ -38,3 +53,92 @@ def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
} // Predicates = [HasUA2007]
+
+// Oracle SPARC Architecture 2011 Instructions
+let Predicates = [HasOSA2011] in {
+let isBranch = 1, isTerminator = 1, hasDelaySlot = 0 in {
+defm CWBCOND : F2_56<"cwb", 0>;
+defm CXBCOND : F2_56<"cxb", 1>;
+}
+
+def FPMADDX : FourOp<"fpmaddx", 0b110111, 0b, DFPRegs>;
+def FPMADDXHI : FourOp<"fpmaddxhi", 0b110111, 0b0100, DFPRegs>;
+
+def AES_EROUND01 : FourOp<"aes_eround01", 0b011001, 0b, DFPRegs>;
s-barannikov wrote:
Contrary to my comments in other PRs in the stack, I think it is fine to put
these instructions in a separate file, as it is a new "class" of instructions
(cryptography). I wouldn't bind them to a specific extension name though,
something like `SparcInstrInfoCrypto.td` maybe?
Not a strong objection (in other PRs too), it is a personal PoV.
https://github.com/llvm/llvm-project/pull/138403
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