[llvm-branch-commits] [clang] release/20.x: [clang-format] RemoveParentheses shouldn't remove empty… (PR #138380)
https://github.com/owenca updated
https://github.com/llvm/llvm-project/pull/138380
>From 4b85fd08252bfe37382d4f9a7ecde898422830c7 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Fri, 2 May 2025 19:19:39 -0700
Subject: [PATCH 1/2] release/20.x: [clang-format] RemoveParentheses shouldn't
remove empty parentheses (#138229)
Backport d3506ee573a2aa1403817642ef45f8c0305bb572
---
clang/lib/Format/UnwrappedLineParser.cpp | 3 ++-
clang/unittests/Format/FormatTest.cpp| 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index 2b348c926294e..c3ffabce15ec8 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2581,7 +2581,8 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
if (Prev) {
auto OptionalParens = [&] {
if (MightBeStmtExpr || MightBeFoldExpr || Line->InMacroBody ||
- SeenComma || Style.RemoveParentheses == FormatStyle::RPS_Leave) {
+ SeenComma || Style.RemoveParentheses == FormatStyle::RPS_Leave ||
+ RParen->getPreviousNonComment() == LParen) {
return false;
}
const bool DoubleParens =
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index bf3eff129efd5..49e1fde1d9ccf 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -27895,6 +27895,8 @@ TEST_F(FormatTest, RemoveParentheses) {
verifyFormat("return ((... && std::is_convertible_v));",
"return (((... && std::is_convertible_v)));",
Style);
+ verifyFormat("MOCK_METHOD(void, Function, (), override);",
+ "MOCK_METHOD(void, Function, (), (override));", Style);
Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement;
verifyFormat("#define Return0 return (0);", Style);
>From 0e88d0b2e6c88c3996ec72f31e211c91976cb7b0 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Fri, 2 May 2025 19:20:42 -0700
Subject: [PATCH 2/2] release/20.x: [clang-format] Fix a crash on formatting
missing r_paren/r_brace (#138230)
Backport 79210feb2993ff9a79ef11f8a7016a527d4fcf22
---
clang/lib/Format/UnwrappedLineParser.cpp | 4 ++--
clang/unittests/Format/FormatTest.cpp| 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index c3ffabce15ec8..673b3e6c4b8c2 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -1837,8 +1837,8 @@ void UnwrappedLineParser::parseStructuralElement(
nextToken();
if (FormatTok->is(tok::l_paren)) {
parseParens();
-assert(FormatTok->Previous);
-if (FormatTok->Previous->endsSequence(tok::r_paren, tok::kw_auto,
+if (FormatTok->Previous &&
+FormatTok->Previous->endsSequence(tok::r_paren, tok::kw_auto,
tok::l_paren)) {
Line->SeenDecltypeAuto = true;
}
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index 49e1fde1d9ccf..90a79230e9f4c 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -13962,6 +13962,8 @@ TEST_F(FormatTest, IncorrectCodeUnbalancedBraces) {
verifyNoCrash("struct Foo {\n"
" operator foo(bar\n"
"};");
+ verifyNoCrash("decltype( {\n"
+" {");
}
TEST_F(FormatTest, IncorrectUnbalancedBracesInMacrosWithUnicode) {
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [clang-format] RemoveParentheses shouldn't remove empty… (PR #138380)
https://github.com/owenca updated
https://github.com/llvm/llvm-project/pull/138380
>From 4b85fd08252bfe37382d4f9a7ecde898422830c7 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Fri, 2 May 2025 19:19:39 -0700
Subject: [PATCH] release/20.x: [clang-format] RemoveParentheses shouldn't
remove empty parentheses (#138229)
Backport d3506ee573a2aa1403817642ef45f8c0305bb572
---
clang/lib/Format/UnwrappedLineParser.cpp | 3 ++-
clang/unittests/Format/FormatTest.cpp| 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index 2b348c926294e..c3ffabce15ec8 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2581,7 +2581,8 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
if (Prev) {
auto OptionalParens = [&] {
if (MightBeStmtExpr || MightBeFoldExpr || Line->InMacroBody ||
- SeenComma || Style.RemoveParentheses == FormatStyle::RPS_Leave) {
+ SeenComma || Style.RemoveParentheses == FormatStyle::RPS_Leave ||
+ RParen->getPreviousNonComment() == LParen) {
return false;
}
const bool DoubleParens =
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index bf3eff129efd5..49e1fde1d9ccf 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -27895,6 +27895,8 @@ TEST_F(FormatTest, RemoveParentheses) {
verifyFormat("return ((... && std::is_convertible_v));",
"return (((... && std::is_convertible_v)));",
Style);
+ verifyFormat("MOCK_METHOD(void, Function, (), override);",
+ "MOCK_METHOD(void, Function, (), (override));", Style);
Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement;
verifyFormat("#define Return0 return (0);", Style);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
https://github.com/s-barannikov commented: What about other instructions? (OTHERW, NORMALW, INVALWP) https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -0,0 +1,21 @@
+//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===--===//
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
s-barannikov wrote:
Can it be put next to SAVED/RESTORED in `SparcInstrInfo.td`?
https://github.com/llvm/llvm-project/pull/138400
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -0,0 +1,21 @@ +//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===// s-barannikov wrote: Copy&paste bug https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)
https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138399 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS][NFC] Rename CBCOND -> CPBCOND (PR #138402)
https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138402 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] release/20.x: [clang-tidy] Do not pass any file when listing checks in run_clang_ti… (#137286) (PR #137775)
https://github.com/PiotrZSL approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/137775 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] release/20.x: [clang-tidy] Do not pass any file when listing checks in run_clang_ti… (#137286) (PR #137775)
carlosgalvezp wrote: @HerrCai0907 Could you approve the PR so we can bring it to the release? https://github.com/llvm/llvm-project/pull/137775 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[clang] release/20.x: [clang-format] RemoveParentheses shouldn't remove empty… (PR #138380)
https://github.com/HazardyKnusperkeks approved this pull request. https://github.com/llvm/llvm-project/pull/138380 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)
https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138399 >From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138400 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)
@@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81) ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82) ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83) ELF_RELOC(R_SPARC_GOTDATA_OP, 84) +ELF_RELOC(R_SPARC_WDISP10, 88) koachan wrote: This is redundant with the one in PR #137916, will rebase once that one gets merged :) https://github.com/llvm/llvm-project/pull/138403 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)
koachan wrote: Ping? https://github.com/llvm/llvm-project/pull/135717 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)
koachan wrote: Ping? https://github.com/llvm/llvm-project/pull/135718 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)
llvmbot wrote:
@llvm/pr-subscribers-backend-sparc
Author: Koakuma (koachan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/138401.diff
6 Files Affected:
- (modified) llvm/lib/Target/Sparc/Sparc.td (+5-2)
- (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+17)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+4)
- (modified) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+20-1)
- (modified) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+20-1)
- (added) llvm/test/MC/Sparc/sparc-ua2007.s (+30)
``diff
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 0d66a03fd941d..93c3098bd89fe 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -52,6 +52,9 @@ def FeatureVIS3
def FeatureUA2005
: SubtargetFeature<"ua2005", "IsUA2005", "true",
"Enable UltraSPARC Architecture 2005 extensions">;
+def FeatureUA2007
+ : SubtargetFeature<"ua2007", "IsUA2007", "true",
+ "Enable UltraSPARC Architecture 2007 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
@@ -160,10 +163,10 @@ def : Proc<"niagara2",[FeatureV9,
FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara3",[FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
- FeatureUA2005]>;
+ FeatureUA2005, FeatureUA2007]>;
def : Proc<"niagara4",[FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
- FeatureUA2005]>;
+ FeatureUA2005, FeatureUA2007]>;
// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td
b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 4ff902b190a3b..2998f53ef2dbc 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -260,6 +260,23 @@ multiclass F3_S Op3Val, bit XVal,
SDNode OpNode,
itin>;
}
+// 4-operand instructions.
+class F3_4 op3val, bits<4> op5val, dag outs, dag ins,
+ string asmstr, list pattern = [], InstrItinClass itin =
NoItinerary>
+ : F3 {
+ bits<4> op5;
+ bits<5> rs3;
+ bits<5> rs2;
+
+ let op = 2;
+ let op3= op3val;
+ let op5= op5val;
+
+ let Inst{13-9} = rs3;
+ let Inst{8-5} = op5;
+ let Inst{4-0} = rs2;
+}
+
class F4 op3, dag outs, dag ins, string asmstr, list pattern,
InstrItinClass itin = NoItinerary>
: InstSP {
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index a220e0379213c..eb6485eaa3d98 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -51,6 +51,10 @@ def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
AssemblerPredicate<(all_of FeatureUA2005)>;
+// HasUA2007 - This is true when the target processor has UA 2007 extensions.
+def HasUA2007 : Predicate<"Subtarget->isUA2007()">,
+AssemblerPredicate<(all_of FeatureUA2007)>;
+
// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
index d883e517db89d..a1bfcc3dbb652 100644
--- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -7,9 +7,15 @@
//===--===//
//
// This file contains instruction formats, definitions and patterns needed for
-// UA 2005 instructions on SPARC.
+// UA 2005 and UA 2007 instructions on SPARC.
//===--===//
+// Convenience template for 4-operand instructions
+class FourOp op3val, bits<4> op5val,
+RegisterClass RC>
+ : F3_4;
+
// UltraSPARC Architecture 2005 Instructions
let Predicates = [HasUA2005] in {
let hasSideEffects = 1 in
@@ -19,3 +25,16 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
let Inst{18-0} = 0;
}
} // Predicates = [HasUA2005]
+
+// UltraSPARC Architecture 2007 Instructions
+let Predicates = [HasUA2007] in {
+def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
+def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
+def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
+def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
+
+def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
+def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
+def FNMSUBS : FourOp<"fnmsubs", 0b11
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Koakuma (koachan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/138401.diff
6 Files Affected:
- (modified) llvm/lib/Target/Sparc/Sparc.td (+5-2)
- (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+17)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+4)
- (modified) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+20-1)
- (modified) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+20-1)
- (added) llvm/test/MC/Sparc/sparc-ua2007.s (+30)
``diff
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 0d66a03fd941d..93c3098bd89fe 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -52,6 +52,9 @@ def FeatureVIS3
def FeatureUA2005
: SubtargetFeature<"ua2005", "IsUA2005", "true",
"Enable UltraSPARC Architecture 2005 extensions">;
+def FeatureUA2007
+ : SubtargetFeature<"ua2007", "IsUA2007", "true",
+ "Enable UltraSPARC Architecture 2007 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
@@ -160,10 +163,10 @@ def : Proc<"niagara2",[FeatureV9,
FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara3",[FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
- FeatureUA2005]>;
+ FeatureUA2005, FeatureUA2007]>;
def : Proc<"niagara4",[FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
- FeatureUA2005]>;
+ FeatureUA2005, FeatureUA2007]>;
// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td
b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 4ff902b190a3b..2998f53ef2dbc 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -260,6 +260,23 @@ multiclass F3_S Op3Val, bit XVal,
SDNode OpNode,
itin>;
}
+// 4-operand instructions.
+class F3_4 op3val, bits<4> op5val, dag outs, dag ins,
+ string asmstr, list pattern = [], InstrItinClass itin =
NoItinerary>
+ : F3 {
+ bits<4> op5;
+ bits<5> rs3;
+ bits<5> rs2;
+
+ let op = 2;
+ let op3= op3val;
+ let op5= op5val;
+
+ let Inst{13-9} = rs3;
+ let Inst{8-5} = op5;
+ let Inst{4-0} = rs2;
+}
+
class F4 op3, dag outs, dag ins, string asmstr, list pattern,
InstrItinClass itin = NoItinerary>
: InstSP {
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index a220e0379213c..eb6485eaa3d98 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -51,6 +51,10 @@ def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
AssemblerPredicate<(all_of FeatureUA2005)>;
+// HasUA2007 - This is true when the target processor has UA 2007 extensions.
+def HasUA2007 : Predicate<"Subtarget->isUA2007()">,
+AssemblerPredicate<(all_of FeatureUA2007)>;
+
// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
index d883e517db89d..a1bfcc3dbb652 100644
--- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -7,9 +7,15 @@
//===--===//
//
// This file contains instruction formats, definitions and patterns needed for
-// UA 2005 instructions on SPARC.
+// UA 2005 and UA 2007 instructions on SPARC.
//===--===//
+// Convenience template for 4-operand instructions
+class FourOp op3val, bits<4> op5val,
+RegisterClass RC>
+ : F3_4;
+
// UltraSPARC Architecture 2005 Instructions
let Predicates = [HasUA2005] in {
let hasSideEffects = 1 in
@@ -19,3 +25,16 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
let Inst{18-0} = 0;
}
} // Predicates = [HasUA2005]
+
+// UltraSPARC Architecture 2007 Instructions
+let Predicates = [HasUA2007] in {
+def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
+def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
+def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
+def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
+
+def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
+def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
+def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b100
[llvm-branch-commits] [SPARC][IAS][NFC] Rename CBCOND -> CPBCOND (PR #138402)
llvmbot wrote:
@llvm/pr-subscribers-backend-sparc
Author: Koakuma (koachan)
Changes
This is in prep for OSA2011 instruction definitions, which has a CBCond
instruction family.
---
Full diff: https://github.com/llvm/llvm-project/pull/138402.diff
3 Files Affected:
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp (+2-2)
- (modified) llvm/lib/Target/Sparc/SparcInstrAliases.td (+2-2)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+2-2)
``diff
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
index f2a61c95fefb5..42f3b9d3c4ce9 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
@@ -192,8 +192,8 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int
opNum,
// Make sure CC is a fp conditional flag.
CC = (CC < SPCC::FCC_BEGIN) ? (CC + SPCC::FCC_BEGIN) : CC;
break;
- case SP::CBCOND:
- case SP::CBCONDA:
+ case SP::CPBCOND:
+ case SP::CPBCONDA:
// Make sure CC is a cp conditional flag.
CC = (CC < SPCC::CPCC_BEGIN) ? (CC + SPCC::CPCC_BEGIN) : CC;
break;
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td
b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index bc57ddbb5682f..590395c16965b 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -286,11 +286,11 @@ multiclass cp_cond_alias {
// cb $imm
def : InstAlias;
+ (CPBCOND brtarget:$imm, condVal), 0>;
// cb,a $imm
def : InstAlias;
+ (CPBCONDA brtarget:$imm, condVal), 0>;
}
// Instruction aliases for register conditional branches and moves.
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index eb6485eaa3d98..057eafd734e71 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1028,10 +1028,10 @@ class CPBranchSPA
pattern>
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
-def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
+def CPBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
"cb$cond $imm22",
[(SPbrfcc bb:$imm22, imm:$cond)]>;
-def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
+def CPBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
"cb$cond,a $imm22", []>;
// Section B.24 - Call and Link Instruction, p. 125
``
https://github.com/llvm/llvm-project/pull/138402
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Koakuma (koachan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/138400.diff
5 Files Affected:
- (modified) llvm/lib/Target/Sparc/Sparc.td (+9-4)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+5)
- (added) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+21)
- (added) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+6)
- (added) llvm/test/MC/Sparc/sparc-ua2005.s (+8)
``diff
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 2083c0e763b82..0d66a03fd941d 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -49,6 +49,9 @@ def FeatureVIS2
def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true",
"Enable Visual Instruction Set extensions III">;
+def FeatureUA2005
+ : SubtargetFeature<"ua2005", "IsUA2005", "true",
+ "Enable UltraSPARC Architecture 2005 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9,
FeatureV8Deprecated, FeatureVIS,
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
- FeatureVIS2]>;
+ FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara2",[FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2]>;
+ FeatureVIS, FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara3",[FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+ FeatureVIS, FeatureVIS2, FeatureVIS3,
+ FeatureUA2005]>;
def : Proc<"niagara4",[FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+ FeatureVIS, FeatureVIS2, FeatureVIS3,
+ FeatureUA2005]>;
// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 0c890721da0f4..a220e0379213c 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
AssemblerPredicate<(all_of FeatureVIS3)>;
+// HasUA2005 - This is true when the target processor has UA 2005 extensions.
+def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
+AssemblerPredicate<(all_of FeatureUA2005)>;
+
// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
@@ -1968,4 +1972,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32
IntRegs:$a2)),
include "SparcInstr64Bit.td"
include "SparcInstrVIS.td"
+include "SparcInstrUAOSA.td"
include "SparcInstrAliases.td"
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
new file mode 100644
index 0..d883e517db89d
--- /dev/null
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -0,0 +1,21 @@
+//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===--===//
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
+let op = 2;
+let Inst{29-19} = 0b00010110001;
+let Inst{18-0} = 0;
+}
+} // Predicates = [HasUA2005]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
new file mode 100644
index 0..dc3d196091c6b
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 |
FileCheck %s
+
+## UA 2005 instructions.
+
+# CHECK: allclean
+0x85,0x88,0x00,0x00
diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s
b/llvm/test/MC/Sparc/sparc-ua2005.s
new file mode 100644
index 0..2214b91b335cd
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc-ua2005.s
@@ -0,0 +1,8 @@
+! RUN: not llvm-mc %s -triple=sparcv
[llvm-branch-commits] [SPARC][IAS][NFC] Rename CBCOND -> CPBCOND (PR #138402)
https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138402 This is in prep for OSA2011 instruction definitions, which has a CBCond instruction family. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)
https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138403 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)
llvmbot wrote: @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) Changes >From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. --- Full diff: https://github.com/llvm/llvm-project/pull/138399.diff 1 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+1-1) ``diff diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 8b1122741b661..2083c0e763b82 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -156,7 +156,7 @@ def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, def : Proc<"niagara2",[FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2]>; def : Proc<"niagara3",[FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureVIS3]>; def : Proc<"niagara4",[FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3]>; `` https://github.com/llvm/llvm-project/pull/138399 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)
https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138401 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)
llvmbot wrote:
@llvm/pr-subscribers-llvm-binary-utilities
Author: Koakuma (koachan)
Changes
---
Patch is 56.90 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/138403.diff
15 Files Affected:
- (modified) llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def (+1)
- (modified) llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (+9)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (+15)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp (+2)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h (+5-1)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp (+39)
- (modified) llvm/lib/Target/Sparc/Sparc.td (+4-1)
- (modified) llvm/lib/Target/Sparc/SparcInstrAliases.td (+65)
- (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+43)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+16)
- (modified) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+105-1)
- (modified) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+176-1)
- (added) llvm/test/MC/Sparc/sparc-osa2011.s (+274)
- (removed) llvm/test/MC/Sparc/sparc64-bpr-offset.s (-31)
- (added) llvm/test/MC/Sparc/sparc64-branch-offset.s (+267)
``diff
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
b/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
index 7e01a4a8a0a06..b87949ab199b5 100644
--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
@@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81)
ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82)
ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83)
ELF_RELOC(R_SPARC_GOTDATA_OP, 84)
+ELF_RELOC(R_SPARC_WDISP10, 88)
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index 828d638723587..c42e173379a39 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -261,6 +261,8 @@ DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
+static DecodeStatus DecodeSIMM5(MCInst &Inst, unsigned insn, uint64_t Address,
+const MCDisassembler *Decoder);
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
@@ -340,6 +342,13 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSIMM5(MCInst &MI, unsigned insn, uint64_t Address,
+const MCDisassembler *Decoder) {
+ assert(isUInt<5>(insn));
+ MI.addOperand(MCOperand::createImm(SignExtend64<5>(insn)));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<13>(insn));
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
index cc8b86e6135b5..d37724699be5d 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
@@ -50,6 +50,15 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t
Value) {
return (d16hi << 20) | d16lo;
}
+ case Sparc::fixup_sparc_br10: {
+// 7.17 Compare and Branch
+// Inst{20-19} = d10hi;
+// Inst{12-5} = d10lo;
+unsigned d10hi = (Value >> 10) & 0x3;
+unsigned d10lo = (Value >> 2) & 0xff;
+return (d10hi << 19) | (d10lo << 5);
+ }
+
case Sparc::fixup_sparc_hix22:
return (~Value >> 10) & 0x3f;
@@ -162,11 +171,13 @@ namespace {
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
+ // clang-format off
// nameoffset bits flags
{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br16", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_sparc_br10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_13",19, 13, 0 },
{ "fixup_sparc_hi22", 10, 22, 0 },
{ "fixup_sparc_lo10", 22, 10, 0 },
@@ -205,14 +216,17 @@ namespace {
{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
{ "fixup_sparc_gotdata_op", 0, 0, 0 },
+ // clang-format on
}
[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Koakuma (koachan)
Changes
---
Patch is 56.90 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/138403.diff
15 Files Affected:
- (modified) llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def (+1)
- (modified) llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (+9)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (+15)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp (+2)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h (+5-1)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp (+39)
- (modified) llvm/lib/Target/Sparc/Sparc.td (+4-1)
- (modified) llvm/lib/Target/Sparc/SparcInstrAliases.td (+65)
- (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+43)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+16)
- (modified) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+105-1)
- (modified) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+176-1)
- (added) llvm/test/MC/Sparc/sparc-osa2011.s (+274)
- (removed) llvm/test/MC/Sparc/sparc64-bpr-offset.s (-31)
- (added) llvm/test/MC/Sparc/sparc64-branch-offset.s (+267)
``diff
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
b/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
index 7e01a4a8a0a06..b87949ab199b5 100644
--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
@@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81)
ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82)
ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83)
ELF_RELOC(R_SPARC_GOTDATA_OP, 84)
+ELF_RELOC(R_SPARC_WDISP10, 88)
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index 828d638723587..c42e173379a39 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -261,6 +261,8 @@ DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
+static DecodeStatus DecodeSIMM5(MCInst &Inst, unsigned insn, uint64_t Address,
+const MCDisassembler *Decoder);
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
@@ -340,6 +342,13 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSIMM5(MCInst &MI, unsigned insn, uint64_t Address,
+const MCDisassembler *Decoder) {
+ assert(isUInt<5>(insn));
+ MI.addOperand(MCOperand::createImm(SignExtend64<5>(insn)));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<13>(insn));
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
index cc8b86e6135b5..d37724699be5d 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
@@ -50,6 +50,15 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t
Value) {
return (d16hi << 20) | d16lo;
}
+ case Sparc::fixup_sparc_br10: {
+// 7.17 Compare and Branch
+// Inst{20-19} = d10hi;
+// Inst{12-5} = d10lo;
+unsigned d10hi = (Value >> 10) & 0x3;
+unsigned d10lo = (Value >> 2) & 0xff;
+return (d10hi << 19) | (d10lo << 5);
+ }
+
case Sparc::fixup_sparc_hix22:
return (~Value >> 10) & 0x3f;
@@ -162,11 +171,13 @@ namespace {
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
+ // clang-format off
// nameoffset bits flags
{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br16", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_sparc_br10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_13",19, 13, 0 },
{ "fixup_sparc_hi22", 10, 22, 0 },
{ "fixup_sparc_lo10", 22, 10, 0 },
@@ -205,14 +216,17 @@ namespace {
{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
{ "fixup_sparc_gotdata_op", 0, 0, 0 },
+ // clang-format on
};
const st
[llvm-branch-commits] [lld] [LLD][COFF] Don't dllimport from static libraries (#134443) (PR #138354)
https://github.com/mstorsjo approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138354 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)
@@ -3613,13 +3613,15 @@ bool SparcTargetLowering::isFNegFree(EVT VT) const {
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
+ bool CanLower = false;
if (VT != MVT::f32 && VT != MVT::f64)
return false;
- if (Imm.isZero())
-return Subtarget->isVIS();
- if (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5))
-return Subtarget->isVIS3();
- return false;
+ if (Subtarget->isVIS())
+CanLower = CanLower || Imm.isZero();
arsenm wrote:
```suggestion
if (Subtarget->isVIS() mm.isZero())
return true;
```
Did this mean to include -0?
https://github.com/llvm/llvm-project/pull/135718
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)
@@ -3613,13 +3613,15 @@ bool SparcTargetLowering::isFNegFree(EVT VT) const {
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
+ bool CanLower = false;
if (VT != MVT::f32 && VT != MVT::f64)
return false;
- if (Imm.isZero())
-return Subtarget->isVIS();
- if (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5))
-return Subtarget->isVIS3();
- return false;
+ if (Subtarget->isVIS())
+CanLower = CanLower || Imm.isZero();
+ if (Subtarget->isVIS3())
+CanLower =
+CanLower || (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5));
+ return CanLower;
arsenm wrote:
```suggestion
if (Subtarget->isVIS3())
return Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5);
return false;
```
Could also use getExactLog2Abs == -1?
https://github.com/llvm/llvm-project/pull/135718
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)
@@ -3613,13 +3613,15 @@ bool SparcTargetLowering::isFNegFree(EVT VT) const {
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
+ bool CanLower = false;
arsenm wrote:
```suggestion
```
https://github.com/llvm/llvm-project/pull/135718
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [llvm] Introduce callee_type metadata (PR #87573)
@@ -1302,6 +1302,26 @@ static void addRange(SmallVectorImpl
&EndPoints,
EndPoints.push_back(High);
}
+MDNode *MDNode::getMergedCalleeTypeMetadata(LLVMContext &Ctx, MDNode *A,
+MDNode *B) {
+ SmallVector AB;
+ SmallSet MergedCallees;
+ auto AddUniqueCallees = [&](llvm::MDNode *N) {
ilovepi wrote:
can you specify the captures explicitly?
https://github.com/llvm/llvm-project/pull/87573
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [llvm] Introduce callee_type metadata (PR #87573)
@@ -5096,6 +5097,23 @@ void Verifier::visitCallsiteMetadata(Instruction &I,
MDNode *MD) {
visitCallStackMetadata(MD);
}
+void Verifier::visitCalleeTypeMetadata(Instruction &I, MDNode *MD) {
+ Check(isa(I), "!callee_type metadata should only exist on calls",
+&I);
+ CallBase *CB = cast(&I);
+ Check(CB->isIndirectCall(),
+"!callee_type metadata should only exist on indirect function calls",
+&I);
+ for (const auto &Op : MD->operands()) {
ilovepi wrote:
nit:
```suggestion
for (const Operand &Op : MD->operands()) {
```
https://github.com/llvm/llvm-project/pull/87573
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/138400
>From b2e8de55ea9e54239a017eb932f7107f29f465a4 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Sun, 4 May 2025 08:57:07 +0700
Subject: [PATCH] Add other instructions & fix typo
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrUAOSA.td| 17 -
.../test/MC/Disassembler/Sparc/sparc-ua-osa.txt | 6 ++
llvm/test/MC/Sparc/sparc-ua2005.s | 9 +
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
index d883e517db89d..5ecc02ed10bfb 100644
--- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -1,4 +1,4 @@
-//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===//
+//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions
===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -18,4 +18,19 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
let Inst{29-19} = 0b00010110001;
let Inst{18-0} = 0;
}
+def INVALW : InstSP<(outs), (ins), "invalw", []> {
+let op = 2;
+let Inst{29-19} = 0b00101110001;
+let Inst{18-0} = 0;
+}
+def NORMALW : InstSP<(outs), (ins), "normalw", []> {
+let op = 2;
+let Inst{29-19} = 0b00100110001;
+let Inst{18-0} = 0;
+}
+def OTHERW : InstSP<(outs), (ins), "otherw", []> {
+let op = 2;
+let Inst{29-19} = 0b0000001;
+let Inst{18-0} = 0;
+}
} // Predicates = [HasUA2005]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
index dc3d196091c6b..4a2de98e03fe3 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
@@ -4,3 +4,9 @@
# CHECK: allclean
0x85,0x88,0x00,0x00
+# CHECK: invalw
+0x8b,0x88,0x00,0x00
+# CHECK: otherw
+0x87,0x88,0x00,0x00
+# CHECK: normalw
+0x89,0x88,0x00,0x00
diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s
b/llvm/test/MC/Sparc/sparc-ua2005.s
index 2214b91b335cd..b07c99a20033b 100644
--- a/llvm/test/MC/Sparc/sparc-ua2005.s
+++ b/llvm/test/MC/Sparc/sparc-ua2005.s
@@ -6,3 +6,12 @@
! NO-UA2005: error: instruction requires a CPU feature not currently enabled
! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00]
allclean
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: invalw ! encoding: [0x8b,0x88,0x00,0x00]
+invalw
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: otherw ! encoding: [0x87,0x88,0x00,0x00]
+otherw
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: normalw! encoding: [0x89,0x88,0x00,0x00]
+normalw
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [llvm] Introduce callee_type metadata (PR #87573)
@@ -1302,6 +1302,26 @@ static void addRange(SmallVectorImpl
&EndPoints,
EndPoints.push_back(High);
}
+MDNode *MDNode::getMergedCalleeTypeMetadata(LLVMContext &Ctx, MDNode *A,
+MDNode *B) {
+ SmallVector AB;
+ SmallSet MergedCallees;
+ auto AddUniqueCallees = [&](llvm::MDNode *N) {
+if (!N)
+ return;
+for (const MDOperand &Op : N->operands()) {
+ Metadata *MD = Op.get();
+ if (!MergedCallees.contains(MD)) {
+MergedCallees.insert(MD);
+AB.push_back(MD);
ilovepi wrote:
`SmallSet::inesert(()` returns `pair`, so you don't need to use
`contains()`
```suggestion
if ( MergedCallees.contains(MD).second) {
AB.push_back(MD);
```
https://github.com/llvm/llvm-project/pull/87573
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/135718
>From 50422a4d24403ef55bf76ccd710511e8dec6b77d Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Sun, 4 May 2025 09:33:39 +0700
Subject: [PATCH] Rework isFPImmLegal
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcISelLowering.cpp | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 68c523709d38d..727857b647acc 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3613,15 +3613,14 @@ bool SparcTargetLowering::isFNegFree(EVT VT) const {
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
- bool CanLower = false;
if (VT != MVT::f32 && VT != MVT::f64)
return false;
- if (Subtarget->isVIS())
-CanLower = CanLower || Imm.isZero();
+ if (Subtarget->isVIS() && Imm.isZero())
+return true;
if (Subtarget->isVIS3())
-CanLower =
-CanLower || (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5));
- return CanLower;
+return Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5) ||
+ Imm.getExactLog2Abs() == -1;
+ return false;
}
bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/138399
>From 8618666abc7028770617cd77adfc83c61550dbd0 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Sat, 3 May 2025 20:50:21 +0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?=
=?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.5
[skip ci]
---
llvm/lib/Target/Sparc/SparcInstr64Bit.td | 30 +++---
llvm/lib/Target/Sparc/SparcInstrInfo.td | 32
2 files changed, 19 insertions(+), 43 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 372ab80a3bb71..5dc19144bebe9 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
//===--===//
let Predicates = [Is64Bit] in {
-
-def MULXrr : F3_1<2, 0b001001,
- (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
- "mulx $rs1, $rs2, $rd",
- [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
-def MULXri : F3_2<2, 0b001001,
- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
- "mulx $rs1, $simm13, $rd",
- [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
+defm MULX: F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;
// Division can trap.
let hasSideEffects = 1 in {
-def SDIVXrr : F3_1<2, 0b101101,
- (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
- "sdivx $rs1, $rs2, $rd",
- [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
-def SDIVXri : F3_2<2, 0b101101,
- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
- "sdivx $rs1, $simm13, $rd",
- [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
-
-def UDIVXrr : F3_1<2, 0b001101,
- (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
- "udivx $rs1, $rs2, $rd",
- [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
-def UDIVXri : F3_2<2, 0b001101,
- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
- "udivx $rs1, $simm13, $rd",
- [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
+defm SDIVX: F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;
+defm UDIVX: F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;
} // hasSideEffects = 1
-
} // Predicates = [Is64Bit]
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 02f4b202e9645..0c890721da0f4 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -467,22 +467,6 @@ multiclass LoadA Op3Val, bits<6>
LoadAOp3Val,
defm A : LoadASI;
}
-
-// The LDSTUB instruction is supported for asm only.
-// It is unlikely that general-purpose code could make use of it.
-// CAS is preferred for sparc v9.
-def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1,
$rs2):$addr),
-"ldstub [$addr], $rd", []>;
-def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1,
$simm13):$addr),
-"ldstub [$addr], $rd", []>;
-def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
- (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
- "ldstuba [$addr] $asi, $rd", []>;
-let Predicates = [HasV9], Uses = [ASR3] in
-def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
- (ins (MEMri $rs1, $simm13):$addr),
- "ldstuba [$addr] %asi, $rd", []>;
-
// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
multiclass Store Op3Val, SDPatternOperator OpNode,
RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
@@ -740,6 +724,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in {
"stx %fsr, [$addr]", []>, Requires<[HasV9]>;
}
+// B.7. Atomic Load-Store Unsigned Byte Instructions
+// (Atomic test-and-set)
+// TODO look into the possibility to use this to implment `atomic_flag`.
+// If it's possible, then LDSTUB is the preferred way to do it.
+def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1,
$rs2):$addr),
+"ldstub [$addr], $rd", []>;
+def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1,
$simm13):$addr),
+"ldstub [$addr], $rd", []>;
+def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
+ (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
+ "ldstuba [$addr] $asi, $rd", []>;
+let Predicates = [HasV9], Uses = [ASR3] in
[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)
@@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81) ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82) ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83) ELF_RELOC(R_SPARC_GOTDATA_OP, 84) +ELF_RELOC(R_SPARC_WDISP10, 88) alexrp wrote: Don't worry too much about it FWIW, I'll just resolve the conflicts if this one happens to be merged first. https://github.com/llvm/llvm-project/pull/138403 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
@@ -0,0 +1,21 @@
+//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===--===//
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
koachan wrote:
I prefer for these to be kept here in a separate file, especially since the
other patches are adding more ISA extension instructions to this file.
https://github.com/llvm/llvm-project/pull/138400
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)
@@ -3613,13 +3613,15 @@ bool SparcTargetLowering::isFNegFree(EVT VT) const {
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
+ bool CanLower = false;
if (VT != MVT::f32 && VT != MVT::f64)
return false;
- if (Imm.isZero())
-return Subtarget->isVIS();
- if (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5))
-return Subtarget->isVIS3();
- return false;
+ if (Subtarget->isVIS())
+CanLower = CanLower || Imm.isZero();
koachan wrote:
Yes, +0 and -0.
https://github.com/llvm/llvm-project/pull/135718
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)
koachan wrote: > What about other instructions? (OTHERW, NORMALW, INVALWP) Added, thanks! https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
