[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 9985dc44013cce96c62847c91a6a07f56b295094 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
and deprecate RISCVToolchain object
This patch:
- Adds CXXStdlib, runtimelib and unwindlib defaults for riscv target to
BareMetal toolchain object.
- Add riscv 32 and 64-bit emulation flags to linker job of BareMetal
toolchain.
- Removes call to RISCVToolChain object from llvm.
This PR is last patch in the series of patches of merging RISCVToolchain
object into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I2877ac328f55a7638cc185d6034866cbd2ac4203
---
clang/lib/Driver/CMakeLists.txt | 1 -
clang/lib/Driver/Driver.cpp | 10 +-
clang/lib/Driver/ToolChains/BareMetal.cpp | 33 ++-
clang/lib/Driver/ToolChains/BareMetal.h | 11 +-
.../lib/Driver/ToolChains/RISCVToolchain.cpp | 232 --
clang/lib/Driver/ToolChains/RISCVToolchain.h | 67 -
.../test/Driver/baremetal-undefined-symbols.c | 14 +-
clang/test/Driver/baremetal.cpp | 44 ++--
clang/test/Driver/riscv32-toolchain-extra.c | 7 +-
clang/test/Driver/riscv32-toolchain.c | 26 +-
clang/test/Driver/riscv64-toolchain-extra.c | 7 +-
clang/test/Driver/riscv64-toolchain.c | 20 +-
12 files changed, 91 insertions(+), 381 deletions(-)
delete mode 100644 clang/lib/Driver/ToolChains/RISCVToolchain.cpp
delete mode 100644 clang/lib/Driver/ToolChains/RISCVToolchain.h
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 5bdb6614389cf..eee29af5d181a 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -74,7 +74,6 @@ add_clang_library(clangDriver
ToolChains/OHOS.cpp
ToolChains/OpenBSD.cpp
ToolChains/PS4CPU.cpp
- ToolChains/RISCVToolchain.cpp
ToolChains/Solaris.cpp
ToolChains/SPIRV.cpp
ToolChains/SPIRVOpenMP.cpp
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 056bfcf1b739a..82b49da928a79 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -41,7 +41,6 @@
#include "ToolChains/PPCFreeBSD.h"
#include "ToolChains/PPCLinux.h"
#include "ToolChains/PS4CPU.h"
-#include "ToolChains/RISCVToolchain.h"
#include "ToolChains/SPIRV.h"
#include "ToolChains/SPIRVOpenMP.h"
#include "ToolChains/SYCL.h"
@@ -6886,16 +6885,11 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::msp430:
-TC =
-std::make_unique(*this, Target, Args);
+TC = std::make_unique(*this, Target,
Args);
break;
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
-if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
- TC =
- std::make_unique(*this, Target,
Args);
-else
- TC = std::make_unique(*this, Target, Args);
+TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::ve:
TC = std::make_unique(*this, Target, Args);
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 508c2bbb2339e..8e721aa72d9c5 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::RLT_Libgcc;
+ return ToolChain::RLT_CompilerRT;
+}
+
+ToolChain::UnwindLibType
+BareMetal::GetUnwindLibType(const llvm::opt::ArgList &Args) const {
+ if (getTriple().isRISCV())
+return ToolChain::UNW_None;
+
+ return ToolChain::GetUnwindLibType(Args);
+}
+
void BareMetal::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
ArgStringList &CC1Args) const {
if (DriverArgs.hasArg(options::OPT_nostdinc))
@@ -534,8 +554,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+ CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+
[llvm-branch-commits] [clang] [Driver] Forward sysroot from Driver to linker in BareMetal ToolChain Object (PR #132808)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132808
>From 7aef889e3fbd5140a484a1f0d56832cd7bd192a7 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 07:04:59 -0700
Subject: [PATCH] [Driver] Forward sysroot from Driver to linker in BareMetal
ToolChain Object
RISCVToolChain object passes `--sysroot` option from clang to gnuld. Adding
the supprt for the same in BareMetal toolchain object.
This is done as a part of the effort to merge RISCVToolchain object into
BareMetal toolchain object.
This is the 5th patch in the series of patches for merging RISCVToolchain object
into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: Ie830bf6d126fea46dc225e5ef97e14349765ba07
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 3 +
clang/test/Driver/aarch64-toolchain.c | 5 +-
clang/test/Driver/arm-toolchain.c | 3 +
clang/test/Driver/baremetal.cpp | 96 +--
4 files changed, 82 insertions(+), 25 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index edf9ecc728282..508c2bbb2339e 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -529,6 +529,9 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
+ if (!D.SysRoot.empty())
+CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
+
CmdArgs.push_back("-Bstatic");
if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
diff --git a/clang/test/Driver/aarch64-toolchain.c
b/clang/test/Driver/aarch64-toolchain.c
index 121e335466dce..38b94cbc57066 100644
--- a/clang/test/Driver/aarch64-toolchain.c
+++ b/clang/test/Driver/aarch64-toolchain.c
@@ -17,6 +17,7 @@
// C-AARCH64-BAREMETAL: "-isysroot"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// C-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// C-AARCH64-BAREMETAL:
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// C-AARCH64-BAREMETAL: "-Bstatic" "-EL"
// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o"
// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o"
@@ -53,6 +54,7 @@
// CXX-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1"
// CXX-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
// CXX-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// CXX-AARCH64-BAREMETAL:
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// CXX-AARCH64-BAREMETAL: "-Bstatic" "-EL"
// CXX-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o"
// CXX-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o"
@@ -89,7 +91,8 @@
// CXX-AARCH64-BAREMETAL-LIBCXX: "-isysroot"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// CXX-AARCH64-BAREMETAL-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/v1"
// CXX-AARCH64-BAREMETAL-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
-// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld
+// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// CXX-AARCH64-BAREMETAL-LIBCXX:
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// CXX-AARCH64-BAREMETAL-LIBCXX: "-Bstatic" "-EL"
// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o"
// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o"
diff --git a/clang/test/Driver/arm-toolchain.c
b/clang/test/Driver/arm-toolchain.c
index d89f77b86c23b..ac4fe8d2271fb 100644
--- a/clang/test/Driver/arm-toolchain.c
+++ b/clang/test/Driver/arm-toolchain.c
@@ -17,6 +17,7 @@
// C-ARM-BAREMETAL: "-isysroot"
"{{.*}}Inputs/basic_arm_gcc_tree/armv6m-none-eabi"
// C-ARM-BAREMETAL: "-internal-isystem"
"{{.*}}Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include"
// C-ARM-BAREMETAL:
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../bin/armv6m-none-eabi-ld"
+// C-ARM-BAREMETAL:
"--sysroot={{.*}}/Inputs/basic_arm_gc
[llvm-branch-commits] [clang] [Driver] Fix link order of BareMetal toolchain object (PR #132806)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132806
>From 66c86ddfd852b3f70aa5fde9002ef0d6e5735274 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:17:42 -0700
Subject: [PATCH] [Driver] Fix link order of BareMetal toolchain object
The linker job in BareMetal toolchain object will be used by gnuld and lld both.
However, gnuld process the arguments in the order in which they appear on
command
line, whereas there is no such restriction with lld.
The previous order was:
LibraryPaths -> Libraries -> LTOOptions -> LinkerInputs
The new iorder is:
LibraryPaths -> LTOOptions -> LinkerInputs -> Libraries
LTO options need to be added before adding any linker inputs because file format
after compile stage during LTO is bitcode which gnuld natively cannot process.
Hence iwill need to pass appropriate plugins before adding any bitcode file on
the
command line.
Object files that are getting linked need to be passed before processing any
libraries so that gnuld can appropriately do symbol resolution for the symbols
for which no definition is provided through user code.
Similar link order is also followed by other linker jobs for gnuld such as in
gnutools::Linker in Gnu.cpp
This is the 3rd patch in the series of patches of merging RISCVToolchain into
BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I0e68e403c08b5687cc3346e833981f7b9f3819c4
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 32 -
clang/test/Driver/aarch64-toolchain-extra.c | 2 +-
clang/test/Driver/aarch64-toolchain.c | 24 +++
clang/test/Driver/arm-toolchain-extra.c | 2 +-
clang/test/Driver/arm-toolchain.c | 24 +++
clang/test/Driver/baremetal-multilib.yaml | 3 +-
clang/test/Driver/baremetal-sysroot.cpp | 8 ++-
clang/test/Driver/baremetal.cpp | 79 +
8 files changed, 98 insertions(+), 76 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 7ec6d86d998a4..919fc6fe71178 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -529,8 +529,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
- AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA);
-
CmdArgs.push_back("-Bstatic");
if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
@@ -576,6 +574,22 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
for (const auto &LibPath : TC.getLibraryPaths())
CmdArgs.push_back(Args.MakeArgString(llvm::Twine("-L", LibPath)));
+ if (D.isUsingLTO()) {
+assert(!Inputs.empty() && "Must have at least one input.");
+// Find the first filename InputInfo object.
+auto Input = llvm::find_if(
+Inputs, [](const InputInfo &II) -> bool { return II.isFilename(); });
+if (Input == Inputs.end())
+ // For a very rare case, all of the inputs to the linker are
+ // InputArg. If that happens, just use the first InputInfo.
+ Input = Inputs.begin();
+
+addLTOOptions(TC, Args, CmdArgs, Output, *Input,
+ D.getLTOMode() == LTOK_Thin);
+ }
+
+ AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA);
+
if (TC.ShouldLinkCXXStdlib(Args)) {
bool OnlyLibstdcxxStatic = Args.hasArg(options::OPT_static_libstdcxx) &&
!Args.hasArg(options::OPT_static);
@@ -596,20 +610,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("--end-group");
}
- if (D.isUsingLTO()) {
-assert(!Inputs.empty() && "Must have at least one input.");
-// Find the first filename InputInfo object.
-auto Input = llvm::find_if(
-Inputs, [](const InputInfo &II) -> bool { return II.isFilename(); });
-if (Input == Inputs.end())
- // For a very rare case, all of the inputs to the linker are
- // InputArg. If that happens, just use the first InputInfo.
- Input = Inputs.begin();
-
-addLTOOptions(TC, Args, CmdArgs, Output, *Input,
- D.getLTOMode() == LTOK_Thin);
- }
-
if ((TC.hasValidGCCInstallation() || hasGCCToolChainAlongSideClang(D)) &&
WantCRTs)
CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(crtend)));
diff --git a/clang/test/Driver/aarch64-toolchain-extra.c
b/clang/test/Driver/aarch64-toolchain-extra.c
index 2a930e35acd45..a0b5f2902962f 100644
--- a/clang/test/Driver/aarch64-toolchain-extra.c
+++ b/clang/test/Driver/aarch64-toolchain-extra.c
@@ -31,5 +31,5 @@
// C-AARCH64-BAREMETAL-NOGCC:
"{{.*}}/aarch64-nogcc/bin/../aarch64-none-elf/lib/crt0.o"
// C-AARCH64-BAREMETAL-NOGCC:
"{{.*}}/aarch64-nogcc/{{.*}}/aarch64-none-elf/lib/crtbegin.o"
// C-AARCH64-BAREMETAL-NOGCC:
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 5efd1f2166deb15c7a8de505c7851954d7e31c71 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
and deprecate RISCVToolchain object
This patch:
- Adds CXXStdlib, runtimelib and unwindlib defaults for riscv target to
BareMetal toolchain object.
- Add riscv 32 and 64-bit emulation flags to linker job of BareMetal
toolchain.
- Removes call to RISCVToolChain object from llvm.
This PR is last patch in the series of patches of merging RISCVToolchain
object into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I2877ac328f55a7638cc185d6034866cbd2ac4203
---
clang/lib/Driver/CMakeLists.txt | 1 -
clang/lib/Driver/Driver.cpp | 10 +-
clang/lib/Driver/ToolChains/BareMetal.cpp | 33 ++-
clang/lib/Driver/ToolChains/BareMetal.h | 11 +-
.../lib/Driver/ToolChains/RISCVToolchain.cpp | 232 --
clang/lib/Driver/ToolChains/RISCVToolchain.h | 67 -
.../test/Driver/baremetal-undefined-symbols.c | 14 +-
clang/test/Driver/baremetal.cpp | 44 ++--
clang/test/Driver/riscv32-toolchain-extra.c | 7 +-
clang/test/Driver/riscv32-toolchain.c | 26 +-
clang/test/Driver/riscv64-toolchain-extra.c | 7 +-
clang/test/Driver/riscv64-toolchain.c | 20 +-
12 files changed, 91 insertions(+), 381 deletions(-)
delete mode 100644 clang/lib/Driver/ToolChains/RISCVToolchain.cpp
delete mode 100644 clang/lib/Driver/ToolChains/RISCVToolchain.h
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 5bdb6614389cf..eee29af5d181a 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -74,7 +74,6 @@ add_clang_library(clangDriver
ToolChains/OHOS.cpp
ToolChains/OpenBSD.cpp
ToolChains/PS4CPU.cpp
- ToolChains/RISCVToolchain.cpp
ToolChains/Solaris.cpp
ToolChains/SPIRV.cpp
ToolChains/SPIRVOpenMP.cpp
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 056bfcf1b739a..82b49da928a79 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -41,7 +41,6 @@
#include "ToolChains/PPCFreeBSD.h"
#include "ToolChains/PPCLinux.h"
#include "ToolChains/PS4CPU.h"
-#include "ToolChains/RISCVToolchain.h"
#include "ToolChains/SPIRV.h"
#include "ToolChains/SPIRVOpenMP.h"
#include "ToolChains/SYCL.h"
@@ -6886,16 +6885,11 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::msp430:
-TC =
-std::make_unique(*this, Target, Args);
+TC = std::make_unique(*this, Target,
Args);
break;
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
-if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
- TC =
- std::make_unique(*this, Target,
Args);
-else
- TC = std::make_unique(*this, Target, Args);
+TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::ve:
TC = std::make_unique(*this, Target, Args);
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 508c2bbb2339e..8e721aa72d9c5 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::RLT_Libgcc;
+ return ToolChain::RLT_CompilerRT;
+}
+
+ToolChain::UnwindLibType
+BareMetal::GetUnwindLibType(const llvm::opt::ArgList &Args) const {
+ if (getTriple().isRISCV())
+return ToolChain::UNW_None;
+
+ return ToolChain::GetUnwindLibType(Args);
+}
+
void BareMetal::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
ArgStringList &CC1Args) const {
if (DriverArgs.hasArg(options::OPT_nostdinc))
@@ -534,8 +554,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+ CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+
[llvm-branch-commits] [clang] [llvm] [Driver] Forward sysroot from Driver to linker in BareMetal ToolChain Object (PR #132808)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132808
>From 6480848c32fad1fc9f69ff1d445bbb7932afd428 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 07:04:59 -0700
Subject: [PATCH] [Driver] Forward sysroot from Driver to linker in BareMetal
ToolChain Object
RISCVToolChain object passes `--sysroot` option from clang to gnuld. Adding
the supprt for the same in BareMetal toolchain object.
This is done as a part of the effort to merge RISCVToolchain object into
BareMetal toolchain object.
This is the 5th patch in the series of patches for merging RISCVToolchain object
into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: Ie830bf6d126fea46dc225e5ef97e14349765ba07
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 3 +
clang/test/Driver/aarch64-toolchain.c | 5 +-
clang/test/Driver/arm-toolchain.c | 3 +
clang/test/Driver/baremetal.cpp | 96 +--
tatus | 59 ++
5 files changed, 141 insertions(+), 25 deletions(-)
create mode 100644 tatus
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index edf9ecc728282..508c2bbb2339e 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -529,6 +529,9 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
+ if (!D.SysRoot.empty())
+CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
+
CmdArgs.push_back("-Bstatic");
if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
diff --git a/clang/test/Driver/aarch64-toolchain.c
b/clang/test/Driver/aarch64-toolchain.c
index 121e335466dce..38b94cbc57066 100644
--- a/clang/test/Driver/aarch64-toolchain.c
+++ b/clang/test/Driver/aarch64-toolchain.c
@@ -17,6 +17,7 @@
// C-AARCH64-BAREMETAL: "-isysroot"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// C-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// C-AARCH64-BAREMETAL:
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// C-AARCH64-BAREMETAL: "-Bstatic" "-EL"
// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o"
// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o"
@@ -53,6 +54,7 @@
// CXX-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1"
// CXX-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
// CXX-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// CXX-AARCH64-BAREMETAL:
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// CXX-AARCH64-BAREMETAL: "-Bstatic" "-EL"
// CXX-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o"
// CXX-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o"
@@ -89,7 +91,8 @@
// CXX-AARCH64-BAREMETAL-LIBCXX: "-isysroot"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// CXX-AARCH64-BAREMETAL-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/v1"
// CXX-AARCH64-BAREMETAL-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
-// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld
+// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// CXX-AARCH64-BAREMETAL-LIBCXX:
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// CXX-AARCH64-BAREMETAL-LIBCXX: "-Bstatic" "-EL"
// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o"
// CXX-AARCH64-BAREMETAL-LIBCXX:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o"
diff --git a/clang/test/Driver/arm-toolchain.c
b/clang/test/Driver/arm-toolchain.c
index d89f77b86c23b..ac4fe8d2271fb 100644
--- a/clang/test/Driver/arm-toolchain.c
+++ b/clang/test/Driver/arm-toolchain.c
@@ -17,6 +17,7 @@
// C-ARM-BAREMETAL: "-isysroot"
"{{.*}}Inputs/basic_arm_gcc_tree/armv6m-none-eabi"
// C-ARM-BAREMETAL: "-internal-isystem"
"{{.*}}Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include"
// C-ARM-BAREMETAL:
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../
[llvm-branch-commits] [clang] [Driver] Add option to force undefined symbols during linking in BareMetal toolchain object. (PR #132807)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132807
>From 22c7d24f4e27a907306bef8f946946ff80c1d48f Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:49:09 -0700
Subject: [PATCH] [Driver] Add option to force udnefined symbols during linking
in BareMetal toolchain object.
Add support for `-u` option to force defined symbols. This option is supported
by both lld and gnuld.
This is done as a part of the effort to merge RISCVToolchain object into
BareMetal toolchain object.
This is the 4th patch in the series of patches for merging RISCVToolchain object
into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: Ia6597c756923a77fd9c7cb9a6ae8e52a56f5457d
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 5 +++--
clang/test/Driver/baremetal-undefined-symbols.c | 15 +++
clang/test/Driver/riscv-args.c | 6 --
3 files changed, 18 insertions(+), 8 deletions(-)
create mode 100644 clang/test/Driver/baremetal-undefined-symbols.c
delete mode 100644 clang/test/Driver/riscv-args.c
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 919fc6fe71178..edf9ecc728282 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -566,8 +566,9 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
}
}
- Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_T_Group,
-options::OPT_s, options::OPT_t, options::OPT_r});
+ Args.addAllArgs(CmdArgs,
+ {options::OPT_L, options::OPT_u, options::OPT_T_Group,
+ options::OPT_s, options::OPT_t, options::OPT_r});
TC.AddFilePathLibArgs(Args, CmdArgs);
diff --git a/clang/test/Driver/baremetal-undefined-symbols.c
b/clang/test/Driver/baremetal-undefined-symbols.c
new file mode 100644
index 0..0ce0db43bccad
--- /dev/null
+++ b/clang/test/Driver/baremetal-undefined-symbols.c
@@ -0,0 +1,15 @@
+// Check the arguments are correctly passed
+
+// Make sure -T is the last with gcc-toolchain option
+// RUN: %clang -### --target=riscv32 --gcc-toolchain= -Xlinker --defsym=FOO=10
-T a.lds -u foo %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-LD %s
+// CHECK-LD: {{.*}} "--defsym=FOO=10" {{.*}} "-u" "foo" {{.*}} "-T" "a.lds"
+
+// TODO: Merge this test with the above in the last patch when finally
integrating riscv
+// Make sure -T is the last with gcc-toolchain option
+// RUN: %clang -### --target=aarch64-none-elf --gcc-toolchain= -Xlinker
--defsym=FOO=10 -T a.lds -u foo %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-ARM-LD %s
+// RUN: %clang -### --target=armv6m-none-eabi --gcc-toolchain= -Xlinker
--defsym=FOO=10 -T a.lds -u foo %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-ARM-LD %s
+// CHECK-ARM-LD: {{.*}} "-T" "a.lds" "-u" "foo" {{.*}} "--defsym=FOO=10"
+
diff --git a/clang/test/Driver/riscv-args.c b/clang/test/Driver/riscv-args.c
deleted file mode 100644
index cab08e5b0f811..0
--- a/clang/test/Driver/riscv-args.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// Check the arguments are correctly passed
-
-// Make sure -T is the last with gcc-toolchain option
-// RUN: %clang -### --target=riscv32 --gcc-toolchain= -Xlinker --defsym=FOO=10
-T a.lds -u foo %s 2>&1 \
-// RUN: | FileCheck -check-prefix=CHECK-LD %s
-// CHECK-LD: {{.*}} "--defsym=FOO=10" {{.*}} "-u" "foo" {{.*}} "-T" "a.lds"
___
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[llvm-branch-commits] [clang] [llvm] [Driver] Forward sysroot from Driver to linker in BareMetal ToolChain Object (PR #132808)
@@ -16,7 +16,7 @@
// C-AARCH64-BAREMETAL: "-cc1" "-triple" "aarch64-unknown-none-elf"
// C-AARCH64-BAREMETAL: "-isysroot"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// C-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include"
-// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
+// C-AARCH64-BAREMETAL:
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../bin/aarch64-none-elf-ld"
"--sysroot={{.*}}/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
quic-garvgupt wrote:
fixed!
https://github.com/llvm/llvm-project/pull/132808
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[llvm-branch-commits] [clang] ecde8c2 - [clang] fix matching of nested template template parameters
Author: Matheus Izvekov
Date: 2025-03-25T16:56:10-07:00
New Revision: ecde8c235e5e09ff71789725c96416f8daf93cd7
URL:
https://github.com/llvm/llvm-project/commit/ecde8c235e5e09ff71789725c96416f8daf93cd7
DIFF:
https://github.com/llvm/llvm-project/commit/ecde8c235e5e09ff71789725c96416f8daf93cd7.diff
LOG: [clang] fix matching of nested template template parameters
When checking the template template parameters of template template
parameters, the PartialOrdering context was not correctly propagated.
This also has a few drive-by fixes, such as checking the template parameter
lists of template template parameters, which was previously missing and
would have been it's own bug, but we need to fix it in order to
prevent crashes in error recovery in a simple way.
Fixes #130362
Backport of: https://github.com/llvm/llvm-project/pull/130447
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaDeclCXX.cpp
clang/lib/Sema/SemaTemplate.cpp
clang/lib/Sema/SemaTemplateDeduction.cpp
clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
clang/test/SemaTemplate/cwg2398.cpp
clang/test/SemaTemplate/temp_arg_template_p0522.cpp
clang/unittests/AST/DeclPrinterTest.cpp
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 955325026f369..c921ac3518f01 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1058,6 +1058,9 @@ Bug Fixes to C++ Support
- Fixed a substitution bug in transforming CTAD aliases when the type alias
contains a non-pack template argument
corresponding to a pack parameter (#GH124715)
- Clang is now better at keeping track of friend function template instance
contexts. (#GH55509)
+- Fixes matching of nested template template parameters. (#GH130362)
+- Correctly diagnoses template template paramters which have a pack parameter
+ not in the last position.
- Fixed an integer overflow bug in computing template parameter depths when
synthesizing CTAD guides. (#GH128691)
- Fixed an incorrect pointer access when checking access-control on concepts.
(#GH131530)
- Fixed various alias CTAD bugs involving variadic template arguments.
(#GH123591), (#GH127539), (#GH129077),
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index cecf5cff332f4..d8cc0171c22c6 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -11279,14 +11279,16 @@ class Sema final : public SemaBase {
/// The context in which we are checking a template parameter list.
enum TemplateParamListContext {
-TPC_ClassTemplate,
-TPC_VarTemplate,
+// For this context, Class, Variable, TypeAlias, and non-pack Template
+// Template Parameters are treated uniformly.
+TPC_Other,
+
TPC_FunctionTemplate,
TPC_ClassTemplateMember,
TPC_FriendClassTemplate,
TPC_FriendFunctionTemplate,
TPC_FriendFunctionTemplateDefinition,
-TPC_TypeAliasTemplate
+TPC_TemplateTemplateParameterPack,
};
/// Checks the validity of a template parameter list, possibly
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index f70401ea33b4a..41d5f9f2f3420 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8145,7 +8145,7 @@ NamedDecl *Sema::ActOnVariableDeclarator(
(D.getCXXScopeSpec().isSet() && DC && DC->isRecord() &&
DC->isDependentContext())
? TPC_ClassTemplateMember
- : TPC_VarTemplate))
+ : TPC_Other))
NewVD->setInvalidDecl();
// If we are providing an explicit specialization of a static variable
diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp
index e4e3bbad1f520..85de46c9adab4 100644
--- a/clang/lib/Sema/SemaDeclCXX.cpp
+++ b/clang/lib/Sema/SemaDeclCXX.cpp
@@ -13533,7 +13533,7 @@ Decl *Sema::ActOnAliasDeclaration(Scope *S,
AccessSpecifier AS,
// Merge any previous default template arguments into our parameters,
// and check the parameter list.
if (CheckTemplateParameterList(TemplateParams, OldTemplateParams,
- TPC_TypeAliasTemplate))
+ TPC_Other))
return nullptr;
TypeAliasTemplateDecl *NewDecl =
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 938671055333c..1c555b38277b0 100644
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -1591,8 +1591,16 @@ NamedDecl *Sema::ActOnTemplateTemplateParameter(
assert(S->isTemplateParamScope() &&
"Template template parameter not in template parameter scope!");
- // Construct the parameter object.
bool IsParameterPack = EllipsisLoc.isValid();
+
+ bool Invalid = false;
+ if (CheckTemplateParameterLis
[llvm-branch-commits] [clang] Backport: [clang] fix matching of nested template template parameters (PR #130950)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/130950 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/20.x: [rtsan][Apple] Add interceptor for _os_nospin_lock_lock (#131034) (PR #132997)
llvmbot wrote: @cjappl What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/132997 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
https://github.com/snehasish edited https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] fcd0ad2 - [AArch64] Add test for scalar copysign. NFC
Author: David Green
Date: 2025-03-25T15:52:20-07:00
New Revision: fcd0ad23f668bce4b3a3731c5baa115434dc3269
URL:
https://github.com/llvm/llvm-project/commit/fcd0ad23f668bce4b3a3731c5baa115434dc3269
DIFF:
https://github.com/llvm/llvm-project/commit/fcd0ad23f668bce4b3a3731c5baa115434dc3269.diff
LOG: [AArch64] Add test for scalar copysign. NFC
(cherry picked from commit 4c2d1b4c53def85e16d3612b92379a347d76baf0)
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
Removed:
diff --git
a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
index 2282e74af5d00..238c124b7cb06 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
@@ -8,6 +8,234 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
+define void @test_copysign_f16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_f16:
+; SVE: // %bb.0:
+; SVE-NEXT:adrp x8, .LCPI0_0
+; SVE-NEXT:ldr h1, [x0]
+; SVE-NEXT:ldr h2, [x1]
+; SVE-NEXT:ldr q0, [x8, :lo12:.LCPI0_0]
+; SVE-NEXT:adrp x8, .LCPI0_1
+; SVE-NEXT:ldr q4, [x8, :lo12:.LCPI0_1]
+; SVE-NEXT:mov z3.d, z0.d
+; SVE-NEXT:fmov s0, s1
+; SVE-NEXT:fmov s3, s2
+; SVE-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE-NEXT:str h0, [x0]
+; SVE-NEXT:ret
+;
+; SVE2-LABEL: test_copysign_f16:
+; SVE2: // %bb.0:
+; SVE2-NEXT:adrp x8, .LCPI0_0
+; SVE2-NEXT:ldr h1, [x0]
+; SVE2-NEXT:ldr h2, [x1]
+; SVE2-NEXT:ldr q0, [x8, :lo12:.LCPI0_0]
+; SVE2-NEXT:adrp x8, .LCPI0_1
+; SVE2-NEXT:ldr q4, [x8, :lo12:.LCPI0_1]
+; SVE2-NEXT:mov z3.d, z0.d
+; SVE2-NEXT:fmov s0, s1
+; SVE2-NEXT:fmov s3, s2
+; SVE2-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE2-NEXT:str h0, [x0]
+; SVE2-NEXT:ret
+;
+; NONEON-NOSVE-LABEL: test_copysign_f16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT:sub sp, sp, #16
+; NONEON-NOSVE-NEXT:.cfi_def_cfa_offset 16
+; NONEON-NOSVE-NEXT:ldr h0, [x0]
+; NONEON-NOSVE-NEXT:ldr h1, [x1]
+; NONEON-NOSVE-NEXT:fcvt s0, h0
+; NONEON-NOSVE-NEXT:str h1, [sp, #12]
+; NONEON-NOSVE-NEXT:ldrb w8, [sp, #13]
+; NONEON-NOSVE-NEXT:tst w8, #0x80
+; NONEON-NOSVE-NEXT:fabs s0, s0
+; NONEON-NOSVE-NEXT:fneg s1, s0
+; NONEON-NOSVE-NEXT:fcsel s0, s1, s0, ne
+; NONEON-NOSVE-NEXT:fcvt h0, s0
+; NONEON-NOSVE-NEXT:str h0, [x0]
+; NONEON-NOSVE-NEXT:add sp, sp, #16
+; NONEON-NOSVE-NEXT:ret
+ %a = load half, ptr %ap
+ %b = load half, ptr %bp
+ %r = call half @llvm.copysign.f16(half %a, half %b)
+ store half %r, ptr %ap
+ ret void
+}
+
+define void @test_copysign_bf16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_bf16:
+; SVE: // %bb.0:
+; SVE-NEXT:adrp x8, .LCPI1_0
+; SVE-NEXT:ldr h1, [x0]
+; SVE-NEXT:ldr h2, [x1]
+; SVE-NEXT:ldr q0, [x8, :lo12:.LCPI1_0]
+; SVE-NEXT:adrp x8, .LCPI1_1
+; SVE-NEXT:ldr q4, [x8, :lo12:.LCPI1_1]
+; SVE-NEXT:mov z3.d, z0.d
+; SVE-NEXT:fmov s0, s1
+; SVE-NEXT:fmov s3, s2
+; SVE-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE-NEXT:str h0, [x0]
+; SVE-NEXT:ret
+;
+; SVE2-LABEL: test_copysign_bf16:
+; SVE2: // %bb.0:
+; SVE2-NEXT:adrp x8, .LCPI1_0
+; SVE2-NEXT:ldr h1, [x0]
+; SVE2-NEXT:ldr h2, [x1]
+; SVE2-NEXT:ldr q0, [x8, :lo12:.LCPI1_0]
+; SVE2-NEXT:adrp x8, .LCPI1_1
+; SVE2-NEXT:ldr q4, [x8, :lo12:.LCPI1_1]
+; SVE2-NEXT:mov z3.d, z0.d
+; SVE2-NEXT:fmov s0, s1
+; SVE2-NEXT:fmov s3, s2
+; SVE2-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE2-NEXT:str h0, [x0]
+; SVE2-NEXT:ret
+;
+; NONEON-NOSVE-LABEL: test_copysign_bf16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT:sub sp, sp, #80
+; NONEON-NOSVE-NEXT:.cfi_def_cfa_offset 80
+; NONEON-NOSVE-NEXT:ldr h0, [x0]
+; NONEON-NOSVE-NEXT:ldr h1, [x1]
+; NONEON-NOSVE-NEXT:str h0, [sp, #40]
+; NONEON-NOSVE-NEXT:ldr d0, [sp, #40]
+; NONEON-NOSVE-NEXT:str h1, [sp, #76]
+; NONEON-NOSVE-NEXT:ushll v0.4s, v0.4h, #0
+; NONEON-NOSVE-NEXT:str q0, [sp]
+; NONEON-NOSVE-NEXT:ldr w8, [sp, #12]
+; NONEON-NOSVE-NEXT:lsl w9, w8, #16
+; NONEON-NOSVE-NEXT:ldr w8, [sp, #8]
+; NONEON-NOSVE-NEXT:lsl w8, w8, #16
+; NONEON-NOSVE-NEXT:stp w8, w9, [sp, #24]
+; NONEON-NOSVE-NEXT:ldr w8, [sp, #4]
+; NONEON-NOSVE-NEXT:lsl w9, w8, #16
+; NONEON-NOSVE-NEXT:ldr w8, [sp]
+; NONEON-NOSVE-NEXT:lsl w8, w8, #16
+; NONEON-NOSVE-NEXT:stp w8, w9, [sp, #16]
+; NONEON-NOSVE-NEXT:ldrb w8, [sp, #77]
+; NONEON-NOSVE-NEXT:ldr q0, [sp, #16]
+; NONEON-NOSVE-NEXT:tst w8, #0x80
+; NONEON-NOSVE-NEXT:str q0, [sp, #48]
+; NONEON-NOSVE-NEXT:ldr s0, [sp, #48]
+; NONEON-NOSVE-NEXT:fabs s0, s0
[llvm-branch-commits] [llvm] dc7b743 - [AArch64] Fix SVE scalar fcopysign lowering without neon. (#129787)
Author: David Green
Date: 2025-03-25T15:52:21-07:00
New Revision: dc7b743515d3a463465dd38a62869ab9f77704cd
URL:
https://github.com/llvm/llvm-project/commit/dc7b743515d3a463465dd38a62869ab9f77704cd
DIFF:
https://github.com/llvm/llvm-project/commit/dc7b743515d3a463465dd38a62869ab9f77704cd.diff
LOG: [AArch64] Fix SVE scalar fcopysign lowering without neon. (#129787)
Without this we can try to generate invalid instructions or create
illegal types. This patch generates a SVE fcopysign instead and use its
lowering. BF16 is left out of the moment as it doesn't lower
successfully (but could use the same code as fp16).
(cherry picked from commit d4ab3df320f9eebf11cc5fb600a0919f93678abe)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 16fcd589cecd1..cfd0fc32357ce 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10683,6 +10683,25 @@ SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue
Op,
return convertFromScalableVector(DAG, VT, Res);
}
+ // With SVE, but without Neon, extend the scalars to scalable vectors and use
+ // a SVE FCOPYSIGN.
+ if (!VT.isVector() && !Subtarget->isNeonAvailable() &&
+ Subtarget->isSVEorStreamingSVEAvailable()) {
+if (VT != MVT::f16 && VT != MVT::f32 && VT != MVT::f64)
+ return SDValue();
+EVT SVT = getPackedSVEVectorVT(VT);
+
+SDValue Ins1 =
+DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, SVT, DAG.getUNDEF(SVT), In1,
+DAG.getConstant(0, DL, MVT::i64));
+SDValue Ins2 =
+DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, SVT, DAG.getUNDEF(SVT), In2,
+DAG.getConstant(0, DL, MVT::i64));
+SDValue FCS = DAG.getNode(ISD::FCOPYSIGN, DL, SVT, Ins1, Ins2);
+return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, FCS,
+ DAG.getConstant(0, DL, MVT::i64));
+ }
+
auto BitCast = [this](EVT VT, SDValue Op, SelectionDAG &DAG) {
if (VT.isScalableVector())
return getSVESafeBitCast(VT, Op, DAG);
diff --git
a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
index 238c124b7cb06..79921e25caf53 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
@@ -11,32 +11,21 @@ target triple = "aarch64-unknown-linux-gnu"
define void @test_copysign_f16(ptr %ap, ptr %bp) {
; SVE-LABEL: test_copysign_f16:
; SVE: // %bb.0:
-; SVE-NEXT:adrp x8, .LCPI0_0
+; SVE-NEXT:ldr h0, [x1]
; SVE-NEXT:ldr h1, [x0]
-; SVE-NEXT:ldr h2, [x1]
-; SVE-NEXT:ldr q0, [x8, :lo12:.LCPI0_0]
-; SVE-NEXT:adrp x8, .LCPI0_1
-; SVE-NEXT:ldr q4, [x8, :lo12:.LCPI0_1]
-; SVE-NEXT:mov z3.d, z0.d
-; SVE-NEXT:fmov s0, s1
-; SVE-NEXT:fmov s3, s2
-; SVE-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE-NEXT:and z0.h, z0.h, #0x8000
+; SVE-NEXT:and z1.h, z1.h, #0x7fff
+; SVE-NEXT:orr z0.d, z1.d, z0.d
; SVE-NEXT:str h0, [x0]
; SVE-NEXT:ret
;
; SVE2-LABEL: test_copysign_f16:
; SVE2: // %bb.0:
-; SVE2-NEXT:adrp x8, .LCPI0_0
-; SVE2-NEXT:ldr h1, [x0]
-; SVE2-NEXT:ldr h2, [x1]
-; SVE2-NEXT:ldr q0, [x8, :lo12:.LCPI0_0]
-; SVE2-NEXT:adrp x8, .LCPI0_1
-; SVE2-NEXT:ldr q4, [x8, :lo12:.LCPI0_1]
-; SVE2-NEXT:mov z3.d, z0.d
-; SVE2-NEXT:fmov s0, s1
-; SVE2-NEXT:fmov s3, s2
-; SVE2-NEXT:bif v0.16b, v3.16b, v4.16b
-; SVE2-NEXT:str h0, [x0]
+; SVE2-NEXT:mov z0.h, #32767 // =0x7fff
+; SVE2-NEXT:ldr h1, [x1]
+; SVE2-NEXT:ldr h2, [x0]
+; SVE2-NEXT:bsl z2.d, z2.d, z1.d, z0.d
+; SVE2-NEXT:str h2, [x0]
; SVE2-NEXT:ret
;
; NONEON-NOSVE-LABEL: test_copysign_f16:
@@ -66,32 +55,40 @@ define void @test_copysign_f16(ptr %ap, ptr %bp) {
define void @test_copysign_bf16(ptr %ap, ptr %bp) {
; SVE-LABEL: test_copysign_bf16:
; SVE: // %bb.0:
-; SVE-NEXT:adrp x8, .LCPI1_0
-; SVE-NEXT:ldr h1, [x0]
-; SVE-NEXT:ldr h2, [x1]
-; SVE-NEXT:ldr q0, [x8, :lo12:.LCPI1_0]
-; SVE-NEXT:adrp x8, .LCPI1_1
-; SVE-NEXT:ldr q4, [x8, :lo12:.LCPI1_1]
-; SVE-NEXT:mov z3.d, z0.d
-; SVE-NEXT:fmov s0, s1
-; SVE-NEXT:fmov s3, s2
-; SVE-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE-NEXT:sub sp, sp, #16
+; SVE-NEXT:.cfi_def_cfa_offset 16
+; SVE-NEXT:ldr h0, [x0]
+; SVE-NEXT:ldr h1, [x1]
+; SVE-NEXT:fmov w8, s0
+; SVE-NEXT:str h1, [sp, #12]
+; SVE-NEXT:ldrb w9, [sp, #13]
+; SVE-NEXT:and w8, w8, #0x7fff
+; SVE-NEXT:tst w9, #0x80
+; SVE-NEXT:fmov s0, w8
+; SVE-NEXT:eor w8, w8, #0x8000
+; SVE
[llvm-branch-commits] [llvm] release/20.x: [AArch64] Fix SVE scalar fcopysign lowering without neon. (#129787) (PR #129997)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/129997 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64] Fix SVE scalar fcopysign lowering without neon. (#129787) (PR #129997)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/129997
>From fcd0ad23f668bce4b3a3731c5baa115434dc3269 Mon Sep 17 00:00:00 2001
From: David Green
Date: Tue, 4 Mar 2025 21:46:55 +
Subject: [PATCH 1/2] [AArch64] Add test for scalar copysign. NFC
(cherry picked from commit 4c2d1b4c53def85e16d3612b92379a347d76baf0)
---
...e-streaming-mode-fixed-length-fcopysign.ll | 228 ++
1 file changed, 228 insertions(+)
diff --git
a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
index 2282e74af5d00..238c124b7cb06 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
@@ -8,6 +8,234 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
+define void @test_copysign_f16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_f16:
+; SVE: // %bb.0:
+; SVE-NEXT:adrp x8, .LCPI0_0
+; SVE-NEXT:ldr h1, [x0]
+; SVE-NEXT:ldr h2, [x1]
+; SVE-NEXT:ldr q0, [x8, :lo12:.LCPI0_0]
+; SVE-NEXT:adrp x8, .LCPI0_1
+; SVE-NEXT:ldr q4, [x8, :lo12:.LCPI0_1]
+; SVE-NEXT:mov z3.d, z0.d
+; SVE-NEXT:fmov s0, s1
+; SVE-NEXT:fmov s3, s2
+; SVE-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE-NEXT:str h0, [x0]
+; SVE-NEXT:ret
+;
+; SVE2-LABEL: test_copysign_f16:
+; SVE2: // %bb.0:
+; SVE2-NEXT:adrp x8, .LCPI0_0
+; SVE2-NEXT:ldr h1, [x0]
+; SVE2-NEXT:ldr h2, [x1]
+; SVE2-NEXT:ldr q0, [x8, :lo12:.LCPI0_0]
+; SVE2-NEXT:adrp x8, .LCPI0_1
+; SVE2-NEXT:ldr q4, [x8, :lo12:.LCPI0_1]
+; SVE2-NEXT:mov z3.d, z0.d
+; SVE2-NEXT:fmov s0, s1
+; SVE2-NEXT:fmov s3, s2
+; SVE2-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE2-NEXT:str h0, [x0]
+; SVE2-NEXT:ret
+;
+; NONEON-NOSVE-LABEL: test_copysign_f16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT:sub sp, sp, #16
+; NONEON-NOSVE-NEXT:.cfi_def_cfa_offset 16
+; NONEON-NOSVE-NEXT:ldr h0, [x0]
+; NONEON-NOSVE-NEXT:ldr h1, [x1]
+; NONEON-NOSVE-NEXT:fcvt s0, h0
+; NONEON-NOSVE-NEXT:str h1, [sp, #12]
+; NONEON-NOSVE-NEXT:ldrb w8, [sp, #13]
+; NONEON-NOSVE-NEXT:tst w8, #0x80
+; NONEON-NOSVE-NEXT:fabs s0, s0
+; NONEON-NOSVE-NEXT:fneg s1, s0
+; NONEON-NOSVE-NEXT:fcsel s0, s1, s0, ne
+; NONEON-NOSVE-NEXT:fcvt h0, s0
+; NONEON-NOSVE-NEXT:str h0, [x0]
+; NONEON-NOSVE-NEXT:add sp, sp, #16
+; NONEON-NOSVE-NEXT:ret
+ %a = load half, ptr %ap
+ %b = load half, ptr %bp
+ %r = call half @llvm.copysign.f16(half %a, half %b)
+ store half %r, ptr %ap
+ ret void
+}
+
+define void @test_copysign_bf16(ptr %ap, ptr %bp) {
+; SVE-LABEL: test_copysign_bf16:
+; SVE: // %bb.0:
+; SVE-NEXT:adrp x8, .LCPI1_0
+; SVE-NEXT:ldr h1, [x0]
+; SVE-NEXT:ldr h2, [x1]
+; SVE-NEXT:ldr q0, [x8, :lo12:.LCPI1_0]
+; SVE-NEXT:adrp x8, .LCPI1_1
+; SVE-NEXT:ldr q4, [x8, :lo12:.LCPI1_1]
+; SVE-NEXT:mov z3.d, z0.d
+; SVE-NEXT:fmov s0, s1
+; SVE-NEXT:fmov s3, s2
+; SVE-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE-NEXT:str h0, [x0]
+; SVE-NEXT:ret
+;
+; SVE2-LABEL: test_copysign_bf16:
+; SVE2: // %bb.0:
+; SVE2-NEXT:adrp x8, .LCPI1_0
+; SVE2-NEXT:ldr h1, [x0]
+; SVE2-NEXT:ldr h2, [x1]
+; SVE2-NEXT:ldr q0, [x8, :lo12:.LCPI1_0]
+; SVE2-NEXT:adrp x8, .LCPI1_1
+; SVE2-NEXT:ldr q4, [x8, :lo12:.LCPI1_1]
+; SVE2-NEXT:mov z3.d, z0.d
+; SVE2-NEXT:fmov s0, s1
+; SVE2-NEXT:fmov s3, s2
+; SVE2-NEXT:bif v0.16b, v3.16b, v4.16b
+; SVE2-NEXT:str h0, [x0]
+; SVE2-NEXT:ret
+;
+; NONEON-NOSVE-LABEL: test_copysign_bf16:
+; NONEON-NOSVE: // %bb.0:
+; NONEON-NOSVE-NEXT:sub sp, sp, #80
+; NONEON-NOSVE-NEXT:.cfi_def_cfa_offset 80
+; NONEON-NOSVE-NEXT:ldr h0, [x0]
+; NONEON-NOSVE-NEXT:ldr h1, [x1]
+; NONEON-NOSVE-NEXT:str h0, [sp, #40]
+; NONEON-NOSVE-NEXT:ldr d0, [sp, #40]
+; NONEON-NOSVE-NEXT:str h1, [sp, #76]
+; NONEON-NOSVE-NEXT:ushll v0.4s, v0.4h, #0
+; NONEON-NOSVE-NEXT:str q0, [sp]
+; NONEON-NOSVE-NEXT:ldr w8, [sp, #12]
+; NONEON-NOSVE-NEXT:lsl w9, w8, #16
+; NONEON-NOSVE-NEXT:ldr w8, [sp, #8]
+; NONEON-NOSVE-NEXT:lsl w8, w8, #16
+; NONEON-NOSVE-NEXT:stp w8, w9, [sp, #24]
+; NONEON-NOSVE-NEXT:ldr w8, [sp, #4]
+; NONEON-NOSVE-NEXT:lsl w9, w8, #16
+; NONEON-NOSVE-NEXT:ldr w8, [sp]
+; NONEON-NOSVE-NEXT:lsl w8, w8, #16
+; NONEON-NOSVE-NEXT:stp w8, w9, [sp, #16]
+; NONEON-NOSVE-NEXT:ldrb w8, [sp, #77]
+; NONEON-NOSVE-NEXT:ldr q0, [sp, #16]
+; NONEON-NOSVE-NEXT:tst w8, #0x80
+; NONEON-NOSVE-NEXT:str q0, [sp, #48]
+; NONEON-NOSVE-NEXT:ldr s0, [sp, #48]
+; NONEON-NOSVE-NEXT:fabs s0, s0
+; NONEON-NOSVE-NEXT:fneg s1, s0
+; NONEON-NOSVE-NEXT:fcsel s0, s1, s0, ne
+; NONEON-NOSVE-NEXT:fmov w8, s0
+; NONEON-NOSVE-NEXT:lsr w8, w8,
[llvm-branch-commits] [compiler-rt] release/20.x: XFAIL malloc_zone.cpp for darwin/lsan (#131234) (PR #133006)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/133006 Backport ab58a3c35b6fc6a4b513d75c38881134f5b2c9b9 Requested by: @wrotki >From 50c746f024a9d6ddbbef2a2a89f6cd62540e9435 Mon Sep 17 00:00:00 2001 From: Mariusz Borsa Date: Thu, 13 Mar 2025 16:01:32 -0700 Subject: [PATCH] XFAIL malloc_zone.cpp for darwin/lsan (#131234) Silence darwin bot while we investigate the problem rdar://145873843 Co-authored-by: Mariusz Borsa (cherry picked from commit ab58a3c35b6fc6a4b513d75c38881134f5b2c9b9) --- .../test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp b/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp index fd6ef03629438..e68e93129be2f 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp @@ -17,6 +17,8 @@ // UBSan does not install a malloc zone. // XFAIL: ubsan // +// Curently fails on darwin/lsan rdar://145873843 +// XFAIL: darwin && lsan #include #include ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824) (PR #132932)
github-actions[bot] wrote: @phoebewang (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/132932 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] release/20.x: [LLD] [COFF] Add a few more mingw libs to skip autoexports for (#132289) (PR #132478)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/132478
>From 66825a89b8e0e9e1d202cb4d3824791b81afdc98 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Storsj=C3=B6?=
Date: Fri, 21 Mar 2025 15:33:25 +0200
Subject: [PATCH] [LLD] [COFF] Add a few more mingw libs to skip autoexports
for (#132289)
"libmsvcrt-os" was added to the list of excluded libs in binutils in
9d9c67b06c1bf4c4550e3de0eb575c2bfbe96df9 in 2017.
"libucrt" was added in c4a8df19ba0a82aa8dea88d9f72ed9e63cb1fa84 in 2022.
"libucrtapp" isn't in the binutils exclusion list yet, but a patch for
adding it has been submitted. Since
0d403d5dd13ce22c07418058f3b640708992890c in mingw-w64 (in 2020), there's
such a third variant of the UCRT import library available.
Since 18df3e8323dcf9fdfec56b5f12c04a9c723a0931 in 2025, "libpthread" and
"libwinpthread" are also excluded.
(cherry picked from commit af93db9344919085551fac38d6d6a4f774a7220a)
---
lld/COFF/MinGW.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/lld/COFF/MinGW.cpp b/lld/COFF/MinGW.cpp
index 76f5a0a7500b9..097cf228f7d6e 100644
--- a/lld/COFF/MinGW.cpp
+++ b/lld/COFF/MinGW.cpp
@@ -54,7 +54,12 @@ AutoExporter::AutoExporter(
"libFortranDecimal",
"libunwind",
"libmsvcrt",
+ "libmsvcrt-os",
"libucrtbase",
+ "libucrt",
+ "libucrtapp",
+ "libpthread",
+ "libwinpthread",
};
excludeObjects = {
___
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llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [lld] release/20.x: [LLD] [COFF] Add a few more mingw libs to skip autoexports for (#132289) (PR #132478)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/132478 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] 66825a8 - [LLD] [COFF] Add a few more mingw libs to skip autoexports for (#132289)
Author: Martin Storsjö
Date: 2025-03-25T13:15:01-07:00
New Revision: 66825a89b8e0e9e1d202cb4d3824791b81afdc98
URL:
https://github.com/llvm/llvm-project/commit/66825a89b8e0e9e1d202cb4d3824791b81afdc98
DIFF:
https://github.com/llvm/llvm-project/commit/66825a89b8e0e9e1d202cb4d3824791b81afdc98.diff
LOG: [LLD] [COFF] Add a few more mingw libs to skip autoexports for (#132289)
"libmsvcrt-os" was added to the list of excluded libs in binutils in
9d9c67b06c1bf4c4550e3de0eb575c2bfbe96df9 in 2017.
"libucrt" was added in c4a8df19ba0a82aa8dea88d9f72ed9e63cb1fa84 in 2022.
"libucrtapp" isn't in the binutils exclusion list yet, but a patch for
adding it has been submitted. Since
0d403d5dd13ce22c07418058f3b640708992890c in mingw-w64 (in 2020), there's
such a third variant of the UCRT import library available.
Since 18df3e8323dcf9fdfec56b5f12c04a9c723a0931 in 2025, "libpthread" and
"libwinpthread" are also excluded.
(cherry picked from commit af93db9344919085551fac38d6d6a4f774a7220a)
Added:
Modified:
lld/COFF/MinGW.cpp
Removed:
diff --git a/lld/COFF/MinGW.cpp b/lld/COFF/MinGW.cpp
index 76f5a0a7500b9..097cf228f7d6e 100644
--- a/lld/COFF/MinGW.cpp
+++ b/lld/COFF/MinGW.cpp
@@ -54,7 +54,12 @@ AutoExporter::AutoExporter(
"libFortranDecimal",
"libunwind",
"libmsvcrt",
+ "libmsvcrt-os",
"libucrtbase",
+ "libucrt",
+ "libucrtapp",
+ "libpthread",
+ "libwinpthread",
};
excludeObjects = {
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[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
@@ -577,6 +577,16 @@ class MCPlusBuilder {
return getNoRegister();
}
+ /// Returns the register used as call destination, or no-register, if not
+ /// an indirect call. Sets IsAuthenticatedInternally if the instruction
+ /// accepts signed pointer as its operand and authenticates it internally.
kbeyls wrote:
maybe s/accepts signed pointer/accepts a signed pointer/?
https://github.com/llvm/llvm-project/pull/131899
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[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824) (PR #132932)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/132932 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/20.x: [rtsan][Apple] Add interceptor for _os_nospin_lock_lock (#131034) (PR #132997)
https://github.com/wrotki closed https://github.com/llvm/llvm-project/pull/132997 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/20.x: [rtsan][Apple] Add interceptor for _os_nospin_lock_lock (#131034) (PR #132997)
wrotki wrote: @cjappl I misunderstood @thetruestblue 's request, she asked me to cherry-pick XFAIL on the test, not your change. Apologies - I'll let you cherry-pick this yourself once you decide it's ready 🙂 https://github.com/llvm/llvm-project/pull/132997 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang][OpenMP] Add AST node for root of compound directive (PR #118878)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/118878
>From 1447ec21597f752b29e367a46f06eecdf9c81dd7 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Wed, 30 Oct 2024 13:34:21 -0500
Subject: [PATCH 1/2] [clang][OpenMP] Add AST node for root of compound
directive
This will be used to print the original directive source from the AST
after splitting compound directives.
---
clang/bindings/python/clang/cindex.py | 3 +
clang/include/clang-c/Index.h | 4 ++
clang/include/clang/AST/RecursiveASTVisitor.h | 3 +
clang/include/clang/AST/StmtOpenMP.h | 60 +++
clang/include/clang/AST/TextNodeDumper.h | 1 +
clang/include/clang/Basic/StmtNodes.td| 1 +
clang/include/clang/Sema/SemaOpenMP.h | 6 ++
.../include/clang/Serialization/ASTBitCodes.h | 1 +
clang/lib/AST/StmtOpenMP.cpp | 15 +
clang/lib/AST/StmtPrinter.cpp | 6 ++
clang/lib/AST/StmtProfile.cpp | 5 ++
clang/lib/AST/TextNodeDumper.cpp | 7 +++
clang/lib/CodeGen/CGStmt.cpp | 4 ++
clang/lib/Sema/SemaExceptionSpec.cpp | 1 +
clang/lib/Sema/SemaOpenMP.cpp | 7 +++
clang/lib/Sema/TreeTransform.h| 8 +++
clang/lib/Serialization/ASTReaderStmt.cpp | 15 +
clang/lib/Serialization/ASTWriterStmt.cpp | 7 +++
clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 1 +
19 files changed, 155 insertions(+)
diff --git a/clang/bindings/python/clang/cindex.py
b/clang/bindings/python/clang/cindex.py
index 3ae7c47915369..5174e16f28f06 100644
--- a/clang/bindings/python/clang/cindex.py
+++ b/clang/bindings/python/clang/cindex.py
@@ -1416,6 +1416,9 @@ def is_unexposed(self):
# OpenMP opaque loop-associated directive.
OMP_OPAQUE_LOOP_DIRECTIVE = 311
+# OpenMP compound root directive.
+OMP_COMPOUND_ROOT_DIRECTIVE = 312
+
# OpenACC Compute Construct.
OPEN_ACC_COMPUTE_DIRECTIVE = 320
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 5d1db153aaafe..02ce2b7690ef0 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2166,6 +2166,10 @@ enum CXCursorKind {
*/
CXCursor_OMPOpaqueLoopDirective = 311,
+ /** OpenMP compound root directive.
+ */
+ CXCursor_OMPCompoundRootDirective = 312,
+
/** OpenACC Compute Construct.
*/
CXCursor_OpenACCComputeConstruct = 320,
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h
b/clang/include/clang/AST/RecursiveASTVisitor.h
index e6fe46acb5fbc..2881604ec781a 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3026,6 +3026,9 @@
RecursiveASTVisitor::TraverseOMPLoopDirective(OMPLoopDirective *S) {
return TraverseOMPExecutableDirective(S);
}
+DEF_TRAVERSE_STMT(OMPCompoundRootDirective,
+ { TRY_TO(TraverseOMPExecutableDirective(S)); })
+
DEF_TRAVERSE_STMT(OMPOpaqueBlockDirective,
{ TRY_TO(TraverseOMPExecutableDirective(S)); })
diff --git a/clang/include/clang/AST/StmtOpenMP.h
b/clang/include/clang/AST/StmtOpenMP.h
index 65434967142c8..4a3c2a53377d6 100644
--- a/clang/include/clang/AST/StmtOpenMP.h
+++ b/clang/include/clang/AST/StmtOpenMP.h
@@ -1560,6 +1560,66 @@ class OMPLoopDirective : public OMPLoopBasedDirective {
}
};
+/// This represents the root of the tree of broken-up compound directive.
+/// It is used to implement pretty-printing consistent with the original
+/// source. This is a pass-through directive for the purposes of semantic
+/// analysis and code generation.
+/// The getDirectiveKind() will return the id of the original, compound
+/// directive. The associated statement will be the outermost one of the
+/// constituent directives. The associated statement is always present.
+class OMPCompoundRootDirective final : public OMPExecutableDirective {
+ friend class ASTStmtReader;
+ friend class OMPExecutableDirective;
+
+ /// Build directive with the given start and end location.
+ ///
+ /// \param DKind The OpenMP directive kind.
+ /// \param StartLoc Starting location of the directive kind.
+ /// \param EndLoc Ending location of the directive.
+ ///
+ OMPCompoundRootDirective(OpenMPDirectiveKind DKind, SourceLocation StartLoc,
+ SourceLocation EndLoc)
+ : OMPExecutableDirective(OMPCompoundRootDirectiveClass, DKind, StartLoc,
+ EndLoc) {}
+
+ /// Build an empty directive.
+ ///
+ /// \param Kind The OpenMP directive kind.
+ ///
+ explicit OMPCompoundRootDirective(OpenMPDirectiveKind DKind)
+ : OMPExecutableDirective(OMPCompoundRootDirectiveClass, DKind,
+ SourceLocation(), SourceLocation()) {}
+
+public:
+ /// Creates directive with a list of \a Clauses.
+ ///
+ /// \param C AST context.
+ /// \param StartLoc Starting location of the directive k
[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dbd24547b2304..dc3b253237e51 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3623,7 +3623,6 @@ void CodeGenFunction::EmitCheck(
llvm::Value *RecoverableCond = nullptr;
llvm::Value *TrapCond = nullptr;
bool NoMerge = false;
-
// Expand checks into:
// (Check1 || !allow_ubsan_check) && (Check2 || !allow_ubsan_check) ...
// We need separate allow_ubsan_check intrinsics because they have separately
@@ -3933,6 +3932,7 @@ void CodeGenFunction::EmitTrapCheck(llvm::Value *Checked,
TrapBBs.resize(CheckHandlerID + 1);
llvm::BasicBlock *&TrapBB = TrapBBs[CheckHandlerID];
+
NoMerge = NoMerge || !CGM.getCodeGenOpts().OptimizationLevel ||
(CurCodeDecl && CurCodeDecl->hasAttr());
>From a16b7a8c48353226fe1323a45f59cd4167ddc3d4 Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:15:20 -0800
Subject: [PATCH 2/4] rename & fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGDebugInfo.cpp | 7 ---
clang/lib/CodeGen/CGDebugInfo.h| 8 +---
clang/lib/CodeGen/CGExpr.cpp | 5 ++---
clang/test/CodeGen/bounds-checking-debuginfo.c | 4 ++--
4 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index ae19e8f724314..35fd78b15ff30 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3598,13 +3598,14 @@ llvm::DIMacroFile
*CGDebugInfo::CreateTempMacroFile(llvm::DIMacroFile *Parent,
return DBuilder.createTempMacroFile(Parent, Line, FName);
}
-llvm::DILocation *CGDebugInfo::CreateSyntheticInline(
-llvm::DebugLoc TrapLocation, StringRef FuncName) {
+llvm::DILocation *
+CGDebugInfo::CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName) {
llvm::DISubprogram *TrapSP =
createInlinedTrapSubprogram(FuncName, TrapLocation->getFile());
return llvm::DILocation::get(CGM.getLLVMContext(), /*Line=*/0, /*Column=*/0,
/*Scope=*/TrapSP, /*InlinedAt=*/TrapLocation);
-}
+}
llvm::DILocation *CGDebugInfo::CreateTrapFailureMessageFor(
llvm::DebugLoc TrapLocation, StringRef Category, StringRef FailureMsg) {
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 0b06bdf78ac78..d01ad3b3d8df5 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -638,9 +638,11 @@ class CGDebugInfo {
/// Create a debug location from `TrapLocation` that adds an artificial
inline
/// frame where the frame name is FuncName
///
- /// This is used to indiciate instructions that come from compiler
instrumentation.
- llvm::DILocation *CreateSyntheticInline(
- llvm::DebugLoc TrapLocation, StringRef FuncName);
+ /// This is used to indiciate instructions that come from compiler
+ /// instrumentation.
+ llvm::DILocation *CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName);
+
private:
/// Emit call to llvm.dbg.declare for a variable declaration.
/// Returns a pointer to the DILocalVariable associated with the
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dc3b253237e51..d5cc2cc69c921 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1219,10 +1219,9 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E,
llvm::Value *Bound,
llvm::DILocation *TrapSP = Builder.getCurrentDebugLocation();
if (TrapSP) {
TrapSP = getDebugInfo()->CreateSyntheticInline(
- Builder.getCurrentDebugLocation(),
- "check_array_bounds");
+Builder.getCurrentDebugLocation(), "__ubsan_check_array_bounds");
}
- ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
+ ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType();
llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned);
diff --git a/clang/test/CodeGen/bounds-checking-debuginfo.c
b/clang/test/CodeGen/bounds-checking-debuginfo.c
index e2a604bc962ba..58fcc89058d72 100644
--- a/clang/test/CodeGen/bounds-checking-debuginfo.c
+++ b/clang/test/CodeGen/bounds-checking-debuginfo.c
@@ -89,7 +89,7 @@ double f1(int b, int i) {
// CHECK-TRAP: [[DBG22]] = !DILocation(line: 65, column: 3, scope: [[DBG5]])
// CHECK-TRAP: [[DBG23]] = !DILocation(line: 66, column: 12, scope: [[DBG5]])
// CHECK-TRAP: [[DBG24]] = !DILocation(line: 0, scope: [[META
[llvm-branch-commits] [compiler-rt] release/20.x: XFAIL malloc_zone.cpp for darwin/lsan (#131234) (PR #133006)
llvmbot wrote: @llvm/pr-subscribers-compiler-rt-sanitizer Author: None (llvmbot) Changes Backport ab58a3c35b6fc6a4b513d75c38881134f5b2c9b9 Requested by: @wrotki --- Full diff: https://github.com/llvm/llvm-project/pull/133006.diff 1 Files Affected: - (modified) compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp (+2) ``diff diff --git a/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp b/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp index fd6ef03629438..e68e93129be2f 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/Darwin/malloc_zone.cpp @@ -17,6 +17,8 @@ // UBSan does not install a malloc zone. // XFAIL: ubsan // +// Curently fails on darwin/lsan rdar://145873843 +// XFAIL: darwin && lsan #include #include `` https://github.com/llvm/llvm-project/pull/133006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)
@@ -3598,6 +3598,14 @@ llvm::DIMacroFile
*CGDebugInfo::CreateTempMacroFile(llvm::DIMacroFile *Parent,
return DBuilder.createTempMacroFile(Parent, Line, FName);
}
+llvm::DILocation *CGDebugInfo::CreateSyntheticInline(llvm::DebugLoc Location,
+ StringRef FuncName) {
+ llvm::DISubprogram *TrapSP =
fmayer wrote:
Done.
https://github.com/llvm/llvm-project/pull/128977
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[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dbd24547b2304..dc3b253237e51 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3623,7 +3623,6 @@ void CodeGenFunction::EmitCheck(
llvm::Value *RecoverableCond = nullptr;
llvm::Value *TrapCond = nullptr;
bool NoMerge = false;
-
// Expand checks into:
// (Check1 || !allow_ubsan_check) && (Check2 || !allow_ubsan_check) ...
// We need separate allow_ubsan_check intrinsics because they have separately
@@ -3933,6 +3932,7 @@ void CodeGenFunction::EmitTrapCheck(llvm::Value *Checked,
TrapBBs.resize(CheckHandlerID + 1);
llvm::BasicBlock *&TrapBB = TrapBBs[CheckHandlerID];
+
NoMerge = NoMerge || !CGM.getCodeGenOpts().OptimizationLevel ||
(CurCodeDecl && CurCodeDecl->hasAttr());
>From a16b7a8c48353226fe1323a45f59cd4167ddc3d4 Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:15:20 -0800
Subject: [PATCH 2/4] rename & fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGDebugInfo.cpp | 7 ---
clang/lib/CodeGen/CGDebugInfo.h| 8 +---
clang/lib/CodeGen/CGExpr.cpp | 5 ++---
clang/test/CodeGen/bounds-checking-debuginfo.c | 4 ++--
4 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index ae19e8f724314..35fd78b15ff30 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3598,13 +3598,14 @@ llvm::DIMacroFile
*CGDebugInfo::CreateTempMacroFile(llvm::DIMacroFile *Parent,
return DBuilder.createTempMacroFile(Parent, Line, FName);
}
-llvm::DILocation *CGDebugInfo::CreateSyntheticInline(
-llvm::DebugLoc TrapLocation, StringRef FuncName) {
+llvm::DILocation *
+CGDebugInfo::CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName) {
llvm::DISubprogram *TrapSP =
createInlinedTrapSubprogram(FuncName, TrapLocation->getFile());
return llvm::DILocation::get(CGM.getLLVMContext(), /*Line=*/0, /*Column=*/0,
/*Scope=*/TrapSP, /*InlinedAt=*/TrapLocation);
-}
+}
llvm::DILocation *CGDebugInfo::CreateTrapFailureMessageFor(
llvm::DebugLoc TrapLocation, StringRef Category, StringRef FailureMsg) {
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 0b06bdf78ac78..d01ad3b3d8df5 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -638,9 +638,11 @@ class CGDebugInfo {
/// Create a debug location from `TrapLocation` that adds an artificial
inline
/// frame where the frame name is FuncName
///
- /// This is used to indiciate instructions that come from compiler
instrumentation.
- llvm::DILocation *CreateSyntheticInline(
- llvm::DebugLoc TrapLocation, StringRef FuncName);
+ /// This is used to indiciate instructions that come from compiler
+ /// instrumentation.
+ llvm::DILocation *CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName);
+
private:
/// Emit call to llvm.dbg.declare for a variable declaration.
/// Returns a pointer to the DILocalVariable associated with the
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dc3b253237e51..d5cc2cc69c921 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1219,10 +1219,9 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E,
llvm::Value *Bound,
llvm::DILocation *TrapSP = Builder.getCurrentDebugLocation();
if (TrapSP) {
TrapSP = getDebugInfo()->CreateSyntheticInline(
- Builder.getCurrentDebugLocation(),
- "check_array_bounds");
+Builder.getCurrentDebugLocation(), "__ubsan_check_array_bounds");
}
- ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
+ ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType();
llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned);
diff --git a/clang/test/CodeGen/bounds-checking-debuginfo.c
b/clang/test/CodeGen/bounds-checking-debuginfo.c
index e2a604bc962ba..58fcc89058d72 100644
--- a/clang/test/CodeGen/bounds-checking-debuginfo.c
+++ b/clang/test/CodeGen/bounds-checking-debuginfo.c
@@ -89,7 +89,7 @@ double f1(int b, int i) {
// CHECK-TRAP: [[DBG22]] = !DILocation(line: 65, column: 3, scope: [[DBG5]])
// CHECK-TRAP: [[DBG23]] = !DILocation(line: 66, column: 12, scope: [[DBG5]])
// CHECK-TRAP: [[DBG24]] = !DILocation(line: 0, scope: [[META
[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dbd24547b2304..dc3b253237e51 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3623,7 +3623,6 @@ void CodeGenFunction::EmitCheck(
llvm::Value *RecoverableCond = nullptr;
llvm::Value *TrapCond = nullptr;
bool NoMerge = false;
-
// Expand checks into:
// (Check1 || !allow_ubsan_check) && (Check2 || !allow_ubsan_check) ...
// We need separate allow_ubsan_check intrinsics because they have separately
@@ -3933,6 +3932,7 @@ void CodeGenFunction::EmitTrapCheck(llvm::Value *Checked,
TrapBBs.resize(CheckHandlerID + 1);
llvm::BasicBlock *&TrapBB = TrapBBs[CheckHandlerID];
+
NoMerge = NoMerge || !CGM.getCodeGenOpts().OptimizationLevel ||
(CurCodeDecl && CurCodeDecl->hasAttr());
>From a16b7a8c48353226fe1323a45f59cd4167ddc3d4 Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:15:20 -0800
Subject: [PATCH 2/4] rename & fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGDebugInfo.cpp | 7 ---
clang/lib/CodeGen/CGDebugInfo.h| 8 +---
clang/lib/CodeGen/CGExpr.cpp | 5 ++---
clang/test/CodeGen/bounds-checking-debuginfo.c | 4 ++--
4 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index ae19e8f724314..35fd78b15ff30 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3598,13 +3598,14 @@ llvm::DIMacroFile
*CGDebugInfo::CreateTempMacroFile(llvm::DIMacroFile *Parent,
return DBuilder.createTempMacroFile(Parent, Line, FName);
}
-llvm::DILocation *CGDebugInfo::CreateSyntheticInline(
-llvm::DebugLoc TrapLocation, StringRef FuncName) {
+llvm::DILocation *
+CGDebugInfo::CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName) {
llvm::DISubprogram *TrapSP =
createInlinedTrapSubprogram(FuncName, TrapLocation->getFile());
return llvm::DILocation::get(CGM.getLLVMContext(), /*Line=*/0, /*Column=*/0,
/*Scope=*/TrapSP, /*InlinedAt=*/TrapLocation);
-}
+}
llvm::DILocation *CGDebugInfo::CreateTrapFailureMessageFor(
llvm::DebugLoc TrapLocation, StringRef Category, StringRef FailureMsg) {
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 0b06bdf78ac78..d01ad3b3d8df5 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -638,9 +638,11 @@ class CGDebugInfo {
/// Create a debug location from `TrapLocation` that adds an artificial
inline
/// frame where the frame name is FuncName
///
- /// This is used to indiciate instructions that come from compiler
instrumentation.
- llvm::DILocation *CreateSyntheticInline(
- llvm::DebugLoc TrapLocation, StringRef FuncName);
+ /// This is used to indiciate instructions that come from compiler
+ /// instrumentation.
+ llvm::DILocation *CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName);
+
private:
/// Emit call to llvm.dbg.declare for a variable declaration.
/// Returns a pointer to the DILocalVariable associated with the
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dc3b253237e51..d5cc2cc69c921 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1219,10 +1219,9 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E,
llvm::Value *Bound,
llvm::DILocation *TrapSP = Builder.getCurrentDebugLocation();
if (TrapSP) {
TrapSP = getDebugInfo()->CreateSyntheticInline(
- Builder.getCurrentDebugLocation(),
- "check_array_bounds");
+Builder.getCurrentDebugLocation(), "__ubsan_check_array_bounds");
}
- ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
+ ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType();
llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned);
diff --git a/clang/test/CodeGen/bounds-checking-debuginfo.c
b/clang/test/CodeGen/bounds-checking-debuginfo.c
index e2a604bc962ba..58fcc89058d72 100644
--- a/clang/test/CodeGen/bounds-checking-debuginfo.c
+++ b/clang/test/CodeGen/bounds-checking-debuginfo.c
@@ -89,7 +89,7 @@ double f1(int b, int i) {
// CHECK-TRAP: [[DBG22]] = !DILocation(line: 65, column: 3, scope: [[DBG5]])
// CHECK-TRAP: [[DBG23]] = !DILocation(line: 66, column: 12, scope: [[DBG5]])
// CHECK-TRAP: [[DBG24]] = !DILocation(line: 0, scope: [[META
[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)
@@ -355,12 +355,12 @@ class CGDebugInfo {
llvm::ArrayRef PreviousFieldsDI, const RecordDecl *RD);
/// A cache that maps names of artificial inlined functions to subprograms.
- llvm::StringMap InlinedTrapFuncMap;
+ llvm::StringMap InlinedSubprogramMap;
fmayer wrote:
https://github.com/llvm/llvm-project/pull/132993
https://github.com/llvm/llvm-project/pull/128977
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[llvm-branch-commits] [compiler-rt] release/20.x: XFAIL malloc_zone.cpp for darwin/lsan (#131234) (PR #133006)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/133006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Driver] Forward sysroot from Driver to linker in BareMetal ToolChain Object (PR #132808)
https://github.com/petrhosek approved this pull request. https://github.com/llvm/llvm-project/pull/132808 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: Detect address materialization and arithmetics (PR #132540)
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/132540
>From de28401e6c4f68117f0b71f2b08c3c065b286f62 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Thu, 20 Mar 2025 20:15:07 +0300
Subject: [PATCH] [BOLT] Gadget scanner: Detect address materialization and
arithmetics
In addition to authenticated pointers, consider the contents of a
register safe if it was
* written by PC-relative address computation
* updated by an arithmetic instruction whose input address is safe
---
bolt/include/bolt/Core/MCPlusBuilder.h| 16 ++
bolt/lib/Passes/PAuthGadgetScanner.cpp| 92 +--
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 30 +++
.../AArch64/gs-pacret-autiasp.s | 15 --
.../gs-pauth-address-materialization.s| 228 ++
.../binary-analysis/AArch64/lit.local.cfg | 3 +-
6 files changed, 345 insertions(+), 39 deletions(-)
create mode 100644
bolt/test/binary-analysis/AArch64/gs-pauth-address-materialization.s
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h
b/bolt/include/bolt/Core/MCPlusBuilder.h
index 8b6dc14121480..e94f82d00349a 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -587,6 +587,22 @@ class MCPlusBuilder {
return getNoRegister();
}
+ virtual MCPhysReg getSafelyMaterializedAddressReg(const MCInst &Inst) const {
+llvm_unreachable("not implemented");
+return getNoRegister();
+ }
+
+ /// Analyzes if this instruction can safely perform address arithmetics.
+ ///
+ /// If the first element of the returned pair is no-register, this
instruction
+ /// is considered unknown. Otherwise, (output, input) pair is returned,
+ /// so that output is as trusted as input is.
+ virtual std::pair
+ analyzeSafeAddressArithmetics(const MCInst &Inst) const {
+llvm_unreachable("not implemented");
+return std::make_pair(getNoRegister(), getNoRegister());
+ }
+
virtual bool isTerminator(const MCInst &Inst) const;
virtual bool isNoop(const MCInst &Inst) const {
diff --git a/bolt/lib/Passes/PAuthGadgetScanner.cpp
b/bolt/lib/Passes/PAuthGadgetScanner.cpp
index dcc7d93183900..33f925070290e 100644
--- a/bolt/lib/Passes/PAuthGadgetScanner.cpp
+++ b/bolt/lib/Passes/PAuthGadgetScanner.cpp
@@ -335,6 +335,50 @@ class PacRetAnalysis
});
}
+ BitVector getClobberedRegs(const MCInst &Point) const {
+BitVector Clobbered(NumRegs, false);
+// Assume a call can clobber all registers, including callee-saved
+// registers. There's a good chance that callee-saved registers will be
+// saved on the stack at some point during execution of the callee.
+// Therefore they should also be considered as potentially modified by an
+// attacker/written to.
+// Also, not all functions may respect the AAPCS ABI rules about
+// caller/callee-saved registers.
+if (BC.MIB->isCall(Point))
+ Clobbered.set();
+else
+ BC.MIB->getClobberedRegs(Point, Clobbered);
+return Clobbered;
+ }
+
+ // Returns all registers that can be treated as if they are written by an
+ // authentication instruction.
+ SmallVector getAuthenticatedRegs(const MCInst &Point,
+ const State &Cur) const {
+SmallVector Regs;
+const MCPhysReg NoReg = BC.MIB->getNoRegister();
+
+// A signed pointer can be authenticated, or
+ErrorOr AutReg = BC.MIB->getAuthenticatedReg(Point);
+if (AutReg && *AutReg != NoReg)
+ Regs.push_back(*AutReg);
+
+// ... a safe address can be materialized, or
+MCPhysReg NewAddrReg = BC.MIB->getSafelyMaterializedAddressReg(Point);
+if (NewAddrReg != NoReg)
+ Regs.push_back(NewAddrReg);
+
+// ... an address can be updated in a safe manner, producing the result
+// which is as trusted as the input address.
+MCPhysReg ArithResult, ArithSrc;
+std::tie(ArithResult, ArithSrc) =
+BC.MIB->analyzeSafeAddressArithmetics(Point);
+if (ArithResult != NoReg && Cur.SafeToDerefRegs[ArithSrc])
+ Regs.push_back(ArithResult);
+
+return Regs;
+ }
+
State computeNext(const MCInst &Point, const State &Cur) {
PacStatePrinter P(BC);
LLVM_DEBUG({
@@ -355,19 +399,20 @@ class PacRetAnalysis
return State();
}
+// First, compute various properties of the instruction, taking the state
+// before its execution into account, if necessary.
+
+BitVector Clobbered = getClobberedRegs(Point);
+// Compute the set of registers that can be considered as written by
+// an authentication instruction. This includes operations that are
+// *strictly better* than authentication, such as materializing a
+// PC-relative constant.
+SmallVector AuthenticatedOrBetter =
+getAuthenticatedRegs(Point, Cur);
+
+// Then, compute the state after this instruction is executed.
State Next = Cur;
-BitVector Clobbered(NumRegs, false);
-// Assume a call can clo
[llvm-branch-commits] [lld] release/20.x: [LLD] [COFF] Add a few more mingw libs to skip autoexports for (#132289) (PR #132478)
github-actions[bot] wrote: @mstorsjo (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/132478 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] 9c43831 - Revert "[mlir] Fix DistinctAttributeUniquer deleting attribute storage when c…"
Author: Emilio Cota
Date: 2025-03-25T21:35:52Z
New Revision: 9c438311e573094c76c2b2d2425d625e068f841a
URL:
https://github.com/llvm/llvm-project/commit/9c438311e573094c76c2b2d2425d625e068f841a
DIFF:
https://github.com/llvm/llvm-project/commit/9c438311e573094c76c2b2d2425d625e068f841a.diff
LOG: Revert "[mlir] Fix DistinctAttributeUniquer deleting attribute storage
when c…"
This reverts commit 0aa5ba43a0d11ce8e7f143380ae75fea516b6841.
Added:
Modified:
mlir/include/mlir/IR/MLIRContext.h
mlir/lib/IR/AttributeDetail.h
mlir/lib/IR/MLIRContext.cpp
mlir/lib/Pass/PassCrashRecovery.cpp
Removed:
mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope-with-crash-reproduction.mlir
mlir/test/IR/test-builtin-distinct-attrs-with-crash-reproduction.mlir
diff --git a/mlir/include/mlir/IR/MLIRContext.h
b/mlir/include/mlir/IR/MLIRContext.h
index ad89d631c8a5f..ef8dab87f131a 100644
--- a/mlir/include/mlir/IR/MLIRContext.h
+++ b/mlir/include/mlir/IR/MLIRContext.h
@@ -153,14 +153,6 @@ class MLIRContext {
disableMultithreading(!enable);
}
- /// Set the flag specifying if thread-local storage should be used by storage
- /// allocators in this context. Note that disabling mutlithreading implies
- /// thread-local storage is also disabled.
- void disableThreadLocalStorage(bool disable = true);
- void enableThreadLocalStorage(bool enable = true) {
-disableThreadLocalStorage(!enable);
- }
-
/// Set a new thread pool to be used in this context. This method requires
/// that multithreading is disabled for this context prior to the call. This
/// allows to share a thread pool across multiple contexts, as well as
diff --git a/mlir/lib/IR/AttributeDetail.h b/mlir/lib/IR/AttributeDetail.h
index 8fed18140433c..26d40ac3a38f6 100644
--- a/mlir/lib/IR/AttributeDetail.h
+++ b/mlir/lib/IR/AttributeDetail.h
@@ -24,7 +24,6 @@
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/Support/TrailingObjects.h"
-#include
namespace mlir {
namespace detail {
@@ -402,8 +401,7 @@ class DistinctAttributeUniquer {
/// is freed after the destruction of the distinct attribute allocator.
class DistinctAttributeAllocator {
public:
- DistinctAttributeAllocator(bool threadingIsEnabled)
- : threadingIsEnabled(threadingIsEnabled), useThreadLocalAllocator(true)
{};
+ DistinctAttributeAllocator() = default;
DistinctAttributeAllocator(DistinctAttributeAllocator &&) = delete;
DistinctAttributeAllocator(const DistinctAttributeAllocator &) = delete;
@@ -413,49 +411,12 @@ class DistinctAttributeAllocator {
/// Allocates a distinct attribute storage using a thread local bump pointer
/// allocator to enable synchronization free parallel allocations.
DistinctAttrStorage *allocate(Attribute referencedAttr) {
-if (!useThreadLocalAllocator && threadingIsEnabled) {
- std::scoped_lock lock(allocatorMutex);
- return allocateImpl(referencedAttr);
-}
-return allocateImpl(referencedAttr);
- }
-
- /// Sets a flag that stores if multithreading is enabled. The flag is used to
- /// decide if locking is needed when using a non thread-safe allocator.
- void disableMultiThreading(bool disable = true) {
-threadingIsEnabled = !disable;
- }
-
- /// Sets a flag to disable using thread local bump pointer allocators and use
- /// a single thread-safe allocator. Use this to persist allocated storage
- /// beyond the lifetime of a child thread calling this function while
ensuring
- /// thread-safe allocation.
- void disableThreadLocalStorage(bool disable = true) {
-useThreadLocalAllocator = !disable;
- }
-
-private:
- DistinctAttrStorage *allocateImpl(Attribute referencedAttr) {
-return new (getAllocatorInUse().Allocate())
+return new (allocatorCache.get().Allocate())
DistinctAttrStorage(referencedAttr);
}
- /// If threading is disabled on the owning MLIR context, a normal non
- /// thread-local, non-thread safe bump pointer allocator is used instead to
- /// prevent use-after-free errors whenever attribute storage created on a
- /// crash recover thread is accessed after the thread joins.
- llvm::BumpPtrAllocator &getAllocatorInUse() {
-if (useThreadLocalAllocator)
- return allocatorCache.get();
-return allocator;
- }
-
+private:
ThreadLocalCache allocatorCache;
- llvm::BumpPtrAllocator allocator;
- std::mutex allocatorMutex;
-
- bool threadingIsEnabled : 1;
- bool useThreadLocalAllocator : 1;
};
} // namespace detail
} // namespace mlir
diff --git a/mlir/lib/IR/MLIRContext.cpp b/mlir/lib/IR/MLIRContext.cpp
index ab6a5ac8b76e8..87782e84dd6e4 100644
--- a/mlir/lib/IR/MLIRContext.cpp
+++ b/mlir/lib/IR/MLIRContext.cpp
@@ -268,8 +268,7 @@ class MLIRContextImpl {
public:
MLIRContextImpl(bool threadingIsEnabled)
- : threadingIsEnabled(threadingIsEnabled),
-distinctAttributeAllocato
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
@@ -0,0 +1,141 @@ +; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \ snehasish wrote: Can we drop the `-enable-split-machine-functions` flag here and below? https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
@@ -0,0 +1,141 @@
+; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Repeat the RUN command above for big-endian systems.
+; RUN: llc -mtriple=aarch64_be -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Tests that constant pool hotness is aggregated across the module. The
+; static-data-splitter processes data from cold_func first, unprofiled_func
+; secondly, and then hot_func. Specifically, tests that
+; - If a constant is accessed by hot functions, all constant pools for this
+; constant (e.g., from an unprofiled function, or cold function) should have
+; `.hot` suffix.
+; - Similarly if a constant is accessed by both cold function and un-profiled
+; function, constant pools for this constant should not have `.unlikely`
suffix.
+
+; CHECK: .section .rodata.cst8.hot,"aM",@progbits,8
+; CHECK: .LCPI0_0:
+; CHECK: .xword 0x3fe5c28f5c28f5c3 // double
0.68005
+; CHECK: .section .rodata.cst8.unlikely,"aM",@progbits,8
+; CHECK: .LCPI0_1:
+; CHECK: .xword 0x3fe5eb851eb851ec // double
0.68505
+; CHECK: .section .rodata.cst8,"aM",@progbits,8
+; CHECK: .LCPI0_2:
+; CHECK: .byte 0 // 0x0
+; CHECK: .byte 4 // 0x4
+; CHECK: .byte 8 // 0x8
+; CHECK: .byte 12 // 0xc
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+
+; CHECK: .section .rodata.cst8,"aM",@progbits,8
+; CHECK: .LCPI1_0:
+; CHECK: .byte 0 // 0x0
+; CHECK: .byte 4 // 0x4
+; CHECK: .byte 8 // 0x8
+; CHECK: .byte 12 // 0xc
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .section.rodata.cst16.hot,"aM",@progbits,16
+; CHECK: .LCPI1_1:
+; CHECK: .word 442 // 0x1ba
+; CHECK: .word 100 // 0x64
+; CHECK: .word 0 // 0x0
+; CHECK: .word 0 // 0x0
+
+; CHECK: .section.rodata.cst8.hot,"aM",@progbits,8
+; CHECK: .LCPI2_0:
+; CHECK: .xword 0x3fe5c28f5c28f5c3 // double
0.68005
+; CHECK: .section.rodata.cst16.hot,"aM",@progbits,16
+; CHECK: .LCPI2_1:
+; CHECK: .word 442 // 0x1ba
+; CHECK: .word 100 // 0x64
+; CHECK: .word 0 // 0x0
+; CHECK: .word 0 // 0x0
+
+; CHECK:.section .rodata.cst32,"aM",@progbits,32
+; CHECK:.globl val
+
+define i32 @cold_func(double %x, <16 x i8> %a, <16 x i8> %b) !prof !16 {
+ %2 = tail call i32 (...) @func_taking_arbitrary_param(double 6.80e-01)
+ %num = tail call i32 (...) @func_taking_arbitrary_param(double 6.850e-01)
+ %t1 = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %a, <16 x i8> %b,
<8 x i8> )
+ %t2 = bitcast <8 x i8> %t1 to <2 x i32>
+ %3 = extractelement <2 x i32> %t2, i32 1
+ %sum = add i32 %2, %3
+ %ret = add i32 %sum, %num
+ ret i32 %ret
+}
+
+declare <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8>, <16 x i8>, <8 x i8>)
+declare i32 @func_taking_arbitrary_param(...)
+
+define <4 x i1> @unprofiled_func(<16 x i8> %a, <16 x i8> %b) {
+ %t1 = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %a, <16 x i8> %b,
<8 x i8> )
+ %t2 = bitcast <8 x i8> %t1 to <4 x i16>
+ %t3 = zext <4 x i16> %t2 to <4 x i32>
+ %cmp = icmp ule <4 x i32> , %t3
snehasish wrote:
Can we use different values for the constant in the unprofiled func and the hot
func? Using <442, 100, 0, 0> for both seems like it could lead to false
positives.
https://github.com/llvm/llvm-project/pull/129781
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[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
@@ -0,0 +1,141 @@
+; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Repeat the RUN command above for big-endian systems.
+; RUN: llc -mtriple=aarch64_be -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Tests that constant pool hotness is aggregated across the module. The
+; static-data-splitter processes data from cold_func first, unprofiled_func
+; secondly, and then hot_func. Specifically, tests that
+; - If a constant is accessed by hot functions, all constant pools for this
+; constant (e.g., from an unprofiled function, or cold function) should have
+; `.hot` suffix.
+; - Similarly if a constant is accessed by both cold function and un-profiled
+; function, constant pools for this constant should not have `.unlikely`
suffix.
+
+; CHECK: .section .rodata.cst8.hot,"aM",@progbits,8
+; CHECK: .LCPI0_0:
+; CHECK: .xword 0x3fe5c28f5c28f5c3 // double
0.68005
+; CHECK: .section .rodata.cst8.unlikely,"aM",@progbits,8
+; CHECK: .LCPI0_1:
+; CHECK: .xword 0x3fe5eb851eb851ec // double
0.68505
+; CHECK: .section .rodata.cst8,"aM",@progbits,8
+; CHECK: .LCPI0_2:
+; CHECK: .byte 0 // 0x0
+; CHECK: .byte 4 // 0x4
+; CHECK: .byte 8 // 0x8
+; CHECK: .byte 12 // 0xc
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+
+; CHECK: .section .rodata.cst8,"aM",@progbits,8
+; CHECK: .LCPI1_0:
+; CHECK: .byte 0 // 0x0
+; CHECK: .byte 4 // 0x4
+; CHECK: .byte 8 // 0x8
+; CHECK: .byte 12 // 0xc
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .byte 255 // 0xff
+; CHECK: .section.rodata.cst16.hot,"aM",@progbits,16
+; CHECK: .LCPI1_1:
+; CHECK: .word 442 // 0x1ba
+; CHECK: .word 100 // 0x64
+; CHECK: .word 0 // 0x0
+; CHECK: .word 0 // 0x0
+
+; CHECK: .section.rodata.cst8.hot,"aM",@progbits,8
+; CHECK: .LCPI2_0:
+; CHECK: .xword 0x3fe5c28f5c28f5c3 // double
0.68005
+; CHECK: .section.rodata.cst16.hot,"aM",@progbits,16
+; CHECK: .LCPI2_1:
+; CHECK: .word 442 // 0x1ba
+; CHECK: .word 100 // 0x64
+; CHECK: .word 0 // 0x0
+; CHECK: .word 0 // 0x0
+
+; CHECK:.section .rodata.cst32,"aM",@progbits,32
+; CHECK:.globl val
+
+define i32 @cold_func(double %x, <16 x i8> %a, <16 x i8> %b) !prof !16 {
+ %2 = tail call i32 (...) @func_taking_arbitrary_param(double 6.80e-01)
+ %num = tail call i32 (...) @func_taking_arbitrary_param(double 6.850e-01)
+ %t1 = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %a, <16 x i8> %b,
<8 x i8> )
+ %t2 = bitcast <8 x i8> %t1 to <2 x i32>
+ %3 = extractelement <2 x i32> %t2, i32 1
+ %sum = add i32 %2, %3
+ %ret = add i32 %sum, %num
+ ret i32 %ret
+}
+
+declare <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8>, <16 x i8>, <8 x i8>)
+declare i32 @func_taking_arbitrary_param(...)
+
+define <4 x i1> @unprofiled_func(<16 x i8> %a, <16 x i8> %b) {
+ %t1 = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %a, <16 x i8> %b,
<8 x i8> )
+ %t2 = bitcast <8 x i8> %t1 to <4 x i16>
+ %t3 = zext <4 x i16> %t2 to <4 x i32>
+ %cmp = icmp ule <4 x i32> , %t3
+ ret <4 x i1> %cmp
+}
+
+define <4 x i1> @hot_func(i32 %0, <4 x i32> %a) !prof !17 {
+ %2 = tail call i32 (...) @func_taking_arbitrary_param(double 6.80e-01)
+ %b = icmp ule <4 x i32> %a,
+ ret <4 x i1> %b
+}
+
+@val = unnamed_addr constant i256 1
snehasish wrote:
Should this be used somewhere so that we can check that we correctly assign the
section suffix for 32 bit consts?
https://github.com/llvm/llvm-project/pull/129781
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[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
@@ -0,0 +1,141 @@ +; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \ +; RUN: -partition-static-data-sections=true -function-sections=true \ +; RUN: -unique-section-names=false \ +; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always + +; Repeat the RUN command above for big-endian systems. +; RUN: llc -mtriple=aarch64_be -enable-split-machine-functions \ +; RUN: -partition-static-data-sections=true -function-sections=true \ +; RUN: -unique-section-names=false \ +; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always + +; Tests that constant pool hotness is aggregated across the module. The +; static-data-splitter processes data from cold_func first, unprofiled_func +; secondly, and then hot_func. Specifically, tests that +; - If a constant is accessed by hot functions, all constant pools for this +; constant (e.g., from an unprofiled function, or cold function) should have +; `.hot` suffix. +; - Similarly if a constant is accessed by both cold function and un-profiled +; function, constant pools for this constant should not have `.unlikely` suffix. + +; CHECK: .section .rodata.cst8.hot,"aM",@progbits,8 +; CHECK: .LCPI0_0: snehasish wrote: Can some (most) of these be CHECK-NEXT to make the test tighter? https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
https://github.com/snehasish approved this pull request. lgtm with some suggested changes to the tests. https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/20.x: [rtsan][Apple] Add interceptor for _os_nospin_lock_lock (#131034) (PR #132997)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: None (llvmbot)
Changes
Backport 481a55a3d9645a6bc1540d326319b78ad8ed8db1
Requested by: @wrotki
---
Full diff: https://github.com/llvm/llvm-project/pull/132997.diff
2 Files Affected:
- (modified) compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp (+11)
- (modified) compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
(+19)
``diff
diff --git a/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
b/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
index 6816119065263..4d602a88ba9ae 100644
--- a/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
+++ b/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
@@ -30,6 +30,12 @@
extern "C" {
typedef int32_t OSSpinLock;
void OSSpinLockLock(volatile OSSpinLock *__lock);
+// A pointer to this type is in the interface for `_os_nospin_lock_lock`, but
+// it's an internal implementation detail of `os/lock.c` on Darwin, and
+// therefore not available in any headers. As a workaround, we forward declare
+// it here, which is enough to facilitate interception of _os_nospin_lock_lock.
+struct _os_nospin_lock_s;
+using _os_nospin_lock_t = _os_nospin_lock_s *;
}
#endif // TARGET_OS_MAC
@@ -642,6 +648,11 @@ INTERCEPTOR(void, os_unfair_lock_lock, os_unfair_lock_t
lock) {
__rtsan_notify_intercepted_call("os_unfair_lock_lock");
return REAL(os_unfair_lock_lock)(lock);
}
+
+INTERCEPTOR(void, _os_nospin_lock_lock, _os_nospin_lock_t lock) {
+ __rtsan_notify_intercepted_call("_os_nospin_lock_lock");
+ return REAL(_os_nospin_lock_lock)(lock);
+}
#define RTSAN_MAYBE_INTERCEPT_OS_UNFAIR_LOCK_LOCK
\
INTERCEPT_FUNCTION(os_unfair_lock_lock)
#else
diff --git a/compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
b/compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
index 59663776366bb..75f723081c4b6 100644
--- a/compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
+++ b/compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
@@ -1058,6 +1058,25 @@ TEST(TestRtsanInterceptors,
OsUnfairLockLockDiesWhenRealtime) {
ExpectRealtimeDeath(Func, "os_unfair_lock_lock");
ExpectNonRealtimeSurvival(Func);
}
+
+// We intercept _os_nospin_lock_lock because it's the internal
+// locking mechanism for MacOS's atomic implementation for data
+// types that are larger than the hardware's maximum lock-free size.
+// However, it's a private implementation detail and not visible in any
headers,
+// so we must duplicate the required type definitions to forward declaration
+// what we need here.
+extern "C" {
+struct _os_nospin_lock_s {
+ unsigned int oul_value;
+};
+void _os_nospin_lock_lock(_os_nospin_lock_s *);
+}
+TEST(TestRtsanInterceptors, OsNoSpinLockLockDiesWhenRealtime) {
+ _os_nospin_lock_s lock{};
+ auto Func = [&]() { _os_nospin_lock_lock(&lock); };
+ ExpectRealtimeDeath(Func, "_os_nospin_lock_lock");
+ ExpectNonRealtimeSurvival(Func);
+}
#endif
#if SANITIZER_LINUX
``
https://github.com/llvm/llvm-project/pull/132997
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[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824) (PR #132932)
llvmbot wrote: @RKSimon What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/132932 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824) (PR #132932)
https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/132932 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
https://github.com/kbeyls edited https://github.com/llvm/llvm-project/pull/131899 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
@@ -0,0 +1,131 @@ +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-grtev4-linux-gnu" + +; Tests that constant pool hotness is aggregated across the module. The snehasish wrote: I think the comments for the ARM testt applies to this file too. https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)
@@ -1375,14 +1375,20 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type, return 1; } + // LoongArch support IE to LE optimization in non-extreme code model. + bool execOptimizeInLoongArch = + ctx.arg.emachine == EM_LOONGARCH && + (type == R_LARCH_TLS_IE_PC_HI20 || type == R_LARCH_TLS_IE_PC_LO12); ylzsx wrote: At this point, I cannot determine whether current execution is in extreme or medium code mode, since I cannot obtain the next relocation record. So, as a workaround, I have chosen to convert the relocation type in both modes and then restore it(extreme code mode) or relax it(medium code mode) later in relocateAlloc. https://github.com/llvm/llvm-project/pull/123680 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
@@ -18,6 +18,6 @@ .globl _start _start: .data - .word foo@PLT - . - .word foo@PLT - . + 1 - .word foo@PLT - . - 1 + .word %plt(foo - .) MaskRay wrote: Implemented `%pltpcrel`, while a bit complex, I am happy with the result. (As in `RISCVMCExpr::evaluateAsRelocatableImpl`, we don't need an exception for `VK_PLT`, if we go with `%plt`. This might be difficult to explain without playing with it.) https://github.com/llvm/llvm-project/pull/132569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Driver] Fix link order of BareMetal toolchain object (PR #132806)
https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/132806 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Backport: [clang] fix matching of nested template template parameters (PR #130950)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/130950
>From ecde8c235e5e09ff71789725c96416f8daf93cd7 Mon Sep 17 00:00:00 2001
From: Matheus Izvekov
Date: Sat, 8 Mar 2025 20:32:14 -0300
Subject: [PATCH] [clang] fix matching of nested template template parameters
When checking the template template parameters of template template
parameters, the PartialOrdering context was not correctly propagated.
This also has a few drive-by fixes, such as checking the template parameter
lists of template template parameters, which was previously missing and
would have been it's own bug, but we need to fix it in order to
prevent crashes in error recovery in a simple way.
Fixes #130362
Backport of: https://github.com/llvm/llvm-project/pull/130447
---
clang/docs/ReleaseNotes.rst | 3 ++
clang/include/clang/Sema/Sema.h | 8 +++--
clang/lib/Sema/SemaDecl.cpp | 2 +-
clang/lib/Sema/SemaDeclCXX.cpp| 2 +-
clang/lib/Sema/SemaTemplate.cpp | 36 ---
clang/lib/Sema/SemaTemplateDeduction.cpp | 16 +
.../lib/Sema/SemaTemplateInstantiateDecl.cpp | 2 +-
clang/test/SemaTemplate/cwg2398.cpp | 22 ++--
.../SemaTemplate/temp_arg_template_p0522.cpp | 3 +-
clang/unittests/AST/DeclPrinterTest.cpp | 16 -
10 files changed, 64 insertions(+), 46 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 955325026f369..c921ac3518f01 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1058,6 +1058,9 @@ Bug Fixes to C++ Support
- Fixed a substitution bug in transforming CTAD aliases when the type alias
contains a non-pack template argument
corresponding to a pack parameter (#GH124715)
- Clang is now better at keeping track of friend function template instance
contexts. (#GH55509)
+- Fixes matching of nested template template parameters. (#GH130362)
+- Correctly diagnoses template template paramters which have a pack parameter
+ not in the last position.
- Fixed an integer overflow bug in computing template parameter depths when
synthesizing CTAD guides. (#GH128691)
- Fixed an incorrect pointer access when checking access-control on concepts.
(#GH131530)
- Fixed various alias CTAD bugs involving variadic template arguments.
(#GH123591), (#GH127539), (#GH129077),
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index cecf5cff332f4..d8cc0171c22c6 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -11279,14 +11279,16 @@ class Sema final : public SemaBase {
/// The context in which we are checking a template parameter list.
enum TemplateParamListContext {
-TPC_ClassTemplate,
-TPC_VarTemplate,
+// For this context, Class, Variable, TypeAlias, and non-pack Template
+// Template Parameters are treated uniformly.
+TPC_Other,
+
TPC_FunctionTemplate,
TPC_ClassTemplateMember,
TPC_FriendClassTemplate,
TPC_FriendFunctionTemplate,
TPC_FriendFunctionTemplateDefinition,
-TPC_TypeAliasTemplate
+TPC_TemplateTemplateParameterPack,
};
/// Checks the validity of a template parameter list, possibly
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index f70401ea33b4a..41d5f9f2f3420 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8145,7 +8145,7 @@ NamedDecl *Sema::ActOnVariableDeclarator(
(D.getCXXScopeSpec().isSet() && DC && DC->isRecord() &&
DC->isDependentContext())
? TPC_ClassTemplateMember
- : TPC_VarTemplate))
+ : TPC_Other))
NewVD->setInvalidDecl();
// If we are providing an explicit specialization of a static variable
diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp
index e4e3bbad1f520..85de46c9adab4 100644
--- a/clang/lib/Sema/SemaDeclCXX.cpp
+++ b/clang/lib/Sema/SemaDeclCXX.cpp
@@ -13533,7 +13533,7 @@ Decl *Sema::ActOnAliasDeclaration(Scope *S,
AccessSpecifier AS,
// Merge any previous default template arguments into our parameters,
// and check the parameter list.
if (CheckTemplateParameterList(TemplateParams, OldTemplateParams,
- TPC_TypeAliasTemplate))
+ TPC_Other))
return nullptr;
TypeAliasTemplateDecl *NewDecl =
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 938671055333c..1c555b38277b0 100644
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -1591,8 +1591,16 @@ NamedDecl *Sema::ActOnTemplateTemplateParameter(
assert(S->isTemplateParamScope() &&
"Template template parameter not in template parameter scope!");
- // Construct the parameter object.
bool IsParameterPack = EllipsisLoc.isValid();
+
+ bool Invalid
[llvm-branch-commits] [clang] [clang-tools-extra] [clang][HeuristicResolver] Default argument heuristic for template parameters (PR #131074)
https://github.com/zyn0217 approved this pull request. Sorry for missing this. LGTM assuming @hokein is happy too. https://github.com/llvm/llvm-project/pull/131074 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/20.x: [rtsan][Apple] Add interceptor for _os_nospin_lock_lock (#131034) (PR #132997)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/132997 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
quic-garvgupt wrote: Hi @petrhosek @MaskRay, can you review this PR as well. This PR is also the part of the ongoing series of patches for merging RISCVToolchain object into baremetal toolchain object https://github.com/llvm/llvm-project/pull/121831 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Backport/20.x: [LoongArch] Fix the type of tls-le symbols (PR #133027)
MaskRay wrote: LGTM. Note: test/CodeGen is probably not the best place for such tests. `test/MC/CSKY/relocation-specifier.s` contains a nice example and tests multiple relocations at the same time. https://github.com/llvm/llvm-project/pull/133027 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
@@ -18,6 +18,6 @@ .globl _start _start: .data - .word foo@PLT - . - .word foo@PLT - . + 1 - .word foo@PLT - . - 1 + .word %plt(foo - .) jrtc27 wrote: I've not looked at the implementation in detail, but thank you for taking the time to do so, I know from experience it can be quite painful getting the MC code to do things that weren't previously expected of it https://github.com/llvm/llvm-project/pull/132569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
petrhosek wrote:
Could we make it conditional only on valid GCC installation?
```suggestion
if (GCCInstallation.isValid())
```
https://github.com/llvm/llvm-project/pull/121831
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[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::RLT_Libgcc;
+ return ToolChain::RLT_CompilerRT;
+}
+
+ToolChain::UnwindLibType
+BareMetal::GetUnwindLibType(const llvm::opt::ArgList &Args) const {
+ if (getTriple().isRISCV())
+return ToolChain::UNW_None;
petrhosek wrote:
Shouldn't this return `UNW_Libgcc`?
```suggestion
return ToolChain::UNW_Libgcc;
```
https://github.com/llvm/llvm-project/pull/121831
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[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::RLT_Libgcc;
+ return ToolChain::RLT_CompilerRT;
+}
+
+ToolChain::UnwindLibType
+BareMetal::GetUnwindLibType(const llvm::opt::ArgList &Args) const {
+ if (getTriple().isRISCV())
petrhosek wrote:
Could we make it conditional only on valid GCC installation?
```suggestion
if (GCCInstallation.isValid())
```
https://github.com/llvm/llvm-project/pull/121831
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[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
@@ -534,8 +554,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+ CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");
+CmdArgs.push_back("-X");
+ }
petrhosek wrote:
This would ideally be a separate PR which could land before the final removal
of `RISCVToolchain`.
https://github.com/llvm/llvm-project/pull/121831
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[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
https://github.com/david-xl approved this pull request. https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] [sanitizer] add pseudofunction to indicate array-bounds check (PR #128977)
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dbd24547b2304..dc3b253237e51 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3623,7 +3623,6 @@ void CodeGenFunction::EmitCheck(
llvm::Value *RecoverableCond = nullptr;
llvm::Value *TrapCond = nullptr;
bool NoMerge = false;
-
// Expand checks into:
// (Check1 || !allow_ubsan_check) && (Check2 || !allow_ubsan_check) ...
// We need separate allow_ubsan_check intrinsics because they have separately
@@ -3933,6 +3932,7 @@ void CodeGenFunction::EmitTrapCheck(llvm::Value *Checked,
TrapBBs.resize(CheckHandlerID + 1);
llvm::BasicBlock *&TrapBB = TrapBBs[CheckHandlerID];
+
NoMerge = NoMerge || !CGM.getCodeGenOpts().OptimizationLevel ||
(CurCodeDecl && CurCodeDecl->hasAttr());
>From a16b7a8c48353226fe1323a45f59cd4167ddc3d4 Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:15:20 -0800
Subject: [PATCH 2/4] rename & fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGDebugInfo.cpp | 7 ---
clang/lib/CodeGen/CGDebugInfo.h| 8 +---
clang/lib/CodeGen/CGExpr.cpp | 5 ++---
clang/test/CodeGen/bounds-checking-debuginfo.c | 4 ++--
4 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index ae19e8f724314..35fd78b15ff30 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3598,13 +3598,14 @@ llvm::DIMacroFile
*CGDebugInfo::CreateTempMacroFile(llvm::DIMacroFile *Parent,
return DBuilder.createTempMacroFile(Parent, Line, FName);
}
-llvm::DILocation *CGDebugInfo::CreateSyntheticInline(
-llvm::DebugLoc TrapLocation, StringRef FuncName) {
+llvm::DILocation *
+CGDebugInfo::CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName) {
llvm::DISubprogram *TrapSP =
createInlinedTrapSubprogram(FuncName, TrapLocation->getFile());
return llvm::DILocation::get(CGM.getLLVMContext(), /*Line=*/0, /*Column=*/0,
/*Scope=*/TrapSP, /*InlinedAt=*/TrapLocation);
-}
+}
llvm::DILocation *CGDebugInfo::CreateTrapFailureMessageFor(
llvm::DebugLoc TrapLocation, StringRef Category, StringRef FailureMsg) {
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 0b06bdf78ac78..d01ad3b3d8df5 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -638,9 +638,11 @@ class CGDebugInfo {
/// Create a debug location from `TrapLocation` that adds an artificial
inline
/// frame where the frame name is FuncName
///
- /// This is used to indiciate instructions that come from compiler
instrumentation.
- llvm::DILocation *CreateSyntheticInline(
- llvm::DebugLoc TrapLocation, StringRef FuncName);
+ /// This is used to indiciate instructions that come from compiler
+ /// instrumentation.
+ llvm::DILocation *CreateSyntheticInline(llvm::DebugLoc TrapLocation,
+ StringRef FuncName);
+
private:
/// Emit call to llvm.dbg.declare for a variable declaration.
/// Returns a pointer to the DILocalVariable associated with the
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index dc3b253237e51..d5cc2cc69c921 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1219,10 +1219,9 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E,
llvm::Value *Bound,
llvm::DILocation *TrapSP = Builder.getCurrentDebugLocation();
if (TrapSP) {
TrapSP = getDebugInfo()->CreateSyntheticInline(
- Builder.getCurrentDebugLocation(),
- "check_array_bounds");
+Builder.getCurrentDebugLocation(), "__ubsan_check_array_bounds");
}
- ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
+ ApplyDebugLocation ApplyTrapDI(*this, TrapSP);
bool IndexSigned = IndexType->isSignedIntegerOrEnumerationType();
llvm::Value *IndexVal = Builder.CreateIntCast(Index, SizeTy, IndexSigned);
diff --git a/clang/test/CodeGen/bounds-checking-debuginfo.c
b/clang/test/CodeGen/bounds-checking-debuginfo.c
index e2a604bc962ba..58fcc89058d72 100644
--- a/clang/test/CodeGen/bounds-checking-debuginfo.c
+++ b/clang/test/CodeGen/bounds-checking-debuginfo.c
@@ -89,7 +89,7 @@ double f1(int b, int i) {
// CHECK-TRAP: [[DBG22]] = !DILocation(line: 65, column: 3, scope: [[DBG5]])
// CHECK-TRAP: [[DBG23]] = !DILocation(line: 66, column: 12, scope: [[DBG5]])
// CHECK-TRAP: [[DBG24]] = !DILocation(line: 0, scope: [[META
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
petrhosek wrote:
Could we make it conditional only on valid GCC installation?
```suggestion
if (GCCInstallation.isValid())
```
https://github.com/llvm/llvm-project/pull/121831
___
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llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object (PR #121831)
@@ -54,12 +54,11 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public
Generic_ELF {
return UnwindTableLevel::None;
}
- RuntimeLibType GetDefaultRuntimeLibType() const override {
-return ToolChain::RLT_CompilerRT;
- }
- CXXStdlibType GetDefaultCXXStdlibType() const override {
-return ToolChain::CST_Libcxx;
- }
+ CXXStdlibType GetDefaultCXXStdlibType() const override;
+
+ RuntimeLibType GetDefaultRuntimeLibType() const override;
+
+ UnwindLibType GetUnwindLibType(const llvm::opt::ArgList &Args) const
override;
petrhosek wrote:
These changes would ideally be separate from the final removal of the
`RISCVToolchain` at which point that should be effectively a no-op.
https://github.com/llvm/llvm-project/pull/121831
___
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[llvm-branch-commits] [compiler-rt] release/20.x: [rtsan][Apple] Add interceptor for _os_nospin_lock_lock (#131034) (PR #132997)
github-actions[bot] wrote: ⚠️ We detected that you are using a GitHub private e-mail address to contribute to the repo. Please turn off [Keep my email addresses private](https://github.com/settings/emails) setting in your account. See [LLVM Discourse](https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it) for more information. https://github.com/llvm/llvm-project/pull/132997 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: Detect address materialization and arithmetics (PR #132540)
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/132540
>From de28401e6c4f68117f0b71f2b08c3c065b286f62 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Thu, 20 Mar 2025 20:15:07 +0300
Subject: [PATCH] [BOLT] Gadget scanner: Detect address materialization and
arithmetics
In addition to authenticated pointers, consider the contents of a
register safe if it was
* written by PC-relative address computation
* updated by an arithmetic instruction whose input address is safe
---
bolt/include/bolt/Core/MCPlusBuilder.h| 16 ++
bolt/lib/Passes/PAuthGadgetScanner.cpp| 92 +--
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 30 +++
.../AArch64/gs-pacret-autiasp.s | 15 --
.../gs-pauth-address-materialization.s| 228 ++
.../binary-analysis/AArch64/lit.local.cfg | 3 +-
6 files changed, 345 insertions(+), 39 deletions(-)
create mode 100644
bolt/test/binary-analysis/AArch64/gs-pauth-address-materialization.s
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h
b/bolt/include/bolt/Core/MCPlusBuilder.h
index 8b6dc14121480..e94f82d00349a 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -587,6 +587,22 @@ class MCPlusBuilder {
return getNoRegister();
}
+ virtual MCPhysReg getSafelyMaterializedAddressReg(const MCInst &Inst) const {
+llvm_unreachable("not implemented");
+return getNoRegister();
+ }
+
+ /// Analyzes if this instruction can safely perform address arithmetics.
+ ///
+ /// If the first element of the returned pair is no-register, this
instruction
+ /// is considered unknown. Otherwise, (output, input) pair is returned,
+ /// so that output is as trusted as input is.
+ virtual std::pair
+ analyzeSafeAddressArithmetics(const MCInst &Inst) const {
+llvm_unreachable("not implemented");
+return std::make_pair(getNoRegister(), getNoRegister());
+ }
+
virtual bool isTerminator(const MCInst &Inst) const;
virtual bool isNoop(const MCInst &Inst) const {
diff --git a/bolt/lib/Passes/PAuthGadgetScanner.cpp
b/bolt/lib/Passes/PAuthGadgetScanner.cpp
index dcc7d93183900..33f925070290e 100644
--- a/bolt/lib/Passes/PAuthGadgetScanner.cpp
+++ b/bolt/lib/Passes/PAuthGadgetScanner.cpp
@@ -335,6 +335,50 @@ class PacRetAnalysis
});
}
+ BitVector getClobberedRegs(const MCInst &Point) const {
+BitVector Clobbered(NumRegs, false);
+// Assume a call can clobber all registers, including callee-saved
+// registers. There's a good chance that callee-saved registers will be
+// saved on the stack at some point during execution of the callee.
+// Therefore they should also be considered as potentially modified by an
+// attacker/written to.
+// Also, not all functions may respect the AAPCS ABI rules about
+// caller/callee-saved registers.
+if (BC.MIB->isCall(Point))
+ Clobbered.set();
+else
+ BC.MIB->getClobberedRegs(Point, Clobbered);
+return Clobbered;
+ }
+
+ // Returns all registers that can be treated as if they are written by an
+ // authentication instruction.
+ SmallVector getAuthenticatedRegs(const MCInst &Point,
+ const State &Cur) const {
+SmallVector Regs;
+const MCPhysReg NoReg = BC.MIB->getNoRegister();
+
+// A signed pointer can be authenticated, or
+ErrorOr AutReg = BC.MIB->getAuthenticatedReg(Point);
+if (AutReg && *AutReg != NoReg)
+ Regs.push_back(*AutReg);
+
+// ... a safe address can be materialized, or
+MCPhysReg NewAddrReg = BC.MIB->getSafelyMaterializedAddressReg(Point);
+if (NewAddrReg != NoReg)
+ Regs.push_back(NewAddrReg);
+
+// ... an address can be updated in a safe manner, producing the result
+// which is as trusted as the input address.
+MCPhysReg ArithResult, ArithSrc;
+std::tie(ArithResult, ArithSrc) =
+BC.MIB->analyzeSafeAddressArithmetics(Point);
+if (ArithResult != NoReg && Cur.SafeToDerefRegs[ArithSrc])
+ Regs.push_back(ArithResult);
+
+return Regs;
+ }
+
State computeNext(const MCInst &Point, const State &Cur) {
PacStatePrinter P(BC);
LLVM_DEBUG({
@@ -355,19 +399,20 @@ class PacRetAnalysis
return State();
}
+// First, compute various properties of the instruction, taking the state
+// before its execution into account, if necessary.
+
+BitVector Clobbered = getClobberedRegs(Point);
+// Compute the set of registers that can be considered as written by
+// an authentication instruction. This includes operations that are
+// *strictly better* than authentication, such as materializing a
+// PC-relative constant.
+SmallVector AuthenticatedOrBetter =
+getAuthenticatedRegs(Point, Cur);
+
+// Then, compute the state after this instruction is executed.
State Next = Cur;
-BitVector Clobbered(NumRegs, false);
-// Assume a call can clo
[llvm-branch-commits] [llvm] Backport/20.x: [LoongArch] Fix the type of tls-le symbols (PR #133027)
https://github.com/SixWeining approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/133027 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Driver] Fix link order of BareMetal toolchain object (PR #132806)
https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/132806 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [GlobalISel] Combine redundant sext_inreg (PR #131624)
@@ -0,0 +1,164 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s cdevadas wrote: Drop the -verify-machineinstrs if they aren't significant here. https://github.com/llvm/llvm-project/pull/131624 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [GlobalISel] Combine redundant sext_inreg (PR #131624)
@@ -0,0 +1,87 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s cdevadas wrote: Ditto. https://github.com/llvm/llvm-project/pull/131624 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] llvm-reduce: Do not reduce alloca array sizes to 0 (PR #132864)
https://github.com/aeubanks approved this pull request. https://github.com/llvm/llvm-project/pull/132864 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Driver] Fix link order of BareMetal toolchain object (PR #132806)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/132806 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824) (PR #132932)
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: None (llvmbot)
Changes
Backport 975c208556ef85b321a223fe592fa6d98fadfaa0
Requested by: @phoebewang
---
Patch is 106.53 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/132932.diff
15 Files Affected:
- (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+10-10)
- (modified) llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll (+10-10)
- (modified) llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt (+27-27)
- (modified) llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt (+27-27)
- (modified) llvm/test/MC/Disassembler/X86/avx10.2-com-ef-32.txt (+48-48)
- (modified) llvm/test/MC/Disassembler/X86/avx10.2-com-ef-64.txt (+48-48)
- (modified) llvm/test/MC/X86/avx10.2-bf16-32-att.s (+27-27)
- (modified) llvm/test/MC/X86/avx10.2-bf16-32-intel.s (+27-27)
- (modified) llvm/test/MC/X86/avx10.2-bf16-64-att.s (+27-27)
- (modified) llvm/test/MC/X86/avx10.2-bf16-64-intel.s (+27-27)
- (modified) llvm/test/MC/X86/avx10.2-com-ef-32-att.s (+48-48)
- (modified) llvm/test/MC/X86/avx10.2-com-ef-32-intel.s (+48-48)
- (modified) llvm/test/MC/X86/avx10.2-com-ef-64-att.s (+48-48)
- (modified) llvm/test/MC/X86/avx10.2-com-ef-64-intel.s (+48-48)
``diff
diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td
b/llvm/lib/Target/X86/X86InstrAVX10.td
index 9bb3e364f7c62..37d3b0a67cd33 100644
--- a/llvm/lib/Target/X86/X86InstrAVX10.td
+++ b/llvm/lib/Target/X86/X86InstrAVX10.td
@@ -1468,7 +1468,7 @@ defm VRSQRT : avx10_fp14_bf16<0x4E, "vrsqrt",
X86rsqrt14, SchedWriteFRsqrt>,
defm VRCP: avx10_fp14_bf16<0x4C, "vrcp", X86rcp14, SchedWriteFRcp>,
T_MAP6, PS, EVEX_CD8<16, CD8VF>;
defm VGETEXP : avx10_fp14_bf16<0x42, "vgetexp", X86fgetexp, SchedWriteFRnd>,
-T_MAP5, EVEX_CD8<16, CD8VF>;
+T_MAP6, PS, EVEX_CD8<16, CD8VF>;
// VSCALEFBF16
multiclass avx10_fp_scalef_bf16 opc, string OpcodeStr,
@@ -1665,31 +1665,31 @@ multiclass avx10_com_ef_int Opc,
X86VectorVTInfo _, SDNode OpNode,
let Defs = [EFLAGS], Uses = [MXCSR], Predicates = [HasAVX10_2] in {
defm VUCOMXSDZ : avx10_com_ef<0x2e, FR64X, f64, X86ucomi512,
"vucomxsd", f64mem, loadf64,
SSEPackedDouble>,
- TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;
+ TB, XD, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;
defm VUCOMXSHZ : avx10_com_ef<0x2e, FR16X, f16, X86ucomi512,
"vucomxsh", f16mem, loadf16,
SSEPackedSingle>,
- T_MAP5, XD, EVEX_CD8<16, CD8VT1>;
+ T_MAP5, XS, EVEX_CD8<16, CD8VT1>;
defm VUCOMXSSZ : avx10_com_ef<0x2e, FR32X, f32, X86ucomi512,
"vucomxss", f32mem, loadf32,
SSEPackedSingle>,
- TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
+ TB, XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
defm VCOMXSDZ : avx10_com_ef_int<0x2f, v2f64x_info, X86comi512,
"vcomxsd", SSEPackedDouble>,
- TB, XS, VEX_LIG, REX_W, EVEX_CD8<64,
CD8VT1>;
+ TB, XD, VEX_LIG, REX_W, EVEX_CD8<64,
CD8VT1>;
defm VCOMXSHZ : avx10_com_ef_int<0x2f, v8f16x_info, X86comi512,
"vcomxsh", SSEPackedSingle>,
- T_MAP5, XD, EVEX_CD8<16, CD8VT1>;
+ T_MAP5, XS, EVEX_CD8<16, CD8VT1>;
defm VCOMXSSZ : avx10_com_ef_int<0x2f, v4f32x_info, X86comi512,
"vcomxss", SSEPackedSingle>,
- TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
+ TB, XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
defm VUCOMXSDZ : avx10_com_ef_int<0x2e, v2f64x_info, X86ucomi512,
"vucomxsd", SSEPackedDouble>,
- TB, XS, VEX_LIG, REX_W, EVEX_CD8<64,
CD8VT1>;
+ TB, XD, VEX_LIG, REX_W, EVEX_CD8<64,
CD8VT1>;
defm VUCOMXSHZ : avx10_com_ef_int<0x2e, v8f16x_info, X86ucomi512,
"vucomxsh", SSEPackedSingle>,
- T_MAP5, XD, EVEX_CD8<16, CD8VT1>;
+ T_MAP5, XS, EVEX_CD8<16, CD8VT1>;
defm VUCOMXSSZ : avx10_com_ef_int<0x2e, v4f32x_info, X86ucomi512,
"vucomxss", SSEPackedSingle>,
- TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
+ TB, XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
}
//-
diff --git a/llvm/test/CodeGen/X
[llvm-branch-commits] [llvm] AMDGPU: Start considering new atomicrmw metadata on integer operations (PR #122138)
yxsamliu wrote: > > Clang adds !amdgpu.no.fine.grained.memory and !amdgpu.no.remote.memory to > > any atomic instructions by default. I think this behavior is expected to > > keep ISA unchanged compared to the ISA before these metatadat were > > introduced. Did I miss anything? > > All of the tests that fail are atomicMin_system and atomicMax_system. I would > expect that the explicit system scoped functions would not be using these > annotations. With this PR, these tests are switching from CAS expansion to > the direct instruction. > > It just happens that the integer min and max are the cases we handled > conservatively before, so it's possible the test is just wrong in some way I investigated a similar issue about `__hip_atomic_fetch_max` for float on gfx1100. https://github.com/ROCm/hip-tests/blob/amd-staging/catch/unit/atomics/__hip_atomic_fetch_max.cc#L46 Basically it sets the original memory with 5.5 and do an atomic float max with 7.5, so the expected value in the memory should be 7.5 but we got 5.5. It was triggered by my clang change to add no_remote_memory and no_fine_grained_memory to atomicRMW max instruction. Before my change, the backend emits global_atomic_cmpswp_b32. After my change, the backend emits global_atomic_max_f32. The test tried shared memory and global memory allocated in different ways: https://github.com/ROCm/hip-tests/blob/amd-staging/catch/include/resource_guards.hh#L63 shared memory passes memory allocated by hipMalloc, malloc/hipHostRegister, hipMallocManaged passes only memory allocated by hipHostMalloc fails I think the difference is that hipHostMalloc allocates fine-grained memory, so it violates the requirement no_fine_grained_memory imposed on the atomic max instruction. If I add [[clang::atomic(fine_grained_memory)]] to the block that calls `__hip_atomic_fetch_max` (https://github.com/ROCm/hip-tests/blob/amd-staging/catch/unit/atomics/min_max_common.hh#L85), the test passes. I think this verifies that the atomic attribute works. https://github.com/llvm/llvm-project/pull/122138 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/130967
>From e2e0d44800b65a8fbddd6234c2ee9f83af92d7da Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 12 Mar 2025 21:14:42 +0700
Subject: [PATCH 1/3] Add missing NO-VIS lines
Created using spr 1.3.5
---
llvm/test/MC/Sparc/sparc-vis.s | 11 +++
1 file changed, 11 insertions(+)
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index bf01da19293d0..bed901b6a7272 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -199,28 +199,39 @@ fcmpeq16 %f0, %f2, %o0
! VIS: fcmpeq32 %f0, %f2, %o0 ! encoding:
[0x91,0xb0,0x05,0xc2]
fcmpeq32 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge8 %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x00,0x09]
edge8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge8l %o0, %o1, %o2! encoding:
[0x95,0xb2,0x00,0x49]
edge8l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge16 %o0, %o1, %o2! encoding:
[0x95,0xb2,0x00,0x89]
edge16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge16l %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x00,0xc9]
edge16l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge32 %o0, %o1, %o2! encoding:
[0x95,0xb2,0x01,0x09]
edge32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge32l %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x01,0x49]
edge32l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: pdist %f0, %f2, %f4 ! encoding:
[0x89,0xb0,0x07,0xc2]
pdist %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array8 %o0, %o1, %o2! encoding:
[0x95,0xb2,0x02,0x09]
array8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array16 %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x02,0x49]
array16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array32 %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x02,0x89]
array32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: shutdown! encoding:
[0x81,0xb0,0x10,0x00]
shutdown
>From b98295fcdaa9fc1d6a839956c304dd5a7d31cc24 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 12 Mar 2025 22:27:36 +0700
Subject: [PATCH 2/3] Fix typo in comment
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td
b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index 6d0f12da3afcf..fbf56ae22cd30 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -7,7 +7,7 @@
//===--===//
//
// This file contains instruction formats, definitions and patterns needed for
-// VIS, VIS II, VIS II instructions on SPARC.
+// VIS, VIS II, VIS III instructions on SPARC.
//===--===//
// VIS Instruction Format.
>From 618c4853f63fa60bd6d6d0e9ec69d6149e2b2137 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Sun, 23 Mar 2025 20:51:40 +0700
Subject: [PATCH 3/3] Apply suggestions
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrFormats.td | 4 ++--
llvm/lib/Target/Sparc/SparcInstrInfo.td| 3 ++-
llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
llvm/test/MC/Sparc/sparc-vis.s | 2 +-
llvm/test/MC/Sparc/sparc-vis2.s| 2 +-
llvm/test/MC/Sparc/sparc-vis3.s| 2 +-
6 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td
b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 7d32cd8e5671b..3ddb485923fcc 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -205,7 +205,7 @@ class F3_3c opVal, bits<6> op3val, bits<9> opfval,
dag outs, dag ins,
class F3_3_siam opVal, bits<6> op3val, bits<9> opfval, dag outs, dag
ins,
string asmstr, list pattern, InstrItinClass itin = NoItinerary>
: F3 {
- bits<3> siam_mode;
+ bits<3> uimm3;
let op = opVal;
let op3= op3val;
@@ -213,7 +213,7 @@ class F3_3_siam opVal, bits<6> op3val, bits<9>
opfval, dag outs, dag ins
let rs1= 0;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-3} = 0;
- let Inst{2-0} = siam_mode;
+ let Inst{2-0} = uimm3;
}
//
[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)
alexrp wrote: Seems like the tests are failing because #126880 hasn't been backported. Probably should just adjust the tests accordingly. What's standard practice here? Should someone with commit access just push a fix to the PR branch? https://github.com/llvm/llvm-project/pull/132049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
@@ -0,0 +1,676 @@ +// RUN: %clang %cflags -march=armv8.3-a %s -o %t.exe +// RUN: llvm-bolt-binary-analysis --scanners=pacret %t.exe 2>&1 | FileCheck %s kbeyls wrote: I'm wondering if the user interface for this should be adapted? `pac-ret` is a widely deployed hardening scheme, so just verifying the correct application of pac-ret hardening is something that users presumably want to do, without also checking pauthabi hardening guarantees that do not exist in pac-ret? Maybe the checking of non-protected indirect calls should happen under a different `--scanners` option? https://github.com/llvm/llvm-project/pull/131899 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [Clang] Fix various bugs in alias CTAD transform (PR #132697)
https://github.com/cor3ntin approved this pull request. https://github.com/llvm/llvm-project/pull/132697 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
@@ -577,6 +577,16 @@ class MCPlusBuilder {
return getNoRegister();
}
+ /// Returns the register used as call destination, or no-register, if not
+ /// an indirect call. Sets IsAuthenticatedInternally if the instruction
+ /// accepts signed pointer as its operand and authenticates it internally.
atrosinenko wrote:
Applied, thanks!
https://github.com/llvm/llvm-project/pull/131899
___
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[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
https://github.com/kbeyls commented: I haven't had time yet to review the test cases, but I thought I'd share my comments so far already. https://github.com/llvm/llvm-project/pull/131899 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
@@ -0,0 +1,676 @@ +// RUN: %clang %cflags -march=armv8.3-a %s -o %t.exe +// RUN: llvm-bolt-binary-analysis --scanners=pacret %t.exe 2>&1 | FileCheck %s + +// FIXME In the below test cases, LR is usually not spilled as needed, as it is +// not checked by BOLT. kbeyls wrote: I'm wondering if this needs to be a FIXME, or simply a note to explain that the test cases are simplified/artificial? I don't think I've got a strong opinion either way. Presumably, it'd be better for the test cases to be closer to "real-world" code, so ideally, they should have the ldp/stp spill/fill instructions? https://github.com/llvm/llvm-project/pull/131899 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
@@ -277,6 +277,48 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ MCPhysReg
+ getRegUsedAsCallDest(const MCInst &Inst,
+ bool &IsAuthenticatedInternally) const override {
kbeyls wrote:
I'm wondering if this could be adapt so that it only needs to handle indirect
calls?
That would make the switch statement simpler, and also easier to maintain,
because it won't need to handle all branch instructions.
For example, at the moment, it seems the switch statement is not handling the
newly introduced (in armv9.5) Compare and Branch instructions, see
[https://developer.arm.com/documentation/ddi0602/2024-09/Base-Instructions/CB-cc---register---Compare-registers-and-branch-](https://developer.arm.com/documentation/ddi0602/2024-12/Base-Instructions/CB-cc---register---Compare-registers-and-branch-)
My understanding is that only indirect calls need to be checked, not direct
calls.
https://github.com/llvm/llvm-project/pull/131899
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[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: detect non-protected indirect calls (PR #131899)
@@ -382,11 +382,11 @@ class PacRetAnalysis
public:
std::vector
- getLastClobberingInsts(const MCInst Ret, BinaryFunction &BF,
- const ArrayRef UsedDirtyRegs) const {
kbeyls wrote:
I was wondering whether `const` has to be removed here.
Looking at the implementation of `getStateAt` and `getStateBefore`, it seems
that it might be better to add the `const` qualifier to `getStateBefore` at
https://github.com/llvm/llvm-project/blob/9768077de65e31daa619eae231f027e052d601c2/bolt/include/bolt/Passes/DataflowAnalysis.h#L295?
https://github.com/llvm/llvm-project/pull/131899
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[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/130967
>From e2e0d44800b65a8fbddd6234c2ee9f83af92d7da Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 12 Mar 2025 21:14:42 +0700
Subject: [PATCH 1/3] Add missing NO-VIS lines
Created using spr 1.3.5
---
llvm/test/MC/Sparc/sparc-vis.s | 11 +++
1 file changed, 11 insertions(+)
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index bf01da19293d0..bed901b6a7272 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -199,28 +199,39 @@ fcmpeq16 %f0, %f2, %o0
! VIS: fcmpeq32 %f0, %f2, %o0 ! encoding:
[0x91,0xb0,0x05,0xc2]
fcmpeq32 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge8 %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x00,0x09]
edge8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge8l %o0, %o1, %o2! encoding:
[0x95,0xb2,0x00,0x49]
edge8l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge16 %o0, %o1, %o2! encoding:
[0x95,0xb2,0x00,0x89]
edge16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge16l %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x00,0xc9]
edge16l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge32 %o0, %o1, %o2! encoding:
[0x95,0xb2,0x01,0x09]
edge32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge32l %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x01,0x49]
edge32l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: pdist %f0, %f2, %f4 ! encoding:
[0x89,0xb0,0x07,0xc2]
pdist %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array8 %o0, %o1, %o2! encoding:
[0x95,0xb2,0x02,0x09]
array8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array16 %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x02,0x49]
array16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array32 %o0, %o1, %o2 ! encoding:
[0x95,0xb2,0x02,0x89]
array32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: shutdown! encoding:
[0x81,0xb0,0x10,0x00]
shutdown
>From b98295fcdaa9fc1d6a839956c304dd5a7d31cc24 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 12 Mar 2025 22:27:36 +0700
Subject: [PATCH 2/3] Fix typo in comment
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td
b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index 6d0f12da3afcf..fbf56ae22cd30 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -7,7 +7,7 @@
//===--===//
//
// This file contains instruction formats, definitions and patterns needed for
-// VIS, VIS II, VIS II instructions on SPARC.
+// VIS, VIS II, VIS III instructions on SPARC.
//===--===//
// VIS Instruction Format.
>From 618c4853f63fa60bd6d6d0e9ec69d6149e2b2137 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Sun, 23 Mar 2025 20:51:40 +0700
Subject: [PATCH 3/3] Apply suggestions
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrFormats.td | 4 ++--
llvm/lib/Target/Sparc/SparcInstrInfo.td| 3 ++-
llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
llvm/test/MC/Sparc/sparc-vis.s | 2 +-
llvm/test/MC/Sparc/sparc-vis2.s| 2 +-
llvm/test/MC/Sparc/sparc-vis3.s| 2 +-
6 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td
b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 7d32cd8e5671b..3ddb485923fcc 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -205,7 +205,7 @@ class F3_3c opVal, bits<6> op3val, bits<9> opfval,
dag outs, dag ins,
class F3_3_siam opVal, bits<6> op3val, bits<9> opfval, dag outs, dag
ins,
string asmstr, list pattern, InstrItinClass itin = NoItinerary>
: F3 {
- bits<3> siam_mode;
+ bits<3> uimm3;
let op = opVal;
let op3= op3val;
@@ -213,7 +213,7 @@ class F3_3_siam opVal, bits<6> op3val, bits<9>
opfval, dag outs, dag ins
let rs1= 0;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-3} = 0;
- let Inst{2-0} = siam_mode;
+ let Inst{2-0} = uimm3;
}
//
[llvm-branch-commits] [clang] [Driver] Add support for crtbegin.o, crtend.o and libgloss lib to BareMetal toolchain object (PR #121830)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From 077eae0ad90d07540f3d84ac084488bc29cbf37e Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 04:58:57 -0700
Subject: [PATCH] [Driver] Add support for crtbegin.o, crtend.o and libgloss
lib to BareMetal toolchain object
This patch conditionalise the addition of crt{begin,end}.o object files along
with addition of -lgloss lib based on whether libc selected is newlib or llvm
libc. Since there is no way a user can specify which libc it wants to link
against, currently passing valid GCCInstallation to driver will select newlib
otherwise it will default to llvm libc.
Moreover, this patch makes gnuld the default linker for baremetal toolchain
object. User need to pass `-fuse-ld=lld` explicitly to driver to select lld
This is the 2nd patch in the series of patches of merging RISCVToolchain into
BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: Ie06dc976c306cf04ec2733bbb2d271c57d201f86
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 34 +++-
clang/lib/Driver/ToolChains/BareMetal.h | 3 +-
clang/test/Driver/aarch64-toolchain-extra.c | 13 ++-
clang/test/Driver/aarch64-toolchain.c | 83 +++
clang/test/Driver/arm-toolchain-extra.c | 7 ++
clang/test/Driver/arm-toolchain.c | 88 -
clang/test/Driver/baremetal.cpp | 3 +-
clang/test/Driver/sanitizer-ld.c| 2 +-
8 files changed, 220 insertions(+), 13 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index b2e62e3d254af..7ec6d86d998a4 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -545,9 +545,27 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back(Arch == llvm::Triple::aarch64_be ? "-EB" : "-EL");
}
- if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles,
- options::OPT_r)) {
-CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath("crt0.o")));
+ bool WantCRTs =
+ !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles);
+
+ const char *crtbegin, *crtend;
+ if (WantCRTs) {
+if (!Args.hasArg(options::OPT_r))
+ CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath("crt0.o")));
+if (TC.hasValidGCCInstallation() || hasGCCToolChainAlongSideClang(D)) {
+ auto RuntimeLib = TC.GetRuntimeLibType(Args);
+ if (RuntimeLib == ToolChain::RLT_Libgcc) {
+crtbegin = "crtbegin.o";
+crtend = "crtend.o";
+ } else {
+assert(RuntimeLib == ToolChain::RLT_CompilerRT);
+crtbegin =
+TC.getCompilerRTArgString(Args, "crtbegin", ToolChain::FT_Object);
+crtend =
+TC.getCompilerRTArgString(Args, "crtend", ToolChain::FT_Object);
+ }
+ CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(crtbegin)));
+}
}
Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_T_Group,
@@ -570,9 +588,12 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
}
if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs)) {
+CmdArgs.push_back("--start-group");
AddRunTimeLibs(TC, D, CmdArgs, Args);
-
CmdArgs.push_back("-lc");
+if (TC.hasValidGCCInstallation() || hasGCCToolChainAlongSideClang(D))
+ CmdArgs.push_back("-lgloss");
+CmdArgs.push_back("--end-group");
}
if (D.isUsingLTO()) {
@@ -588,6 +609,11 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
addLTOOptions(TC, Args, CmdArgs, Output, *Input,
D.getLTOMode() == LTOK_Thin);
}
+
+ if ((TC.hasValidGCCInstallation() || hasGCCToolChainAlongSideClang(D)) &&
+ WantCRTs)
+CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(crtend)));
+
if (TC.getTriple().isRISCV())
CmdArgs.push_back("-X");
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index 2a791e7672e5e..87f173342def2 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public Generic_ELF {
Tool *buildStaticLibTool() const override;
public:
+ bool hasValidGCCInstallation() const { return GCCInstallation.isValid(); }
bool isBareMetal() const override { return true; }
bool isCrossCompiling() const override { return true; }
bool HasNativeLLVMSupport() const override { return true; }
@@ -60,8 +61,6 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public Generic_ELF {
return ToolChain::CST_Libcxx;
}
- const char *getDefaultLinker() const override { return "ld.lld"; }
-
void
AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
llvm::opt::ArgStringList &CC
[llvm-branch-commits] [clang] [Driver] Fix link order of BareMetal toolchain object (PR #132806)
https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/132806 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][memref] Remove runtime verification for `memref.reinterpret_cast` (PR #132547)
matthias-springer wrote: > I think this is OK, but when we create a new memref, dont we want to verify > that the strides specified dont make it such that accessing using strides > goes out of bounds? By "create a new memref" you mean the reinterpret_cast result, right? I'd say you don't want to verify this. Maybe you know that the source memref is a view into a larger allocation, so out-of-bounds access is safe. I think of it like a C++ reinterpret_cast, there you can cast to almost an arbitrary memref type. https://github.com/llvm/llvm-project/pull/132547 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
