[llvm-branch-commits] [llvm] AMDGPU: Remove undef in subreg-coalescer-crash.ll (PR #131256)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/131256

None

>From c2d9e5b611da357eea217904717d6676e4646eaa Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:35:11 +0700
Subject: [PATCH] AMDGPU: Remove undef in subreg-coalescer-crash.ll

---
 .../CodeGen/AMDGPU/subreg-coalescer-crash.ll  | 32 +++
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index a0ac6c1b28449..a69ee2e1a8b5c 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -9,17 +9,19 @@ define amdgpu_kernel void @row_filter_C1_D0() #0 {
 ; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
 ; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
-  br i1 undef, label %for.inc.1, label %do.body.preheader
+  br i1 poison, label %for.inc.1, label %do.body.preheader
 
 do.body.preheader:; preds = %entry
   %tmp = insertelement <4 x i32> zeroinitializer, i32 poison, i32 1
-  br i1 undef, label %do.body56.1, label %do.body90
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %do.body56.1, label %do.body90
 
 do.body90:; preds = %do.body56.2, 
%do.body56.1, %do.body.preheader
   %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ 
%tmp, %do.body.preheader ]
   %tmp2 = insertelement <4 x i32> %tmp1, i32 poison, i32 2
   %tmp3 = insertelement <4 x i32> %tmp2, i32 poison, i32 3
-  br i1 undef, label %do.body124.1, label %do.body.1562.preheader
+  %undef3 = freeze i1 poison
+  br i1 %undef3, label %do.body124.1, label %do.body.1562.preheader
 
 do.body.1562.preheader:   ; preds = %do.body124.1, 
%do.body90
   %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
@@ -28,7 +30,7 @@ do.body.1562.preheader:   ; preds = 
%do.body124.1, %do.b
 
 do.body56.1:  ; preds = %do.body.preheader
   %tmp5 = insertelement <4 x i32> %tmp, i32 poison, i32 1
-  %or.cond472.1 = or i1 undef, undef
+  %or.cond472.1 = or i1 poison, poison
   br i1 %or.cond472.1, label %do.body56.2, label %do.body90
 
 do.body56.2:  ; preds = %do.body56.1
@@ -41,7 +43,8 @@ do.body124.1: ; preds = 
%do.body90
 
 for.inc.1:; preds = 
%do.body.1562.preheader, %entry
   %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, 
%do.body.1562.preheader ]
-  %add.i495 = add <4 x i32> %storemerge591, undef
+  %undef2 = freeze <4 x i32> poison
+  %add.i495 = add <4 x i32> %storemerge591, %undef2
   unreachable
 }
 
@@ -68,24 +71,27 @@ define amdgpu_ps void @foo() #0 {
 ; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
 ; GCN-NEXT:s_endpgm
 bb:
-  br i1 undef, label %bb2, label %bb1
+  %undef0 = freeze i1 poison
+  br i1 %undef0, label %bb2, label %bb1
 
 bb1:  ; preds = %bb
-  br i1 undef, label %bb4, label %bb6
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %bb4, label %bb6
 
 bb2:  ; preds = %bb4, %bb
   %tmp = phi float [ %tmp5, %bb4 ], [ 0.00e+00, %bb ]
-  br i1 undef, label %bb9, label %bb13
+  br i1 poison, label %bb9, label %bb13
 
 bb4:  ; preds = %bb7, %bb6, %bb1
   %tmp5 = phi float [ poison, %bb1 ], [ poison, %bb6 ], [ %tmp8, %bb7 ]
   br label %bb2
 
 bb6:  ; preds = %bb1
-  br i1 undef, label %bb7, label %bb4
+  %undef2 = freeze i1 poison
+  br i1 %undef2, label %bb7, label %bb4
 
 bb7:  ; preds = %bb6
-  %tmp8 = fmul float undef, undef
+  %tmp8 = fmul float poison, poison
   br label %bb4
 
 bb9:  ; preds = %bb2
@@ -95,7 +101,7 @@ bb9:  ; preds = 
%bb2
   br label %bb14
 
 bb13: ; preds = %bb2
-  br i1 undef, label %bb23, label %bb24
+  br i1 poison, label %bb23, label %bb24
 
 bb14: ; preds = %bb27, %bb24, %bb9
   %tmp15 = phi float [ %tmp12, %bb9 ], [ poison, %bb27 ], [ 0.00e+00, 
%bb24 ]
@@ -106,11 +112,11 @@ bb14: ; preds 
= %bb27, %bb24, %bb9
   ret void
 
 bb23: ; preds = %bb13
-  br i1 undef, label %bb24, label %bb26
+  br i1 poison, label %bb24, label %bb26
 
 bb24: ; preds = %bb26, %bb23, %bb13
   %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.00e+00, %bb23 ]
-  br i1 undef, label %bb27, label %bb14
+  br i1 poison, label %bb27, label %bb14
 
 bb26:

[llvm-branch-commits] [llvm] AMDGPU: Switch a test to generated checks which only tested labels (PR #131257)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes

Also remove an undef use

---
Full diff: https://github.com/llvm/llvm-project/pull/131257.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll (+47-6) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll 
b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
index d198ec28f1602..21d4bcfcdc8c1 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
@@ -1,16 +1,58 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck 
%s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck 
%s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
-; CHECK-LABEL: {{^}}main:
-;
 ; Test for compilation only. This generated an invalid machine instruction
 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
+; GFX6-LABEL: main:
+; GFX6:   ; %bb.0: ; %main_body
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %IF57
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %IF60
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf4
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX6-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX6-NEXT:s_branch .LBB0_7
+; GFX6-NEXT:  .LBB0_6: ; %IF63
+; GFX6-NEXT:  .LBB0_7:
+;
+; GFX8-LABEL: main:
+; GFX8:   ; %bb.0: ; %main_body
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %IF57
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3c0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %IF60
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3d0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX8-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX8-NEXT:s_branch .LBB0_7
+; GFX8-NEXT:  .LBB0_6: ; %IF63
+; GFX8-NEXT:  .LBB0_7:
 main_body:
   %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, 
i32 0)
   %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, 
i32 0)
-  br i1 undef, label %ENDIF56, label %IF57
+  br i1 poison, label %ENDIF56, label %IF57
 
 IF57: ; preds = %ENDIF
   %v.1 = mul i32 %v, 2
@@ -40,7 +82,6 @@ ENDIF62:  ; preds = 
%ENDIF59
   ret float %r
 }
 
-; Function Attrs: nounwind readnone
 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
 
 attributes #0 = { nounwind readnone }

``




https://github.com/llvm/llvm-project/pull/131257
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[llvm-branch-commits] [llvm] AMDGPU: Remove undef in subreg-coalescer-crash.ll (PR #131256)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

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[llvm-branch-commits] [llvm] AMDGPU: Replace undef references with poison in some MIR tests (PR #131254)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm ready_for_review 
https://github.com/llvm/llvm-project/pull/131254
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[llvm-branch-commits] [llvm] AMDGPU: Switch a test to generated checks which only tested labels (PR #131257)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

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[llvm-branch-commits] [llvm] AMDGPU: Switch a test with only function label checks to generated (PR #131255)

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[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

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[llvm-branch-commits] [llvm] AMDGPU: Switch a test with only function label checks to generated (PR #131255)

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https://github.com/arsenm ready_for_review 
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[llvm-branch-commits] [llvm] AMDGPU: Switch a test with only function label checks to generated (PR #131255)

[via llvm-branch-commits]

llvmbot wrote:



@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes

I suspect the first function at least is not usefully testing
the original failure.

---
Full diff: https://github.com/llvm/llvm-project/pull/131255.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll (+32-5) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index 19c43fa22271b..a0ac6c1b28449 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -1,8 +1,13 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck 
-check-prefixes=GCN,GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -o - %s | FileCheck 
-check-prefixes=GCN,GFX8 %s
 
-; GCN-LABEL:{{^}}row_filter_C1_D0:
 define amdgpu_kernel void @row_filter_C1_D0() #0 {
+; GCN-LABEL: row_filter_C1_D0:
+; GCN:   ; %bb.0: ; %entry
+; GCN-NEXT:s_cbranch_scc1 .LBB0_2
+; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
+; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
   br i1 undef, label %for.inc.1, label %do.body.preheader
 
@@ -40,9 +45,28 @@ for.inc.1:; preds = 
%do.body.1562.prehea
   unreachable
 }
 
-; GCN-LABEL: {{^}}foo:
-; GCN: s_endpgm
 define amdgpu_ps void @foo() #0 {
+; GCN-LABEL: foo:
+; GCN:   ; %bb.0: ; %bb
+; GCN-NEXT:s_mov_b64 s[0:1], -1
+; GCN-NEXT:s_cbranch_scc0 .LBB1_2
+; GCN-NEXT:  ; %bb.1: ; %bb24
+; GCN-NEXT:s_mov_b64 s[0:1], 0
+; GCN-NEXT:  .LBB1_2: ; %Flow1
+; GCN-NEXT:s_and_b64 vcc, exec, s[0:1]
+; GCN-NEXT:s_cbranch_vccz .LBB1_4
+; GCN-NEXT:  ; %bb.3: ; %bb9
+; GCN-NEXT:image_sample v[0:1], v0, s[0:7], s[0:3] dmask:0xa
+; GCN-NEXT:s_branch .LBB1_5
+; GCN-NEXT:  .LBB1_4:
+; GCN-NEXT:v_mov_b32_e32 v1, 0
+; GCN-NEXT:v_mov_b32_e32 v0, v1
+; GCN-NEXT:  .LBB1_5: ; %bb14
+; GCN-NEXT:s_waitcnt vmcnt(0)
+; GCN-NEXT:v_mul_f32_e32 v0, 0x4128, v0
+; GCN-NEXT:v_mul_f32_e32 v1, 0x4138, v1
+; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
+; GCN-NEXT:s_endpgm
 bb:
   br i1 undef, label %bb2, label %bb1
 
@@ -101,3 +125,6 @@ declare <4 x float> 
@llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add 
tests below this line:
+; GFX6: {{.*}}
+; GFX8: {{.*}}

``




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[llvm-branch-commits] [llvm] AMDGPU: Switch a test to generated checks which only tested labels (PR #131257)

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[llvm-branch-commits] [llvm] AMDGPU: Remove undef in subreg-coalescer-crash.ll (PR #131256)

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[llvm-branch-commits] [llvm] AMDGPU: Add generated checks to compile only test (PR #131258)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm ready_for_review 
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[llvm-branch-commits] [llvm] AMDGPU: Remove undef in subreg-coalescer-crash.ll (PR #131256)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/131256.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll (+19-13) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index a0ac6c1b28449..a69ee2e1a8b5c 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -9,17 +9,19 @@ define amdgpu_kernel void @row_filter_C1_D0() #0 {
 ; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
 ; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
-  br i1 undef, label %for.inc.1, label %do.body.preheader
+  br i1 poison, label %for.inc.1, label %do.body.preheader
 
 do.body.preheader:; preds = %entry
   %tmp = insertelement <4 x i32> zeroinitializer, i32 poison, i32 1
-  br i1 undef, label %do.body56.1, label %do.body90
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %do.body56.1, label %do.body90
 
 do.body90:; preds = %do.body56.2, 
%do.body56.1, %do.body.preheader
   %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ 
%tmp, %do.body.preheader ]
   %tmp2 = insertelement <4 x i32> %tmp1, i32 poison, i32 2
   %tmp3 = insertelement <4 x i32> %tmp2, i32 poison, i32 3
-  br i1 undef, label %do.body124.1, label %do.body.1562.preheader
+  %undef3 = freeze i1 poison
+  br i1 %undef3, label %do.body124.1, label %do.body.1562.preheader
 
 do.body.1562.preheader:   ; preds = %do.body124.1, 
%do.body90
   %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
@@ -28,7 +30,7 @@ do.body.1562.preheader:   ; preds = 
%do.body124.1, %do.b
 
 do.body56.1:  ; preds = %do.body.preheader
   %tmp5 = insertelement <4 x i32> %tmp, i32 poison, i32 1
-  %or.cond472.1 = or i1 undef, undef
+  %or.cond472.1 = or i1 poison, poison
   br i1 %or.cond472.1, label %do.body56.2, label %do.body90
 
 do.body56.2:  ; preds = %do.body56.1
@@ -41,7 +43,8 @@ do.body124.1: ; preds = 
%do.body90
 
 for.inc.1:; preds = 
%do.body.1562.preheader, %entry
   %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, 
%do.body.1562.preheader ]
-  %add.i495 = add <4 x i32> %storemerge591, undef
+  %undef2 = freeze <4 x i32> poison
+  %add.i495 = add <4 x i32> %storemerge591, %undef2
   unreachable
 }
 
@@ -68,24 +71,27 @@ define amdgpu_ps void @foo() #0 {
 ; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
 ; GCN-NEXT:s_endpgm
 bb:
-  br i1 undef, label %bb2, label %bb1
+  %undef0 = freeze i1 poison
+  br i1 %undef0, label %bb2, label %bb1
 
 bb1:  ; preds = %bb
-  br i1 undef, label %bb4, label %bb6
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %bb4, label %bb6
 
 bb2:  ; preds = %bb4, %bb
   %tmp = phi float [ %tmp5, %bb4 ], [ 0.00e+00, %bb ]
-  br i1 undef, label %bb9, label %bb13
+  br i1 poison, label %bb9, label %bb13
 
 bb4:  ; preds = %bb7, %bb6, %bb1
   %tmp5 = phi float [ poison, %bb1 ], [ poison, %bb6 ], [ %tmp8, %bb7 ]
   br label %bb2
 
 bb6:  ; preds = %bb1
-  br i1 undef, label %bb7, label %bb4
+  %undef2 = freeze i1 poison
+  br i1 %undef2, label %bb7, label %bb4
 
 bb7:  ; preds = %bb6
-  %tmp8 = fmul float undef, undef
+  %tmp8 = fmul float poison, poison
   br label %bb4
 
 bb9:  ; preds = %bb2
@@ -95,7 +101,7 @@ bb9:  ; preds = 
%bb2
   br label %bb14
 
 bb13: ; preds = %bb2
-  br i1 undef, label %bb23, label %bb24
+  br i1 poison, label %bb23, label %bb24
 
 bb14: ; preds = %bb27, %bb24, %bb9
   %tmp15 = phi float [ %tmp12, %bb9 ], [ poison, %bb27 ], [ 0.00e+00, 
%bb24 ]
@@ -106,11 +112,11 @@ bb14: ; preds 
= %bb27, %bb24, %bb9
   ret void
 
 bb23: ; preds = %bb13
-  br i1 undef, label %bb24, label %bb26
+  br i1 poison, label %bb24, label %bb26
 
 bb24: ; preds = %bb26, %bb23, %bb13
   %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.00e+00, %bb23 ]
-  br i1 undef, label %bb27, label %bb14
+  br i1 poison, label %bb27, label %bb14
 
 bb26: ; preds = %bb23
   br label %bb24

``




https://github.com/llvm/llvm-project/pull/131256
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[llvm-branch-commits] [llvm] AMDGPU: Add generated checks to compile only test (PR #131258)

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[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-llvm-globalisel

Author: Matt Arsenault (arsenm)


Changes

This wasn't checking anything. Also remove undef uses.

---
Full diff: https://github.com/llvm/llvm-project/pull/131259.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll (+64-4) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll 
b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
index 51072c36dadd2..a3b3831f5b954 100644
--- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -o /dev/null < %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global 
-verify-machineinstrs -o /dev/null < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
 ; The register coalescer introduces a verifier error which later
 ; results in a crash during scheduling.
@@ -7,13 +8,72 @@
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) 
nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %c0) #1 {
+; GFX6-LABEL: reg_coalescer_breaks_dead:
+; GFX6:   ; %bb.0: ; %bb
+; GFX6-NEXT:v_mov_b32_e32 v1, 0
+; GFX6-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX6-NEXT:v_mov_b32_e32 v2, 0
+; GFX6-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX6-NEXT:s_cbranch_execz .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %bb3
+; GFX6-NEXT:s_load_dword s2, s[4:5], 0xb
+; GFX6-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x9
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX6-NEXT:s_add_u32 s2, s6, s2
+; GFX6-NEXT:s_addc_u32 s3, s7, s3
+; GFX6-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:v_mov_b32_e32 v1, s2
+; GFX6-NEXT:v_mov_b32_e32 v2, s3
+; GFX6-NEXT:  .LBB0_2: ; %bb4
+; GFX6-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:s_load_dword s0, s[4:5], 0xe
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_bitcmp0_b32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %bb15
+; GFX6-NEXT:s_mov_b32 m0, -1
+; GFX6-NEXT:ds_write_b64 v0, v[1:2]
+; GFX6-NEXT:  .LBB0_4: ; %bb16
+;
+; GFX8-LABEL: reg_coalescer_breaks_dead:
+; GFX8:   ; %bb.0: ; %bb
+; GFX8-NEXT:v_mov_b32_e32 v1, 0
+; GFX8-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT:v_mov_b32_e32 v2, 0
+; GFX8-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:s_cbranch_execz .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %bb3
+; GFX8-NEXT:s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_ashr_i32 s3, s2, 31
+; GFX8-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX8-NEXT:s_add_u32 s2, s6, s2
+; GFX8-NEXT:s_addc_u32 s3, s7, s3
+; GFX8-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:v_mov_b32_e32 v1, s2
+; GFX8-NEXT:v_mov_b32_e32 v2, s3
+; GFX8-NEXT:  .LBB0_2: ; %bb4
+; GFX8-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:s_load_dword s0, s[4:5], 0x38
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_bitcmp0_b32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %bb15
+; GFX8-NEXT:s_mov_b32 m0, -1
+; GFX8-NEXT:ds_write_b64 v0, v[1:2]
+; GFX8-NEXT:  .LBB0_4: ; %bb16
 bb:
   %id.x = call i32 @llvm.amdgcn.workitem.id.x()
   %cmp0 = icmp eq i32 %id.x, 0
   br i1 %cmp0, label %bb3, label %bb4
 
 bb3:  ; preds = %bb
-  %tmp = ashr exact i32 undef, 8
+  %tmp = ashr exact i32 poison, 8
   br label %bb6
 
 bb4:  ; preds = %bb6, %bb
@@ -28,7 +88,7 @@ bb6:  ; preds = 
%bb6, %bb3
   %tmp11 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i64 %tmp10
   %tmp12 = load <2 x i32>, ptr addrspace(1) %tmp11, align 8
   %tmp13 = add <2 x i32> %tmp12, %tmp7
-  %tmp14 = icmp slt i32 undef, %arg2
+  %tmp14 = icmp slt i32 poison, %arg2
   br i1 %tmp14, label %bb6, label %bb4
 
 bb15: ; preds = %bb4

``




https://github.com/llvm/llvm-project/pull/131259
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[llvm-branch-commits] [llvm] [llvm][AsmPrinter] Emit call graph section (PR #87576)

[via llvm-branch-commits]

https://github.com/Prabhuk updated 
https://github.com/llvm/llvm-project/pull/87576

>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran 
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.

Created using spr 1.3.6-beta.1
---
 llvm/test/CodeGen/X86/call-graph-section.ll | 66 +++
 llvm/test/CodeGen/call-graph-section.ll | 73 -
 2 files changed, 66 insertions(+), 73 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/call-graph-section.ll
 delete mode 100644 llvm/test/CodeGen/call-graph-section.ll

diff --git a/llvm/test/CodeGen/X86/call-graph-section.ll 
b/llvm/test/CodeGen/X86/call-graph-section.ll
new file mode 100644
index 0..a77a2b8051ed3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-graph-section.ll
@@ -0,0 +1,66 @@
+;; Tests that we store the type identifiers in .callgraph section of the 
binary.
+
+; RUN: llc --call-graph-section -filetype=obj -o - < %s | \
+; RUN: llvm-readelf -x .callgraph - | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local void @foo() #0 !type !4 {
+entry:
+  ret void
+}
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local i32 @bar(i8 signext %a) #0 !type !5 {
+entry:
+  %a.addr = alloca i8, align 1
+  store i8 %a, ptr %a.addr, align 1
+  ret i32 0
+}
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local ptr @baz(ptr %a) #0 !type !6 {
+entry:
+  %a.addr = alloca ptr, align 8
+  store ptr %a, ptr %a.addr, align 8
+  ret ptr null
+}
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local void @main() #0 !type !7 {
+entry:
+  %retval = alloca i32, align 4
+  %fp_foo = alloca ptr, align 8
+  %a = alloca i8, align 1
+  %fp_bar = alloca ptr, align 8
+  %fp_baz = alloca ptr, align 8
+  store i32 0, ptr %retval, align 4
+  store ptr @foo, ptr %fp_foo, align 8
+  %0 = load ptr, ptr %fp_foo, align 8
+  call void (...) %0() [ "callee_type"(metadata !"_ZTSFvE.generalized") ]
+  store ptr @bar, ptr %fp_bar, align 8
+  %1 = load ptr, ptr %fp_bar, align 8
+  %2 = load i8, ptr %a, align 1
+  %call = call i32 %1(i8 signext %2) [ "callee_type"(metadata 
!"_ZTSFicE.generalized") ]
+  store ptr @baz, ptr %fp_baz, align 8
+  %3 = load ptr, ptr %fp_baz, align 8
+  %call1 = call ptr %3(ptr %a) [ "callee_type"(metadata 
!"_ZTSFPvS_E.generalized") ]
+  call void @foo() [ "callee_type"(metadata !"_ZTSFvE.generalized") ]
+  %4 = load i8, ptr %a, align 1
+  %call2 = call i32 @bar(i8 signext %4) [ "callee_type"(metadata 
!"_ZTSFicE.generalized") ]
+  %call3 = call ptr @baz(ptr %a) [ "callee_type"(metadata 
!"_ZTSFPvS_E.generalized") ]
+  ret void
+}
+
+;; Check that the numeric type id (md5 hash) for the below type ids are emitted
+;; to the callgraph section.
+
+; CHECK: Hex dump of section '.callgraph':
+
+; CHECK-DAG: 2444f731 f5eecb3e
+!4 = !{i64 0, !"_ZTSFvE.generalized"}
+; CHECK-DAG: 5486bc59 814b8e30
+!5 = !{i64 0, !"_ZTSFicE.generalized"}
+; CHECK-DAG: 7ade6814 f897fd77
+!6 = !{i64 0, !"_ZTSFPvS_E.generalized"}
+; CHECK-DAG: caaf769a 600968fa
+!7 = !{i64 0, !"_ZTSFiE.generalized"}
diff --git a/llvm/test/CodeGen/call-graph-section.ll 
b/llvm/test/CodeGen/call-graph-section.ll
deleted file mode 100644
index bb158d11e82c9..0
--- a/llvm/test/CodeGen/call-graph-section.ll
+++ /dev/null
@@ -1,73 +0,0 @@
-; Tests that we store the type identifiers in .callgraph section of the binary.
-
-; RUN: llc --call-graph-section -filetype=obj -o - < %s | \
-; RUN: llvm-readelf -x .callgraph - | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
-
-define dso_local void @foo() #0 !type !4 {
-entry:
-  ret void
-}
-
-define dso_local i32 @bar(i8 signext %a) #0 !type !5 {
-entry:
-  %a.addr = alloca i8, align 1
-  store i8 %a, i8* %a.addr, align 1
-  ret i32 0
-}
-
-define dso_local i32* @baz(i8* %a) #0 !type !6 {
-entry:
-  %a.addr = alloca i8*, align 8
-  store i8* %a, i8** %a.addr, align 8
-  ret i32* null
-}
-
-define dso_local i32 @main() #0 !type !7 {
-entry:
-  %retval = alloca i32, align 4
-  %fp_foo = alloca void (...)*, align 8
-  %a = alloca i8, align 1
-  %fp_bar = alloca i32 (i8)*, align 8
-  %fp_baz = alloca i32* (i8*)*, align 8
-  store i32 0, i32* %retval, align 4
-  store void (...)* bitcast (void ()* @foo to void (...)*), void (...)** 
%fp_foo, align 8
-  %0 = load void (...)*, void (...)** %fp_foo, align 8
-  call void (...) %0() [ "callee_type"(metadata !"_ZTSFvE.generalized") ]
-  store i32 (i8)* @bar, i32 (i8)** %fp_bar, align 8
-  %1 = load i32 (i8)*, i32 (i8)** %fp_bar, align 8
-  %2 = load i8, i8* %a, align 1
-  %call = call i32 %1(i8 signext %2) [ "callee_type"(metadata 
!"_ZTSFicE.generalized") ]
-  store i32* (i8*)* @baz, i32* (i8*)** %fp_baz, align 8
-  %3 = load i32* (i8*)*, i32* (i8*)** %fp_baz, align 8
-  %call1 = call i32* %3(i8* %a) [ "callee_type"(metadata 
!"_ZTSFPvS_E.generalized") ]
-  call void @foo() [ "callee_type"(meta

[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-hexagon

Author: None (llvmbot)


Changes

Backport d642eec78fc94ef3c5266dc0b10b8c51ea046e7a

Requested by: @androm3da

---
Full diff: https://github.com/llvm/llvm-project/pull/131270.diff


2 Files Affected:

- (modified) llvm/lib/Target/Hexagon/HexagonPatterns.td (+24-14) 
- (added) llvm/test/CodeGen/Hexagon/fcmp-nan.ll (+189) 


``diff
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td 
b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index cba5ff1ab0d9b..244f204539c89 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -721,11 +721,6 @@ def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F32>;
-def: OpR_RR_pat, i1, F32>;
 def: OpR_RR_pat,  i1, F32>;
 def: OpR_RR_pat,  i1, F32>;
 def: OpR_RR_pat;
@@ -733,11 +728,6 @@ def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F64>;
-def: OpR_RR_pat, i1, F64>;
 def: OpR_RR_pat,  i1, F64>;
 def: OpR_RR_pat,  i1, F64>;
 def: OpR_RR_pat;
@@ -900,15 +890,35 @@ def: OpmR_RR_pat,  RevCmp, i1, 
F64>;
 def: OpmR_RR_pat,  RevCmp, i1, F64>;
 def: OpmR_RR_pat, setune, i1, F64>;
 
-def: OpmR_RR_pat, setone, i1, F32>;
-def: OpmR_RR_pat, setne,  i1, F32>;
+class T4
+  : OutPatFrag<(ops node:$Rs, node:$Rt),
+   (MI1 (MI2 (MI3 $Rs, $Rt), (MI4 $Rs, $Rt)))>;
 
-def: OpmR_RR_pat, setone, i1, F64>;
-def: OpmR_RR_pat, setne,  i1, F64>;
+class Cmpof: T3;
+class Cmpod: T3;
+
+class Cmpofn: T4;
+class Cmpodn: T4;
+
+def: OpmR_RR_pat,  setoeq, i1, F32>;
+def: OpmR_RR_pat,  setoge, i1, F32>;
+def: OpmR_RR_pat,  setogt, i1, F32>;
+def: OpmR_RR_pat,  RevCmp, i1, F32>;
+def: OpmR_RR_pat,  RevCmp, i1, F32>;
+def: OpmR_RR_pat, setone, i1, F32>;
+
+def: OpmR_RR_pat,  setoeq, i1, F64>;
+def: OpmR_RR_pat,  setoge, i1, F64>;
+def: OpmR_RR_pat,  setogt, i1, F64>;
+def: OpmR_RR_pat,  RevCmp, i1, F64>;
+def: OpmR_RR_pat,  RevCmp, i1, F64>;
+def: OpmR_RR_pat, setone, i1, F64>;
 
 def: OpmR_RR_pat, seto,   i1, F32>;
 def: OpmR_RR_pat, seto,   i1, F64>;
 
+def: OpmR_RR_pat, setne,  i1, F32>;
+def: OpmR_RR_pat, setne,  i1, F64>;
 
 // --(6) Select --
 //
diff --git a/llvm/test/CodeGen/Hexagon/fcmp-nan.ll 
b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
new file mode 100644
index 0..1469402911601
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
@@ -0,0 +1,189 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Test that all FP ordered compare instructions generate the correct
+; post-processing to accommodate NaNs.
+;
+; Specifically for ordered FP compares, we have to check if one of
+; the operands was a NaN to comform to the semantics of the ordered
+; fcmp bitcode instruction
+;
+target triple = "hexagon"
+
+;
+; Functions for float:
+;
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_oeq_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp oeq float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = or([[REG0]],[[REG1]])
+; CHECK: r0 = mux([[REG2]],#0,#1)
+;
+define i32 @compare_one_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp one float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_ogt_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp ogt float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r1,r0)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r1,r0)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_ole_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp ole float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_oge_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp oge float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r1,r0)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp

[llvm-branch-commits] [llvm] AMDGPU: Switch a test with only function label checks to generated (PR #131255)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131255

>From 9eeb3a6aa1ff43ea4b60320ffb532db1b1a772b3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:27:08 +0700
Subject: [PATCH] AMDGPU: Switch a test with only function label checks to
 generated

I suspect the first function at least is not usefully testing
the original failure.
---
 .../CodeGen/AMDGPU/subreg-coalescer-crash.ll  | 37 ---
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index 19c43fa22271b..a0ac6c1b28449 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -1,8 +1,13 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck 
-check-prefixes=GCN,GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -o - %s | FileCheck 
-check-prefixes=GCN,GFX8 %s
 
-; GCN-LABEL:{{^}}row_filter_C1_D0:
 define amdgpu_kernel void @row_filter_C1_D0() #0 {
+; GCN-LABEL: row_filter_C1_D0:
+; GCN:   ; %bb.0: ; %entry
+; GCN-NEXT:s_cbranch_scc1 .LBB0_2
+; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
+; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
   br i1 undef, label %for.inc.1, label %do.body.preheader
 
@@ -40,9 +45,28 @@ for.inc.1:; preds = 
%do.body.1562.prehea
   unreachable
 }
 
-; GCN-LABEL: {{^}}foo:
-; GCN: s_endpgm
 define amdgpu_ps void @foo() #0 {
+; GCN-LABEL: foo:
+; GCN:   ; %bb.0: ; %bb
+; GCN-NEXT:s_mov_b64 s[0:1], -1
+; GCN-NEXT:s_cbranch_scc0 .LBB1_2
+; GCN-NEXT:  ; %bb.1: ; %bb24
+; GCN-NEXT:s_mov_b64 s[0:1], 0
+; GCN-NEXT:  .LBB1_2: ; %Flow1
+; GCN-NEXT:s_and_b64 vcc, exec, s[0:1]
+; GCN-NEXT:s_cbranch_vccz .LBB1_4
+; GCN-NEXT:  ; %bb.3: ; %bb9
+; GCN-NEXT:image_sample v[0:1], v0, s[0:7], s[0:3] dmask:0xa
+; GCN-NEXT:s_branch .LBB1_5
+; GCN-NEXT:  .LBB1_4:
+; GCN-NEXT:v_mov_b32_e32 v1, 0
+; GCN-NEXT:v_mov_b32_e32 v0, v1
+; GCN-NEXT:  .LBB1_5: ; %bb14
+; GCN-NEXT:s_waitcnt vmcnt(0)
+; GCN-NEXT:v_mul_f32_e32 v0, 0x4128, v0
+; GCN-NEXT:v_mul_f32_e32 v1, 0x4138, v1
+; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
+; GCN-NEXT:s_endpgm
 bb:
   br i1 undef, label %bb2, label %bb1
 
@@ -101,3 +125,6 @@ declare <4 x float> 
@llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add 
tests below this line:
+; GFX6: {{.*}}
+; GFX8: {{.*}}

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[llvm-branch-commits] [llvm] AMDGPU: Switch a test with only function label checks to generated (PR #131255)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/131255

I suspect the first function at least is not usefully testing
the original failure.

>From a0b3a1c68d44fc0aaf680503001eae57137979da Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:27:08 +0700
Subject: [PATCH] AMDGPU: Switch a test with only function label checks to
 generated

I suspect the first function at least is not usefully testing
the original failure.
---
 .../CodeGen/AMDGPU/subreg-coalescer-crash.ll  | 37 ---
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index 19c43fa22271b..a0ac6c1b28449 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -1,8 +1,13 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck 
-check-prefixes=GCN,GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -o - %s | FileCheck 
-check-prefixes=GCN,GFX8 %s
 
-; GCN-LABEL:{{^}}row_filter_C1_D0:
 define amdgpu_kernel void @row_filter_C1_D0() #0 {
+; GCN-LABEL: row_filter_C1_D0:
+; GCN:   ; %bb.0: ; %entry
+; GCN-NEXT:s_cbranch_scc1 .LBB0_2
+; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
+; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
   br i1 undef, label %for.inc.1, label %do.body.preheader
 
@@ -40,9 +45,28 @@ for.inc.1:; preds = 
%do.body.1562.prehea
   unreachable
 }
 
-; GCN-LABEL: {{^}}foo:
-; GCN: s_endpgm
 define amdgpu_ps void @foo() #0 {
+; GCN-LABEL: foo:
+; GCN:   ; %bb.0: ; %bb
+; GCN-NEXT:s_mov_b64 s[0:1], -1
+; GCN-NEXT:s_cbranch_scc0 .LBB1_2
+; GCN-NEXT:  ; %bb.1: ; %bb24
+; GCN-NEXT:s_mov_b64 s[0:1], 0
+; GCN-NEXT:  .LBB1_2: ; %Flow1
+; GCN-NEXT:s_and_b64 vcc, exec, s[0:1]
+; GCN-NEXT:s_cbranch_vccz .LBB1_4
+; GCN-NEXT:  ; %bb.3: ; %bb9
+; GCN-NEXT:image_sample v[0:1], v0, s[0:7], s[0:3] dmask:0xa
+; GCN-NEXT:s_branch .LBB1_5
+; GCN-NEXT:  .LBB1_4:
+; GCN-NEXT:v_mov_b32_e32 v1, 0
+; GCN-NEXT:v_mov_b32_e32 v0, v1
+; GCN-NEXT:  .LBB1_5: ; %bb14
+; GCN-NEXT:s_waitcnt vmcnt(0)
+; GCN-NEXT:v_mul_f32_e32 v0, 0x4128, v0
+; GCN-NEXT:v_mul_f32_e32 v1, 0x4138, v1
+; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
+; GCN-NEXT:s_endpgm
 bb:
   br i1 undef, label %bb2, label %bb1
 
@@ -101,3 +125,6 @@ declare <4 x float> 
@llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add 
tests below this line:
+; GFX6: {{.*}}
+; GFX8: {{.*}}

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[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes

This wasn't checking anything. Also remove undef uses.

---
Full diff: https://github.com/llvm/llvm-project/pull/131259.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll (+64-4) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll 
b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
index 51072c36dadd2..a3b3831f5b954 100644
--- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -o /dev/null < %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global 
-verify-machineinstrs -o /dev/null < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
 ; The register coalescer introduces a verifier error which later
 ; results in a crash during scheduling.
@@ -7,13 +8,72 @@
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) 
nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %c0) #1 {
+; GFX6-LABEL: reg_coalescer_breaks_dead:
+; GFX6:   ; %bb.0: ; %bb
+; GFX6-NEXT:v_mov_b32_e32 v1, 0
+; GFX6-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX6-NEXT:v_mov_b32_e32 v2, 0
+; GFX6-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX6-NEXT:s_cbranch_execz .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %bb3
+; GFX6-NEXT:s_load_dword s2, s[4:5], 0xb
+; GFX6-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x9
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX6-NEXT:s_add_u32 s2, s6, s2
+; GFX6-NEXT:s_addc_u32 s3, s7, s3
+; GFX6-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:v_mov_b32_e32 v1, s2
+; GFX6-NEXT:v_mov_b32_e32 v2, s3
+; GFX6-NEXT:  .LBB0_2: ; %bb4
+; GFX6-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:s_load_dword s0, s[4:5], 0xe
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_bitcmp0_b32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %bb15
+; GFX6-NEXT:s_mov_b32 m0, -1
+; GFX6-NEXT:ds_write_b64 v0, v[1:2]
+; GFX6-NEXT:  .LBB0_4: ; %bb16
+;
+; GFX8-LABEL: reg_coalescer_breaks_dead:
+; GFX8:   ; %bb.0: ; %bb
+; GFX8-NEXT:v_mov_b32_e32 v1, 0
+; GFX8-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT:v_mov_b32_e32 v2, 0
+; GFX8-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:s_cbranch_execz .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %bb3
+; GFX8-NEXT:s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_ashr_i32 s3, s2, 31
+; GFX8-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX8-NEXT:s_add_u32 s2, s6, s2
+; GFX8-NEXT:s_addc_u32 s3, s7, s3
+; GFX8-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:v_mov_b32_e32 v1, s2
+; GFX8-NEXT:v_mov_b32_e32 v2, s3
+; GFX8-NEXT:  .LBB0_2: ; %bb4
+; GFX8-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:s_load_dword s0, s[4:5], 0x38
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_bitcmp0_b32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %bb15
+; GFX8-NEXT:s_mov_b32 m0, -1
+; GFX8-NEXT:ds_write_b64 v0, v[1:2]
+; GFX8-NEXT:  .LBB0_4: ; %bb16
 bb:
   %id.x = call i32 @llvm.amdgcn.workitem.id.x()
   %cmp0 = icmp eq i32 %id.x, 0
   br i1 %cmp0, label %bb3, label %bb4
 
 bb3:  ; preds = %bb
-  %tmp = ashr exact i32 undef, 8
+  %tmp = ashr exact i32 poison, 8
   br label %bb6
 
 bb4:  ; preds = %bb6, %bb
@@ -28,7 +88,7 @@ bb6:  ; preds = 
%bb6, %bb3
   %tmp11 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i64 %tmp10
   %tmp12 = load <2 x i32>, ptr addrspace(1) %tmp11, align 8
   %tmp13 = add <2 x i32> %tmp12, %tmp7
-  %tmp14 = icmp slt i32 undef, %arg2
+  %tmp14 = icmp slt i32 poison, %arg2
   br i1 %tmp14, label %bb6, label %bb4
 
 bb15: ; preds = %bb4

``




https://github.com/llvm/llvm-project/pull/131259
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[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/131259?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
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[llvm-branch-commits] [llvm] AMDGPU: Replace undef references with poison in some MIR tests (PR #131254)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/131254

None

>From a9ed4e3b97281d17174077e1e5be012ab70b6b57 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:20:37 +0700
Subject: [PATCH] AMDGPU: Replace undef references with poison in some MIR
 tests

---
 .../CodeGen/AMDGPU/invert-br-undef-vcc.mir|   2 +-
 llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir  |  18 +-
 .../memory-legalizer-invalid-addrspace.mir|   2 +-
 .../CodeGen/AMDGPU/memory-legalizer-local.mir |  40 ++--
 .../AMDGPU/memory-legalizer-region.mir|  40 ++--
 .../CodeGen/AMDGPU/merge-flat-load-store.mir  | 210 +-
 .../merge-flat-with-global-load-store.mir |  62 +++---
 .../CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir  |   6 +-
 .../AMDGPU/optimize-if-exec-masking.mir   |  22 +-
 .../AMDGPU/scalar-store-cache-flush.mir   |   4 +-
 .../CodeGen/AMDGPU/sched-crash-dbg-value.mir  |  16 +-
 11 files changed, 211 insertions(+), 211 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir 
b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
index c9c99a9953fcd..10c46e39c3664 100644
--- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
@@ -3,7 +3,7 @@
 
   define amdgpu_kernel void @invert_br_undef_vcc(float %cond, ptr addrspace(1) 
%out) #0 {
   entry:
-br i1 undef, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
+br i1 poison, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
 
   else: ; preds = %entry
 store volatile i32 100, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir 
b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
index 195597c480319..cab45900b996e 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
@@ -10,7 +10,7 @@ name: buffer_load_dword_lds_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3) undef` + 4)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3)` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -27,7 +27,7 @@ name: buffer_load_dword_lds_vmcnt_1
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3)`)
 $vgpr10 = BUFFER_LOAD_DWORD_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 
$sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr 
addrspace(1) poison`)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
@@ -44,8 +44,8 @@ name: buffer_load_dword_lds_flat_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
-$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3)`)
+$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr poison`)
 
 S_ENDPGM 0
 
@@ -61,7 +61,7 @@ name: global_load_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3) undef` + 4)
+GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3)` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -91,7 +91,7 @@ name: buffer_store_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_STORE_LDS_DWORD $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implici

[llvm-branch-commits] [llvm] AMDGPU: Replace undef references with poison in some MIR tests (PR #131254)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/131254?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#131259** https://app.graphite.dev/github/pr/llvm/llvm-project/131259?utm_source=stack-comment-icon";
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* **#131257** https://app.graphite.dev/github/pr/llvm/llvm-project/131257?utm_source=stack-comment-icon";
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* **#131255** https://app.graphite.dev/github/pr/llvm/llvm-project/131255?utm_source=stack-comment-icon";
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* **#131254** https://app.graphite.dev/github/pr/llvm/llvm-project/131254?utm_source=stack-comment-icon";
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* **#131110** https://app.graphite.dev/github/pr/llvm/llvm-project/131110?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131103** https://app.graphite.dev/github/pr/llvm/llvm-project/131103?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131102** https://app.graphite.dev/github/pr/llvm/llvm-project/131102?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131101** https://app.graphite.dev/github/pr/llvm/llvm-project/131101?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131095** https://app.graphite.dev/github/pr/llvm/llvm-project/131095?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131092** https://app.graphite.dev/github/pr/llvm/llvm-project/131092?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>: 1 other dependent PR 
([#131106](https://github.com/llvm/llvm-project/pull/131106) https://app.graphite.dev/github/pr/llvm/llvm-project/131106?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>)
* **#131090** https://app.graphite.dev/github/pr/llvm/llvm-project/131090?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131084** https://app.graphite.dev/github/pr/llvm/llvm-project/131084?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131083** https://app.graphite.dev/github/pr/llvm/llvm-project/131083?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/131254
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test undef uses with poison (PR #131103)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

### Merge activity

* **Mar 13, 10:46 PM EDT**: A user started a stack merge that includes this 
pull request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131103).


https://github.com/llvm/llvm-project/pull/131103
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[llvm-branch-commits] [llvm] AMDGPU: Add generated checks to compile only test (PR #131258)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131258

>From 810371b2bc4945b5818308abfe0703eb59343481 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 09:00:37 +0700
Subject: [PATCH] AMDGPU: Add generated checks to compile only test

Also replace an undef use
---
 llvm/test/CodeGen/AMDGPU/swdev282079.ll | 28 +++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.ll 
b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
index 184eb4f6f0baa..20eb6ff560979 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
@@ -1,11 +1,35 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
 
 define protected amdgpu_kernel void @foo(ptr addrspace(1) %arg, ptr 
addrspace(1) %arg1) {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %bb
+; CHECK-NEXT:s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:s_add_u32 s0, s0, s17
+; CHECK-NEXT:s_addc_u32 s1, s1, 0
+; CHECK-NEXT:s_add_u32 s8, s8, 16
+; CHECK-NEXT:s_addc_u32 s9, s9, 0
+; CHECK-NEXT:s_mov_b32 s13, s15
+; CHECK-NEXT:s_mov_b32 s12, s14
+; CHECK-NEXT:s_getpc_b64 s[18:19]
+; CHECK-NEXT:s_add_u32 s18, s18, eggs@rel32@lo+4
+; CHECK-NEXT:s_addc_u32 s19, s19, eggs@rel32@hi+12
+; CHECK-NEXT:s_mov_b32 s14, s16
+; CHECK-NEXT:v_mov_b32_e32 v31, v0
+; CHECK-NEXT:v_mov_b32_e32 v1, 0
+; CHECK-NEXT:s_mov_b32 s32, 0
+; CHECK-NEXT:s_swappc_b64 s[30:31], s[18:19]
+; CHECK-NEXT:buffer_load_dword v2, off, s[0:3], 0
+; CHECK-NEXT:buffer_load_dword v3, off, s[0:3], 0 offset:4
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:flat_store_dwordx2 v[2:3], v[0:1]
+; CHECK-NEXT:s_endpgm
 bb:
   %tmp = addrspacecast ptr addrspace(5) null to ptr
   %tmp2 = call i64 @eggs(ptr poison) #1
   %tmp3 = load ptr, ptr %tmp, align 8
-  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 undef
+  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 0
   store i64 %tmp2, ptr %tmp4, align 8
   ret void
 }

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[llvm-branch-commits] [clang] [clang] Introduce CallGraphSection option (PR #117037)

[via llvm-branch-commits]

https://github.com/Prabhuk updated 
https://github.com/llvm/llvm-project/pull/117037

>From 6a12be2c5b60a95a06875b0b2c4f14228d1fa882 Mon Sep 17 00:00:00 2001
From: prabhukr 
Date: Wed, 12 Mar 2025 23:30:01 +
Subject: [PATCH] Fix EOF newlines.

Created using spr 1.3.6-beta.1
---
 clang/test/Driver/call-graph-section.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/Driver/call-graph-section.c 
b/clang/test/Driver/call-graph-section.c
index 108446729d857..5832aa6754137 100644
--- a/clang/test/Driver/call-graph-section.c
+++ b/clang/test/Driver/call-graph-section.c
@@ -2,4 +2,4 @@
 // RUN: %clang -### -S -fcall-graph-section -fno-call-graph-section %s 2>&1 | 
FileCheck --check-prefix=NO-CALL-GRAPH-SECTION %s
 
 // CALL-GRAPH-SECTION: "-fcall-graph-section"
-// NO-CALL-GRAPH-SECTION-NOT: "-fcall-graph-section"
\ No newline at end of file
+// NO-CALL-GRAPH-SECTION-NOT: "-fcall-graph-section"

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[llvm-branch-commits] [clang][CallGraphSection] Type id metadata for indirect calls (PR #117036)

[via llvm-branch-commits]

https://github.com/Prabhuk updated 
https://github.com/llvm/llvm-project/pull/117036


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[llvm-branch-commits] [llvm] [llvm] Extract and propagate indirect call type id (PR #87575)

[via llvm-branch-commits]

https://github.com/Prabhuk updated 
https://github.com/llvm/llvm-project/pull/87575

>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran 
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/4] Fixed the tests and addressed most of the review
 comments.

Created using spr 1.3.6-beta.1
---
 llvm/include/llvm/CodeGen/MachineFunction.h   | 15 +++--
 .../CodeGen/AArch64/call-site-info-typeid.ll  | 28 +++--
 .../test/CodeGen/ARM/call-site-info-typeid.ll | 28 +++--
 .../CodeGen/MIR/X86/call-site-info-typeid.ll  | 58 ---
 .../CodeGen/MIR/X86/call-site-info-typeid.mir | 13 ++---
 .../CodeGen/Mips/call-site-info-typeid.ll | 28 +++--
 .../test/CodeGen/X86/call-site-info-typeid.ll | 28 +++--
 7 files changed, 71 insertions(+), 127 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h 
b/llvm/include/llvm/CodeGen/MachineFunction.h
index bb0b87a3a04a3..44633df38a651 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -493,7 +493,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
 /// Callee type id.
 ConstantInt *TypeId = nullptr;
 
-CallSiteInfo() {}
+CallSiteInfo() = default;
 
 /// Extracts the numeric type id from the CallBase's type operand bundle,
 /// and sets TypeId. This is used as type id for the indirect call in the
@@ -503,12 +503,11 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   if (!CB.isIndirectCall())
 return;
 
-  auto Opt = CB.getOperandBundle(LLVMContext::OB_type);
-  if (!Opt.has_value()) {
-errs() << "warning: cannot find indirect call type operand bundle for  
"
-  "call graph section\n";
+  std::optional Opt =
+  CB.getOperandBundle(LLVMContext::OB_type);
+  // Return if the operand bundle for call graph section cannot be found.
+  if (!Opt.has_value())
 return;
-  }
 
   // Get generalized type id string
   auto OB = Opt.value();
@@ -520,9 +519,9 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
  "invalid type identifier");
 
   // Compute numeric type id from generalized type id string
-  uint64_t TypeIdVal = llvm::MD5Hash(TypeIdStr->getString());
+  uint64_t TypeIdVal = MD5Hash(TypeIdStr->getString());
   IntegerType *Int64Ty = Type::getInt64Ty(CB.getContext());
-  TypeId = llvm::ConstantInt::get(Int64Ty, TypeIdVal, /*IsSigned=*/false);
+  TypeId = ConstantInt::get(Int64Ty, TypeIdVal, /*IsSigned=*/false);
 }
   };
 
diff --git a/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll 
b/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
index f0a6b44755c5c..f3b98c2c7a395 100644
--- a/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
+++ b/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
@@ -1,14 +1,9 @@
-; Tests that call site type ids can be extracted and set from type operand
-; bundles.
+;; Tests that call site type ids can be extracted and set from type operand
+;; bundles.
 
-; Verify the exact typeId value to ensure it is not garbage but the value
-; computed as the type id from the type operand bundle.
-; RUN: llc --call-graph-section -mtriple aarch64-linux-gnu %s 
-stop-before=finalize-isel -o - | FileCheck %s
-
-; ModuleID = 'test.c'
-source_filename = "test.c"
-target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-unknown-linux-gnu"
+;; Verify the exact typeId value to ensure it is not garbage but the value
+;; computed as the type id from the type operand bundle.
+; RUN: llc --call-graph-section -mtriple aarch64-linux-gnu < %s 
-stop-before=finalize-isel -o - | FileCheck %s
 
 define dso_local void @foo(i8 signext %a) !type !3 {
 entry:
@@ -19,10 +14,10 @@ entry:
 define dso_local i32 @main() !type !4 {
 entry:
   %retval = alloca i32, align 4
-  %fp = alloca void (i8)*, align 8
-  store i32 0, i32* %retval, align 4
-  store void (i8)* @foo, void (i8)** %fp, align 8
-  %0 = load void (i8)*, void (i8)** %fp, align 8
+  %fp = alloca ptr, align 8
+  store i32 0, ptr %retval, align 4
+  store ptr @foo, ptr %fp, align 8
+  %0 = load ptr, ptr %fp, align 8
   ; CHECK: callSites:
   ; CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], typeId:
   ; CHECK-NEXT: 7854600665770582568 }
@@ -30,10 +25,5 @@ entry:
   ret i32 0
 }
 
-!llvm.module.flags = !{!0, !1, !2}
-
-!0 = !{i32 1, !"wchar_size", i32 4}
-!1 = !{i32 7, !"uwtable", i32 1}
-!2 = !{i32 7, !"frame-pointer", i32 2}
 !3 = !{i64 0, !"_ZTSFvcE.generalized"}
 !4 = !{i64 0, !"_ZTSFiE.generalized"}
diff --git a/llvm/test/CodeGen/ARM/call-site-info-typeid.ll 
b/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
index ec7f8a425051b..9feeef9a564cc 100644
--- a/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
+++ b/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
@@ -1,14 +1,9 @@
-; Tests that call site type ids can be extracted and set from type operand
-; bundles.
+;; Tests that ca

[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)

[via llvm-branch-commits]

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/131270
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[llvm-branch-commits] [llvm] AMDGPU: Replace undef references with poison in some MIR tests (PR #131254)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131254

>From 2e03138f1e53fd481861c5aaa780a889daa191eb Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:20:37 +0700
Subject: [PATCH] AMDGPU: Replace undef references with poison in some MIR
 tests

---
 .../CodeGen/AMDGPU/invert-br-undef-vcc.mir|   2 +-
 llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir  |  18 +-
 .../memory-legalizer-invalid-addrspace.mir|   2 +-
 .../CodeGen/AMDGPU/memory-legalizer-local.mir |  40 ++--
 .../AMDGPU/memory-legalizer-region.mir|  40 ++--
 .../CodeGen/AMDGPU/merge-flat-load-store.mir  | 210 +-
 .../merge-flat-with-global-load-store.mir |  62 +++---
 .../CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir  |   6 +-
 .../AMDGPU/optimize-if-exec-masking.mir   |  22 +-
 .../AMDGPU/scalar-store-cache-flush.mir   |   4 +-
 .../CodeGen/AMDGPU/sched-crash-dbg-value.mir  |  16 +-
 11 files changed, 211 insertions(+), 211 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir 
b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
index c9c99a9953fcd..10c46e39c3664 100644
--- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
@@ -3,7 +3,7 @@
 
   define amdgpu_kernel void @invert_br_undef_vcc(float %cond, ptr addrspace(1) 
%out) #0 {
   entry:
-br i1 undef, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
+br i1 poison, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
 
   else: ; preds = %entry
 store volatile i32 100, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir 
b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
index 195597c480319..21372c06d3223 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
@@ -10,7 +10,7 @@ name: buffer_load_dword_lds_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3) undef` + 4)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3) poison` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -27,7 +27,7 @@ name: buffer_load_dword_lds_vmcnt_1
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) poison`)
 $vgpr10 = BUFFER_LOAD_DWORD_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 
$sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr 
addrspace(1) poison`)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
@@ -44,8 +44,8 @@ name: buffer_load_dword_lds_flat_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
-$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) poison`)
+$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr poison`)
 
 S_ENDPGM 0
 
@@ -61,7 +61,7 @@ name: global_load_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3) undef` + 4)
+GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3) poison` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -91,7 +91,7 @@ name: buffer_store_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_STORE_LDS_DWORD $sgpr0_sgpr1_sgpr2_sgpr3, $s

[llvm-branch-commits] [llvm] AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (PR #131101)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

### Merge activity

* **Mar 13, 10:46 PM EDT**: A user started a stack merge that includes this 
pull request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131101).


https://github.com/llvm/llvm-project/pull/131101
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[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)

[via llvm-branch-commits]

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/131270

Backport d642eec78fc94ef3c5266dc0b10b8c51ea046e7a

Requested by: @androm3da

>From aacfe069eaacb4c1b562308fe6be7808fc50ba8b Mon Sep 17 00:00:00 2001
From: aankit-ca 
Date: Thu, 13 Mar 2025 12:48:31 -0700
Subject: [PATCH] [HEXAGON] Fix semantics of ordered FP compares (#131089)

For the ordered FP compare bitcode instructions, the Hexagon backend was
assuming that no operand could be a NaN. This assumption is flawed. This
patch fixes the code-generation to produce fpcmp.uo and and appropriate
bit comparison operators to account for the case when an operand to a FP
compare is a NaN.

Fix for https://github.com/llvm/llvm-project/issues/129391

Co-authored-by: aankit-quic 
(cherry picked from commit d642eec78fc94ef3c5266dc0b10b8c51ea046e7a)
---
 llvm/lib/Target/Hexagon/HexagonPatterns.td |  38 +++--
 llvm/test/CodeGen/Hexagon/fcmp-nan.ll  | 189 +
 2 files changed, 213 insertions(+), 14 deletions(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/fcmp-nan.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td 
b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index cba5ff1ab0d9b..244f204539c89 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -721,11 +721,6 @@ def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F32>;
-def: OpR_RR_pat, i1, F32>;
 def: OpR_RR_pat,  i1, F32>;
 def: OpR_RR_pat,  i1, F32>;
 def: OpR_RR_pat;
@@ -733,11 +728,6 @@ def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
 def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F64>;
-def: OpR_RR_pat, i1, F64>;
 def: OpR_RR_pat,  i1, F64>;
 def: OpR_RR_pat,  i1, F64>;
 def: OpR_RR_pat;
@@ -900,15 +890,35 @@ def: OpmR_RR_pat,  RevCmp, i1, 
F64>;
 def: OpmR_RR_pat,  RevCmp, i1, F64>;
 def: OpmR_RR_pat, setune, i1, F64>;
 
-def: OpmR_RR_pat, setone, i1, F32>;
-def: OpmR_RR_pat, setne,  i1, F32>;
+class T4
+  : OutPatFrag<(ops node:$Rs, node:$Rt),
+   (MI1 (MI2 (MI3 $Rs, $Rt), (MI4 $Rs, $Rt)))>;
 
-def: OpmR_RR_pat, setone, i1, F64>;
-def: OpmR_RR_pat, setne,  i1, F64>;
+class Cmpof: T3;
+class Cmpod: T3;
+
+class Cmpofn: T4;
+class Cmpodn: T4;
+
+def: OpmR_RR_pat,  setoeq, i1, F32>;
+def: OpmR_RR_pat,  setoge, i1, F32>;
+def: OpmR_RR_pat,  setogt, i1, F32>;
+def: OpmR_RR_pat,  RevCmp, i1, F32>;
+def: OpmR_RR_pat,  RevCmp, i1, F32>;
+def: OpmR_RR_pat, setone, i1, F32>;
+
+def: OpmR_RR_pat,  setoeq, i1, F64>;
+def: OpmR_RR_pat,  setoge, i1, F64>;
+def: OpmR_RR_pat,  setogt, i1, F64>;
+def: OpmR_RR_pat,  RevCmp, i1, F64>;
+def: OpmR_RR_pat,  RevCmp, i1, F64>;
+def: OpmR_RR_pat, setone, i1, F64>;
 
 def: OpmR_RR_pat, seto,   i1, F32>;
 def: OpmR_RR_pat, seto,   i1, F64>;
 
+def: OpmR_RR_pat, setne,  i1, F32>;
+def: OpmR_RR_pat, setne,  i1, F64>;
 
 // --(6) Select --
 //
diff --git a/llvm/test/CodeGen/Hexagon/fcmp-nan.ll 
b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
new file mode 100644
index 0..1469402911601
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
@@ -0,0 +1,189 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Test that all FP ordered compare instructions generate the correct
+; post-processing to accommodate NaNs.
+;
+; Specifically for ordered FP compares, we have to check if one of
+; the operands was a NaN to comform to the semantics of the ordered
+; fcmp bitcode instruction
+;
+target triple = "hexagon"
+
+;
+; Functions for float:
+;
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_oeq_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp oeq float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = or([[REG0]],[[REG1]])
+; CHECK: r0 = mux([[REG2]],#0,#1)
+;
+define i32 @compare_one_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp one float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_ogt_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+  %cmpinf = fcmp ogt float %val, %val2
+  %0 = zext i1 %cmpinf to i32
+  ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r1,r0)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r1,r0)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])

[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)

[via llvm-branch-commits]

llvmbot wrote:

@iajbar What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/131270
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[llvm-branch-commits] [clang] [clang-tools-extra] [clang][HeuristicResolver] Default argument heuristic for template parameters (PR #131074)

[Nathan Ridge via llvm-branch-commits]

https://github.com/HighCommander4 updated 
https://github.com/llvm/llvm-project/pull/131074

>From aeeb8f20927850b11c66110021fe404576ff084f Mon Sep 17 00:00:00 2001
From: Nathan Ridge 
Date: Thu, 13 Mar 2025 01:23:03 -0400
Subject: [PATCH] [clang][HeuristicResolver] Default argument heuristic for
 template parameters

---
 .../clangd/unittests/XRefsTests.cpp |  2 +-
 clang/lib/Sema/HeuristicResolver.cpp| 15 +++
 clang/unittests/Sema/HeuristicResolverTest.cpp  | 17 +
 3 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/clang-tools-extra/clangd/unittests/XRefsTests.cpp 
b/clang-tools-extra/clangd/unittests/XRefsTests.cpp
index e12d7691c58fb..693e965e78a96 100644
--- a/clang-tools-extra/clangd/unittests/XRefsTests.cpp
+++ b/clang-tools-extra/clangd/unittests/XRefsTests.cpp
@@ -1091,7 +1091,7 @@ TEST(LocateSymbol, All) {
   )objc",
   R"cpp(
 struct PointerIntPairInfo {
-  static void *getPointer(void *Value);
+  static void *$decl[[getPointer]](void *Value);
 };
 
 template  struct PointerIntPair {
diff --git a/clang/lib/Sema/HeuristicResolver.cpp 
b/clang/lib/Sema/HeuristicResolver.cpp
index d377379c627db..feda9696b8e05 100644
--- a/clang/lib/Sema/HeuristicResolver.cpp
+++ b/clang/lib/Sema/HeuristicResolver.cpp
@@ -11,6 +11,7 @@
 #include "clang/AST/CXXInheritance.h"
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/ExprCXX.h"
+#include "clang/AST/TemplateBase.h"
 #include "clang/AST/Type.h"
 
 namespace clang {
@@ -125,6 +126,20 @@ TagDecl 
*HeuristicResolverImpl::resolveTypeToTagDecl(QualType QT) {
   if (!T)
 return nullptr;
 
+  // If T is the type of a template parameter, we can't get a useful TagDecl
+  // out of it. However, if the template parameter has a default argument,
+  // as a heuristic we can replace T with the default argument type.
+  if (const auto *TTPT = dyn_cast(T)) {
+if (const auto *TTPD = TTPT->getDecl()) {
+  if (TTPD->hasDefaultArgument()) {
+const auto &DefaultArg = TTPD->getDefaultArgument().getArgument();
+if (DefaultArg.getKind() == TemplateArgument::Type) {
+  T = DefaultArg.getAsType().getTypePtrOrNull();
+}
+  }
+}
+  }
+
   // Unwrap type sugar such as type aliases.
   T = T->getCanonicalTypeInternal().getTypePtr();
 
diff --git a/clang/unittests/Sema/HeuristicResolverTest.cpp 
b/clang/unittests/Sema/HeuristicResolverTest.cpp
index c7cfe7917c532..5e36108172702 100644
--- a/clang/unittests/Sema/HeuristicResolverTest.cpp
+++ b/clang/unittests/Sema/HeuristicResolverTest.cpp
@@ -410,6 +410,23 @@ TEST(HeuristicResolver, MemberExpr_HangIssue126536) {
   cxxDependentScopeMemberExpr(hasMemberName("foo")).bind("input"));
 }
 
+TEST(HeuristicResolver, MemberExpr_DefaultTemplateArgument) {
+  std::string Code = R"cpp(
+struct Default {
+  void foo();
+};
+template 
+void bar(T t) {
+  t.foo();
+}
+  )cpp";
+  // Test resolution of "foo" in "t.foo()".
+  expectResolution(
+  Code, &HeuristicResolver::resolveMemberExpr,
+  cxxDependentScopeMemberExpr(hasMemberName("foo")).bind("input"),
+  cxxMethodDecl(hasName("foo")).bind("output"));
+}
+
 TEST(HeuristicResolver, DeclRefExpr_StaticMethod) {
   std::string Code = R"cpp(
 template 

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[llvm-branch-commits] [llvm] [llvm][AsmPrinter] Emit call graph section (PR #87576)

[via llvm-branch-commits]

https://github.com/Prabhuk updated 
https://github.com/llvm/llvm-project/pull/87576

>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran 
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.

Created using spr 1.3.6-beta.1
---
 llvm/test/CodeGen/X86/call-graph-section.ll | 66 +++
 llvm/test/CodeGen/call-graph-section.ll | 73 -
 2 files changed, 66 insertions(+), 73 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/call-graph-section.ll
 delete mode 100644 llvm/test/CodeGen/call-graph-section.ll

diff --git a/llvm/test/CodeGen/X86/call-graph-section.ll 
b/llvm/test/CodeGen/X86/call-graph-section.ll
new file mode 100644
index 0..a77a2b8051ed3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-graph-section.ll
@@ -0,0 +1,66 @@
+;; Tests that we store the type identifiers in .callgraph section of the 
binary.
+
+; RUN: llc --call-graph-section -filetype=obj -o - < %s | \
+; RUN: llvm-readelf -x .callgraph - | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local void @foo() #0 !type !4 {
+entry:
+  ret void
+}
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local i32 @bar(i8 signext %a) #0 !type !5 {
+entry:
+  %a.addr = alloca i8, align 1
+  store i8 %a, ptr %a.addr, align 1
+  ret i32 0
+}
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local ptr @baz(ptr %a) #0 !type !6 {
+entry:
+  %a.addr = alloca ptr, align 8
+  store ptr %a, ptr %a.addr, align 8
+  ret ptr null
+}
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local void @main() #0 !type !7 {
+entry:
+  %retval = alloca i32, align 4
+  %fp_foo = alloca ptr, align 8
+  %a = alloca i8, align 1
+  %fp_bar = alloca ptr, align 8
+  %fp_baz = alloca ptr, align 8
+  store i32 0, ptr %retval, align 4
+  store ptr @foo, ptr %fp_foo, align 8
+  %0 = load ptr, ptr %fp_foo, align 8
+  call void (...) %0() [ "callee_type"(metadata !"_ZTSFvE.generalized") ]
+  store ptr @bar, ptr %fp_bar, align 8
+  %1 = load ptr, ptr %fp_bar, align 8
+  %2 = load i8, ptr %a, align 1
+  %call = call i32 %1(i8 signext %2) [ "callee_type"(metadata 
!"_ZTSFicE.generalized") ]
+  store ptr @baz, ptr %fp_baz, align 8
+  %3 = load ptr, ptr %fp_baz, align 8
+  %call1 = call ptr %3(ptr %a) [ "callee_type"(metadata 
!"_ZTSFPvS_E.generalized") ]
+  call void @foo() [ "callee_type"(metadata !"_ZTSFvE.generalized") ]
+  %4 = load i8, ptr %a, align 1
+  %call2 = call i32 @bar(i8 signext %4) [ "callee_type"(metadata 
!"_ZTSFicE.generalized") ]
+  %call3 = call ptr @baz(ptr %a) [ "callee_type"(metadata 
!"_ZTSFPvS_E.generalized") ]
+  ret void
+}
+
+;; Check that the numeric type id (md5 hash) for the below type ids are emitted
+;; to the callgraph section.
+
+; CHECK: Hex dump of section '.callgraph':
+
+; CHECK-DAG: 2444f731 f5eecb3e
+!4 = !{i64 0, !"_ZTSFvE.generalized"}
+; CHECK-DAG: 5486bc59 814b8e30
+!5 = !{i64 0, !"_ZTSFicE.generalized"}
+; CHECK-DAG: 7ade6814 f897fd77
+!6 = !{i64 0, !"_ZTSFPvS_E.generalized"}
+; CHECK-DAG: caaf769a 600968fa
+!7 = !{i64 0, !"_ZTSFiE.generalized"}
diff --git a/llvm/test/CodeGen/call-graph-section.ll 
b/llvm/test/CodeGen/call-graph-section.ll
deleted file mode 100644
index bb158d11e82c9..0
--- a/llvm/test/CodeGen/call-graph-section.ll
+++ /dev/null
@@ -1,73 +0,0 @@
-; Tests that we store the type identifiers in .callgraph section of the binary.
-
-; RUN: llc --call-graph-section -filetype=obj -o - < %s | \
-; RUN: llvm-readelf -x .callgraph - | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
-
-define dso_local void @foo() #0 !type !4 {
-entry:
-  ret void
-}
-
-define dso_local i32 @bar(i8 signext %a) #0 !type !5 {
-entry:
-  %a.addr = alloca i8, align 1
-  store i8 %a, i8* %a.addr, align 1
-  ret i32 0
-}
-
-define dso_local i32* @baz(i8* %a) #0 !type !6 {
-entry:
-  %a.addr = alloca i8*, align 8
-  store i8* %a, i8** %a.addr, align 8
-  ret i32* null
-}
-
-define dso_local i32 @main() #0 !type !7 {
-entry:
-  %retval = alloca i32, align 4
-  %fp_foo = alloca void (...)*, align 8
-  %a = alloca i8, align 1
-  %fp_bar = alloca i32 (i8)*, align 8
-  %fp_baz = alloca i32* (i8*)*, align 8
-  store i32 0, i32* %retval, align 4
-  store void (...)* bitcast (void ()* @foo to void (...)*), void (...)** 
%fp_foo, align 8
-  %0 = load void (...)*, void (...)** %fp_foo, align 8
-  call void (...) %0() [ "callee_type"(metadata !"_ZTSFvE.generalized") ]
-  store i32 (i8)* @bar, i32 (i8)** %fp_bar, align 8
-  %1 = load i32 (i8)*, i32 (i8)** %fp_bar, align 8
-  %2 = load i8, i8* %a, align 1
-  %call = call i32 %1(i8 signext %2) [ "callee_type"(metadata 
!"_ZTSFicE.generalized") ]
-  store i32* (i8*)* @baz, i32* (i8*)** %fp_baz, align 8
-  %3 = load i32* (i8*)*, i32* (i8*)** %fp_baz, align 8
-  %call1 = call i32* %3(i8* %a) [ "callee_type"(metadata 
!"_ZTSFPvS_E.generalized") ]
-  call void @foo() [ "callee_type"(meta

[llvm-branch-commits] [llvm] AMDGPU: Add generated checks to compile only test (PR #131258)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes

Also replace an undef use

---
Full diff: https://github.com/llvm/llvm-project/pull/131258.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/swdev282079.ll (+26-2) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.ll 
b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
index 184eb4f6f0baa..20eb6ff560979 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
@@ -1,11 +1,35 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
 
 define protected amdgpu_kernel void @foo(ptr addrspace(1) %arg, ptr 
addrspace(1) %arg1) {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %bb
+; CHECK-NEXT:s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:s_add_u32 s0, s0, s17
+; CHECK-NEXT:s_addc_u32 s1, s1, 0
+; CHECK-NEXT:s_add_u32 s8, s8, 16
+; CHECK-NEXT:s_addc_u32 s9, s9, 0
+; CHECK-NEXT:s_mov_b32 s13, s15
+; CHECK-NEXT:s_mov_b32 s12, s14
+; CHECK-NEXT:s_getpc_b64 s[18:19]
+; CHECK-NEXT:s_add_u32 s18, s18, eggs@rel32@lo+4
+; CHECK-NEXT:s_addc_u32 s19, s19, eggs@rel32@hi+12
+; CHECK-NEXT:s_mov_b32 s14, s16
+; CHECK-NEXT:v_mov_b32_e32 v31, v0
+; CHECK-NEXT:v_mov_b32_e32 v1, 0
+; CHECK-NEXT:s_mov_b32 s32, 0
+; CHECK-NEXT:s_swappc_b64 s[30:31], s[18:19]
+; CHECK-NEXT:buffer_load_dword v2, off, s[0:3], 0
+; CHECK-NEXT:buffer_load_dword v3, off, s[0:3], 0 offset:4
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:flat_store_dwordx2 v[2:3], v[0:1]
+; CHECK-NEXT:s_endpgm
 bb:
   %tmp = addrspacecast ptr addrspace(5) null to ptr
   %tmp2 = call i64 @eggs(ptr poison) #1
   %tmp3 = load ptr, ptr %tmp, align 8
-  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 undef
+  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 0
   store i64 %tmp2, ptr %tmp4, align 8
   ret void
 }

``




https://github.com/llvm/llvm-project/pull/131258
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[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/131259

This wasn't checking anything. Also remove undef uses.

>From ab94652a381edcb9ebe2a9b36f67ea13f391dcab Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 09:14:10 +0700
Subject: [PATCH] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll
 test

This wasn't checking anything. Also remove undef uses.
---
 .../AMDGPU/reg-coalescer-sched-crash.ll   | 68 +--
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll 
b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
index 51072c36dadd2..a3b3831f5b954 100644
--- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -o /dev/null < %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global 
-verify-machineinstrs -o /dev/null < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
 ; The register coalescer introduces a verifier error which later
 ; results in a crash during scheduling.
@@ -7,13 +8,72 @@
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) 
nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %c0) #1 {
+; GFX6-LABEL: reg_coalescer_breaks_dead:
+; GFX6:   ; %bb.0: ; %bb
+; GFX6-NEXT:v_mov_b32_e32 v1, 0
+; GFX6-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX6-NEXT:v_mov_b32_e32 v2, 0
+; GFX6-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX6-NEXT:s_cbranch_execz .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %bb3
+; GFX6-NEXT:s_load_dword s2, s[4:5], 0xb
+; GFX6-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x9
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX6-NEXT:s_add_u32 s2, s6, s2
+; GFX6-NEXT:s_addc_u32 s3, s7, s3
+; GFX6-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:v_mov_b32_e32 v1, s2
+; GFX6-NEXT:v_mov_b32_e32 v2, s3
+; GFX6-NEXT:  .LBB0_2: ; %bb4
+; GFX6-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:s_load_dword s0, s[4:5], 0xe
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_bitcmp0_b32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %bb15
+; GFX6-NEXT:s_mov_b32 m0, -1
+; GFX6-NEXT:ds_write_b64 v0, v[1:2]
+; GFX6-NEXT:  .LBB0_4: ; %bb16
+;
+; GFX8-LABEL: reg_coalescer_breaks_dead:
+; GFX8:   ; %bb.0: ; %bb
+; GFX8-NEXT:v_mov_b32_e32 v1, 0
+; GFX8-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT:v_mov_b32_e32 v2, 0
+; GFX8-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:s_cbranch_execz .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %bb3
+; GFX8-NEXT:s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_ashr_i32 s3, s2, 31
+; GFX8-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX8-NEXT:s_add_u32 s2, s6, s2
+; GFX8-NEXT:s_addc_u32 s3, s7, s3
+; GFX8-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:v_mov_b32_e32 v1, s2
+; GFX8-NEXT:v_mov_b32_e32 v2, s3
+; GFX8-NEXT:  .LBB0_2: ; %bb4
+; GFX8-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:s_load_dword s0, s[4:5], 0x38
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_bitcmp0_b32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %bb15
+; GFX8-NEXT:s_mov_b32 m0, -1
+; GFX8-NEXT:ds_write_b64 v0, v[1:2]
+; GFX8-NEXT:  .LBB0_4: ; %bb16
 bb:
   %id.x = call i32 @llvm.amdgcn.workitem.id.x()
   %cmp0 = icmp eq i32 %id.x, 0
   br i1 %cmp0, label %bb3, label %bb4
 
 bb3:  ; preds = %bb
-  %tmp = ashr exact i32 undef, 8
+  %tmp = ashr exact i32 poison, 8
   br label %bb6
 
 bb4:  ; preds = %bb6, %bb
@@ -28,7 +88,7 @@ bb6:  ; preds = 
%bb6, %bb3
   %tmp11 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i64 %tmp10
   %tmp12 = load <2 x i32>, ptr addrspace(1) %tmp11, align 8
   %tmp13 = add <2 x i32> %tmp12, %tmp7
-  %tmp14 = icmp slt i32 undef, %arg2
+  %tmp14 = icmp slt i32 poison, %arg2
   br i1 %tmp14, label %bb6, label %bb4
 
 bb15: ; preds = %bb4

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[llvm-branch-commits] [llvm] AMDGPU: Add generated checks to compile only test (PR #131258)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/131258

Also replace an undef use

>From 054d0f34e83192f7aceacb99db18746d5dfab617 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 09:00:37 +0700
Subject: [PATCH] AMDGPU: Add generated checks to compile only test

Also replace an undef use
---
 llvm/test/CodeGen/AMDGPU/swdev282079.ll | 28 +++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.ll 
b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
index 184eb4f6f0baa..20eb6ff560979 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
@@ -1,11 +1,35 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
 
 define protected amdgpu_kernel void @foo(ptr addrspace(1) %arg, ptr 
addrspace(1) %arg1) {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %bb
+; CHECK-NEXT:s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:s_add_u32 s0, s0, s17
+; CHECK-NEXT:s_addc_u32 s1, s1, 0
+; CHECK-NEXT:s_add_u32 s8, s8, 16
+; CHECK-NEXT:s_addc_u32 s9, s9, 0
+; CHECK-NEXT:s_mov_b32 s13, s15
+; CHECK-NEXT:s_mov_b32 s12, s14
+; CHECK-NEXT:s_getpc_b64 s[18:19]
+; CHECK-NEXT:s_add_u32 s18, s18, eggs@rel32@lo+4
+; CHECK-NEXT:s_addc_u32 s19, s19, eggs@rel32@hi+12
+; CHECK-NEXT:s_mov_b32 s14, s16
+; CHECK-NEXT:v_mov_b32_e32 v31, v0
+; CHECK-NEXT:v_mov_b32_e32 v1, 0
+; CHECK-NEXT:s_mov_b32 s32, 0
+; CHECK-NEXT:s_swappc_b64 s[30:31], s[18:19]
+; CHECK-NEXT:buffer_load_dword v2, off, s[0:3], 0
+; CHECK-NEXT:buffer_load_dword v3, off, s[0:3], 0 offset:4
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:flat_store_dwordx2 v[2:3], v[0:1]
+; CHECK-NEXT:s_endpgm
 bb:
   %tmp = addrspacecast ptr addrspace(5) null to ptr
   %tmp2 = call i64 @eggs(ptr poison) #1
   %tmp3 = load ptr, ptr %tmp, align 8
-  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 undef
+  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 0
   store i64 %tmp2, ptr %tmp4, align 8
   ret void
 }

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[llvm-branch-commits] [llvm] AMDGPU: Replace undef references with poison in some MIR tests (PR #131254)

[via llvm-branch-commits]

llvmbot wrote:



@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes



---

Patch is 102.20 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/131254.diff


11 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir (+9-9) 
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir 
(+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir (+20-20) 
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir (+20-20) 
- (modified) llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir (+105-105) 
- (modified) llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir 
(+31-31) 
- (modified) llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir (+3-3) 
- (modified) llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir (+11-11) 
- (modified) llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir (+8-8) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir 
b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
index c9c99a9953fcd..10c46e39c3664 100644
--- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
@@ -3,7 +3,7 @@
 
   define amdgpu_kernel void @invert_br_undef_vcc(float %cond, ptr addrspace(1) 
%out) #0 {
   entry:
-br i1 undef, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
+br i1 poison, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
 
   else: ; preds = %entry
 store volatile i32 100, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir 
b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
index 195597c480319..cab45900b996e 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
@@ -10,7 +10,7 @@ name: buffer_load_dword_lds_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3) undef` + 4)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3)` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -27,7 +27,7 @@ name: buffer_load_dword_lds_vmcnt_1
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3)`)
 $vgpr10 = BUFFER_LOAD_DWORD_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 
$sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr 
addrspace(1) poison`)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
@@ -44,8 +44,8 @@ name: buffer_load_dword_lds_flat_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
-$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3)`)
+$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr poison`)
 
 S_ENDPGM 0
 
@@ -61,7 +61,7 @@ name: global_load_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3) undef` + 4)
+GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3)` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -91,7 +91,7 @@ name: buffer_store_lds_dword_ds_read
 b

[llvm-branch-commits] [llvm] AMDGPU: Switch a test to generated checks which only tested labels (PR #131257)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/131257

Also remove an undef use

>From 568de613be189432152c007ab89e9b73cbd333d6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 08:41:22 +0700
Subject: [PATCH] AMDGPU: Switch a test to generated checks which only tested
 labels

Also remove an undef use
---
 llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll | 53 +---
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll 
b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
index d198ec28f1602..21d4bcfcdc8c1 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
@@ -1,16 +1,58 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck 
%s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck 
%s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
-; CHECK-LABEL: {{^}}main:
-;
 ; Test for compilation only. This generated an invalid machine instruction
 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
+; GFX6-LABEL: main:
+; GFX6:   ; %bb.0: ; %main_body
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %IF57
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %IF60
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf4
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX6-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX6-NEXT:s_branch .LBB0_7
+; GFX6-NEXT:  .LBB0_6: ; %IF63
+; GFX6-NEXT:  .LBB0_7:
+;
+; GFX8-LABEL: main:
+; GFX8:   ; %bb.0: ; %main_body
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %IF57
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3c0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %IF60
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3d0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX8-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX8-NEXT:s_branch .LBB0_7
+; GFX8-NEXT:  .LBB0_6: ; %IF63
+; GFX8-NEXT:  .LBB0_7:
 main_body:
   %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, 
i32 0)
   %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, 
i32 0)
-  br i1 undef, label %ENDIF56, label %IF57
+  br i1 poison, label %ENDIF56, label %IF57
 
 IF57: ; preds = %ENDIF
   %v.1 = mul i32 %v, 2
@@ -40,7 +82,6 @@ ENDIF62:  ; preds = 
%ENDIF59
   ret float %r
 }
 
-; Function Attrs: nounwind readnone
 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
 
 attributes #0 = { nounwind readnone }

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[llvm-branch-commits] [llvm] AMDGPU: Switch a test to generated checks which only tested labels (PR #131257)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131257

>From 77fef8e3337bd6ccbce04c38de4365eb155d4172 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 08:41:22 +0700
Subject: [PATCH] AMDGPU: Switch a test to generated checks which only tested
 labels

Also remove an undef use
---
 llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll | 53 +---
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll 
b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
index d198ec28f1602..21d4bcfcdc8c1 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
@@ -1,16 +1,58 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck 
%s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck 
%s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
-; CHECK-LABEL: {{^}}main:
-;
 ; Test for compilation only. This generated an invalid machine instruction
 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
+; GFX6-LABEL: main:
+; GFX6:   ; %bb.0: ; %main_body
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %IF57
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %IF60
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf4
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX6-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX6-NEXT:s_branch .LBB0_7
+; GFX6-NEXT:  .LBB0_6: ; %IF63
+; GFX6-NEXT:  .LBB0_7:
+;
+; GFX8-LABEL: main:
+; GFX8:   ; %bb.0: ; %main_body
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %IF57
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3c0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %IF60
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3d0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX8-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX8-NEXT:s_branch .LBB0_7
+; GFX8-NEXT:  .LBB0_6: ; %IF63
+; GFX8-NEXT:  .LBB0_7:
 main_body:
   %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, 
i32 0)
   %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, 
i32 0)
-  br i1 undef, label %ENDIF56, label %IF57
+  br i1 poison, label %ENDIF56, label %IF57
 
 IF57: ; preds = %ENDIF
   %v.1 = mul i32 %v, 2
@@ -40,7 +82,6 @@ ENDIF62:  ; preds = 
%ENDIF59
   ret float %r
 }
 
-; Function Attrs: nounwind readnone
 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
 
 attributes #0 = { nounwind readnone }

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[llvm-branch-commits] [llvm] AMDGPU: Switch a test with only function label checks to generated (PR #131255)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131255

>From 9eeb3a6aa1ff43ea4b60320ffb532db1b1a772b3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:27:08 +0700
Subject: [PATCH] AMDGPU: Switch a test with only function label checks to
 generated

I suspect the first function at least is not usefully testing
the original failure.
---
 .../CodeGen/AMDGPU/subreg-coalescer-crash.ll  | 37 ---
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index 19c43fa22271b..a0ac6c1b28449 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -1,8 +1,13 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | 
FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck 
-check-prefixes=GCN,GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -o - %s | FileCheck 
-check-prefixes=GCN,GFX8 %s
 
-; GCN-LABEL:{{^}}row_filter_C1_D0:
 define amdgpu_kernel void @row_filter_C1_D0() #0 {
+; GCN-LABEL: row_filter_C1_D0:
+; GCN:   ; %bb.0: ; %entry
+; GCN-NEXT:s_cbranch_scc1 .LBB0_2
+; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
+; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
   br i1 undef, label %for.inc.1, label %do.body.preheader
 
@@ -40,9 +45,28 @@ for.inc.1:; preds = 
%do.body.1562.prehea
   unreachable
 }
 
-; GCN-LABEL: {{^}}foo:
-; GCN: s_endpgm
 define amdgpu_ps void @foo() #0 {
+; GCN-LABEL: foo:
+; GCN:   ; %bb.0: ; %bb
+; GCN-NEXT:s_mov_b64 s[0:1], -1
+; GCN-NEXT:s_cbranch_scc0 .LBB1_2
+; GCN-NEXT:  ; %bb.1: ; %bb24
+; GCN-NEXT:s_mov_b64 s[0:1], 0
+; GCN-NEXT:  .LBB1_2: ; %Flow1
+; GCN-NEXT:s_and_b64 vcc, exec, s[0:1]
+; GCN-NEXT:s_cbranch_vccz .LBB1_4
+; GCN-NEXT:  ; %bb.3: ; %bb9
+; GCN-NEXT:image_sample v[0:1], v0, s[0:7], s[0:3] dmask:0xa
+; GCN-NEXT:s_branch .LBB1_5
+; GCN-NEXT:  .LBB1_4:
+; GCN-NEXT:v_mov_b32_e32 v1, 0
+; GCN-NEXT:v_mov_b32_e32 v0, v1
+; GCN-NEXT:  .LBB1_5: ; %bb14
+; GCN-NEXT:s_waitcnt vmcnt(0)
+; GCN-NEXT:v_mul_f32_e32 v0, 0x4128, v0
+; GCN-NEXT:v_mul_f32_e32 v1, 0x4138, v1
+; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
+; GCN-NEXT:s_endpgm
 bb:
   br i1 undef, label %bb2, label %bb1
 
@@ -101,3 +125,6 @@ declare <4 x float> 
@llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add 
tests below this line:
+; GFX6: {{.*}}
+; GFX8: {{.*}}

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[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131259

>From 494add88ab7be9eb33aaa3489634457df033c90f Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 09:14:10 +0700
Subject: [PATCH] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll
 test

This wasn't checking anything. Also remove undef uses.
---
 .../AMDGPU/reg-coalescer-sched-crash.ll   | 68 +--
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll 
b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
index 51072c36dadd2..a3b3831f5b954 100644
--- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -o /dev/null < %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global 
-verify-machineinstrs -o /dev/null < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
 ; The register coalescer introduces a verifier error which later
 ; results in a crash during scheduling.
@@ -7,13 +8,72 @@
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) 
nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %c0) #1 {
+; GFX6-LABEL: reg_coalescer_breaks_dead:
+; GFX6:   ; %bb.0: ; %bb
+; GFX6-NEXT:v_mov_b32_e32 v1, 0
+; GFX6-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX6-NEXT:v_mov_b32_e32 v2, 0
+; GFX6-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX6-NEXT:s_cbranch_execz .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %bb3
+; GFX6-NEXT:s_load_dword s2, s[4:5], 0xb
+; GFX6-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x9
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX6-NEXT:s_add_u32 s2, s6, s2
+; GFX6-NEXT:s_addc_u32 s3, s7, s3
+; GFX6-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:v_mov_b32_e32 v1, s2
+; GFX6-NEXT:v_mov_b32_e32 v2, s3
+; GFX6-NEXT:  .LBB0_2: ; %bb4
+; GFX6-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:s_load_dword s0, s[4:5], 0xe
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_bitcmp0_b32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %bb15
+; GFX6-NEXT:s_mov_b32 m0, -1
+; GFX6-NEXT:ds_write_b64 v0, v[1:2]
+; GFX6-NEXT:  .LBB0_4: ; %bb16
+;
+; GFX8-LABEL: reg_coalescer_breaks_dead:
+; GFX8:   ; %bb.0: ; %bb
+; GFX8-NEXT:v_mov_b32_e32 v1, 0
+; GFX8-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT:v_mov_b32_e32 v2, 0
+; GFX8-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:s_cbranch_execz .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %bb3
+; GFX8-NEXT:s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_ashr_i32 s3, s2, 31
+; GFX8-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX8-NEXT:s_add_u32 s2, s6, s2
+; GFX8-NEXT:s_addc_u32 s3, s7, s3
+; GFX8-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:v_mov_b32_e32 v1, s2
+; GFX8-NEXT:v_mov_b32_e32 v2, s3
+; GFX8-NEXT:  .LBB0_2: ; %bb4
+; GFX8-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:s_load_dword s0, s[4:5], 0x38
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_bitcmp0_b32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %bb15
+; GFX8-NEXT:s_mov_b32 m0, -1
+; GFX8-NEXT:ds_write_b64 v0, v[1:2]
+; GFX8-NEXT:  .LBB0_4: ; %bb16
 bb:
   %id.x = call i32 @llvm.amdgcn.workitem.id.x()
   %cmp0 = icmp eq i32 %id.x, 0
   br i1 %cmp0, label %bb3, label %bb4
 
 bb3:  ; preds = %bb
-  %tmp = ashr exact i32 undef, 8
+  %tmp = ashr exact i32 poison, 8
   br label %bb6
 
 bb4:  ; preds = %bb6, %bb
@@ -28,7 +88,7 @@ bb6:  ; preds = 
%bb6, %bb3
   %tmp11 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i64 %tmp10
   %tmp12 = load <2 x i32>, ptr addrspace(1) %tmp11, align 8
   %tmp13 = add <2 x i32> %tmp12, %tmp7
-  %tmp14 = icmp slt i32 undef, %arg2
+  %tmp14 = icmp slt i32 poison, %arg2
   br i1 %tmp14, label %bb6, label %bb4
 
 bb15: ; preds = %bb4

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[llvm-branch-commits] [llvm] AMDGPU: Replace undef references with poison in some MIR tests (PR #131254)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131254

>From 2e03138f1e53fd481861c5aaa780a889daa191eb Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:20:37 +0700
Subject: [PATCH] AMDGPU: Replace undef references with poison in some MIR
 tests

---
 .../CodeGen/AMDGPU/invert-br-undef-vcc.mir|   2 +-
 llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir  |  18 +-
 .../memory-legalizer-invalid-addrspace.mir|   2 +-
 .../CodeGen/AMDGPU/memory-legalizer-local.mir |  40 ++--
 .../AMDGPU/memory-legalizer-region.mir|  40 ++--
 .../CodeGen/AMDGPU/merge-flat-load-store.mir  | 210 +-
 .../merge-flat-with-global-load-store.mir |  62 +++---
 .../CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir  |   6 +-
 .../AMDGPU/optimize-if-exec-masking.mir   |  22 +-
 .../AMDGPU/scalar-store-cache-flush.mir   |   4 +-
 .../CodeGen/AMDGPU/sched-crash-dbg-value.mir  |  16 +-
 11 files changed, 211 insertions(+), 211 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir 
b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
index c9c99a9953fcd..10c46e39c3664 100644
--- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
@@ -3,7 +3,7 @@
 
   define amdgpu_kernel void @invert_br_undef_vcc(float %cond, ptr addrspace(1) 
%out) #0 {
   entry:
-br i1 undef, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
+br i1 poison, label %if, label %else, !structurizecfg.uniform !0, 
!amdgpu.uniform !0
 
   else: ; preds = %entry
 store volatile i32 100, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir 
b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
index 195597c480319..21372c06d3223 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
@@ -10,7 +10,7 @@ name: buffer_load_dword_lds_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3) undef` + 4)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison` + 4), (store (s32) into `ptr addrspace(3) poison` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -27,7 +27,7 @@ name: buffer_load_dword_lds_vmcnt_1
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) poison`)
 $vgpr10 = BUFFER_LOAD_DWORD_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 
$sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr 
addrspace(1) poison`)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
@@ -44,8 +44,8 @@ name: buffer_load_dword_lds_flat_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) undef`)
-$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr undef`)
+BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 
0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) 
poison`), (store (s32) into `ptr addrspace(3) poison`)
+$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit 
$flat_scr :: (load (s32) from `ptr poison`)
 
 S_ENDPGM 0
 
@@ -61,7 +61,7 @@ name: global_load_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3) undef` + 4)
+GLOBAL_LOAD_LDS_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $m0 :: 
(load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr 
addrspace(3) poison` + 4)
 $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: 
(load (s32) from `ptr addrspace(3) poison`)
 S_ENDPGM 0
 
@@ -91,7 +91,7 @@ name: buffer_store_lds_dword_ds_read
 body: |
   bb.0:
 $m0 = S_MOV_B32 0
-BUFFER_STORE_LDS_DWORD $sgpr0_sgpr1_sgpr2_sgpr3, $s

[llvm-branch-commits] [llvm] AMDGPU: Remove undef in subreg-coalescer-crash.ll (PR #131256)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131256

>From 5202d325afa9704a5b18e37353a410d9079855a4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:35:11 +0700
Subject: [PATCH] AMDGPU: Remove undef in subreg-coalescer-crash.ll

---
 .../CodeGen/AMDGPU/subreg-coalescer-crash.ll  | 32 +++
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index a0ac6c1b28449..a69ee2e1a8b5c 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -9,17 +9,19 @@ define amdgpu_kernel void @row_filter_C1_D0() #0 {
 ; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
 ; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
-  br i1 undef, label %for.inc.1, label %do.body.preheader
+  br i1 poison, label %for.inc.1, label %do.body.preheader
 
 do.body.preheader:; preds = %entry
   %tmp = insertelement <4 x i32> zeroinitializer, i32 poison, i32 1
-  br i1 undef, label %do.body56.1, label %do.body90
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %do.body56.1, label %do.body90
 
 do.body90:; preds = %do.body56.2, 
%do.body56.1, %do.body.preheader
   %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ 
%tmp, %do.body.preheader ]
   %tmp2 = insertelement <4 x i32> %tmp1, i32 poison, i32 2
   %tmp3 = insertelement <4 x i32> %tmp2, i32 poison, i32 3
-  br i1 undef, label %do.body124.1, label %do.body.1562.preheader
+  %undef3 = freeze i1 poison
+  br i1 %undef3, label %do.body124.1, label %do.body.1562.preheader
 
 do.body.1562.preheader:   ; preds = %do.body124.1, 
%do.body90
   %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
@@ -28,7 +30,7 @@ do.body.1562.preheader:   ; preds = 
%do.body124.1, %do.b
 
 do.body56.1:  ; preds = %do.body.preheader
   %tmp5 = insertelement <4 x i32> %tmp, i32 poison, i32 1
-  %or.cond472.1 = or i1 undef, undef
+  %or.cond472.1 = or i1 poison, poison
   br i1 %or.cond472.1, label %do.body56.2, label %do.body90
 
 do.body56.2:  ; preds = %do.body56.1
@@ -41,7 +43,8 @@ do.body124.1: ; preds = 
%do.body90
 
 for.inc.1:; preds = 
%do.body.1562.preheader, %entry
   %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, 
%do.body.1562.preheader ]
-  %add.i495 = add <4 x i32> %storemerge591, undef
+  %undef2 = freeze <4 x i32> poison
+  %add.i495 = add <4 x i32> %storemerge591, %undef2
   unreachable
 }
 
@@ -68,24 +71,27 @@ define amdgpu_ps void @foo() #0 {
 ; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
 ; GCN-NEXT:s_endpgm
 bb:
-  br i1 undef, label %bb2, label %bb1
+  %undef0 = freeze i1 poison
+  br i1 %undef0, label %bb2, label %bb1
 
 bb1:  ; preds = %bb
-  br i1 undef, label %bb4, label %bb6
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %bb4, label %bb6
 
 bb2:  ; preds = %bb4, %bb
   %tmp = phi float [ %tmp5, %bb4 ], [ 0.00e+00, %bb ]
-  br i1 undef, label %bb9, label %bb13
+  br i1 poison, label %bb9, label %bb13
 
 bb4:  ; preds = %bb7, %bb6, %bb1
   %tmp5 = phi float [ poison, %bb1 ], [ poison, %bb6 ], [ %tmp8, %bb7 ]
   br label %bb2
 
 bb6:  ; preds = %bb1
-  br i1 undef, label %bb7, label %bb4
+  %undef2 = freeze i1 poison
+  br i1 %undef2, label %bb7, label %bb4
 
 bb7:  ; preds = %bb6
-  %tmp8 = fmul float undef, undef
+  %tmp8 = fmul float poison, poison
   br label %bb4
 
 bb9:  ; preds = %bb2
@@ -95,7 +101,7 @@ bb9:  ; preds = 
%bb2
   br label %bb14
 
 bb13: ; preds = %bb2
-  br i1 undef, label %bb23, label %bb24
+  br i1 poison, label %bb23, label %bb24
 
 bb14: ; preds = %bb27, %bb24, %bb9
   %tmp15 = phi float [ %tmp12, %bb9 ], [ poison, %bb27 ], [ 0.00e+00, 
%bb24 ]
@@ -106,11 +112,11 @@ bb14: ; preds 
= %bb27, %bb24, %bb9
   ret void
 
 bb23: ; preds = %bb13
-  br i1 undef, label %bb24, label %bb26
+  br i1 poison, label %bb24, label %bb26
 
 bb24: ; preds = %bb26, %bb23, %bb13
   %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.00e+00, %bb23 ]
-  br i1 undef, label %bb27, label %bb14
+  br i1 poison, label %bb27, label %bb14
 
 bb26:  

[llvm-branch-commits] [llvm] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test (PR #131259)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131259

>From 494add88ab7be9eb33aaa3489634457df033c90f Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 09:14:10 +0700
Subject: [PATCH] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll
 test

This wasn't checking anything. Also remove undef uses.
---
 .../AMDGPU/reg-coalescer-sched-crash.ll   | 68 +--
 1 file changed, 64 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll 
b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
index 51072c36dadd2..a3b3831f5b954 100644
--- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -o /dev/null < %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global 
-verify-machineinstrs -o /dev/null < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
 ; The register coalescer introduces a verifier error which later
 ; results in a crash during scheduling.
@@ -7,13 +8,72 @@
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) 
nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %c0) #1 {
+; GFX6-LABEL: reg_coalescer_breaks_dead:
+; GFX6:   ; %bb.0: ; %bb
+; GFX6-NEXT:v_mov_b32_e32 v1, 0
+; GFX6-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX6-NEXT:v_mov_b32_e32 v2, 0
+; GFX6-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX6-NEXT:s_cbranch_execz .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %bb3
+; GFX6-NEXT:s_load_dword s2, s[4:5], 0xb
+; GFX6-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x9
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX6-NEXT:s_add_u32 s2, s6, s2
+; GFX6-NEXT:s_addc_u32 s3, s7, s3
+; GFX6-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:v_mov_b32_e32 v1, s2
+; GFX6-NEXT:v_mov_b32_e32 v2, s3
+; GFX6-NEXT:  .LBB0_2: ; %bb4
+; GFX6-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:s_load_dword s0, s[4:5], 0xe
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_bitcmp0_b32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %bb15
+; GFX6-NEXT:s_mov_b32 m0, -1
+; GFX6-NEXT:ds_write_b64 v0, v[1:2]
+; GFX6-NEXT:  .LBB0_4: ; %bb16
+;
+; GFX8-LABEL: reg_coalescer_breaks_dead:
+; GFX8:   ; %bb.0: ; %bb
+; GFX8-NEXT:v_mov_b32_e32 v1, 0
+; GFX8-NEXT:v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT:v_mov_b32_e32 v2, 0
+; GFX8-NEXT:s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:s_cbranch_execz .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %bb3
+; GFX8-NEXT:s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT:s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_ashr_i32 s3, s2, 31
+; GFX8-NEXT:s_lshl_b64 s[2:3], s[2:3], 3
+; GFX8-NEXT:s_add_u32 s2, s6, s2
+; GFX8-NEXT:s_addc_u32 s3, s7, s3
+; GFX8-NEXT:s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:v_mov_b32_e32 v1, s2
+; GFX8-NEXT:v_mov_b32_e32 v2, s3
+; GFX8-NEXT:  .LBB0_2: ; %bb4
+; GFX8-NEXT:s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:s_load_dword s0, s[4:5], 0x38
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_bitcmp0_b32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %bb15
+; GFX8-NEXT:s_mov_b32 m0, -1
+; GFX8-NEXT:ds_write_b64 v0, v[1:2]
+; GFX8-NEXT:  .LBB0_4: ; %bb16
 bb:
   %id.x = call i32 @llvm.amdgcn.workitem.id.x()
   %cmp0 = icmp eq i32 %id.x, 0
   br i1 %cmp0, label %bb3, label %bb4
 
 bb3:  ; preds = %bb
-  %tmp = ashr exact i32 undef, 8
+  %tmp = ashr exact i32 poison, 8
   br label %bb6
 
 bb4:  ; preds = %bb6, %bb
@@ -28,7 +88,7 @@ bb6:  ; preds = 
%bb6, %bb3
   %tmp11 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i64 %tmp10
   %tmp12 = load <2 x i32>, ptr addrspace(1) %tmp11, align 8
   %tmp13 = add <2 x i32> %tmp12, %tmp7
-  %tmp14 = icmp slt i32 undef, %arg2
+  %tmp14 = icmp slt i32 poison, %arg2
   br i1 %tmp14, label %bb6, label %bb4
 
 bb15: ; preds = %bb4

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[llvm-branch-commits] [llvm] AMDGPU: Add generated checks to compile only test (PR #131258)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131258

>From 810371b2bc4945b5818308abfe0703eb59343481 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 09:00:37 +0700
Subject: [PATCH] AMDGPU: Add generated checks to compile only test

Also replace an undef use
---
 llvm/test/CodeGen/AMDGPU/swdev282079.ll | 28 +++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/swdev282079.ll 
b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
index 184eb4f6f0baa..20eb6ff560979 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev282079.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev282079.ll
@@ -1,11 +1,35 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
 
 define protected amdgpu_kernel void @foo(ptr addrspace(1) %arg, ptr 
addrspace(1) %arg1) {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %bb
+; CHECK-NEXT:s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:s_add_u32 s0, s0, s17
+; CHECK-NEXT:s_addc_u32 s1, s1, 0
+; CHECK-NEXT:s_add_u32 s8, s8, 16
+; CHECK-NEXT:s_addc_u32 s9, s9, 0
+; CHECK-NEXT:s_mov_b32 s13, s15
+; CHECK-NEXT:s_mov_b32 s12, s14
+; CHECK-NEXT:s_getpc_b64 s[18:19]
+; CHECK-NEXT:s_add_u32 s18, s18, eggs@rel32@lo+4
+; CHECK-NEXT:s_addc_u32 s19, s19, eggs@rel32@hi+12
+; CHECK-NEXT:s_mov_b32 s14, s16
+; CHECK-NEXT:v_mov_b32_e32 v31, v0
+; CHECK-NEXT:v_mov_b32_e32 v1, 0
+; CHECK-NEXT:s_mov_b32 s32, 0
+; CHECK-NEXT:s_swappc_b64 s[30:31], s[18:19]
+; CHECK-NEXT:buffer_load_dword v2, off, s[0:3], 0
+; CHECK-NEXT:buffer_load_dword v3, off, s[0:3], 0 offset:4
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:flat_store_dwordx2 v[2:3], v[0:1]
+; CHECK-NEXT:s_endpgm
 bb:
   %tmp = addrspacecast ptr addrspace(5) null to ptr
   %tmp2 = call i64 @eggs(ptr poison) #1
   %tmp3 = load ptr, ptr %tmp, align 8
-  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 undef
+  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 0
   store i64 %tmp2, ptr %tmp4, align 8
   ret void
 }

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[llvm-branch-commits] [llvm] AMDGPU: Switch a test to generated checks which only tested labels (PR #131257)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131257

>From 77fef8e3337bd6ccbce04c38de4365eb155d4172 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 14 Mar 2025 08:41:22 +0700
Subject: [PATCH] AMDGPU: Switch a test to generated checks which only tested
 labels

Also remove an undef use
---
 llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll | 53 +---
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll 
b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
index d198ec28f1602..21d4bcfcdc8c1 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
@@ -1,16 +1,58 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck 
%s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck 
%s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
-; CHECK-LABEL: {{^}}main:
-;
 ; Test for compilation only. This generated an invalid machine instruction
 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
+; GFX6-LABEL: main:
+; GFX6:   ; %bb.0: ; %main_body
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %IF57
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf0
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %IF60
+; GFX6-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX6-NEXT:s_buffer_load_dword s0, s[0:3], 0xf4
+; GFX6-NEXT:s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX6-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX6-NEXT:s_branch .LBB0_7
+; GFX6-NEXT:  .LBB0_6: ; %IF63
+; GFX6-NEXT:  .LBB0_7:
+;
+; GFX8-LABEL: main:
+; GFX8:   ; %bb.0: ; %main_body
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %IF57
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3c0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %IF60
+; GFX8-NEXT:v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX8-NEXT:s_buffer_load_dword s0, s[0:3], 0x3d0
+; GFX8-NEXT:s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:s_cbranch_scc0 .LBB0_6
+; GFX8-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX8-NEXT:s_branch .LBB0_7
+; GFX8-NEXT:  .LBB0_6: ; %IF63
+; GFX8-NEXT:  .LBB0_7:
 main_body:
   %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, 
i32 0)
   %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, 
i32 0)
-  br i1 undef, label %ENDIF56, label %IF57
+  br i1 poison, label %ENDIF56, label %IF57
 
 IF57: ; preds = %ENDIF
   %v.1 = mul i32 %v, 2
@@ -40,7 +82,6 @@ ENDIF62:  ; preds = 
%ENDIF59
   ret float %r
 }
 
-; Function Attrs: nounwind readnone
 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
 
 attributes #0 = { nounwind readnone }

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[llvm-branch-commits] [llvm] AMDGPU: Remove undef in subreg-coalescer-crash.ll (PR #131256)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131256

>From 5202d325afa9704a5b18e37353a410d9079855a4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:35:11 +0700
Subject: [PATCH] AMDGPU: Remove undef in subreg-coalescer-crash.ll

---
 .../CodeGen/AMDGPU/subreg-coalescer-crash.ll  | 32 +++
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll 
b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index a0ac6c1b28449..a69ee2e1a8b5c 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -9,17 +9,19 @@ define amdgpu_kernel void @row_filter_C1_D0() #0 {
 ; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
 ; GCN-NEXT:  .LBB0_2: ; %for.inc.1
 entry:
-  br i1 undef, label %for.inc.1, label %do.body.preheader
+  br i1 poison, label %for.inc.1, label %do.body.preheader
 
 do.body.preheader:; preds = %entry
   %tmp = insertelement <4 x i32> zeroinitializer, i32 poison, i32 1
-  br i1 undef, label %do.body56.1, label %do.body90
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %do.body56.1, label %do.body90
 
 do.body90:; preds = %do.body56.2, 
%do.body56.1, %do.body.preheader
   %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ 
%tmp, %do.body.preheader ]
   %tmp2 = insertelement <4 x i32> %tmp1, i32 poison, i32 2
   %tmp3 = insertelement <4 x i32> %tmp2, i32 poison, i32 3
-  br i1 undef, label %do.body124.1, label %do.body.1562.preheader
+  %undef3 = freeze i1 poison
+  br i1 %undef3, label %do.body124.1, label %do.body.1562.preheader
 
 do.body.1562.preheader:   ; preds = %do.body124.1, 
%do.body90
   %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
@@ -28,7 +30,7 @@ do.body.1562.preheader:   ; preds = 
%do.body124.1, %do.b
 
 do.body56.1:  ; preds = %do.body.preheader
   %tmp5 = insertelement <4 x i32> %tmp, i32 poison, i32 1
-  %or.cond472.1 = or i1 undef, undef
+  %or.cond472.1 = or i1 poison, poison
   br i1 %or.cond472.1, label %do.body56.2, label %do.body90
 
 do.body56.2:  ; preds = %do.body56.1
@@ -41,7 +43,8 @@ do.body124.1: ; preds = 
%do.body90
 
 for.inc.1:; preds = 
%do.body.1562.preheader, %entry
   %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, 
%do.body.1562.preheader ]
-  %add.i495 = add <4 x i32> %storemerge591, undef
+  %undef2 = freeze <4 x i32> poison
+  %add.i495 = add <4 x i32> %storemerge591, %undef2
   unreachable
 }
 
@@ -68,24 +71,27 @@ define amdgpu_ps void @foo() #0 {
 ; GCN-NEXT:exp mrt0 v1, v0, v0, v0 done vm
 ; GCN-NEXT:s_endpgm
 bb:
-  br i1 undef, label %bb2, label %bb1
+  %undef0 = freeze i1 poison
+  br i1 %undef0, label %bb2, label %bb1
 
 bb1:  ; preds = %bb
-  br i1 undef, label %bb4, label %bb6
+  %undef1 = freeze i1 poison
+  br i1 %undef1, label %bb4, label %bb6
 
 bb2:  ; preds = %bb4, %bb
   %tmp = phi float [ %tmp5, %bb4 ], [ 0.00e+00, %bb ]
-  br i1 undef, label %bb9, label %bb13
+  br i1 poison, label %bb9, label %bb13
 
 bb4:  ; preds = %bb7, %bb6, %bb1
   %tmp5 = phi float [ poison, %bb1 ], [ poison, %bb6 ], [ %tmp8, %bb7 ]
   br label %bb2
 
 bb6:  ; preds = %bb1
-  br i1 undef, label %bb7, label %bb4
+  %undef2 = freeze i1 poison
+  br i1 %undef2, label %bb7, label %bb4
 
 bb7:  ; preds = %bb6
-  %tmp8 = fmul float undef, undef
+  %tmp8 = fmul float poison, poison
   br label %bb4
 
 bb9:  ; preds = %bb2
@@ -95,7 +101,7 @@ bb9:  ; preds = 
%bb2
   br label %bb14
 
 bb13: ; preds = %bb2
-  br i1 undef, label %bb23, label %bb24
+  br i1 poison, label %bb23, label %bb24
 
 bb14: ; preds = %bb27, %bb24, %bb9
   %tmp15 = phi float [ %tmp12, %bb9 ], [ poison, %bb27 ], [ 0.00e+00, 
%bb24 ]
@@ -106,11 +112,11 @@ bb14: ; preds 
= %bb27, %bb24, %bb9
   ret void
 
 bb23: ; preds = %bb13
-  br i1 undef, label %bb24, label %bb26
+  br i1 poison, label %bb24, label %bb26
 
 bb24: ; preds = %bb26, %bb23, %bb13
   %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.00e+00, %bb23 ]
-  br i1 undef, label %bb27, label %bb14
+  br i1 poison, label %bb27, label %bb14
 
 bb26:  

[llvm-branch-commits] [llvm] AMDGPU: Replace some test i32 undef uses with poison (PR #131092)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap edited 
https://github.com/llvm/llvm-project/pull/131092
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[llvm-branch-commits] [llvm] AMDGPU: Fix broken negative test from ancient times (PR #131106)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131106

>From d96b1dffd5e7ec3b1d8552fdd34ff596fd9a7f2e Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:05:26 +0700
Subject: [PATCH] AMDGPU: Fix broken negative test from ancient times

Before the dawn of civilization, instructions were printed in all
caps using the raw tablegen pseudo-names. This -NOT check was looking
for that, instead of the actual ISA output. Just switch to using generated
checks. Also replace a use of undef.
---
 .../dead-machine-elim-after-dead-lane.ll   | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll 
b/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
index 9ce0235fdcb18..d616fecfdc1ff 100644
--- a/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
+++ b/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
@@ -1,12 +1,22 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
 
-; CHECK-LABEL: foo
-; CHECK-NOT: BUFFER_LOAD_DWORDX2_OFFSET
 ; After dead code elimination, that buffer load should be eliminated finally
 ; after dead lane detection.
 define amdgpu_kernel void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:s_cbranch_execnz .LBB0_2
+; CHECK-NEXT:  ; %bb.1: ; %LeafBlock1
+; CHECK-NEXT:  .LBB0_2: ; %foo.exit
+; CHECK-NEXT:s_mov_b32 s3, 0xf000
+; CHECK-NEXT:s_mov_b32 s2, -1
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:buffer_store_dword v0, off, s[0:3], 0
+; CHECK-NEXT:s_endpgm
+; CHECK-NEXT:  ; %bb.3: ; %sw.bb10
 entry:
-  switch i8 undef, label %foo.exit [
+  switch i8 poison, label %foo.exit [
 i8 4, label %sw.bb4
 i8 10, label %sw.bb10
   ]

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[llvm-branch-commits] [llvm] AMDGPU: Fix broken negative test from ancient times (PR #131106)

[Pravin Jagtap via llvm-branch-commits]

@@ -1,12 +1,22 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
 
-; CHECK-LABEL: foo
-; CHECK-NOT: BUFFER_LOAD_DWORDX2_OFFSET
 ; After dead code elimination, that buffer load should be eliminated finally
 ; after dead lane detection.
 define amdgpu_kernel void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:s_cbranch_execnz .LBB0_2
+; CHECK-NEXT:  ; %bb.1: ; %LeafBlock1
+; CHECK-NEXT:  .LBB0_2: ; %foo.exit
+; CHECK-NEXT:s_mov_b32 s3, 0xf000
+; CHECK-NEXT:s_mov_b32 s2, -1
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:buffer_store_dword v0, off, s[0:3], 0
+; CHECK-NEXT:s_endpgm
+; CHECK-NEXT:  ; %bb.3: ; %sw.bb10
 entry:
-  switch i8 undef, label %foo.exit [
+  switch i8 poison, label %foo.exit [

pravinjagtap wrote:

In one of the prev. PR github actions suggested following:

In tests, avoid using undef and having tests that trigger undefined behavior. 
If you need an operand with some unimportant value, you can add a new argument 
to the function and use that instead.


https://github.com/llvm/llvm-project/pull/131106
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test undef uses with poison (PR #131103)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131103
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test undef uses with poison (PR #131103)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap edited 
https://github.com/llvm/llvm-project/pull/131103
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[llvm-branch-commits] [llvm] AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (PR #131101)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131101
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[llvm-branch-commits] [llvm] AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (PR #131095)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131095
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[llvm-branch-commits] [llvm] AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (PR #131101)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap edited 
https://github.com/llvm/llvm-project/pull/131101
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[llvm-branch-commits] [llvm] AMDGPU: Use generated checks in test missing checks (PR #131110)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap edited 
https://github.com/llvm/llvm-project/pull/131110
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[llvm-branch-commits] [llvm] AMDGPU: Use generated checks in test missing checks (PR #131110)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131110
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[llvm-branch-commits] [clang] [Clang driver] Diagnose `-maix-shared-lib-tls-model-opt` on wrong targets (PR #130865)

[David Tenty via llvm-branch-commits]

https://github.com/daltenty approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/130865
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[llvm-branch-commits] [llvm] AMDGPU: Use generated checks in test missing checks (PR #131110)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131110

>From c456233f87c3cbed80298649463abddf3e78df7d Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:14:29 +0700
Subject: [PATCH] AMDGPU: Use generated checks in test missing checks

---
 .../CodeGen/AMDGPU/mdt-preserving-crash.ll| 68 ++-
 1 file changed, 65 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll 
b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
index ef1cbd78d7cd7..50cc8065718a2 100644
--- a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
@@ -1,10 +1,72 @@
-; RUN: llc < %s
-target datalayout = 
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
-target triple = "amdgcn-amd-amdhsa"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 @_RSENC_gDcd___ = external protected addrspace(1) 
externally_initialized global [4096 x i8], align 16
 
 define protected amdgpu_kernel void 
@_RSENC_PRInit__(i1 %c0) local_unnamed_addr #0 {
+; CHECK-LABEL: _RSENC_PRInit__:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:flat_load_dword v0, v[0:1]
+; CHECK-NEXT:s_add_u32 s0, s0, s17
+; CHECK-NEXT:s_mov_b32 s4, 0xf19b3
+; CHECK-NEXT:s_addc_u32 s1, s1, 0
+; CHECK-NEXT:s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:v_lshl_add_u32 v0, v0, 1, v0
+; CHECK-NEXT:v_cmp_ne_u32_e32 vcc, s4, v0
+; CHECK-NEXT:s_and_saveexec_b64 s[4:5], vcc
+; CHECK-NEXT:s_cbranch_execz .LBB0_12
+; CHECK-NEXT:  ; %bb.1: ; %if.end15
+; CHECK-NEXT:s_load_dword s4, s[8:9], 0x0
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:s_bitcmp1_b32 s4, 0
+; CHECK-NEXT:s_cselect_b64 s[4:5], -1, 0
+; CHECK-NEXT:s_and_b64 vcc, exec, s[4:5]
+; CHECK-NEXT:s_cbranch_vccnz .LBB0_12
+; CHECK-NEXT:  .LBB0_2: ; %while.cond.i
+; CHECK-NEXT:; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:s_cbranch_scc1 .LBB0_2
+; CHECK-NEXT:  ; %bb.3: ; %if.end60
+; CHECK-NEXT:s_mov_b64 vcc, exec
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.4: ; %if.end5.i
+; CHECK-NEXT:s_mov_b64 vcc, vcc
+; CHECK-NEXT:s_cbranch_vccz .LBB0_11
+; CHECK-NEXT:  ; %bb.5: ; %if.end5.i314
+; CHECK-NEXT:s_mov_b64 vcc, exec
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.6: ; %if.end5.i338
+; CHECK-NEXT:s_mov_b64 vcc, vcc
+; CHECK-NEXT:s_cbranch_vccz .LBB0_11
+; CHECK-NEXT:  ; %bb.7: ; %if.end5.i362
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:s_getpc_b64 s[4:5]
+; CHECK-NEXT:s_add_u32 s4, s4, 
_RSENC_gDcd___@rel32@lo+1157
+; CHECK-NEXT:s_addc_u32 s5, s5, 
_RSENC_gDcd___@rel32@hi+1165
+; CHECK-NEXT:global_load_ubyte v1, v0, s[4:5]
+; CHECK-NEXT:s_nop 0
+; CHECK-NEXT:buffer_store_byte v0, v0, s[0:3], 0 offen
+; CHECK-NEXT:s_waitcnt vmcnt(1)
+; CHECK-NEXT:buffer_store_byte v1, off, s[0:3], 0 offset:257
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.8: ; %if.end5.i400
+; CHECK-NEXT:flat_load_ubyte v0, v[0:1]
+; CHECK-NEXT:s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:v_cmp_eq_u16_e32 vcc, 0, v0
+; CHECK-NEXT:s_and_b64 exec, exec, vcc
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.9: ; %if.then404
+; CHECK-NEXT:s_movk_i32 s4, 0x1000
+; CHECK-NEXT:  .LBB0_10: ; %for.body564
+; CHECK-NEXT:; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:s_sub_i32 s4, s4, 32
+; CHECK-NEXT:s_cmp_lg_u32 s4, 0
+; CHECK-NEXT:s_cbranch_scc1 .LBB0_10
+; CHECK-NEXT:  .LBB0_11: ; %UnifiedUnreachableBlock
+; CHECK-NEXT:; divergent unreachable
+; CHECK-NEXT:  .LBB0_12: ; %UnifiedReturnBlock
+; CHECK-NEXT:s_endpgm
 entry:
   %runtimeVersionCopy = alloca [128 x i8], align 16, addrspace(5)
   %licenseVersionCopy = alloca [128 x i8], align 16, addrspace(5)

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[llvm-branch-commits] [llvm] AMDGPU: Make fma_legacy intrinsic propagate poison (PR #131063)

[Pierre van Houtryve via llvm-branch-commits]

https://github.com/Pierre-vh approved this pull request.


https://github.com/llvm/llvm-project/pull/131063
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test undef uses with poison (PR #131103)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131103

>From 1b2dc4629c9348d64d98d0d187600082587d8a89 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 15:07:57 +0700
Subject: [PATCH] AMDGPU: Replace some test undef uses with poison

---
 .../GlobalISel/call-outgoing-stack-args.ll |  4 ++--
 .../GlobalISel/divergent-control-flow.ll   |  2 +-
 .../CodeGen/AMDGPU/diverge-interp-mov-lower.ll |  2 +-
 llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll |  2 +-
 .../CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll | 18 +-
 llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll |  2 +-
 .../test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll | 10 +-
 llvm/test/CodeGen/AMDGPU/ret_jump.ll   |  4 ++--
 llvm/test/CodeGen/AMDGPU/sgpr-copy.ll  |  4 ++--
 llvm/test/CodeGen/AMDGPU/split-smrd.ll |  2 +-
 llvm/test/CodeGen/AMDGPU/v1024.ll  |  4 ++--
 llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll |  2 +-
 llvm/test/CodeGen/AMDGPU/wqm.ll|  4 ++--
 13 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
index c99424fe2f7d9..7adaddf2fc8ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
@@ -53,7 +53,7 @@ define amdgpu_kernel void @kernel_caller_stack() {
 ; FLATSCR-NEXT:scratch_store_dword off, v0, s2
 ; FLATSCR-NEXT:s_swappc_b64 s[30:31], s[0:1]
 ; FLATSCR-NEXT:s_endpgm
-  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> undef, <16 x 
i32> undef, <4 x i32> )
+  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> poison, <16 x 
i32> poison, <4 x i32> )
   ret void
 }
 
@@ -294,7 +294,7 @@ define void @func_caller_stack() {
 ; FLATSCR-NEXT:s_mov_b32 s33, s0
 ; FLATSCR-NEXT:s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:s_setpc_b64 s[30:31]
-  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> undef, <16 x 
i32> undef, <4 x i32> )
+  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> poison, <16 x 
i32> poison, <4 x i32> )
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index 989ee80a1f002..9efed32bbe082 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -231,7 +231,7 @@ bb:
   br label %bb1
 
 bb1:
-  %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
+  %lsr.iv = phi i32 [ poison, %bb ], [ %lsr.iv.next, %bb4 ]
   %lsr.iv.next = add i32 %lsr.iv, 1
   %cmp0 = icmp slt i32 %lsr.iv.next, 0
   br i1 %cmp0, label %bb4, label %bb9
diff --git a/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll 
b/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
index c923991f5cfcb..e03be90a22d3c 100644
--- a/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
+++ b/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
@@ -21,7 +21,7 @@ define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg 
%arg) local_unnamed_a
   %tmp6 = load <4 x float>, ptr addrspace(4) %tmp5, align 16
   %tmp7 = extractelement <4 x float> %tmp6, i32 3
   %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7) #1
-  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x 
half> %tmp8, i1 true, i1 true) #2
+  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> poison, <2 
x half> %tmp8, i1 true, i1 true) #2
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
index 235d8dde96658..b86ad8f2e4476 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
@@ -29,7 +29,7 @@ entry:
 ; OPT: s_endpgm
 define amdgpu_kernel void @only_undef_dbg_value() #1 {
 bb:
-  call void @llvm.dbg.value(metadata <4 x float> undef, metadata !10, metadata 
!DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !14
+  call void @llvm.dbg.value(metadata <4 x float> poison, metadata !10, 
metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !14
   ret void, !dbg !14
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll 
b/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
index f86891d174468..1c032857f2688 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
@@ -33,7 +33,7 @@ bb:
 define amdgpu_kernel void @test_mfma_f32_16x16x2bf16(ptr addrspace(1) %arg) #0 
{
 bb:
   %in.1 = load <16 x float>, ptr addrspace(1) %arg
-  %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x2bf16(<2 x i16> 
undef, <2 x i16> undef, <16 x float> %in.1, i32 0, i32 0, i32 0)
+  %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32

[llvm-branch-commits] [llvm] AMDGPU: Make fmul_legacy intrinsic propagate poison (PR #131062)

[Pierre van Houtryve via llvm-branch-commits]

https://github.com/Pierre-vh approved this pull request.


https://github.com/llvm/llvm-project/pull/131062
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[llvm-branch-commits] [llvm] AMDGPU: Replace i16 undefs with poison in tests (PR #131084)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131084
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test i32 undef uses with poison (PR #131092)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm ready_for_review 
https://github.com/llvm/llvm-project/pull/131092
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test i32 undef uses with poison (PR #131092)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

### Merge activity

* **Mar 13, 9:03 AM EDT**: A user started a stack merge that includes this pull 
request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131092).


https://github.com/llvm/llvm-project/pull/131092
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[llvm-branch-commits] [llvm] AMDGPU: Fix broken negative test from ancient times (PR #131106)

[Matt Arsenault via llvm-branch-commits]

@@ -1,12 +1,22 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
 
-; CHECK-LABEL: foo
-; CHECK-NOT: BUFFER_LOAD_DWORDX2_OFFSET
 ; After dead code elimination, that buffer load should be eliminated finally
 ; after dead lane detection.
 define amdgpu_kernel void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:s_cbranch_execnz .LBB0_2
+; CHECK-NEXT:  ; %bb.1: ; %LeafBlock1
+; CHECK-NEXT:  .LBB0_2: ; %foo.exit
+; CHECK-NEXT:s_mov_b32 s3, 0xf000
+; CHECK-NEXT:s_mov_b32 s2, -1
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:buffer_store_dword v0, off, s[0:3], 0
+; CHECK-NEXT:s_endpgm
+; CHECK-NEXT:  ; %bb.3: ; %sw.bb10
 entry:
-  switch i8 undef, label %foo.exit [
+  switch i8 poison, label %foo.exit [

arsenm wrote:

The bot is very overzealous and has no contextual understanding. This test 
needs to preserve the codegen output as exactly as possible, regardless of how 
well defined the program is 

https://github.com/llvm/llvm-project/pull/131106
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[llvm-branch-commits] [llvm] AMDGPU: Fix broken negative test from ancient times (PR #131106)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm ready_for_review 
https://github.com/llvm/llvm-project/pull/131106
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[llvm-branch-commits] [llvm] [SeparateConstOffsetFromGEP] Preserve inbounds flag based on ValueTracking (PR #130617)

[Fabian Ritter via llvm-branch-commits]

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/130617

>From c957d905bea1d664564a08dbca0909b905920a8c Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Mon, 10 Mar 2025 06:55:10 -0400
Subject: [PATCH 1/2] [SeparateConstOffsetFromGEP] Preserve inbounds flag based
 on ValueTracking

If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the new GEPs are inbounds.

For SWDEV-516125.
---
 .../Scalar/SeparateConstOffsetFromGEP.cpp | 18 +++
 .../AMDGPU/preserve-inbounds.ll   | 23 +++
 .../NVPTX/split-gep-and-gvn.ll| 16 ++---
 .../NVPTX/split-gep.ll|  8 +++
 4 files changed, 48 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp 
b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
index ab8e979e7b40a..7f93115499bc9 100644
--- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
@@ -1052,6 +1052,8 @@ bool 
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
 }
   }
 
+  bool MayRecoverInbounds = AccumulativeByteOffset >= 0 && GEP->isInBounds();
+
   // Remove the constant offset in each sequential index. The resultant GEP
   // computes the variadic base.
   // Notice that we don't remove struct field indices here. If LowerGEP is
@@ -1079,6 +1081,8 @@ bool 
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
 // and the old index if they are not used.
 RecursivelyDeleteTriviallyDeadInstructions(UserChainTail);
 RecursivelyDeleteTriviallyDeadInstructions(OldIdx);
+MayRecoverInbounds =
+MayRecoverInbounds && computeKnownBits(NewIdx, 
*DL).isNonNegative();
   }
 }
   }
@@ -1100,11 +1104,15 @@ bool 
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
   // address with silently-wrapping two's complement arithmetic".
   // Therefore, the final code will be a semantically equivalent.
   //
-  // TODO(jingyue): do some range analysis to keep as many inbounds as
-  // possible. GEPs with inbounds are more friendly to alias analysis.
-  // TODO(gep_nowrap): Preserve nuw at least.
-  GEPNoWrapFlags NewGEPFlags = GEPNoWrapFlags::none();
-  GEP->setNoWrapFlags(GEPNoWrapFlags::none());
+  // If the initial GEP was inbounds and all variable indices and the
+  // accumulated offsets are non-negative, they can be added in any order and
+  // the intermediate results are in bounds. So, we can preserve the inbounds
+  // flag for both GEPs. GEPs with inbounds are more friendly to alias 
analysis.
+  //
+  // TODO(gep_nowrap): Preserve nuw?
+  GEPNoWrapFlags NewGEPFlags =
+  MayRecoverInbounds ? GEPNoWrapFlags::inBounds() : GEPNoWrapFlags::none();
+  GEP->setNoWrapFlags(NewGEPFlags);
 
   // Lowers a GEP to either GEPs with a single index or arithmetic operations.
   if (LowerGEP) {
diff --git 
a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll 
b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
index 422e5d8215502..01619aa481ddd 100644
--- 
a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
+++ 
b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
@@ -16,3 +16,26 @@ entry:
   %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx
   ret ptr %arrayidx
 }
+
+; All offsets must be positive, so inbounds can be preserved.
+define void @must_be_inbounds(ptr %dst, ptr %src, i32 %i) {
+; CHECK-LABEL: @must_be_inbounds(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[I_PROM:%.*]] = zext i32 [[I:%.*]] to i64
+; CHECK-NEXT:[[TMP0:%.*]] = getelementptr inbounds float, ptr [[SRC:%.*]], 
i64 [[I_PROM]]
+; CHECK-NEXT:[[ARRAYIDX_SRC2:%.*]] = getelementptr inbounds i8, ptr 
[[TMP0]], i64 4
+; CHECK-NEXT:[[TMP1:%.*]] = load float, ptr [[ARRAYIDX_SRC2]], align 4
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds float, ptr [[DST:%.*]], 
i64 [[I_PROM]]
+; CHECK-NEXT:[[ARRAYIDX_DST4:%.*]] = getelementptr inbounds i8, ptr 
[[TMP2]], i64 4
+; CHECK-NEXT:store float [[TMP1]], ptr [[ARRAYIDX_DST4]], align 4
+; CHECK-NEXT:ret void
+;
+entry:
+  %i.prom = zext i32 %i to i64
+  %idx = add nsw i64 %i.prom, 1
+  %arrayidx.src = getelementptr inbounds float, ptr %src, i64 %idx
+  %3 = load float, ptr %arrayidx.src, align 4
+  %arrayidx.dst = getelementptr inbounds float, ptr %dst, i64 %idx
+  store float %3, ptr %arrayidx.dst, align 4
+  ret void
+}
diff --git 
a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll 
b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
index 9a73feb2c4b5c..4474585bf9b06 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/

[llvm-branch-commits] [llvm] [SeparateConstOffsetFromGEP] Preserve inbounds flag based on ValueTracking (PR #130617)

[Fabian Ritter via llvm-branch-commits]

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/130617

>From c957d905bea1d664564a08dbca0909b905920a8c Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Mon, 10 Mar 2025 06:55:10 -0400
Subject: [PATCH 1/2] [SeparateConstOffsetFromGEP] Preserve inbounds flag based
 on ValueTracking

If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the new GEPs are inbounds.

For SWDEV-516125.
---
 .../Scalar/SeparateConstOffsetFromGEP.cpp | 18 +++
 .../AMDGPU/preserve-inbounds.ll   | 23 +++
 .../NVPTX/split-gep-and-gvn.ll| 16 ++---
 .../NVPTX/split-gep.ll|  8 +++
 4 files changed, 48 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp 
b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
index ab8e979e7b40a..7f93115499bc9 100644
--- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
@@ -1052,6 +1052,8 @@ bool 
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
 }
   }
 
+  bool MayRecoverInbounds = AccumulativeByteOffset >= 0 && GEP->isInBounds();
+
   // Remove the constant offset in each sequential index. The resultant GEP
   // computes the variadic base.
   // Notice that we don't remove struct field indices here. If LowerGEP is
@@ -1079,6 +1081,8 @@ bool 
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
 // and the old index if they are not used.
 RecursivelyDeleteTriviallyDeadInstructions(UserChainTail);
 RecursivelyDeleteTriviallyDeadInstructions(OldIdx);
+MayRecoverInbounds =
+MayRecoverInbounds && computeKnownBits(NewIdx, 
*DL).isNonNegative();
   }
 }
   }
@@ -1100,11 +1104,15 @@ bool 
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
   // address with silently-wrapping two's complement arithmetic".
   // Therefore, the final code will be a semantically equivalent.
   //
-  // TODO(jingyue): do some range analysis to keep as many inbounds as
-  // possible. GEPs with inbounds are more friendly to alias analysis.
-  // TODO(gep_nowrap): Preserve nuw at least.
-  GEPNoWrapFlags NewGEPFlags = GEPNoWrapFlags::none();
-  GEP->setNoWrapFlags(GEPNoWrapFlags::none());
+  // If the initial GEP was inbounds and all variable indices and the
+  // accumulated offsets are non-negative, they can be added in any order and
+  // the intermediate results are in bounds. So, we can preserve the inbounds
+  // flag for both GEPs. GEPs with inbounds are more friendly to alias 
analysis.
+  //
+  // TODO(gep_nowrap): Preserve nuw?
+  GEPNoWrapFlags NewGEPFlags =
+  MayRecoverInbounds ? GEPNoWrapFlags::inBounds() : GEPNoWrapFlags::none();
+  GEP->setNoWrapFlags(NewGEPFlags);
 
   // Lowers a GEP to either GEPs with a single index or arithmetic operations.
   if (LowerGEP) {
diff --git 
a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll 
b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
index 422e5d8215502..01619aa481ddd 100644
--- 
a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
+++ 
b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
@@ -16,3 +16,26 @@ entry:
   %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx
   ret ptr %arrayidx
 }
+
+; All offsets must be positive, so inbounds can be preserved.
+define void @must_be_inbounds(ptr %dst, ptr %src, i32 %i) {
+; CHECK-LABEL: @must_be_inbounds(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[I_PROM:%.*]] = zext i32 [[I:%.*]] to i64
+; CHECK-NEXT:[[TMP0:%.*]] = getelementptr inbounds float, ptr [[SRC:%.*]], 
i64 [[I_PROM]]
+; CHECK-NEXT:[[ARRAYIDX_SRC2:%.*]] = getelementptr inbounds i8, ptr 
[[TMP0]], i64 4
+; CHECK-NEXT:[[TMP1:%.*]] = load float, ptr [[ARRAYIDX_SRC2]], align 4
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds float, ptr [[DST:%.*]], 
i64 [[I_PROM]]
+; CHECK-NEXT:[[ARRAYIDX_DST4:%.*]] = getelementptr inbounds i8, ptr 
[[TMP2]], i64 4
+; CHECK-NEXT:store float [[TMP1]], ptr [[ARRAYIDX_DST4]], align 4
+; CHECK-NEXT:ret void
+;
+entry:
+  %i.prom = zext i32 %i to i64
+  %idx = add nsw i64 %i.prom, 1
+  %arrayidx.src = getelementptr inbounds float, ptr %src, i64 %idx
+  %3 = load float, ptr %arrayidx.src, align 4
+  %arrayidx.dst = getelementptr inbounds float, ptr %dst, i64 %idx
+  store float %3, ptr %arrayidx.dst, align 4
+  ret void
+}
diff --git 
a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll 
b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
index 9a73feb2c4b5c..4474585bf9b06 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/

[llvm-branch-commits] [llvm] AMDGPU: Replace more undef test pointer uses with poison (PR #131102)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131102
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[llvm-branch-commits] [flang] [flang][OpenMP] Use OmpDirectiveSpecification in standalone directives (PR #131163)

[Krzysztof Parzyszek via llvm-branch-commits]

https://github.com/kparzysz created 
https://github.com/llvm/llvm-project/pull/131163

This uses OmpDirectiveSpecification in the rest of the standalone directives.

>From 01dd3f55995e507ddee61e80e3eb29e35f722c0f Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek 
Date: Mon, 10 Mar 2025 15:42:42 -0500
Subject: [PATCH] [flang][OpenMP] Use OmpDirectiveSpecification in standalone
 directives

This uses OmpDirectiveSpecification in the rest of the standalone
directives.
---
 flang/include/flang/Parser/dump-parse-tree.h  |   1 +
 flang/include/flang/Parser/parse-tree.h   |  23 ++--
 flang/lib/Lower/OpenMP/Clauses.cpp|  19 +++
 flang/lib/Lower/OpenMP/Clauses.h  |   3 +
 flang/lib/Lower/OpenMP/OpenMP.cpp |  31 ++---
 flang/lib/Parser/openmp-parsers.cpp   |  74 ++-
 flang/lib/Parser/parse-tree.cpp   |   8 ++
 flang/lib/Parser/unparse.cpp  |  30 ++---
 flang/lib/Semantics/check-omp-structure.cpp   | 125 +-
 flang/lib/Semantics/check-omp-structure.h |   3 +-
 flang/lib/Semantics/resolve-directives.cpp|   9 +-
 flang/lib/Semantics/resolve-names.cpp |   6 +-
 flang/test/Parser/OpenMP/depobj-construct.f90 |  32 ++---
 .../Parser/OpenMP/metadirective-dirspec.f90   |  18 +--
 .../Parser/OpenMP/metadirective-flush.f90 |   4 +-
 .../Semantics/OpenMP/depobj-construct-v50.f90 |  17 +++
 16 files changed, 257 insertions(+), 146 deletions(-)

diff --git a/flang/include/flang/Parser/dump-parse-tree.h 
b/flang/include/flang/Parser/dump-parse-tree.h
index 118df6cf2a4ff..9bff2dab974ec 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -484,6 +484,7 @@ class ParseTreeDumper {
   NODE(parser, OmpLocatorList)
   NODE(parser, OmpReductionSpecifier)
   NODE(parser, OmpArgument)
+  NODE(parser, OmpArgumentList)
   NODE(parser, OmpMetadirectiveDirective)
   NODE(parser, OmpMatchClause)
   NODE(parser, OmpOtherwiseClause)
diff --git a/flang/include/flang/Parser/parse-tree.h 
b/flang/include/flang/Parser/parse-tree.h
index dfde4ceb787d2..a31018c9abc09 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3557,6 +3557,11 @@ struct OmpArgument {
   OmpMapperSpecifier, OmpReductionSpecifier>
   u;
 };
+
+struct OmpArgumentList {
+  WRAPPER_CLASS_BOILERPLATE(OmpArgumentList, std::list);
+  CharBlock source;
+};
 } // namespace arguments
 
 inline namespace traits {
@@ -4511,10 +4516,11 @@ struct OmpDirectiveSpecification {
   llvm::omp::Directive DirId() const { //
 return std::get(t).v;
   }
+  const OmpArgumentList &Arguments() const;
   const OmpClauseList &Clauses() const;
 
   CharBlock source;
-  std::tuple>,
+  std::tuple,
   std::optional, Flags>
   t;
 };
@@ -4865,16 +4871,15 @@ struct OmpLoopDirective {
 
 // 2.14.2 cancellation-point -> CANCELLATION POINT construct-type-clause
 struct OpenMPCancellationPointConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPCancellationPointConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPCancellationPointConstruct,
+  OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // 2.14.1 cancel -> CANCEL construct-type-clause [ [,] if-clause]
 struct OpenMPCancelConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPCancelConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPCancelConstruct, OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // Ref: [5.0:254-255], [5.1:287-288], [5.2:322-323]
@@ -4884,9 +4889,8 @@ struct OpenMPCancelConstruct {
 //  destroy-clause |
 //  update-clause
 struct OpenMPDepobjConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPDepobjConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPDepobjConstruct, OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // Ref: [5.2: 200-201]
@@ -4927,11 +4931,8 @@ struct OpenMPDispatchConstruct {
 //ACQ_REL | RELEASE | ACQUIRE | // since 5.0
 //SEQ_CST   // since 5.1
 struct OpenMPFlushConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPFlushConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPFlushConstruct, OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple,
-  std::optional, /*TrailingClauses=*/bool>
-  t;
 };
 
 struct OpenMPSimpleStandaloneConstruct {
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp 
b/flang/lib/Lower/OpenMP/Clauses.cpp
index 9fa9abd9e8ceb..7ad6f7f3da00a 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -132,6 +132,25 @@ Object makeObject(const parser::OmpObject &object,
   return makeObject(std::get(object.u), semaCtx);
 }
 
+ObjectList makeObjects(const parser::OmpArgumentList &objects,
+   semantics::SemanticsContext &semaCtx) {
+  return makeList(objects.v, [&](const parser::OmpArgument &arg) {
+return common::visit(
+common::visitors{
+[&](const parser::OmpLocato

[llvm-branch-commits] [llvm] AMDGPU: Replace more undef test pointer uses with poison (PR #131102)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap edited 
https://github.com/llvm/llvm-project/pull/131102
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[llvm-branch-commits] [llvm] AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (PR #131095)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap edited 
https://github.com/llvm/llvm-project/pull/131095
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[llvm-branch-commits] [llvm] AMDGPU: Replace i16 undefs with poison in tests (PR #131084)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/131084.diff


2 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/inline-constraints.ll (+3-3) 
- (modified) llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll (+2-2) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll 
b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll
index 2888fd77a9b53..3aa6f3a43d2ee 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll
@@ -295,7 +295,7 @@ define i32 @inline_A_constraint_V1() {
 
 ; NOGCN: error: invalid operand for inline asm constraint 'A'
 define i32 @inline_A_constraint_V2() {
-  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x i16> )
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x i16> )
   ret i32 %v0
 }
 
@@ -456,7 +456,7 @@ define i32 @inline_I_constraint_V1() {
 
 ; NOGCN: error: invalid operand for inline asm constraint 'I'
 define i32 @inline_I_constraint_V2() {
-  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> )
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> )
   ret i32 %v0
 }
 
@@ -1160,7 +1160,7 @@ define i32 @inline_DA_constraint_V1() {
 
 ; NOGCN: error: invalid operand for inline asm constraint 'DA'
 define i32 @inline_DA_constraint_V2() {
-  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i16> )
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i16> )
   ret i32 %v0
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll 
b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
index fe45d7d0284bb..21aa40d69998e 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
@@ -4249,7 +4249,7 @@ define amdgpu_kernel void 
@v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out,
   %gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
   %gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 
%tid.ext
   %x = load <2 x i16>, ptr addrspace(1) %gep
-  %result = add <2 x i16> %x, 
+  %result = add <2 x i16> %x, 
   store <2 x i16> %result, ptr addrspace(1) %gep.out
   ret void
 }
@@ -4403,7 +4403,7 @@ define amdgpu_kernel void 
@v_test_v2i16_x_add_neg32_undef(ptr addrspace(1) %out,
   %gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
   %gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 
%tid.ext
   %x = load <2 x i16>, ptr addrspace(1) %gep
-  %result = add <2 x i16> %x, 
+  %result = add <2 x i16> %x, 
   store <2 x i16> %result, ptr addrspace(1) %gep.out
   ret void
 }

``




https://github.com/llvm/llvm-project/pull/131084
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[llvm-branch-commits] [llvm] release/20.x: [SystemZ] Move disabling of arg verification to before isFullyInternal(). (#130693) (PR #130998)

[Ulrich Weigand via llvm-branch-commits]

https://github.com/uweigand approved this pull request.


https://github.com/llvm/llvm-project/pull/130998
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[llvm-branch-commits] [llvm] AMDGPU: Replace some test undef uses with poison (PR #131103)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131103

>From b07ce09af4d3619c20a3e96be7eb497f4c8e22ad Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 15:07:57 +0700
Subject: [PATCH] AMDGPU: Replace some test undef uses with poison

---
 .../GlobalISel/call-outgoing-stack-args.ll |  4 ++--
 .../GlobalISel/divergent-control-flow.ll   |  2 +-
 .../CodeGen/AMDGPU/diverge-interp-mov-lower.ll |  2 +-
 llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll |  2 +-
 .../CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll | 18 +-
 llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll |  2 +-
 .../test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll | 10 +-
 llvm/test/CodeGen/AMDGPU/ret_jump.ll   |  4 ++--
 llvm/test/CodeGen/AMDGPU/sgpr-copy.ll  |  4 ++--
 llvm/test/CodeGen/AMDGPU/split-smrd.ll |  2 +-
 llvm/test/CodeGen/AMDGPU/v1024.ll  |  4 ++--
 llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll |  2 +-
 llvm/test/CodeGen/AMDGPU/wqm.ll|  4 ++--
 13 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
index c99424fe2f7d9..7adaddf2fc8ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
@@ -53,7 +53,7 @@ define amdgpu_kernel void @kernel_caller_stack() {
 ; FLATSCR-NEXT:scratch_store_dword off, v0, s2
 ; FLATSCR-NEXT:s_swappc_b64 s[30:31], s[0:1]
 ; FLATSCR-NEXT:s_endpgm
-  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> undef, <16 x 
i32> undef, <4 x i32> )
+  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> poison, <16 x 
i32> poison, <4 x i32> )
   ret void
 }
 
@@ -294,7 +294,7 @@ define void @func_caller_stack() {
 ; FLATSCR-NEXT:s_mov_b32 s33, s0
 ; FLATSCR-NEXT:s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:s_setpc_b64 s[30:31]
-  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> undef, <16 x 
i32> undef, <4 x i32> )
+  call void @external_void_func_v16i32_v16i32_v4i32(<16 x i32> poison, <16 x 
i32> poison, <4 x i32> )
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index 989ee80a1f002..9efed32bbe082 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -231,7 +231,7 @@ bb:
   br label %bb1
 
 bb1:
-  %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
+  %lsr.iv = phi i32 [ poison, %bb ], [ %lsr.iv.next, %bb4 ]
   %lsr.iv.next = add i32 %lsr.iv, 1
   %cmp0 = icmp slt i32 %lsr.iv.next, 0
   br i1 %cmp0, label %bb4, label %bb9
diff --git a/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll 
b/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
index c923991f5cfcb..e03be90a22d3c 100644
--- a/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
+++ b/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
@@ -21,7 +21,7 @@ define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg 
%arg) local_unnamed_a
   %tmp6 = load <4 x float>, ptr addrspace(4) %tmp5, align 16
   %tmp7 = extractelement <4 x float> %tmp6, i32 3
   %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7) #1
-  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x 
half> %tmp8, i1 true, i1 true) #2
+  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> poison, <2 
x half> %tmp8, i1 true, i1 true) #2
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
index 235d8dde96658..b86ad8f2e4476 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
@@ -29,7 +29,7 @@ entry:
 ; OPT: s_endpgm
 define amdgpu_kernel void @only_undef_dbg_value() #1 {
 bb:
-  call void @llvm.dbg.value(metadata <4 x float> undef, metadata !10, metadata 
!DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !14
+  call void @llvm.dbg.value(metadata <4 x float> poison, metadata !10, 
metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !14
   ret void, !dbg !14
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll 
b/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
index f86891d174468..1c032857f2688 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
@@ -33,7 +33,7 @@ bb:
 define amdgpu_kernel void @test_mfma_f32_16x16x2bf16(ptr addrspace(1) %arg) #0 
{
 bb:
   %in.1 = load <16 x float>, ptr addrspace(1) %arg
-  %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x2bf16(<2 x i16> 
undef, <2 x i16> undef, <16 x float> %in.1, i32 0, i32 0, i32 0)
+  %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32

[llvm-branch-commits] [llvm] AMDGPU: Use generated checks in test missing checks (PR #131110)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131110

>From 137161f1259bd9c09fd59ec360f8e5cd111c7a8e Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 16:14:29 +0700
Subject: [PATCH] AMDGPU: Use generated checks in test missing checks

---
 .../CodeGen/AMDGPU/mdt-preserving-crash.ll| 68 ++-
 1 file changed, 65 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll 
b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
index ef1cbd78d7cd7..50cc8065718a2 100644
--- a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
@@ -1,10 +1,72 @@
-; RUN: llc < %s
-target datalayout = 
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
-target triple = "amdgcn-amd-amdhsa"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 @_RSENC_gDcd___ = external protected addrspace(1) 
externally_initialized global [4096 x i8], align 16
 
 define protected amdgpu_kernel void 
@_RSENC_PRInit__(i1 %c0) local_unnamed_addr #0 {
+; CHECK-LABEL: _RSENC_PRInit__:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:flat_load_dword v0, v[0:1]
+; CHECK-NEXT:s_add_u32 s0, s0, s17
+; CHECK-NEXT:s_mov_b32 s4, 0xf19b3
+; CHECK-NEXT:s_addc_u32 s1, s1, 0
+; CHECK-NEXT:s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:v_lshl_add_u32 v0, v0, 1, v0
+; CHECK-NEXT:v_cmp_ne_u32_e32 vcc, s4, v0
+; CHECK-NEXT:s_and_saveexec_b64 s[4:5], vcc
+; CHECK-NEXT:s_cbranch_execz .LBB0_12
+; CHECK-NEXT:  ; %bb.1: ; %if.end15
+; CHECK-NEXT:s_load_dword s4, s[8:9], 0x0
+; CHECK-NEXT:s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:s_bitcmp1_b32 s4, 0
+; CHECK-NEXT:s_cselect_b64 s[4:5], -1, 0
+; CHECK-NEXT:s_and_b64 vcc, exec, s[4:5]
+; CHECK-NEXT:s_cbranch_vccnz .LBB0_12
+; CHECK-NEXT:  .LBB0_2: ; %while.cond.i
+; CHECK-NEXT:; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:s_cbranch_scc1 .LBB0_2
+; CHECK-NEXT:  ; %bb.3: ; %if.end60
+; CHECK-NEXT:s_mov_b64 vcc, exec
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.4: ; %if.end5.i
+; CHECK-NEXT:s_mov_b64 vcc, vcc
+; CHECK-NEXT:s_cbranch_vccz .LBB0_11
+; CHECK-NEXT:  ; %bb.5: ; %if.end5.i314
+; CHECK-NEXT:s_mov_b64 vcc, exec
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.6: ; %if.end5.i338
+; CHECK-NEXT:s_mov_b64 vcc, vcc
+; CHECK-NEXT:s_cbranch_vccz .LBB0_11
+; CHECK-NEXT:  ; %bb.7: ; %if.end5.i362
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:s_getpc_b64 s[4:5]
+; CHECK-NEXT:s_add_u32 s4, s4, 
_RSENC_gDcd___@rel32@lo+1157
+; CHECK-NEXT:s_addc_u32 s5, s5, 
_RSENC_gDcd___@rel32@hi+1165
+; CHECK-NEXT:global_load_ubyte v1, v0, s[4:5]
+; CHECK-NEXT:s_nop 0
+; CHECK-NEXT:buffer_store_byte v0, v0, s[0:3], 0 offen
+; CHECK-NEXT:s_waitcnt vmcnt(1)
+; CHECK-NEXT:buffer_store_byte v1, off, s[0:3], 0 offset:257
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.8: ; %if.end5.i400
+; CHECK-NEXT:flat_load_ubyte v0, v[0:1]
+; CHECK-NEXT:s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:v_cmp_eq_u16_e32 vcc, 0, v0
+; CHECK-NEXT:s_and_b64 exec, exec, vcc
+; CHECK-NEXT:s_cbranch_execz .LBB0_11
+; CHECK-NEXT:  ; %bb.9: ; %if.then404
+; CHECK-NEXT:s_movk_i32 s4, 0x1000
+; CHECK-NEXT:  .LBB0_10: ; %for.body564
+; CHECK-NEXT:; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:s_sub_i32 s4, s4, 32
+; CHECK-NEXT:s_cmp_lg_u32 s4, 0
+; CHECK-NEXT:s_cbranch_scc1 .LBB0_10
+; CHECK-NEXT:  .LBB0_11: ; %UnifiedUnreachableBlock
+; CHECK-NEXT:; divergent unreachable
+; CHECK-NEXT:  .LBB0_12: ; %UnifiedReturnBlock
+; CHECK-NEXT:s_endpgm
 entry:
   %runtimeVersionCopy = alloca [128 x i8], align 16, addrspace(5)
   %licenseVersionCopy = alloca [128 x i8], align 16, addrspace(5)

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[llvm-branch-commits] [llvm] AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (PR #131101)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131101

>From 94e7a51783c878035c8e463dfb6931fc84fe066f Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 14:55:45 +0700
Subject: [PATCH] AMDGPU: Replace test uses of ptr addrspace(5) undef with
 poison

---
 .../AMDGPU/GlobalISel/divergent-control-flow.ll  |  2 +-
 llvm/test/CodeGen/AMDGPU/collapse-endcf.ll   |  4 ++--
 llvm/test/CodeGen/AMDGPU/dag-divergence.ll   |  2 +-
 llvm/test/CodeGen/AMDGPU/debug-value.ll  |  2 +-
 llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll  |  2 +-
 llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir |  2 +-
 llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll |  2 +-
 ...emory-legalizer-multiple-mem-operands-atomics.mir |  6 +++---
 llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll|  2 +-
 llvm/test/CodeGen/AMDGPU/operand-folding.ll  |  2 +-
 .../test/CodeGen/AMDGPU/private-access-no-objects.ll |  4 ++--
 .../CodeGen/AMDGPU/promote-alloca-to-lds-select.ll   |  6 +++---
 llvm/test/CodeGen/AMDGPU/sad.ll  | 12 ++--
 llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll   |  8 
 .../stack-pointer-offset-relative-frameindex.ll  |  2 +-
 15 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index 3ad5845467cd0..989ee80a1f002 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -183,7 +183,7 @@ bb8:
   br i1 %tmp10, label %bb11, label %bb12
 
 bb11:
-  store float 4.0, ptr addrspace(5) undef, align 4
+  store float 4.0, ptr addrspace(5) poison, align 4
   br label %bb12
 
 bb12:
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll 
b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index c8a4f2d2e6b7b..a60a16c9be47e 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -1360,7 +1360,7 @@ bb2:  ; preds 
= %bb1
   br i1 %tmp3, label %bb4, label %bb10
 
 bb4:  ; preds = %bb2
-  %tmp6 = load float, ptr addrspace(5) undef
+  %tmp6 = load float, ptr addrspace(5) poison
   %tmp7 = fcmp olt float %tmp6, 0.0
   br i1 %tmp7, label %bb8, label %Flow
 
@@ -1380,7 +1380,7 @@ Flow1:; preds 
= %bb10
   br label %bb1
 
 bb12: ; preds = %bb10
-  store volatile <4 x float> %tmp11, ptr addrspace(5) undef, align 16
+  store volatile <4 x float> %tmp11, ptr addrspace(5) poison, align 16
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll 
b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
index 8b27a9bde8ea6..9f83393d88061 100644
--- a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
+++ b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
@@ -6,7 +6,7 @@
 ; GCN: flat_load_dword
 ; GCN-NOT: s_load_dword s
 define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, 
ptr %flat) {
-  %load = load volatile i32, ptr addrspace(5) undef, align 4
+  %load = load volatile i32, ptr addrspace(5) poison, align 4
   %gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
   %maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
   store i32 %maybe.not.uniform.load, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll 
b/llvm/test/CodeGen/AMDGPU/debug-value.ll
index 167c0ce7ceefa..f13bd665cc7f0 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll
@@ -35,7 +35,7 @@ bb25: ; preds = 
%bb
 
 bb28: ; preds = %bb25, %bb21
   %tmp29 = phi <4 x float> [ %tmp27, %bb25 ], [ %tmp24, %bb21 ]
-  store <4 x float> %tmp29, ptr addrspace(5) undef, align 16
+  store <4 x float> %tmp29, ptr addrspace(5) poison, align 16
   %tmp30 = getelementptr inbounds %struct.wombat, ptr addrspace(1) %arg, i64 
%tmp2, i32 2, i64 2
   %tmp31 = load i32, ptr addrspace(1) %tmp30, align 4
   %tmp32 = sext i32 %tmp31 to i64
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll 
b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
index ea33925117aea..25fe57c16c661 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
@@ -255,7 +255,7 @@ define void @undefined_stack_store_reg(float %arg, i32 
%arg1) #0 {
 bb:
   %tmp = alloca <4 x float>, align 16, addrspace(5)
   %tmp2 = insertelement <4 x float> poison, float %arg, i32 0
-  store <4 x float> %tmp2, ptr addrspace(5) undef
+  store <4 x float> %tmp2, ptr addrspace(5) poison
   %tmp3 = icmp eq i32 %arg1, 0
   br i1 %tmp3, label %bb4, label %bb5
 
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt

[llvm-branch-commits] [llvm] [DirectX] Updating Root Signature documentation with Descriptor table description (PR #129797)

[via llvm-branch-commits]

https://github.com/joaosaffran closed 
https://github.com/llvm/llvm-project/pull/129797
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[llvm-branch-commits] [llvm] [DirectX] Updating DXContainer documentation to add Root Descriptors (PR #129759)

[via llvm-branch-commits]

https://github.com/joaosaffran closed 
https://github.com/llvm/llvm-project/pull/129759
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[llvm-branch-commits] [clang] Backport: [clang] fix matching of nested template template parameters (PR #130950)

[Mike Lothian via llvm-branch-commits]

FireBurn wrote:

The reduced case works assuming you mean:

```
template  typename> typename>
struct foo {};

template  typename>
struct bar {};

using baz = foo;
```

https://github.com/llvm/llvm-project/pull/130950
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[llvm-branch-commits] [clang] release/20.x: Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (#129934) (PR #131209)

[via llvm-branch-commits]

llvmbot wrote:

@higher-performance What do you think about merging this PR to the release 
branch?

https://github.com/llvm/llvm-project/pull/131209
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[llvm-branch-commits] [clang] release/20.x: Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (#129934) (PR #131209)

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https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/131209
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[llvm-branch-commits] [clang] release/20.x: Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (#129934) (PR #131209)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: None (llvmbot)


Changes

Backport 8c7f0eaa6ee3f84e3d8260535cced234bed4fa28

Requested by: @higher-performance

---
Full diff: https://github.com/llvm/llvm-project/pull/131209.diff


1 Files Affected:

- (modified) clang/lib/AST/ParentMapContext.cpp (+11-6) 


``diff
diff --git a/clang/lib/AST/ParentMapContext.cpp 
b/clang/lib/AST/ParentMapContext.cpp
index 7ff492443031d..d8dd352c42d6b 100644
--- a/clang/lib/AST/ParentMapContext.cpp
+++ b/clang/lib/AST/ParentMapContext.cpp
@@ -12,10 +12,11 @@
 
//===--===//
 
 #include "clang/AST/ParentMapContext.h"
-#include "clang/AST/RecursiveASTVisitor.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/Expr.h"
+#include "clang/AST/RecursiveASTVisitor.h"
 #include "clang/AST/TemplateBase.h"
+#include "llvm/ADT/SmallPtrSet.h"
 
 using namespace clang;
 
@@ -69,17 +70,21 @@ class ParentMapContext::ParentMap {
   for (; N > 0; --N)
 push_back(Value);
 }
-bool contains(const DynTypedNode &Value) {
-  return Seen.contains(Value);
+bool contains(const DynTypedNode &Value) const {
+  const void *Identity = Value.getMemoizationData();
+  assert(Identity);
+  return Dedup.contains(Identity);
 }
 void push_back(const DynTypedNode &Value) {
-  if (!Value.getMemoizationData() || Seen.insert(Value).second)
+  const void *Identity = Value.getMemoizationData();
+  if (!Identity || Dedup.insert(Identity).second) {
 Items.push_back(Value);
+  }
 }
 llvm::ArrayRef view() const { return Items; }
   private:
-llvm::SmallVector Items;
-llvm::SmallDenseSet Seen;
+llvm::SmallVector Items;
+llvm::SmallPtrSet Dedup;
   };
 
   /// Maps from a node to its parents. This is used for nodes that have

``




https://github.com/llvm/llvm-project/pull/131209
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[llvm-branch-commits] [clang] release/20.x: Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (#129934) (PR #131209)

[Erich Keane via llvm-branch-commits]

erichkeane wrote:

FWIW: I'm in favor of this.  This is quite low risk/a pretty trivial change 
that has an incredibly big impact on the memory pressure of our compiler in 
certain situations.  I think this is  a good candidate to back port.

https://github.com/llvm/llvm-project/pull/131209
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[llvm-branch-commits] [clang] release/20.x: Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (#129934) (PR #131209)

[via llvm-branch-commits]

higher-performance wrote:

LGTM. @erichkeane?

https://github.com/llvm/llvm-project/pull/131209
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[llvm-branch-commits] [clang] Backport: [clang] fix matching of nested template template parameters (PR #130950)

[Matheus Izvekov via llvm-branch-commits]

mizvekov wrote:

@FireBurn does it work on the main branch, but not on this branch?

You can see this PR includes a test case for GH130362, so maybe if you tested 
everything right, you have a different bug in your hands?

Can you try the reduced example yourself?

https://github.com/llvm/llvm-project/pull/130950
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[llvm-branch-commits] [clang] release/20.x: Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (#129934) (PR #131209)

[via llvm-branch-commits]

https://github.com/cor3ntin approved this pull request.


https://github.com/llvm/llvm-project/pull/131209
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[llvm-branch-commits] [lld] [llvm] release/20.x: [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (#128942) (PR #129762)

[Nikita Popov via llvm-branch-commits]

https://github.com/nikic requested changes to this pull request.

This has multiple ABI and API breaking changes. I wonder why the ABI job 
doesn't flag this.

https://github.com/llvm/llvm-project/pull/129762
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[llvm-branch-commits] [llvm] AMDGPU: Use generated checks in test missing checks (PR #131110)

[Matt Arsenault via llvm-branch-commits]

@@ -1,10 +1,72 @@
-; RUN: llc < %s
-target datalayout = 
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
-target triple = "amdgcn-amd-amdhsa"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 @_RSENC_gDcd___ = external protected addrspace(1) 
externally_initialized global [4096 x i8], align 16
 
 define protected amdgpu_kernel void 
@_RSENC_PRInit__(i1 %c0) local_unnamed_addr #0 {

arsenm wrote:

Came from something real I assume, but I have no idea 

https://github.com/llvm/llvm-project/pull/131110
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[llvm-branch-commits] [llvm] AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (PR #131101)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/131101

>From 054d80a8ef3d5d456b2ff692d9bf7215c31933a8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Thu, 13 Mar 2025 14:55:45 +0700
Subject: [PATCH] AMDGPU: Replace test uses of ptr addrspace(5) undef with
 poison

---
 .../AMDGPU/GlobalISel/divergent-control-flow.ll  |  2 +-
 llvm/test/CodeGen/AMDGPU/collapse-endcf.ll   |  4 ++--
 llvm/test/CodeGen/AMDGPU/dag-divergence.ll   |  2 +-
 llvm/test/CodeGen/AMDGPU/debug-value.ll  |  2 +-
 llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll  |  2 +-
 llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir |  2 +-
 llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll |  2 +-
 ...emory-legalizer-multiple-mem-operands-atomics.mir |  6 +++---
 llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll|  2 +-
 llvm/test/CodeGen/AMDGPU/operand-folding.ll  |  2 +-
 .../test/CodeGen/AMDGPU/private-access-no-objects.ll |  4 ++--
 .../CodeGen/AMDGPU/promote-alloca-to-lds-select.ll   |  6 +++---
 llvm/test/CodeGen/AMDGPU/sad.ll  | 12 ++--
 llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll   |  8 
 .../stack-pointer-offset-relative-frameindex.ll  |  2 +-
 15 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index 3ad5845467cd0..989ee80a1f002 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -183,7 +183,7 @@ bb8:
   br i1 %tmp10, label %bb11, label %bb12
 
 bb11:
-  store float 4.0, ptr addrspace(5) undef, align 4
+  store float 4.0, ptr addrspace(5) poison, align 4
   br label %bb12
 
 bb12:
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll 
b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index c8a4f2d2e6b7b..a60a16c9be47e 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -1360,7 +1360,7 @@ bb2:  ; preds 
= %bb1
   br i1 %tmp3, label %bb4, label %bb10
 
 bb4:  ; preds = %bb2
-  %tmp6 = load float, ptr addrspace(5) undef
+  %tmp6 = load float, ptr addrspace(5) poison
   %tmp7 = fcmp olt float %tmp6, 0.0
   br i1 %tmp7, label %bb8, label %Flow
 
@@ -1380,7 +1380,7 @@ Flow1:; preds 
= %bb10
   br label %bb1
 
 bb12: ; preds = %bb10
-  store volatile <4 x float> %tmp11, ptr addrspace(5) undef, align 16
+  store volatile <4 x float> %tmp11, ptr addrspace(5) poison, align 16
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll 
b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
index 8b27a9bde8ea6..9f83393d88061 100644
--- a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
+++ b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
@@ -6,7 +6,7 @@
 ; GCN: flat_load_dword
 ; GCN-NOT: s_load_dword s
 define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, 
ptr %flat) {
-  %load = load volatile i32, ptr addrspace(5) undef, align 4
+  %load = load volatile i32, ptr addrspace(5) poison, align 4
   %gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
   %maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
   store i32 %maybe.not.uniform.load, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll 
b/llvm/test/CodeGen/AMDGPU/debug-value.ll
index 167c0ce7ceefa..f13bd665cc7f0 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll
@@ -35,7 +35,7 @@ bb25: ; preds = 
%bb
 
 bb28: ; preds = %bb25, %bb21
   %tmp29 = phi <4 x float> [ %tmp27, %bb25 ], [ %tmp24, %bb21 ]
-  store <4 x float> %tmp29, ptr addrspace(5) undef, align 16
+  store <4 x float> %tmp29, ptr addrspace(5) poison, align 16
   %tmp30 = getelementptr inbounds %struct.wombat, ptr addrspace(1) %arg, i64 
%tmp2, i32 2, i64 2
   %tmp31 = load i32, ptr addrspace(1) %tmp30, align 4
   %tmp32 = sext i32 %tmp31 to i64
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll 
b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
index ea33925117aea..25fe57c16c661 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
@@ -255,7 +255,7 @@ define void @undefined_stack_store_reg(float %arg, i32 
%arg1) #0 {
 bb:
   %tmp = alloca <4 x float>, align 16, addrspace(5)
   %tmp2 = insertelement <4 x float> poison, float %arg, i32 0
-  store <4 x float> %tmp2, ptr addrspace(5) undef
+  store <4 x float> %tmp2, ptr addrspace(5) poison
   %tmp3 = icmp eq i32 %arg1, 0
   br i1 %tmp3, label %bb4, label %bb5
 
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt

[llvm-branch-commits] [llvm] AMDGPU: Replace some test i32 undef uses with poison (PR #131092)

[Pravin Jagtap via llvm-branch-commits]

https://github.com/pravinjagtap approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/131092
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[llvm-branch-commits] [flang] [flang][OpenMP] Use OmpDirectiveSpecification in standalone directives (PR #131163)

[via llvm-branch-commits]

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff 64bca90b7d6ac5b39a29f1cfdfe7569518b7c460 
01dd3f55995e507ddee61e80e3eb29e35f722c0f --extensions h,cpp -- 
flang/include/flang/Parser/dump-parse-tree.h 
flang/include/flang/Parser/parse-tree.h flang/lib/Lower/OpenMP/Clauses.cpp 
flang/lib/Lower/OpenMP/Clauses.h flang/lib/Lower/OpenMP/OpenMP.cpp 
flang/lib/Parser/openmp-parsers.cpp flang/lib/Parser/parse-tree.cpp 
flang/lib/Parser/unparse.cpp flang/lib/Semantics/check-omp-structure.cpp 
flang/lib/Semantics/check-omp-structure.h 
flang/lib/Semantics/resolve-directives.cpp flang/lib/Semantics/resolve-names.cpp
``





View the diff from clang-format here.


``diff
diff --git a/flang/include/flang/Parser/parse-tree.h 
b/flang/include/flang/Parser/parse-tree.h
index a31018c9ab..029c3de354 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -4871,8 +4871,8 @@ struct OmpLoopDirective {
 
 // 2.14.2 cancellation-point -> CANCELLATION POINT construct-type-clause
 struct OpenMPCancellationPointConstruct {
-  WRAPPER_CLASS_BOILERPLATE(OpenMPCancellationPointConstruct,
-  OmpDirectiveSpecification);
+  WRAPPER_CLASS_BOILERPLATE(
+  OpenMPCancellationPointConstruct, OmpDirectiveSpecification);
   CharBlock source;
 };
 
diff --git a/flang/lib/Semantics/check-omp-structure.cpp 
b/flang/lib/Semantics/check-omp-structure.cpp
index 8a8dc5e571..34da443124 100644
--- a/flang/lib/Semantics/check-omp-structure.cpp
+++ b/flang/lib/Semantics/check-omp-structure.cpp
@@ -1614,8 +1614,8 @@ void OmpStructureChecker::Enter(const 
parser::OpenMPDepobjConstruct &x) {
 if (arguments.v.size() != 1) {
   parser::CharBlock source(
   arguments.v.empty() ? dirName.source : arguments.source);
-  context_.Say(source,
-  "The DEPOBJ directive requires a single argument"_err_en_US);
+  context_.Say(
+  source, "The DEPOBJ directive requires a single argument"_err_en_US);
 }
   }
   if (clauses.v.size() != 1) {

``




https://github.com/llvm/llvm-project/pull/131163
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[llvm-branch-commits] [llvm] AMDGPU: Replace some float undef test uses with poison (PR #131090)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/131090?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#131090** https://app.graphite.dev/github/pr/llvm/llvm-project/131090?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/131090?utm_source=stack-comment-view-in-graphite";
 target="_blank">(View in Graphite)
* **#131084** https://app.graphite.dev/github/pr/llvm/llvm-project/131084?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#131083** https://app.graphite.dev/github/pr/llvm/llvm-project/131083?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/131090
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[llvm-branch-commits] [flang] [flang][OpenMP] Use OmpDirectiveSpecification in standalone directives (PR #131163)

[Krzysztof Parzyszek via llvm-branch-commits]

https://github.com/kparzysz updated 
https://github.com/llvm/llvm-project/pull/131163

>From 01dd3f55995e507ddee61e80e3eb29e35f722c0f Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek 
Date: Mon, 10 Mar 2025 15:42:42 -0500
Subject: [PATCH 1/2] [flang][OpenMP] Use OmpDirectiveSpecification in
 standalone directives

This uses OmpDirectiveSpecification in the rest of the standalone
directives.
---
 flang/include/flang/Parser/dump-parse-tree.h  |   1 +
 flang/include/flang/Parser/parse-tree.h   |  23 ++--
 flang/lib/Lower/OpenMP/Clauses.cpp|  19 +++
 flang/lib/Lower/OpenMP/Clauses.h  |   3 +
 flang/lib/Lower/OpenMP/OpenMP.cpp |  31 ++---
 flang/lib/Parser/openmp-parsers.cpp   |  74 ++-
 flang/lib/Parser/parse-tree.cpp   |   8 ++
 flang/lib/Parser/unparse.cpp  |  30 ++---
 flang/lib/Semantics/check-omp-structure.cpp   | 125 +-
 flang/lib/Semantics/check-omp-structure.h |   3 +-
 flang/lib/Semantics/resolve-directives.cpp|   9 +-
 flang/lib/Semantics/resolve-names.cpp |   6 +-
 flang/test/Parser/OpenMP/depobj-construct.f90 |  32 ++---
 .../Parser/OpenMP/metadirective-dirspec.f90   |  18 +--
 .../Parser/OpenMP/metadirective-flush.f90 |   4 +-
 .../Semantics/OpenMP/depobj-construct-v50.f90 |  17 +++
 16 files changed, 257 insertions(+), 146 deletions(-)

diff --git a/flang/include/flang/Parser/dump-parse-tree.h 
b/flang/include/flang/Parser/dump-parse-tree.h
index 118df6cf2a4ff..9bff2dab974ec 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -484,6 +484,7 @@ class ParseTreeDumper {
   NODE(parser, OmpLocatorList)
   NODE(parser, OmpReductionSpecifier)
   NODE(parser, OmpArgument)
+  NODE(parser, OmpArgumentList)
   NODE(parser, OmpMetadirectiveDirective)
   NODE(parser, OmpMatchClause)
   NODE(parser, OmpOtherwiseClause)
diff --git a/flang/include/flang/Parser/parse-tree.h 
b/flang/include/flang/Parser/parse-tree.h
index dfde4ceb787d2..a31018c9abc09 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3557,6 +3557,11 @@ struct OmpArgument {
   OmpMapperSpecifier, OmpReductionSpecifier>
   u;
 };
+
+struct OmpArgumentList {
+  WRAPPER_CLASS_BOILERPLATE(OmpArgumentList, std::list);
+  CharBlock source;
+};
 } // namespace arguments
 
 inline namespace traits {
@@ -4511,10 +4516,11 @@ struct OmpDirectiveSpecification {
   llvm::omp::Directive DirId() const { //
 return std::get(t).v;
   }
+  const OmpArgumentList &Arguments() const;
   const OmpClauseList &Clauses() const;
 
   CharBlock source;
-  std::tuple>,
+  std::tuple,
   std::optional, Flags>
   t;
 };
@@ -4865,16 +4871,15 @@ struct OmpLoopDirective {
 
 // 2.14.2 cancellation-point -> CANCELLATION POINT construct-type-clause
 struct OpenMPCancellationPointConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPCancellationPointConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPCancellationPointConstruct,
+  OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // 2.14.1 cancel -> CANCEL construct-type-clause [ [,] if-clause]
 struct OpenMPCancelConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPCancelConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPCancelConstruct, OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // Ref: [5.0:254-255], [5.1:287-288], [5.2:322-323]
@@ -4884,9 +4889,8 @@ struct OpenMPCancelConstruct {
 //  destroy-clause |
 //  update-clause
 struct OpenMPDepobjConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPDepobjConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPDepobjConstruct, OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple t;
 };
 
 // Ref: [5.2: 200-201]
@@ -4927,11 +4931,8 @@ struct OpenMPDispatchConstruct {
 //ACQ_REL | RELEASE | ACQUIRE | // since 5.0
 //SEQ_CST   // since 5.1
 struct OpenMPFlushConstruct {
-  TUPLE_CLASS_BOILERPLATE(OpenMPFlushConstruct);
+  WRAPPER_CLASS_BOILERPLATE(OpenMPFlushConstruct, OmpDirectiveSpecification);
   CharBlock source;
-  std::tuple,
-  std::optional, /*TrailingClauses=*/bool>
-  t;
 };
 
 struct OpenMPSimpleStandaloneConstruct {
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp 
b/flang/lib/Lower/OpenMP/Clauses.cpp
index 9fa9abd9e8ceb..7ad6f7f3da00a 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -132,6 +132,25 @@ Object makeObject(const parser::OmpObject &object,
   return makeObject(std::get(object.u), semaCtx);
 }
 
+ObjectList makeObjects(const parser::OmpArgumentList &objects,
+   semantics::SemanticsContext &semaCtx) {
+  return makeList(objects.v, [&](const parser::OmpArgument &arg) {
+return common::visit(
+common::visitors{
+[&](const parser::OmpLocator &locator) -> Object {
+  if (auto *object = std::get_if(&loca

[llvm-branch-commits] [llvm] AMDGPU: Use generated checks in test missing checks (PR #131110)

[Shilei Tian via llvm-branch-commits]

@@ -1,10 +1,72 @@
-; RUN: llc < %s
-target datalayout = 
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
-target triple = "amdgcn-amd-amdhsa"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 @_RSENC_gDcd___ = external protected addrspace(1) 
externally_initialized global [4096 x i8], align 16
 
 define protected amdgpu_kernel void 
@_RSENC_PRInit__(i1 %c0) local_unnamed_addr #0 {

shiltian wrote:

what the heck of the function name is...

https://github.com/llvm/llvm-project/pull/131110
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[llvm-branch-commits] [libcxx] [libc++][format] Implements P3107R5 in . (PR #130500)

[Mark de Wever via llvm-branch-commits]

https://github.com/mordante updated 
https://github.com/llvm/llvm-project/pull/130500

>From c132aa555a38efde9b04c2a3f435ba598778c28d Mon Sep 17 00:00:00 2001
From: Mark de Wever 
Date: Sat, 30 Mar 2024 17:35:56 +0100
Subject: [PATCH 1/2] [libc++][format] Implements P3107R5 in .

The followup paper P3235R3 which is voted in as a DR changes the names
foo_locking to foo_buffered. These changes have been applied in this
patch.

Before
---
Benchmark Time CPU   Iterations
---
printf 71.3 ns 71.3 ns  9525175
print_string226 ns  226 ns  3105850
print_stack 232 ns  232 ns  3026498
print_direct530 ns  530 ns  1318447

After
---
Benchmark Time CPU   Iterations
---
printf 70.6 ns 70.6 ns  9789585
print_string222 ns  222 ns  3147678
print_stack 227 ns  227 ns  3084767
print_direct474 ns  474 ns  1472786

Note: The performance of libc++'s std::print is still extemely slow
compared to printf. Based on P3107R5 std::print should outperform
printf. The main culprit is the call to isatty, which is resolved
after implementing
LWG4044  Confusing requirements for std::print on POSIX platforms

Implements
- P3107R5 - Permit an efficient implementation of ``std::print``

Implements parts of
- P3235R3 std::print more types faster with less memory

Fixes: #105435
---
 libcxx/docs/ReleaseNotes/21.rst   |   1 +
 libcxx/include/__format/buffer.h  |   3 +
 libcxx/include/print  | 270 +-
 libcxx/modules/std/print.inc  |   1 +
 .../test/libcxx/system_reserved_names.gen.py  |   5 +
 .../test/libcxx/transitive_includes/cxx03.csv |   5 +
 .../test/libcxx/transitive_includes/cxx11.csv |   5 +
 .../test/libcxx/transitive_includes/cxx14.csv |   5 +
 .../test/libcxx/transitive_includes/cxx17.csv |   5 +
 .../test/libcxx/transitive_includes/cxx23.csv |   5 +-
 .../test/libcxx/transitive_includes/cxx26.csv |   4 +
 11 files changed, 296 insertions(+), 13 deletions(-)

diff --git a/libcxx/docs/ReleaseNotes/21.rst b/libcxx/docs/ReleaseNotes/21.rst
index e7cfa625a132c..a1f30b26c5a1d 100644
--- a/libcxx/docs/ReleaseNotes/21.rst
+++ b/libcxx/docs/ReleaseNotes/21.rst
@@ -40,6 +40,7 @@ Implemented Papers
 
 - N4258: Cleaning-up noexcept in the Library (`Github 
`__)
 - P1361R2: Integration of chrono with text formatting (`Github 
`__)
+- P3107R5 - Permit an efficient implementation of ``std::print`` (`Github 
`__)
 
 Improvements and New Features
 -
diff --git a/libcxx/include/__format/buffer.h b/libcxx/include/__format/buffer.h
index c88b7f3222010..d6e4ddc840e2d 100644
--- a/libcxx/include/__format/buffer.h
+++ b/libcxx/include/__format/buffer.h
@@ -12,6 +12,7 @@
 
 #include <__algorithm/copy_n.h>
 #include <__algorithm/fill_n.h>
+#include <__algorithm/for_each.h>
 #include <__algorithm/max.h>
 #include <__algorithm/min.h>
 #include <__algorithm/ranges_copy.h>
@@ -34,11 +35,13 @@
 #include <__memory/construct_at.h>
 #include <__memory/destroy.h>
 #include <__memory/uninitialized_algorithms.h>
+#include <__system_error/system_error.h>
 #include <__type_traits/add_pointer.h>
 #include <__type_traits/conditional.h>
 #include <__utility/exception_guard.h>
 #include <__utility/move.h>
 #include 
+#include  // Uses the POSIX/Windows unlocked stream I/O
 #include 
 
 #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
diff --git a/libcxx/include/print b/libcxx/include/print
index 1794d6014efcd..f6d03edfbd4bc 100644
--- a/libcxx/include/print
+++ b/libcxx/include/print
@@ -27,9 +27,11 @@ namespace std {
 
   void vprint_unicode(string_view fmt, format_args args);
   void vprint_unicode(FILE* stream, string_view fmt, format_args args);
+  void vprint_unicode_buffered(FILE* stream, string_view fmt, format_args 
args);
 
   void vprint_nonunicode(string_view fmt, format_args args);
   void vprint_nonunicode(FILE* stream, string_view fmt, format_args args);
+  void vprint_nonunicode_buffered(FILE* stream, string_view fmt, format_args 
args);
 }
 */
 
@@ -41,6 +43,7 @@ namespace std {
 #  include <__config>
 #  include <__system_error/throw_system_error.h>
 #  include <__utility/forward.h>
+#  include <__utility/move.h>
 #  include 
 #  include 
 #  include 
@@ -52,6 +55,9 @@ namespace std {
 #pragma GCC system_header
 #  endif
 
+_LIBCPP_PUSH_MACROS
+#  include <__undef_macros>
+
 _LIBCPP_BEGIN_NAMESPACE_STD
 
 #  ifdef _LIBCPP_WIN32API
@@ -213,6 +219,122 @@ _LIBCPP_HIDE_FROM_ABI inline

[llvm-branch-commits] [clang] Backport: [clang] fix matching of nested template template parameters (PR #130950)

[Matheus Izvekov via llvm-branch-commits]

mizvekov wrote:

Yeah that's the reduced example for the issue this PR solves.

https://github.com/llvm/llvm-project/pull/130950
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