[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)
https://github.com/ritter-x2a created
https://github.com/llvm/llvm-project/pull/126878
This was only used for gfx940 and gfx941, which have since been removed.
For SWDEV-512631
>From 79c331e05d2b06597ff1b69f08c8af04f0dbe86b Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 04:13:18 -0500
Subject: [PATCH] [AMDGPU] Remove FeatureForceStoreSC0SC1
This was only used for gfx940 and gfx941, which have since been removed.
For SWDEV-512631
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 6 --
llvm/lib/Target/AMDGPU/GCNSubtarget.h| 3 ---
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 20
3 files changed, 29 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 3aabca49b249e..effc8d2ed6b49 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1040,12 +1040,6 @@ def FeatureVALUTransUseHazard :
SubtargetFeature<"valu-trans-use-hazard",
"Hazard when TRANS instructions are closely followed by a use of the result"
>;
-def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
- "HasForceStoreSC0SC1",
- "true",
- "Has SC0 and SC1 on stores"
->;
-
def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
"HasSALUFloatInsts",
"true",
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index f7c5c472c93a5..6664a70572ded 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -246,7 +246,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasMADIntraFwdBug = false;
bool HasVOPDInsts = false;
bool HasVALUTransUseHazard = false;
- bool HasForceStoreSC0SC1 = false;
bool HasRequiredExportPriority = false;
bool HasVmemWriteVgprInOrder = false;
bool HasAshrPkInsts = false;
@@ -1264,8 +1263,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasCvtScaleForwardingHazard() const { return GFX950Insts; }
- bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; }
-
bool requiresCodeObjectV6() const { return RequiresCOV6; }
bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 79fb36acc0ea7..34953f9c08db7 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -359,11 +359,6 @@ class SICacheControl {
/// Virtual destructor to allow derivations to be deleted.
virtual ~SICacheControl() = default;
-
- virtual bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
- MachineBasicBlock::iterator &MI) const {
-return false;
- }
};
class SIGfx6CacheControl : public SICacheControl {
@@ -517,20 +512,6 @@ class SIGfx940CacheControl : public SIGfx90ACacheControl {
bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, bool
IsCrossAddrSpaceOrdering,
Position Pos) const override;
-
- bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
- MachineBasicBlock::iterator &MI) const override {
-bool Changed = false;
-if (ST.hasForceStoreSC0SC1() &&
-(MOI.getInstrAddrSpace() & (SIAtomicAddrSpace::SCRATCH |
-SIAtomicAddrSpace::GLOBAL |
-SIAtomicAddrSpace::OTHER)) !=
- SIAtomicAddrSpace::NONE) {
- Changed |= enableSC0Bit(MI);
- Changed |= enableSC1Bit(MI);
-}
-return Changed;
- }
};
class SIGfx10CacheControl : public SIGfx7CacheControl {
@@ -2820,7 +2801,6 @@ bool
SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
Changed |= expandLoad(*MOI, MI);
else if (const auto &MOI = MOA.getStoreInfo(MI)) {
Changed |= expandStore(*MOI, MI);
-Changed |= CC->tryForceStoreSC0SC1(*MOI, MI);
} else if (const auto &MOI = MOA.getAtomicFenceInfo(MI))
Changed |= expandAtomicFence(*MOI, MI);
else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI))
___
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[llvm-branch-commits] [polly] [Polly] Introduce PhaseManager and remove LPM support (PR #125442)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/125442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [polly] [Polly] Introduce PhaseManager and remove LPM support (PR #125442)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/125442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs (PR #126887)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/126887 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [polly] [Polly] Introduce PhaseManager and remove LPM support (PR #125442)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/125442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
llvmbot wrote: @arsenm What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/126891 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/126891 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/126891
Backport bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c
Requested by: @davemgreen
>From cc60c22a9247423d5e32bd848c405e09b1175a32 Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 12 Feb 2025 11:04:08 +
Subject: [PATCH] [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799)
We we previously running into problems with fp128 types and certain
integer sizes.
Fixes an issue reported on #124984
(cherry picked from commit bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c)
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 18 +++
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 148 ++
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 118 ++
4 files changed, 285 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index f13f70e66cfaa..b58c160b5c8b8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -880,6 +880,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BITCAST(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
+ SDValue ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
SDValue ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 1000235ab4061..7c77e8a72c8ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -773,6 +773,10 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N,
unsigned OpNo) {
case ISD::LLRINT:
Res = ScalarizeVecOp_UnaryOp(N);
break;
+ case ISD::FP_TO_SINT_SAT:
+ case ISD::FP_TO_UINT_SAT:
+Res = ScalarizeVecOp_UnaryOpWithExtraInput(N);
+break;
case ISD::STRICT_SINT_TO_FP:
case ISD::STRICT_UINT_TO_FP:
case ISD::STRICT_FP_TO_SINT:
@@ -880,6 +884,20 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode
*N) {
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
}
+/// Same as ScalarizeVecOp_UnaryOp with an extra operand (for example a
+/// typesize).
+SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N) {
+ assert(N->getValueType(0).getVectorNumElements() == 1 &&
+ "Unexpected vector type!");
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));
+ SDValue Op =
+ DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0).getScalarType(),
+ Elt, N->getOperand(1));
+ // Revectorize the result so the types line up with what the uses of this
+ // expression expect.
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
+}
+
/// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
/// Do the strict FP operation on the element instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N) {
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 9ef6d61c350ec..b2b3430f4d85e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -5548,3 +5548,151 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x
double> %f) {
%x = call <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f)
ret <16 x i16> %x
}
+
+define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
+; CHECK-SD-LABEL: test_signed_v2f128_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:sub sp, sp, #96
+; CHECK-SD-NEXT:stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-SD-NEXT:stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT:.cfi_def_cfa_offset 96
+; CHECK-SD-NEXT:.cfi_offset w19, -8
+; CHECK-SD-NEXT:.cfi_offset w20, -16
+; CHECK-SD-NEXT:.cfi_offset w21, -24
+; CHECK-SD-NEXT:.cfi_offset w30, -32
+; CHECK-SD-NEXT:mov v2.16b, v1.16b
+; CHECK-SD-NEXT:stp q1, q0, [sp, #32] // 32-byte Folded Spill
+; CHECK-SD-NEXT:adrp x8, .LCPI86_0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_0]
+; CHECK-SD-NEXT:mov v0.16b, v2.16b
+; CHECK-SD-NEXT:str q1, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT:bl __getf2
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:mov w19, w0
+; CHECK-SD-NEXT:bl __fixtfdi
+; CHECK-SD-NEXT:adrp x8, .LCPI86_1
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:cmp w19, #0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_1]
+; CHECK-SD-NEXT:mov x20, #-9223372036854775808 // =0x8000
+; CHECK-SD-NEXT:csel x19, x20, x0,
[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: None (llvmbot)
Changes
Backport bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c
Requested by: @davemgreen
---
Full diff: https://github.com/llvm/llvm-project/pull/126891.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h (+1)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+18)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+148)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+118)
``diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index f13f70e66cfaa..b58c160b5c8b8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -880,6 +880,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BITCAST(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
+ SDValue ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
SDValue ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 1000235ab4061..7c77e8a72c8ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -773,6 +773,10 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N,
unsigned OpNo) {
case ISD::LLRINT:
Res = ScalarizeVecOp_UnaryOp(N);
break;
+ case ISD::FP_TO_SINT_SAT:
+ case ISD::FP_TO_UINT_SAT:
+Res = ScalarizeVecOp_UnaryOpWithExtraInput(N);
+break;
case ISD::STRICT_SINT_TO_FP:
case ISD::STRICT_UINT_TO_FP:
case ISD::STRICT_FP_TO_SINT:
@@ -880,6 +884,20 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode
*N) {
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
}
+/// Same as ScalarizeVecOp_UnaryOp with an extra operand (for example a
+/// typesize).
+SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N) {
+ assert(N->getValueType(0).getVectorNumElements() == 1 &&
+ "Unexpected vector type!");
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));
+ SDValue Op =
+ DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0).getScalarType(),
+ Elt, N->getOperand(1));
+ // Revectorize the result so the types line up with what the uses of this
+ // expression expect.
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
+}
+
/// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
/// Do the strict FP operation on the element instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N) {
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 9ef6d61c350ec..b2b3430f4d85e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -5548,3 +5548,151 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x
double> %f) {
%x = call <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f)
ret <16 x i16> %x
}
+
+define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
+; CHECK-SD-LABEL: test_signed_v2f128_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:sub sp, sp, #96
+; CHECK-SD-NEXT:stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-SD-NEXT:stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT:.cfi_def_cfa_offset 96
+; CHECK-SD-NEXT:.cfi_offset w19, -8
+; CHECK-SD-NEXT:.cfi_offset w20, -16
+; CHECK-SD-NEXT:.cfi_offset w21, -24
+; CHECK-SD-NEXT:.cfi_offset w30, -32
+; CHECK-SD-NEXT:mov v2.16b, v1.16b
+; CHECK-SD-NEXT:stp q1, q0, [sp, #32] // 32-byte Folded Spill
+; CHECK-SD-NEXT:adrp x8, .LCPI86_0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_0]
+; CHECK-SD-NEXT:mov v0.16b, v2.16b
+; CHECK-SD-NEXT:str q1, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT:bl __getf2
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:mov w19, w0
+; CHECK-SD-NEXT:bl __fixtfdi
+; CHECK-SD-NEXT:adrp x8, .LCPI86_1
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:cmp w19, #0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_1]
+; CHECK-SD-NEXT:mov x20, #-9223372036854775808 // =0x8000
+; CHECK-SD-NEXT:csel x19, x20, x0, lt
+; CHECK-SD-NEXT:str q1, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT:bl __gttf2
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:mov x21, #9223372036854775807 // =0x7fff
+; CHECK-SD-NEXT:cmp w0, #0
+; CHECK-SD-NEXT:csel x19, x21, x1
[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/126878 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/126881 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/126881
Backport 0abe058d7f99c9c7bbaf4ee98308c5e78d229897
Requested by: @nikic
>From 540c45e578ae099533ce459674557e8db4852ba5 Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Wed, 12 Feb 2025 09:44:26 +0100
Subject: [PATCH] [BOLT] Use getMainExecutable() (#126698)
Use LLVM's getMainExecutable() helper instead of rolling our own. This
will result in standard behavior across platforms, such as making sure
that symlinks are always resolved.
(cherry picked from commit 0abe058d7f99c9c7bbaf4ee98308c5e78d229897)
---
bolt/tools/driver/llvm-bolt.cpp | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/bolt/tools/driver/llvm-bolt.cpp b/bolt/tools/driver/llvm-bolt.cpp
index efa06cd68cb99..f151cf5f63fc5 100644
--- a/bolt/tools/driver/llvm-bolt.cpp
+++ b/bolt/tools/driver/llvm-bolt.cpp
@@ -173,16 +173,6 @@ void boltMode(int argc, char **argv) {
}
}
-static std::string GetExecutablePath(const char *Argv0) {
- SmallString<256> ExecutablePath(Argv0);
- // Do a PATH lookup if Argv0 isn't a valid path.
- if (!llvm::sys::fs::exists(ExecutablePath))
-if (llvm::ErrorOr P =
-llvm::sys::findProgramByName(ExecutablePath))
- ExecutablePath = *P;
- return std::string(ExecutablePath);
-}
-
int main(int argc, char **argv) {
// Print a stack trace if we signal out.
sys::PrintStackTraceOnErrorSignal(argv[0]);
@@ -190,7 +180,7 @@ int main(int argc, char **argv) {
llvm_shutdown_obj Y; // Call llvm_shutdown() on exit.
- std::string ToolPath = GetExecutablePath(argv[0]);
+ std::string ToolPath = llvm::sys::fs::getMainExecutable(argv[0], nullptr);
// Initialize targets and assembly printers/parsers.
llvm::InitializeAllTargetInfos();
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[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
llvmbot wrote: @dcci What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/126881 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: None (llvmbot)
Changes
Backport 0abe058d7f99c9c7bbaf4ee98308c5e78d229897
Requested by: @nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/126881.diff
1 Files Affected:
- (modified) bolt/tools/driver/llvm-bolt.cpp (+1-11)
``diff
diff --git a/bolt/tools/driver/llvm-bolt.cpp b/bolt/tools/driver/llvm-bolt.cpp
index efa06cd68cb99..f151cf5f63fc5 100644
--- a/bolt/tools/driver/llvm-bolt.cpp
+++ b/bolt/tools/driver/llvm-bolt.cpp
@@ -173,16 +173,6 @@ void boltMode(int argc, char **argv) {
}
}
-static std::string GetExecutablePath(const char *Argv0) {
- SmallString<256> ExecutablePath(Argv0);
- // Do a PATH lookup if Argv0 isn't a valid path.
- if (!llvm::sys::fs::exists(ExecutablePath))
-if (llvm::ErrorOr P =
-llvm::sys::findProgramByName(ExecutablePath))
- ExecutablePath = *P;
- return std::string(ExecutablePath);
-}
-
int main(int argc, char **argv) {
// Print a stack trace if we signal out.
sys::PrintStackTraceOnErrorSignal(argv[0]);
@@ -190,7 +180,7 @@ int main(int argc, char **argv) {
llvm_shutdown_obj Y; // Call llvm_shutdown() on exit.
- std::string ToolPath = GetExecutablePath(argv[0]);
+ std::string ToolPath = llvm::sys::fs::getMainExecutable(argv[0], nullptr);
// Initialize targets and assembly printers/parsers.
llvm::InitializeAllTargetInfos();
``
https://github.com/llvm/llvm-project/pull/126881
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[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/126883 Backport 2ad9d5f5f01cd4f29788a0cf7b21790df13fca71 Requested by: @mgorny >From 42a57e68d5da8c688070d3263dc01551b5012d62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Tue, 11 Feb 2025 17:20:23 +0100 Subject: [PATCH] [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) Add `LLVM_BUILD_TELEMETRY` to the list of flags exposed in `LLVMConfig.cmake`. This fixes telemetry library being misdetected as `OFF` when building LLDB standalone. Fixes bac62ee5b473e70981a6bd9759ec316315fca07d. -- I guess this also needs a backport to 20.x. (cherry picked from commit 2ad9d5f5f01cd4f29788a0cf7b21790df13fca71) --- llvm/cmake/modules/LLVMConfig.cmake.in | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/cmake/modules/LLVMConfig.cmake.in b/llvm/cmake/modules/LLVMConfig.cmake.in index c49f10b9343ff..28655ee3ab87d 100644 --- a/llvm/cmake/modules/LLVMConfig.cmake.in +++ b/llvm/cmake/modules/LLVMConfig.cmake.in @@ -100,6 +100,8 @@ set(LLVM_ENABLE_PIC @LLVM_ENABLE_PIC@) set(LLVM_BUILD_32_BITS @LLVM_BUILD_32_BITS@) +set(LLVM_BUILD_TELEMETRY @LLVM_BUILD_TELEMETRY@) + if (NOT "@LLVM_PTHREAD_LIB@" STREQUAL "") set(LLVM_PTHREAD_LIB "@LLVM_PTHREAD_LIB@") endif() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/126883 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
llvmbot wrote: @JDevlieghere What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/126883 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Add release note for Armv9.6 updates (PR #126513)
https://github.com/mgabka approved this pull request. https://github.com/llvm/llvm-project/pull/126513 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
https://github.com/ritter-x2a created https://github.com/llvm/llvm-project/pull/126906 gfx940 and gfx941 are no longer supported. This is the last one of a series of PRs to remove them from the code base. The ISA documentation still contains a lot of links and file names with the "gfx940" identifier. Changing them to "gfx942" is probably not worth the cost of breaking all URLs to these pages that users might have saved in the past. For SWDEV-512631 >From 666b36b6a80581fb3ad505da0b03c77ca43085f7 Mon Sep 17 00:00:00 2001 From: Fabian Ritter Date: Wed, 12 Feb 2025 08:04:43 -0500 Subject: [PATCH] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc gfx940 and gfx941 are no longer supported. This is the last one of a series of PRs to remove them from the code base. The ISA documentation still contains a lot of links and file names with the "gfx940" identifier. Changing them to "gfx942" is probably not worth the cost of breaking all URLs to these pages that users might have saved in the past. For SWDEV-512631 --- llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst index 90797499dec22..7603bcc95383b 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst @@ -6,7 +6,7 @@ ** -Syntax of gfx940 Instructions +Syntax of gfx942 Instructions .. contents:: @@ -15,7 +15,7 @@ Syntax of gfx940 Instructions Introduction -This document describes the syntax of gfx940 instructions. +This document describes the syntax of gfx942 instructions. Notation ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
ritter-x2a wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/126906?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#126906** https://app.graphite.dev/github/pr/llvm/llvm-project/126906?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/126906?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#126887** https://app.graphite.dev/github/pr/llvm/llvm-project/126887?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#126878** https://app.graphite.dev/github/pr/llvm/llvm-project/126878?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#126763** https://app.graphite.dev/github/pr/llvm/llvm-project/126763?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#126762** https://app.graphite.dev/github/pr/llvm/llvm-project/126762?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125836** https://app.graphite.dev/github/pr/llvm/llvm-project/125836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125827** https://app.graphite.dev/github/pr/llvm/llvm-project/125827?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125826** https://app.graphite.dev/github/pr/llvm/llvm-project/125826?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125711** https://app.graphite.dev/github/pr/llvm/llvm-project/125711?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -56,9 +75,18 @@ llvm::Type
*DirectXTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
return llvm::TargetExtType::get(Ctx, TypeName, {ElemType}, Ints);
}
- case llvm::dxil::ResourceClass::CBuffer:
-llvm_unreachable("dx.CBuffer handles are not implemented yet");
-break;
+ case llvm::dxil::ResourceClass::CBuffer: {
+QualType ContainedTy = ResType->getContainedType();
+if (ContainedTy.isNull() || !ContainedTy->isStructureType())
farzonl wrote:
why would we return nullptr if the ContainedTy ia not struct? seems like we
could return back a valid llvm::Type for this case?
https://github.com/llvm/llvm-project/pull/124886
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[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/124886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 41bcb19 - Revert "Reapply "[Driver][ROCm][OpenMP] Fix default ockl linking for OpenMP."…"
Author: Saiyedul Islam
Date: 2025-02-12T20:21:43+05:30
New Revision: 41bcb19c3c8e4a6a37d1d1d1866cf7d4f7806f54
URL:
https://github.com/llvm/llvm-project/commit/41bcb19c3c8e4a6a37d1d1d1866cf7d4f7806f54
DIFF:
https://github.com/llvm/llvm-project/commit/41bcb19c3c8e4a6a37d1d1d1866cf7d4f7806f54.diff
LOG: Revert "Reapply "[Driver][ROCm][OpenMP] Fix default ockl linking for
OpenMP."…"
This reverts commit 46f1bab7930cb118c61bf5ff221790240ec07512.
Added:
Modified:
clang/lib/Driver/ToolChains/AMDGPU.cpp
clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
clang/lib/Driver/ToolChains/ROCm.h
clang/test/Driver/amdgpu-openmp-sanitize-options.c
clang/test/Driver/hip-sanitize-options.hip
Removed:
diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 8d5cb91ebad9a..e66e5a32e58ac 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -950,7 +950,13 @@ void ROCMToolChain::addClangTargetOptions(
ABIVer))
return;
+ std::tuple GPUSan(
+ DriverArgs.hasFlag(options::OPT_fgpu_sanitize,
+ options::OPT_fno_gpu_sanitize, true),
+ getSanitizerArgs(DriverArgs));
+
bool Wave64 = isWave64(DriverArgs, Kind);
+
// TODO: There are way too many flags that change this. Do we need to check
// them all?
bool DAZ = DriverArgs.hasArg(options::OPT_cl_denorms_are_zero) ||
@@ -963,12 +969,6 @@ void ROCMToolChain::addClangTargetOptions(
bool CorrectSqrt =
DriverArgs.hasArg(options::OPT_cl_fp32_correctly_rounded_divide_sqrt);
- // GPU Sanitizer currently only supports ASan and is enabled through host
- // ASan.
- bool GPUSan = DriverArgs.hasFlag(options::OPT_fgpu_sanitize,
- options::OPT_fno_gpu_sanitize, true) &&
-getSanitizerArgs(DriverArgs).needsAsanRt();
-
// Add the OpenCL specific bitcode library.
llvm::SmallVector BCLibs;
BCLibs.emplace_back(RocmInstallation->getOpenCLPath().str());
@@ -1009,25 +1009,30 @@ llvm::SmallVector
RocmInstallationDetector::getCommonBitcodeLibs(
const llvm::opt::ArgList &DriverArgs, StringRef LibDeviceFile, bool Wave64,
bool DAZ, bool FiniteOnly, bool UnsafeMathOpt, bool FastRelaxedMath,
-bool CorrectSqrt, DeviceLibABIVersion ABIVer, bool GPUSan,
-bool isOpenMP) const {
+bool CorrectSqrt, DeviceLibABIVersion ABIVer,
+const std::tuple &GPUSan,
+bool isOpenMP = false) const {
llvm::SmallVector BCLibs;
+ auto GPUSanEnabled = [GPUSan]() { return std::get(GPUSan); };
auto AddBCLib = [&](ToolChain::BitCodeLibraryInfo BCLib,
bool Internalize = true) {
BCLib.ShouldInternalize = Internalize;
BCLibs.emplace_back(BCLib);
};
auto AddSanBCLibs = [&]() {
-if (GPUSan)
- AddBCLib(getAsanRTLPath(), false);
+if (GPUSanEnabled()) {
+ auto SanArgs = std::get(GPUSan);
+ if (SanArgs.needsAsanRt())
+AddBCLib(getAsanRTLPath(), false);
+}
};
AddSanBCLibs();
AddBCLib(getOCMLPath());
if (!isOpenMP)
AddBCLib(getOCKLPath());
- else if (GPUSan && isOpenMP)
+ else if (GPUSanEnabled() && isOpenMP)
AddBCLib(getOCKLPath(), false);
AddBCLib(getDenormalsAreZeroPath(DAZ));
AddBCLib(getUnsafeMathPath(UnsafeMathOpt || FastRelaxedMath));
@@ -1059,6 +1064,10 @@ ROCMToolChain::getCommonDeviceLibNames(const
llvm::opt::ArgList &DriverArgs,
// If --hip-device-lib is not set, add the default bitcode libraries.
// TODO: There are way too many flags that change this. Do we need to check
// them all?
+ std::tuple GPUSan(
+ DriverArgs.hasFlag(options::OPT_fgpu_sanitize,
+ options::OPT_fno_gpu_sanitize, false),
+ getSanitizerArgs(DriverArgs));
bool DAZ = DriverArgs.hasFlag(options::OPT_fgpu_flush_denormals_to_zero,
options::OPT_fno_gpu_flush_denormals_to_zero,
getDefaultDenormsAreZeroForTarget(Kind));
@@ -1074,12 +1083,6 @@ ROCMToolChain::getCommonDeviceLibNames(const
llvm::opt::ArgList &DriverArgs,
options::OPT_fno_hip_fp32_correctly_rounded_divide_sqrt, true);
bool Wave64 = isWave64(DriverArgs, Kind);
- // GPU Sanitizer currently only supports ASan and is enabled through host
- // ASan.
- bool GPUSan = DriverArgs.hasFlag(options::OPT_fgpu_sanitize,
- options::OPT_fno_gpu_sanitize, true) &&
-getSanitizerArgs(DriverArgs).needsAsanRt();
-
return RocmInstallation->getCommonBitcodeLibs(
DriverArgs, LibDeviceFile, Wave64, DAZ, FiniteOnly, UnsafeMathOpt,
FastRelaxedMath, CorrectSqrt, ABIVer, GPUSan, isOpenMP);
@@ -1092,12 +1095,11 @@ bool AMDGPUToolChain::shouldSkipSanitizeOption(
if (TargetID.empty())
return false;
Option O = A->getOption();
-
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -0,0 +1,201 @@
+//===-
HLSLTargetInto.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "HLSLTargetInfo.h"
+#include "CGHLSLRuntime.h"
+#include "TargetInfo.h"
+#include "clang/AST/DeclCXX.h"
+
+//===--===//
+// Target codegen info implementation common between DirectX and SPIR/SPIR-V.
+//===--===//
+
+namespace {
+
+// Creates a new array type with the same dimentions
+// but with the new element type.
+static llvm::Type *
+createArrayWithNewElementType(CodeGenModule &CGM,
+ const ConstantArrayType *ArrayType,
+ llvm::Type *NewElemType) {
+ const clang::Type *ArrayElemType =
ArrayType->getArrayElementTypeNoTypeQual();
+ if (ArrayElemType->isConstantArrayType())
+NewElemType = createArrayWithNewElementType(
+CGM, cast(ArrayElemType), NewElemType);
+ return llvm::ArrayType::get(NewElemType, ArrayType->getSExtSize());
+}
+
+// Returns the size of a scalar or vector in bytes/
+static unsigned getScalarOrVectorSize(llvm::Type *Ty) {
farzonl wrote:
This function could use from a more descript name. Below are some suggestions:
```suggestion
static unsigned getScalarOrVectorByteSize(llvm::Type *Ty) {
```
```suggestion
static unsigned getScalarOrVectorStorageSize(llvm::Type *Ty) {
```
```suggestion
static unsigned getScalarOrVectorMemorySize(llvm::Type *Ty) {
```
https://github.com/llvm/llvm-project/pull/124886
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[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/124886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -0,0 +1,201 @@
+//===-
HLSLTargetInto.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "HLSLTargetInfo.h"
+#include "CGHLSLRuntime.h"
+#include "TargetInfo.h"
+#include "clang/AST/DeclCXX.h"
+
+//===--===//
+// Target codegen info implementation common between DirectX and SPIR/SPIR-V.
+//===--===//
+
+namespace {
+
+// Creates a new array type with the same dimentions
+// but with the new element type.
+static llvm::Type *
+createArrayWithNewElementType(CodeGenModule &CGM,
+ const ConstantArrayType *ArrayType,
+ llvm::Type *NewElemType) {
+ const clang::Type *ArrayElemType =
ArrayType->getArrayElementTypeNoTypeQual();
+ if (ArrayElemType->isConstantArrayType())
+NewElemType = createArrayWithNewElementType(
+CGM, cast(ArrayElemType), NewElemType);
+ return llvm::ArrayType::get(NewElemType, ArrayType->getSExtSize());
+}
+
+// Returns the size of a scalar or vector in bytes/
+static unsigned getScalarOrVectorSize(llvm::Type *Ty) {
+ assert(Ty->isVectorTy() || Ty->isIntegerTy() || Ty->isFloatingPointTy());
+ if (Ty->isVectorTy()) {
+llvm::FixedVectorType *FVT = cast(Ty);
+return FVT->getNumElements() *
+ (FVT->getElementType()->getScalarSizeInBits() / 8);
+ }
+ return Ty->getScalarSizeInBits() / 8;
+}
+
+} // namespace
+
+// Creates a layout type for given struct with HLSL constant buffer layout
+// taking into account Packoffsets, if provided.
+// Previously created layout types are cached in CGHLSLRuntime because
+// TargetCodeGenInto info is cannot store any data
+// (CGM.getTargetCodeGenInfo() returns a const reference to
TargetCondegenInfo).
+//
+// The function iterates over all fields of the StructType (including base
+// classes), converts each field to its corresponding LLVM type and calculated
+// it's HLSL constant bufffer layout (offset and size). Any embedded struct (or
+// arrays of structs) are converted to target layout types as well.
+llvm::Type *CommonHLSLTargetCodeGenInfo::createHLSLBufferLayoutType(
+CodeGenModule &CGM, const RecordType *StructType,
+const SmallVector *Packoffsets) const {
+
+ // check if we already have the layout type for this struct
+ if (llvm::Type *Ty =
CGM.getHLSLRuntime().getHLSLBufferLayoutType(StructType))
+return Ty;
+
+ SmallVector Layout;
+ SmallVector LayoutElements;
+ unsigned Index = 0; // packoffset index
+ unsigned EndOffset = 0;
+
+ // reserve first spot in the layout vector for buffer size
+ Layout.push_back(0);
+
+ // iterate over all fields of the record, including fields on base classes
+ llvm::SmallVector RecordTypes;
+ RecordTypes.push_back(StructType);
+ while (RecordTypes.back()->getAsCXXRecordDecl()->getNumBases()) {
+CXXRecordDecl *D = RecordTypes.back()->getAsCXXRecordDecl();
+assert(D->getNumBases() == 1 &&
+ "HLSL doesn't support multiple inheritance");
+RecordTypes.push_back(D->bases_begin()->getType()->getAs());
+ }
+ while (!RecordTypes.empty()) {
+const RecordType *RT = RecordTypes.back();
+RecordTypes.pop_back();
+
+for (const auto *FD : RT->getDecl()->fields()) {
+ assert(!Packoffsets || Index < Packoffsets->size() &&
+ "number of elements in layout struct does not
"
+ "match number of packoffset annotations");
+ // Size of element; for arrays this is a size of a single element in the
+ // array. Total array size of calculated as (ArrayCount-1) * ArrayStride
+
+ // ElemSize.
+ unsigned ElemSize = 0;
+
+ unsigned ElemOffset = 0;
+ unsigned ArrayCount = 1;
+ unsigned ArrayStride = 0;
+ unsigned NextRowOffset = llvm::alignTo(EndOffset, 16U);
+ llvm::Type *ElemLayoutTy = nullptr;
+
+ QualType FieldTy = FD->getType();
+
+ if (FieldTy->isConstantArrayType()) {
+// Unwrap array to find the element type and get combined array size.
+QualType Ty = FieldTy;
+while (Ty->isConstantArrayType()) {
+ const ConstantArrayType *ArrayTy = cast(Ty);
+ ArrayCount *= ArrayTy->getSExtSize();
+ Ty = ArrayTy->getElementType();
+}
+// For array of structures, create a new array with a layout type
+// instead of the structure type.
+if (Ty->isStructureType()) {
+ llvm::Type *NewTy = cast(
+ createHLSLBufferLayoutType(CGM, Ty->getAsStructureType()));
+ if (!NewTy)
+return nullptr;
+ asser
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -0,0 +1,39 @@
+//===- HLSLTargetInfo.h
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABIInfoImpl.h"
+#include "TargetInfo.h"
+
+using namespace clang;
+using namespace clang::CodeGen;
+
+//===--===//
+// Target codegen info implementation common between DirectX and SPIR/SPIR-V.
+//===--===//
+
+class CommonHLSLTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+ CommonHLSLTargetCodeGenInfo(std::unique_ptr Info)
+ : TargetCodeGenInfo(std::move(Info)) {}
+
+ // Returns LLVM target extension type "dx.Layout" or "spv.Layout"
+ // for given structure type and layout data. The first number in
+ // the Layout is the size followed by offsets for each struct element.
+ virtual llvm::Type *getHLSLLayoutType(CodeGenModule &CGM,
+llvm::StructType *LayoutStructTy,
+SmallVector Layout) const {
+return nullptr;
farzonl wrote:
Do we need a todo here? Maybe an issue tracking that this needs an
implementation?
https://github.com/llvm/llvm-project/pull/124886
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[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -0,0 +1,49 @@ +; ModuleID = 'C:\llvm-project\clang\test\CodeGenHLSL\cbuffer_and_namespaces.hlsl' farzonl wrote: delete? https://github.com/llvm/llvm-project/pull/124886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -0,0 +1,49 @@ +; ModuleID = 'C:\llvm-project\clang\test\CodeGenHLSL\cbuffer_and_namespaces.hlsl' +source_filename = "C:\\llvm-project\\clang\\test\\CodeGenHLSL\\cbuffer_and_namespaces.hlsl" farzonl wrote: delete? https://github.com/llvm/llvm-project/pull/124886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
ritter-x2a wrote: Let me know if you think that this PR should also update labels and file names like, [for example](https://github.com/llvm/llvm-project/blob/7647f478c3244f39e92b99ec07667595f86b84ff/llvm/docs/AMDGPU/gfx940_imm16_0533c2.rst?plain=1#L8), `gfx940_imm16_0533c2` (and consequently break existing URLs like https://llvm.org/docs/AMDGPU/gfx940_imm16_0533c2.html ) https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Fabian Ritter (ritter-x2a) Changes gfx940 and gfx941 are no longer supported. This is the last one of a series of PRs to remove them from the code base. The ISA documentation still contains a lot of links and file names with the "gfx940" identifier. Changing them to "gfx942" is probably not worth the cost of breaking all URLs to these pages that users might have saved in the past. For SWDEV-512631 --- Full diff: https://github.com/llvm/llvm-project/pull/126906.diff 1 Files Affected: - (modified) llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst (+2-2) ``diff diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst index 90797499dec22..7603bcc95383b 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst @@ -6,7 +6,7 @@ ** -Syntax of gfx940 Instructions +Syntax of gfx942 Instructions .. contents:: @@ -15,7 +15,7 @@ Syntax of gfx940 Instructions Introduction -This document describes the syntax of gfx940 instructions. +This document describes the syntax of gfx942 instructions. Notation `` https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
https://github.com/ritter-x2a ready_for_review https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Define the HLSLRootSignature Attr (PR #123985)
@@ -647,6 +648,40 @@ void SemaHLSL::emitLogicalOperatorFixIt(Expr *LHS, Expr
*RHS,
<< NewFnName << FixItHint::CreateReplacement(FullRange, OS.str());
}
+void SemaHLSL::handleRootSignatureAttr(Decl *D, const ParsedAttr &AL) {
+ if (AL.getNumArgs() != 1)
+return;
+
+ StringRef Signature;
+ if (!SemaRef.checkStringLiteralArgumentAttr(AL, 0, Signature))
+return;
+
+ SourceLocation Loc = AL.getArgAsExpr(0)->getExprLoc();
+ // FIXME: pass down below to lexer when fp is supported
farzonl wrote:
Do you have a ticket tracking this?
https://github.com/llvm/llvm-project/pull/123985
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[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/124886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
farzonl wrote: Really appreciate your judicious use of comments. Helped me understand why you were doing certain things. Most of what I found seemed minor so LGTM. https://github.com/llvm/llvm-project/pull/124886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Constant buffers codegen (PR #124886)
@@ -0,0 +1,201 @@
+//===-
HLSLTargetInto.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "HLSLTargetInfo.h"
+#include "CGHLSLRuntime.h"
+#include "TargetInfo.h"
+#include "clang/AST/DeclCXX.h"
+
+//===--===//
+// Target codegen info implementation common between DirectX and SPIR/SPIR-V.
+//===--===//
+
+namespace {
+
+// Creates a new array type with the same dimentions
+// but with the new element type.
+static llvm::Type *
+createArrayWithNewElementType(CodeGenModule &CGM,
+ const ConstantArrayType *ArrayType,
+ llvm::Type *NewElemType) {
+ const clang::Type *ArrayElemType =
ArrayType->getArrayElementTypeNoTypeQual();
+ if (ArrayElemType->isConstantArrayType())
+NewElemType = createArrayWithNewElementType(
+CGM, cast(ArrayElemType), NewElemType);
+ return llvm::ArrayType::get(NewElemType, ArrayType->getSExtSize());
+}
+
+// Returns the size of a scalar or vector in bytes/
+static unsigned getScalarOrVectorSize(llvm::Type *Ty) {
+ assert(Ty->isVectorTy() || Ty->isIntegerTy() || Ty->isFloatingPointTy());
+ if (Ty->isVectorTy()) {
+llvm::FixedVectorType *FVT = cast(Ty);
+return FVT->getNumElements() *
+ (FVT->getElementType()->getScalarSizeInBits() / 8);
+ }
+ return Ty->getScalarSizeInBits() / 8;
+}
+
+} // namespace
+
+// Creates a layout type for given struct with HLSL constant buffer layout
+// taking into account Packoffsets, if provided.
+// Previously created layout types are cached in CGHLSLRuntime because
+// TargetCodeGenInto info is cannot store any data
+// (CGM.getTargetCodeGenInfo() returns a const reference to
TargetCondegenInfo).
+//
+// The function iterates over all fields of the StructType (including base
+// classes), converts each field to its corresponding LLVM type and calculated
+// it's HLSL constant bufffer layout (offset and size). Any embedded struct (or
+// arrays of structs) are converted to target layout types as well.
+llvm::Type *CommonHLSLTargetCodeGenInfo::createHLSLBufferLayoutType(
+CodeGenModule &CGM, const RecordType *StructType,
+const SmallVector *Packoffsets) const {
+
+ // check if we already have the layout type for this struct
+ if (llvm::Type *Ty =
CGM.getHLSLRuntime().getHLSLBufferLayoutType(StructType))
+return Ty;
+
+ SmallVector Layout;
+ SmallVector LayoutElements;
+ unsigned Index = 0; // packoffset index
+ unsigned EndOffset = 0;
+
+ // reserve first spot in the layout vector for buffer size
+ Layout.push_back(0);
+
+ // iterate over all fields of the record, including fields on base classes
+ llvm::SmallVector RecordTypes;
+ RecordTypes.push_back(StructType);
+ while (RecordTypes.back()->getAsCXXRecordDecl()->getNumBases()) {
+CXXRecordDecl *D = RecordTypes.back()->getAsCXXRecordDecl();
+assert(D->getNumBases() == 1 &&
farzonl wrote:
We do a variation of this assert across the code base. Saw it three times in
PRs in last two days. Is there a place we can check for multiple inheritance
once and not have to do so many checks for it later.
https://github.com/llvm/llvm-project/pull/124886
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[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)
https://github.com/ritter-x2a unassigned https://github.com/llvm/llvm-project/pull/126878 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Fabian Ritter (ritter-x2a)
Changes
This was only used for gfx940 and gfx941, which have since been removed.
For SWDEV-512631
---
Full diff: https://github.com/llvm/llvm-project/pull/126878.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (-6)
- (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (-3)
- (modified) llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp (-20)
``diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 3aabca49b249e..effc8d2ed6b49 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1040,12 +1040,6 @@ def FeatureVALUTransUseHazard :
SubtargetFeature<"valu-trans-use-hazard",
"Hazard when TRANS instructions are closely followed by a use of the result"
>;
-def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
- "HasForceStoreSC0SC1",
- "true",
- "Has SC0 and SC1 on stores"
->;
-
def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
"HasSALUFloatInsts",
"true",
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index f7c5c472c93a5..6664a70572ded 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -246,7 +246,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasMADIntraFwdBug = false;
bool HasVOPDInsts = false;
bool HasVALUTransUseHazard = false;
- bool HasForceStoreSC0SC1 = false;
bool HasRequiredExportPriority = false;
bool HasVmemWriteVgprInOrder = false;
bool HasAshrPkInsts = false;
@@ -1264,8 +1263,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasCvtScaleForwardingHazard() const { return GFX950Insts; }
- bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; }
-
bool requiresCodeObjectV6() const { return RequiresCOV6; }
bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 79fb36acc0ea7..34953f9c08db7 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -359,11 +359,6 @@ class SICacheControl {
/// Virtual destructor to allow derivations to be deleted.
virtual ~SICacheControl() = default;
-
- virtual bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
- MachineBasicBlock::iterator &MI) const {
-return false;
- }
};
class SIGfx6CacheControl : public SICacheControl {
@@ -517,20 +512,6 @@ class SIGfx940CacheControl : public SIGfx90ACacheControl {
bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, bool
IsCrossAddrSpaceOrdering,
Position Pos) const override;
-
- bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
- MachineBasicBlock::iterator &MI) const override {
-bool Changed = false;
-if (ST.hasForceStoreSC0SC1() &&
-(MOI.getInstrAddrSpace() & (SIAtomicAddrSpace::SCRATCH |
-SIAtomicAddrSpace::GLOBAL |
-SIAtomicAddrSpace::OTHER)) !=
- SIAtomicAddrSpace::NONE) {
- Changed |= enableSC0Bit(MI);
- Changed |= enableSC1Bit(MI);
-}
-return Changed;
- }
};
class SIGfx10CacheControl : public SIGfx7CacheControl {
@@ -2820,7 +2801,6 @@ bool
SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
Changed |= expandLoad(*MOI, MI);
else if (const auto &MOI = MOA.getStoreInfo(MI)) {
Changed |= expandStore(*MOI, MI);
-Changed |= CC->tryForceStoreSC0SC1(*MOI, MI);
} else if (const auto &MOI = MOA.getAtomicFenceInfo(MI))
Changed |= expandAtomicFence(*MOI, MI);
else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI))
``
https://github.com/llvm/llvm-project/pull/126878
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[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)
ritter-x2a wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/126878?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#126878** https://app.graphite.dev/github/pr/llvm/llvm-project/126878?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/126878?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#126763** https://app.graphite.dev/github/pr/llvm/llvm-project/126763?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#126762** https://app.graphite.dev/github/pr/llvm/llvm-project/126762?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125836** https://app.graphite.dev/github/pr/llvm/llvm-project/125836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125827** https://app.graphite.dev/github/pr/llvm/llvm-project/125827?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125826** https://app.graphite.dev/github/pr/llvm/llvm-project/125826?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125711** https://app.graphite.dev/github/pr/llvm/llvm-project/125711?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/126878 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (PR #126763)
ritter-x2a wrote: > Should just leave the subtarget feature name alone. It's not worth the > trouble, and this will now start spewing warnings on old IR (due to > unnecessary target-features spam clang should stop emitting). It really > should have been named 94-insts, but I think it's best to leave it alone @arsenm @rampitec I reverted the changes related to that with the most recent commit on this PR. https://github.com/llvm/llvm-project/pull/126763 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (PR #126763)
@@ -1619,28 +1613,6 @@ def FeatureISAVersion9_5_Common : FeatureSet< FeatureAtomicBufferPkAddBF16Inst ])>; -def FeatureISAVersion9_4_0 : FeatureSet< - !listconcat(FeatureISAVersion9_4_Common.Features, -[ - FeatureAddressableLocalMemorySize65536, - FeatureForceStoreSC0SC1, ritter-x2a wrote: I reverted that part in the most recent commit on this PR as well and opened #126878 to remove FeatureForceStoreSC0SC1 separately. https://github.com/llvm/llvm-project/pull/126763 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in MLIR (PR #125836)
@@ -602,7 +602,7 @@ def AMDGPU_MFMAOp : order (that is, v[0] will go to arg[7:0], v[1] to arg[15:8] and so on). The negateA, negateB, and negateC flags are only supported for double-precision -operations on gfx940+. +operations on gfx942+. ritter-x2a wrote: Changed to gfx94x https://github.com/llvm/llvm-project/pull/125836 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)
https://github.com/ritter-x2a ready_for_review https://github.com/llvm/llvm-project/pull/126878 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs (PR #126887)
https://github.com/ritter-x2a created https://github.com/llvm/llvm-project/pull/126887 gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR removes all documentation occurrences of gfx940/gfx941 except for the gfx940 ISA description, which will be the subject of a separate PR. For SWDEV-512631 >From 12460f083060a7e330975a7354bdc019f670f386 Mon Sep 17 00:00:00 2001 From: Fabian Ritter Date: Wed, 12 Feb 2025 05:45:01 -0500 Subject: [PATCH] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR removes all documentation occurrences of gfx940/gfx941 except for the gfx940 ISA description, which will be the subject of a separate PR. For SWDEV-512631 --- llvm/docs/AMDGPUOperandSyntax.rst | 4 +- llvm/docs/AMDGPUUsage.rst | 97 ++- 2 files changed, 34 insertions(+), 67 deletions(-) diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst index ff6ec6cf71ff2..e8a76322fe76a 100644 --- a/llvm/docs/AMDGPUOperandSyntax.rst +++ b/llvm/docs/AMDGPUOperandSyntax.rst @@ -63,7 +63,7 @@ Note: *N* and *K* must satisfy the following conditions: * 0 <= *K* <= 255. * *K-N+1* must be in the range from 1 to 12 or equal to 16 or 32. -GFX90A and GFX940 have an additional alignment requirement: +GFX90A and GFX942 have an additional alignment requirement: pairs of *vector* registers must be even-aligned (first register must be even). @@ -183,7 +183,7 @@ Note: *N* and *K* must satisfy the following conditions: * 0 <= *K* <= 255. * *K-N+1* must be in the range from 1 to 12 or equal to 16 or 32. -GFX90A and GFX940 have an additional alignment requirement: +GFX90A and GFX942 have an additional alignment requirement: pairs of *accumulator* registers must be even-aligned (first register must be even). diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 83ec1eecb6e5e..14b3b6fce9e70 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -323,7 +323,7 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following Add product names. - **GCN GFX9 (Vega)** [AMD-GCN-GFX900-GFX904-VEGA]_ [AMD-GCN-GFX906-VEGA7NM]_ [AMD-GCN-GFX908-CDNA1]_ [AMD-GCN-GFX90A-CDNA2]_ [AMD-GCN-GFX940-GFX942-CDNA3]_ + **GCN GFX9 (Vega)** [AMD-GCN-GFX900-GFX904-VEGA]_ [AMD-GCN-GFX906-VEGA7NM]_ [AMD-GCN-GFX908-CDNA1]_ [AMD-GCN-GFX90A-CDNA2]_ [AMD-GCN-GFX942-CDNA3]_ --- ``gfx900`` ``amdgcn`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega flat - *pal-amdhsa*Frontier Edition @@ -378,20 +378,6 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following - Ryzen 3 Pro 4350G - Ryzen 3 Pro 4350GE - ``gfx940`` ``amdgcn`` dGPU - sramecc - Architected *TBA* -- tgsplit flat -- xnack scratch .. TODO:: -- kernarg preload - Packed - work-item Add product -IDs names. - - ``gfx941`` ``amdgcn`` dGPU - sramecc - Architected *TBA* -- tgsplit flat -- xnack scratch .. TODO:: -- kernarg preload - Packed - work-item Add product -IDs names. - ``gfx942`` ``amdgcn`` dGPU - sramecc - Architected - AMD Instinct MI300X - tgsplit flat - AMD Instin
[llvm-branch-commits] [llvm] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs (PR #126887)
ritter-x2a wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/126887?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#126887** https://app.graphite.dev/github/pr/llvm/llvm-project/126887?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/126887?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#126878** https://app.graphite.dev/github/pr/llvm/llvm-project/126878?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#126763** https://app.graphite.dev/github/pr/llvm/llvm-project/126763?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#126762** https://app.graphite.dev/github/pr/llvm/llvm-project/126762?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125836** https://app.graphite.dev/github/pr/llvm/llvm-project/125836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125827** https://app.graphite.dev/github/pr/llvm/llvm-project/125827?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125826** https://app.graphite.dev/github/pr/llvm/llvm-project/125826?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#125711** https://app.graphite.dev/github/pr/llvm/llvm-project/125711?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/126887 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [polly] [Polly] Introduce PhaseManager and remove LPM support (PR #125442)
Meinersbur wrote: OK, please signal your LGTM when you are ready https://github.com/llvm/llvm-project/pull/125442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs (PR #126887)
llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Fabian Ritter (ritter-x2a) Changes gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR removes all documentation occurrences of gfx940/gfx941 except for the gfx940 ISA description, which will be the subject of a separate PR. For SWDEV-512631 --- Patch is 24.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/126887.diff 2 Files Affected: - (modified) llvm/docs/AMDGPUOperandSyntax.rst (+2-2) - (modified) llvm/docs/AMDGPUUsage.rst (+32-65) ``diff diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst index ff6ec6cf71ff2..e8a76322fe76a 100644 --- a/llvm/docs/AMDGPUOperandSyntax.rst +++ b/llvm/docs/AMDGPUOperandSyntax.rst @@ -63,7 +63,7 @@ Note: *N* and *K* must satisfy the following conditions: * 0 <= *K* <= 255. * *K-N+1* must be in the range from 1 to 12 or equal to 16 or 32. -GFX90A and GFX940 have an additional alignment requirement: +GFX90A and GFX942 have an additional alignment requirement: pairs of *vector* registers must be even-aligned (first register must be even). @@ -183,7 +183,7 @@ Note: *N* and *K* must satisfy the following conditions: * 0 <= *K* <= 255. * *K-N+1* must be in the range from 1 to 12 or equal to 16 or 32. -GFX90A and GFX940 have an additional alignment requirement: +GFX90A and GFX942 have an additional alignment requirement: pairs of *accumulator* registers must be even-aligned (first register must be even). diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 83ec1eecb6e5e..14b3b6fce9e70 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -323,7 +323,7 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following Add product names. - **GCN GFX9 (Vega)** [AMD-GCN-GFX900-GFX904-VEGA]_ [AMD-GCN-GFX906-VEGA7NM]_ [AMD-GCN-GFX908-CDNA1]_ [AMD-GCN-GFX90A-CDNA2]_ [AMD-GCN-GFX940-GFX942-CDNA3]_ + **GCN GFX9 (Vega)** [AMD-GCN-GFX900-GFX904-VEGA]_ [AMD-GCN-GFX906-VEGA7NM]_ [AMD-GCN-GFX908-CDNA1]_ [AMD-GCN-GFX90A-CDNA2]_ [AMD-GCN-GFX942-CDNA3]_ --- ``gfx900`` ``amdgcn`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega flat - *pal-amdhsa*Frontier Edition @@ -378,20 +378,6 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following - Ryzen 3 Pro 4350G - Ryzen 3 Pro 4350GE - ``gfx940`` ``amdgcn`` dGPU - sramecc - Architected *TBA* -- tgsplit flat -- xnack scratch .. TODO:: -- kernarg preload - Packed - work-item Add product -IDs names. - - ``gfx941`` ``amdgcn`` dGPU - sramecc - Architected *TBA* -- tgsplit flat -- xnack scratch .. TODO:: -- kernarg preload - Packed - work-item Add product -IDs names. - ``gfx942`` ``amdgcn`` dGPU - sramecc - Architected - AMD Instinct MI300X - tgsplit flat - AMD Instinct MI300A - xnack scratch @@ -583,10 +569,10 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor - ``v_dot2_f32_f16`` - ``gfx9-4-generic`` ``amdgcn`` - ``gfx940`` - s
[llvm-branch-commits] [clang] release/20.x: [clang-format] Fix a crash on parsing requires clause (#125021) (PR #126843)
https://github.com/rymiel approved this pull request. https://github.com/llvm/llvm-project/pull/126843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs (PR #126887)
https://github.com/ritter-x2a ready_for_review https://github.com/llvm/llvm-project/pull/126887 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [polly] [Polly] Introduce PhaseManager and remove LPM support (PR #125442)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/125442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
llvmbot wrote:
@llvm/pr-subscribers-llvm-selectiondag
Author: None (llvmbot)
Changes
Backport bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c
Requested by: @davemgreen
---
Full diff: https://github.com/llvm/llvm-project/pull/126891.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h (+1)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+18)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+148)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+118)
``diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index f13f70e66cfaa..b58c160b5c8b8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -880,6 +880,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BITCAST(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
+ SDValue ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
SDValue ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 1000235ab4061..7c77e8a72c8ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -773,6 +773,10 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N,
unsigned OpNo) {
case ISD::LLRINT:
Res = ScalarizeVecOp_UnaryOp(N);
break;
+ case ISD::FP_TO_SINT_SAT:
+ case ISD::FP_TO_UINT_SAT:
+Res = ScalarizeVecOp_UnaryOpWithExtraInput(N);
+break;
case ISD::STRICT_SINT_TO_FP:
case ISD::STRICT_UINT_TO_FP:
case ISD::STRICT_FP_TO_SINT:
@@ -880,6 +884,20 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode
*N) {
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
}
+/// Same as ScalarizeVecOp_UnaryOp with an extra operand (for example a
+/// typesize).
+SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N) {
+ assert(N->getValueType(0).getVectorNumElements() == 1 &&
+ "Unexpected vector type!");
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));
+ SDValue Op =
+ DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0).getScalarType(),
+ Elt, N->getOperand(1));
+ // Revectorize the result so the types line up with what the uses of this
+ // expression expect.
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
+}
+
/// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
/// Do the strict FP operation on the element instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N) {
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 9ef6d61c350ec..b2b3430f4d85e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -5548,3 +5548,151 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x
double> %f) {
%x = call <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f)
ret <16 x i16> %x
}
+
+define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
+; CHECK-SD-LABEL: test_signed_v2f128_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:sub sp, sp, #96
+; CHECK-SD-NEXT:stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-SD-NEXT:stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT:.cfi_def_cfa_offset 96
+; CHECK-SD-NEXT:.cfi_offset w19, -8
+; CHECK-SD-NEXT:.cfi_offset w20, -16
+; CHECK-SD-NEXT:.cfi_offset w21, -24
+; CHECK-SD-NEXT:.cfi_offset w30, -32
+; CHECK-SD-NEXT:mov v2.16b, v1.16b
+; CHECK-SD-NEXT:stp q1, q0, [sp, #32] // 32-byte Folded Spill
+; CHECK-SD-NEXT:adrp x8, .LCPI86_0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_0]
+; CHECK-SD-NEXT:mov v0.16b, v2.16b
+; CHECK-SD-NEXT:str q1, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT:bl __getf2
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:mov w19, w0
+; CHECK-SD-NEXT:bl __fixtfdi
+; CHECK-SD-NEXT:adrp x8, .LCPI86_1
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:cmp w19, #0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_1]
+; CHECK-SD-NEXT:mov x20, #-9223372036854775808 // =0x8000
+; CHECK-SD-NEXT:csel x19, x20, x0, lt
+; CHECK-SD-NEXT:str q1, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT:bl __gttf2
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:mov x21, #9223372036854775807 // =0x7fff
+; CHECK-SD-NEXT:cmp w0, #0
+; CHECK-SD-NEXT:csel x19, x21,
[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)
https://github.com/skatrak approved this pull request. LGTM, thank you. https://github.com/llvm/llvm-project/pull/117046 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 7bc1b9a - Revert "[Clang][CMake][MSVC] Install PDBs alongside executables (#126675)"
Author: Miguel A. Arroyo
Date: 2025-02-12T08:05:36-08:00
New Revision: 7bc1b9a09073b6b40ce3c12134391c5697af29cf
URL:
https://github.com/llvm/llvm-project/commit/7bc1b9a09073b6b40ce3c12134391c5697af29cf
DIFF:
https://github.com/llvm/llvm-project/commit/7bc1b9a09073b6b40ce3c12134391c5697af29cf.diff
LOG: Revert "[Clang][CMake][MSVC] Install PDBs alongside executables (#126675)"
This reverts commit acd34d90d3acd9dd260fdb93c54f70c222e26875.
Added:
Modified:
clang/cmake/modules/AddClang.cmake
Removed:
diff --git a/clang/cmake/modules/AddClang.cmake
b/clang/cmake/modules/AddClang.cmake
index 02f26b6d861ad..cdc8bd5cd503b 100644
--- a/clang/cmake/modules/AddClang.cmake
+++ b/clang/cmake/modules/AddClang.cmake
@@ -138,10 +138,6 @@ macro(add_clang_library name)
ARCHIVE DESTINATION lib${LLVM_LIBDIR_SUFFIX}
RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}")
-if (LLVM_ENABLE_PDB)
- install(FILES $ DESTINATION
"${CMAKE_INSTALL_BINDIR}" COMPONENT ${name} OPTIONAL)
-endif()
-
if (NOT LLVM_ENABLE_IDE)
add_llvm_install_targets(install-${lib}
DEPENDS ${lib}
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[llvm-branch-commits] [clang] [flang] [llvm] [mlir] [MLIR][OpenMP] Add LLVM translation support for OpenMP UserDefinedMappers (PR #124746)
@@ -3529,6 +3549,84 @@ static void genMapInfos(llvm::IRBuilderBase &builder,
}
}
+static llvm::Expected
+emitUserDefinedMapper(Operation *declMapperOp, llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation);
+
+static llvm::Expected
+getOrCreateUserDefinedMapperFunc(Operation *declMapperOp,
+ llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation) {
+ static llvm::DenseMap userDefMapperMap;
skatrak wrote:
I think we're still missing a call to
`moduleTranslation.mapFunction(mapperName, *newFn)` before returning from
`emitUserDefinedMapper()`. Otherwise, `getOrCreateUserDefinedMapperFunc()` will
never find the already created functions and always produce a new one
(potentially with the same name).
https://github.com/llvm/llvm-project/pull/124746
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[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
github-actions[bot] wrote: @davemgreen (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/126891 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/126883 >From 2342bb2b004349b466e4473db53d190d797f9ef2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Tue, 11 Feb 2025 17:20:23 +0100 Subject: [PATCH] [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) Add `LLVM_BUILD_TELEMETRY` to the list of flags exposed in `LLVMConfig.cmake`. This fixes telemetry library being misdetected as `OFF` when building LLDB standalone. Fixes bac62ee5b473e70981a6bd9759ec316315fca07d. -- I guess this also needs a backport to 20.x. (cherry picked from commit 2ad9d5f5f01cd4f29788a0cf7b21790df13fca71) --- llvm/cmake/modules/LLVMConfig.cmake.in | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/cmake/modules/LLVMConfig.cmake.in b/llvm/cmake/modules/LLVMConfig.cmake.in index c49f10b9343ff..28655ee3ab87d 100644 --- a/llvm/cmake/modules/LLVMConfig.cmake.in +++ b/llvm/cmake/modules/LLVMConfig.cmake.in @@ -100,6 +100,8 @@ set(LLVM_ENABLE_PIC @LLVM_ENABLE_PIC@) set(LLVM_BUILD_32_BITS @LLVM_BUILD_32_BITS@) +set(LLVM_BUILD_TELEMETRY @LLVM_BUILD_TELEMETRY@) + if (NOT "@LLVM_PTHREAD_LIB@" STREQUAL "") set(LLVM_PTHREAD_LIB "@LLVM_PTHREAD_LIB@") endif() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 2342bb2 - [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710)
Author: Michał Górny Date: 2025-02-12T19:38:51-08:00 New Revision: 2342bb2b004349b466e4473db53d190d797f9ef2 URL: https://github.com/llvm/llvm-project/commit/2342bb2b004349b466e4473db53d190d797f9ef2 DIFF: https://github.com/llvm/llvm-project/commit/2342bb2b004349b466e4473db53d190d797f9ef2.diff LOG: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) Add `LLVM_BUILD_TELEMETRY` to the list of flags exposed in `LLVMConfig.cmake`. This fixes telemetry library being misdetected as `OFF` when building LLDB standalone. Fixes bac62ee5b473e70981a6bd9759ec316315fca07d. -- I guess this also needs a backport to 20.x. (cherry picked from commit 2ad9d5f5f01cd4f29788a0cf7b21790df13fca71) Added: Modified: llvm/cmake/modules/LLVMConfig.cmake.in Removed: diff --git a/llvm/cmake/modules/LLVMConfig.cmake.in b/llvm/cmake/modules/LLVMConfig.cmake.in index c49f10b9343ff..28655ee3ab87d 100644 --- a/llvm/cmake/modules/LLVMConfig.cmake.in +++ b/llvm/cmake/modules/LLVMConfig.cmake.in @@ -100,6 +100,8 @@ set(LLVM_ENABLE_PIC @LLVM_ENABLE_PIC@) set(LLVM_BUILD_32_BITS @LLVM_BUILD_32_BITS@) +set(LLVM_BUILD_TELEMETRY @LLVM_BUILD_TELEMETRY@) + if (NOT "@LLVM_PTHREAD_LIB@" STREQUAL "") set(LLVM_PTHREAD_LIB "@LLVM_PTHREAD_LIB@") endif() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/126883 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
github-actions[bot] wrote: @mgorny (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/126883 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/126881
>From c99d6118fe0d1c323b2a978344491881197c8dee Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Wed, 12 Feb 2025 09:44:26 +0100
Subject: [PATCH] [BOLT] Use getMainExecutable() (#126698)
Use LLVM's getMainExecutable() helper instead of rolling our own. This
will result in standard behavior across platforms, such as making sure
that symlinks are always resolved.
(cherry picked from commit 0abe058d7f99c9c7bbaf4ee98308c5e78d229897)
---
bolt/tools/driver/llvm-bolt.cpp | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/bolt/tools/driver/llvm-bolt.cpp b/bolt/tools/driver/llvm-bolt.cpp
index efa06cd68cb99..f151cf5f63fc5 100644
--- a/bolt/tools/driver/llvm-bolt.cpp
+++ b/bolt/tools/driver/llvm-bolt.cpp
@@ -173,16 +173,6 @@ void boltMode(int argc, char **argv) {
}
}
-static std::string GetExecutablePath(const char *Argv0) {
- SmallString<256> ExecutablePath(Argv0);
- // Do a PATH lookup if Argv0 isn't a valid path.
- if (!llvm::sys::fs::exists(ExecutablePath))
-if (llvm::ErrorOr P =
-llvm::sys::findProgramByName(ExecutablePath))
- ExecutablePath = *P;
- return std::string(ExecutablePath);
-}
-
int main(int argc, char **argv) {
// Print a stack trace if we signal out.
sys::PrintStackTraceOnErrorSignal(argv[0]);
@@ -190,7 +180,7 @@ int main(int argc, char **argv) {
llvm_shutdown_obj Y; // Call llvm_shutdown() on exit.
- std::string ToolPath = GetExecutablePath(argv[0]);
+ std::string ToolPath = llvm::sys::fs::getMainExecutable(argv[0], nullptr);
// Initialize targets and assembly printers/parsers.
llvm::InitializeAllTargetInfos();
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[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
github-actions[bot] wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/126881 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
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[llvm-branch-commits] [llvm] cc60c22 - [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799)
Author: David Green
Date: 2025-02-12T11:11:37Z
New Revision: cc60c22a9247423d5e32bd848c405e09b1175a32
URL:
https://github.com/llvm/llvm-project/commit/cc60c22a9247423d5e32bd848c405e09b1175a32
DIFF:
https://github.com/llvm/llvm-project/commit/cc60c22a9247423d5e32bd848c405e09b1175a32.diff
LOG: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799)
We we previously running into problems with fp128 types and certain
integer sizes.
Fixes an issue reported on #124984
(cherry picked from commit bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c)
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index f13f70e66cfaa..b58c160b5c8b8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -880,6 +880,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BITCAST(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
+ SDValue ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N);
SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
SDValue ScalarizeVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 1000235ab4061..7c77e8a72c8ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -773,6 +773,10 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N,
unsigned OpNo) {
case ISD::LLRINT:
Res = ScalarizeVecOp_UnaryOp(N);
break;
+ case ISD::FP_TO_SINT_SAT:
+ case ISD::FP_TO_UINT_SAT:
+Res = ScalarizeVecOp_UnaryOpWithExtraInput(N);
+break;
case ISD::STRICT_SINT_TO_FP:
case ISD::STRICT_UINT_TO_FP:
case ISD::STRICT_FP_TO_SINT:
@@ -880,6 +884,20 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode
*N) {
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
}
+/// Same as ScalarizeVecOp_UnaryOp with an extra operand (for example a
+/// typesize).
+SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOpWithExtraInput(SDNode *N) {
+ assert(N->getValueType(0).getVectorNumElements() == 1 &&
+ "Unexpected vector type!");
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));
+ SDValue Op =
+ DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0).getScalarType(),
+ Elt, N->getOperand(1));
+ // Revectorize the result so the types line up with what the uses of this
+ // expression expect.
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
+}
+
/// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
/// Do the strict FP operation on the element instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N) {
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 9ef6d61c350ec..b2b3430f4d85e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -5548,3 +5548,151 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x
double> %f) {
%x = call <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f)
ret <16 x i16> %x
}
+
+define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
+; CHECK-SD-LABEL: test_signed_v2f128_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:sub sp, sp, #96
+; CHECK-SD-NEXT:stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-SD-NEXT:stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT:.cfi_def_cfa_offset 96
+; CHECK-SD-NEXT:.cfi_offset w19, -8
+; CHECK-SD-NEXT:.cfi_offset w20, -16
+; CHECK-SD-NEXT:.cfi_offset w21, -24
+; CHECK-SD-NEXT:.cfi_offset w30, -32
+; CHECK-SD-NEXT:mov v2.16b, v1.16b
+; CHECK-SD-NEXT:stp q1, q0, [sp, #32] // 32-byte Folded Spill
+; CHECK-SD-NEXT:adrp x8, .LCPI86_0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_0]
+; CHECK-SD-NEXT:mov v0.16b, v2.16b
+; CHECK-SD-NEXT:str q1, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT:bl __getf2
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:mov w19, w0
+; CHECK-SD-NEXT:bl __fixtfdi
+; CHECK-SD-NEXT:adrp x8, .LCPI86_1
+; CHECK-SD-NEXT:ldr q0, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT:cmp w19, #0
+; CHECK-SD-NEXT:ldr q1, [x8, :lo12:.LCPI86_1]
+; CHECK-SD-NEXT:mov x20, #-9223372036854775808 // =0x8000
+; CHE
[llvm-branch-commits] [llvm] release/20.x: [AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799) (PR #126891)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/126891 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SHT_LLVM_FUNC_MAP][CodeGen]Introduce function address map section and emit dynamic instruction count(CodeGen part) (PR #124334)
https://github.com/wlei-llvm updated https://github.com/llvm/llvm-project/pull/124334 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SHT_LLVM_FUNC_MAP][CodeGen]Introduce function address map section and emit dynamic instruction count(CodeGen part) (PR #124334)
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[llvm-branch-commits] [SHT_LLVM_FUNC_MAP][llvm-readobj]Introduce function address map section and emit dynamic instruction count(readobj part) (PR #124333)
https://github.com/wlei-llvm updated https://github.com/llvm/llvm-project/pull/124333 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SHT_LLVM_FUNC_MAP][llvm-readobj]Introduce function address map section and emit dynamic instruction count(readobj part) (PR #124333)
https://github.com/wlei-llvm updated https://github.com/llvm/llvm-project/pull/124333 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclang] Replace createRef with createDup (PR #126683)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/126683 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclang] Replace createRef with createDup (PR #126683)
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[llvm-branch-commits] [libclang] Replace createRef with createDup (PR #126683)
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[llvm-branch-commits] [libclang] Replace createRef with createDup (PR #126683)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/126683 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
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[llvm-branch-commits] [libclang] Replace createRef with createDup (PR #126683)
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[llvm-branch-commits] [libclang] Replace createRef with createDup (PR #126683)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/126683 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SHT_LLVM_FUNC_MAP][llvm-readobj]Introduce function address map section and emit dynamic instruction count(readobj part) (PR #124333)
https://github.com/wlei-llvm updated
https://github.com/llvm/llvm-project/pull/124333
>From 0f1f43a5f19d4055c1896a70e050965b4d309790 Mon Sep 17 00:00:00 2001
From: wlei
Date: Wed, 12 Feb 2025 22:03:21 -0800
Subject: [PATCH] remove irrelevant code
Created using spr 1.3.6-beta.1
---
llvm/tools/llvm-readobj/ELFDumper.cpp | 4
1 file changed, 4 deletions(-)
diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp
b/llvm/tools/llvm-readobj/ELFDumper.cpp
index 5f8c4613dd79f..fcd9842fd1cac 100644
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -7961,10 +7961,6 @@ template void
LLVMELFDumper::printFuncMaps() {
continue;
}
for (const auto &AM : *FuncMapOrErr) {
- // Do not print dead entry where the functon address is zero.
- if (!AM.getFunctionAddress())
-continue;
-
DictScope D(W, "Function");
W.printHex("At", AM.getFunctionAddress());
SmallVector FuncSymIndex =
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[llvm-branch-commits] [lld] [lld][LoongArch] Relax call36/tail36: R_LARCH_CALL36 (PR #123576)
https://github.com/SixWeining approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/123576 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (PR #126763)
@@ -2221,7 +2221,7 @@ The AMDGPU backend uses the following ELF header: ``EF_AMDGPU_MACH_AMDGCN_GFX1035`` 0x03d ``gfx1035`` ``EF_AMDGPU_MACH_AMDGCN_GFX1034`` 0x03e ``gfx1034`` ``EF_AMDGPU_MACH_AMDGCN_GFX90A`` 0x03f ``gfx90a`` - ``EF_AMDGPU_MACH_AMDGCN_GFX940`` 0x040 ``gfx940`` ritter-x2a wrote: @kzhuravl asked me to do it this way, consistently to the other reserved entries https://github.com/llvm/llvm-project/pull/126763 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT][NFC] Simplify parseAggregatedLBREntry (PR #126998)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/126998
>From a3ce5fb3b34ebddda7b68db1a8a288dcb729e319 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Wed, 12 Feb 2025 21:18:05 -0800
Subject: [PATCH] fix build
Created using spr 1.3.4
---
bolt/lib/Profile/DataAggregator.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/bolt/lib/Profile/DataAggregator.cpp
b/bolt/lib/Profile/DataAggregator.cpp
index f30f00ac1dd5e..2df2fa16ecf64 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -1255,11 +1255,10 @@ std::error_code
DataAggregator::parseAggregatedLBREntry() {
while (checkAndConsumeFS()) {
}
- ErrorOr FrequencyOrErr =
+ ErrorOr Frequency =
parseNumberField(FieldSeparator, Type != AggregatedLBREntry::BRANCH);
- if (std::error_code EC = FrequencyOrErr.getError())
+ if (std::error_code EC = Frequency.getError())
return EC;
- uint64_t Frequency = static_cast(FrequencyOrErr.get());
uint64_t Mispreds = 0;
if (Type == AggregatedLBREntry::BRANCH) {
@@ -1283,7 +1282,9 @@ std::error_code DataAggregator::parseAggregatedLBREntry()
{
if (BF)
BF->setHasProfileAvailable();
- AggregatedLBRs.emplace_back(From.get(), To.get(), Frequency, Mispreds, Type);
+ AggregatedLBRs.emplace_back(AggregatedLBREntry{
+ From.get(), To.get(), static_cast(Frequency.get()), Mispreds,
+ Type});
return std::error_code();
}
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[llvm-branch-commits] [clang] [llvm] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (PR #126763)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/126763 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (PR #126763)
@@ -2221,7 +2221,7 @@ The AMDGPU backend uses the following ELF header: ``EF_AMDGPU_MACH_AMDGCN_GFX1035`` 0x03d ``gfx1035`` ``EF_AMDGPU_MACH_AMDGCN_GFX1034`` 0x03e ``gfx1034`` ``EF_AMDGPU_MACH_AMDGCN_GFX90A`` 0x03f ``gfx90a`` - ``EF_AMDGPU_MACH_AMDGCN_GFX940`` 0x040 ``gfx940`` arsenm wrote: Could keep this documented https://github.com/llvm/llvm-project/pull/126763 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)
shiltian wrote: I guess there is no `gfx941` in the doc. https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710) (PR #126883)
https://github.com/JDevlieghere approved this pull request. https://github.com/llvm/llvm-project/pull/126883 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [MLIR][OpenMP] Add LLVM translation support for OpenMP UserDefinedMappers (PR #124746)
https://github.com/TIFitis updated
https://github.com/llvm/llvm-project/pull/124746
>From 7b5c918249a9c29ae586d9f1ccae6b7359fcd793 Mon Sep 17 00:00:00 2001
From: Akash Banerjee
Date: Tue, 28 Jan 2025 13:38:13 +
Subject: [PATCH 1/7] [MLIR][OpenMP] Add LLVM translation support for OpenMP
UserDefinedMappers
This patch adds OpenMPToLLVMIRTranslation support for the OpenMP Declare Mapper
directive.
Since both MLIR and Clang now support custom mappers, I've made the relative
params required instead of optional as well.
Depends on #121005
---
clang/lib/CodeGen/CGOpenMPRuntime.cpp | 11 +-
.../llvm/Frontend/OpenMP/OMPIRBuilder.h | 31 +--
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 70 +++---
.../Frontend/OpenMPIRBuilderTest.cpp | 46 ++--
.../OpenMP/OpenMPToLLVMIRTranslation.cpp | 215 +++---
mlir/test/Target/LLVMIR/omptarget-llvm.mlir | 117 ++
.../fortran/target-custom-mapper.f90 | 46
7 files changed, 437 insertions(+), 99 deletions(-)
create mode 100644 offload/test/offloading/fortran/target-custom-mapper.f90
diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp
b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
index cafaaa364cb76..b919c1f6ac627 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
@@ -8889,8 +8889,8 @@ static void emitOffloadingArraysAndArgs(
return MFunc;
};
OMPBuilder.emitOffloadingArraysAndArgs(
- AllocaIP, CodeGenIP, Info, Info.RTArgs, CombinedInfo, IsNonContiguous,
- ForEndCall, DeviceAddrCB, CustomMapperCB);
+ AllocaIP, CodeGenIP, Info, Info.RTArgs, CombinedInfo, CustomMapperCB,
+ IsNonContiguous, ForEndCall, DeviceAddrCB);
}
/// Check for inner distribute directive.
@@ -9099,9 +9099,10 @@ void CGOpenMPRuntime::emitUserDefinedMapper(const
OMPDeclareMapperDecl *D,
CGM.getCXXABI().getMangleContext().mangleCanonicalTypeName(Ty, Out);
std::string Name = getName({"omp_mapper", TyStr, D->getName()});
- auto *NewFn = OMPBuilder.emitUserDefinedMapper(PrivatizeAndGenMapInfoCB,
- ElemTy, Name, CustomMapperCB);
- UDMMap.try_emplace(D, NewFn);
+ llvm::Expected NewFn = OMPBuilder.emitUserDefinedMapper(
+ PrivatizeAndGenMapInfoCB, ElemTy, Name, CustomMapperCB);
+ assert(NewFn && "Unexpected error in emitUserDefinedMapper");
+ UDMMap.try_emplace(D, *NewFn);
if (CGF)
FunctionUDMMap[CGF->CurFn].push_back(D);
}
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
index d25077cae63e4..151bd36aadaf0 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
@@ -2399,6 +2399,7 @@ class OpenMPIRBuilder {
CurInfo.NonContigInfo.Strides.end());
}
};
+ using MapInfosOrErrorTy = Expected;
/// Callback function type for functions emitting the host fallback code that
/// is executed when the kernel launch fails. It takes an insertion point as
@@ -2475,9 +2476,9 @@ class OpenMPIRBuilder {
/// including base pointers, pointers, sizes, map types, user-defined
mappers.
void emitOffloadingArrays(
InsertPointTy AllocaIP, InsertPointTy CodeGenIP, MapInfosTy
&CombinedInfo,
- TargetDataInfo &Info, bool IsNonContiguous = false,
- function_ref DeviceAddrCB = nullptr,
- function_ref CustomMapperCB = nullptr);
+ TargetDataInfo &Info, function_ref CustomMapperCB,
+ bool IsNonContiguous = false,
+ function_ref DeviceAddrCB = nullptr);
/// Allocates memory for and populates the arrays required for offloading
/// (offload_{baseptrs|ptrs|mappers|sizes|maptypes|mapnames}). Then, it
@@ -2488,9 +2489,9 @@ class OpenMPIRBuilder {
void emitOffloadingArraysAndArgs(
InsertPointTy AllocaIP, InsertPointTy CodeGenIP, TargetDataInfo &Info,
TargetDataRTArgs &RTArgs, MapInfosTy &CombinedInfo,
+ function_ref CustomMapperCB,
bool IsNonContiguous = false, bool ForEndCall = false,
- function_ref DeviceAddrCB = nullptr,
- function_ref CustomMapperCB = nullptr);
+ function_ref DeviceAddrCB = nullptr);
/// Creates offloading entry for the provided entry ID \a ID, address \a
/// Addr, size \a Size, and flags \a Flags.
@@ -2950,12 +2951,12 @@ class OpenMPIRBuilder {
/// \param FuncName Optional param to specify mapper function name.
/// \param CustomMapperCB Optional callback to generate code related to
/// custom mappers.
- Function *emitUserDefinedMapper(
- function_ref
+ Expected emitUserDefinedMapper(
+ function_ref
PrivAndGenMapInfoCB,
llvm::Type *ElemTy, StringRef FuncName,
- function_ref CustomMapperCB = nullptr);
+ function_ref CustomMapperCB);
/// Generator for '#omp target data'
///
@@ -2969,21 +2970,21 @@ class OpenMPIRBuilder {
/// \param IfCond Value which corresponds to the if clause
[llvm-branch-commits] [clang] [llvm] [mlir] [MLIR][OpenMP] Add LLVM translation support for OpenMP UserDefinedMappers (PR #124746)
@@ -3529,6 +3549,84 @@ static void genMapInfos(llvm::IRBuilderBase &builder,
}
}
+static llvm::Expected
+emitUserDefinedMapper(Operation *declMapperOp, llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation);
+
+static llvm::Expected
+getOrCreateUserDefinedMapperFunc(Operation *declMapperOp,
+ llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation) {
+ static llvm::DenseMap userDefMapperMap;
TIFitis wrote:
Oops, fixed now.
https://github.com/llvm/llvm-project/pull/124746
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[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
dcci wrote: OK with merging this. https://github.com/llvm/llvm-project/pull/126881 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] release/20.x: [libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877) (PR #126960)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/126960 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [clang-format] Hanlde qualified type name for `QualifierAlignment` (#125327) (PR #126839)
https://github.com/mydeveloperday approved this pull request. https://github.com/llvm/llvm-project/pull/126839 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [BOLT] Use getMainExecutable() (#126698) (PR #126881)
https://github.com/dcci approved this pull request. https://github.com/llvm/llvm-project/pull/126881 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [HLSL][RootSignature] Add Metadata generation of Root Signatures for Attr (PR #125131)
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/125131
>From abe7e6703a008608e19ce3f9bdcbd1b613fab60d Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 29 Jan 2025 19:40:08 +
Subject: [PATCH 1/6] add basic empty root signature
---
clang/lib/CodeGen/CGHLSLRuntime.cpp | 21 +
clang/test/CodeGenHLSL/RootSignature.hlsl | 19 +++
2 files changed, 40 insertions(+)
create mode 100644 clang/test/CodeGenHLSL/RootSignature.hlsl
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp
b/clang/lib/CodeGen/CGHLSLRuntime.cpp
index c354e58e15f4b..ff608323e9ac3 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.cpp
+++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp
@@ -119,6 +119,20 @@ GlobalVariable *replaceBuffer(CGHLSLRuntime::Buffer &Buf) {
return CBGV;
}
+void addRootSignature(llvm::Function *Fn, llvm::Module &M) {
+ auto &Ctx = M.getContext();
+ IRBuilder<> B(M.getContext());
+
+ MDNode *ExampleRootSignature = MDNode::get(Ctx, {});
+
+ MDNode *ExamplePairing = MDNode::get(Ctx, {ValueAsMetadata::get(Fn),
+ ExampleRootSignature});
+
+ StringRef RootSignatureValKey = "dx.rootsignatures";
+ auto *RootSignatureValMD = M.getOrInsertNamedMetadata(RootSignatureValKey);
+ RootSignatureValMD->addOperand(ExamplePairing);
+}
+
} // namespace
llvm::Type *CGHLSLRuntime::convertHLSLSpecificType(const Type *T) {
@@ -453,6 +467,13 @@ void CGHLSLRuntime::emitEntryFunction(const FunctionDecl
*FD,
// FIXME: Handle codegen for return type semantics.
// See: https://github.com/llvm/llvm-project/issues/57875
B.CreateRetVoid();
+
+ // Add and identify root signature to function, if applicable
+ const AttrVec &Attrs = FD->getAttrs();
+ for (const Attr *Attr : Attrs) {
+if (isa(Attr))
+ addRootSignature(EntryFn, M);
+ }
}
void CGHLSLRuntime::setHLSLFunctionAttributes(const FunctionDecl *FD,
diff --git a/clang/test/CodeGenHLSL/RootSignature.hlsl
b/clang/test/CodeGenHLSL/RootSignature.hlsl
new file mode 100644
index 0..1ea9ab7aaa2c3
--- /dev/null
+++ b/clang/test/CodeGenHLSL/RootSignature.hlsl
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
+
+// CHECK: !dx.rootsignatures = !{![[#FIRST_ENTRY:]], ![[#SECOND_ENTRY:]]}
+// CHECK-DAG: ![[#FIRST_ENTRY]] = !{ptr @FirstEntry, ![[#RS:]]}
+// CHECK-DAG: ![[#SECOND_ENTRY]] = !{ptr @SecondEntry, ![[#RS:]]}
+// CHECK-DAG: ![[#RS]] = !{}
+
+[shader("compute"), RootSignature("")]
+[numthreads(1,1,1)]
+void FirstEntry() {}
+
+[shader("compute"), RootSignature("DescriptorTable()")]
+[numthreads(1,1,1)]
+void SecondEntry() {}
+
+// Sanity test to ensure to root is added for this function
+[shader("compute")]
+[numthreads(1,1,1)]
+void ThirdEntry() {}
>From 671f099d3d58995677c47b4226481b72295e525d Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 29 Jan 2025 19:57:48 +
Subject: [PATCH 2/6] pass down the actual root elements
- test that we have the correct number of elements
---
clang/lib/CodeGen/CGHLSLRuntime.cpp | 17 -
clang/test/CodeGenHLSL/RootSignature.hlsl | 9 +
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp
b/clang/lib/CodeGen/CGHLSLRuntime.cpp
index ff608323e9ac3..4c9adcd8a9053 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.cpp
+++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp
@@ -119,11 +119,18 @@ GlobalVariable *replaceBuffer(CGHLSLRuntime::Buffer &Buf)
{
return CBGV;
}
-void addRootSignature(llvm::Function *Fn, llvm::Module &M) {
+void addRootSignature(
+ArrayRef Elements,
+llvm::Function *Fn, llvm::Module &M) {
auto &Ctx = M.getContext();
- IRBuilder<> B(M.getContext());
- MDNode *ExampleRootSignature = MDNode::get(Ctx, {});
+ SmallVector GeneratedMetadata;
+ for (auto Element : Elements) {
+MDNode *ExampleRootElement = MDNode::get(Ctx, {});
+GeneratedMetadata.push_back(ExampleRootElement);
+ }
+
+ MDNode *ExampleRootSignature = MDNode::get(Ctx, GeneratedMetadata);
MDNode *ExamplePairing = MDNode::get(Ctx, {ValueAsMetadata::get(Fn),
ExampleRootSignature});
@@ -471,8 +478,8 @@ void CGHLSLRuntime::emitEntryFunction(const FunctionDecl
*FD,
// Add and identify root signature to function, if applicable
const AttrVec &Attrs = FD->getAttrs();
for (const Attr *Attr : Attrs) {
-if (isa(Attr))
- addRootSignature(EntryFn, M);
+if (const auto *RSAttr = dyn_cast(Attr))
+ addRootSignature(RSAttr->getElements(), EntryFn, M);
}
}
diff --git a/clang/test/CodeGenHLSL/RootSignature.hlsl
b/clang/test/CodeGenHLSL/RootSignature.hlsl
index 1ea9ab7aaa2c3..63c0505e224f0 100644
--- a/clang/test/CodeGenHLSL/RootSignature.hlsl
+++ b/clang/test/CodeGenHLSL/RootSignature.hlsl
@@ -1,9 +1,10 @@
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
-// CHECK:
[llvm-branch-commits] [clang] [llvm] [HLSL][RootSignature] Add Metadata generation of Root Signatures for Attr (PR #125131)
llvmbot wrote:
@llvm/pr-subscribers-hlsl
@llvm/pr-subscribers-clang
Author: Finn Plummer (inbelic)
Changes
- Define and implement `MetadataBuilder` in `HLSLRootSignature`
- Integrate and invoke the builder in `CGHLSLRuntime.cpp` to generate the Root
Signature for any associated entry functions
- Add tests to demonstrate functionality in `RootSignature.hlsl`
Resolves https://github.com/llvm/llvm-project/issues/126584
---
Full diff: https://github.com/llvm/llvm-project/pull/125131.diff
5 Files Affected:
- (modified) clang/lib/CodeGen/CGHLSLRuntime.cpp (+20)
- (added) clang/test/CodeGenHLSL/RootSignature.hlsl (+29)
- (modified) llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h (+27)
- (modified) llvm/lib/Frontend/HLSL/CMakeLists.txt (+1)
- (added) llvm/lib/Frontend/HLSL/HLSLRootSignature.cpp (+108)
``diff
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp
b/clang/lib/CodeGen/CGHLSLRuntime.cpp
index c354e58e15f4b..62d062be91046 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.cpp
+++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp
@@ -119,6 +119,20 @@ GlobalVariable *replaceBuffer(CGHLSLRuntime::Buffer &Buf) {
return CBGV;
}
+void addRootSignature(ArrayRef Elements,
+ llvm::Function *Fn, llvm::Module &M) {
+ auto &Ctx = M.getContext();
+
+ llvm::hlsl::rootsig::MetadataBuilder Builder(Ctx, Elements);
+ MDNode *RootSignature = Builder.BuildRootSignature();
+ MDNode *FnPairing =
+ MDNode::get(Ctx, {ValueAsMetadata::get(Fn), RootSignature});
+
+ StringRef RootSignatureValKey = "dx.rootsignatures";
+ auto *RootSignatureValMD = M.getOrInsertNamedMetadata(RootSignatureValKey);
+ RootSignatureValMD->addOperand(FnPairing);
+}
+
} // namespace
llvm::Type *CGHLSLRuntime::convertHLSLSpecificType(const Type *T) {
@@ -453,6 +467,12 @@ void CGHLSLRuntime::emitEntryFunction(const FunctionDecl
*FD,
// FIXME: Handle codegen for return type semantics.
// See: https://github.com/llvm/llvm-project/issues/57875
B.CreateRetVoid();
+
+ // Add and identify root signature to function, if applicable
+ const AttrVec &Attrs = FD->getAttrs();
+ for (const Attr *Attr : Attrs)
+if (const auto *RSAttr = dyn_cast(Attr))
+ addRootSignature(RSAttr->getElements(), EntryFn, M);
}
void CGHLSLRuntime::setHLSLFunctionAttributes(const FunctionDecl *FD,
diff --git a/clang/test/CodeGenHLSL/RootSignature.hlsl
b/clang/test/CodeGenHLSL/RootSignature.hlsl
new file mode 100644
index 0..76aa2690b96a7
--- /dev/null
+++ b/clang/test/CodeGenHLSL/RootSignature.hlsl
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
+
+// CHECK-DAG: ![[#EMPTY:]] = !{}
+[shader("compute"), RootSignature("")]
+[numthreads(1,1,1)]
+void FirstEntry() {}
+
+// CHECK-DAG: ![[#CBV:]] = !{!"CBV", i32 1, i32 0, i32 0, i32 -1, i32 4}
+// CHECK-DAG: ![[#SRV:]] = !{!"SRV", i32 4, i32 42, i32 3, i32 32, i32 0}
+// CHECK-DAG: ![[#TABLE:]] = !{!"DescriptorTable", i32 0, ![[#CBV]], ![[#SRV]]}
+// CHECK-DAG: ![[#SECOND_RS:]] = !{![[#TABLE]]}
+
+#define SampleDescriptorTable \
+ "DescriptorTable( " \
+ " CBV(b0), " \
+ " SRV(t42, space = 3, offset = 32, numDescriptors = 4, flags = 0) " \
+ ")"
+[shader("compute"), RootSignature(SampleDescriptorTable)]
+[numthreads(1,1,1)]
+void SecondEntry() {}
+
+// Sanity test to ensure no root is added for this function
+[shader("compute")]
+[numthreads(1,1,1)]
+void ThirdEntry() {}
+
+// CHECK-DAG: ![[#FIRST_ENTRY:]] = !{ptr @FirstEntry, ![[#EMPTY]]}
+// CHECK-DAG: ![[#SECOND_ENTRY:]] = !{ptr @SecondEntry, ![[#SECOND_RS]]}
+// CHECK-DAG: !dx.rootsignatures = !{![[#FIRST_ENTRY]], ![[#SECOND_ENTRY]]}
diff --git a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
index f999a0b5eef33..d1c39b720d213 100644
--- a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
+++ b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
@@ -14,10 +14,16 @@
#ifndef LLVM_FRONTEND_HLSL_HLSLROOTSIGNATURE_H
#define LLVM_FRONTEND_HLSL_HLSLROOTSIGNATURE_H
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLForwardCompat.h"
#include "llvm/Support/DXILABI.h"
#include
namespace llvm {
+class LLVMContext;
+class MDNode;
+class Metadata;
+
namespace hlsl {
namespace rootsig {
@@ -122,6 +128,27 @@ using RootElement = std::variant;
using ParamType = std::variant;
+class MetadataBuilder {
+public:
+ MetadataBuilder(llvm::LLVMContext &Ctx, ArrayRef Elements)
+ : Ctx(Ctx), Elements(Elements) {}
+
+ /// Iterates through the elements and dispatches onto the correct Build
method
+ ///
+ /// Accumulates the root signature and returns the Metadata node that is just
+ /// a list of all the elements
+ MDNode *BuildRootSignature();
+
+private:
+ /// Define the various builders for the different metadata types
+ MDNode *BuildDescriptorTable(const DescriptorTable &Table);
+ MDNode *BuildDescriptorTableClause(const DescriptorTableClause &Clause);
+
+ llvm::
[llvm-branch-commits] [clang] [llvm] [HLSL][RootSignature] Add Metadata generation of Root Signatures for Attr (PR #125131)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Finn Plummer (inbelic)
Changes
- Define and implement `MetadataBuilder` in `HLSLRootSignature`
- Integrate and invoke the builder in `CGHLSLRuntime.cpp` to generate the Root
Signature for any associated entry functions
- Add tests to demonstrate functionality in `RootSignature.hlsl`
Resolves https://github.com/llvm/llvm-project/issues/126584
---
Full diff: https://github.com/llvm/llvm-project/pull/125131.diff
5 Files Affected:
- (modified) clang/lib/CodeGen/CGHLSLRuntime.cpp (+20)
- (added) clang/test/CodeGenHLSL/RootSignature.hlsl (+29)
- (modified) llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h (+27)
- (modified) llvm/lib/Frontend/HLSL/CMakeLists.txt (+1)
- (added) llvm/lib/Frontend/HLSL/HLSLRootSignature.cpp (+108)
``diff
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp
b/clang/lib/CodeGen/CGHLSLRuntime.cpp
index c354e58e15f4b..62d062be91046 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.cpp
+++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp
@@ -119,6 +119,20 @@ GlobalVariable *replaceBuffer(CGHLSLRuntime::Buffer &Buf) {
return CBGV;
}
+void addRootSignature(ArrayRef Elements,
+ llvm::Function *Fn, llvm::Module &M) {
+ auto &Ctx = M.getContext();
+
+ llvm::hlsl::rootsig::MetadataBuilder Builder(Ctx, Elements);
+ MDNode *RootSignature = Builder.BuildRootSignature();
+ MDNode *FnPairing =
+ MDNode::get(Ctx, {ValueAsMetadata::get(Fn), RootSignature});
+
+ StringRef RootSignatureValKey = "dx.rootsignatures";
+ auto *RootSignatureValMD = M.getOrInsertNamedMetadata(RootSignatureValKey);
+ RootSignatureValMD->addOperand(FnPairing);
+}
+
} // namespace
llvm::Type *CGHLSLRuntime::convertHLSLSpecificType(const Type *T) {
@@ -453,6 +467,12 @@ void CGHLSLRuntime::emitEntryFunction(const FunctionDecl
*FD,
// FIXME: Handle codegen for return type semantics.
// See: https://github.com/llvm/llvm-project/issues/57875
B.CreateRetVoid();
+
+ // Add and identify root signature to function, if applicable
+ const AttrVec &Attrs = FD->getAttrs();
+ for (const Attr *Attr : Attrs)
+if (const auto *RSAttr = dyn_cast(Attr))
+ addRootSignature(RSAttr->getElements(), EntryFn, M);
}
void CGHLSLRuntime::setHLSLFunctionAttributes(const FunctionDecl *FD,
diff --git a/clang/test/CodeGenHLSL/RootSignature.hlsl
b/clang/test/CodeGenHLSL/RootSignature.hlsl
new file mode 100644
index 0..76aa2690b96a7
--- /dev/null
+++ b/clang/test/CodeGenHLSL/RootSignature.hlsl
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -o - %s |
FileCheck %s
+
+// CHECK-DAG: ![[#EMPTY:]] = !{}
+[shader("compute"), RootSignature("")]
+[numthreads(1,1,1)]
+void FirstEntry() {}
+
+// CHECK-DAG: ![[#CBV:]] = !{!"CBV", i32 1, i32 0, i32 0, i32 -1, i32 4}
+// CHECK-DAG: ![[#SRV:]] = !{!"SRV", i32 4, i32 42, i32 3, i32 32, i32 0}
+// CHECK-DAG: ![[#TABLE:]] = !{!"DescriptorTable", i32 0, ![[#CBV]], ![[#SRV]]}
+// CHECK-DAG: ![[#SECOND_RS:]] = !{![[#TABLE]]}
+
+#define SampleDescriptorTable \
+ "DescriptorTable( " \
+ " CBV(b0), " \
+ " SRV(t42, space = 3, offset = 32, numDescriptors = 4, flags = 0) " \
+ ")"
+[shader("compute"), RootSignature(SampleDescriptorTable)]
+[numthreads(1,1,1)]
+void SecondEntry() {}
+
+// Sanity test to ensure no root is added for this function
+[shader("compute")]
+[numthreads(1,1,1)]
+void ThirdEntry() {}
+
+// CHECK-DAG: ![[#FIRST_ENTRY:]] = !{ptr @FirstEntry, ![[#EMPTY]]}
+// CHECK-DAG: ![[#SECOND_ENTRY:]] = !{ptr @SecondEntry, ![[#SECOND_RS]]}
+// CHECK-DAG: !dx.rootsignatures = !{![[#FIRST_ENTRY]], ![[#SECOND_ENTRY]]}
diff --git a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
index f999a0b5eef33..d1c39b720d213 100644
--- a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
+++ b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
@@ -14,10 +14,16 @@
#ifndef LLVM_FRONTEND_HLSL_HLSLROOTSIGNATURE_H
#define LLVM_FRONTEND_HLSL_HLSLROOTSIGNATURE_H
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLForwardCompat.h"
#include "llvm/Support/DXILABI.h"
#include
namespace llvm {
+class LLVMContext;
+class MDNode;
+class Metadata;
+
namespace hlsl {
namespace rootsig {
@@ -122,6 +128,27 @@ using RootElement = std::variant;
using ParamType = std::variant;
+class MetadataBuilder {
+public:
+ MetadataBuilder(llvm::LLVMContext &Ctx, ArrayRef Elements)
+ : Ctx(Ctx), Elements(Elements) {}
+
+ /// Iterates through the elements and dispatches onto the correct Build
method
+ ///
+ /// Accumulates the root signature and returns the Metadata node that is just
+ /// a list of all the elements
+ MDNode *BuildRootSignature();
+
+private:
+ /// Define the various builders for the different metadata types
+ MDNode *BuildDescriptorTable(const DescriptorTable &Table);
+ MDNode *BuildDescriptorTableClause(const DescriptorTableClause &Clause);
+
+ llvm::LLVMContext &Ctx;
[llvm-branch-commits] [clang] [llvm] [HLSL][RootSignature] Add Metadata generation of Root Signatures for Attr (PR #125131)
https://github.com/inbelic ready_for_review https://github.com/llvm/llvm-project/pull/125131 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [HLSL] Define the HLSLRootSignature Attr (PR #123985)
https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/123985 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [MLIR][OpenMP] Add LLVM translation support for OpenMP UserDefinedMappers (PR #124746)
@@ -3529,6 +3549,84 @@ static void genMapInfos(llvm::IRBuilderBase &builder,
}
}
+static llvm::Expected
+emitUserDefinedMapper(Operation *declMapperOp, llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation);
+
+static llvm::Expected
+getOrCreateUserDefinedMapperFunc(Operation *declMapperOp,
+ llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation) {
+ static llvm::DenseMap userDefMapperMap;
+ auto iter = userDefMapperMap.find(declMapperOp);
+ if (iter != userDefMapperMap.end())
+return iter->second;
+ llvm::Expected mapperFunc =
+ emitUserDefinedMapper(declMapperOp, builder, moduleTranslation);
+ if (!mapperFunc)
+return mapperFunc.takeError();
+ userDefMapperMap.try_emplace(declMapperOp, *mapperFunc);
+ return mapperFunc;
+}
+
+static llvm::Expected
+emitUserDefinedMapper(Operation *op, llvm::IRBuilderBase &builder,
+ LLVM::ModuleTranslation &moduleTranslation) {
+ auto declMapperOp = cast(op);
+ auto declMapperInfoOp =
+ *declMapperOp.getOps().begin();
+ DataLayout dl = DataLayout(declMapperOp->getParentOfType());
+ llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder();
+ llvm::Type *varType = moduleTranslation.convertType(declMapperOp.getType());
+ std::string mapperName = ompBuilder->createPlatformSpecificName(
+ {"omp_mapper", declMapperOp.getSymName()});
+ SmallVector mapVars = declMapperInfoOp.getMapVars();
+
+ using InsertPointTy = llvm::OpenMPIRBuilder::InsertPointTy;
+
+ // Fill up the arrays with all the mapped variables.
+ MapInfosTy combinedInfo;
+ auto genMapInfoCB =
+ [&](InsertPointTy codeGenIP, llvm::Value *ptrPHI,
+ llvm::Value *unused2) -> llvm::OpenMPIRBuilder::MapInfosOrErrorTy {
+builder.restoreIP(codeGenIP);
+moduleTranslation.mapValue(declMapperOp.getRegion().getArgument(0),
ptrPHI);
+moduleTranslation.mapBlock(&declMapperOp.getRegion().front(),
+ builder.GetInsertBlock());
+if (failed(moduleTranslation.convertBlock(declMapperOp.getRegion().front(),
+ /*ignoreArguments=*/true,
+ builder)))
+ return llvm::make_error();
+MapInfoData mapData;
+collectMapDataFromMapOperands(mapData, mapVars, moduleTranslation, dl,
+ builder);
+genMapInfos(builder, moduleTranslation, dl, combinedInfo, mapData);
+
+// Drop the mapping that is no longer necessary so that the same region can
+// be processed multiple times.
+moduleTranslation.forgetMapping(declMapperOp.getRegion());
+return combinedInfo;
+ };
+
+ auto customMapperCB = [&](unsigned i, llvm::Function **mapperFunc) {
+if (combinedInfo.Mappers[i]) {
+ // Call the corresponding mapper function.
+ llvm::Expected newFn =
getOrCreateUserDefinedMapperFunc(
+ combinedInfo.Mappers[i], builder, moduleTranslation);
+ assert(newFn && "Expect a valid mapper function is available");
TIFitis wrote:
I've added error propagation.
https://github.com/llvm/llvm-project/pull/124746
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[llvm-branch-commits] [libc] release/20.x: [libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877) (PR #126960)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/126960 Backport b0d782080529cf5d422847e1f91f29bd7c62f691 Requested by: @petrhosek >From 87587f925442d6369a7d511426a55ad50f3141ea Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Wed, 12 Feb 2025 11:37:07 -0800 Subject: [PATCH] [libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877) Relying on features.h is problematic since codebases are free to have such a header on their search path, which breaks compilation. libc should instead provide a more standard way of getting __LLVM_LIBC__. Since __llvm-libc-common.h is included from all libc headers, defining __LLVM_LIBC__ there ensures that this define is available whenever any of the standard header is included. (cherry picked from commit b0d782080529cf5d422847e1f91f29bd7c62f691) --- libc/include/__llvm-libc-common.h | 2 ++ libc/include/llvm-libc-macros/features-macros.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/include/__llvm-libc-common.h b/libc/include/__llvm-libc-common.h index b5a23c5765f4d..9112d1ebe302c 100644 --- a/libc/include/__llvm-libc-common.h +++ b/libc/include/__llvm-libc-common.h @@ -9,6 +9,8 @@ #ifndef LLVM_LIBC_COMMON_H #define LLVM_LIBC_COMMON_H +#define __LLVM_LIBC__ 1 + #ifdef __cplusplus #undef __BEGIN_C_DECLS diff --git a/libc/include/llvm-libc-macros/features-macros.h b/libc/include/llvm-libc-macros/features-macros.h index 5bc87a68fc0ba..f87ae4ad12408 100644 --- a/libc/include/llvm-libc-macros/features-macros.h +++ b/libc/include/llvm-libc-macros/features-macros.h @@ -9,6 +9,4 @@ #ifndef LLVM_LIBC_MACROS_FEATURES_MACROS_H #define LLVM_LIBC_MACROS_FEATURES_MACROS_H -#define __LLVM_LIBC__ 1 - #endif // LLVM_LIBC_MACROS_FEATURES_MACROS_H ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] release/20.x: [libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877) (PR #126960)
llvmbot wrote: @michaelrj-google What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/126960 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] release/20.x: [libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877) (PR #126960)
llvmbot wrote: @llvm/pr-subscribers-libc Author: None (llvmbot) Changes Backport b0d782080529cf5d422847e1f91f29bd7c62f691 Requested by: @petrhosek --- Full diff: https://github.com/llvm/llvm-project/pull/126960.diff 2 Files Affected: - (modified) libc/include/__llvm-libc-common.h (+2) - (modified) libc/include/llvm-libc-macros/features-macros.h (-2) ``diff diff --git a/libc/include/__llvm-libc-common.h b/libc/include/__llvm-libc-common.h index b5a23c5765f4d..9112d1ebe302c 100644 --- a/libc/include/__llvm-libc-common.h +++ b/libc/include/__llvm-libc-common.h @@ -9,6 +9,8 @@ #ifndef LLVM_LIBC_COMMON_H #define LLVM_LIBC_COMMON_H +#define __LLVM_LIBC__ 1 + #ifdef __cplusplus #undef __BEGIN_C_DECLS diff --git a/libc/include/llvm-libc-macros/features-macros.h b/libc/include/llvm-libc-macros/features-macros.h index 5bc87a68fc0ba..f87ae4ad12408 100644 --- a/libc/include/llvm-libc-macros/features-macros.h +++ b/libc/include/llvm-libc-macros/features-macros.h @@ -9,6 +9,4 @@ #ifndef LLVM_LIBC_MACROS_FEATURES_MACROS_H #define LLVM_LIBC_MACROS_FEATURES_MACROS_H -#define __LLVM_LIBC__ 1 - #endif // LLVM_LIBC_MACROS_FEATURES_MACROS_H `` https://github.com/llvm/llvm-project/pull/126960 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
