[llvm-branch-commits] [lld][WebAssembly] Replace config-> with ctx.arg. (PR #119835)
@@ -48,7 +48,7 @@ ConfigWrapper config; Ctx ctx; sbc100 wrote: Can we remove the global `config` on line 47, or is that for a followup? https://github.com/llvm/llvm-project/pull/119835 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld][WebAssembly] Replace config-> with ctx.arg. (PR #119835)
https://github.com/sbc100 commented: lgtm % comment https://github.com/llvm/llvm-project/pull/119835 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [lld][LoongArch] Implement TLSDESC GD/LD to IE/LE. (PR #121120)
https://github.com/ylzsx closed https://github.com/llvm/llvm-project/pull/121120 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (PR #121330)
https://github.com/zhaoqi5 created
https://github.com/llvm/llvm-project/pull/121330
If linker relaxation enabled, relaxable code sequence expanded from pseudos
should avoid being separated by instruction scheduling. This commit tags
scheduling boundary for them to avoid being scheduled. (Except for `tls_le` and
`call36/tail36`. Because `tls_le` can be scheduled and have no influence to
relax, `call36/tail36` are expanded later in `LoongArchExpandPseudo` pass.)
A new mask target-flag is added to attach relax relocs to the relaxable code
sequence. (No need to add it for `tls_le` and `call36/tail36` because of the
reasons shown above.) Because of this, get "direct" flags is necessary when
using their target-flags. In addition, code sequence after being optimized by
`MergeBaseOffset` pass may not relaxable any more, so the relax "bitmask" flag
should be removed.
>From 85be5541a23a859ad8e50bd75fb7ff35985c5988 Mon Sep 17 00:00:00 2001
From: Qi Zhao
Date: Tue, 24 Dec 2024 11:03:23 +0800
Subject: [PATCH] [LoongArch] Avoid scheduling relaxable code sequence and
attach relax relocs
If linker relaxation enabled, relaxable code sequence expanded
from pseudos should avoid being separated by instruction scheduling.
This commit tags scheduling boundary for them to avoid being
scheduled. (Except for `tls_le` and `call36/tail36`. Because
`tls_le` can be scheduled and have no influence to relax,
`call36/tail36` are expanded later in `LoongArchExpandPseudo` pass.)
A new mask target-flag is added to attach relax relocs to the
relaxable code sequence. (No need to add it for `tls_le` and
`call36/tail36` because of the reasons shown above.) Because of this,
get "direct" flags is necessary when using their target-flags.
In addition, code sequence after being optimized by `MergeBaseOffset`
pass may not relaxable any more, so the relax "bitmask" flag should
be removed.
---
.../LoongArch/LoongArchExpandPseudoInsts.cpp | 34 --
.../Target/LoongArch/LoongArchInstrInfo.cpp | 99 -
.../lib/Target/LoongArch/LoongArchInstrInfo.h | 3 +
.../Target/LoongArch/LoongArchMCInstLower.cpp | 4 +-
.../LoongArch/LoongArchMergeBaseOffset.cpp| 30 +-
.../LoongArch/LoongArchTargetMachine.cpp | 1 +
.../MCTargetDesc/LoongArchBaseInfo.h | 22
.../MCTargetDesc/LoongArchMCCodeEmitter.cpp | 1 +
.../CodeGen/LoongArch/linker-relaxation.ll| 102 ++
.../test/CodeGen/LoongArch/mir-relax-flags.ll | 64 +++
.../CodeGen/LoongArch/mir-target-flags.ll | 31 +-
11 files changed, 370 insertions(+), 21 deletions(-)
create mode 100644 llvm/test/CodeGen/LoongArch/linker-relaxation.ll
create mode 100644 llvm/test/CodeGen/LoongArch/mir-relax-flags.ll
diff --git a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
index 0218934ea3344a..be60de3d63d061 100644
--- a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
@@ -187,18 +187,23 @@ bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
+ const auto &STI = MF->getSubtarget();
+ bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
+
Register DestReg = MI.getOperand(0).getReg();
Register ScratchReg =
MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
MachineOperand &Symbol = MI.getOperand(1);
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
- .addDisp(Symbol, 0, FlagsHi);
+ .addDisp(Symbol, 0,
+ EnableRelax ? LoongArchII::addRelaxFlag(FlagsHi) : FlagsHi);
MachineInstr *SecondMI =
BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
.addReg(ScratchReg)
- .addDisp(Symbol, 0, FlagsLo);
+ .addDisp(Symbol, 0,
+ EnableRelax ? LoongArchII::addRelaxFlag(FlagsLo) : FlagsLo);
if (MI.hasOneMemOperand())
SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
@@ -481,6 +486,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
unsigned ADD = STI.is64Bit() ? LoongArch::ADD_D : LoongArch::ADD_W;
unsigned ADDI = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
unsigned LD = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
+ bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
Register DestReg = MI.getOperand(0).getReg();
Register Tmp1Reg =
@@ -488,7 +494,10 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
MachineOperand &Symbol = MI.getOperand(Large ? 2 : 1);
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), Tmp1Reg)
- .addDisp(Symbol, 0, LoongArchII::MO_DESC_PC_HI);
+ .addDisp(Symbol, 0,
+ (EnableRelax && !Large)
+ ? LoongArchII::addRelaxFlag(LoongArchII::MO_DESC_PC_HI)
+ : LoongArchII::MO_DESC_PC_HI);
if (Large) {
// Code S
[llvm-branch-commits] [llvm] [LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (PR #121330)
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: ZhaoQi (zhaoqi5)
Changes
If linker relaxation enabled, relaxable code sequence expanded from pseudos
should avoid being separated by instruction scheduling. This commit tags
scheduling boundary for them to avoid being scheduled. (Except for `tls_le` and
`call36/tail36`. Because `tls_le` can be scheduled and have no influence to
relax, `call36/tail36` are expanded later in `LoongArchExpandPseudo` pass.)
A new mask target-flag is added to attach relax relocs to the relaxable code
sequence. (No need to add it for `tls_le` and `call36/tail36` because of the
reasons shown above.) Because of this, get "direct" flags is necessary when
using their target-flags. In addition, code sequence after being optimized by
`MergeBaseOffset` pass may not relaxable any more, so the relax "bitmask" flag
should be removed.
---
Patch is 28.44 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/121330.diff
11 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp (+26-8)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp (+96-3)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.h (+3)
- (modified) llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp (+2-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp (+25-5)
- (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+1)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h (+22)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
(+1)
- (added) llvm/test/CodeGen/LoongArch/linker-relaxation.ll (+102)
- (added) llvm/test/CodeGen/LoongArch/mir-relax-flags.ll (+64)
- (modified) llvm/test/CodeGen/LoongArch/mir-target-flags.ll (+28-3)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
index 0218934ea3344a..be60de3d63d061 100644
--- a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
@@ -187,18 +187,23 @@ bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
+ const auto &STI = MF->getSubtarget();
+ bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
+
Register DestReg = MI.getOperand(0).getReg();
Register ScratchReg =
MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
MachineOperand &Symbol = MI.getOperand(1);
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
- .addDisp(Symbol, 0, FlagsHi);
+ .addDisp(Symbol, 0,
+ EnableRelax ? LoongArchII::addRelaxFlag(FlagsHi) : FlagsHi);
MachineInstr *SecondMI =
BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
.addReg(ScratchReg)
- .addDisp(Symbol, 0, FlagsLo);
+ .addDisp(Symbol, 0,
+ EnableRelax ? LoongArchII::addRelaxFlag(FlagsLo) : FlagsLo);
if (MI.hasOneMemOperand())
SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
@@ -481,6 +486,7 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
unsigned ADD = STI.is64Bit() ? LoongArch::ADD_D : LoongArch::ADD_W;
unsigned ADDI = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
unsigned LD = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
+ bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
Register DestReg = MI.getOperand(0).getReg();
Register Tmp1Reg =
@@ -488,7 +494,10 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
MachineOperand &Symbol = MI.getOperand(Large ? 2 : 1);
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), Tmp1Reg)
- .addDisp(Symbol, 0, LoongArchII::MO_DESC_PC_HI);
+ .addDisp(Symbol, 0,
+ (EnableRelax && !Large)
+ ? LoongArchII::addRelaxFlag(LoongArchII::MO_DESC_PC_HI)
+ : LoongArchII::MO_DESC_PC_HI);
if (Large) {
// Code Sequence:
@@ -526,19 +535,28 @@ bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
// pcalau12i $a0, %desc_pc_hi20(sym)
// addi.w/d $a0, $a0, %desc_pc_lo12(sym)
// ld.w/d$ra, $a0, %desc_ld(sym)
-// jirl $ra, $ra, %desc_ld(sym)
-// add.d $dst, $a0, $tp
+// jirl $ra, $ra, %desc_call(sym)
+// add.w/d $dst, $a0, $tp
BuildMI(MBB, MBBI, DL, TII->get(ADDI), LoongArch::R4)
.addReg(Tmp1Reg)
-.addDisp(Symbol, 0, LoongArchII::MO_DESC_PC_LO);
+.addDisp(Symbol, 0,
+ EnableRelax
+ ? LoongArchII::addRelaxFlag(LoongArchII::MO_DESC_PC_LO)
+ : LoongArchII::MO_DESC_PC_LO);
}
BuildMI(MBB, MBBI, DL, TII->get(LD), LoongArch::R1)
.addReg(LoongArch::R4)
- .addDisp(Symbol, 0, LoongArchII::MO_DESC_LD);
+ .addDisp(Symbol, 0,
+ (E
[llvm-branch-commits] [lld] [lld][LoongArch] Implement TLSDESC GD/LD to IE/LE. (PR #121120)
https://github.com/ylzsx converted_to_draft https://github.com/llvm/llvm-project/pull/121120 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [DirectX] Implement the resource.store.rawbuffer intrinsic (PR #121282)
bogner wrote: > ⚠️ undef deprecator found issues in your code. ⚠️ > > You can test this locally with the following command: > The following files introduce new uses of undef: > > * llvm/lib/Target/DirectX/DXILOpLowering.cpp > * llvm/test/CodeGen/DirectX/BufferStore-sm61.ll > * llvm/test/CodeGen/DirectX/RawBufferStore.ll False positive - we’re generating DXIL-compatible IR here so the undefs are required https://github.com/llvm/llvm-project/pull/121282 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (PR #121330)
https://github.com/zhaoqi5 edited https://github.com/llvm/llvm-project/pull/121330 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
