[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
https://github.com/ergawy approved this pull request. Thanks Andrew. Compared the new PR against my comments in the old one and seems ok to me. However, the PR is hge and I cannot claim I got every little detail of what is going on, therefore, it would be better to wait for other approvals. https://github.com/llvm/llvm-project/pull/113557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
+// RHS to LHS ("member" to "parent") and then we reverse it so that the
+// returned omp::ObjectList is LHS to RHS, with the "parent" at the
+// beginning.
+omp::ObjectList gatherObjectsOf(omp::Object derivedTypeMember,
+semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = derivedTypeMember;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+// This function generates a series of indices from a provided omp::Object,
+// that devolves to an ArrayRef symbol, e.g. "array(2,3,4)", this function
+// would generate a series of indices of "[1][2][3]" for the above example,
+// offsetting by -1 to account for the non-zero fortran indexes.
+//
+// These indices can then be provided to a coordinate operation or other
+// GEP-like operation to access the relevant positional member of the
+// array.
+//
+// It is of note that the function only supports subscript integers currently
+// and not Triplets i.e. Array(1:2:3).
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ auto maybeRef = evaluate::ExtractDataRef(*object.ref());
+ if (!maybeRef)
+return;
+
+ auto *arr = std::get_if(&maybeRef->u);
+ if (!arr)
+return;
+
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript =
+ fir::getBase(converter.genExprValue(toEvExpr(expr.value()),
stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+
+/// When mapping members of derived types, there is a chance that one of the
+/// members along the way to a mapped member is an descriptor. In which case
+/// we have to make sure we generate a map for those along the way otherwise
+/// we will be missing a chunk of data required to actually map the member
+/// type to device. This function effectively generates these maps and the
+/// appropriate data accesses required to generate these maps. It will avoid
+/// creating duplicate maps, as duplicates are just as bad as unmapped
+/// descriptor data in a lot of cases for the runtime (and unnecessary
+/// data movement should be avoided where possible).
+///
+/// As an example for the following mapping:
+///
+/// type :: vertexes
+/// integer(4), allocatable :: vertexx(:)
+/// integer(4), allocatable :: vertexy(:)
+/// end type vertexes
+///
+/// type :: dtype
+/// real(4) :: i
+/// type(vertexes), allocatable :: vertexes(:)
+/// end type dtype
+///
+/// type(dtype), allocatable :: alloca_dtype
+///
+/// !$omp target map(tofrom: alloca_dtype%vertexes(N1)%vertexx)
+///
+/// The below HLFIR/FIR is generated (trimmed for conciseness):
+///
+/// On the first iteration we index into the record type alloca_dtype
+/// to access "vertexes", we then generate a map for this descriptor
+/// alongside bounds to indicate we only need the 1 member, rather than
+/// the whole array block in this case (In theory we could map its
+/// entirety at the cost of data transfer bandwidth).
+///
+/// %13:2 = hlfir.declare ... "alloca_dtype" ...
+/// %39 = fir.load %13#0 : ...
+/// %40 = fir.coordinate_of %39, %c1 : ...
+/// %51 = omp.map.info var_ptr(%40 : ...) map_clauses(to) capture(ByRef) ...
+/// %52 = fir.load %40 : ...
+///
+/// Second iteration generating access to "vertexes(N1) utilising the N1 index
+/// %53 = load N1 ...
+/// %54 = fir.convert %53 : (i32) -> i64
+/// %55 = fir.convert
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -119,10 +119,10 @@ void gatherFuncAndVarSyms( mlir::omp::MapInfoOp createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc, -mlir::Value baseAddr, mlir::Value varPtrPtr, std::string name, -llvm::ArrayRef bounds, -llvm::ArrayRef members, -mlir::DenseIntElementsAttr membersIndex, uint64_t mapType, +mlir::Value baseAddr, mlir::Value varPtrPtr, +llvm::StringRef name, mlir::ArrayRef bounds, skatrak wrote: Nit: A quick search shows that, in the MLIR project, `llvm::ArrayRef` is much more widely used than `mlir::ArrayRef`, but feel free to keep it like this if you think it's better like that. ```suggestion llvm::StringRef name, llvm::ArrayRef bounds, ``` https://github.com/llvm/llvm-project/pull/113557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -183,173 +466,119 @@ getComponentObject(std::optional object,
return getComponentObject(baseObj.value(), semaCtx);
}
-static void
-generateMemberPlacementIndices(const Object &object,
- llvm::SmallVectorImpl &indices,
- semantics::SemanticsContext &semaCtx) {
+void generateMemberPlacementIndices(const Object &object,
+llvm::SmallVectorImpl &indices,
+semantics::SemanticsContext &semaCtx) {
+ assert(indices.empty() && "indices vector passed to "
+"generateMemberPlacementIndices should be empty");
auto compObj = getComponentObject(object, semaCtx);
+
while (compObj) {
-indices.push_back(getComponentPlacementInParent(compObj->sym()));
+int64_t index = getComponentPlacementInParent(compObj->sym());
+assert(
+index >= 0 &&
+"unexpected index value returned from getComponentPlacementInParent");
+indices.push_back(index);
compObj =
getComponentObject(getBaseObject(compObj.value(), semaCtx), semaCtx);
}
- indices = llvm::SmallVector{llvm::reverse(indices)};
+ indices = llvm::SmallVector{llvm::reverse(indices)};
}
-void addChildIndexAndMapToParent(
-const omp::Object &object,
-std::map> &parentMemberIndices,
-mlir::omp::MapInfoOp &mapOp, semantics::SemanticsContext &semaCtx) {
- std::optional dataRef = ExtractDataRef(object.ref());
- assert(dataRef.has_value() &&
- "DataRef could not be extracted during mapping of derived type "
- "cannot proceed");
- const semantics::Symbol *parentSym = &dataRef->GetFirstSymbol();
- assert(parentSym && "Could not find parent symbol during lower of "
- "a component member in OpenMP map clause");
- llvm::SmallVector indices;
+void OmpMapParentAndMemberData::addChildIndexAndMapToParent(
+const omp::Object &object, mlir::omp::MapInfoOp &mapOp,
+semantics::SemanticsContext &semaCtx) {
+ llvm::SmallVector indices;
generateMemberPlacementIndices(object, indices, semaCtx);
- parentMemberIndices[parentSym].push_back({indices, mapOp});
+ memberPlacementIndices.push_back(indices);
+ memberMap.push_back(mapOp);
}
-static void calculateShapeAndFillIndices(
-llvm::SmallVectorImpl &shape,
-llvm::SmallVectorImpl &memberPlacementData) {
- shape.push_back(memberPlacementData.size());
- size_t largestIndicesSize =
- std::max_element(memberPlacementData.begin(), memberPlacementData.end(),
- [](auto a, auto b) {
- return a.memberPlacementIndices.size() <
-b.memberPlacementIndices.size();
- })
- ->memberPlacementIndices.size();
- shape.push_back(largestIndicesSize);
-
- // DenseElementsAttr expects a rectangular shape for the data, so all
- // index lists have to be of the same length, this emplaces -1 as filler.
- for (auto &v : memberPlacementData) {
-if (v.memberPlacementIndices.size() < largestIndicesSize) {
- auto *prevEnd = v.memberPlacementIndices.end();
- v.memberPlacementIndices.resize(largestIndicesSize);
- std::fill(prevEnd, v.memberPlacementIndices.end(), -1);
-}
+bool isMemberOrParentAllocatableOrPointer(
+const Object &object, semantics::SemanticsContext &semaCtx) {
+ if (semantics::IsAllocatableOrObjectPointer(object.sym()))
+return true;
+
+ auto compObj = getBaseObject(object, semaCtx);
+ while (compObj) {
+if (semantics::IsAllocatableOrObjectPointer(compObj.value().sym()))
+ return true;
+compObj = getBaseObject(compObj.value(), semaCtx);
}
-}
-static mlir::DenseIntElementsAttr createDenseElementsAttrFromIndices(
-llvm::SmallVectorImpl &memberPlacementData,
-fir::FirOpBuilder &builder) {
- llvm::SmallVector shape;
- calculateShapeAndFillIndices(shape, memberPlacementData);
-
- llvm::SmallVector indicesFlattened =
- std::accumulate(memberPlacementData.begin(), memberPlacementData.end(),
- llvm::SmallVector(),
- [](llvm::SmallVector &x, OmpMapMemberIndicesData y)
{
-x.insert(x.end(), y.memberPlacementIndices.begin(),
- y.memberPlacementIndices.end());
-return x;
- });
-
- return mlir::DenseIntElementsAttr::get(
- mlir::VectorType::get(shape,
-mlir::IntegerType::get(builder.getContext(), 32)),
- indicesFlattened);
+ return false;
}
void insertChildMapInfoIntoParent(
-lower::AbstractConverter &converter,
-std::map> &parentMemberIndices,
+lower::AbstractConverter &converter, semantics::SemanticsContext &semaCtx,
+lower::StatementContext &stmtCtx,
+std::map &parentMemberIndices,
llvm::SmallVectorImpl &mapOperands,
llvm::SmallVectorImpl &mapSyms) {
+ fir::FirOpBuilder
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
+// RHS to LHS ("member" to "parent") and then we reverse it so that the
+// returned omp::ObjectList is LHS to RHS, with the "parent" at the
+// beginning.
+omp::ObjectList gatherObjectsOf(omp::Object derivedTypeMember,
+semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = derivedTypeMember;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+// This function generates a series of indices from a provided omp::Object,
+// that devolves to an ArrayRef symbol, e.g. "array(2,3,4)", this function
+// would generate a series of indices of "[1][2][3]" for the above example,
+// offsetting by -1 to account for the non-zero fortran indexes.
+//
+// These indices can then be provided to a coordinate operation or other
+// GEP-like operation to access the relevant positional member of the
+// array.
+//
+// It is of note that the function only supports subscript integers currently
+// and not Triplets i.e. Array(1:2:3).
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ auto maybeRef = evaluate::ExtractDataRef(*object.ref());
+ if (!maybeRef)
+return;
+
+ auto *arr = std::get_if(&maybeRef->u);
+ if (!arr)
+return;
+
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript =
+ fir::getBase(converter.genExprValue(toEvExpr(expr.value()),
stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+
+/// When mapping members of derived types, there is a chance that one of the
+/// members along the way to a mapped member is an descriptor. In which case
+/// we have to make sure we generate a map for those along the way otherwise
+/// we will be missing a chunk of data required to actually map the member
+/// type to device. This function effectively generates these maps and the
+/// appropriate data accesses required to generate these maps. It will avoid
+/// creating duplicate maps, as duplicates are just as bad as unmapped
+/// descriptor data in a lot of cases for the runtime (and unnecessary
+/// data movement should be avoided where possible).
+///
+/// As an example for the following mapping:
+///
+/// type :: vertexes
+/// integer(4), allocatable :: vertexx(:)
+/// integer(4), allocatable :: vertexy(:)
+/// end type vertexes
+///
+/// type :: dtype
+/// real(4) :: i
+/// type(vertexes), allocatable :: vertexes(:)
+/// end type dtype
+///
+/// type(dtype), allocatable :: alloca_dtype
+///
+/// !$omp target map(tofrom: alloca_dtype%vertexes(N1)%vertexx)
+///
+/// The below HLFIR/FIR is generated (trimmed for conciseness):
+///
+/// On the first iteration we index into the record type alloca_dtype
+/// to access "vertexes", we then generate a map for this descriptor
+/// alongside bounds to indicate we only need the 1 member, rather than
+/// the whole array block in this case (In theory we could map its
+/// entirety at the cost of data transfer bandwidth).
+///
+/// %13:2 = hlfir.declare ... "alloca_dtype" ...
+/// %39 = fir.load %13#0 : ...
+/// %40 = fir.coordinate_of %39, %c1 : ...
+/// %51 = omp.map.info var_ptr(%40 : ...) map_clauses(to) capture(ByRef) ...
+/// %52 = fir.load %40 : ...
+///
+/// Second iteration generating access to "vertexes(N1) utilising the N1 index
+/// %53 = load N1 ...
+/// %54 = fir.convert %53 : (i32) -> i64
+/// %55 = fir.convert
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -21,11 +23,9 @@ #include #include #include +#include skatrak wrote: Nit: I think this should be placed below flang/llvm includes, where algorithm and numeric used to be. https://github.com/llvm/llvm-project/pull/113557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
https://github.com/skatrak commented: Thank you Andrew for all this work. I went through your PR and I have some comments, the vast majority of which are only nits. Generally, this looks ok to me, though it's a very large and complex patch, so I'm putting a good amount of trust in unit tests and in that you know what you're doing 😅. Not sure if anything can be done here to make it simpler for other people to follow, since you've already introduced a good amount of comments. https://github.com/llvm/llvm-project/pull/113557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
+// RHS to LHS ("member" to "parent") and then we reverse it so that the
+// returned omp::ObjectList is LHS to RHS, with the "parent" at the
+// beginning.
+omp::ObjectList gatherObjectsOf(omp::Object derivedTypeMember,
+semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = derivedTypeMember;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+// This function generates a series of indices from a provided omp::Object,
+// that devolves to an ArrayRef symbol, e.g. "array(2,3,4)", this function
+// would generate a series of indices of "[1][2][3]" for the above example,
+// offsetting by -1 to account for the non-zero fortran indexes.
+//
+// These indices can then be provided to a coordinate operation or other
+// GEP-like operation to access the relevant positional member of the
+// array.
+//
+// It is of note that the function only supports subscript integers currently
+// and not Triplets i.e. Array(1:2:3).
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ auto maybeRef = evaluate::ExtractDataRef(*object.ref());
+ if (!maybeRef)
+return;
+
+ auto *arr = std::get_if(&maybeRef->u);
+ if (!arr)
+return;
+
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript =
+ fir::getBase(converter.genExprValue(toEvExpr(expr.value()),
stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+
+/// When mapping members of derived types, there is a chance that one of the
+/// members along the way to a mapped member is an descriptor. In which case
+/// we have to make sure we generate a map for those along the way otherwise
+/// we will be missing a chunk of data required to actually map the member
+/// type to device. This function effectively generates these maps and the
+/// appropriate data accesses required to generate these maps. It will avoid
+/// creating duplicate maps, as duplicates are just as bad as unmapped
+/// descriptor data in a lot of cases for the runtime (and unnecessary
+/// data movement should be avoided where possible).
+///
+/// As an example for the following mapping:
+///
+/// type :: vertexes
+/// integer(4), allocatable :: vertexx(:)
+/// integer(4), allocatable :: vertexy(:)
+/// end type vertexes
+///
+/// type :: dtype
+/// real(4) :: i
+/// type(vertexes), allocatable :: vertexes(:)
+/// end type dtype
+///
+/// type(dtype), allocatable :: alloca_dtype
+///
+/// !$omp target map(tofrom: alloca_dtype%vertexes(N1)%vertexx)
+///
+/// The below HLFIR/FIR is generated (trimmed for conciseness):
+///
+/// On the first iteration we index into the record type alloca_dtype
+/// to access "vertexes", we then generate a map for this descriptor
+/// alongside bounds to indicate we only need the 1 member, rather than
+/// the whole array block in this case (In theory we could map its
+/// entirety at the cost of data transfer bandwidth).
+///
+/// %13:2 = hlfir.declare ... "alloca_dtype" ...
+/// %39 = fir.load %13#0 : ...
+/// %40 = fir.coordinate_of %39, %c1 : ...
+/// %51 = omp.map.info var_ptr(%40 : ...) map_clauses(to) capture(ByRef) ...
+/// %52 = fir.load %40 : ...
+///
+/// Second iteration generating access to "vertexes(N1) utilising the N1 index
+/// %53 = load N1 ...
+/// %54 = fir.convert %53 : (i32) -> i64
+/// %55 = fir.convert
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc, builder.getIntegerAttr(builder.getIntegerType(64, false), mapType), builder.getAttr(mapCaptureType), builder.getStringAttr(name), builder.getBoolAttr(partialMap)); - return op; } -static int +// This function gathers the individual omp::Object's that make up an skatrak wrote: ```suggestion // This function gathers the individual omp::Object's that make up a ``` https://github.com/llvm/llvm-project/pull/113557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
+// RHS to LHS ("member" to "parent") and then we reverse it so that the
+// returned omp::ObjectList is LHS to RHS, with the "parent" at the
+// beginning.
+omp::ObjectList gatherObjectsOf(omp::Object derivedTypeMember,
+semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = derivedTypeMember;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+// This function generates a series of indices from a provided omp::Object,
+// that devolves to an ArrayRef symbol, e.g. "array(2,3,4)", this function
+// would generate a series of indices of "[1][2][3]" for the above example,
+// offsetting by -1 to account for the non-zero fortran indexes.
+//
+// These indices can then be provided to a coordinate operation or other
+// GEP-like operation to access the relevant positional member of the
+// array.
+//
+// It is of note that the function only supports subscript integers currently
+// and not Triplets i.e. Array(1:2:3).
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ auto maybeRef = evaluate::ExtractDataRef(*object.ref());
+ if (!maybeRef)
+return;
+
+ auto *arr = std::get_if(&maybeRef->u);
+ if (!arr)
+return;
+
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
skatrak wrote:
Nit: This 'else' can be removed (only leaving its body), since
`llvm_unreachable` does not return. Also, it looks like the 'if' +
`llvm_unreachable` could be an `assert`.
However, is this an invalid condition to assert on or should it trigger a TODO
and inform the user instead?
https://github.com/llvm/llvm-project/pull/113557
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[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
https://github.com/skatrak edited https://github.com/llvm/llvm-project/pull/113557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -81,105 +135,192 @@ class MapInfoFinalizationPass
// !fir.ref> to access the data we need to map we must
// perform an alloca and then store to it and retrieve the data from the
new
// alloca.
-if (mlir::isa(descriptor.getType())) {
- // If we have already created a local allocation for this BoxType,
- // we must be sure to re-use it so that we end up with the same
- // allocations being utilised for the same descriptor across all map
uses,
- // this prevents runtime issues such as not appropriately releasing or
- // deleting all mapped data.
- auto find = localBoxAllocas.find(descriptor.getAsOpaquePointer());
- if (find != localBoxAllocas.end()) {
-builder.create(loc, descriptor, find->second);
-descriptor = find->second;
- } else {
-mlir::OpBuilder::InsertPoint insPt = builder.saveInsertionPoint();
-mlir::Block *allocaBlock = builder.getAllocaBlock();
-assert(allocaBlock && "No alloca block found for this top level op");
-builder.setInsertionPointToStart(allocaBlock);
-auto alloca = builder.create(loc, descriptor.getType());
-builder.restoreInsertionPoint(insPt);
-builder.create(loc, descriptor, alloca);
-localBoxAllocas[descriptor.getAsOpaquePointer()] = alloca;
-descriptor = alloca;
- }
-}
+mlir::OpBuilder::InsertPoint insPt = builder.saveInsertionPoint();
+mlir::Block *allocaBlock = builder.getAllocaBlock();
+mlir::Location loc = boxMap->getLoc();
+assert(allocaBlock && "No alloca block found for this top level op");
+builder.setInsertionPointToStart(allocaBlock);
+auto alloca = builder.create(loc, descriptor.getType());
+builder.restoreInsertionPoint(insPt);
+builder.create(loc, descriptor, alloca);
+return alloca;
+ }
+ /// Function that generates a FIR operation accessing the descriptor's
+ /// base address (BoxOffsetOp) and a MapInfoOp for it. The most
+ /// important thing to note is that we normally move the bounds from
+ /// the descriptor map onto the base address map.
+ mlir::omp::MapInfoOp genBaseAddrMap(mlir::Value descriptor,
+ mlir::OperandRange bounds,
+ int64_t mapType,
+ fir::FirOpBuilder &builder) {
+mlir::Location loc = descriptor.getLoc();
mlir::Value baseAddrAddr = builder.create(
loc, descriptor, fir::BoxFieldAttr::base_addr);
// Member of the descriptor pointing at the allocated data
-mlir::Value baseAddr = builder.create(
+return builder.create(
loc, baseAddrAddr.getType(), descriptor,
mlir::TypeAttr::get(llvm::cast(
fir::unwrapRefType(baseAddrAddr.getType()))
.getElementType()),
baseAddrAddr, /*members=*/mlir::SmallVector{},
-/*member_index=*/mlir::DenseIntElementsAttr{}, op.getBounds(),
-builder.getIntegerAttr(builder.getIntegerType(64, false),
- op.getMapType().value()),
+/*membersIndex=*/mlir::ArrayAttr{}, bounds,
+builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(
mlir::omp::VariableCaptureKind::ByRef),
/*name=*/builder.getStringAttr(""),
/*partial_map=*/builder.getBoolAttr(false));
+ }
-// TODO: map the addendum segment of the descriptor, similarly to the
-// above base address/data pointer member.
+ /// This function adjusts the member indices vector to include a new
+ /// base address member. We take the position of the descriptor in
+ /// the member indices list, which is the index data that the base
+ /// addresses index will be based off of, as the base address is
+ /// a member of the descriptor. We must also alter other members
+ /// that are members of this descriptor to account for the addition
+ /// of the base address index.
+ void adjustMemberIndices(
+ llvm::SmallVectorImpl> &memberIndices,
+ size_t memberIndex) {
+llvm::SmallVector baseAddrIndex = memberIndices[memberIndex];
-auto addOperands = [&](mlir::OperandRange &operandsArr,
- mlir::MutableOperandRange &mutableOpRange,
- auto directiveOp) {
- llvm::SmallVector newMapOps;
- for (size_t i = 0; i < operandsArr.size(); ++i) {
-if (operandsArr[i] == op) {
- // Push new implicit maps generated for the descriptor.
- newMapOps.push_back(baseAddr);
-
- // for TargetOp's which have IsolatedFromAbove we must align the
- // new additional map operand with an appropriate BlockArgument,
- // as the printing and later processing currently requires a 1:1
- // mapping of BlockArgs to MapInfoOp's at the same placement in
- // each array (BlockArgs and MapOperands).
-
[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Avoid generating nested CALLSEQ for TLS pointer function arguments (PR #106965)
https://github.com/ritter-x2a closed https://github.com/llvm/llvm-project/pull/106965 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Add -fmultilib-flag command-line option (PR #110658)
@@ -196,6 +196,16 @@ bool ToolChain::defaultToIEEELongDouble() const {
return PPC_LINUX_DEFAULT_IEEELONGDOUBLE && getTriple().isOSLinux();
}
+static void
+processARMAArch64MultilibCustomFlags(Multilib::flags_list &List,
vhscampos wrote:
Fixed
https://github.com/llvm/llvm-project/pull/110658
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[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
@@ -95,9 +96,113 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) {
void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); }
+static void WarnUnclaimedMultilibCustomFlags(
+const Driver &D, const SmallVector &UnclaimedCustomFlagValues,
+const SmallVector &CustomFlagDecls)
{
+ struct EditDistanceInfo {
+StringRef FlagValue;
+unsigned EditDistance;
+ };
+ const unsigned MaxEditDistance = 5;
+
+ for (StringRef Unclaimed : UnclaimedCustomFlagValues) {
+std::optional BestCandidate;
+for (const auto &Decl : CustomFlagDecls) {
+ for (const auto &Value : Decl->ValueList) {
+const std::string &FlagValueName = Value.Name;
+unsigned EditDistance =
+Unclaimed.edit_distance(FlagValueName, /*AllowReplacements=*/true,
+/*MaxEditDistance=*/MaxEditDistance);
+if (!BestCandidate || (EditDistance <= MaxEditDistance &&
+ EditDistance < BestCandidate->EditDistance)) {
+ BestCandidate = {FlagValueName, EditDistance};
+}
+ }
+}
+if (!BestCandidate)
+ D.Diag(clang::diag::warn_drv_unsupported_opt)
+ << (custom_flag::Prefix + Unclaimed).str();
+else
+ D.Diag(clang::diag::warn_drv_unsupported_opt_with_suggestion)
+ << (custom_flag::Prefix + Unclaimed).str()
+ << (custom_flag::Prefix + BestCandidate->FlagValue).str();
+ }
+}
+
+namespace clang::driver::custom_flag {
+class ValueNameToDetailMap {
+ SmallVector> Mapping;
+
+public:
+ template
+ ValueNameToDetailMap(It FlagDeclsBegin, It FlagDeclsEnd) {
+for (auto DeclIt = FlagDeclsBegin; DeclIt != FlagDeclsEnd; ++DeclIt) {
+ const CustomFlagDeclarationPtr &Decl = *DeclIt;
+ for (const auto &Value : Decl->ValueList)
+Mapping.emplace_back(Value.Name, &Value);
+}
+ }
+
+ const CustomFlagValueDetail *get(StringRef Key) const {
+auto Iter = llvm::find_if(
+Mapping, [&](const auto &Pair) { return Pair.first == Key; });
+return Iter != Mapping.end() ? Iter->second : nullptr;
+ }
+};
+} // namespace clang::driver::custom_flag
+
+Multilib::flags_list
+MultilibSet::processCustomFlags(const Driver &D,
+const Multilib::flags_list &Flags) const {
+ Multilib::flags_list Result;
+ SmallVector
+ ClaimedCustomFlagValues;
+ SmallVector UnclaimedCustomFlagValueStrs;
+
+ const auto ValueNameToValueDetail = custom_flag::ValueNameToDetailMap(
+ CustomFlagDecls.begin(), CustomFlagDecls.end());
+
+ for (StringRef Flag : Flags) {
+if (!Flag.starts_with(custom_flag::Prefix)) {
+ Result.push_back(Flag.str());
+ continue;
+}
+
+StringRef CustomFlagValueStr = Flag.substr(custom_flag::Prefix.size());
+const custom_flag::CustomFlagValueDetail *Detail =
+ValueNameToValueDetail.get(CustomFlagValueStr);
+if (Detail)
+ ClaimedCustomFlagValues.push_back(Detail);
+else
+ UnclaimedCustomFlagValueStrs.push_back(CustomFlagValueStr);
+ }
+
+ llvm::SmallSet
+ TriggeredCustomFlagDecls;
+
+ for (auto *CustomFlagValue : llvm::reverse(ClaimedCustomFlagValues)) {
+if (!TriggeredCustomFlagDecls.insert(CustomFlagValue->Decl).second)
+ continue;
+Result.push_back(std::string(custom_flag::Prefix) + CustomFlagValue->Name);
+ }
vhscampos wrote:
Fixed
https://github.com/llvm/llvm-project/pull/110659
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[llvm-branch-commits] [llvm] [TableGen] Fix calculation of Lanemask for RCs with artificial subregs. (PR #114392)
https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/114392
>From 303e1c87e0ea835d5892afaa04c9e72d2d1778f4 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Thu, 31 Oct 2024 09:54:52 +
Subject: [PATCH] [TableGen] Fix calculation of Lanemask for RCs with
artificial subregs.
TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is
the largest class where all registers have SubRegIdx as a
sub-register. When SubRegIdx (vis-a-vis the sub-register) is
artificial it should still include it in the map. This map is used in
various places, including in the calculation of the Lanemask of a
register class, which otherwise calculates an incorrect lanemask.
---
llvm/test/TableGen/ArtificialSubregs.td | 4 ++--
llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 10 --
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/llvm/test/TableGen/ArtificialSubregs.td
b/llvm/test/TableGen/ArtificialSubregs.td
index dbac129fb2463b..b8d5686dee51be 100644
--- a/llvm/test/TableGen/ArtificialSubregs.td
+++ b/llvm/test/TableGen/ArtificialSubregs.td
@@ -104,7 +104,7 @@ def TestTarget : Target;
// CHECK: SuperClasses:
//
// CHECK: RegisterClass DRegs:
-// CHECK: LaneMask: 0004
+// CHECK: LaneMask: 0044
// CHECK: HasDisjunctSubRegs: 1
// CHECK: CoveredBySubRegs: 1
// CHECK: Regs: D0 D1 D2
@@ -112,7 +112,7 @@ def TestTarget : Target;
// CHECK: SuperClasses:
//
// CHECK: RegisterClass QRegs:
-// CHECK: LaneMask: 0044
+// CHECK: LaneMask: 0045
// CHECK: HasDisjunctSubRegs: 1
// CHECK: CoveredBySubRegs: 1
// CHECK: Regs: Q0 Q1 Q2
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 2bf6a3740c486b..2dbee94d7e5406 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2300,10 +2300,8 @@ void
CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
if (R->Artificial)
continue;
const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
-for (auto I : SRM) {
- if (!I.first->Artificial)
-SRSets[I.first].push_back(R);
-}
+for (auto I : SRM)
+ SRSets[I.first].push_back(R);
}
for (auto I : SRSets)
@@ -2312,8 +2310,6 @@ void
CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// Find matching classes for all SRSets entries. Iterate in SubRegIndex
// numerical order to visit synthetic indices last.
for (const auto &SubIdx : SubRegIndices) {
-if (SubIdx.Artificial)
- continue;
SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
// Unsupported SubRegIndex. Skip it.
if (I == SRSets.end())
@@ -2323,6 +2319,8 @@ void
CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
RC->setSubClassWithSubReg(&SubIdx, RC);
continue;
}
+if (SubIdx.Artificial)
+ continue;
// This is a real subset. See if we have a matching class.
CodeGenRegisterClass *SubRC = getOrCreateSubClass(
RC, &I->second, RC->getName() + "_with_" + I->first->getName());
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[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
https://github.com/vhscampos edited https://github.com/llvm/llvm-project/pull/110659 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
@@ -14,6 +14,12 @@ def err_drv_no_such_file_with_suggestion : Error< def err_drv_unsupported_opt : Error<"unsupported option '%0'">; def err_drv_unsupported_opt_with_suggestion : Error< "unsupported option '%0'; did you mean '%1'?">; +def warn_drv_unsupported_opt : Warning< + "unsupported option '%0'">, + InGroup; +def warn_drv_unsupported_opt_with_suggestion : Warning< + "unsupported option '%0'; did you mean '%1'?">, + InGroup; vhscampos wrote: Fixed https://github.com/llvm/llvm-project/pull/110659 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
https://github.com/vhscampos updated
https://github.com/llvm/llvm-project/pull/110659
>From f2525efdd1f70c59923220b787be005903bdced5 Mon Sep 17 00:00:00 2001
From: Victor Campos
Date: Thu, 26 Sep 2024 14:44:33 +0100
Subject: [PATCH 1/2] [Multilib] Custom flags processing for library selection
Select library variants in the multilib system using the flags passed
following the '-fmultilib-flag=' format.
Multilib flags that were not passed in the command-line have their
default value fed into the library selection mechanism.
A warning is shown if the flag's value name is invalid. If the wrong
name is close enough to any valid one, according to edit distance, the
closest valid value name is suggested.
Details about this change can be found in this thread:
https://discourse.llvm.org/t/rfc-multilib-custom-flags/81058
---
.../clang/Basic/DiagnosticDriverKinds.td | 6 +
clang/include/clang/Driver/Multilib.h | 3 +
clang/lib/Driver/Driver.cpp | 4 +-
clang/lib/Driver/Multilib.cpp | 137 +-
.../baremetal-multilib-custom-flags.yaml | 57
5 files changed, 201 insertions(+), 6 deletions(-)
create mode 100644 clang/test/Driver/baremetal-multilib-custom-flags.yaml
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 65551bd7761a9d..6874614557f837 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -14,6 +14,12 @@ def err_drv_no_such_file_with_suggestion : Error<
def err_drv_unsupported_opt : Error<"unsupported option '%0'">;
def err_drv_unsupported_opt_with_suggestion : Error<
"unsupported option '%0'; did you mean '%1'?">;
+def warn_drv_unsupported_opt : Warning<
+ "unsupported option '%0'">,
+ InGroup;
+def warn_drv_unsupported_opt_with_suggestion : Warning<
+ "unsupported option '%0'; did you mean '%1'?">,
+ InGroup;
def err_drv_unsupported_opt_for_target : Error<
"unsupported option '%0' for target '%1'">;
def err_drv_unsupported_opt_for_language_mode : Error<
diff --git a/clang/include/clang/Driver/Multilib.h
b/clang/include/clang/Driver/Multilib.h
index 0662feb114c796..d0a3dd827e3531 100644
--- a/clang/include/clang/Driver/Multilib.h
+++ b/clang/include/clang/Driver/Multilib.h
@@ -163,6 +163,9 @@ class MultilibSet {
const_iterator begin() const { return Multilibs.begin(); }
const_iterator end() const { return Multilibs.end(); }
+ Multilib::flags_list
+ processCustomFlags(const Driver &D, const Multilib::flags_list &Flags) const;
+
/// Select compatible variants, \returns false if none are compatible
bool select(const Driver &D, const Multilib::flags_list &Flags,
llvm::SmallVectorImpl &) const;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 9878a9dad78d40..cee10d36070616 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -2324,9 +2324,7 @@ bool Driver::HandleImmediateArgs(Compilation &C) {
}
if (C.getArgs().hasArg(options::OPT_print_multi_lib)) {
-for (const Multilib &Multilib : TC.getMultilibs())
- if (!Multilib.isError())
-llvm::outs() << Multilib << "\n";
+llvm::outs() << TC.getMultilibs();
return false;
}
diff --git a/clang/lib/Driver/Multilib.cpp b/clang/lib/Driver/Multilib.cpp
index 236074478e7d84..adabf21057eb35 100644
--- a/clang/lib/Driver/Multilib.cpp
+++ b/clang/lib/Driver/Multilib.cpp
@@ -12,6 +12,7 @@
#include "clang/Driver/Driver.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Error.h"
@@ -95,9 +96,113 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) {
void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); }
+static void WarnUnclaimedMultilibCustomFlags(
+const Driver &D, const SmallVector &UnclaimedCustomFlagValues,
+const SmallVector &CustomFlagDecls)
{
+ struct EditDistanceInfo {
+StringRef FlagValue;
+unsigned EditDistance;
+ };
+ const unsigned MaxEditDistance = 5;
+
+ for (StringRef Unclaimed : UnclaimedCustomFlagValues) {
+std::optional BestCandidate;
+for (const auto &Decl : CustomFlagDecls) {
+ for (const auto &Value : Decl->ValueList) {
+const std::string &FlagValueName = Value.Name;
+unsigned EditDistance =
+Unclaimed.edit_distance(FlagValueName, /*AllowReplacements=*/true,
+/*MaxEditDistance=*/MaxEditDistance);
+if (!BestCandidate || (EditDistance <= MaxEditDistance &&
+ EditDistance < BestCandidate->EditDistance)) {
+ BestCandidate = {FlagValueName, EditDistance};
+}
+ }
+}
+if (!BestCandidate)
+ D.Diag(clang::diag::warn_drv_unsupported_opt)
+ << (custom_flag::Pref
[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
@@ -95,9 +96,113 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) {
void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); }
+static void WarnUnclaimedMultilibCustomFlags(
+const Driver &D, const SmallVector &UnclaimedCustomFlagValues,
+const SmallVector &CustomFlagDecls)
{
+ struct EditDistanceInfo {
+StringRef FlagValue;
+unsigned EditDistance;
+ };
+ const unsigned MaxEditDistance = 5;
+
+ for (StringRef Unclaimed : UnclaimedCustomFlagValues) {
+std::optional BestCandidate;
+for (const auto &Decl : CustomFlagDecls) {
+ for (const auto &Value : Decl->ValueList) {
+const std::string &FlagValueName = Value.Name;
+unsigned EditDistance =
+Unclaimed.edit_distance(FlagValueName, /*AllowReplacements=*/true,
+/*MaxEditDistance=*/MaxEditDistance);
+if (!BestCandidate || (EditDistance <= MaxEditDistance &&
+ EditDistance < BestCandidate->EditDistance)) {
+ BestCandidate = {FlagValueName, EditDistance};
+}
+ }
+}
+if (!BestCandidate)
+ D.Diag(clang::diag::warn_drv_unsupported_opt)
+ << (custom_flag::Prefix + Unclaimed).str();
+else
+ D.Diag(clang::diag::warn_drv_unsupported_opt_with_suggestion)
+ << (custom_flag::Prefix + Unclaimed).str()
+ << (custom_flag::Prefix + BestCandidate->FlagValue).str();
+ }
+}
+
+namespace clang::driver::custom_flag {
+class ValueNameToDetailMap {
+ SmallVector> Mapping;
+
+public:
+ template
+ ValueNameToDetailMap(It FlagDeclsBegin, It FlagDeclsEnd) {
+for (auto DeclIt = FlagDeclsBegin; DeclIt != FlagDeclsEnd; ++DeclIt) {
+ const CustomFlagDeclarationPtr &Decl = *DeclIt;
+ for (const auto &Value : Decl->ValueList)
+Mapping.emplace_back(Value.Name, &Value);
+}
+ }
+
+ const CustomFlagValueDetail *get(StringRef Key) const {
+auto Iter = llvm::find_if(
+Mapping, [&](const auto &Pair) { return Pair.first == Key; });
+return Iter != Mapping.end() ? Iter->second : nullptr;
+ }
+};
+} // namespace clang::driver::custom_flag
+
+Multilib::flags_list
+MultilibSet::processCustomFlags(const Driver &D,
+const Multilib::flags_list &Flags) const {
+ Multilib::flags_list Result;
+ SmallVector
+ ClaimedCustomFlagValues;
+ SmallVector UnclaimedCustomFlagValueStrs;
+
+ const auto ValueNameToValueDetail = custom_flag::ValueNameToDetailMap(
+ CustomFlagDecls.begin(), CustomFlagDecls.end());
+
+ for (StringRef Flag : Flags) {
+if (!Flag.starts_with(custom_flag::Prefix)) {
+ Result.push_back(Flag.str());
+ continue;
+}
+
+StringRef CustomFlagValueStr = Flag.substr(custom_flag::Prefix.size());
+const custom_flag::CustomFlagValueDetail *Detail =
+ValueNameToValueDetail.get(CustomFlagValueStr);
+if (Detail)
+ ClaimedCustomFlagValues.push_back(Detail);
+else
+ UnclaimedCustomFlagValueStrs.push_back(CustomFlagValueStr);
+ }
+
+ llvm::SmallSet
+ TriggeredCustomFlagDecls;
+
+ for (auto *CustomFlagValue : llvm::reverse(ClaimedCustomFlagValues)) {
+if (!TriggeredCustomFlagDecls.insert(CustomFlagValue->Decl).second)
+ continue;
+Result.push_back(std::string(custom_flag::Prefix) + CustomFlagValue->Name);
+ }
vhscampos wrote:
If the added comments aren't still good enough to improve clarity, please let
me know
https://github.com/llvm/llvm-project/pull/110659
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[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
https://github.com/sdesmalen-arm closed https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [llvm] Fix __builtin_object_size interaction between Negative Offset … (#111827) (PR #114786)
hvdijk wrote: The `version_check` failure is because the repo was expected to be updated after the last release, but it has not yet been. Based on https://discourse.llvm.org/t/potential-abi-break-in-19-1-3/82865 I assume this is because it is not yet decided what the next version number is supposed to be? Either way, I think we can ignore that error. But based on that discussion: this PR is also technically an ABI break. It breaks symbols that are public for technical reasons, but are meant to only be used by LLVM internally. What is the policy on that? Is that something that can go into `19.1.y`, or does that have to wait until `19.2.y`? (No preference either way from me.) https://github.com/llvm/llvm-project/pull/114786 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/arsenm commented: We want to moving things out of TargetOptions, not into. Can we turn this into a pass parameter, and just let the targets set it when they add the pass to the pipeline? Alternatively it seems to be just one debug flag, could move it directly into the pass instead of making targets create aliased cl::opts https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld][AArch64][ELF] Support signed TLSDESC (PR #113817)
smithp35 wrote: Just got back from vacation today. I plan to create a PR for the ABI tomorrow. Will take a look at this patch tomorrow. https://github.com/llvm/llvm-project/pull/113817 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
@@ -95,12 +107,29 @@ static const Function *findCalledFunction(const Module &M,
return nullptr;
}
-bool RegUsageInfoPropagation::runOnMachineFunction(MachineFunction &MF) {
- const Module &M = *MF.getFunction().getParent();
+bool RegUsageInfoPropagationLegacy::runOnMachineFunction(MachineFunction &MF) {
PhysicalRegisterUsageInfo *PRUI =
&getAnalysis().getPRUI();
- LLVM_DEBUG(dbgs() << " " << getPassName()
+ RegUsageInfoPropagation RUIP(PRUI);
+ return RUIP.run(MF);
+}
+
+PreservedAnalyses
+RegUsageInfoPropagationPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ Module &MFA = *MF.getFunction().getParent();
+ auto *PRUI = MFAM.getResult(MF)
+ .getCachedResult(MFA);
+ assert(PRUI && "PhysicalRegisterUsageAnalysis not available");
optimisan wrote:
It is an outer analysis so cannot run it from an inner IR,
https://github.com/llvm/llvm-project/pull/114010
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[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/114010 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From a95b69c07c7804d2e2a10b939a178a191643a41c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
.../llvm/CodeGen/RegUsageInfoCollector.h | 25
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoCollector.cpp| 60 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 5 ++
8 files changed, 76 insertions(+), 22 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
new file mode 100644
index 00..6b88cc4f99089e
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoCollector.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoCollector.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+#define LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoCollectorPass
+: public AnalysisInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOCOLLECTOR_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index edc237f2819818..44b7ba830bb329 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -257,7 +257,7 @@ void
initializeRegAllocPriorityAdvisorAnalysisPass(PassRegistry &);
void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
-void initializeRegUsageInfoCollectorPass(PassRegistry &);
+void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
void initializeRegUsageInfoPropagationPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 8cbc9f71ab26d0..066cd70ec8b996 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -53,6 +53,7 @@
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 7db28cb0092525..0ee4794034e98b 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -156,6 +156,7 @@ MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -250,7 +251,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass)
DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..e7e8a121369b75 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -113,7 +113,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRABasicPass(Registry);
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Reg
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 9792d73efca78fc55a9d25afb17448c7aeb490c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH 1/3] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
---
.../llvm/CodeGen/RegUsageInfoPropagate.h | 25 +++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp| 75 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/AArch64/preserve.ll | 4 +
8 files changed, 86 insertions(+), 26 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
diff --git a/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
new file mode 100644
index 00..73624015e37d9d
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegUsageInfoPropagate.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RegUsageInfoPropagate.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+#define LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RegUsageInfoPropagationPass
+: public PassInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGUSAGEINFOPROPAGATE_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 44b7ba830bb329..bc209a4e939415 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -258,7 +258,7 @@ void initializeRegAllocScoringPass(PassRegistry &);
void initializeRegBankSelectPass(PassRegistry &);
void initializeRegToMemWrapperPassPass(PassRegistry &);
void initializeRegUsageInfoCollectorLegacyPass(PassRegistry &);
-void initializeRegUsageInfoPropagationPass(PassRegistry &);
+void initializeRegUsageInfoPropagationLegacyPass(PassRegistry &);
void initializeRegionInfoPassPass(PassRegistry &);
void initializeRegionOnlyPrinterPass(PassRegistry &);
void initializeRegionOnlyViewerPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 066cd70ec8b996..9f41cc41a7c926 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -54,6 +54,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
+#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 0ee4794034e98b..6327ab1abd48e9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -157,6 +157,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
+MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -251,7 +252,6 @@ DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code",
PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
-DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation",
RegUsageInfoPropagationPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index e7e8a121369b75..013a9b3c9c4ffa 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -114,7 +114,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeRAGreedyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollector
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
+// RHS to LHS ("member" to "parent") and then we reverse it so that the
+// returned omp::ObjectList is LHS to RHS, with the "parent" at the
+// beginning.
+omp::ObjectList gatherObjectsOf(omp::Object derivedTypeMember,
+semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = derivedTypeMember;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+// This function generates a series of indices from a provided omp::Object,
+// that devolves to an ArrayRef symbol, e.g. "array(2,3,4)", this function
+// would generate a series of indices of "[1][2][3]" for the above example,
+// offsetting by -1 to account for the non-zero fortran indexes.
+//
+// These indices can then be provided to a coordinate operation or other
+// GEP-like operation to access the relevant positional member of the
+// array.
+//
+// It is of note that the function only supports subscript integers currently
+// and not Triplets i.e. Array(1:2:3).
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ auto maybeRef = evaluate::ExtractDataRef(*object.ref());
+ if (!maybeRef)
+return;
+
+ auto *arr = std::get_if(&maybeRef->u);
+ if (!arr)
+return;
+
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript =
+ fir::getBase(converter.genExprValue(toEvExpr(expr.value()),
stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+
+/// When mapping members of derived types, there is a chance that one of the
+/// members along the way to a mapped member is an descriptor. In which case
+/// we have to make sure we generate a map for those along the way otherwise
+/// we will be missing a chunk of data required to actually map the member
+/// type to device. This function effectively generates these maps and the
+/// appropriate data accesses required to generate these maps. It will avoid
+/// creating duplicate maps, as duplicates are just as bad as unmapped
+/// descriptor data in a lot of cases for the runtime (and unnecessary
+/// data movement should be avoided where possible).
+///
+/// As an example for the following mapping:
+///
+/// type :: vertexes
+/// integer(4), allocatable :: vertexx(:)
+/// integer(4), allocatable :: vertexy(:)
+/// end type vertexes
+///
+/// type :: dtype
+/// real(4) :: i
+/// type(vertexes), allocatable :: vertexes(:)
+/// end type dtype
+///
+/// type(dtype), allocatable :: alloca_dtype
+///
+/// !$omp target map(tofrom: alloca_dtype%vertexes(N1)%vertexx)
+///
+/// The below HLFIR/FIR is generated (trimmed for conciseness):
+///
+/// On the first iteration we index into the record type alloca_dtype
+/// to access "vertexes", we then generate a map for this descriptor
+/// alongside bounds to indicate we only need the 1 member, rather than
+/// the whole array block in this case (In theory we could map its
+/// entirety at the cost of data transfer bandwidth).
+///
+/// %13:2 = hlfir.declare ... "alloca_dtype" ...
+/// %39 = fir.load %13#0 : ...
+/// %40 = fir.coordinate_of %39, %c1 : ...
+/// %51 = omp.map.info var_ptr(%40 : ...) map_clauses(to) capture(ByRef) ...
+/// %52 = fir.load %40 : ...
+///
+/// Second iteration generating access to "vertexes(N1) utilising the N1 index
+/// %53 = load N1 ...
+/// %54 = fir.convert %53 : (i32) -> i64
+/// %55 = fir.convert
[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
skatrak wrote:
```suggestion
// introspect details. Important to note is this function breaks it up from
```
https://github.com/llvm/llvm-project/pull/113557
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[llvm-branch-commits] [flang] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #113557)
@@ -145,11 +145,294 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+// This function gathers the individual omp::Object's that make up an
+// larger omp::Object symbol.
+//
+// For example, provided the larger symbol: "parent%child%member", this
+// function breaks it up into it's constituent components ("parent",
+// "child", "member"), so we can access each individual component and
+// introspect details, important to note this function breaks it up from
+// RHS to LHS ("member" to "parent") and then we reverse it so that the
+// returned omp::ObjectList is LHS to RHS, with the "parent" at the
+// beginning.
+omp::ObjectList gatherObjectsOf(omp::Object derivedTypeMember,
+semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = derivedTypeMember;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+// This function generates a series of indices from a provided omp::Object,
+// that devolves to an ArrayRef symbol, e.g. "array(2,3,4)", this function
+// would generate a series of indices of "[1][2][3]" for the above example,
+// offsetting by -1 to account for the non-zero fortran indexes.
+//
+// These indices can then be provided to a coordinate operation or other
+// GEP-like operation to access the relevant positional member of the
+// array.
+//
+// It is of note that the function only supports subscript integers currently
+// and not Triplets i.e. Array(1:2:3).
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ auto maybeRef = evaluate::ExtractDataRef(*object.ref());
+ if (!maybeRef)
+return;
+
+ auto *arr = std::get_if(&maybeRef->u);
+ if (!arr)
+return;
+
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript =
+ fir::getBase(converter.genExprValue(toEvExpr(expr.value()),
stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+
+/// When mapping members of derived types, there is a chance that one of the
+/// members along the way to a mapped member is an descriptor. In which case
+/// we have to make sure we generate a map for those along the way otherwise
+/// we will be missing a chunk of data required to actually map the member
+/// type to device. This function effectively generates these maps and the
+/// appropriate data accesses required to generate these maps. It will avoid
+/// creating duplicate maps, as duplicates are just as bad as unmapped
+/// descriptor data in a lot of cases for the runtime (and unnecessary
+/// data movement should be avoided where possible).
+///
+/// As an example for the following mapping:
+///
+/// type :: vertexes
+/// integer(4), allocatable :: vertexx(:)
+/// integer(4), allocatable :: vertexy(:)
+/// end type vertexes
+///
+/// type :: dtype
+/// real(4) :: i
+/// type(vertexes), allocatable :: vertexes(:)
+/// end type dtype
+///
+/// type(dtype), allocatable :: alloca_dtype
+///
+/// !$omp target map(tofrom: alloca_dtype%vertexes(N1)%vertexx)
+///
+/// The below HLFIR/FIR is generated (trimmed for conciseness):
+///
+/// On the first iteration we index into the record type alloca_dtype
+/// to access "vertexes", we then generate a map for this descriptor
+/// alongside bounds to indicate we only need the 1 member, rather than
+/// the whole array block in this case (In theory we could map its
+/// entirety at the cost of data transfer bandwidth).
+///
+/// %13:2 = hlfir.declare ... "alloca_dtype" ...
+/// %39 = fir.load %13#0 : ...
+/// %40 = fir.coordinate_of %39, %c1 : ...
+/// %51 = omp.map.info var_ptr(%40 : ...) map_clauses(to) capture(ByRef) ...
+/// %52 = fir.load %40 : ...
+///
+/// Second iteration generating access to "vertexes(N1) utilising the N1 index
+/// %53 = load N1 ...
+/// %54 = fir.convert %53 : (i32) -> i64
+/// %55 = fir.convert
[llvm-branch-commits] [lld] [PAC][lld] Do not emit warnings for `-z pac-plt` with valid PAuth core info (PR #112959)
https://github.com/DanielKristofKiss approved this pull request. lgtm https://github.com/llvm/llvm-project/pull/112959 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [llvm] [Flang] Move runtime library files to flang-rt. NFC (PR #110298)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/110298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)
@@ -740,6 +740,16 @@ struct AAAMDSizeRangeAttribute
if (!CallerInfo || !CallerInfo->isValidState())
return false;
+ /// When the caller AA is in its initial state, the state remains valid
+ /// but awaits propagation. We skip processing in this case. Note that we
+ /// must return true since the state is still considered valid.
+ if (CallerInfo->isAtInitialState()) {
+LLVM_DEBUG(dbgs() << '[' << getName() << "] Caller "
+ << Caller->getName()
arsenm wrote:
use printAsOperand to handle anonymous functions correctly
https://github.com/llvm/llvm-project/pull/114726
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[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT:addi sp, sp, -16
; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:call bcmp
+; CHECK-RV32-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT:addi sp, sp, 16
+; CHECK-RV32-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-ZBB-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-ZBB-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-ZBB-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-ZBB-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-ZBB-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-ZBB-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-ZBB-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-ZBB-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-ZBKB-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-V-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-V-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-V-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-V-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-V-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-V-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a4, a0
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-ZBB-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a0, a4, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-ZBKB-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:or a0, a4, a
[llvm-branch-commits] [lld] [PAC][lld] Use braa instr in PAC PLT sequence with valid PAuth core info (PR #113945)
@@ -1096,8 +1113,10 @@ void AArch64BtiPac::writePlt(uint8_t *buf, const Symbol &sym, relocateNoSym(buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, gotPltEntryAddr); relocateNoSym(buf + 8, R_AARCH64_ADD_ABS_LO12_NC, gotPltEntryAddr); - if (pacEntry) -memcpy(buf + sizeof(addrInst), pacBr, sizeof(pacBr)); + if (pacEntryKind != PEK_NoAuth) +memcpy(buf + sizeof(addrInst), + pacEntryKind == PEK_AuthHint ? pacHintBr : pacBr, smithp35 wrote: Could be a possibility to make pacHintBr and pacBr into an array indexed by pacEntryKind. ``` memcpy(buf + sizeof(addrInst), pacBrInstrs[pacEntryKind], sizeof(pacBrInstrs[pacEntryKind])); ``` Not sure if it is worth the trouble though. https://github.com/llvm/llvm-project/pull/113945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld] Use braa instr in PAC PLT sequence with valid PAuth core info (PR #113945)
@@ -1014,9 +1018,18 @@ AArch64BtiPac::AArch64BtiPac(Ctx &ctx) : AArch64(ctx) {
// relocations.
// The PAC PLT entries require dynamic loader support and this isn't known
// from properties in the objects, so we use the command line flag.
- pacEntry = ctx.arg.zPacPlt;
smithp35 wrote:
It could be worth adding to the comment here. Something like:
```
By default we only use hint-space instructions, but if we detect the PAuthABI,
which requires v8.3-A we can use the non-hint space instructions.
```
https://github.com/llvm/llvm-project/pull/113945
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[llvm-branch-commits] [lld] [PAC][lld] Use braa instr in PAC PLT sequence with valid PAuth core info (PR #113945)
https://github.com/smithp35 edited https://github.com/llvm/llvm-project/pull/113945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld] Use braa instr in PAC PLT sequence with valid PAuth core info (PR #113945)
https://github.com/smithp35 commented: No objections from me. A small suggestion for the comment and a possible simplification. https://github.com/llvm/llvm-project/pull/113945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
https://github.com/wangleiat updated
https://github.com/llvm/llvm-project/pull/114742
>From f390561ee9c49dd10f0b13b79b713624664d7da2 Mon Sep 17 00:00:00 2001
From: wanglei
Date: Mon, 4 Nov 2024 17:12:03 +0800
Subject: [PATCH] comply with code style
Created using spr 1.3.5-bogner
---
lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
index 6e57b0806e54f5..5069bc48bbfba2 100644
--- a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
+++ b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
@@ -6,8 +6,8 @@
//
//===--===//
-#ifndef liblldb_ABISysV_loongarch_h_
-#define liblldb_ABISysV_loongarch_h_
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
// Other libraries and framework includes
#include "llvm/TargetParser/Triple.h"
@@ -101,4 +101,4 @@ class ABISysV_loongarch : public
lldb_private::RegInfoBasedABI {
// loongarch32
};
-#endif // liblldb_ABISysV_loongarch_h_
+#endif // LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: AMDGPURegBankLegalize (PR #112864)
petar-avramovic wrote: Ping. There were changes because of improvements to builder accepting regbank+LLT, think I addressed most of the comments. https://github.com/llvm/llvm-project/pull/112864 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT:addi sp, sp, -16
; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:call bcmp
+; CHECK-RV32-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT:addi sp, sp, 16
+; CHECK-RV32-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-ZBB-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-ZBB-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-ZBB-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-ZBB-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-ZBB-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-ZBB-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-ZBB-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-ZBB-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-ZBKB-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-V-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-V-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-V-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-V-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-V-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-V-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a4, a0
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-ZBB-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a0, a4, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-ZBKB-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:or a0, a4, a
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114745
>From e7e38bc2bce6add242f8af0d2a1d942fdecab3ed Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:59:30 +
Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM
---
.../llvm/CodeGen/MachineCycleAnalysis.h | 18 ++
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 3 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/MachineCycleAnalysis.cpp | 34 ++-
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/X86/cycle-info.mir | 2 ++
7 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
index 1888dd053ce65e..f740a9599edf29 100644
--- a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/GenericCycleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineSSAContext.h"
namespace llvm {
@@ -46,6 +47,23 @@ class MachineCycleInfoWrapperPass : public
MachineFunctionPass {
// version.
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
+class MachineCycleAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = MachineCycleInfo;
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class MachineCycleInfoPrinterPass : public
PassInfoMixin {
+ raw_ostream &OS;
+ public:
+explicit MachineCycleInfoPrinterPass(raw_ostream &OS) : OS(OS) {}
+PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager
&MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINECYCLEANALYSIS_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 54c070401ec8a4..b040e7c096d1f5 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -191,7 +191,7 @@ void initializeMachineCFGPrinterPass(PassRegistry &);
void initializeMachineCSELegacyPass(PassRegistry &);
void initializeMachineCombinerPass(PassRegistry &);
void initializeMachineCopyPropagationPass(PassRegistry &);
-void initializeMachineCycleInfoPrinterPassPass(PassRegistry &);
+void initializeMachineCycleInfoPrinterLegacyPass(PassRegistry &);
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &);
void initializeMachineDominanceFrontierPass(PassRegistry &);
void initializeMachineDominatorTreeWrapperPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9d12a120ff7ac6..bfe8caba0ce0b3 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -101,6 +101,7 @@ MACHINE_FUNCTION_ANALYSIS("live-vars",
LiveVariablesAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-cycles", MachineCycleAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
@@ -151,6 +152,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print",
MachineDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", MachineLoopPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print",
MachineCycleInfoPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
@@ -241,7 +243,6 @@ DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched",
PostRASchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
-DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles",
MachineCycleInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity",
MachineUniformityInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..adddb8daaa0e91 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -78,7 +78,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachineCSELegacyPass(Registry);
initializeMachineCombinerPass(Re
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From 4e815d99d6c214f0780d70224559a5eb7504cdc6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 8
llvm/include/llvm/Target/TargetOptions.h | 8 +++-
llvm/lib/CodeGen/MachineSink.cpp | 5 -
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 ++--
5 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+/// a computation can be folded into the addressing mode of a memory
+/// load/store instruction or replace a copy.
+unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..a3a6b24f9be2d1 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include
#include
#include
@@ -729,7 +730,9 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
+ // EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
-setEnableSinkAndFold(EnableSinkFold);
+TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
i
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
preames wrote: At a macro level, it looks like ExpandMemCmp is making some problematic choices around unaligned loads and stores. As I commented before, ExpandMemCmp appears to be blindly emitting unaligned accesses (counted as one against budget) without accounting for the fact that such loads are going to be scalarized again (i.e. resulting in N x loads, where N is the type size). I think we need to fix this. In particular, the discussion around Zbb and Zbkb in this review seem to mostly come from cases where unaligned load.store are being expanded implicitly, I don't believe this change should move forward until the underlying issue in ExpandMemCmp has been addressed. https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)
@@ -740,6 +740,16 @@ struct AAAMDSizeRangeAttribute
if (!CallerInfo || !CallerInfo->isValidState())
return false;
+ /// When the caller AA is in its initial state, the state remains valid
+ /// but awaits propagation. We skip processing in this case. Note that we
+ /// must return true since the state is still considered valid.
+ if (CallerInfo->isAtInitialState()) {
+LLVM_DEBUG(dbgs() << '[' << getName() << "] Caller "
+ << Caller->getName()
shiltian wrote:
This is copied from existing code. I'll do a follow up patch to change them all.
https://github.com/llvm/llvm-project/pull/114726
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] c110aaa - Revert "[HLSL] add IsTypedResourceElementCompatible type trait (#113730)"
Author: Joshua Batista
Date: 2024-11-04T11:11:46-08:00
New Revision: c110aaa2eb7862657df58c5f76e4231f27110450
URL:
https://github.com/llvm/llvm-project/commit/c110aaa2eb7862657df58c5f76e4231f27110450
DIFF:
https://github.com/llvm/llvm-project/commit/c110aaa2eb7862657df58c5f76e4231f27110450.diff
LOG: Revert "[HLSL] add IsTypedResourceElementCompatible type trait (#113730)"
This reverts commit 4894c67230135c8cb177c0bff45a99c8bf09cefe.
Added:
Modified:
clang/include/clang/Basic/TokenKinds.def
clang/include/clang/Sema/SemaHLSL.h
clang/lib/Sema/SemaExprCXX.cpp
clang/lib/Sema/SemaHLSL.cpp
Removed:
clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl
diff --git a/clang/include/clang/Basic/TokenKinds.def
b/clang/include/clang/Basic/TokenKinds.def
index 2c692c999bdff5..fdfb35de9cf287 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -662,7 +662,6 @@ KEYWORD(out , KEYHLSL)
// HLSL Type traits
TYPE_TRAIT_2(__builtin_hlsl_is_scalarized_layout_compatible,
IsScalarizedLayoutCompatible, KEYHLSL)
TYPE_TRAIT_1(__builtin_hlsl_is_intangible, IsIntangibleType, KEYHLSL)
-TYPE_TRAIT_1(__builtin_hlsl_is_typed_resource_element_compatible,
IsTypedResourceElementCompatible, KEYHLSL)
// OpenMP Type Traits
UNARY_EXPR_OR_TYPE_TRAIT(__builtin_omp_required_simd_align,
OpenMPRequiredSimdAlign, KEYALL)
diff --git a/clang/include/clang/Sema/SemaHLSL.h
b/clang/include/clang/Sema/SemaHLSL.h
index 06c541dec08cc8..e30acd87f77218 100644
--- a/clang/include/clang/Sema/SemaHLSL.h
+++ b/clang/include/clang/Sema/SemaHLSL.h
@@ -132,7 +132,6 @@ class SemaHLSL : public SemaBase {
// HLSL Type trait implementations
bool IsScalarizedLayoutCompatible(QualType T1, QualType T2) const;
- bool IsTypedResourceElementCompatible(QualType T1);
bool CheckCompatibleParameterABI(FunctionDecl *New, FunctionDecl *Old);
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index 0001e343da84be..50c1b24fce6da7 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -5032,7 +5032,6 @@ static bool CheckUnaryTypeTraitTypeCompleteness(Sema &S,
TypeTrait UTT,
case UTT_IsScalar:
case UTT_IsCompound:
case UTT_IsMemberPointer:
- case UTT_IsTypedResourceElementCompatible:
// Fall-through
// These traits are modeled on type predicates in C++0x [meta.unary.prop]
@@ -5715,15 +5714,6 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait
UTT,
tok::kw___builtin_hlsl_is_intangible))
return false;
return T->isHLSLIntangibleType();
-
- case UTT_IsTypedResourceElementCompatible:
-assert(Self.getLangOpts().HLSL &&
- "line vector layout compatible types are HLSL-only feature");
-if (Self.RequireCompleteType(TInfo->getTypeLoc().getBeginLoc(), T,
- diag::err_incomplete_type))
- return false;
-
-return Self.HLSL().IsTypedResourceElementCompatible(T);
}
}
diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp
index e5eb75765383c0..a472538236e2d9 100644
--- a/clang/lib/Sema/SemaHLSL.cpp
+++ b/clang/lib/Sema/SemaHLSL.cpp
@@ -2199,51 +2199,6 @@ static void BuildFlattenedTypeList(QualType BaseTy,
}
}
-bool SemaHLSL::IsTypedResourceElementCompatible(clang::QualType QT) {
- if (QT.isNull())
-return false;
-
- // check if the outer type was an array type
- if (QT->isArrayType())
-return false;
-
- llvm::SmallVector QTTypes;
- BuildFlattenedTypeList(QT, QTTypes);
-
- assert(QTTypes.size() > 0 &&
- "expected at least one constituent type from non-null type");
- QualType FirstQT = QTTypes[0];
-
- // element count cannot exceed 4
- if (QTTypes.size() > 4)
-return false;
-
- for (QualType TempQT : QTTypes) {
-// ensure homogeneity
-if (TempQT != FirstQT)
- return false;
-
-if (const BuiltinType *BT = TempQT->getAs()) {
- if (BT->getKind() == BuiltinType::Bool ||
- BT->getKind() == BuiltinType::Enum)
-return false;
-
- // Check if it is an array type.
- if (TempQT->isArrayType())
-return false;
-}
- }
-
- // if the loop above completes without returning, then
- // we've guaranteed homogeneity
- int TotalSizeInBytes =
- (SemaRef.Context.getTypeSize(FirstQT) / 8) * QTTypes.size();
- if (TotalSizeInBytes > 16)
-return false;
-
- return true;
-}
-
bool SemaHLSL::IsScalarizedLayoutCompatible(QualType T1, QualType T2) const {
if (T1.isNull() || T2.isNull())
return false;
diff --git
a/clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
b/clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
deleted file mode 100644
index 66
[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)
@@ -219,14 +219,14 @@ __extension__ typedef __int128 a128; // Part of ABI, do not change. vitalybuka wrote: Does #114916 help? https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From 51b20bb48e08130eaa6e3a71f91d06d02e2e23d9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 8
llvm/include/llvm/Target/TargetOptions.h | 8 +++-
llvm/lib/CodeGen/MachineSink.cpp | 5 -
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 ++--
5 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+/// a computation can be folded into the addressing mode of a memory
+/// load/store instruction or replace a copy.
+unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..a3a6b24f9be2d1 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include
#include
#include
@@ -729,7 +730,9 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
+ // EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
-setEnableSinkAndFold(EnableSinkFold);
+TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
i
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114745
>From ada4056395347f4bc5f138bd8bca31710629c155 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:59:30 +
Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM
---
.../llvm/CodeGen/MachineCycleAnalysis.h | 21 ++
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 3 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/MachineCycleAnalysis.cpp | 38 ++-
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/test/CodeGen/X86/cycle-info.mir | 2 +
7 files changed, 57 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
index 1888dd053ce65e..64cf30e6ddf3b8 100644
--- a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/GenericCycleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineSSAContext.h"
namespace llvm {
@@ -46,6 +47,26 @@ class MachineCycleInfoWrapperPass : public
MachineFunctionPass {
// version.
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
+class MachineCycleAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = MachineCycleInfo;
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class MachineCycleInfoPrinterPass
+: public PassInfoMixin {
+ raw_ostream &OS;
+
+public:
+ explicit MachineCycleInfoPrinterPass(raw_ostream &OS) : OS(OS) {}
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINECYCLEANALYSIS_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 54c070401ec8a4..b040e7c096d1f5 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -191,7 +191,7 @@ void initializeMachineCFGPrinterPass(PassRegistry &);
void initializeMachineCSELegacyPass(PassRegistry &);
void initializeMachineCombinerPass(PassRegistry &);
void initializeMachineCopyPropagationPass(PassRegistry &);
-void initializeMachineCycleInfoPrinterPassPass(PassRegistry &);
+void initializeMachineCycleInfoPrinterLegacyPass(PassRegistry &);
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &);
void initializeMachineDominanceFrontierPass(PassRegistry &);
void initializeMachineDominatorTreeWrapperPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9d12a120ff7ac6..bfe8caba0ce0b3 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -101,6 +101,7 @@ MACHINE_FUNCTION_ANALYSIS("live-vars",
LiveVariablesAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-cycles", MachineCycleAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
@@ -151,6 +152,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print",
MachineDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", MachineLoopPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print",
MachineCycleInfoPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
@@ -241,7 +243,6 @@ DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched",
PostRASchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
-DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles",
MachineCycleInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity",
MachineUniformityInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..adddb8daaa0e91 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -78,7 +78,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachineCSELegacyPass(Registry);
initializ
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/114745.diff
7 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineCycleAnalysis.h (+21)
- (modified) llvm/include/llvm/InitializePasses.h (+1-1)
- (modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+2-1)
- (modified) llvm/lib/CodeGen/CodeGen.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineCycleAnalysis.cpp (+29-9)
- (modified) llvm/lib/Passes/PassBuilder.cpp (+1)
- (modified) llvm/test/CodeGen/X86/cycle-info.mir (+2)
``diff
diff --git a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
index 1888dd053ce65e..64cf30e6ddf3b8 100644
--- a/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/GenericCycleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineSSAContext.h"
namespace llvm {
@@ -46,6 +47,26 @@ class MachineCycleInfoWrapperPass : public
MachineFunctionPass {
// version.
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
+class MachineCycleAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = MachineCycleInfo;
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class MachineCycleInfoPrinterPass
+: public PassInfoMixin {
+ raw_ostream &OS;
+
+public:
+ explicit MachineCycleInfoPrinterPass(raw_ostream &OS) : OS(OS) {}
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINECYCLEANALYSIS_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 54c070401ec8a4..b040e7c096d1f5 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -191,7 +191,7 @@ void initializeMachineCFGPrinterPass(PassRegistry &);
void initializeMachineCSELegacyPass(PassRegistry &);
void initializeMachineCombinerPass(PassRegistry &);
void initializeMachineCopyPropagationPass(PassRegistry &);
-void initializeMachineCycleInfoPrinterPassPass(PassRegistry &);
+void initializeMachineCycleInfoPrinterLegacyPass(PassRegistry &);
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &);
void initializeMachineDominanceFrontierPass(PassRegistry &);
void initializeMachineDominatorTreeWrapperPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9d12a120ff7ac6..bfe8caba0ce0b3 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -101,6 +101,7 @@ MACHINE_FUNCTION_ANALYSIS("live-vars",
LiveVariablesAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-cycles", MachineCycleAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
@@ -151,6 +152,7 @@ MACHINE_FUNCTION_PASS("print",
MACHINE_FUNCTION_PASS("print",
MachineDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", MachineLoopPrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print",
MachineCycleInfoPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print",
MachinePostDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs()))
@@ -241,7 +243,6 @@ DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched",
PostRASchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
-DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles",
MachineCycleInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity",
MachineUniformityInfoPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..adddb8daaa0e91 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -78,7 +78,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachineCSELegacyPass(Registry);
initializeMachineCombinerPass(Registry);
initializeMachineCopyPropagationPass(Registry);
- initializeMachineCycleInfoPrinterPass
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)
https://github.com/optimisan ready_for_review https://github.com/llvm/llvm-project/pull/114745 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)
https://github.com/melver approved this pull request. https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [tsan] Don't use `enum __tsan_memory_order` in tsan interface (PR #114724)
@@ -219,14 +219,14 @@ __extension__ typedef __int128 a128; // Part of ABI, do not change. melver wrote: Is it still following the ABI - if we do not static_cast it to int, then I don't think this is strictly required to follow ABI. https://github.com/llvm/llvm-project/pull/114724 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [llvm] Fix __builtin_object_size interaction between Negative Offset … (#111827) (PR #114786)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: None (llvmbot)
Changes
Backport 01a103b0b9c449e8dec17950835991757d1c4f88
Requested by: @hvdijk
---
Patch is 30.47 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/114786.diff
4 Files Affected:
- (modified) llvm/include/llvm/Analysis/MemoryBuiltins.h (+47-24)
- (modified) llvm/lib/Analysis/MemoryBuiltins.cpp (+80-65)
- (modified)
llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-phi.ll (+254)
- (modified) llvm/test/Transforms/LowerConstantIntrinsics/objectsize_basic.ll
(+24)
``diff
diff --git a/llvm/include/llvm/Analysis/MemoryBuiltins.h
b/llvm/include/llvm/Analysis/MemoryBuiltins.h
index bb282a1b73d320..a21f116db7e70d 100644
--- a/llvm/include/llvm/Analysis/MemoryBuiltins.h
+++ b/llvm/include/llvm/Analysis/MemoryBuiltins.h
@@ -222,21 +222,43 @@ struct SizeOffsetAPInt : public SizeOffsetType {
static bool known(const APInt &V) { return V.getBitWidth() > 1; }
};
+/// OffsetSpan - Used internally by \p ObjectSizeOffsetVisitor. Represents a
+/// point in memory as a pair of allocated bytes before and after it.
+struct OffsetSpan {
+ APInt Before; /// Number of allocated bytes before this point.
+ APInt After; /// Number of allocated bytes after this point.
+
+ OffsetSpan() = default;
+ OffsetSpan(APInt Before, APInt After) : Before(Before), After(After) {}
+
+ bool knownBefore() const { return known(Before); }
+ bool knownAfter() const { return known(After); }
+ bool anyKnown() const { return knownBefore() || knownAfter(); }
+ bool bothKnown() const { return knownBefore() && knownAfter(); }
+
+ bool operator==(const OffsetSpan &RHS) const {
+return Before == RHS.Before && After == RHS.After;
+ }
+ bool operator!=(const OffsetSpan &RHS) const { return !(*this == RHS); }
+
+ static bool known(const APInt &V) { return V.getBitWidth() > 1; }
+};
+
/// Evaluate the size and offset of an object pointed to by a Value*
/// statically. Fails if size or offset are not known at compile time.
class ObjectSizeOffsetVisitor
-: public InstVisitor {
+: public InstVisitor {
const DataLayout &DL;
const TargetLibraryInfo *TLI;
ObjectSizeOpts Options;
unsigned IntTyBits;
APInt Zero;
- SmallDenseMap SeenInsts;
+ SmallDenseMap SeenInsts;
unsigned InstructionsVisited;
APInt align(APInt Size, MaybeAlign Align);
- static SizeOffsetAPInt unknown() { return SizeOffsetAPInt(); }
+ static OffsetSpan unknown() { return OffsetSpan(); }
public:
ObjectSizeOffsetVisitor(const DataLayout &DL, const TargetLibraryInfo *TLI,
@@ -246,29 +268,30 @@ class ObjectSizeOffsetVisitor
// These are "private", except they can't actually be made private. Only
// compute() should be used by external users.
- SizeOffsetAPInt visitAllocaInst(AllocaInst &I);
- SizeOffsetAPInt visitArgument(Argument &A);
- SizeOffsetAPInt visitCallBase(CallBase &CB);
- SizeOffsetAPInt visitConstantPointerNull(ConstantPointerNull &);
- SizeOffsetAPInt visitExtractElementInst(ExtractElementInst &I);
- SizeOffsetAPInt visitExtractValueInst(ExtractValueInst &I);
- SizeOffsetAPInt visitGlobalAlias(GlobalAlias &GA);
- SizeOffsetAPInt visitGlobalVariable(GlobalVariable &GV);
- SizeOffsetAPInt visitIntToPtrInst(IntToPtrInst &);
- SizeOffsetAPInt visitLoadInst(LoadInst &I);
- SizeOffsetAPInt visitPHINode(PHINode &);
- SizeOffsetAPInt visitSelectInst(SelectInst &I);
- SizeOffsetAPInt visitUndefValue(UndefValue &);
- SizeOffsetAPInt visitInstruction(Instruction &I);
+ OffsetSpan visitAllocaInst(AllocaInst &I);
+ OffsetSpan visitArgument(Argument &A);
+ OffsetSpan visitCallBase(CallBase &CB);
+ OffsetSpan visitConstantPointerNull(ConstantPointerNull &);
+ OffsetSpan visitExtractElementInst(ExtractElementInst &I);
+ OffsetSpan visitExtractValueInst(ExtractValueInst &I);
+ OffsetSpan visitGlobalAlias(GlobalAlias &GA);
+ OffsetSpan visitGlobalVariable(GlobalVariable &GV);
+ OffsetSpan visitIntToPtrInst(IntToPtrInst &);
+ OffsetSpan visitLoadInst(LoadInst &I);
+ OffsetSpan visitPHINode(PHINode &);
+ OffsetSpan visitSelectInst(SelectInst &I);
+ OffsetSpan visitUndefValue(UndefValue &);
+ OffsetSpan visitInstruction(Instruction &I);
private:
- SizeOffsetAPInt findLoadSizeOffset(
- LoadInst &LoadFrom, BasicBlock &BB, BasicBlock::iterator From,
- SmallDenseMap &VisitedBlocks,
- unsigned &ScannedInstCount);
- SizeOffsetAPInt combineSizeOffset(SizeOffsetAPInt LHS, SizeOffsetAPInt RHS);
- SizeOffsetAPInt computeImpl(Value *V);
- SizeOffsetAPInt computeValue(Value *V);
+ OffsetSpan
+ findLoadOffsetRange(LoadInst &LoadFrom, BasicBlock &BB,
+ BasicBlock::iterator From,
+ SmallDenseMap
&VisitedBlocks,
+ unsigned &ScannedInstCount);
+ OffsetSpan combineOffsetRange(OffsetSpan LHS, OffsetSpan RHS);
+ OffsetSpan computeImpl(Value *V);
+ OffsetSpan computeValue(Value *V);
[llvm-branch-commits] [llvm] release/19.x: [llvm] Fix __builtin_object_size interaction between Negative Offset … (#111827) (PR #114786)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/114786
Backport 01a103b0b9c449e8dec17950835991757d1c4f88
Requested by: @hvdijk
>From c228140e0bfddb21d24535e6c81cad00f46db749 Mon Sep 17 00:00:00 2001
From: serge-sans-paille
Date: Sat, 2 Nov 2024 09:14:35 +
Subject: [PATCH] =?UTF-8?q?[llvm]=20Fix=20=5F=5Fbuiltin=5Fobject=5Fsize=20?=
=?UTF-8?q?interaction=20between=20Negative=20Offset=20=E2=80=A6=20(#11182?=
=?UTF-8?q?7)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
…and Select/Phi
When picking a SizeOffsetAPInt through combineSizeOffset, the behavior
differs if we're going to apply a constant offset that's positive or
negative: If it's positive, then we need to compare the remaining bytes
(i.e. Size
- Offset), but if it's negative, we need to compare the preceding bytes
(i.e. Offset).
Fix #111709
(cherry picked from commit 01a103b0b9c449e8dec17950835991757d1c4f88)
---
llvm/include/llvm/Analysis/MemoryBuiltins.h | 71 +++--
llvm/lib/Analysis/MemoryBuiltins.cpp | 145 +-
.../builtin-object-size-phi.ll| 254 ++
.../objectsize_basic.ll | 24 ++
4 files changed, 405 insertions(+), 89 deletions(-)
diff --git a/llvm/include/llvm/Analysis/MemoryBuiltins.h
b/llvm/include/llvm/Analysis/MemoryBuiltins.h
index bb282a1b73d320..a21f116db7e70d 100644
--- a/llvm/include/llvm/Analysis/MemoryBuiltins.h
+++ b/llvm/include/llvm/Analysis/MemoryBuiltins.h
@@ -222,21 +222,43 @@ struct SizeOffsetAPInt : public SizeOffsetType {
static bool known(const APInt &V) { return V.getBitWidth() > 1; }
};
+/// OffsetSpan - Used internally by \p ObjectSizeOffsetVisitor. Represents a
+/// point in memory as a pair of allocated bytes before and after it.
+struct OffsetSpan {
+ APInt Before; /// Number of allocated bytes before this point.
+ APInt After; /// Number of allocated bytes after this point.
+
+ OffsetSpan() = default;
+ OffsetSpan(APInt Before, APInt After) : Before(Before), After(After) {}
+
+ bool knownBefore() const { return known(Before); }
+ bool knownAfter() const { return known(After); }
+ bool anyKnown() const { return knownBefore() || knownAfter(); }
+ bool bothKnown() const { return knownBefore() && knownAfter(); }
+
+ bool operator==(const OffsetSpan &RHS) const {
+return Before == RHS.Before && After == RHS.After;
+ }
+ bool operator!=(const OffsetSpan &RHS) const { return !(*this == RHS); }
+
+ static bool known(const APInt &V) { return V.getBitWidth() > 1; }
+};
+
/// Evaluate the size and offset of an object pointed to by a Value*
/// statically. Fails if size or offset are not known at compile time.
class ObjectSizeOffsetVisitor
-: public InstVisitor {
+: public InstVisitor {
const DataLayout &DL;
const TargetLibraryInfo *TLI;
ObjectSizeOpts Options;
unsigned IntTyBits;
APInt Zero;
- SmallDenseMap SeenInsts;
+ SmallDenseMap SeenInsts;
unsigned InstructionsVisited;
APInt align(APInt Size, MaybeAlign Align);
- static SizeOffsetAPInt unknown() { return SizeOffsetAPInt(); }
+ static OffsetSpan unknown() { return OffsetSpan(); }
public:
ObjectSizeOffsetVisitor(const DataLayout &DL, const TargetLibraryInfo *TLI,
@@ -246,29 +268,30 @@ class ObjectSizeOffsetVisitor
// These are "private", except they can't actually be made private. Only
// compute() should be used by external users.
- SizeOffsetAPInt visitAllocaInst(AllocaInst &I);
- SizeOffsetAPInt visitArgument(Argument &A);
- SizeOffsetAPInt visitCallBase(CallBase &CB);
- SizeOffsetAPInt visitConstantPointerNull(ConstantPointerNull &);
- SizeOffsetAPInt visitExtractElementInst(ExtractElementInst &I);
- SizeOffsetAPInt visitExtractValueInst(ExtractValueInst &I);
- SizeOffsetAPInt visitGlobalAlias(GlobalAlias &GA);
- SizeOffsetAPInt visitGlobalVariable(GlobalVariable &GV);
- SizeOffsetAPInt visitIntToPtrInst(IntToPtrInst &);
- SizeOffsetAPInt visitLoadInst(LoadInst &I);
- SizeOffsetAPInt visitPHINode(PHINode &);
- SizeOffsetAPInt visitSelectInst(SelectInst &I);
- SizeOffsetAPInt visitUndefValue(UndefValue &);
- SizeOffsetAPInt visitInstruction(Instruction &I);
+ OffsetSpan visitAllocaInst(AllocaInst &I);
+ OffsetSpan visitArgument(Argument &A);
+ OffsetSpan visitCallBase(CallBase &CB);
+ OffsetSpan visitConstantPointerNull(ConstantPointerNull &);
+ OffsetSpan visitExtractElementInst(ExtractElementInst &I);
+ OffsetSpan visitExtractValueInst(ExtractValueInst &I);
+ OffsetSpan visitGlobalAlias(GlobalAlias &GA);
+ OffsetSpan visitGlobalVariable(GlobalVariable &GV);
+ OffsetSpan visitIntToPtrInst(IntToPtrInst &);
+ OffsetSpan visitLoadInst(LoadInst &I);
+ OffsetSpan visitPHINode(PHINode &);
+ OffsetSpan visitSelectInst(SelectInst &I);
+ OffsetSpan visitUndefValue(UndefValue &);
+ OffsetSpan visitInstruction(Instruction &I);
private:
- SizeOffsetAPInt findLoadSizeOffset(
- LoadInst &LoadFrom, BasicBlock
[llvm-branch-commits] [lld] [PAC][lld] Use braa instr in PAC PLT sequence with valid PAuth core info (PR #113945)
https://github.com/DanielKristofKiss approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/113945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [llvm] Fix __builtin_object_size interaction between Negative Offset … (#111827) (PR #114786)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/114786 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [llvm] Fix __builtin_object_size interaction between Negative Offset … (#111827) (PR #114786)
llvmbot wrote: @hvdijk What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/114786 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld] Use braa instr in PAC PLT sequence with valid PAuth core info (PR #113945)
@@ -1066,9 +1079,13 @@ void AArch64BtiPac::writePlt(uint8_t *buf, const Symbol
&sym,
0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.got.plt[n]))]
0x10, 0x02, 0x00, 0x91 // add x16, x16, Offset(&(.got.plt[n]))
};
+ const uint8_t pacHintBr[] = {
+ 0x9f, 0x21, 0x03, 0xd5, // autia1716
+ 0x20, 0x02, 0x1f, 0xd6 // br x17
+ };
const uint8_t pacBr[] = {
- 0x9f, 0x21, 0x03, 0xd5, // autia1716
- 0x20, 0x02, 0x1f, 0xd6 // br x17
+ 0x30, 0x0a, 0x1f, 0xd7, // braa x17, x16
+ 0x1f, 0x20, 0x03, 0xd5 // nop
DanielKristofKiss wrote:
maybe UDF instruction is a safer choice instead of NOP. also may not have any
significance.
https://github.com/llvm/llvm-project/pull/113945
___
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[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
@@ -97,14 +104,32 @@ static bool isCallableFunction(const MachineFunction &MF) {
}
}
-bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+RegUsageInfoCollectorPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ Module &MFA = *MF.getFunction().getParent();
+ auto *PRUI = MFAM.getResult(MF)
+ .getCachedResult(MFA);
+ assert(PRUI && "PhysicalRegisterUsageAnalysis not available");
optimisan wrote:
The machine function's OuterAnalysisProxy can't run the module analysis (as we
are inside a module)
https://github.com/llvm/llvm-project/pull/113874
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[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+
+// Other libraries and framework includes
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_loongarch : public lldb_private::RegInfoBasedABI {
+public:
+ ~ABISysV_loongarch() override = default;
+
+ size_t GetRedZoneSize() const override { return 0; }
+
+ bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+ lldb::addr_t functionAddress,
+ lldb::addr_t returnAddress,
+ llvm::ArrayRef args) const override;
+
+ bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+ lldb_private::Status
+ SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+ lldb::ValueObjectSP &new_value) override;
+
+ lldb::ValueObjectSP
+ GetReturnValueObjectImpl(lldb_private::Thread &thread,
+ lldb_private::CompilerType &type) const override;
+
+ bool
+ CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan)
override;
+
+ bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+ bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+ bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned.
DavidSpickett wrote:
128 bit or 128 byte? This mask doesn't seem to fit either.
https://github.com/llvm/llvm-project/pull/114742
___
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[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
DavidSpickett wrote:
If the second parameter is always nullptr, make the macros emit it instead of
passing it in every time.
https://github.com/llvm/llvm-project/pull/114742
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[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+
+// Other libraries and framework includes
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_loongarch : public lldb_private::RegInfoBasedABI {
+public:
+ ~ABISysV_loongarch() override = default;
+
+ size_t GetRedZoneSize() const override { return 0; }
+
+ bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+ lldb::addr_t functionAddress,
+ lldb::addr_t returnAddress,
+ llvm::ArrayRef args) const override;
+
+ bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+ lldb_private::Status
+ SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+ lldb::ValueObjectSP &new_value) override;
+
+ lldb::ValueObjectSP
+ GetReturnValueObjectImpl(lldb_private::Thread &thread,
+ lldb_private::CompilerType &type) const override;
+
+ bool
+ CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan)
override;
+
+ bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+ bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+ bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned.
+return (cfa & 0xfull) == 0;
+ }
+
+ void SetIsLA64(bool is_la64) { m_is_la64 = is_la64; }
+
+ bool CodeAddressIsValid(lldb::addr_t pc) override {
+if (pc & (4ull - 1ull))
+ return false; // Not 4 byte aligned
+
+// Anything else if fair game..
DavidSpickett wrote:
The comment is redundant so remove it but it would be "is fair game" if you
keep it.
https://github.com/llvm/llvm-project/pull/114742
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[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
@@ -1,5 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \ optimisan wrote: I wanted to test by using the printer pass, is `-stop-after=prologepilog` correct instead? https://github.com/llvm/llvm-project/pull/113874 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Avoid generating nested CALLSEQ for TLS pointer function arguments (PR #106965)
ritter-x2a wrote: With #113706 now merged, this PR is obsolete. https://github.com/llvm/llvm-project/pull/106965 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From d9957fa8395cb0754fdf935fec55123284e15b30 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 8
llvm/include/llvm/Target/TargetOptions.h | 8 +++-
llvm/lib/CodeGen/MachineSink.cpp | 4 +++-
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +-
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+/// a computation can be folded into the addressing mode of a memory
+/// load/store instruction or replace a copy.
+unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..6849a3f12d8cfd 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include
#include
#include
@@ -729,7 +730,8 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
-setEnableSinkAndFold(EnableSinkFold);
+TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 72d74d2d79b1d5..00653ca348476e 100644
--- a/llvm/lib/Target/
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan ready_for_review https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/114746.diff
5 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetPassConfig.h (-8)
- (modified) llvm/include/llvm/Target/TargetOptions.h (+7-1)
- (modified) llvm/lib/CodeGen/MachineSink.cpp (+3-1)
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+1-1)
``diff
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h
b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..b395774b14c441 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -131,11 +131,6 @@ class TargetPassConfig : public ImmutablePass {
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge = true;
- /// Enable sinking of instructions in MachineSink where a computation can be
- /// folded into the addressing mode of a memory load/store instruction or
- /// replace a copy.
- bool EnableSinkAndFold = false;
-
/// Require processing of functions such that callees are generated before
/// callers.
bool RequireCodeGenSCCOrder = false;
@@ -198,9 +193,6 @@ class TargetPassConfig : public ImmutablePass {
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
- bool getEnableSinkAndFold() const { return EnableSinkAndFold; }
- void setEnableSinkAndFold(bool Enable) { setOpt(EnableSinkAndFold, Enable); }
-
bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
void setRequiresCodeGenSCCOrder(bool Enable = true) {
setOpt(RequireCodeGenSCCOrder, Enable);
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index 88f253805ca99c..b16ad5b69ff05a 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,7 +137,8 @@ namespace llvm {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableSinkAndFold(false), EnableFastISel(false),
+ EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -239,6 +240,11 @@ namespace llvm {
/// they were generated. Default is true.
unsigned StackSymbolOrdering : 1;
+/// EnableSinkAndFold - Enable sinking of instructions in MachineSink where
+/// a computation can be folded into the addressing mode of a memory
+/// load/store instruction or replace a copy.
+unsigned EnableSinkAndFold : 1;
+
/// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing
/// compile time.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..6849a3f12d8cfd 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -54,6 +54,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
#include
#include
#include
@@ -729,7 +730,8 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
TargetPassConfig *PassConfig = &getAnalysis();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+ auto &TM = PassConfig->getTM();
+ EnableSinkAndFold = TM.Options.EnableSinkAndFold;
bool EverMadeChange = false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c7bd0390b65620..ee8aae4ee8bcc8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -505,7 +505,7 @@ class AArch64PassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
-setEnableSinkAndFold(EnableSinkFold);
+TM.Options.EnableSinkAndFold = EnableSinkFold;
}
AArch64TargetMachine &getAArch64TargetMachine() const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 72d74d2d79b1d5..00653ca348476e 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -337,7 +337,7 @@ class RISCVPassC
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Add -fmultilib-flag command-line option (PR #110658)
https://github.com/vhscampos updated
https://github.com/llvm/llvm-project/pull/110658
>From 4f85ea57b021362f2a1bff12f720c8991093 Mon Sep 17 00:00:00 2001
From: Victor Campos
Date: Thu, 26 Sep 2024 14:44:01 +0100
Subject: [PATCH 1/2] [Multilib] Add -fmultilib-flag command-line option
This option is passed through to the multilib system. It is then used in
conjunction with other options to select the proper library variant.
Details about this change can be found in this thread:
https://discourse.llvm.org/t/rfc-multilib-custom-flags/81058
---
clang/include/clang/Driver/Options.td | 2 ++
clang/lib/Driver/ToolChain.cpp | 14 ++
clang/test/Driver/print-multi-selection-flags.c | 7 +++
3 files changed, 23 insertions(+)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 0cb7c0c0ae04f7..1fff1fa3edd052 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5684,6 +5684,8 @@ def print_multi_directory : Flag<["-", "--"],
"print-multi-directory">;
def print_multi_lib : Flag<["-", "--"], "print-multi-lib">;
def print_multi_flags : Flag<["-", "--"], "print-multi-flags-experimental">,
HelpText<"Print the flags used for selecting multilibs (experimental)">;
+def fmultilib_flag : Joined<["-", "--"], "fmultilib-flag=">,
+ Visibility<[ClangOption]>;
def print_multi_os_directory : Flag<["-", "--"], "print-multi-os-directory">,
Flags<[Unsupported]>;
def print_target_triple : Flag<["-", "--"], "print-target-triple">,
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 4df31770950858..19f5f59897eda2 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -196,6 +196,16 @@ bool ToolChain::defaultToIEEELongDouble() const {
return PPC_LINUX_DEFAULT_IEEELONGDOUBLE && getTriple().isOSLinux();
}
+static void
+processARMAArch64MultilibCustomFlags(Multilib::flags_list &List,
+ const llvm::opt::ArgList &Args) {
+ for (const Arg *MultilibFlagArg :
+ Args.filtered(options::OPT_fmultilib_flag)) {
+List.push_back(MultilibFlagArg->getAsString(Args));
+MultilibFlagArg->claim();
+ }
+}
+
static void getAArch64MultilibFlags(const Driver &D,
const llvm::Triple &Triple,
const llvm::opt::ArgList &Args,
@@ -232,6 +242,8 @@ static void getAArch64MultilibFlags(const Driver &D,
if (ABIArg) {
Result.push_back(ABIArg->getAsString(Args));
}
+
+ processARMAArch64MultilibCustomFlags(Result, Args);
}
static void getARMMultilibFlags(const Driver &D,
@@ -285,6 +297,8 @@ static void getARMMultilibFlags(const Driver &D,
if (BranchProtectionArg) {
Result.push_back(BranchProtectionArg->getAsString(Args));
}
+
+ processARMAArch64MultilibCustomFlags(Result, Args);
}
static void getRISCVMultilibFlags(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/test/Driver/print-multi-selection-flags.c
b/clang/test/Driver/print-multi-selection-flags.c
index 4bb62665ad8981..6bf50cd0976a6b 100644
--- a/clang/test/Driver/print-multi-selection-flags.c
+++ b/clang/test/Driver/print-multi-selection-flags.c
@@ -82,3 +82,10 @@
// CHECK-RV32E-ORDER: --target=riscv32-unknown-none-elf
// CHECK-RV32E-ORDER: -mabi=ilp32e
// CHECK-RV32E-ORDER:
-march=rv32e{{[0-9]+p[0-9]+}}_c{{[0-9]+p[0-9]+}}_zicsr{{[0-9]+p[0-9]+}}
+
+// RUN: %clang -print-multi-flags-experimental --target=armv8m.main-none-eabi
-fmultilib-flag=foo -fmultilib-flag=bar | FileCheck
--check-prefixes=CHECK-MULTILIB-CUSTOM-FLAG,CHECK-ARM-MULTILIB-CUSTOM-FLAG %s
+// RUN: %clang -print-multi-flags-experimental --target=aarch64-none-eabi
-fmultilib-flag=foo -fmultilib-flag=bar | FileCheck
--check-prefixes=CHECK-MULTILIB-CUSTOM-FLAG,CHECK-AARCH64-MULTILIB-CUSTOM-FLAG
%s
+// CHECK-ARM-MULTILIB-CUSTOM-FLAG: --target=thumbv8m.main-unknown-none-eabi
+// CHECK-AARCH64-MULTILIB-CUSTOM-FLAG: --target=aarch64-unknown-none-eabi
+// CHECK-MULTILIB-CUSTOM-FLAG-DAG: -fmultilib-flag=foo
+// CHECK-MULTILIB-CUSTOM-FLAG-DAG: -fmultilib-flag=bar
>From ee2d268d6ab0f231da471875194744b2fb5d32be Mon Sep 17 00:00:00 2001
From: Victor Campos
Date: Mon, 4 Nov 2024 13:45:58 +
Subject: [PATCH 2/2] Renamed function
---
clang/lib/Driver/ToolChain.cpp | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 19f5f59897eda2..b9ddb65d2ef886 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -196,9 +196,8 @@ bool ToolChain::defaultToIEEELongDouble() const {
return PPC_LINUX_DEFAULT_IEEELONGDOUBLE && getTriple().isOSLinux();
}
-static void
-processARMAArch64MultilibCustomFlags(Multilib::flags_list &List,
- const llvm::opt::ArgList &Args) {
+static void processMultilibCusto
[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
arsenm wrote: Was this reopened as a new PR? https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
sdesmalen-arm wrote: Trying to reopen.. https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
sdesmalen-arm wrote: I think I need to create a new PR for this as Github doesn't allow me to reopen and choose a different branch to merge into. https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
sdesmalen-arm wrote: It wasn't, but I also didn't realise that I closed it. Could Github have done this automatically after the branch it was based of was deleted? (I was about to push the rebased branch of this PR after merging #114391 and #114392) https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Add -fmultilib-flag command-line option (PR #110658)
https://github.com/statham-arm approved this pull request. https://github.com/llvm/llvm-project/pull/110658 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
@@ -95,9 +96,113 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) {
void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); }
+static void WarnUnclaimedMultilibCustomFlags(
+const Driver &D, const SmallVector &UnclaimedCustomFlagValues,
+const SmallVector &CustomFlagDecls)
{
+ struct EditDistanceInfo {
+StringRef FlagValue;
+unsigned EditDistance;
+ };
+ const unsigned MaxEditDistance = 5;
+
+ for (StringRef Unclaimed : UnclaimedCustomFlagValues) {
+std::optional BestCandidate;
+for (const auto &Decl : CustomFlagDecls) {
+ for (const auto &Value : Decl->ValueList) {
+const std::string &FlagValueName = Value.Name;
+unsigned EditDistance =
+Unclaimed.edit_distance(FlagValueName, /*AllowReplacements=*/true,
+/*MaxEditDistance=*/MaxEditDistance);
+if (!BestCandidate || (EditDistance <= MaxEditDistance &&
+ EditDistance < BestCandidate->EditDistance)) {
+ BestCandidate = {FlagValueName, EditDistance};
+}
+ }
+}
+if (!BestCandidate)
+ D.Diag(clang::diag::warn_drv_unsupported_opt)
+ << (custom_flag::Prefix + Unclaimed).str();
+else
+ D.Diag(clang::diag::warn_drv_unsupported_opt_with_suggestion)
+ << (custom_flag::Prefix + Unclaimed).str()
+ << (custom_flag::Prefix + BestCandidate->FlagValue).str();
+ }
+}
+
+namespace clang::driver::custom_flag {
+class ValueNameToDetailMap {
+ SmallVector> Mapping;
+
+public:
+ template
+ ValueNameToDetailMap(It FlagDeclsBegin, It FlagDeclsEnd) {
+for (auto DeclIt = FlagDeclsBegin; DeclIt != FlagDeclsEnd; ++DeclIt) {
+ const CustomFlagDeclarationPtr &Decl = *DeclIt;
+ for (const auto &Value : Decl->ValueList)
+Mapping.emplace_back(Value.Name, &Value);
+}
+ }
+
+ const CustomFlagValueDetail *get(StringRef Key) const {
+auto Iter = llvm::find_if(
+Mapping, [&](const auto &Pair) { return Pair.first == Key; });
+return Iter != Mapping.end() ? Iter->second : nullptr;
+ }
+};
+} // namespace clang::driver::custom_flag
+
+Multilib::flags_list
+MultilibSet::processCustomFlags(const Driver &D,
+const Multilib::flags_list &Flags) const {
+ Multilib::flags_list Result;
+ SmallVector
+ ClaimedCustomFlagValues;
+ SmallVector UnclaimedCustomFlagValueStrs;
+
+ const auto ValueNameToValueDetail = custom_flag::ValueNameToDetailMap(
+ CustomFlagDecls.begin(), CustomFlagDecls.end());
+
+ for (StringRef Flag : Flags) {
+if (!Flag.starts_with(custom_flag::Prefix)) {
+ Result.push_back(Flag.str());
+ continue;
+}
+
+StringRef CustomFlagValueStr = Flag.substr(custom_flag::Prefix.size());
+const custom_flag::CustomFlagValueDetail *Detail =
+ValueNameToValueDetail.get(CustomFlagValueStr);
+if (Detail)
+ ClaimedCustomFlagValues.push_back(Detail);
+else
+ UnclaimedCustomFlagValueStrs.push_back(CustomFlagValueStr);
+ }
+
+ llvm::SmallSet
+ TriggeredCustomFlagDecls;
+
+ for (auto *CustomFlagValue : llvm::reverse(ClaimedCustomFlagValues)) {
+if (!TriggeredCustomFlagDecls.insert(CustomFlagValue->Decl).second)
+ continue;
+Result.push_back(std::string(custom_flag::Prefix) + CustomFlagValue->Name);
+ }
statham-arm wrote:
Thanks. Yes, that's better: the de-duplication wasn't at all obvious, and now
it is. (And I much prefer the explanation in comments in the code than here
where nobody will ever look for it :-)
https://github.com/llvm/llvm-project/pull/110659
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[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
https://github.com/statham-arm approved this pull request. https://github.com/llvm/llvm-project/pull/110659 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
