[llvm-branch-commits] [compiler-rt] 19f3976 - Revert "[scudo] Apply the min release threshold to the group (#112014)"
Author: ChiaHungDuan
Date: 2024-10-14T12:52:25-07:00
New Revision: 19f39761410daf3edde455aa164221ca04ad40ad
URL:
https://github.com/llvm/llvm-project/commit/19f39761410daf3edde455aa164221ca04ad40ad
DIFF:
https://github.com/llvm/llvm-project/commit/19f39761410daf3edde455aa164221ca04ad40ad.diff
LOG: Revert "[scudo] Apply the min release threshold to the group (#112014)"
This reverts commit 53c9553562c778338a82574123fb7cfb943c4042.
Added:
Modified:
compiler-rt/lib/scudo/standalone/primary64.h
Removed:
diff --git a/compiler-rt/lib/scudo/standalone/primary64.h
b/compiler-rt/lib/scudo/standalone/primary64.h
index 1865ed41368e3c..97188a5ac235cc 100644
--- a/compiler-rt/lib/scudo/standalone/primary64.h
+++ b/compiler-rt/lib/scudo/standalone/primary64.h
@@ -1492,8 +1492,6 @@ template class SizeClassAllocator64 {
}
const uptr PushedBytesDelta = BytesInBG - BG->BytesInBGAtLastCheckpoint;
- if (PushedBytesDelta < getMinReleaseAttemptSize(BlockSize))
-continue;
// Given the randomness property, we try to release the pages only if the
// bytes used by free blocks exceed certain proportion of group size.
Note
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[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/112258 Backport 9bf68c2400e8966511332dfbf5c0f05e8a3300fa Requested by: @efriedma-quic >From 006c85c64ac4b381020b4b566da33ec31f363561 Mon Sep 17 00:00:00 2001 From: Max Winkler Date: Mon, 14 Oct 2024 12:22:25 -0700 Subject: [PATCH] [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) Fixes https://github.com/llvm/llvm-project/pull/87717. (cherry picked from commit 9bf68c2400e8966511332dfbf5c0f05e8a3300fa) --- clang/lib/Headers/intrin0.h | 2 +- clang/test/Headers/ms-intrin.cpp | 12 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/clang/lib/Headers/intrin0.h b/clang/lib/Headers/intrin0.h index 866c8896617d22..6b01f3808652aa 100644 --- a/clang/lib/Headers/intrin0.h +++ b/clang/lib/Headers/intrin0.h @@ -44,7 +44,7 @@ unsigned char _InterlockedCompareExchange128_rel(__int64 volatile *_Destination, __int64 *_ComparandResult); #endif -#ifdef __x86_64__ && !defined(__arm64ec__) +#if defined(__x86_64__) && !defined(__arm64ec__) unsigned __int64 _umul128(unsigned __int64, unsigned __int64, unsigned __int64 *); unsigned __int64 __shiftleft128(unsigned __int64 _LowPart, diff --git a/clang/test/Headers/ms-intrin.cpp b/clang/test/Headers/ms-intrin.cpp index cb7cd47956205c..d630883e79d6a5 100644 --- a/clang/test/Headers/ms-intrin.cpp +++ b/clang/test/Headers/ms-intrin.cpp @@ -1,31 +1,31 @@ // RUN: %clang_cc1 -triple i386-pc-win32 -target-cpu pentium4 \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple i386-pc-win32 -target-cpu broadwell \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -emit-obj -o /dev/null -Werror \ +// RUN: -ffreestanding -emit-obj -o /dev/null -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple x86_64-pc-win32 \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -emit-obj -o /dev/null -Werror \ +// RUN: -ffreestanding -emit-obj -o /dev/null -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple thumbv7--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple aarch64--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple arm64ec--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // REQUIRES: x86-registered-target ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
llvmbot wrote: @llvm/pr-subscribers-clang Author: None (llvmbot) Changes Backport 9bf68c2400e8966511332dfbf5c0f05e8a3300fa Requested by: @efriedma-quic --- Full diff: https://github.com/llvm/llvm-project/pull/112258.diff 2 Files Affected: - (modified) clang/lib/Headers/intrin0.h (+1-1) - (modified) clang/test/Headers/ms-intrin.cpp (+6-6) ``diff diff --git a/clang/lib/Headers/intrin0.h b/clang/lib/Headers/intrin0.h index 866c8896617d22..6b01f3808652aa 100644 --- a/clang/lib/Headers/intrin0.h +++ b/clang/lib/Headers/intrin0.h @@ -44,7 +44,7 @@ unsigned char _InterlockedCompareExchange128_rel(__int64 volatile *_Destination, __int64 *_ComparandResult); #endif -#ifdef __x86_64__ && !defined(__arm64ec__) +#if defined(__x86_64__) && !defined(__arm64ec__) unsigned __int64 _umul128(unsigned __int64, unsigned __int64, unsigned __int64 *); unsigned __int64 __shiftleft128(unsigned __int64 _LowPart, diff --git a/clang/test/Headers/ms-intrin.cpp b/clang/test/Headers/ms-intrin.cpp index cb7cd47956205c..d630883e79d6a5 100644 --- a/clang/test/Headers/ms-intrin.cpp +++ b/clang/test/Headers/ms-intrin.cpp @@ -1,31 +1,31 @@ // RUN: %clang_cc1 -triple i386-pc-win32 -target-cpu pentium4 \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple i386-pc-win32 -target-cpu broadwell \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -emit-obj -o /dev/null -Werror \ +// RUN: -ffreestanding -emit-obj -o /dev/null -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple x86_64-pc-win32 \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -emit-obj -o /dev/null -Werror \ +// RUN: -ffreestanding -emit-obj -o /dev/null -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple thumbv7--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple aarch64--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple arm64ec--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // REQUIRES: x86-registered-target `` https://github.com/llvm/llvm-project/pull/112258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
llvmbot wrote: @llvm/pr-subscribers-backend-x86 Author: None (llvmbot) Changes Backport 9bf68c2400e8966511332dfbf5c0f05e8a3300fa Requested by: @efriedma-quic --- Full diff: https://github.com/llvm/llvm-project/pull/112258.diff 2 Files Affected: - (modified) clang/lib/Headers/intrin0.h (+1-1) - (modified) clang/test/Headers/ms-intrin.cpp (+6-6) ``diff diff --git a/clang/lib/Headers/intrin0.h b/clang/lib/Headers/intrin0.h index 866c8896617d22..6b01f3808652aa 100644 --- a/clang/lib/Headers/intrin0.h +++ b/clang/lib/Headers/intrin0.h @@ -44,7 +44,7 @@ unsigned char _InterlockedCompareExchange128_rel(__int64 volatile *_Destination, __int64 *_ComparandResult); #endif -#ifdef __x86_64__ && !defined(__arm64ec__) +#if defined(__x86_64__) && !defined(__arm64ec__) unsigned __int64 _umul128(unsigned __int64, unsigned __int64, unsigned __int64 *); unsigned __int64 __shiftleft128(unsigned __int64 _LowPart, diff --git a/clang/test/Headers/ms-intrin.cpp b/clang/test/Headers/ms-intrin.cpp index cb7cd47956205c..d630883e79d6a5 100644 --- a/clang/test/Headers/ms-intrin.cpp +++ b/clang/test/Headers/ms-intrin.cpp @@ -1,31 +1,31 @@ // RUN: %clang_cc1 -triple i386-pc-win32 -target-cpu pentium4 \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple i386-pc-win32 -target-cpu broadwell \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -emit-obj -o /dev/null -Werror \ +// RUN: -ffreestanding -emit-obj -o /dev/null -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple x86_64-pc-win32 \ // RUN: -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -emit-obj -o /dev/null -Werror \ +// RUN: -ffreestanding -emit-obj -o /dev/null -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple thumbv7--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple aarch64--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // RUN: %clang_cc1 -triple arm64ec--windows \ // RUN: -fms-compatibility -fms-compatibility-version=17.00 \ -// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -ffreestanding -fsyntax-only -Werror -Wsystem-headers \ // RUN: -isystem %S/Inputs/include %s // REQUIRES: x86-registered-target `` https://github.com/llvm/llvm-project/pull/112258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/112258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
llvmbot wrote: @efriedma-quic What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/112258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Instantiate Typedefs referenced by type alias deduction guides (#111804) (PR #112293)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport 0bc02b999a
Requested by: @zyn0217
---
Full diff: https://github.com/llvm/llvm-project/pull/112293.diff
2 Files Affected:
- (modified) clang/lib/Sema/SemaTemplateDeductionGuide.cpp (+18-3)
- (modified) clang/test/SemaCXX/cxx20-ctad-type-alias.cpp (+13)
``diff
diff --git a/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
b/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
index 0602d07c6b9b0d..1bf82b31def977 100644
--- a/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
+++ b/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
@@ -69,8 +69,8 @@ class ExtractTypeForDeductionGuide
ExtractTypeForDeductionGuide(
Sema &SemaRef,
llvm::SmallVectorImpl &MaterializedTypedefs,
- ClassTemplateDecl *NestedPattern,
- const MultiLevelTemplateArgumentList *OuterInstantiationArgs)
+ ClassTemplateDecl *NestedPattern = nullptr,
+ const MultiLevelTemplateArgumentList *OuterInstantiationArgs = nullptr)
: Base(SemaRef), MaterializedTypedefs(MaterializedTypedefs),
NestedPattern(NestedPattern),
OuterInstantiationArgs(OuterInstantiationArgs) {
@@ -1263,10 +1263,25 @@ FunctionTemplateDecl
*DeclareAggregateDeductionGuideForTypeAlias(
getRHSTemplateDeclAndArgs(SemaRef, AliasTemplate).first;
if (!RHSTemplate)
return nullptr;
+
+ llvm::SmallVector TypedefDecls;
+ llvm::SmallVector NewParamTypes;
+ ExtractTypeForDeductionGuide TypeAliasTransformer(SemaRef, TypedefDecls);
+ for (QualType P : ParamTypes) {
+QualType Type = TypeAliasTransformer.TransformType(P);
+if (Type.isNull())
+ return nullptr;
+NewParamTypes.push_back(Type);
+ }
+
auto *RHSDeductionGuide = SemaRef.DeclareAggregateDeductionGuideFromInitList(
- RHSTemplate, ParamTypes, Loc);
+ RHSTemplate, NewParamTypes, Loc);
if (!RHSDeductionGuide)
return nullptr;
+
+ for (TypedefNameDecl *TD : TypedefDecls)
+TD->setDeclContext(RHSDeductionGuide->getTemplatedDecl());
+
return BuildDeductionGuideForTypeAlias(SemaRef, AliasTemplate,
RHSDeductionGuide, Loc);
}
diff --git a/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
b/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
index 5392573fcdb9d5..675c32a81f1ae8 100644
--- a/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
+++ b/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
@@ -481,3 +481,16 @@ struct Out {
Out::B out(100); // deduced to Out::A;
static_assert(__is_same(decltype(out), Out::A));
}
+
+namespace GH111508 {
+
+template struct S {
+ using T = V;
+ T Data;
+};
+
+template using Alias = S;
+
+Alias A(42);
+
+} // namespace GH111508
``
https://github.com/llvm/llvm-project/pull/112293
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[llvm-branch-commits] [clang] f173e12 - Revert "[Coverage][WebAssembly] Add initial support for WebAssembly/WASI (#11…"
Author: dpalermo
Date: 2024-10-14T16:41:25-05:00
New Revision: f173e127c135f88ea37aef26010583078063c202
URL:
https://github.com/llvm/llvm-project/commit/f173e127c135f88ea37aef26010583078063c202
DIFF:
https://github.com/llvm/llvm-project/commit/f173e127c135f88ea37aef26010583078063c202.diff
LOG: Revert "[Coverage][WebAssembly] Add initial support for WebAssembly/WASI
(#11…"
This reverts commit d4efc3e097f40afbe8ae275150f49bb08fc04572.
Added:
Modified:
clang/lib/Driver/ToolChains/WebAssembly.cpp
compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
compiler-rt/cmake/config-ix.cmake
compiler-rt/lib/profile/CMakeLists.txt
compiler-rt/lib/profile/GCDAProfiling.c
compiler-rt/lib/profile/InstrProfilingPlatformLinux.c
compiler-rt/lib/profile/InstrProfilingPlatformOther.c
compiler-rt/lib/profile/InstrProfilingPort.h
compiler-rt/lib/profile/InstrProfilingUtil.c
lld/wasm/InputChunks.h
lld/wasm/InputFiles.cpp
lld/wasm/OutputSections.cpp
llvm/include/llvm/ProfileData/Coverage/CoverageMappingReader.h
llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
llvm/lib/MC/MCContext.cpp
llvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
llvm/test/Instrumentation/InstrProfiling/profiling.ll
llvm/test/tools/llvm-cov/binary-formats.c
Removed:
lld/test/wasm/custom-section-align.s
llvm/test/CodeGen/WebAssembly/profile.ll
llvm/test/tools/llvm-cov/Inputs/binary-formats.v6.wasm32
llvm/test/tools/llvm-cov/Inputs/binary-formats.wasm.proftext
diff --git a/clang/lib/Driver/ToolChains/WebAssembly.cpp
b/clang/lib/Driver/ToolChains/WebAssembly.cpp
index 44a6894d30fb29..9aec11e69fde1d 100644
--- a/clang/lib/Driver/ToolChains/WebAssembly.cpp
+++ b/clang/lib/Driver/ToolChains/WebAssembly.cpp
@@ -163,8 +163,6 @@ void wasm::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
AddRunTimeLibs(ToolChain, ToolChain.getDriver(), CmdArgs, Args);
}
- ToolChain.addProfileRTLibs(Args, CmdArgs);
-
CmdArgs.push_back("-o");
CmdArgs.push_back(Output.getFilename());
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index d00d39518104bf..809e9277156912 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -77,7 +77,7 @@ set(ALL_HWASAN_SUPPORTED_ARCH ${X86_64} ${ARM64} ${RISCV64})
set(ALL_MEMPROF_SUPPORTED_ARCH ${X86_64})
set(ALL_PROFILE_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${PPC32}
${PPC64}
${MIPS32} ${MIPS64} ${S390X} ${SPARC} ${SPARCV9} ${HEXAGON}
-${RISCV32} ${RISCV64} ${LOONGARCH64} ${WASM32})
+${RISCV32} ${RISCV64} ${LOONGARCH64})
set(ALL_CTX_PROFILE_SUPPORTED_ARCH ${X86_64})
if (OS_NAME MATCHES "FreeBSD")
set(ALL_TSAN_SUPPORTED_ARCH ${X86_64} ${MIPS64} ${ARM64})
diff --git a/compiler-rt/cmake/config-ix.cmake
b/compiler-rt/cmake/config-ix.cmake
index a494e0532a50bc..a93a88a9205001 100644
--- a/compiler-rt/cmake/config-ix.cmake
+++ b/compiler-rt/cmake/config-ix.cmake
@@ -822,7 +822,7 @@ else()
endif()
if (PROFILE_SUPPORTED_ARCH AND NOT LLVM_USE_SANITIZER AND
-OS_NAME MATCHES
"Darwin|Linux|FreeBSD|Windows|Android|Fuchsia|SunOS|NetBSD|AIX|WASI")
+OS_NAME MATCHES
"Darwin|Linux|FreeBSD|Windows|Android|Fuchsia|SunOS|NetBSD|AIX")
set(COMPILER_RT_HAS_PROFILE TRUE)
else()
set(COMPILER_RT_HAS_PROFILE FALSE)
diff --git a/compiler-rt/lib/profile/CMakeLists.txt
b/compiler-rt/lib/profile/CMakeLists.txt
index ac1451c8ceed18..26178412967201 100644
--- a/compiler-rt/lib/profile/CMakeLists.txt
+++ b/compiler-rt/lib/profile/CMakeLists.txt
@@ -38,17 +38,6 @@ int main() {
" COMPILER_RT_TARGET_HAS_FCNTL_LCK)
-CHECK_CXX_SOURCE_COMPILES("
-#include
-
-int fd;
-int main() {
- flock(fd, LOCK_EX);
- return 0;
-}
-
-" COMPILER_RT_TARGET_HAS_FLOCK)
-
CHECK_CXX_SOURCE_COMPILES("
#include
int main() {
@@ -104,13 +93,6 @@ if(FUCHSIA OR UNIX)
-Wno-pedantic)
endif()
-if(CMAKE_SYSTEM_NAME STREQUAL "WASI")
- set(EXTRA_FLAGS
- ${EXTRA_FLAGS}
- -D_WASI_EMULATED_MMAN
- -D_WASI_EMULATED_GETPID)
-endif()
-
if(COMPILER_RT_TARGET_HAS_ATOMICS)
set(EXTRA_FLAGS
${EXTRA_FLAGS}
@@ -123,12 +105,6 @@ if(COMPILER_RT_TARGET_HAS_FCNTL_LCK)
-DCOMPILER_RT_HAS_FCNTL_LCK=1)
endif()
-if(COMPILER_RT_TARGET_HAS_FLOCK)
- set(EXTRA_FLAGS
- ${EXTRA_FLAGS}
- -DCOMPILER_RT_HAS_FLOCK=1)
-endif()
-
if(COMPILER_RT_TARGET_HAS_UNAME)
set(EXTRA_FLAGS
${EXTRA_FLAGS}
diff --git a/compiler-rt/lib/profile/GCDAProfiling.c
b/compiler-rt/lib/profile/GCDAProfiling.c
index f67d95d21a7b54..d6e2175169e4a5 100644
--- a/compiler-rt/lib/profile/GCDAProfiling.c
+++ b/compiler-rt/lib/profile/GCDAProfiling.c
@@ -584,7 +584,7 @@ void llvm_reset_counters(void) {
}
}
-#if !defined(_WIN32) &
[llvm-branch-commits] [compiler-rt] release/19.x: Undef _TIME_BITS along with _FILE_OFFSET_BITS (PR #112247)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/112247
Backport a1217020da219386b29c1a5a4a217904ecf07d7d
Requested by: @mgorny
>From af96ae251ab750b75ce4f2c91f909827a89bd8f7 Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni
Date: Fri, 19 Jul 2024 22:22:55 +0200
Subject: [PATCH] Undef _TIME_BITS along with _FILE_OFFSET_BITS
This change is identical to
26800a2c7e7996dc773b4e990dd5cca41c45e1a9 ("[sanitizer] Undef
_TIME_BITS along with _FILE_OFFSET_BITS on Linux"), but for
sanitizer_procmaps_solaris.cpp.
Indeed, even though sanitizer_procmaps_solaris.cpp is Solaris
specific, it also gets built on Linux platforms. It also includes
sanitizer_platform.h, which also ends up including features-time64.h,
causing a build failure on 32-bit Linux platforms on which 64-bit
time_t is enabled by setting _TIME_BITS=64.
To fix this, we do the same change: undefine _TIME_BITS, which anyway
will cause no harm as the rest of this file is inside a
SANITIZER_SOLARIS compile-time conditional.
Fixes:
In file included from
/home/thomas/buildroot/buildroot/output/host/i686-buildroot-linux-gnu/sysroot/usr/include/features.h:394,
from
../../../../libsanitizer/sanitizer_common/sanitizer_platform.h:25,
from
../../../../libsanitizer/sanitizer_common/sanitizer_procmaps_solaris.cpp:14:
/home/thomas/buildroot/buildroot/output/host/i686-buildroot-linux-gnu/sysroot/usr/include/features-time64.h:26:5:
error: #error "_TIME_BITS=64 is al
lowed only with _FILE_OFFSET_BITS=64"
26 | # error "_TIME_BITS=64 is allowed only with _FILE_OFFSET_BITS=64"
| ^
Signed-off-by: Thomas Petazzoni
Closes: https://github.com/llvm/llvm-project/pull/99699
(cherry picked from commit a1217020da219386b29c1a5a4a217904ecf07d7d)
---
.../lib/sanitizer_common/sanitizer_procmaps_solaris.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp
index eeb49e2afe34d4..80b8158f43db9e 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp
@@ -11,6 +11,10 @@
// Before Solaris 11.4, doesn't work in a largefile environment.
#undef _FILE_OFFSET_BITS
+
+// Avoid conflict between `_TIME_BITS` defined vs. `_FILE_OFFSET_BITS`
+// undefined in some Linux configurations.
+#undef _TIME_BITS
#include "sanitizer_platform.h"
#if SANITIZER_SOLARIS
# include
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[llvm-branch-commits] [compiler-rt] release/19.x: Undef _TIME_BITS along with _FILE_OFFSET_BITS (PR #112247)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/112247 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/19.x: Undef _TIME_BITS along with _FILE_OFFSET_BITS (PR #112247)
llvmbot wrote: @llvm/pr-subscribers-compiler-rt-sanitizer Author: None (llvmbot) Changes Backport a1217020da219386b29c1a5a4a217904ecf07d7d Requested by: @mgorny --- Full diff: https://github.com/llvm/llvm-project/pull/112247.diff 1 Files Affected: - (modified) compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp (+4) ``diff diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp index eeb49e2afe34d4..80b8158f43db9e 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp @@ -11,6 +11,10 @@ // Before Solaris 11.4, doesn't work in a largefile environment. #undef _FILE_OFFSET_BITS + +// Avoid conflict between `_TIME_BITS` defined vs. `_FILE_OFFSET_BITS` +// undefined in some Linux configurations. +#undef _TIME_BITS #include "sanitizer_platform.h" #if SANITIZER_SOLARIS # include `` https://github.com/llvm/llvm-project/pull/112247 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [clang-format] Handle template closer followed by braces (#110971) (PR #111958)
https://github.com/mydeveloperday approved this pull request. https://github.com/llvm/llvm-project/pull/111958 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] 1360969 - [libc++] Adjust the version of __cpp_lib_ranges in C++20 mode
Author: Louis Dionne Date: 2024-10-11T15:30:47+08:00 New Revision: 1360969b8125a633a3a8ad734c8a369bd3cf47c2 URL: https://github.com/llvm/llvm-project/commit/1360969b8125a633a3a8ad734c8a369bd3cf47c2 DIFF: https://github.com/llvm/llvm-project/commit/1360969b8125a633a3a8ad734c8a369bd3cf47c2.diff LOG: [libc++] Adjust the version of __cpp_lib_ranges in C++20 mode This is a (very partial) cherry-pick of #101715 to fix this oversight in the LLVM 19 release. Added: Modified: libcxx/docs/FeatureTestMacroTable.rst libcxx/include/version libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp libcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.compile.pass.cpp libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp libcxx/test/std/language.support/support.limits/support.limits.general/ranges.version.compile.pass.cpp libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp libcxx/utils/generate_feature_test_macro_components.py Removed: diff --git a/libcxx/docs/FeatureTestMacroTable.rst b/libcxx/docs/FeatureTestMacroTable.rst index 7f95f0f4e1c17c..cbed6693f0a5d7 100644 --- a/libcxx/docs/FeatureTestMacroTable.rst +++ b/libcxx/docs/FeatureTestMacroTable.rst @@ -266,7 +266,7 @@ Status -- - ``__cpp_lib_polymorphic_allocator````201902L`` -- - -``__cpp_lib_ranges`` ``202207L`` +``__cpp_lib_ranges`` ``202110L`` -- - ``__cpp_lib_remove_cvref`` ``201711L`` -- - diff --git a/libcxx/include/version b/libcxx/include/version index c8a31f77a915e1..76ab6bedafdd0b 100644 --- a/libcxx/include/version +++ b/libcxx/include/version @@ -184,7 +184,7 @@ __cpp_lib_print 202207L __cpp_lib_ranges202211L -202207L // C++20 +202110L // C++20 __cpp_lib_ranges_as_const 202207L __cpp_lib_ranges_as_rvalue 202207L __cpp_lib_ranges_chunk 202202L @@ -429,7 +429,7 @@ __cpp_lib_void_t 201411L # if _LIBCPP_AVAILABILITY_HAS_PMR # define __cpp_lib_polymorphic_allocator 201902L # endif -# define __cpp_lib_ranges 202207L +# define __cpp_lib_ranges 202110L # define __cpp_lib_remove_cvref 201711L # if !defined(_LIBCPP_HAS_NO_THREADS) && _LIBCPP_AVAILABILITY_HAS_SYNC # define __cpp_lib_semaphore 201907L diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp index 6b756535569f6f..65da07ef029253 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp @@ -21,7 +21,7 @@ __cpp_lib_default_template_type_for_algorithm_values202403L [C++26] __cpp_lib_freestanding_algorithm202311L [C++26] __cpp_lib_parallel_algorithm201603L [C++17] -__cpp_lib_ranges202207L [C++20] +__cpp_lib_ranges202110L [C++20] 202211L [C++23] __cpp_lib_ranges_contains 202207L [C++23] __cpp_lib_ranges_find_last 202207L [C++23] @@ -245,8 +245,8 @@ # ifndef __cpp_lib_ranges # error "__cpp_lib_ranges should be defined in c++20" # endif -# if __cpp_lib_ranges != 202207L -# error "__cpp_lib_ranges should have the value 202207L in c++20" +# if __cpp_lib_ranges != 202110L +# error "__cpp_lib_ranges should have the value 202110L in c++20" # endif # ifdef __
[llvm-branch-commits] [libcxx] [release/19.x][libc++] Adjust the version of __cpp_lib_ranges in C++20 mode (PR #109324)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/109324 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [libcxxabi] release/19.x: [libc++] Avoid re-exporting a few specific symbols from libc++abi (#109054) (PR #110677)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/110677
>From c36d7fd568a5da5b9ea5b0e6f60b1210ecc512d0 Mon Sep 17 00:00:00 2001
From: Louis Dionne
Date: Tue, 1 Oct 2024 09:39:44 -0400
Subject: [PATCH] [libc++] Avoid re-exporting a few specific symbols from
libc++abi (#109054)
In 6a884a9aef39, I synchronized the export list of libc++abi to the
export list of libc++. From the linker's perspective, this caused these
symbols to be taken from libc++.dylib instead of libc++abi.dylib.
However, that can be problematic when back-deploying. Indeed, this means
that the linker will encode an undefined reference to be fullfilled by
libc++.dylib, but when backdeploying against an older system, that
symbol might only be available in libc++abi.dylib.
Most of the symbols that started being re-exported after 6a884a9aef39
turn out to be implementation details of libc++abi, so nobody really
depends on them and this back-deployment issue is inconsequential.
However, we ran into issues with a few of these symbols while testing
LLVM 19, which led to this patch. This slipped between the cracks and
that is why the patch is coming so long after the original patch landed.
In the future, a follow-up cleanup would be to stop exporting most of
the _cxxabiv1_foo_type_infoE symbols from both libc++abi and libc++
since they are implementation details that nobody should be relying on.
rdar://131984512
(cherry picked from commit 677e8cd6ff51e178bcb4669104763f71a2de106c)
---
libcxx/lib/abi/CHANGELOG.TXT | 30 +++
...bcxxabi.v1.stable.exceptions.nonew.abilist | 7 -
...bcxxabi.v1.stable.exceptions.nonew.abilist | 7 -
libcxxabi/lib/cxxabiv1.exp| 3 --
libcxxabi/lib/itanium-base.exp| 1 -
libcxxabi/lib/symbols-not-reexported.exp | 13
libcxxabi/src/CMakeLists.txt | 10 ++-
7 files changed, 52 insertions(+), 19 deletions(-)
create mode 100644 libcxxabi/lib/symbols-not-reexported.exp
diff --git a/libcxx/lib/abi/CHANGELOG.TXT b/libcxx/lib/abi/CHANGELOG.TXT
index 32526f1786c6d9..68c9d980a016ea 100644
--- a/libcxx/lib/abi/CHANGELOG.TXT
+++ b/libcxx/lib/abi/CHANGELOG.TXT
@@ -16,6 +16,36 @@ New entries should be added directly below the "Version"
header.
Version 19.0
+* [libc++] Avoid re-exporting a few specific symbols from libc++abi
+
+ In 6a884a9aef39, I synchronized the export list of libc++abi to the
+ export list of libc++. From the linker's perspective, this caused
+ these symbols to be taken from libc++.dylib instead of libc++abi.dylib.
+
+ However, that can be problematic when back-deploying. Indeed, this means
+ that the linker will encode an undefined reference to be fullfilled by
+ libc++.dylib, but when backdeploying against an older system, that symbol
+ might only be available in libc++abi.dylib.
+
+ Most of the symbols that started being re-exported after 6a884a9aef39
+ turn out to be implementation details of libc++abi, so nobody really
+ depends on them and this back-deployment issue is inconsequential.
+
+ However, we ran into issues with a few of these symbols while testing
+ LLVM 19, which led to this patch.
+
+ In the future, a follow-up cleanup would be to stop exporting most of
+ the _cxxabiv1_foo_type_infoE symbols from both libc++abi and libc++
+ since they are implementation details that nobody should be relying
+ on.
+
+ -apple-darwin
+ ---
+ Symbol not reexported anymore: ___cxa_rethrow_primary_exception
+ Symbol not reexported anymore: __ZTIN10__cxxabiv117__class_type_infoE
+ Symbol not reexported anymore: __ZTIN10__cxxabiv120__si_class_type_infoE
+ Symbol not reexported anymore: __ZTIN10__cxxabiv121__vmi_class_type_infoE
+
* [libc++] Always keep libc++abi re-exports up-to-date
This patch makes sure that the set of libc++abi symbols re-exported from
libc++
diff --git
a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
b/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
index 917388f86811fe..32acae46e292d7 100644
---
a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
+++
b/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
@@ -78,12 +78,9 @@
{'is_defined': False, 'name': '__ZTIN10__cxxabiv116__enum_type_infoE', 'type':
'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv116__shim_type_infoE', 'type':
'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv117__array_type_infoE',
'type': 'U'}
-{'is_defined': False, 'name': '__ZTIN10__cxxabiv117__class_type_infoE',
'type': 'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv117__pbase_type_infoE',
'type': 'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv119__pointer_type_infoE',
'type': 'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv120__function_type_infoE',
'type': 'U'}
-{'is_defined': False, 'name': '__ZTIN10__cxxabiv1
[llvm-branch-commits] [libcxxabi] c36d7fd - [libc++] Avoid re-exporting a few specific symbols from libc++abi (#109054)
Author: Louis Dionne
Date: 2024-10-15T08:50:13+02:00
New Revision: c36d7fd568a5da5b9ea5b0e6f60b1210ecc512d0
URL:
https://github.com/llvm/llvm-project/commit/c36d7fd568a5da5b9ea5b0e6f60b1210ecc512d0
DIFF:
https://github.com/llvm/llvm-project/commit/c36d7fd568a5da5b9ea5b0e6f60b1210ecc512d0.diff
LOG: [libc++] Avoid re-exporting a few specific symbols from libc++abi (#109054)
In 6a884a9aef39, I synchronized the export list of libc++abi to the
export list of libc++. From the linker's perspective, this caused these
symbols to be taken from libc++.dylib instead of libc++abi.dylib.
However, that can be problematic when back-deploying. Indeed, this means
that the linker will encode an undefined reference to be fullfilled by
libc++.dylib, but when backdeploying against an older system, that
symbol might only be available in libc++abi.dylib.
Most of the symbols that started being re-exported after 6a884a9aef39
turn out to be implementation details of libc++abi, so nobody really
depends on them and this back-deployment issue is inconsequential.
However, we ran into issues with a few of these symbols while testing
LLVM 19, which led to this patch. This slipped between the cracks and
that is why the patch is coming so long after the original patch landed.
In the future, a follow-up cleanup would be to stop exporting most of
the _cxxabiv1_foo_type_infoE symbols from both libc++abi and libc++
since they are implementation details that nobody should be relying on.
rdar://131984512
(cherry picked from commit 677e8cd6ff51e178bcb4669104763f71a2de106c)
Added:
libcxxabi/lib/symbols-not-reexported.exp
Modified:
libcxx/lib/abi/CHANGELOG.TXT
libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
libcxxabi/lib/cxxabiv1.exp
libcxxabi/lib/itanium-base.exp
libcxxabi/src/CMakeLists.txt
Removed:
diff --git a/libcxx/lib/abi/CHANGELOG.TXT b/libcxx/lib/abi/CHANGELOG.TXT
index 32526f1786c6d9..68c9d980a016ea 100644
--- a/libcxx/lib/abi/CHANGELOG.TXT
+++ b/libcxx/lib/abi/CHANGELOG.TXT
@@ -16,6 +16,36 @@ New entries should be added directly below the "Version"
header.
Version 19.0
+* [libc++] Avoid re-exporting a few specific symbols from libc++abi
+
+ In 6a884a9aef39, I synchronized the export list of libc++abi to the
+ export list of libc++. From the linker's perspective, this caused
+ these symbols to be taken from libc++.dylib instead of libc++abi.dylib.
+
+ However, that can be problematic when back-deploying. Indeed, this means
+ that the linker will encode an undefined reference to be fullfilled by
+ libc++.dylib, but when backdeploying against an older system, that symbol
+ might only be available in libc++abi.dylib.
+
+ Most of the symbols that started being re-exported after 6a884a9aef39
+ turn out to be implementation details of libc++abi, so nobody really
+ depends on them and this back-deployment issue is inconsequential.
+
+ However, we ran into issues with a few of these symbols while testing
+ LLVM 19, which led to this patch.
+
+ In the future, a follow-up cleanup would be to stop exporting most of
+ the _cxxabiv1_foo_type_infoE symbols from both libc++abi and libc++
+ since they are implementation details that nobody should be relying
+ on.
+
+ -apple-darwin
+ ---
+ Symbol not reexported anymore: ___cxa_rethrow_primary_exception
+ Symbol not reexported anymore: __ZTIN10__cxxabiv117__class_type_infoE
+ Symbol not reexported anymore: __ZTIN10__cxxabiv120__si_class_type_infoE
+ Symbol not reexported anymore: __ZTIN10__cxxabiv121__vmi_class_type_infoE
+
* [libc++] Always keep libc++abi re-exports up-to-date
This patch makes sure that the set of libc++abi symbols re-exported from
libc++
diff --git
a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
b/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
index 917388f86811fe..32acae46e292d7 100644
---
a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
+++
b/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
@@ -78,12 +78,9 @@
{'is_defined': False, 'name': '__ZTIN10__cxxabiv116__enum_type_infoE', 'type':
'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv116__shim_type_infoE', 'type':
'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv117__array_type_infoE',
'type': 'U'}
-{'is_defined': False, 'name': '__ZTIN10__cxxabiv117__class_type_infoE',
'type': 'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv117__pbase_type_infoE',
'type': 'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv119__pointer_type_infoE',
'type': 'U'}
{'is_defined': False, 'name': '__ZTIN10__cxxabiv120__function_type_infoE',
'type': 'U'}
-{'is_defined': False, 'name': '__ZTIN10__
[llvm-branch-commits] [libcxx] [libcxxabi] release/19.x: [libc++] Avoid re-exporting a few specific symbols from libc++abi (#109054) (PR #110677)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/110677 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [libcxxabi] release/19.x: [libc++] Avoid re-exporting a few specific symbols from libc++abi (#109054) (PR #110677)
tru wrote: Can someone post this as a breaking change to the discourse so that I can link it from the release notes? https://github.com/llvm/llvm-project/pull/110677 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [release/19.x][libc++] Adjust the version of __cpp_lib_ranges in C++20 mode (PR #109324)
github-actions[bot] wrote: @ldionne (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/109324 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] f12830a - FastISel: Fix incorrectly using getPointerTy (#110465)
Author: Matt Arsenault
Date: 2024-10-15T08:50:50+02:00
New Revision: f12830aac9040b03d3d53c66d65528bd26a6e47a
URL:
https://github.com/llvm/llvm-project/commit/f12830aac9040b03d3d53c66d65528bd26a6e47a
DIFF:
https://github.com/llvm/llvm-project/commit/f12830aac9040b03d3d53c66d65528bd26a6e47a.diff
LOG: FastISel: Fix incorrectly using getPointerTy (#110465)
This was using the default address space instead of the
correct one.
Fixes #56055
Keep old method around for ABI compatibility on the release branch.
(cherry picked from commit 81ba95cefe1b5a12f0a7d8e6a383bcce9e95b785)
Added:
llvm/test/CodeGen/X86/issue56055.ll
Modified:
llvm/include/llvm/CodeGen/FastISel.h
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/Target/X86/X86FastISel.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/FastISel.h
b/llvm/include/llvm/CodeGen/FastISel.h
index 3cbc35400181dd..f91bd692accad8 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -275,7 +275,12 @@ class FastISel {
/// This is a wrapper around getRegForValue that also takes care of
/// truncating or sign-extending the given getelementptr index value.
- Register getRegForGEPIndex(const Value *Idx);
+ Register getRegForGEPIndex(MVT PtrVT, const Value *Idx);
+
+ /// Retained for ABI compatibility in release branch.
+ Register getRegForGEPIndex(const Value *Idx) {
+return getRegForGEPIndex(TLI.getPointerTy(DL), Idx);
+ }
/// We're checking to see if we can fold \p LI into \p FoldInst. Note
/// that we could have a sequence where multiple LLVM IR instructions are
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index ef9f7833551905..246acc7f405837 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -380,14 +380,13 @@ void FastISel::updateValueMap(const Value *I, Register
Reg, unsigned NumRegs) {
}
}
-Register FastISel::getRegForGEPIndex(const Value *Idx) {
+Register FastISel::getRegForGEPIndex(MVT PtrVT, const Value *Idx) {
Register IdxN = getRegForValue(Idx);
if (!IdxN)
// Unhandled operand. Halt "fast" selection and bail.
return Register();
// If the index is smaller or larger than intptr_t, truncate or extend it.
- MVT PtrVT = TLI.getPointerTy(DL);
EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
if (IdxVT.bitsLT(PtrVT)) {
IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
@@ -543,7 +542,8 @@ bool FastISel::selectGetElementPtr(const User *I) {
uint64_t TotalOffs = 0;
// FIXME: What's a good SWAG number for MaxOffs?
uint64_t MaxOffs = 2048;
- MVT VT = TLI.getPointerTy(DL);
+ MVT VT = TLI.getValueType(DL, I->getType()).getSimpleVT();
+
for (gep_type_iterator GTI = gep_type_begin(I), E = gep_type_end(I);
GTI != E; ++GTI) {
const Value *Idx = GTI.getOperand();
@@ -584,7 +584,7 @@ bool FastISel::selectGetElementPtr(const User *I) {
// N = N + Idx * ElementSize;
uint64_t ElementSize = GTI.getSequentialElementStride(DL);
- Register IdxN = getRegForGEPIndex(Idx);
+ Register IdxN = getRegForGEPIndex(VT, Idx);
if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
return false;
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp
b/llvm/lib/Target/X86/X86FastISel.cpp
index 2eae155956368f..5d594bd54fbfc4 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -902,6 +902,8 @@ bool X86FastISel::X86SelectAddress(const Value *V,
X86AddressMode &AM) {
uint64_t Disp = (int32_t)AM.Disp;
unsigned IndexReg = AM.IndexReg;
unsigned Scale = AM.Scale;
+MVT PtrVT = TLI.getValueType(DL, U->getType()).getSimpleVT();
+
gep_type_iterator GTI = gep_type_begin(U);
// Iterate through the indices, folding what we can. Constants can be
// folded, and one dynamic index can be handled, if the scale is supported.
@@ -937,7 +939,7 @@ bool X86FastISel::X86SelectAddress(const Value *V,
X86AddressMode &AM) {
(S == 1 || S == 2 || S == 4 || S == 8)) {
// Scaled-index addressing.
Scale = S;
- IndexReg = getRegForGEPIndex(Op);
+ IndexReg = getRegForGEPIndex(PtrVT, Op);
if (IndexReg == 0)
return false;
break;
diff --git a/llvm/test/CodeGen/X86/issue56055.ll
b/llvm/test/CodeGen/X86/issue56055.ll
new file mode 100644
index 00..27eaf13e3b00be
--- /dev/null
+++ b/llvm/test/CodeGen/X86/issue56055.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -fast-isel < %s | FileCheck -check-prefixes=CHECK,FASTISEL %s
+; RUN: llc < %s | FileCheck -check-prefixes=CHECK,SDAG %s
+
+target datalayout =
"e-m:w-p270:32:32-p271:32:32
[llvm-branch-commits] [llvm] FastISel: Fix incorrectly using getPointerTy (#110465) (PR #110827)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/110827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 139d737 - Move out of line
Author: Matt Arsenault
Date: 2024-10-15T08:50:50+02:00
New Revision: 139d737ae04cea31232e8b0c83d8687d0234af3d
URL:
https://github.com/llvm/llvm-project/commit/139d737ae04cea31232e8b0c83d8687d0234af3d
DIFF:
https://github.com/llvm/llvm-project/commit/139d737ae04cea31232e8b0c83d8687d0234af3d.diff
LOG: Move out of line
Added:
Modified:
llvm/include/llvm/CodeGen/FastISel.h
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/FastISel.h
b/llvm/include/llvm/CodeGen/FastISel.h
index f91bd692accad8..95e8004cc09c7a 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -278,9 +278,7 @@ class FastISel {
Register getRegForGEPIndex(MVT PtrVT, const Value *Idx);
/// Retained for ABI compatibility in release branch.
- Register getRegForGEPIndex(const Value *Idx) {
-return getRegForGEPIndex(TLI.getPointerTy(DL), Idx);
- }
+ Register getRegForGEPIndex(const Value *Idx);
/// We're checking to see if we can fold \p LI into \p FoldInst. Note
/// that we could have a sequence where multiple LLVM IR instructions are
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 246acc7f405837..398381a8164b2b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -397,6 +397,10 @@ Register FastISel::getRegForGEPIndex(MVT PtrVT, const
Value *Idx) {
return IdxN;
}
+Register FastISel::getRegForGEPIndex(const Value *Idx) {
+ return getRegForGEPIndex(TLI.getPointerTy(DL), Idx);
+}
+
void FastISel::recomputeInsertPt() {
if (getLastLocalValue()) {
FuncInfo.InsertPt = getLastLocalValue();
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[llvm-branch-commits] [llvm] FastISel: Fix incorrectly using getPointerTy (#110465) (PR #110827)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/110827
>From f12830aac9040b03d3d53c66d65528bd26a6e47a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 30 Sep 2024 13:43:53 +0400
Subject: [PATCH 1/2] FastISel: Fix incorrectly using getPointerTy (#110465)
This was using the default address space instead of the
correct one.
Fixes #56055
Keep old method around for ABI compatibility on the release branch.
(cherry picked from commit 81ba95cefe1b5a12f0a7d8e6a383bcce9e95b785)
---
llvm/include/llvm/CodeGen/FastISel.h | 7 +-
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 8 +--
llvm/lib/Target/X86/X86FastISel.cpp| 4 +-
llvm/test/CodeGen/X86/issue56055.ll| 81 ++
4 files changed, 94 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/issue56055.ll
diff --git a/llvm/include/llvm/CodeGen/FastISel.h
b/llvm/include/llvm/CodeGen/FastISel.h
index 3cbc35400181dd..f91bd692accad8 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -275,7 +275,12 @@ class FastISel {
/// This is a wrapper around getRegForValue that also takes care of
/// truncating or sign-extending the given getelementptr index value.
- Register getRegForGEPIndex(const Value *Idx);
+ Register getRegForGEPIndex(MVT PtrVT, const Value *Idx);
+
+ /// Retained for ABI compatibility in release branch.
+ Register getRegForGEPIndex(const Value *Idx) {
+return getRegForGEPIndex(TLI.getPointerTy(DL), Idx);
+ }
/// We're checking to see if we can fold \p LI into \p FoldInst. Note
/// that we could have a sequence where multiple LLVM IR instructions are
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index ef9f7833551905..246acc7f405837 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -380,14 +380,13 @@ void FastISel::updateValueMap(const Value *I, Register
Reg, unsigned NumRegs) {
}
}
-Register FastISel::getRegForGEPIndex(const Value *Idx) {
+Register FastISel::getRegForGEPIndex(MVT PtrVT, const Value *Idx) {
Register IdxN = getRegForValue(Idx);
if (!IdxN)
// Unhandled operand. Halt "fast" selection and bail.
return Register();
// If the index is smaller or larger than intptr_t, truncate or extend it.
- MVT PtrVT = TLI.getPointerTy(DL);
EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
if (IdxVT.bitsLT(PtrVT)) {
IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
@@ -543,7 +542,8 @@ bool FastISel::selectGetElementPtr(const User *I) {
uint64_t TotalOffs = 0;
// FIXME: What's a good SWAG number for MaxOffs?
uint64_t MaxOffs = 2048;
- MVT VT = TLI.getPointerTy(DL);
+ MVT VT = TLI.getValueType(DL, I->getType()).getSimpleVT();
+
for (gep_type_iterator GTI = gep_type_begin(I), E = gep_type_end(I);
GTI != E; ++GTI) {
const Value *Idx = GTI.getOperand();
@@ -584,7 +584,7 @@ bool FastISel::selectGetElementPtr(const User *I) {
// N = N + Idx * ElementSize;
uint64_t ElementSize = GTI.getSequentialElementStride(DL);
- Register IdxN = getRegForGEPIndex(Idx);
+ Register IdxN = getRegForGEPIndex(VT, Idx);
if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
return false;
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp
b/llvm/lib/Target/X86/X86FastISel.cpp
index 2eae155956368f..5d594bd54fbfc4 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -902,6 +902,8 @@ bool X86FastISel::X86SelectAddress(const Value *V,
X86AddressMode &AM) {
uint64_t Disp = (int32_t)AM.Disp;
unsigned IndexReg = AM.IndexReg;
unsigned Scale = AM.Scale;
+MVT PtrVT = TLI.getValueType(DL, U->getType()).getSimpleVT();
+
gep_type_iterator GTI = gep_type_begin(U);
// Iterate through the indices, folding what we can. Constants can be
// folded, and one dynamic index can be handled, if the scale is supported.
@@ -937,7 +939,7 @@ bool X86FastISel::X86SelectAddress(const Value *V,
X86AddressMode &AM) {
(S == 1 || S == 2 || S == 4 || S == 8)) {
// Scaled-index addressing.
Scale = S;
- IndexReg = getRegForGEPIndex(Op);
+ IndexReg = getRegForGEPIndex(PtrVT, Op);
if (IndexReg == 0)
return false;
break;
diff --git a/llvm/test/CodeGen/X86/issue56055.ll
b/llvm/test/CodeGen/X86/issue56055.ll
new file mode 100644
index 00..27eaf13e3b00be
--- /dev/null
+++ b/llvm/test/CodeGen/X86/issue56055.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -fast-isel < %s | FileCheck -check-prefixes=CHECK,FASTISEL %s
+; RUN: llc < %s | FileCheck -check-prefixes=CHECK,SDAG %s
+
+target datalayout =
"e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:12
[llvm-branch-commits] [llvm] FastISel: Fix incorrectly using getPointerTy (#110465) (PR #110827)
github-actions[bot] wrote: @arsenm (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/110827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] [libcxxabi] release/19.x: [libc++] Avoid re-exporting a few specific symbols from libc++abi (#109054) (PR #110677)
github-actions[bot] wrote: @ldionne (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/110677 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 92f4a2b - [x86] combineMUL - when looking for a vector multiply by splat constant, ensure we're only accepting ConstantInt splat scalars.
Author: Simon Pilgrim
Date: 2024-10-15T08:51:57+02:00
New Revision: 92f4a2bf0a9d3962a25d15c1df5b6824950c74dc
URL:
https://github.com/llvm/llvm-project/commit/92f4a2bf0a9d3962a25d15c1df5b6824950c74dc
DIFF:
https://github.com/llvm/llvm-project/commit/92f4a2bf0a9d3962a25d15c1df5b6824950c74dc.diff
LOG: [x86] combineMUL - when looking for a vector multiply by splat constant,
ensure we're only accepting ConstantInt splat scalars.
Fixes #70
(cherry picked from commit 9459d729d22b7bfedad9d3a4237162077c6984a4)
Added:
llvm/test/CodeGen/X86/pr70.ll
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 10f269f8037784..4e3a181f9a3aef 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47899,7 +47899,8 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
if (VT.isVector())
if (auto *RawC = getTargetConstantFromNode(N->getOperand(1)))
if (auto *SplatC = RawC->getSplatValue())
- C = &(SplatC->getUniqueInteger());
+ if (auto *SplatCI = dyn_cast(SplatC))
+C = &(SplatCI->getValue());
if (!C || C->getBitWidth() != VT.getScalarSizeInBits())
return SDValue();
diff --git a/llvm/test/CodeGen/X86/pr70.ll
b/llvm/test/CodeGen/X86/pr70.ll
new file mode 100644
index 00..145bf7119edcb9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr70.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=i686-pc-windows-msvc -mcpu=corei7-avx | FileCheck %s
+
+define void @PR70(<16 x i32> %x_load, ptr %offsetsPtr.i) {
+; CHECK-LABEL: PR70:
+; CHECK: # %bb.0:
+; CHECK-NEXT:movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:vbroadcastss {{.*#+}} xmm2 =
[2.80259693E-44,2.80259693E-44,2.80259693E-44,2.80259693E-44]
+; CHECK-NEXT:vpmulld %xmm2, %xmm1, %xmm3
+; CHECK-NEXT:vextractf128 $1, %ymm1, %xmm1
+; CHECK-NEXT:vpmulld %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:vpmulld %xmm2, %xmm0, %xmm4
+; CHECK-NEXT:vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:vpmulld %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:vmovdqu %xmm0, 16(%eax)
+; CHECK-NEXT:vmovdqu %xmm4, (%eax)
+; CHECK-NEXT:vmovdqu %xmm1, 48(%eax)
+; CHECK-NEXT:vmovdqu %xmm3, 32(%eax)
+; CHECK-NEXT:vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:vmovdqu %xmm0, 16
+; CHECK-NEXT:vmovdqu %xmm0, 0
+; CHECK-NEXT:vmovdqu %xmm0, 48
+; CHECK-NEXT:vmovdqu %xmm0, 32
+; CHECK-NEXT:vzeroupper
+; CHECK-NEXT:retl
+ %mul__x_load = mul <16 x i32> , %x_load
+ store <16 x i32> %mul__x_load, ptr %offsetsPtr.i, align 4
+ %blend1.i12.i = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>
zeroinitializer, <8 x float> , <8 x float> zeroinitializer)
+ %blend.i13.i = shufflevector <8 x float> zeroinitializer, <8 x float>
%blend1.i12.i, <16 x i32>
+ %blendAsInt.i14.i = bitcast <16 x float> %blend.i13.i to <16 x i32>
+ store <16 x i32> %blendAsInt.i14.i, ptr null, align 4
+ ret void
+}
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[llvm-branch-commits] [llvm] release/19.x: [x86] combineMUL - when looking for a vector multiply by splat constant, ensure we're only accepting ConstantInt splat scalars. (PR #111246)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/111246
>From 92f4a2bf0a9d3962a25d15c1df5b6824950c74dc Mon Sep 17 00:00:00 2001
From: Simon Pilgrim
Date: Fri, 4 Oct 2024 18:09:53 +0100
Subject: [PATCH] [x86] combineMUL - when looking for a vector multiply by
splat constant, ensure we're only accepting ConstantInt splat scalars.
Fixes #70
(cherry picked from commit 9459d729d22b7bfedad9d3a4237162077c6984a4)
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 ++-
llvm/test/CodeGen/X86/pr70.ll | 33 +
2 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/pr70.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 10f269f8037784..4e3a181f9a3aef 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47899,7 +47899,8 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
if (VT.isVector())
if (auto *RawC = getTargetConstantFromNode(N->getOperand(1)))
if (auto *SplatC = RawC->getSplatValue())
- C = &(SplatC->getUniqueInteger());
+ if (auto *SplatCI = dyn_cast(SplatC))
+C = &(SplatCI->getValue());
if (!C || C->getBitWidth() != VT.getScalarSizeInBits())
return SDValue();
diff --git a/llvm/test/CodeGen/X86/pr70.ll
b/llvm/test/CodeGen/X86/pr70.ll
new file mode 100644
index 00..145bf7119edcb9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr70.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=i686-pc-windows-msvc -mcpu=corei7-avx | FileCheck %s
+
+define void @PR70(<16 x i32> %x_load, ptr %offsetsPtr.i) {
+; CHECK-LABEL: PR70:
+; CHECK: # %bb.0:
+; CHECK-NEXT:movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:vbroadcastss {{.*#+}} xmm2 =
[2.80259693E-44,2.80259693E-44,2.80259693E-44,2.80259693E-44]
+; CHECK-NEXT:vpmulld %xmm2, %xmm1, %xmm3
+; CHECK-NEXT:vextractf128 $1, %ymm1, %xmm1
+; CHECK-NEXT:vpmulld %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:vpmulld %xmm2, %xmm0, %xmm4
+; CHECK-NEXT:vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:vpmulld %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:vmovdqu %xmm0, 16(%eax)
+; CHECK-NEXT:vmovdqu %xmm4, (%eax)
+; CHECK-NEXT:vmovdqu %xmm1, 48(%eax)
+; CHECK-NEXT:vmovdqu %xmm3, 32(%eax)
+; CHECK-NEXT:vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:vmovdqu %xmm0, 16
+; CHECK-NEXT:vmovdqu %xmm0, 0
+; CHECK-NEXT:vmovdqu %xmm0, 48
+; CHECK-NEXT:vmovdqu %xmm0, 32
+; CHECK-NEXT:vzeroupper
+; CHECK-NEXT:retl
+ %mul__x_load = mul <16 x i32> , %x_load
+ store <16 x i32> %mul__x_load, ptr %offsetsPtr.i, align 4
+ %blend1.i12.i = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>
zeroinitializer, <8 x float> , <8 x float> zeroinitializer)
+ %blend.i13.i = shufflevector <8 x float> zeroinitializer, <8 x float>
%blend1.i12.i, <16 x i32>
+ %blendAsInt.i14.i = bitcast <16 x float> %blend.i13.i to <16 x i32>
+ store <16 x i32> %blendAsInt.i14.i, ptr null, align 4
+ ret void
+}
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[llvm-branch-commits] [llvm] release/19.x: [x86] combineMUL - when looking for a vector multiply by splat constant, ensure we're only accepting ConstantInt splat scalars. (PR #111246)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/111246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 8cb7d8a - [VectorCombine] Do not try to operate on OperandBundles. (#111635)
Author: David Green
Date: 2024-10-15T08:53:11+02:00
New Revision: 8cb7d8a70d81f836a5e4d1f1a8be4989ac8d2671
URL:
https://github.com/llvm/llvm-project/commit/8cb7d8a70d81f836a5e4d1f1a8be4989ac8d2671
DIFF:
https://github.com/llvm/llvm-project/commit/8cb7d8a70d81f836a5e4d1f1a8be4989ac8d2671.diff
LOG: [VectorCombine] Do not try to operate on OperandBundles. (#111635)
This bails out if we see an intrinsic with an operand bundle on it, to
make sure we don't process the bundles incorrectly.
Fixes #110382.
(cherry picked from commit c136d3237a3c6230cfe1ab3f0f6790f903c54a27)
Added:
Modified:
llvm/lib/Transforms/Vectorize/VectorCombine.cpp
llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 444598520c981a..679934d07e36d0 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1900,33 +1900,35 @@ bool VectorCombine::foldShuffleToIdentity(Instruction
&I) {
// We need each element to be the same type of value, and check that each
// element has a single use.
-if (all_of(drop_begin(Item), [Item](InstLane IL) {
- Value *FrontV = Item.front().first->get();
- if (!IL.first)
-return true;
- Value *V = IL.first->get();
- if (auto *I = dyn_cast(V); I && !I->hasOneUse())
-return false;
- if (V->getValueID() != FrontV->getValueID())
-return false;
- if (auto *CI = dyn_cast(V))
-if (CI->getPredicate() != cast(FrontV)->getPredicate())
- return false;
- if (auto *CI = dyn_cast(V))
-if (CI->getSrcTy() != cast(FrontV)->getSrcTy())
- return false;
- if (auto *SI = dyn_cast(V))
-if (!isa(SI->getOperand(0)->getType()) ||
-SI->getOperand(0)->getType() !=
-cast(FrontV)->getOperand(0)->getType())
- return false;
- if (isa(V) && !isa(V))
-return false;
- auto *II = dyn_cast(V);
- return !II || (isa(FrontV) &&
- II->getIntrinsicID() ==
- cast(FrontV)->getIntrinsicID());
-})) {
+auto CheckLaneIsEquivalentToFirst = [Item](InstLane IL) {
+ Value *FrontV = Item.front().first->get();
+ if (!IL.first)
+return true;
+ Value *V = IL.first->get();
+ if (auto *I = dyn_cast(V); I && !I->hasOneUse())
+return false;
+ if (V->getValueID() != FrontV->getValueID())
+return false;
+ if (auto *CI = dyn_cast(V))
+if (CI->getPredicate() != cast(FrontV)->getPredicate())
+ return false;
+ if (auto *CI = dyn_cast(V))
+if (CI->getSrcTy() != cast(FrontV)->getSrcTy())
+ return false;
+ if (auto *SI = dyn_cast(V))
+if (!isa(SI->getOperand(0)->getType()) ||
+SI->getOperand(0)->getType() !=
+cast(FrontV)->getOperand(0)->getType())
+ return false;
+ if (isa(V) && !isa(V))
+return false;
+ auto *II = dyn_cast(V);
+ return !II || (isa(FrontV) &&
+ II->getIntrinsicID() ==
+ cast(FrontV)->getIntrinsicID() &&
+ !II->hasOperandBundles());
+};
+if (all_of(drop_begin(Item), CheckLaneIsEquivalentToFirst)) {
// Check the operator is one that we support.
if (isa(FrontU)) {
// We exclude div/rem in case they hit UB from poison lanes.
@@ -1954,7 +1956,8 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I)
{
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 2));
continue;
} else if (auto *II = dyn_cast(FrontU);
- II && isTriviallyVectorizable(II->getIntrinsicID())) {
+ II && isTriviallyVectorizable(II->getIntrinsicID()) &&
+ !II->hasOperandBundles()) {
for (unsigned Op = 0, E = II->getNumOperands() - 1; Op < E; Op++) {
if (isVectorIntrinsicWithScalarOpAtArg(II->getIntrinsicID(), Op)) {
if (!all_of(drop_begin(Item), [Item, Op](InstLane &IL) {
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
index af04fb0ab4621b..66fe11369d88be 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
@@ -1066,4 +1066,52 @@ entry:
ret <2 x float> %4
}
+define <16 x i64> @operandbundles(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) {
+; CHECK-LABEL: @operandbundles(
+; CHECK-NEXT:[[CALL:%.*]] = call <4 x i64> @llvm.fshl.v4i64(<4 x i64>
[[A:%.*]], <4 x i64> [[B:%.*]], <4 x i64> [[C:%.*]]) [ "j
[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/111796
>From 8cb7d8a70d81f836a5e4d1f1a8be4989ac8d2671 Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Oct 2024 16:20:03 +0100
Subject: [PATCH 1/2] [VectorCombine] Do not try to operate on OperandBundles.
(#111635)
This bails out if we see an intrinsic with an operand bundle on it, to
make sure we don't process the bundles incorrectly.
Fixes #110382.
(cherry picked from commit c136d3237a3c6230cfe1ab3f0f6790f903c54a27)
---
.../Transforms/Vectorize/VectorCombine.cpp| 59 ++-
.../AArch64/shuffletoidentity.ll | 48 +++
2 files changed, 79 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 444598520c981a..679934d07e36d0 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1900,33 +1900,35 @@ bool VectorCombine::foldShuffleToIdentity(Instruction
&I) {
// We need each element to be the same type of value, and check that each
// element has a single use.
-if (all_of(drop_begin(Item), [Item](InstLane IL) {
- Value *FrontV = Item.front().first->get();
- if (!IL.first)
-return true;
- Value *V = IL.first->get();
- if (auto *I = dyn_cast(V); I && !I->hasOneUse())
-return false;
- if (V->getValueID() != FrontV->getValueID())
-return false;
- if (auto *CI = dyn_cast(V))
-if (CI->getPredicate() != cast(FrontV)->getPredicate())
- return false;
- if (auto *CI = dyn_cast(V))
-if (CI->getSrcTy() != cast(FrontV)->getSrcTy())
- return false;
- if (auto *SI = dyn_cast(V))
-if (!isa(SI->getOperand(0)->getType()) ||
-SI->getOperand(0)->getType() !=
-cast(FrontV)->getOperand(0)->getType())
- return false;
- if (isa(V) && !isa(V))
-return false;
- auto *II = dyn_cast(V);
- return !II || (isa(FrontV) &&
- II->getIntrinsicID() ==
- cast(FrontV)->getIntrinsicID());
-})) {
+auto CheckLaneIsEquivalentToFirst = [Item](InstLane IL) {
+ Value *FrontV = Item.front().first->get();
+ if (!IL.first)
+return true;
+ Value *V = IL.first->get();
+ if (auto *I = dyn_cast(V); I && !I->hasOneUse())
+return false;
+ if (V->getValueID() != FrontV->getValueID())
+return false;
+ if (auto *CI = dyn_cast(V))
+if (CI->getPredicate() != cast(FrontV)->getPredicate())
+ return false;
+ if (auto *CI = dyn_cast(V))
+if (CI->getSrcTy() != cast(FrontV)->getSrcTy())
+ return false;
+ if (auto *SI = dyn_cast(V))
+if (!isa(SI->getOperand(0)->getType()) ||
+SI->getOperand(0)->getType() !=
+cast(FrontV)->getOperand(0)->getType())
+ return false;
+ if (isa(V) && !isa(V))
+return false;
+ auto *II = dyn_cast(V);
+ return !II || (isa(FrontV) &&
+ II->getIntrinsicID() ==
+ cast(FrontV)->getIntrinsicID() &&
+ !II->hasOperandBundles());
+};
+if (all_of(drop_begin(Item), CheckLaneIsEquivalentToFirst)) {
// Check the operator is one that we support.
if (isa(FrontU)) {
// We exclude div/rem in case they hit UB from poison lanes.
@@ -1954,7 +1956,8 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I)
{
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 2));
continue;
} else if (auto *II = dyn_cast(FrontU);
- II && isTriviallyVectorizable(II->getIntrinsicID())) {
+ II && isTriviallyVectorizable(II->getIntrinsicID()) &&
+ !II->hasOperandBundles()) {
for (unsigned Op = 0, E = II->getNumOperands() - 1; Op < E; Op++) {
if (isVectorIntrinsicWithScalarOpAtArg(II->getIntrinsicID(), Op)) {
if (!all_of(drop_begin(Item), [Item, Op](InstLane &IL) {
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
index af04fb0ab4621b..66fe11369d88be 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
@@ -1066,4 +1066,52 @@ entry:
ret <2 x float> %4
}
+define <16 x i64> @operandbundles(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) {
+; CHECK-LABEL: @operandbundles(
+; CHECK-NEXT:[[CALL:%.*]] = call <4 x i64> @llvm.fshl.v4i64(<4 x i64>
[[A:%.*]], <4 x i64> [[B:%.*]], <4 x i64> [[C:%.*]]) [ "jl_roots"(ptr
addrspace(10) null, ptr addrspace(10) null) ]
+; CHECK-NEXT:[[SHUFFLEVECTOR:%.*]] = shufflevector <4 x i
[llvm-branch-commits] [clang] [Clang] Improve type traits recognition in `__has_builtin` (#111516) (PR #111660)
github-actions[bot] wrote: @cor3ntin (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/111660 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 0419953 - Update test since trunk
Author: David Green
Date: 2024-10-15T08:53:11+02:00
New Revision: 04199538e3a293303514d93346ddd02bbf1c0314
URL:
https://github.com/llvm/llvm-project/commit/04199538e3a293303514d93346ddd02bbf1c0314
DIFF:
https://github.com/llvm/llvm-project/commit/04199538e3a293303514d93346ddd02bbf1c0314.diff
LOG: Update test since trunk
Added:
Modified:
llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Removed:
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
index 66fe11369d88be..0b91618da64068 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
@@ -1084,8 +1084,8 @@ define <8 x i8> @operandbundles_first(<8 x i8> %a) {
; CHECK-NEXT:[[AB:%.*]] = shufflevector <8 x i8> [[A:%.*]], <8 x i8>
poison, <4 x i32>
; CHECK-NEXT:[[AT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> poison,
<4 x i32>
; CHECK-NEXT:[[ABT:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[AT]],
i1 false) [ "jl_roots"(ptr addrspace(10) null, ptr addrspace(10) null) ]
-; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <4 x i8> [[AT]], <4 x i8>
[[AB]], <8 x i32>
-; CHECK-NEXT:[[R:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP1]],
i1 false)
+; CHECK-NEXT:[[ABB:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[AB]],
i1 false)
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i8> [[ABT]], <4 x i8> [[ABB]],
<8 x i32>
; CHECK-NEXT:ret <8 x i8> [[R]]
;
%ab = shufflevector <8 x i8> %a, <8 x i8> poison, <4 x i32>
@@ -1100,9 +1100,9 @@ define <8 x i8> @operandbundles_second(<8 x i8> %a) {
; CHECK-LABEL: @operandbundles_second(
; CHECK-NEXT:[[AB:%.*]] = shufflevector <8 x i8> [[A:%.*]], <8 x i8>
poison, <4 x i32>
; CHECK-NEXT:[[AT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> poison,
<4 x i32>
+; CHECK-NEXT:[[ABT:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[AT]],
i1 false)
; CHECK-NEXT:[[ABB:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[AB]],
i1 false) [ "jl_roots"(ptr addrspace(10) null, ptr addrspace(10) null) ]
-; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <4 x i8> [[AT]], <4 x i8>
[[AB]], <8 x i32>
-; CHECK-NEXT:[[R:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP1]],
i1 false)
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i8> [[ABT]], <4 x i8> [[ABB]],
<8 x i32>
; CHECK-NEXT:ret <8 x i8> [[R]]
;
%ab = shufflevector <8 x i8> %a, <8 x i8> poison, <4 x i32>
___
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llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] dedbdfb - [Clang] Improve type traits recognition in `__has_builtin` (#111516)
Author: cor3ntin
Date: 2024-10-15T08:52:34+02:00
New Revision: dedbdfb70daf06fc07bb4dfbec1d18af8fcef28f
URL:
https://github.com/llvm/llvm-project/commit/dedbdfb70daf06fc07bb4dfbec1d18af8fcef28f
DIFF:
https://github.com/llvm/llvm-project/commit/dedbdfb70daf06fc07bb4dfbec1d18af8fcef28f.diff
LOG: [Clang] Improve type traits recognition in `__has_builtin` (#111516)
`__has_builtin` was relying on reversible identifiers and string
matching to recognize builtin-type traits, leading to some newer type
traits not being recognized.
Fixes #111477
Added:
Modified:
clang/include/clang/Basic/TokenKinds.def
clang/lib/Lex/PPMacroExpansion.cpp
clang/test/Preprocessor/feature_tests.cpp
Removed:
diff --git a/clang/include/clang/Basic/TokenKinds.def
b/clang/include/clang/Basic/TokenKinds.def
index 8c54661e65cf46..0526fbf51bd91a 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -64,6 +64,10 @@
#ifndef EXPRESSION_TRAIT
#define EXPRESSION_TRAIT(I,E,K) KEYWORD(I,K)
#endif
+#ifndef TRANSFORM_TYPE_TRAIT_DEF
+#define TRANSFORM_TYPE_TRAIT_DEF(K, Trait) KEYWORD(__##Trait, KEYCXX)
+#endif
+
#ifndef ALIAS
#define ALIAS(X,Y,Z)
#endif
@@ -534,7 +538,6 @@ TYPE_TRAIT_1(__has_unique_object_representations,
TYPE_TRAIT_2(__is_layout_compatible, IsLayoutCompatible, KEYCXX)
TYPE_TRAIT_2(__is_pointer_interconvertible_base_of,
IsPointerInterconvertibleBaseOf, KEYCXX)
-#define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) KEYWORD(__##Trait, KEYCXX)
#include "clang/Basic/TransformTypeTraits.def"
// Clang-only C++ Type Traits
diff --git a/clang/lib/Lex/PPMacroExpansion.cpp
b/clang/lib/Lex/PPMacroExpansion.cpp
index 3913ff08c2eb55..fb88ec2bf603fe 100644
--- a/clang/lib/Lex/PPMacroExpansion.cpp
+++ b/clang/lib/Lex/PPMacroExpansion.cpp
@@ -1602,6 +1602,34 @@ static bool isTargetVariantEnvironment(const TargetInfo
&TI,
return false;
}
+static bool IsBuiltinTrait(Token &Tok) {
+
+#define TYPE_TRAIT_1(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define TYPE_TRAIT_2(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define TYPE_TRAIT_N(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define ARRAY_TYPE_TRAIT(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define EXPRESSION_TRAIT(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define TRANSFORM_TYPE_TRAIT_DEF(K, Spelling)
\
+ case tok::kw___##Spelling:
\
+return true;
+
+ switch (Tok.getKind()) {
+ default:
+return false;
+#include "clang/Basic/TokenKinds.def"
+ }
+}
+
/// ExpandBuiltinMacro - If an identifier token is read that is to be expanded
/// as a builtin macro, handle it and return the next token as 'Tok'.
void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
@@ -1798,25 +1826,11 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
getTargetInfo().getTargetOpts().FeatureMap);
}
return true;
-} else if (II->getTokenID() != tok::identifier ||
- II->hasRevertedTokenIDToIdentifier()) {
- // Treat all keywords that introduce a custom syntax of the form
- //
- // '__some_keyword' '(' [...] ')'
- //
- // as being "builtin functions", even if the syntax isn't a valid
- // function call (for example, because the builtin takes a type
- // argument).
- if (II->getName().starts_with("__builtin_") ||
- II->getName().starts_with("__is_") ||
- II->getName().starts_with("__has_"))
-return true;
- return llvm::StringSwitch(II->getName())
- .Case("__array_rank", true)
- .Case("__array_extent", true)
-#define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) .Case("__" #Trait, true)
-#include "clang/Basic/TransformTypeTraits.def"
- .Default(false);
+} else if (IsBuiltinTrait(Tok)) {
+ return true;
+} else if (II->getTokenID() != tok::identifier &&
+ II->getName().starts_with("__builtin_")) {
+ return true;
} else {
return llvm::StringSwitch(II->getName())
// Report builtin templates as being builtins.
diff --git a/clang/test/Preprocessor/feature_tests.cpp
b/clang/test/Preprocessor/fe
[llvm-branch-commits] [llvm] release/19.x: [x86] combineMUL - when looking for a vector multiply by splat constant, ensure we're only accepting ConstantInt splat scalars. (PR #111246)
github-actions[bot] wrote: @RKSimon (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/111246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Clang] Improve type traits recognition in `__has_builtin` (#111516) (PR #111660)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/111660 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Clang] Improve type traits recognition in `__has_builtin` (#111516) (PR #111660)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/111660
>From dedbdfb70daf06fc07bb4dfbec1d18af8fcef28f Mon Sep 17 00:00:00 2001
From: cor3ntin
Date: Tue, 8 Oct 2024 23:03:32 +0200
Subject: [PATCH] [Clang] Improve type traits recognition in `__has_builtin`
(#111516)
`__has_builtin` was relying on reversible identifiers and string
matching to recognize builtin-type traits, leading to some newer type
traits not being recognized.
Fixes #111477
---
clang/include/clang/Basic/TokenKinds.def | 5 ++-
clang/lib/Lex/PPMacroExpansion.cpp| 52 ++-
clang/test/Preprocessor/feature_tests.cpp | 6 ++-
3 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/clang/include/clang/Basic/TokenKinds.def
b/clang/include/clang/Basic/TokenKinds.def
index 8c54661e65cf46..0526fbf51bd91a 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -64,6 +64,10 @@
#ifndef EXPRESSION_TRAIT
#define EXPRESSION_TRAIT(I,E,K) KEYWORD(I,K)
#endif
+#ifndef TRANSFORM_TYPE_TRAIT_DEF
+#define TRANSFORM_TYPE_TRAIT_DEF(K, Trait) KEYWORD(__##Trait, KEYCXX)
+#endif
+
#ifndef ALIAS
#define ALIAS(X,Y,Z)
#endif
@@ -534,7 +538,6 @@ TYPE_TRAIT_1(__has_unique_object_representations,
TYPE_TRAIT_2(__is_layout_compatible, IsLayoutCompatible, KEYCXX)
TYPE_TRAIT_2(__is_pointer_interconvertible_base_of,
IsPointerInterconvertibleBaseOf, KEYCXX)
-#define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) KEYWORD(__##Trait, KEYCXX)
#include "clang/Basic/TransformTypeTraits.def"
// Clang-only C++ Type Traits
diff --git a/clang/lib/Lex/PPMacroExpansion.cpp
b/clang/lib/Lex/PPMacroExpansion.cpp
index 3913ff08c2eb55..fb88ec2bf603fe 100644
--- a/clang/lib/Lex/PPMacroExpansion.cpp
+++ b/clang/lib/Lex/PPMacroExpansion.cpp
@@ -1602,6 +1602,34 @@ static bool isTargetVariantEnvironment(const TargetInfo
&TI,
return false;
}
+static bool IsBuiltinTrait(Token &Tok) {
+
+#define TYPE_TRAIT_1(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define TYPE_TRAIT_2(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define TYPE_TRAIT_N(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define ARRAY_TYPE_TRAIT(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define EXPRESSION_TRAIT(Spelling, Name, Key)
\
+ case tok::kw_##Spelling:
\
+return true;
+#define TRANSFORM_TYPE_TRAIT_DEF(K, Spelling)
\
+ case tok::kw___##Spelling:
\
+return true;
+
+ switch (Tok.getKind()) {
+ default:
+return false;
+#include "clang/Basic/TokenKinds.def"
+ }
+}
+
/// ExpandBuiltinMacro - If an identifier token is read that is to be expanded
/// as a builtin macro, handle it and return the next token as 'Tok'.
void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
@@ -1798,25 +1826,11 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
getTargetInfo().getTargetOpts().FeatureMap);
}
return true;
-} else if (II->getTokenID() != tok::identifier ||
- II->hasRevertedTokenIDToIdentifier()) {
- // Treat all keywords that introduce a custom syntax of the form
- //
- // '__some_keyword' '(' [...] ')'
- //
- // as being "builtin functions", even if the syntax isn't a valid
- // function call (for example, because the builtin takes a type
- // argument).
- if (II->getName().starts_with("__builtin_") ||
- II->getName().starts_with("__is_") ||
- II->getName().starts_with("__has_"))
-return true;
- return llvm::StringSwitch(II->getName())
- .Case("__array_rank", true)
- .Case("__array_extent", true)
-#define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) .Case("__" #Trait, true)
-#include "clang/Basic/TransformTypeTraits.def"
- .Default(false);
+} else if (IsBuiltinTrait(Tok)) {
+ return true;
+} else if (II->getTokenID() != tok::identifier &&
+ II->getName().starts_with("__builtin_")) {
+ return true;
} else {
return llvm::StringSwitch(II->getName())
// Report builtin templates as being builtins.
diff --git a/clang/test/Preprocessor/feature_tests.cpp
b/clang/test/Preprocessor/feature_tests.cpp
index 00421d74e6282a..13e2a9a261b667 100644
--- a/clang/test/Preprocessor/feature_test
[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/111796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Remove SHA2 interceptions for NetBSD/FreeBSD. (#110246) (PR #111954)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/111954
>From 16c2aae4f6163c1eb7321afd1cd3cdb781fe1727 Mon Sep 17 00:00:00 2001
From: David CARLIER
Date: Wed, 9 Oct 2024 05:47:00 +0100
Subject: [PATCH] [compiler-rt] Remove SHA2 interceptions for NetBSD/FreeBSD.
(#110246)
To Fix #110215
Interceptors introduced with 18a7ebda99044473fdbce6376993714ff54e6690
(cherry picked from commit d0b9c2c5647656738cda3fb670aa5d3b3a69d784)
---
.../sanitizer_common_interceptors.inc | 180 ---
.../sanitizer_platform_interceptors.h | 2 -
.../TestCases/FreeBSD/md5.cpp | 119 --
.../TestCases/FreeBSD/sha2.cpp| 214 --
.../sanitizer_common/TestCases/NetBSD/md5.cpp | 114 --
.../TestCases/NetBSD/sha2.cpp | 206 -
6 files changed, 835 deletions(-)
delete mode 100644 compiler-rt/test/sanitizer_common/TestCases/FreeBSD/md5.cpp
delete mode 100644 compiler-rt/test/sanitizer_common/TestCases/FreeBSD/sha2.cpp
delete mode 100644 compiler-rt/test/sanitizer_common/TestCases/NetBSD/md5.cpp
delete mode 100644 compiler-rt/test/sanitizer_common/TestCases/NetBSD/sha2.cpp
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
index 49c9dcbef358ff..7a7af7936af315 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
@@ -8823,83 +8823,6 @@ INTERCEPTOR(char *, RMD160Data, u8 *data, SIZE_T len,
char *buf) {
#define INIT_RMD160
#endif
-#if SANITIZER_INTERCEPT_MD5
-INTERCEPTOR(void, MD5Init, void *context) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Init, context);
- REAL(MD5Init)(context);
- if (context)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, context, MD5_CTX_sz);
-}
-
-INTERCEPTOR(void, MD5Update, void *context, const unsigned char *data,
-unsigned int len) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Update, context, data, len);
- if (data && len > 0)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, data, len);
- if (context)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, context, MD5_CTX_sz);
- REAL(MD5Update)(context, data, len);
- if (context)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, context, MD5_CTX_sz);
-}
-
-INTERCEPTOR(void, MD5Final, unsigned char digest[16], void *context) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Final, digest, context);
- if (context)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, context, MD5_CTX_sz);
- REAL(MD5Final)(digest, context);
- if (digest)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, digest, sizeof(unsigned char) * 16);
-}
-
-INTERCEPTOR(char *, MD5End, void *context, char *buf) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5End, context, buf);
- if (context)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, context, MD5_CTX_sz);
- char *ret = REAL(MD5End)(context, buf);
- if (ret)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, ret, MD5_return_length);
- return ret;
-}
-
-INTERCEPTOR(char *, MD5File, const char *filename, char *buf) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5File, filename, buf);
- if (filename)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, filename, internal_strlen(filename) +
1);
- char *ret = REAL(MD5File)(filename, buf);
- if (ret)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, ret, MD5_return_length);
- return ret;
-}
-
-INTERCEPTOR(char *, MD5Data, const unsigned char *data, unsigned int len,
-char *buf) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Data, data, len, buf);
- if (data && len > 0)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, data, len);
- char *ret = REAL(MD5Data)(data, len, buf);
- if (ret)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, ret, MD5_return_length);
- return ret;
-}
-
-#define INIT_MD5
\
- COMMON_INTERCEPT_FUNCTION(MD5Init);
\
- COMMON_INTERCEPT_FUNCTION(MD5Update);
\
- COMMON_INTERCEPT_FUNCTION(MD5Final);
\
- COMMON_INTERCEPT_FUNCTION(MD5End);
\
- COMMON_INTERCEPT_FUNCTION(MD5File);
\
- COMMON_INTERCEPT_FUNCTION(MD5Data)
-#else
-#define INIT_MD5
-#endif
-
#if SANITIZER_INTERCEPT_FSEEK
INTERCEPTOR(int, fseek, __sanitizer_FILE *stream, long int offset, int whence)
{
void *ctx;
@@ -9030,107 +8953,6 @@ INTERCEPTOR(char *, MD2Data, const unsigned char *data,
unsigned int len,
#define INIT_MD2
#endif
-#if SANITIZER_INTERCEPT_SHA2
-#define SHA2_INTERCEPTORS(LEN, SHA2_STATE_T) \
- INTERCEPTOR(void, SHA##LEN##_Init, void *context) { \
-void *ctx; \
-COMMON_INTERCEPTOR_ENTER(ctx, SHA##LEN##_Init, context); \
-REAL(SHA##LEN##_Init)(context); \
-if (context) \
- COMMON_INTERCEPTOR_WRITE
[llvm-branch-commits] [compiler-rt] 16c2aae - [compiler-rt] Remove SHA2 interceptions for NetBSD/FreeBSD. (#110246)
Author: David CARLIER
Date: 2024-10-15T08:54:46+02:00
New Revision: 16c2aae4f6163c1eb7321afd1cd3cdb781fe1727
URL:
https://github.com/llvm/llvm-project/commit/16c2aae4f6163c1eb7321afd1cd3cdb781fe1727
DIFF:
https://github.com/llvm/llvm-project/commit/16c2aae4f6163c1eb7321afd1cd3cdb781fe1727.diff
LOG: [compiler-rt] Remove SHA2 interceptions for NetBSD/FreeBSD. (#110246)
To Fix #110215
Interceptors introduced with 18a7ebda99044473fdbce6376993714ff54e6690
(cherry picked from commit d0b9c2c5647656738cda3fb670aa5d3b3a69d784)
Added:
Modified:
compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
Removed:
compiler-rt/test/sanitizer_common/TestCases/FreeBSD/md5.cpp
compiler-rt/test/sanitizer_common/TestCases/FreeBSD/sha2.cpp
compiler-rt/test/sanitizer_common/TestCases/NetBSD/md5.cpp
compiler-rt/test/sanitizer_common/TestCases/NetBSD/sha2.cpp
diff --git
a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
index 49c9dcbef358ff..7a7af7936af315 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
@@ -8823,83 +8823,6 @@ INTERCEPTOR(char *, RMD160Data, u8 *data, SIZE_T len,
char *buf) {
#define INIT_RMD160
#endif
-#if SANITIZER_INTERCEPT_MD5
-INTERCEPTOR(void, MD5Init, void *context) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Init, context);
- REAL(MD5Init)(context);
- if (context)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, context, MD5_CTX_sz);
-}
-
-INTERCEPTOR(void, MD5Update, void *context, const unsigned char *data,
-unsigned int len) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Update, context, data, len);
- if (data && len > 0)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, data, len);
- if (context)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, context, MD5_CTX_sz);
- REAL(MD5Update)(context, data, len);
- if (context)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, context, MD5_CTX_sz);
-}
-
-INTERCEPTOR(void, MD5Final, unsigned char digest[16], void *context) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Final, digest, context);
- if (context)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, context, MD5_CTX_sz);
- REAL(MD5Final)(digest, context);
- if (digest)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, digest, sizeof(unsigned char) * 16);
-}
-
-INTERCEPTOR(char *, MD5End, void *context, char *buf) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5End, context, buf);
- if (context)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, context, MD5_CTX_sz);
- char *ret = REAL(MD5End)(context, buf);
- if (ret)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, ret, MD5_return_length);
- return ret;
-}
-
-INTERCEPTOR(char *, MD5File, const char *filename, char *buf) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5File, filename, buf);
- if (filename)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, filename, internal_strlen(filename) +
1);
- char *ret = REAL(MD5File)(filename, buf);
- if (ret)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, ret, MD5_return_length);
- return ret;
-}
-
-INTERCEPTOR(char *, MD5Data, const unsigned char *data, unsigned int len,
-char *buf) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, MD5Data, data, len, buf);
- if (data && len > 0)
-COMMON_INTERCEPTOR_READ_RANGE(ctx, data, len);
- char *ret = REAL(MD5Data)(data, len, buf);
- if (ret)
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, ret, MD5_return_length);
- return ret;
-}
-
-#define INIT_MD5
\
- COMMON_INTERCEPT_FUNCTION(MD5Init);
\
- COMMON_INTERCEPT_FUNCTION(MD5Update);
\
- COMMON_INTERCEPT_FUNCTION(MD5Final);
\
- COMMON_INTERCEPT_FUNCTION(MD5End);
\
- COMMON_INTERCEPT_FUNCTION(MD5File);
\
- COMMON_INTERCEPT_FUNCTION(MD5Data)
-#else
-#define INIT_MD5
-#endif
-
#if SANITIZER_INTERCEPT_FSEEK
INTERCEPTOR(int, fseek, __sanitizer_FILE *stream, long int offset, int whence)
{
void *ctx;
@@ -9030,107 +8953,6 @@ INTERCEPTOR(char *, MD2Data, const unsigned char *data,
unsigned int len,
#define INIT_MD2
#endif
-#if SANITIZER_INTERCEPT_SHA2
-#define SHA2_INTERCEPTORS(LEN, SHA2_STATE_T) \
- INTERCEPTOR(void, SHA##LEN##_Init, void *context) { \
-void *ctx; \
-COMMON_INTERCEPTOR_ENTER(ctx, SHA##LEN##_Init, context); \
-REAL(SHA##LEN##_Init)(context); \
-if (context) \
- COMMON_INTERCEPTOR_WRITE_RANGE(ctx, context, SHA##LEN##_CTX_sz); \
- } \
- INTERCEPTOR(void, SHA##LEN##_Update, void *context, \
- const u8 *data, SIZE_T len) { \
-v
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Remove SHA2 interceptions for NetBSD/FreeBSD. (#110246) (PR #111954)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/111954 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [clang-repl] [codegen] Reduce the state in TBAA. NFC for static compilation. (#98138) (PR #111953)
tru wrote: @nikic Are you worried about this one at all? It seems fine from Eli's comments and the abi checker. https://github.com/llvm/llvm-project/pull/111953 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)
github-actions[bot] wrote: @davemgreen (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/111796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Backport "[InstCombine] Drop range attributes in `foldIsPowerOf2` (#111946)" (PR #111984)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/111984 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 96839b6 - [clang-format] Handle template closer followed by braces (#110971)
Author: Owen Pan
Date: 2024-10-15T08:55:16+02:00
New Revision: 96839b6f16a063c3f15cac5d9b6a0e5912f6341e
URL:
https://github.com/llvm/llvm-project/commit/96839b6f16a063c3f15cac5d9b6a0e5912f6341e
DIFF:
https://github.com/llvm/llvm-project/commit/96839b6f16a063c3f15cac5d9b6a0e5912f6341e.diff
LOG: [clang-format] Handle template closer followed by braces (#110971)
Fixes #110968.
(cherry picked from commit e5b05a51b8151cc7788bbdea4d491e5ccfceedea)
Added:
Modified:
clang/lib/Format/UnwrappedLineParser.cpp
clang/unittests/Format/TokenAnnotatorTest.cpp
Removed:
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index f7b3561f6e0335..631c7c62baac18 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2131,6 +2131,11 @@ void UnwrappedLineParser::parseStructuralElement(
return;
}
break;
+case tok::greater:
+ nextToken();
+ if (FormatTok->is(tok::l_brace))
+FormatTok->Previous->setFinalizedType(TT_TemplateCloser);
+ break;
default:
nextToken();
break;
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp
b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 2f09b380a87134..6f3ef3b646c619 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -3399,6 +3399,11 @@ TEST_F(TokenAnnotatorTest, TemplateInstantiation) {
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::less, TT_TemplateOpener);
EXPECT_TOKEN(Tokens[6], tok::greater, TT_TemplateCloser);
+
+ Tokens = annotate("return std::conditional_t{};");
+ ASSERT_EQ(Tokens.size(), 21u) << Tokens;
+ EXPECT_TOKEN(Tokens[4], tok::less, TT_TemplateOpener);
+ EXPECT_TOKEN(Tokens[16], tok::greater, TT_TemplateCloser);
}
} // namespace
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[llvm-branch-commits] [llvm] 35bd5ff - [InstCombine] Drop range attributes in `foldIsPowerOf2` (#111946)
Author: Yingwei Zheng
Date: 2024-10-15T08:55:36+02:00
New Revision: 35bd5ff4ca7095baeb1f157491e81e3277a0ae34
URL:
https://github.com/llvm/llvm-project/commit/35bd5ff4ca7095baeb1f157491e81e3277a0ae34
DIFF:
https://github.com/llvm/llvm-project/commit/35bd5ff4ca7095baeb1f157491e81e3277a0ae34.diff
LOG: [InstCombine] Drop range attributes in `foldIsPowerOf2` (#111946)
Fixes https://github.com/llvm/llvm-project/issues/111934.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
llvm/test/Transforms/InstCombine/ispow2.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index f9caa4da44931a..3222e8298c3f0b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -926,9 +926,11 @@ static Value *foldIsPowerOf2OrZero(ICmpInst *Cmp0,
ICmpInst *Cmp1, bool IsAnd,
}
/// Reduce a pair of compares that check if a value has exactly 1 bit set.
-/// Also used for logical and/or, must be poison safe.
+/// Also used for logical and/or, must be poison safe if range attributes are
+/// dropped.
static Value *foldIsPowerOf2(ICmpInst *Cmp0, ICmpInst *Cmp1, bool JoinedByAnd,
- InstCombiner::BuilderTy &Builder) {
+ InstCombiner::BuilderTy &Builder,
+ InstCombinerImpl &IC) {
// Handle 'and' / 'or' commutation: make the equality check the first
operand.
if (JoinedByAnd && Cmp1->getPredicate() == ICmpInst::ICMP_NE)
std::swap(Cmp0, Cmp1);
@@ -942,7 +944,10 @@ static Value *foldIsPowerOf2(ICmpInst *Cmp0, ICmpInst
*Cmp1, bool JoinedByAnd,
match(Cmp1, m_ICmp(Pred1, m_Intrinsic(m_Specific(X)),
m_SpecificInt(2))) &&
Pred0 == ICmpInst::ICMP_NE && Pred1 == ICmpInst::ICMP_ULT) {
-Value *CtPop = Cmp1->getOperand(0);
+auto *CtPop = cast(Cmp1->getOperand(0));
+// Drop range attributes and re-infer them in the next iteration.
+CtPop->dropPoisonGeneratingAnnotations();
+IC.addToWorklist(CtPop);
return Builder.CreateICmpEQ(CtPop, ConstantInt::get(CtPop->getType(), 1));
}
// (X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1
@@ -950,7 +955,10 @@ static Value *foldIsPowerOf2(ICmpInst *Cmp0, ICmpInst
*Cmp1, bool JoinedByAnd,
match(Cmp1, m_ICmp(Pred1, m_Intrinsic(m_Specific(X)),
m_SpecificInt(1))) &&
Pred0 == ICmpInst::ICMP_EQ && Pred1 == ICmpInst::ICMP_UGT) {
-Value *CtPop = Cmp1->getOperand(0);
+auto *CtPop = cast(Cmp1->getOperand(0));
+// Drop range attributes and re-infer them in the next iteration.
+CtPop->dropPoisonGeneratingAnnotations();
+IC.addToWorklist(CtPop);
return Builder.CreateICmpNE(CtPop, ConstantInt::get(CtPop->getType(), 1));
}
return nullptr;
@@ -3347,7 +3355,7 @@ Value *InstCombinerImpl::foldAndOrOfICmps(ICmpInst *LHS,
ICmpInst *RHS,
if (Value *V = foldSignedTruncationCheck(LHS, RHS, I, Builder))
return V;
- if (Value *V = foldIsPowerOf2(LHS, RHS, IsAnd, Builder))
+ if (Value *V = foldIsPowerOf2(LHS, RHS, IsAnd, Builder, *this))
return V;
if (Value *V = foldPowerOf2AndShiftedMask(LHS, RHS, IsAnd, Builder))
diff --git a/llvm/test/Transforms/InstCombine/ispow2.ll
b/llvm/test/Transforms/InstCombine/ispow2.ll
index a143b1347ccee5..216ccc5c77257b 100644
--- a/llvm/test/Transforms/InstCombine/ispow2.ll
+++ b/llvm/test/Transforms/InstCombine/ispow2.ll
@@ -1522,3 +1522,35 @@ define <2 x i1>
@not_pow2_or_z_known_bits_fail_wrong_cmp(<2 x i32> %xin) {
%r = icmp ugt <2 x i32> %cnt,
ret <2 x i1> %r
}
+
+; Make sure that range attributes on return values are dropped after merging
these two icmps
+
+define i1 @has_single_bit(i32 %x) {
+; CHECK-LABEL: @has_single_bit(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[POPCNT:%.*]] = call range(i32 0, 33) i32
@llvm.ctpop.i32(i32 [[X:%.*]])
+; CHECK-NEXT:[[SEL:%.*]] = icmp eq i32 [[POPCNT]], 1
+; CHECK-NEXT:ret i1 [[SEL]]
+;
+entry:
+ %cmp1 = icmp ne i32 %x, 0
+ %popcnt = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)
+ %cmp2 = icmp ult i32 %popcnt, 2
+ %sel = select i1 %cmp1, i1 %cmp2, i1 false
+ ret i1 %sel
+}
+
+define i1 @has_single_bit_inv(i32 %x) {
+; CHECK-LABEL: @has_single_bit_inv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[POPCNT:%.*]] = call range(i32 0, 33) i32
@llvm.ctpop.i32(i32 [[X:%.*]])
+; CHECK-NEXT:[[SEL:%.*]] = icmp ne i32 [[POPCNT]], 1
+; CHECK-NEXT:ret i1 [[SEL]]
+;
+entry:
+ %cmp1 = icmp eq i32 %x, 0
+ %popcnt = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)
+ %cmp2 = icmp ugt i32 %popcnt, 1
+ %sel = select i1 %cmp1, i1 true, i1 %cmp2
+ ret i1 %sel
+}
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[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Remove SHA2 interceptions for NetBSD/FreeBSD. (#110246) (PR #111954)
github-actions[bot] wrote: @tru (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/111954 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [clang-format] Handle template closer followed by braces (#110971) (PR #111958)
https://github.com/tru closed https://github.com/llvm/llvm-project/pull/111958 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Backport "[InstCombine] Drop range attributes in `foldIsPowerOf2` (#111946)" (PR #111984)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/111984
>From 35bd5ff4ca7095baeb1f157491e81e3277a0ae34 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 11 Oct 2024 18:19:21 +0800
Subject: [PATCH] [InstCombine] Drop range attributes in `foldIsPowerOf2`
(#111946)
Fixes https://github.com/llvm/llvm-project/issues/111934.
---
.../InstCombine/InstCombineAndOrXor.cpp | 18 ---
llvm/test/Transforms/InstCombine/ispow2.ll| 32 +++
2 files changed, 45 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index f9caa4da44931a..3222e8298c3f0b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -926,9 +926,11 @@ static Value *foldIsPowerOf2OrZero(ICmpInst *Cmp0,
ICmpInst *Cmp1, bool IsAnd,
}
/// Reduce a pair of compares that check if a value has exactly 1 bit set.
-/// Also used for logical and/or, must be poison safe.
+/// Also used for logical and/or, must be poison safe if range attributes are
+/// dropped.
static Value *foldIsPowerOf2(ICmpInst *Cmp0, ICmpInst *Cmp1, bool JoinedByAnd,
- InstCombiner::BuilderTy &Builder) {
+ InstCombiner::BuilderTy &Builder,
+ InstCombinerImpl &IC) {
// Handle 'and' / 'or' commutation: make the equality check the first
operand.
if (JoinedByAnd && Cmp1->getPredicate() == ICmpInst::ICMP_NE)
std::swap(Cmp0, Cmp1);
@@ -942,7 +944,10 @@ static Value *foldIsPowerOf2(ICmpInst *Cmp0, ICmpInst
*Cmp1, bool JoinedByAnd,
match(Cmp1, m_ICmp(Pred1, m_Intrinsic(m_Specific(X)),
m_SpecificInt(2))) &&
Pred0 == ICmpInst::ICMP_NE && Pred1 == ICmpInst::ICMP_ULT) {
-Value *CtPop = Cmp1->getOperand(0);
+auto *CtPop = cast(Cmp1->getOperand(0));
+// Drop range attributes and re-infer them in the next iteration.
+CtPop->dropPoisonGeneratingAnnotations();
+IC.addToWorklist(CtPop);
return Builder.CreateICmpEQ(CtPop, ConstantInt::get(CtPop->getType(), 1));
}
// (X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1
@@ -950,7 +955,10 @@ static Value *foldIsPowerOf2(ICmpInst *Cmp0, ICmpInst
*Cmp1, bool JoinedByAnd,
match(Cmp1, m_ICmp(Pred1, m_Intrinsic(m_Specific(X)),
m_SpecificInt(1))) &&
Pred0 == ICmpInst::ICMP_EQ && Pred1 == ICmpInst::ICMP_UGT) {
-Value *CtPop = Cmp1->getOperand(0);
+auto *CtPop = cast(Cmp1->getOperand(0));
+// Drop range attributes and re-infer them in the next iteration.
+CtPop->dropPoisonGeneratingAnnotations();
+IC.addToWorklist(CtPop);
return Builder.CreateICmpNE(CtPop, ConstantInt::get(CtPop->getType(), 1));
}
return nullptr;
@@ -3347,7 +3355,7 @@ Value *InstCombinerImpl::foldAndOrOfICmps(ICmpInst *LHS,
ICmpInst *RHS,
if (Value *V = foldSignedTruncationCheck(LHS, RHS, I, Builder))
return V;
- if (Value *V = foldIsPowerOf2(LHS, RHS, IsAnd, Builder))
+ if (Value *V = foldIsPowerOf2(LHS, RHS, IsAnd, Builder, *this))
return V;
if (Value *V = foldPowerOf2AndShiftedMask(LHS, RHS, IsAnd, Builder))
diff --git a/llvm/test/Transforms/InstCombine/ispow2.ll
b/llvm/test/Transforms/InstCombine/ispow2.ll
index a143b1347ccee5..216ccc5c77257b 100644
--- a/llvm/test/Transforms/InstCombine/ispow2.ll
+++ b/llvm/test/Transforms/InstCombine/ispow2.ll
@@ -1522,3 +1522,35 @@ define <2 x i1>
@not_pow2_or_z_known_bits_fail_wrong_cmp(<2 x i32> %xin) {
%r = icmp ugt <2 x i32> %cnt,
ret <2 x i1> %r
}
+
+; Make sure that range attributes on return values are dropped after merging
these two icmps
+
+define i1 @has_single_bit(i32 %x) {
+; CHECK-LABEL: @has_single_bit(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[POPCNT:%.*]] = call range(i32 0, 33) i32
@llvm.ctpop.i32(i32 [[X:%.*]])
+; CHECK-NEXT:[[SEL:%.*]] = icmp eq i32 [[POPCNT]], 1
+; CHECK-NEXT:ret i1 [[SEL]]
+;
+entry:
+ %cmp1 = icmp ne i32 %x, 0
+ %popcnt = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)
+ %cmp2 = icmp ult i32 %popcnt, 2
+ %sel = select i1 %cmp1, i1 %cmp2, i1 false
+ ret i1 %sel
+}
+
+define i1 @has_single_bit_inv(i32 %x) {
+; CHECK-LABEL: @has_single_bit_inv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[POPCNT:%.*]] = call range(i32 0, 33) i32
@llvm.ctpop.i32(i32 [[X:%.*]])
+; CHECK-NEXT:[[SEL:%.*]] = icmp ne i32 [[POPCNT]], 1
+; CHECK-NEXT:ret i1 [[SEL]]
+;
+entry:
+ %cmp1 = icmp eq i32 %x, 0
+ %popcnt = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)
+ %cmp2 = icmp ugt i32 %popcnt, 1
+ %sel = select i1 %cmp1, i1 true, i1 %cmp2
+ ret i1 %sel
+}
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[llvm-branch-commits] [clang] release/19.x: [clang-format] Handle template closer followed by braces (#110971) (PR #111958)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/111958
>From 96839b6f16a063c3f15cac5d9b6a0e5912f6341e Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Fri, 4 Oct 2024 18:18:03 -0700
Subject: [PATCH] [clang-format] Handle template closer followed by braces
(#110971)
Fixes #110968.
(cherry picked from commit e5b05a51b8151cc7788bbdea4d491e5ccfceedea)
---
clang/lib/Format/UnwrappedLineParser.cpp | 5 +
clang/unittests/Format/TokenAnnotatorTest.cpp | 5 +
2 files changed, 10 insertions(+)
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index f7b3561f6e0335..631c7c62baac18 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2131,6 +2131,11 @@ void UnwrappedLineParser::parseStructuralElement(
return;
}
break;
+case tok::greater:
+ nextToken();
+ if (FormatTok->is(tok::l_brace))
+FormatTok->Previous->setFinalizedType(TT_TemplateCloser);
+ break;
default:
nextToken();
break;
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp
b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 2f09b380a87134..6f3ef3b646c619 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -3399,6 +3399,11 @@ TEST_F(TokenAnnotatorTest, TemplateInstantiation) {
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::less, TT_TemplateOpener);
EXPECT_TOKEN(Tokens[6], tok::greater, TT_TemplateCloser);
+
+ Tokens = annotate("return std::conditional_t{};");
+ ASSERT_EQ(Tokens.size(), 21u) << Tokens;
+ EXPECT_TOKEN(Tokens[4], tok::less, TT_TemplateOpener);
+ EXPECT_TOKEN(Tokens[16], tok::greater, TT_TemplateCloser);
}
} // namespace
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[llvm-branch-commits] [clang] release/19.x: [clang-format] Handle template closer followed by braces (#110971) (PR #111958)
github-actions[bot] wrote: @owenca (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/111958 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] release/19.x: [lld][Hexagon] Support predicated-add GOT_16_X mask lookup (#111896) (PR #112040)
https://github.com/tru updated https://github.com/llvm/llvm-project/pull/112040
>From f8cf339563e2f38487de15ce11eddc4ea6c883af Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 11 Oct 2024 14:31:41 -0500
Subject: [PATCH] [lld][Hexagon] Support predicated-add GOT_16_X mask lookup
(#111896)
When encountering an instruction like `if (p0) r0 = add(r0,##bar@GOT)`,
lld would fail with:
```
ld.lld: error: unrecognized instruction for 16_X type: 0x7400C000
```
This issue was encountered while building libreadline with clang 19.1.0.
Fixes: #111876
(cherry picked from commit 77aa8257acbd773c0c430cd962da1bcfbd5ee94b)
---
lld/ELF/Arch/Hexagon.cpp | 20 +---
lld/test/ELF/hexagon-shared.s | 19 +++
2 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp
index abde3cd964917e..56cf96fd177042 100644
--- a/lld/ELF/Arch/Hexagon.cpp
+++ b/lld/ELF/Arch/Hexagon.cpp
@@ -181,11 +181,13 @@ static const InstructionMask r6[] = {
{0xd700, 0x006020e0}, {0xd800, 0x006020e0},
{0xdb00, 0x006020e0}, {0xdf00, 0x006020e0}};
+constexpr uint32_t instParsePacketEnd = 0xc000;
+
static bool isDuplex(uint32_t insn) {
// Duplex forms have a fixed mask and parse bits 15:14 are always
// zero. Non-duplex insns will always have at least one bit set in the
// parse field.
- return (0xC000 & insn) == 0;
+ return (instParsePacketEnd & insn) == 0;
}
static uint32_t findMaskR6(uint32_t insn) {
@@ -216,6 +218,12 @@ static uint32_t findMaskR11(uint32_t insn) {
}
static uint32_t findMaskR16(uint32_t insn) {
+ if (isDuplex(insn))
+return 0x03f0;
+
+ // Clear the end-packet-parse bits:
+ insn = insn & ~instParsePacketEnd;
+
if ((0xff00 & insn) == 0x4800)
return 0x061f20ff;
if ((0xff00 & insn) == 0x4900)
@@ -225,8 +233,14 @@ static uint32_t findMaskR16(uint32_t insn) {
if ((0xff00 & insn) == 0xb000)
return 0x0fe03fe0;
- if (isDuplex(insn))
-return 0x03f0;
+ if ((0xff802000 & insn) == 0x7400)
+return 0x1fe0;
+ if ((0xff802000 & insn) == 0x74002000)
+return 0x1fe0;
+ if ((0xff802000 & insn) == 0x7480)
+return 0x1fe0;
+ if ((0xff802000 & insn) == 0x74802000)
+return 0x1fe0;
for (InstructionMask i : r6)
if ((0xff00 & insn) == i.cmpMask)
diff --git a/lld/test/ELF/hexagon-shared.s b/lld/test/ELF/hexagon-shared.s
index 747822039e839a..01f72865847056 100644
--- a/lld/test/ELF/hexagon-shared.s
+++ b/lld/test/ELF/hexagon-shared.s
@@ -42,6 +42,13 @@ r0 = add(r1,##bar@GOT)
{ r0 = add(r0,##bar@GOT)
memw(r0) = r2 }
+# R_HEX_GOT_16_X, pred add
+if (p0) r0 = add(r0,##bar@GOT)
+if (!p0) r0 = add(r0,##bar@GOT)
+{ p0 = cmp.gtu(r0, r1)
+ if (p0.new) r0 = add(r0,##bar@GOT) }
+{ p0 = cmp.gtu(r0, r1)
+ if (!p0.new) r0 = add(r0,##bar@GOT) }
# foo is local so no plt will be generated
foo:
@@ -78,12 +85,16 @@ pvar:
# PLT-NEXT: r28 = memw(r14+#0) }
# PLT-NEXT: jumpr r28 }
-# TEXT: 8c 00 01 00 0001008c
-# TEXT: { call 0x102d0 }
-# TEXT: if (p0) jump:nt 0x102d0
-# TEXT: r0 = #0 ; jump 0x102d0
+# TEXT: bc 00 01 00 000100bc
+# TEXT: { call 0x10300 }
+# TEXT: if (p0) jump:nt 0x10300
+# TEXT: r0 = #0 ; jump 0x10300
# TEXT: r0 = add(r1,##-65548)
# TEXT: r0 = add(r0,##-65548); memw(r0+#0) = r2 }
+# TEXT: if (p0) r0 = add(r0,##-65548)
+# TEXT: if (!p0) r0 = add(r0,##-65548)
+# TEXT: if (p0.new) r0 = add(r0,##-65548)
+# TEXT: if (!p0.new) r0 = add(r0,##-65548)
# GOT: .got:
# GOT: 00 00 00 00
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[llvm-branch-commits] [llvm] Backport "[InstCombine] Drop range attributes in `foldIsPowerOf2` (#111946)" (PR #111984)
github-actions[bot] wrote: @dtcxzyw (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/111984 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [TargetTransformInfo] Remove `getFlatAddressSpace` (PR #108787)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/108787
>From 180bf1360412c25c94407dcfe0bbde1b1097b804 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 15 Sep 2024 23:06:14 -0400
Subject: [PATCH] [TargetTransformInfo] Remove `getFlatAddressSpace`
This has been moved to `DataLayout`.
---
.../llvm/Analysis/TargetTransformInfo.h | 21 ---
.../llvm/Analysis/TargetTransformInfoImpl.h | 2 --
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 5 -
llvm/lib/Analysis/TargetTransformInfo.cpp | 4
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 8 ---
.../Target/NVPTX/NVPTXTargetTransformInfo.h | 4
.../Transforms/Scalar/InferAddressSpaces.cpp | 5 +++--
.../AMDGPU/noop-ptrint-pair.ll| 2 +-
.../old-pass-regressions-inseltpoison.ll | 2 +-
.../AMDGPU/old-pass-regressions.ll| 2 +-
.../InferAddressSpaces/AMDGPU/ptrmask.ll | 2 +-
11 files changed, 7 insertions(+), 50 deletions(-)
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h
b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 0459941fe05cdc..6b5fd0c0fb7c60 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -454,24 +454,6 @@ class TargetTransformInfo {
/// Return false if a \p AS0 address cannot possibly alias a \p AS1 address.
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const;
- /// Returns the address space ID for a target's 'flat' address space. Note
- /// this is not necessarily the same as addrspace(0), which LLVM sometimes
- /// refers to as the generic address space. The flat address space is a
- /// generic address space that can be used access multiple segments of memory
- /// with different address spaces. Access of a memory location through a
- /// pointer with this address space is expected to be legal but slower
- /// compared to the same memory location accessed through a pointer with a
- /// different address space.
- //
- /// This is for targets with different pointer representations which can
- /// be converted with the addrspacecast instruction. If a pointer is
converted
- /// to this address space, optimizations should attempt to replace the access
- /// with the source address space.
- ///
- /// \returns ~0u if the target does not have such a flat address space to
- /// optimize away.
- unsigned getFlatAddressSpace() const;
-
/// Return any intrinsic address operand indexes which may be rewritten if
/// they use a flat address space pointer.
///
@@ -1870,7 +1852,6 @@ class TargetTransformInfo::Concept {
virtual bool isAlwaysUniform(const Value *V) = 0;
virtual bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0;
virtual bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const = 0;
- virtual unsigned getFlatAddressSpace() = 0;
virtual bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes,
Intrinsic::ID IID) const = 0;
virtual bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0;
@@ -2312,8 +2293,6 @@ class TargetTransformInfo::Model final : public
TargetTransformInfo::Concept {
return Impl.addrspacesMayAlias(AS0, AS1);
}
- unsigned getFlatAddressSpace() override { return Impl.getFlatAddressSpace();
}
-
bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes,
Intrinsic::ID IID) const override {
return Impl.collectFlatAddressOperands(OpIndexes, IID);
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index dbdfb4d8cdfa32..23a69f14c231cb 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -120,8 +120,6 @@ class TargetTransformInfoImplBase {
return true;
}
- unsigned getFlatAddressSpace() const { return -1; }
-
bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes,
Intrinsic::ID IID) const {
return false;
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 57d1fa33c8482c..19f1ed2808e940 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -292,11 +292,6 @@ class BasicTTIImplBase : public
TargetTransformInfoImplCRTPBase {
return true;
}
- unsigned getFlatAddressSpace() {
-// Return an invalid address space.
-return -1;
- }
-
bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes,
Intrinsic::ID IID) const {
return false;
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp
b/llvm/lib/Analysis/TargetTransformInfo.cpp
index a47462b61e03b2..1c1f42d8f62e0d 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -313,10 +31
[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
https://github.com/efriedma-quic approved this pull request. LGTM. Obvious typo, obvious fix, very low chance of impacting non-arm64ec targets. https://github.com/llvm/llvm-project/pull/112258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Headers] [ARM64EC] Fix extra tokens inside intrin0.h preprocessor directive (#112066) (PR #112258)
mstorsjo wrote: > @efriedma-quic What do you think about merging this PR to the release branch? The bot didn't ask me, but it does look good to me. https://github.com/llvm/llvm-project/pull/112258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] b106c5e - Revert "[flang][cuda] Add cuf.register_kernel operation (#112268)"
Author: Valentin Clement (バレンタイン クレメン)
Date: 2024-10-14T21:06:42-07:00
New Revision: b106c5edf89c5306de07766078f8449a28a39fc3
URL:
https://github.com/llvm/llvm-project/commit/b106c5edf89c5306de07766078f8449a28a39fc3
DIFF:
https://github.com/llvm/llvm-project/commit/b106c5edf89c5306de07766078f8449a28a39fc3.diff
LOG: Revert "[flang][cuda] Add cuf.register_kernel operation (#112268)"
This reverts commit cbe76a2ac3547258076cc93e8cbc42cdc6219d06.
Added:
Modified:
flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
flang/test/Fir/cuf-invalid.fir
flang/tools/fir-opt/fir-opt.cpp
Removed:
flang/test/Fir/CUDA/cuda-register-func.fir
diff --git a/flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
b/flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
index 98d1ef529738c7..f643674f1d5d6b 100644
--- a/flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
+++ b/flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
@@ -288,23 +288,4 @@ def cuf_KernelOp : cuf_Op<"kernel",
[AttrSizedOperandSegments,
let hasVerifier = 1;
}
-def cuf_RegisterKernelOp : cuf_Op<"register_kernel", []> {
- let summary = "Register a CUDA kernel";
-
- let arguments = (ins
-SymbolRefAttr:$name
- );
-
- let assemblyFormat = [{
-$name attr-dict
- }];
-
- let hasVerifier = 1;
-
- let extraClassDeclaration = [{
-mlir::StringAttr getKernelName();
-mlir::StringAttr getKernelModuleName();
- }];
-}
-
#endif // FORTRAN_DIALECT_CUF_CUF_OPS
diff --git a/flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
b/flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
index 9e3bbd1f9cbee9..7fb2dcf4af115c 100644
--- a/flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
+++ b/flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
@@ -15,7 +15,6 @@
#include "flang/Optimizer/Dialect/CUF/CUFDialect.h"
#include "flang/Optimizer/Dialect/FIRAttr.h"
#include "flang/Optimizer/Dialect/FIRType.h"
-#include "mlir/Dialect/GPU/IR/GPUDialect.h"
#include "mlir/IR/Attributes.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/BuiltinOps.h"
@@ -254,42 +253,6 @@ llvm::LogicalResult cuf::KernelOp::verify() {
return mlir::success();
}
-//===--===//
-// RegisterKernelOp
-//===--===//
-
-mlir::StringAttr cuf::RegisterKernelOp::getKernelModuleName() {
- return getName().getRootReference();
-}
-
-mlir::StringAttr cuf::RegisterKernelOp::getKernelName() {
- return getName().getLeafReference();
-}
-
-mlir::LogicalResult cuf::RegisterKernelOp::verify() {
- if (getKernelName() == getKernelModuleName())
-return emitOpError("expect a module and a kernel name");
-
- auto mod = getOperation()->getParentOfType();
- if (!mod)
-return emitOpError("expect to be in a module");
-
- mlir::SymbolTable symTab(mod);
- auto gpuMod = symTab.lookup(getKernelModuleName());
- if (!gpuMod)
-return emitOpError("gpu module not found");
-
- mlir::SymbolTable gpuSymTab(gpuMod);
- auto func = gpuSymTab.lookup(getKernelName());
- if (!func)
-return emitOpError("device function not found");
-
- if (!func.isKernel())
-return emitOpError("only kernel gpu.func can be registered");
-
- return mlir::success();
-}
-
// Tablegen operators
#define GET_OP_CLASSES
diff --git a/flang/test/Fir/CUDA/cuda-register-func.fir
b/flang/test/Fir/CUDA/cuda-register-func.fir
deleted file mode 100644
index a428f68eb3bf42..00
--- a/flang/test/Fir/CUDA/cuda-register-func.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-// RUN: fir-opt %s | FileCheck %s
-
-module attributes {gpu.container_module} {
- gpu.module @cuda_device_mod {
-gpu.func @_QPsub_device1() kernel {
- gpu.return
-}
-gpu.func @_QPsub_device2(%arg0: !fir.ref) kernel {
- gpu.return
-}
- }
- llvm.func internal @__cudaFortranConstructor() {
-cuf.register_kernel @cuda_device_mod::@_QPsub_device1
-cuf.register_kernel @cuda_device_mod::@_QPsub_device2
-llvm.return
- }
-}
-
-// CHECK: cuf.register_kernel @cuda_device_mod::@_QPsub_device1
-// CHECK: cuf.register_kernel @cuda_device_mod::@_QPsub_device2
diff --git a/flang/test/Fir/cuf-invalid.fir b/flang/test/Fir/cuf-invalid.fir
index a5747b8ee4a3b3..e9aeaa281e2a85 100644
--- a/flang/test/Fir/cuf-invalid.fir
+++ b/flang/test/Fir/cuf-invalid.fir
@@ -125,53 +125,3 @@ func.func @_QPsub1(%arg0: !fir.ref>
{cuf.data_attr = #cuf.cuda
cuf.data_transfer %20#0 to %11#0, %19 : !fir.shape<1> {transfer_kind =
#cuf.cuda_transfer} : !fir.box>,
!fir.box>
return
}
-
-// -
-
-module attributes {gpu.container_module} {
- gpu.module @cuda_device_mod {
-gpu.func @_QPsub_device1() {
- gpu.return
-}
- }
- llvm.func internal @__cudaFortranConstructor() {
-// expected-error@+1{{'cuf.register_kernel' op only kernel gpu.func can be
registered}}
-cu
[llvm-branch-commits] [clang] release/19.x: [Clang] Instantiate Typedefs referenced by type alias deduction guides (#111804) (PR #112293)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/112293
Backport 0bc02b999a
Requested by: @zyn0217
>From 2717eeb2584005e08bc0b2c1b77954ff156a5bab Mon Sep 17 00:00:00 2001
From: Younan Zhang
Date: Fri, 11 Oct 2024 10:31:27 +0800
Subject: [PATCH] [Clang] Instantiate Typedefs referenced by type alias
deduction guides (#111804)
TypedefNameDecl referenced by a synthesized CTAD guide for type aliases
was not transformed previously, resulting in a substitution failure in
BuildDeductionGuideForTypeAlias() when substituting into the
right-hand-side deduction guide.
This patch fixes it in the way we have been doing since
https://reviews.llvm.org/D80743. We transform all the function
parameters, parenting referenced TypedefNameDecls with the
CXXDeductionGuideDecl. Then we instantiate these declarations in
FindInstantiatedDecl() as we build up the eventual deduction guide,
using the mechanism introduced in D80743
Fixes #111508
(cherry picked from commit 0bc02b999a9686ba240b7a68d3f1cbbf037d2170)
---
clang/lib/Sema/SemaTemplateDeductionGuide.cpp | 21 ---
clang/test/SemaCXX/cxx20-ctad-type-alias.cpp | 13
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
b/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
index 0602d07c6b9b0d..1bf82b31def977 100644
--- a/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
+++ b/clang/lib/Sema/SemaTemplateDeductionGuide.cpp
@@ -69,8 +69,8 @@ class ExtractTypeForDeductionGuide
ExtractTypeForDeductionGuide(
Sema &SemaRef,
llvm::SmallVectorImpl &MaterializedTypedefs,
- ClassTemplateDecl *NestedPattern,
- const MultiLevelTemplateArgumentList *OuterInstantiationArgs)
+ ClassTemplateDecl *NestedPattern = nullptr,
+ const MultiLevelTemplateArgumentList *OuterInstantiationArgs = nullptr)
: Base(SemaRef), MaterializedTypedefs(MaterializedTypedefs),
NestedPattern(NestedPattern),
OuterInstantiationArgs(OuterInstantiationArgs) {
@@ -1263,10 +1263,25 @@ FunctionTemplateDecl
*DeclareAggregateDeductionGuideForTypeAlias(
getRHSTemplateDeclAndArgs(SemaRef, AliasTemplate).first;
if (!RHSTemplate)
return nullptr;
+
+ llvm::SmallVector TypedefDecls;
+ llvm::SmallVector NewParamTypes;
+ ExtractTypeForDeductionGuide TypeAliasTransformer(SemaRef, TypedefDecls);
+ for (QualType P : ParamTypes) {
+QualType Type = TypeAliasTransformer.TransformType(P);
+if (Type.isNull())
+ return nullptr;
+NewParamTypes.push_back(Type);
+ }
+
auto *RHSDeductionGuide = SemaRef.DeclareAggregateDeductionGuideFromInitList(
- RHSTemplate, ParamTypes, Loc);
+ RHSTemplate, NewParamTypes, Loc);
if (!RHSDeductionGuide)
return nullptr;
+
+ for (TypedefNameDecl *TD : TypedefDecls)
+TD->setDeclContext(RHSDeductionGuide->getTemplatedDecl());
+
return BuildDeductionGuideForTypeAlias(SemaRef, AliasTemplate,
RHSDeductionGuide, Loc);
}
diff --git a/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
b/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
index 5392573fcdb9d5..675c32a81f1ae8 100644
--- a/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
+++ b/clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
@@ -481,3 +481,16 @@ struct Out {
Out::B out(100); // deduced to Out::A;
static_assert(__is_same(decltype(out), Out::A));
}
+
+namespace GH111508 {
+
+template struct S {
+ using T = V;
+ T Data;
+};
+
+template using Alias = S;
+
+Alias A(42);
+
+} // namespace GH111508
___
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[llvm-branch-commits] [clang] release/19.x: [Clang] Instantiate Typedefs referenced by type alias deduction guides (#111804) (PR #112293)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/112293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Instantiate Typedefs referenced by type alias deduction guides (#111804) (PR #112293)
llvmbot wrote: @erichkeane What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/112293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] Backport "[ELF] Make shouldAddProvideSym return values consistent when demoted to Undefined" (PR #112136)
https://github.com/DianQK converted_to_draft https://github.com/llvm/llvm-project/pull/112136 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] Backport "[ELF] Make shouldAddProvideSym return values consistent when demoted to Undefined" (PR #112136)
DianQK wrote: Mark as draft due to https://github.com/llvm/llvm-project/pull/111945#issuecomment-2412354753. https://github.com/llvm/llvm-project/pull/112136 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
optimisan wrote: Also updated in PR. Initializes correct dependency as VirtRegMapWrapper is unused here https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
https://github.com/arsenm requested changes to this pull request. Description still not fixed https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From b337b06e2ecd3d6bbf740ee9ec857463f32d0f1c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f367b5fbea45af 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 2cefaf6d479b6c7ae6bc8a2267f8e4fee274923c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 604653e56782d625ab2444f02e67cda557cdb166 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 31 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 27 insertions(+), 25 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..2ca275cf950564 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s |
FileCheck %s --check-prefix=CHECK2
+# COM: auto-generated updates might remove checks for MachineFunctionInfo
reserved registers.
---
name: pre_allocate_wwm_regs_strict
@@ -9,6 +11,8 @@ body: |
bb.0:
liveins: $sgpr1
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: wwmReservedRegs:
+; CHECK-NEXT: - '$vgpr0'
; CHECK: liveins: $sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IM
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Updated the correct pass dependency (PR #109937)
https://github.com/cdevadas edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Updated the correct pass dependency. (PR #109937)
https://github.com/cdevadas edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 9ef4d7c5293076be21240a1e8e696b8e1b58d2ff Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..771a530d8d8c47 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4331a96ab4cbe5939c8ae189140a9ea2f305c950 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/8] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterIn
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
optimisan wrote: ### Merge activity * **Oct 14, 4:57 AM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/110229). https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
@@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2 + +--- optimisan wrote: Added a comment for the manual check. https://github.com/llvm/llvm-project/pull/109963 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 671b3c6b33c27374b33eefc4bb20a94aa803f65c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..771a530d8d8c47 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4da5550cabcf293f0beec8aae8c0752d84031cba Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/8] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterIn
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111634
>From ccb60e8277d3beeeffba72349ba0f1ffdb21b0fa Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 9dd11585f667dabc59cbe2b7b0279d42d92d3b77 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 06:22:10 +
Subject: [PATCH 2/2] unrename RegInfo: doesn't belong here
---
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f10a480f7e6160..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-MRI.invalidateLiveness();
+RegInfo.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,7 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
-MRI.noteNewVirtualRegister(Info.VReg);
+RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -721,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-MRI.addLiveIn(Reg, VReg);
+RegInfo.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -734,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-MRI.setCalleeSavedRegs(CalleeSavedRegisters);
+RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 6789308b56f950b89ca1ce822f071e3b499b2924 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..771a530d8d8c47 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 9a575fd028a74e57c858cb90d89f857829da97c8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/8] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterIn
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111634
>From 4d77407b08def09e2ff8e5b87bbce46630271e50 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 9390926f0379ff4d4311c8ce797178677927601a Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 06:22:10 +
Subject: [PATCH 2/2] unrename RegInfo: doesn't belong here
---
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f10a480f7e6160..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-MRI.invalidateLiveness();
+RegInfo.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,7 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
-MRI.noteNewVirtualRegister(Info.VReg);
+RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -721,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-MRI.addLiveIn(Reg, VReg);
+RegInfo.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -734,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-MRI.setCalleeSavedRegs(CalleeSavedRegisters);
+RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] release/19.x: [lld][Hexagon] Support predicated-add GOT_16_X mask lookup (#111896) (PR #112040)
https://github.com/SidManning approved this pull request. https://github.com/llvm/llvm-project/pull/112040 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang] Split runtime headers in preparation for cross-compilation. NFC. (PR #112188)
https://github.com/Meinersbur updated
https://github.com/llvm/llvm-project/pull/112188
>From 42e5abb5b291e78aeb152d7c636c75fe4d90492a Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Mon, 14 Oct 2024 13:55:16 +0200
Subject: [PATCH 1/2] Split headers in preparation for cross-compilation. NFC.
---
flang/include/flang/Lower/Allocatable.h | 2 +-
.../flang/Optimizer/Builder/MutableBox.h | 2 +-
.../flang/Optimizer/CodeGen/DescriptorModel.h | 2 +-
flang/include/flang/Runtime/CUDA/allocator.h | 2 +-
flang/include/flang/Runtime/CUDA/descriptor.h | 2 +-
.../flang/Runtime/allocator-registry-consts.h | 20 +
.../flang/Runtime/allocator-registry.h| 9 +--
.../flang/Runtime/array-constructor-consts.h | 54 +
.../include/flang/Runtime/array-constructor.h | 80 +++
.../include/flang/Runtime/descriptor-consts.h | 72 +
flang/include/flang/Runtime/descriptor.h | 15 +---
flang/include/flang/Runtime/io-api-funcs.h| 39 +
flang/include/flang/Runtime/io-api.h | 3 -
flang/include/flang/Runtime/iostat-funcs.h| 23 ++
flang/include/flang/Runtime/iostat.h | 2 -
flang/lib/Lower/ConvertVariable.cpp | 2 +-
.../Builder/Runtime/ArrayConstructor.cpp | 6 +-
flang/lib/Optimizer/CodeGen/CodeGen.cpp | 18 ++---
flang/lib/Semantics/compute-offsets.cpp | 8 +-
flang/runtime/environment-default-list.h | 0
flang/runtime/extensions.cpp | 2 +-
flang/runtime/internal-unit.cpp | 2 +
flang/runtime/io-api-common.h | 2 +-
flang/runtime/io-api-minimal.cpp | 2 +-
flang/runtime/io-api.cpp | 2 +-
flang/runtime/io-error.h | 2 +-
flang/runtime/io-stmt.h | 2 +-
flang/runtime/iostat.cpp | 2 +-
flang/runtime/namelist.cpp| 2 +-
.../Builder/Runtime/AllocatableTest.cpp | 2 +-
30 files changed, 254 insertions(+), 127 deletions(-)
create mode 100644 flang/include/flang/Runtime/allocator-registry-consts.h
create mode 100644 flang/include/flang/Runtime/array-constructor-consts.h
create mode 100644 flang/include/flang/Runtime/descriptor-consts.h
create mode 100644 flang/include/flang/Runtime/io-api-funcs.h
create mode 100644 flang/include/flang/Runtime/iostat-funcs.h
mode change 100755 => 100644 flang/runtime/environment-default-list.h
diff --git a/flang/include/flang/Lower/Allocatable.h
b/flang/include/flang/Lower/Allocatable.h
index 1209b157ed1f41..0e89af94af40f6 100644
--- a/flang/include/flang/Lower/Allocatable.h
+++ b/flang/include/flang/Lower/Allocatable.h
@@ -15,7 +15,7 @@
#include "flang/Lower/AbstractConverter.h"
#include "flang/Optimizer/Builder/MutableBox.h"
-#include "flang/Runtime/allocator-registry.h"
+#include "flang/Runtime/allocator-registry-consts.h"
#include "llvm/ADT/StringRef.h"
namespace mlir {
diff --git a/flang/include/flang/Optimizer/Builder/MutableBox.h
b/flang/include/flang/Optimizer/Builder/MutableBox.h
index fea7c7204837b4..39657ddaf6e03a 100644
--- a/flang/include/flang/Optimizer/Builder/MutableBox.h
+++ b/flang/include/flang/Optimizer/Builder/MutableBox.h
@@ -14,7 +14,7 @@
#define FORTRAN_OPTIMIZER_BUILDER_MUTABLEBOX_H
#include "flang/Optimizer/Builder/BoxValue.h"
-#include "flang/Runtime/allocator-registry.h"
+#include "flang/Runtime/allocator-registry-consts.h"
#include "llvm/ADT/StringRef.h"
namespace mlir {
diff --git a/flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
b/flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
index ff0cf29e8073e6..9cccf8db87270e 100644
--- a/flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
+++ b/flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
@@ -23,7 +23,7 @@
#define OPTIMIZER_DESCRIPTOR_MODEL_H
#include "flang/ISO_Fortran_binding_wrapper.h"
-#include "flang/Runtime/descriptor.h"
+#include "flang/Runtime/descriptor-consts.h"
#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
#include "mlir/IR/BuiltinTypes.h"
#include "llvm/Support/ErrorHandling.h"
diff --git a/flang/include/flang/Runtime/CUDA/allocator.h
b/flang/include/flang/Runtime/CUDA/allocator.h
index 4527c9f18fa054..cc88896b1f0bd6 100644
--- a/flang/include/flang/Runtime/CUDA/allocator.h
+++ b/flang/include/flang/Runtime/CUDA/allocator.h
@@ -9,7 +9,7 @@
#ifndef FORTRAN_RUNTIME_CUDA_ALLOCATOR_H_
#define FORTRAN_RUNTIME_CUDA_ALLOCATOR_H_
-#include "flang/Runtime/descriptor.h"
+#include "flang/Runtime/descriptor-consts.h"
#include "flang/Runtime/entry-names.h"
#define CUDA_REPORT_IF_ERROR(expr) \
diff --git a/flang/include/flang/Runtime/CUDA/descriptor.h
b/flang/include/flang/Runtime/CUDA/descriptor.h
index d593989420420f..501a834f43bd42 100644
--- a/flang/include/flang/Runtime/CUDA/descriptor.h
+++ b/flang/include/flang/Runtime/CUDA/descriptor.h
@@ -9,7 +9,7 @@
#ifndef FORTRAN_RUNTIME_CUDA_DESCRIPTOR_H_
#define FORTRAN_RUNTIME_CUD
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
@@ -0,0 +1,49 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 arsenm wrote: Best to remote this and remove the comment then https://github.com/llvm/llvm-project/pull/109963 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][CodeGen] Port LiveRegMatrix to NPM (PR #109938)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From 38940e946a1331426c99e095d26fe81fd2e34eb9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include/llvm/CodeGen/LiveRegMatrix.h | 50 ---
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/LiveRegMatrix.cpp| 38 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 8 +--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +--
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +--
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 6 +--
9 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 2b32308c7c075e..c024ca9c1dc38d 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -37,7 +37,9 @@ class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
-class LiveRegMatrix : public MachineFunctionPass {
+class LiveRegMatrix {
+ friend class LiveRegMatrixWrapperPass;
+ friend class LiveRegMatrixAnalysis;
const TargetRegisterInfo *TRI = nullptr;
LiveIntervals *LIS = nullptr;
VirtRegMap *VRM = nullptr;
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) override;
- void releaseMemory() override;
+ LiveRegMatrix() = default;
+ void releaseMemory();
public:
- static char ID;
-
- LiveRegMatrix();
+ LiveRegMatrix(LiveRegMatrix &&Other)
+ : TRI(Other.TRI), LIS(Other.LIS), VRM(Other.VRM), UserTag(Other.UserTag),
+Matrix(std::move(Other.Matrix)), Queries(std::move(Other.Queries)),
+RegMaskTag(Other.RegMaskTag), RegMaskVirtReg(Other.RegMaskVirtReg),
+RegMaskUsable(std::move(Other.RegMaskUsable)) {
+Other.TRI = nullptr;
+Other.LIS = nullptr;
+Other.VRM = nullptr;
+ }
+
+ void init(MachineFunction &MF, LiveIntervals *LIS, VirtRegMap *VRM);
//======//
// High-level interface.
@@ -159,6 +167,32 @@ class LiveRegMatrix : public MachineFunctionPass {
Register getOneVReg(unsigned PhysReg) const;
};
+class LiveRegMatrixWrapperPass : public MachineFunctionPass {
+ LiveRegMatrix LRM;
+
+public:
+ static char ID;
+
+ LiveRegMatrixWrapperPass() : MachineFunctionPass(ID) {}
+
+ LiveRegMatrix &getLRM() { return LRM; }
+ const LiveRegMatrix &getLRM() const { return LRM; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void releaseMemory() override;
+};
+
+class LiveRegMatrixAnalysis : public AnalysisInfoMixin {
+ friend AnalysisInfoMixin;
+ static AnalysisKey Key;
+
+public:
+ using Result = LiveRegMatrix;
+
+ LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index d89a5538b46975..3fee8c40a6607e 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveRegMatrixWrapperPassPass(PassRegistry &);
void initializeLiveStacksPass(PassRegistry &);
void initializeLiveVariablesWrapperPassPass(PassRegistry &);
void initializeLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bdc56ca03f392a..4497c1fce0db69 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-block-freq",
MachineBlockFrequencyAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
MachineBranchProbabilityAnalysis())
@@ -122,8 +123,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap",
VirtRegMapAnalysis())
// MachineRegionInf
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for SIPreAllocateWWMRegs (PR #109963)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 6cf96bb203bc97862ac38776db14365fc75b451f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 26 +++
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 +++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def
$exec, implicit-def $scc, implicit $exec
+; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0,
implicit $exec
+; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec,
implicit-def $scc, implicit $exec
+%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12,
15, 0, implicit $exec
+$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+%2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+ bb.0:
+liveins: $sgpr1
+; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+; CHECK: liveins: $sgpr1
+; CHECK-NEXT: {{ $}}
+; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+%0:vgpr_32 = IMPLICIT_DEF
+%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+%2:vgpr_32 = COPY %0:vgpr_32
+...
+
>From 43c0d2c61edc837da2ebe4c6166c14d12f8c64a1 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 09:13:04 +
Subject: [PATCH 2/2] Keep tests in one file
---
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 31 ---
.../si-pre-allocate-wwm-sgpr-spills.mir | 21 -
2 files changed, 27 insertions(+), 25 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
index f2db299f575f5e..2ca275cf950564 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s |
FileCheck %s --check-prefix=CHECK2
+# COM: auto-generated updates might remove checks for MachineFunctionInfo
reserved registers.
---
name: pre_allocate_wwm_regs_strict
@@ -9,6 +11,8 @@ body: |
bb.0:
liveins: $sgpr1
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+; CHECK: wwmReservedRegs:
+; CHECK-NEXT: - '$vgpr0'
; CHECK: liveins: $sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IM
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency initialization (PR #109937)
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/109937 >From db91ca05946f4bd1067819f788edc45c360ef9d7 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 24 Sep 2024 06:35:43 + Subject: [PATCH] [AMDGPU][SILowerSGPRSpills] Correct pass dependency Replace the unused analysis (VirtRegMap) dependency with the used one (SlotIndexes). This initializes `SlotIndexesWrapperPass` which is used by SILowerSGPRSpills to ensure that legacy pass manager finds it. Removes the initialization for `VirtRegMapWrapperLegacy` pass since it is not requested in this pass. --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 4afefa3d9b245c..d8697aa2ffe1cd 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -95,8 +95,8 @@ char SILowerSGPRSpillsLegacy::ID = 0; INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] LiveIntervalUnions::Array Implement move constructor (PR #111357)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From 052c8b15b41b091cc5b91b41f5dee07f26ccd055 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
---
llvm/include/llvm/CodeGen/LiveIntervalUnion.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index 81003455da4241..cc0f2a45bb182c 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -176,6 +176,13 @@ class LiveIntervalUnion {
Array() = default;
~Array() { clear(); }
+Array(Array &&Other) : Size(Other.Size), LIUs(Other.LIUs) {
+ Other.Size = 0;
+ Other.LIUs = nullptr;
+}
+
+Array(const Array &) = delete;
+
// Initialize the array to have Size entries.
// Reuse an existing allocation if the size matches.
void init(LiveIntervalUnion::Allocator&, unsigned Size);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (PR #109939)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From a94c78f1fb0de895fa153fe4948689e4523b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 ++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp| 60 ---
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h | 25
.../AMDGPU/si-pre-allocate-wwm-regs.mir | 21 +++
6 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 342d55e828bca5..95d0ad0f9dc96a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
FunctionPass *createLowerWWMCopiesPass();
FunctionPass *createSIMemoryLegalizerPass();
FunctionPass *createSIInsertWaitcntsPass();
-FunctionPass *createSIPreAllocateWWMRegsPass();
+FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
FunctionPass *createSIFormMemoryClausesPass();
FunctionPass *createSIPostRABundlerPass();
@@ -212,8 +212,8 @@ extern char &SILateBranchLoweringPassID;
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
-void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
-extern char &SIPreAllocateWWMRegsID;
+void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
+extern char &SIPreAllocateWWMRegsLegacyID;
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
extern char &AMDGPUImageIntrinsicOptimizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ebf34c901c142..174a90f0aa419d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,5 +102,6 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine",
GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 16e23879cd735c..87a6e6cff6dc1d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -41,6 +41,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
+#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -508,7 +509,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSILateBranchLoweringPass(*PR);
initializeSIMemoryLegalizerPass(*PR);
initializeSIOptimizeExecMaskingPass(*PR);
- initializeSIPreAllocateWWMRegsPass(*PR);
+ initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesPass(*PR);
initializeSIPostRABundlerPass(*PR);
initializeGCNCreateVOPDPass(*PR);
@@ -1506,7 +1507,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other wwm register operands.
addPass(createWWMRegAllocPass(false));
@@ -1543,7 +1544,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&SILowerSGPRSpillsLegacyID);
// To Allocate wwm registers used in whole quad mode operations (for
shaders).
- addPass(&SIPreAllocateWWMRegsID);
+ addPass(&SIPreAllocateWWMRegsLegacyID);
// For allocating other whole wave mode registers.
addPass(createWWMRegAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 07303e2aa726c5..f9109c01c8085b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -11,6 +11,7 @@
//
//===--===//
+#include "SIPreAllocateWWMRegs.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt
namespace {
-class SIPreAllocateWWMRegs : public MachineFunctionPass {
+class SIPreAllocateWWMRegs {
private:
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
[llvm-branch-commits] [llvm] [AArch64][PAC] Move emission of LR checks in tail calls to AsmPrinter (PR #110705)
asl wrote: @kbeyls @ahmedbougacha Will you please a look? https://github.com/llvm/llvm-project/pull/110705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support perf2bolt-N in the driver (PR #111072)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/111072 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support perf2bolt-N in the driver (PR #111072)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/111072 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support perf2bolt-N in the driver (PR #111072)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/111072 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [flang] [lld] [llvm] [Flang] LLVM_ENABLE_RUNTIMES=FortranRuntime (PR #110217)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/110217 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [Flang] Split runtime headers in preparation for cross-compilation. NFC. (PR #112188)
https://github.com/Meinersbur created
https://github.com/llvm/llvm-project/pull/112188
Split some headers into headers for public and private declarations in
preparation for #110217. Moving the runtime-private headers in runtime-private
include directory will occur in #110298.
* Do not use `sizeof(Descriptor)` in the compiler. The size of the descriptor
is target-dependent while `sizeof(Descriptor)` is the size of the Descriptor
for the host platform which might be too small when cross-compiling to a
different platform. Another problem is that the emitted assembly
((cross-)compiling to the same target) is not identical between Flang's running
on different systems. Moving the declaration of `class Descriptor` out of the
included header will also reduce the amount of #included source.
* Do not use `sizeof(ArrayConstructorVector)` and
`alignof(ArrayConstructorVector)` in the compiler. Same reason as with
`Descriptor`.
* Compute the descriptor's extra flags without instantiating a Descriptor.
`Fortran::runtime::Descriptor` is defined in the runtime, not the compiler.
* Move `InquiryKeywordHashDecode` into runtime-private header. The function is
defined in the runtime and trying to call it in the compiler will lead to a
link-error.
* Move allocator kind magic numbers into common header. They are the only
declarations out of `allocator-registry.h` in the compiler as well.
>From 42e5abb5b291e78aeb152d7c636c75fe4d90492a Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Mon, 14 Oct 2024 13:55:16 +0200
Subject: [PATCH] Split headers in preparation for cross-compilation. NFC.
---
flang/include/flang/Lower/Allocatable.h | 2 +-
.../flang/Optimizer/Builder/MutableBox.h | 2 +-
.../flang/Optimizer/CodeGen/DescriptorModel.h | 2 +-
flang/include/flang/Runtime/CUDA/allocator.h | 2 +-
flang/include/flang/Runtime/CUDA/descriptor.h | 2 +-
.../flang/Runtime/allocator-registry-consts.h | 20 +
.../flang/Runtime/allocator-registry.h| 9 +--
.../flang/Runtime/array-constructor-consts.h | 54 +
.../include/flang/Runtime/array-constructor.h | 80 +++
.../include/flang/Runtime/descriptor-consts.h | 72 +
flang/include/flang/Runtime/descriptor.h | 15 +---
flang/include/flang/Runtime/io-api-funcs.h| 39 +
flang/include/flang/Runtime/io-api.h | 3 -
flang/include/flang/Runtime/iostat-funcs.h| 23 ++
flang/include/flang/Runtime/iostat.h | 2 -
flang/lib/Lower/ConvertVariable.cpp | 2 +-
.../Builder/Runtime/ArrayConstructor.cpp | 6 +-
flang/lib/Optimizer/CodeGen/CodeGen.cpp | 18 ++---
flang/lib/Semantics/compute-offsets.cpp | 8 +-
flang/runtime/environment-default-list.h | 0
flang/runtime/extensions.cpp | 2 +-
flang/runtime/internal-unit.cpp | 2 +
flang/runtime/io-api-common.h | 2 +-
flang/runtime/io-api-minimal.cpp | 2 +-
flang/runtime/io-api.cpp | 2 +-
flang/runtime/io-error.h | 2 +-
flang/runtime/io-stmt.h | 2 +-
flang/runtime/iostat.cpp | 2 +-
flang/runtime/namelist.cpp| 2 +-
.../Builder/Runtime/AllocatableTest.cpp | 2 +-
30 files changed, 254 insertions(+), 127 deletions(-)
create mode 100644 flang/include/flang/Runtime/allocator-registry-consts.h
create mode 100644 flang/include/flang/Runtime/array-constructor-consts.h
create mode 100644 flang/include/flang/Runtime/descriptor-consts.h
create mode 100644 flang/include/flang/Runtime/io-api-funcs.h
create mode 100644 flang/include/flang/Runtime/iostat-funcs.h
mode change 100755 => 100644 flang/runtime/environment-default-list.h
diff --git a/flang/include/flang/Lower/Allocatable.h
b/flang/include/flang/Lower/Allocatable.h
index 1209b157ed1f41..0e89af94af40f6 100644
--- a/flang/include/flang/Lower/Allocatable.h
+++ b/flang/include/flang/Lower/Allocatable.h
@@ -15,7 +15,7 @@
#include "flang/Lower/AbstractConverter.h"
#include "flang/Optimizer/Builder/MutableBox.h"
-#include "flang/Runtime/allocator-registry.h"
+#include "flang/Runtime/allocator-registry-consts.h"
#include "llvm/ADT/StringRef.h"
namespace mlir {
diff --git a/flang/include/flang/Optimizer/Builder/MutableBox.h
b/flang/include/flang/Optimizer/Builder/MutableBox.h
index fea7c7204837b4..39657ddaf6e03a 100644
--- a/flang/include/flang/Optimizer/Builder/MutableBox.h
+++ b/flang/include/flang/Optimizer/Builder/MutableBox.h
@@ -14,7 +14,7 @@
#define FORTRAN_OPTIMIZER_BUILDER_MUTABLEBOX_H
#include "flang/Optimizer/Builder/BoxValue.h"
-#include "flang/Runtime/allocator-registry.h"
+#include "flang/Runtime/allocator-registry-consts.h"
#include "llvm/ADT/StringRef.h"
namespace mlir {
diff --git a/flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
b/flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
index ff0cf29e807
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Update the correct pass dependency initialization (PR #109937)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][SILowerSGPRSpills] Updated the correct pass dependency (PR #109937)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
