[llvm-branch-commits] [llvm] release/19.x: Restrict LLVM_TARGETS_TO_BUILD in Windows release packaging (#106059) (PR #106546)
zmodem wrote: @tru can I do something to help get that release note ^ into the release? https://github.com/llvm/llvm-project/pull/106546 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: Restrict LLVM_TARGETS_TO_BUILD in Windows release packaging (#106059) (PR #106546)
tru wrote: > @tru can I do something to help get that release note ^ into the release? I think for the initial release we'll just use the release notes document in the docs folder as usual. So I would add it to LLVM release notes and give me PR for that. https://github.com/llvm/llvm-project/pull/106546 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Release note about targets built in the Windows packages (PR #107826)
https://github.com/zmodem milestoned https://github.com/llvm/llvm-project/pull/107826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Release note about targets built in the Windows packages (PR #107826)
https://github.com/zmodem created https://github.com/llvm/llvm-project/pull/107826 LLVM_TARGETS_TO_BUILD was set in #106059 >From d5d63953da88af4c6f09d0f97edaa92f8a326e09 Mon Sep 17 00:00:00 2001 From: Hans Wennborg Date: Mon, 9 Sep 2024 10:56:37 +0200 Subject: [PATCH] Release note about targets built in the Windows packages LLVM_TARGETS_TO_BUILD was set in #106059 --- llvm/docs/ReleaseNotes.rst | 4 1 file changed, 4 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index ac7bdf723a168d..7b9e15da9b2b00 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -42,6 +42,10 @@ Non-comprehensive list of changes in this release functionality, or simply have a lot to talk about), see the `NOTE` below for adding a new subsection. +* Starting with LLVM 19, the Windows installers only include support for the + X86, ARM, and AArch64 targets in order to keep the build size within the + limits of the NSIS installer framework. + * ... Update on required toolchains to build LLVM ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Release note about targets built in the Windows packages (PR #107826)
https://github.com/zmodem edited https://github.com/llvm/llvm-project/pull/107826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: Restrict LLVM_TARGETS_TO_BUILD in Windows release packaging (#106059) (PR #106546)
zmodem wrote: Sent https://github.com/llvm/llvm-project/pull/107826 https://github.com/llvm/llvm-project/pull/106546 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Release note about targets built in the Windows packages (PR #107826)
https://github.com/tru approved this pull request. https://github.com/llvm/llvm-project/pull/107826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Release note about targets built in the Windows packages (PR #107826)
zmodem wrote: I think you need to push the merge button, I don't have permission. https://github.com/llvm/llvm-project/pull/107826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
https://github.com/steakhal milestoned https://github.com/llvm/llvm-project/pull/107841 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/107841
Backports the fix for #107724.
(cherry picked from commit d84d9559bdc7aeb4ce14c251f6a3490c66db8d3a)
>From f791ef134479616ced3d90c5321ecb878c5b6efc Mon Sep 17 00:00:00 2001
From: Nicolas van Kempen
Date: Mon, 9 Sep 2024 07:12:46 -0400
Subject: [PATCH] [clang][analyzer] Fix #embed crash (#107764)
Fix #107724.
(cherry picked from commit d84d9559bdc7aeb4ce14c251f6a3490c66db8d3a)
---
clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 5 +
clang/test/Analysis/embed.c | 12
2 files changed, 13 insertions(+), 4 deletions(-)
create mode 100644 clang/test/Analysis/embed.c
diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
index 62a240ecbc6003..c11468a08ae5ca 100644
--- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
@@ -1928,6 +1928,7 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred,
case Stmt::CXXRewrittenBinaryOperatorClass:
case Stmt::RequiresExprClass:
case Expr::CXXParenListInitExprClass:
+case Stmt::EmbedExprClass:
// Fall through.
// Cases we intentionally don't evaluate, since they don't need
@@ -2430,10 +2431,6 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred,
Bldr.addNodes(Dst);
break;
}
-
-case Stmt::EmbedExprClass:
- llvm::report_fatal_error("Support for EmbedExpr is not implemented.");
- break;
}
}
diff --git a/clang/test/Analysis/embed.c b/clang/test/Analysis/embed.c
new file mode 100644
index 00..32f6c130325740
--- /dev/null
+++ b/clang/test/Analysis/embed.c
@@ -0,0 +1,12 @@
+// RUN: %clang_analyze_cc1 -std=c23
-analyzer-checker=core,debug.ExprInspection -verify %s
+
+void clang_analyzer_dump_ptr(const unsigned char *ptr);
+void clang_analyzer_dump(unsigned char val);
+
+int main() {
+const unsigned char SelfBytes[] = {
+#embed "embed.c"
+};
+clang_analyzer_dump_ptr(SelfBytes); // expected-warning
{{&Element{SelfBytes,0 S64b,unsigned char}}}
+clang_analyzer_dump(SelfBytes[0]); // expected-warning {{Unknown}} FIXME:
This should be the `/` character.
+}
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[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
https://github.com/steakhal edited https://github.com/llvm/llvm-project/pull/107841 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
llvmbot wrote:
@llvm/pr-subscribers-clang-static-analyzer-1
Author: Balazs Benics (steakhal)
Changes
Backports the fix for #107724.
(cherry picked from commit d84d9559bdc7aeb4ce14c251f6a3490c66db8d3a)
---
Full diff: https://github.com/llvm/llvm-project/pull/107841.diff
2 Files Affected:
- (modified) clang/lib/StaticAnalyzer/Core/ExprEngine.cpp (+1-4)
- (added) clang/test/Analysis/embed.c (+12)
``diff
diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
index 62a240ecbc6003..c11468a08ae5ca 100644
--- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
@@ -1928,6 +1928,7 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred,
case Stmt::CXXRewrittenBinaryOperatorClass:
case Stmt::RequiresExprClass:
case Expr::CXXParenListInitExprClass:
+case Stmt::EmbedExprClass:
// Fall through.
// Cases we intentionally don't evaluate, since they don't need
@@ -2430,10 +2431,6 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred,
Bldr.addNodes(Dst);
break;
}
-
-case Stmt::EmbedExprClass:
- llvm::report_fatal_error("Support for EmbedExpr is not implemented.");
- break;
}
}
diff --git a/clang/test/Analysis/embed.c b/clang/test/Analysis/embed.c
new file mode 100644
index 00..32f6c130325740
--- /dev/null
+++ b/clang/test/Analysis/embed.c
@@ -0,0 +1,12 @@
+// RUN: %clang_analyze_cc1 -std=c23
-analyzer-checker=core,debug.ExprInspection -verify %s
+
+void clang_analyzer_dump_ptr(const unsigned char *ptr);
+void clang_analyzer_dump(unsigned char val);
+
+int main() {
+const unsigned char SelfBytes[] = {
+#embed "embed.c"
+};
+clang_analyzer_dump_ptr(SelfBytes); // expected-warning
{{&Element{SelfBytes,0 S64b,unsigned char}}}
+clang_analyzer_dump(SelfBytes[0]); // expected-warning {{Unknown}} FIXME:
This should be the `/` character.
+}
``
https://github.com/llvm/llvm-project/pull/107841
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[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
steakhal wrote: There is no need to update the release notes as `#embed` is a new feature, so the crash is not a regression that needs to be highlighted. https://github.com/llvm/llvm-project/pull/107841 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
https://github.com/NagyDonat approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/107841 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang] Introduce custom loop nest generation for loops in workshare construct (PR #101445)
skatrak wrote: Sorry for the delay getting back to this! I don't have any remaining blocking concerns with your proposal, but I think it would be good if others shared their opinions before proceeding with this approach. https://github.com/llvm/llvm-project/pull/101445 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Backport "[clang][analyzer] Fix #embed crash (#107764)" (PR #107841)
https://github.com/Xazax-hun approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/107841 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6-beta.1
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 15 +
.../Target/RISCV/RISCVTargetTransformInfo.h | 3 +
llvm/test/CodeGen/RISCV/memcmp.ll | 932 ++
3 files changed, 950 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/memcmp.ll
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index e809e15eacf696..ad532aadc83266 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME: Vector haven't been tested.
+ Options.AllowOverlappingLoads =
+ (ST->enableUnalignedScalarMem() || ST->enableUnalignedScalarMem());
+ Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
+ Options.NumLoadsPerBlock = Options.MaxNumLoads;
+ if (ST->is64Bit())
+Options.LoadSizes.push_back(8);
+ llvm::append_range(Options.LoadSizes, ArrayRef({4, 2, 1}));
+ Options.AllowedTailExpansions = {3, 5, 6};
+ return Options;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 763b89bfec0a66..ee9bed09df97f3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -404,6 +404,9 @@ class RISCVTTIImpl : public BasicTTIImplBase {
shouldConsiderAddressTypePromotion(const Instruction &I,
bool &AllowPromotionWithoutCommonHeader);
std::optional getMinPageSize() const { return 4096; }
+
+ TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
+bool IsZeroCmp) const;
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/RISCV/memcmp.ll
b/llvm/test/CodeGen/RISCV/memcmp.ll
new file mode 100644
index 00..652cd02e2c750a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/memcmp.ll
@@ -0,0 +1,932 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV64
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32
-mattr=+unaligned-scalar-mem -O2 \
+; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
-mattr=+unaligned-scalar-mem -O2 \
+; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV64
+
+declare i32 @bcmp(i8*, i8*, iXLen) nounwind readonly
+declare i32 @memcmp(i8*, i8*, iXLen) nounwind readonly
+
+define i1 @bcmp_size_15(i8* %s1, i8* %s2) {
+; CHECK-ALIGNED-RV32-LABEL: bcmp_size_15:
+; CHECK-ALIGNED-RV32: # %bb.0: # %entry
+; CHECK-ALIGNED-RV32-NEXT:lbu a2, 1(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 0(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 2(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 3(a0)
+; CHECK-ALIGNED-RV32-NEXT:slli a2, a2, 8
+; CHECK-ALIGNED-RV32-NEXT:or a2, a2, a3
+; CHECK-ALIGNED-RV32-NEXT:slli a4, a4, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a5, a4
+; CHECK-ALIGNED-RV32-NEXT:or a2, a4, a2
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 1(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 0(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 2(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a6, 3(a1)
+; CHECK-ALIGNED-RV32-NEXT:slli a3, a3, 8
+; CHECK-ALIGNED-RV32-NEXT:or a3, a3, a4
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a6, a6, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a6, a5
+; CHECK-ALIGNED-RV32-NEXT:or a3, a4, a3
+; CHECK-ALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 5(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 4(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 6(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a6, 7(a0)
+; CHECK-ALIGNED-RV32-NEXT:slli a3, a3, 8
+; CHECK-ALIGNED-RV32-NEXT:or a3, a3, a4
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a6, a6, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a6, a5
+; CHECK-ALIGNED-RV32-NEXT:or a3, a4, a3
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 5(a1)
+; CHECK-ALIGNED-RV32-NEXT
[llvm-branch-commits] [flang] [flang] Introduce custom loop nest generation for loops in workshare construct (PR #101445)
https://github.com/tblah approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101445 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
@@ -0,0 +1,932 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 | FileCheck %s --check-prefix=CHECK-ALIGNED-RV32 +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -O2 | FileCheck %s --check-prefix=CHECK-ALIGNED-RV64 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -O2 \ +; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV32 +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -O2 \ +; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV64 + +declare i32 @bcmp(i8*, i8*, iXLen) nounwind readonly wangpc-pp wrote: https://github.com/llvm/llvm-project/pull/107824 https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6-beta.1
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 15 +
.../Target/RISCV/RISCVTargetTransformInfo.h | 3 +
llvm/test/CodeGen/RISCV/memcmp.ll | 932 ++
3 files changed, 950 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/memcmp.ll
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index e809e15eacf696..ad532aadc83266 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME: Vector haven't been tested.
+ Options.AllowOverlappingLoads =
+ (ST->enableUnalignedScalarMem() || ST->enableUnalignedScalarMem());
+ Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
+ Options.NumLoadsPerBlock = Options.MaxNumLoads;
+ if (ST->is64Bit())
+Options.LoadSizes.push_back(8);
+ llvm::append_range(Options.LoadSizes, ArrayRef({4, 2, 1}));
+ Options.AllowedTailExpansions = {3, 5, 6};
+ return Options;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 763b89bfec0a66..ee9bed09df97f3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -404,6 +404,9 @@ class RISCVTTIImpl : public BasicTTIImplBase {
shouldConsiderAddressTypePromotion(const Instruction &I,
bool &AllowPromotionWithoutCommonHeader);
std::optional getMinPageSize() const { return 4096; }
+
+ TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
+bool IsZeroCmp) const;
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/RISCV/memcmp.ll
b/llvm/test/CodeGen/RISCV/memcmp.ll
new file mode 100644
index 00..652cd02e2c750a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/memcmp.ll
@@ -0,0 +1,932 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV64
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32
-mattr=+unaligned-scalar-mem -O2 \
+; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
-mattr=+unaligned-scalar-mem -O2 \
+; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV64
+
+declare i32 @bcmp(i8*, i8*, iXLen) nounwind readonly
+declare i32 @memcmp(i8*, i8*, iXLen) nounwind readonly
+
+define i1 @bcmp_size_15(i8* %s1, i8* %s2) {
+; CHECK-ALIGNED-RV32-LABEL: bcmp_size_15:
+; CHECK-ALIGNED-RV32: # %bb.0: # %entry
+; CHECK-ALIGNED-RV32-NEXT:lbu a2, 1(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 0(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 2(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 3(a0)
+; CHECK-ALIGNED-RV32-NEXT:slli a2, a2, 8
+; CHECK-ALIGNED-RV32-NEXT:or a2, a2, a3
+; CHECK-ALIGNED-RV32-NEXT:slli a4, a4, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a5, a4
+; CHECK-ALIGNED-RV32-NEXT:or a2, a4, a2
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 1(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 0(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 2(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a6, 3(a1)
+; CHECK-ALIGNED-RV32-NEXT:slli a3, a3, 8
+; CHECK-ALIGNED-RV32-NEXT:or a3, a3, a4
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a6, a6, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a6, a5
+; CHECK-ALIGNED-RV32-NEXT:or a3, a4, a3
+; CHECK-ALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 5(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 4(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 6(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a6, 7(a0)
+; CHECK-ALIGNED-RV32-NEXT:slli a3, a3, 8
+; CHECK-ALIGNED-RV32-NEXT:or a3, a3, a4
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a6, a6, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a6, a5
+; CHECK-ALIGNED-RV32-NEXT:or a3, a4, a3
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 5(a1)
+; CHECK-ALIGNED-RV32-NEXT
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME: Vector haven't been tested.
+ Options.AllowOverlappingLoads =
+ (ST->enableUnalignedScalarMem() || ST->enableUnalignedVectorMem());
+ Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
+ Options.NumLoadsPerBlock = Options.MaxNumLoads;
+ if (ST->is64Bit())
+Options.LoadSizes.push_back(8);
+ llvm::append_range(Options.LoadSizes, ArrayRef({4, 2, 1}));
+ Options.AllowedTailExpansions = {3, 5, 6};
wangpc-pp wrote:
Yes, it seems we will generate i40/i48/... loads (see also the tests in
https://github.com/llvm/llvm-project/pull/70469).
This may not work for RISC-V.
https://github.com/llvm/llvm-project/pull/107548
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[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6-beta.1
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 15 +
.../Target/RISCV/RISCVTargetTransformInfo.h | 3 +
llvm/test/CodeGen/RISCV/memcmp.ll | 932 ++
3 files changed, 950 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/memcmp.ll
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index e809e15eacf696..ad532aadc83266 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME: Vector haven't been tested.
+ Options.AllowOverlappingLoads =
+ (ST->enableUnalignedScalarMem() || ST->enableUnalignedScalarMem());
+ Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
+ Options.NumLoadsPerBlock = Options.MaxNumLoads;
+ if (ST->is64Bit())
+Options.LoadSizes.push_back(8);
+ llvm::append_range(Options.LoadSizes, ArrayRef({4, 2, 1}));
+ Options.AllowedTailExpansions = {3, 5, 6};
+ return Options;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 763b89bfec0a66..ee9bed09df97f3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -404,6 +404,9 @@ class RISCVTTIImpl : public BasicTTIImplBase {
shouldConsiderAddressTypePromotion(const Instruction &I,
bool &AllowPromotionWithoutCommonHeader);
std::optional getMinPageSize() const { return 4096; }
+
+ TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
+bool IsZeroCmp) const;
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/RISCV/memcmp.ll
b/llvm/test/CodeGen/RISCV/memcmp.ll
new file mode 100644
index 00..652cd02e2c750a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/memcmp.ll
@@ -0,0 +1,932 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -O2 | FileCheck %s
--check-prefix=CHECK-ALIGNED-RV64
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32
-mattr=+unaligned-scalar-mem -O2 \
+; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64
-mattr=+unaligned-scalar-mem -O2 \
+; RUN: | FileCheck %s --check-prefix=CHECK-UNALIGNED-RV64
+
+declare i32 @bcmp(i8*, i8*, iXLen) nounwind readonly
+declare i32 @memcmp(i8*, i8*, iXLen) nounwind readonly
+
+define i1 @bcmp_size_15(i8* %s1, i8* %s2) {
+; CHECK-ALIGNED-RV32-LABEL: bcmp_size_15:
+; CHECK-ALIGNED-RV32: # %bb.0: # %entry
+; CHECK-ALIGNED-RV32-NEXT:lbu a2, 1(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 0(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 2(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 3(a0)
+; CHECK-ALIGNED-RV32-NEXT:slli a2, a2, 8
+; CHECK-ALIGNED-RV32-NEXT:or a2, a2, a3
+; CHECK-ALIGNED-RV32-NEXT:slli a4, a4, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a5, a4
+; CHECK-ALIGNED-RV32-NEXT:or a2, a4, a2
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 1(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 0(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 2(a1)
+; CHECK-ALIGNED-RV32-NEXT:lbu a6, 3(a1)
+; CHECK-ALIGNED-RV32-NEXT:slli a3, a3, 8
+; CHECK-ALIGNED-RV32-NEXT:or a3, a3, a4
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a6, a6, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a6, a5
+; CHECK-ALIGNED-RV32-NEXT:or a3, a4, a3
+; CHECK-ALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-ALIGNED-RV32-NEXT:lbu a3, 5(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 4(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a5, 6(a0)
+; CHECK-ALIGNED-RV32-NEXT:lbu a6, 7(a0)
+; CHECK-ALIGNED-RV32-NEXT:slli a3, a3, 8
+; CHECK-ALIGNED-RV32-NEXT:or a3, a3, a4
+; CHECK-ALIGNED-RV32-NEXT:slli a5, a5, 16
+; CHECK-ALIGNED-RV32-NEXT:slli a6, a6, 24
+; CHECK-ALIGNED-RV32-NEXT:or a4, a6, a5
+; CHECK-ALIGNED-RV32-NEXT:or a3, a4, a3
+; CHECK-ALIGNED-RV32-NEXT:lbu a4, 5(a1)
+; CHECK-ALIGNED-RV32-NEXT
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
@@ -2113,3 +2113,18 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
}
return Considerable;
}
+
+RISCVTTIImpl::TTI::MemCmpExpansionOptions
+RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
+ TTI::MemCmpExpansionOptions Options;
+ // FIXME: Vector haven't been tested.
+ Options.AllowOverlappingLoads =
+ (ST->enableUnalignedScalarMem() || ST->enableUnalignedVectorMem());
+ Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
+ Options.NumLoadsPerBlock = Options.MaxNumLoads;
+ if (ST->is64Bit())
+Options.LoadSizes.push_back(8);
+ llvm::append_range(Options.LoadSizes, ArrayRef({4, 2, 1}));
+ Options.AllowedTailExpansions = {3, 5, 6};
wangpc-pp wrote:
I removed it first. If RISC-V can benefit from it, we can add it back as a
follow-up.
https://github.com/llvm/llvm-project/pull/107548
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[llvm-branch-commits] [clang] release/19.x: [Clang][Sema] Use the correct lookup context when building overloaded 'operator->' in the current instantiation (#104458) (PR #107886)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/107886
Backport 3cdb30e
Requested by: @cor3ntin
>From e64fc4127deca57ace68d7ad634b926d10858ab5 Mon Sep 17 00:00:00 2001
From: Krystian Stasiowski
Date: Mon, 9 Sep 2024 12:06:45 -0400
Subject: [PATCH] [Clang][Sema] Use the correct lookup context when building
overloaded 'operator->' in the current instantiation (#104458)
Currently, clang erroneously rejects the following:
```
struct A
{
template
void f();
};
template
struct B
{
void g()
{
(*this)->template f(); // error: no member named 'f' in 'B'
}
A* operator->();
};
```
This happens because `Sema::ActOnStartCXXMemberReference` does not adjust the
`ObjectType` parameter when `ObjectType` is a dependent type (except when the
type is a `PointerType` and the class member access is the `->` form). Since
the (possibly adjusted) `ObjectType` parameter (`B` in the above example) is
passed to `Parser::ParseOptionalCXXScopeSpecifier`, we end up looking up `f` in
`B` rather than `A`.
This patch fixes the issue by identifying cases where the type of the object
expression `T` is a dependent, non-pointer type and:
- `T` is the current instantiation and lookup for `operator->` finds a member
of the current instantiation, or
- `T` has at least one dependent base case, and `operator->` is not found in
the current instantiation
and using `ASTContext::DependentTy` as the type of the object expression when
the optional _nested-name-specifier_ is parsed.
Fixes #104268.
(cherry picked from commit 3cdb30ebbc18fa894d3bd67aebcff76ce7c741ac)
---
clang/include/clang/Sema/Sema.h | 6 +--
clang/lib/Sema/SemaExprCXX.cpp| 37 +++
clang/lib/Sema/SemaOverload.cpp | 24 +---
clang/lib/Sema/TreeTransform.h| 8 +++-
.../temp.res/temp.dep/temp.dep.type/p4.cpp| 24 ++--
5 files changed, 62 insertions(+), 37 deletions(-)
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 7bfdaaae45a93e..f1e31f52de0ef5 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -10615,9 +10615,9 @@ class Sema final : public SemaBase {
/// BuildOverloadedArrowExpr - Build a call to an overloaded @c operator->
/// (if one exists), where @c Base is an expression of class type and
/// @c Member is the name of the member we're trying to find.
- ExprResult BuildOverloadedArrowExpr(Scope *S, Expr *Base,
- SourceLocation OpLoc,
- bool *NoArrowOperatorFound = nullptr);
+ ExprResult BuildOverloadedArrowExpr(Expr *Base, SourceLocation OpLoc,
+ bool *NoArrowOperatorFound,
+ bool &IsDependent);
ExprResult BuildCXXMemberCallExpr(Expr *Exp, NamedDecl *FoundDecl,
CXXConversionDecl *Method,
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index 14d1f395af90e3..9061cb5a957f2e 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -7850,18 +7850,6 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
QualType BaseType = Base->getType();
MayBePseudoDestructor = false;
- if (BaseType->isDependentType()) {
-// If we have a pointer to a dependent type and are using the -> operator,
-// the object type is the type that the pointer points to. We might still
-// have enough information about that type to do something useful.
-if (OpKind == tok::arrow)
- if (const PointerType *Ptr = BaseType->getAs())
-BaseType = Ptr->getPointeeType();
-
-ObjectType = ParsedType::make(BaseType);
-MayBePseudoDestructor = true;
-return Base;
- }
// C++ [over.match.oper]p8:
// [...] When operator->returns, the operator-> is applied to the value
@@ -7876,7 +7864,8 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
SmallVector OperatorArrows;
CTypes.insert(Context.getCanonicalType(BaseType));
-while (BaseType->isRecordType()) {
+while (
+isa(BaseType.getCanonicalType())) {
if (OperatorArrows.size() >= getLangOpts().ArrowDepth) {
Diag(OpLoc, diag::err_operator_arrow_depth_exceeded)
<< StartingType << getLangOpts().ArrowDepth <<
Base->getSourceRange();
@@ -7886,15 +7875,26 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
return ExprError();
}
+ bool IsDependent;
Result = BuildOverloadedArrowExpr(
- S, Base, OpLoc,
+ Base, OpLoc,
// When in a template specialization and on the first loop iteration,
// potentially give the default diagnostic (with the fixit in a
// separate note) instead of having the error reported back to here
// and giving a diagnosti
[llvm-branch-commits] [clang] release/19.x: [Clang][Sema] Use the correct lookup context when building overloaded 'operator->' in the current instantiation (#104458) (PR #107886)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/107886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang][Sema] Use the correct lookup context when building overloaded 'operator->' in the current instantiation (#104458) (PR #107886)
llvmbot wrote: @cor3ntin What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/107886 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang][Sema] Use the correct lookup context when building overloaded 'operator->' in the current instantiation (#104458) (PR #107886)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport 3cdb30e
Requested by: @cor3ntin
---
Full diff: https://github.com/llvm/llvm-project/pull/107886.diff
5 Files Affected:
- (modified) clang/include/clang/Sema/Sema.h (+3-3)
- (modified) clang/lib/Sema/SemaExprCXX.cpp (+21-16)
- (modified) clang/lib/Sema/SemaOverload.cpp (+19-5)
- (modified) clang/lib/Sema/TreeTransform.h (+6-2)
- (modified) clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp
(+13-11)
``diff
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 7bfdaaae45a93e..f1e31f52de0ef5 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -10615,9 +10615,9 @@ class Sema final : public SemaBase {
/// BuildOverloadedArrowExpr - Build a call to an overloaded @c operator->
/// (if one exists), where @c Base is an expression of class type and
/// @c Member is the name of the member we're trying to find.
- ExprResult BuildOverloadedArrowExpr(Scope *S, Expr *Base,
- SourceLocation OpLoc,
- bool *NoArrowOperatorFound = nullptr);
+ ExprResult BuildOverloadedArrowExpr(Expr *Base, SourceLocation OpLoc,
+ bool *NoArrowOperatorFound,
+ bool &IsDependent);
ExprResult BuildCXXMemberCallExpr(Expr *Exp, NamedDecl *FoundDecl,
CXXConversionDecl *Method,
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index 14d1f395af90e3..9061cb5a957f2e 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -7850,18 +7850,6 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
QualType BaseType = Base->getType();
MayBePseudoDestructor = false;
- if (BaseType->isDependentType()) {
-// If we have a pointer to a dependent type and are using the -> operator,
-// the object type is the type that the pointer points to. We might still
-// have enough information about that type to do something useful.
-if (OpKind == tok::arrow)
- if (const PointerType *Ptr = BaseType->getAs())
-BaseType = Ptr->getPointeeType();
-
-ObjectType = ParsedType::make(BaseType);
-MayBePseudoDestructor = true;
-return Base;
- }
// C++ [over.match.oper]p8:
// [...] When operator->returns, the operator-> is applied to the value
@@ -7876,7 +7864,8 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
SmallVector OperatorArrows;
CTypes.insert(Context.getCanonicalType(BaseType));
-while (BaseType->isRecordType()) {
+while (
+isa(BaseType.getCanonicalType())) {
if (OperatorArrows.size() >= getLangOpts().ArrowDepth) {
Diag(OpLoc, diag::err_operator_arrow_depth_exceeded)
<< StartingType << getLangOpts().ArrowDepth <<
Base->getSourceRange();
@@ -7886,15 +7875,26 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
return ExprError();
}
+ bool IsDependent;
Result = BuildOverloadedArrowExpr(
- S, Base, OpLoc,
+ Base, OpLoc,
// When in a template specialization and on the first loop iteration,
// potentially give the default diagnostic (with the fixit in a
// separate note) instead of having the error reported back to here
// and giving a diagnostic with a fixit attached to the error itself.
(FirstIteration && CurFD &&
CurFD->isFunctionTemplateSpecialization())
? nullptr
- : &NoArrowOperatorFound);
+ : &NoArrowOperatorFound,
+ IsDependent);
+
+ if (IsDependent) {
+// BuildOverloadedArrowExpr sets IsDependent to indicate that we need
+// to build a dependent overloaded arrow expression.
+assert(BaseType->isDependentType());
+BaseType = Context.DependentTy;
+break;
+ }
+
if (Result.isInvalid()) {
if (NoArrowOperatorFound) {
if (FirstIteration) {
@@ -7914,6 +7914,7 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
}
return ExprError();
}
+
Base = Result.get();
if (CXXOperatorCallExpr *OpCall = dyn_cast(Base))
OperatorArrows.push_back(OpCall->getDirectCallee());
@@ -7951,7 +7952,7 @@ ExprResult Sema::ActOnStartCXXMemberReference(Scope *S,
Expr *Base,
// it's legal for the type to be incomplete if this is a pseudo-destructor
// call. We'll do more incomplete-type checks later in the lookup process,
// so just skip this check for ObjC types.
- if (!BaseType->isRecordType()) {
+ if (!isa(BaseType.getCanonicalType())) {
ObjectType = ParsedType::make(BaseType);
MayBePseudoDestructor = true;
return Base;
@@ -7969,6 +7970,10 @@ ExprResult Sema::ActOnStartCXXMemberRefe
[llvm-branch-commits] [clang] [clang-format] Correctly annotate braces in macro definition (#107352) (PR #107531)
prj- wrote: Any hope that this gets reviewed and merged for the release? https://github.com/llvm/llvm-project/pull/107531 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Release note about targets built in the Windows packages (PR #107826)
tru wrote: Yeah I'll merge it - I just do it in batches when I have time to review and integrate them all (I can't use the merge button either - you have to do it with a script ... due to reasons ...) https://github.com/llvm/llvm-project/pull/107826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 1b84796 - Revert "[Coverage] Ignore unused functions if the count is 0. (#107661)"
Author: Zequan Wu
Date: 2024-09-09T14:33:27-04:00
New Revision: 1b8479684c74caa82e0b5192a780b75f1000a9c2
URL:
https://github.com/llvm/llvm-project/commit/1b8479684c74caa82e0b5192a780b75f1000a9c2
DIFF:
https://github.com/llvm/llvm-project/commit/1b8479684c74caa82e0b5192a780b75f1000a9c2.diff
LOG: Revert "[Coverage] Ignore unused functions if the count is 0. (#107661)"
This reverts commit 6850410562123b6e4fbb039e7ba4a2325b994b84.
Added:
Modified:
llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
Removed:
compiler-rt/test/profile/instrprof-merging-2.cpp
diff --git a/compiler-rt/test/profile/instrprof-merging-2.cpp
b/compiler-rt/test/profile/instrprof-merging-2.cpp
deleted file mode 100644
index 438394f9fb239e..00
--- a/compiler-rt/test/profile/instrprof-merging-2.cpp
+++ /dev/null
@@ -1,55 +0,0 @@
-// UNSUPPORTED: target={{.*windows.*}}
-
-// clang-format off
-// RUN: split-file %s %t
-// RUN: %clangxx_profgen -fcoverage-mapping %t/test1.cpp -o %t/test1.exe
-// RUN: %clangxx_profgen -fcoverage-mapping %t/test2.cpp -o %t/test2.exe
-// RUN: env LLVM_PROFILE_FILE=%t/test1.profraw %run %t/test1.exe
-// RUN: env LLVM_PROFILE_FILE=%t/test2.profraw %run %t/test2.exe
-// RUN: llvm-profdata merge %t/test1.profraw %t/test2.profraw -o
%t/merged.profdata
-// RUN: llvm-cov show -instr-profile=%t/merged.profdata -object %t/test1.exe
%t/test2.exe | FileCheck %s
-// RUN: llvm-cov show -instr-profile=%t/merged.profdata -object %t/test2.exe
%t/test1.exe | FileCheck %s
-
-// CHECK: |struct Test {
-// CHECK-NEXT: 1| int getToTest() {
-// CHECK-NEXT: 2|for (int i = 0; i < 1; i++) {
-// CHECK-NEXT: 1| if (false) {
-// CHECK-NEXT: 0|return 1;
-// CHECK-NEXT: 0| }
-// CHECK-NEXT: 1|}
-// CHECK-NEXT: 1|if (true) {
-// CHECK-NEXT: 1| return 1;
-// CHECK-NEXT: 1|}
-// CHECK-NEXT: 0|return 1;
-// CHECK-NEXT: 1| }
-// CHECK-NEXT: |};
-// CHECK-NEXT: |
-
-#--- test.h
-struct Test {
- int getToTest() {
-for (int i = 0; i < 1; i++) {
- if (false) {
-return 1;
- }
-}
-if (true) {
- return 1;
-}
-return 1;
- }
-};
-
-#--- test1.cpp
-#include "test.h"
-int main() {
- Test t;
- t.getToTest();
- return 0;
-}
-
-#--- test2.cpp
-#include "test.h"
-int main() {
- return 0;
-}
diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
index acb7dd922ab9fa..18643c6b44485e 100644
--- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
@@ -851,7 +851,7 @@ Error CoverageMapping::loadFunctionRecord(
// won't (in which case we don't unintuitively report functions as uncovered
// when they have non-zero counts in the profile).
if (Record.MappingRegions.size() == 1 &&
- Record.MappingRegions[0].Count.isZero())
+ Record.MappingRegions[0].Count.isZero() && Counts[0] > 0)
return Error::success();
MCDCDecisionRecorder MCDCDecisions;
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
https://github.com/damyanp edited https://github.com/llvm/llvm-project/pull/104252 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
https://github.com/damyanp approved this pull request. LGTM, some nits. https://github.com/llvm/llvm-project/pull/104252 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -267,45 +267,38 @@ Examples:
@llvm.dx.handle.fromHeap.tdx.RawBuffer_v4f32_1_0(
i32 2, i1 false)
-Buffer Loads and Stores
-
-*relevant types: Buffers*
-
-We need to treat buffer loads and stores from "dx.TypedBuffer" and
-"dx.RawBuffer" separately. For TypedBuffer, we have ``llvm.dx.typedBufferLoad``
-and ``llvm.dx.typedBufferStore``, which load and store 16-byte "rows" of data
-via a simple index. For RawBuffer, we have ``llvm.dx.rawBufferPtr``, which
-return a pointer that can be indexed, loaded, and stored to as needed.
-
-The typed load and store operations always operate on exactly 16 bytes of data,
-so there are only a few valid overloads. For types that are 32-bits or smaller,
-we operate on 4-element vectors, such as ``<4 x i32>``, ``<4 x float>``, or
-``<4 x half>``. Note that in 16-bit cases each 16-bit value occupies 32-bits of
-storage. For 64-bit types we operate on 2-element vectors - ``<2 x double>`` or
-``<2 x i64>``. When a type like `Buffer` is used at the HLSL level, it
-is expected that this will operate on a single float in each 16 byte row - that
-is, a load would use the ``<4 x float>`` variant and then extract the first
-element.
-
-.. note:: In DXC, trying to operate on a ``Buffer`` crashes the
- compiler. We should probably just reject this in the frontend.
-
-The TypedBuffer intrinsics are lowered to the `bufferLoad`_ and `bufferStore`_
-operations, and the operations on the memory accessed by RawBufferPtr are
-lowered to `rawBufferLoad`_ and `rawBufferStore`_. Note that if we want to
-support DXIL versions prior to 1.2 we'll need to lower the RawBuffer loads and
-stores to the non-raw operations as well.
-
-.. note:: TODO: We need to account for `CheckAccessFullyMapped`_ here.
-
- In DXIL the load operations always return an ``i32`` status value, but this
- isn't very ergonomic when it isn't used. We can (1) bite the bullet and have
- the loads return `{%ret_type, %i32}` all the time, (2) create a variant or
- update the signature iff the status is used, or (3) hide this in a sideband
- channel somewhere. I'm leaning towards (2), but could probably be convinced
- that the ugliness of (1) is worth the simplicity.
-
+16-byte Loads, Samples, and Gathers
+---
+
+*relevant types: TypedBuffer, CBuffer, and Textures*
+
+TypedBuffer, CBuffer, and Texture loads, as well as samples and gathers, can
+return 1 to 4 elements from the given resource, to a maximum of 16 bytes of
+data. DXIL's modeling of this is influenced by DirectX and DXBC's history and
+it generally treats these operations as returning 4 32-bit values. For 16-bit
+elements the values are 16-bit values, and for 64-bit values the operations
+return 4 32-bit integers and combine them with further operations.
damyanp wrote:
> and combine them with further operations.
Feel like there should be something between "operations" and the end of the
sentence?
I think that the 4 32-bit ints are combined to make 2 64-bit values?
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -30,6 +30,9 @@ def int_dx_handle_fromBinding [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty], [IntrNoMem]>; +def int_dx_typedBufferLoad damyanp wrote: Should I expect to find the `checkbit` version in here as well? https://github.com/llvm/llvm-project/pull/104252 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -259,6 +259,114 @@ class OpLowerer {
lowerToBindAndAnnotateHandle(F);
}
+ /// Replace uses of \c V with the values in the `dx.ResRet` of \c Op. Since
we
damyanp wrote:
What is `V` in this context?
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -450,6 +462,10 @@ CallInst *DXILOpBuilder::createOp(dxil::OpCode OpCode,
ArrayRef Args,
return *Result;
}
+StructType *DXILOpBuilder::getResRetType(Type *ElementTy) {
+ return ::getResRetType(ElementTy);
damyanp wrote:
Trying to understand this pattern...it being a non-static member function would
strongly imply to me as the caller that this function somehow depends on the
internal state of DXILOpBuilder. But it doesn't. Do you think it will in the
future? Or is there some other design consideration in play?
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -259,6 +259,114 @@ class OpLowerer {
lowerToBindAndAnnotateHandle(F);
}
+ /// Replace uses of \c V with the values in the `dx.ResRet` of \c Op. Since
we
+ /// expect to be post-scalarization, make an effort to avoid vectors.
+ Error replaceResRetUses(CallInst *Intrin, CallInst *Op) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+
+Type *OldRetTy = Intrin->getType();
+
+// For scalars, we just extract the first element.
+if (!isa(OldRetTy)) {
+ Value *EVI = IRB.CreateExtractValue(Op, 0);
+ Intrin->replaceAllUsesWith(EVI);
+ Intrin->eraseFromParent();
+ return Error::success();
+}
+
+auto *VecTy = cast(OldRetTy);
+unsigned N = VecTy->getNumElements();
damyanp wrote:
`VecTy` and `N` don't seem to be used until after the line 298, IMO it'd be
clearer to have these closer to where they're used.
(And while I'm trying to read this, I'd really like to know if these values are
mutated at all by the subsequent code)
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -30,6 +30,9 @@ def int_dx_handle_fromBinding [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty], [IntrNoMem]>; +def int_dx_typedBufferLoad bogner wrote: No, I plan to add that in a follow up. https://github.com/llvm/llvm-project/pull/104252 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -450,6 +462,10 @@ CallInst *DXILOpBuilder::createOp(dxil::OpCode OpCode,
ArrayRef Args,
return *Result;
}
+StructType *DXILOpBuilder::getResRetType(Type *ElementTy) {
+ return ::getResRetType(ElementTy);
bogner wrote:
This pattern isn't great, and I expect it to go away eventually. The
`getResRetType` static function already exists and is called by other static
functions, so simply making it a member involves quite a bit of code churn.
Further, most of the uses in static functions are in code that has various
TODOs about refactoring how we use TableGen in order to simplify it, so I'd
rather not spend a lot of time on it until we actually do that.
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
https://github.com/bogner updated
https://github.com/llvm/llvm-project/pull/104252
>From 2f317012985068f7130cdf4976d8821924d404c3 Mon Sep 17 00:00:00 2001
From: Justin Bogner
Date: Mon, 9 Sep 2024 12:16:36 -0700
Subject: [PATCH] Improve comments, move code for clarity
Created using spr 1.3.5-bogner
---
llvm/docs/DirectX/DXILResources.rst| 2 +-
llvm/lib/Target/DirectX/DXILOpLowering.cpp | 15 ---
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/docs/DirectX/DXILResources.rst
b/llvm/docs/DirectX/DXILResources.rst
index 07fba4ac644eca..8e43bfaaaf32ea 100644
--- a/llvm/docs/DirectX/DXILResources.rst
+++ b/llvm/docs/DirectX/DXILResources.rst
@@ -277,7 +277,7 @@ return 1 to 4 elements from the given resource, to a
maximum of 16 bytes of
data. DXIL's modeling of this is influenced by DirectX and DXBC's history and
it generally treats these operations as returning 4 32-bit values. For 16-bit
elements the values are 16-bit values, and for 64-bit values the operations
-return 4 32-bit integers and combine them with further operations.
+return 4 32-bit integers and emit further code to construct the double.
In DXIL, these operations return `ResRet`_ and `CBufRet`_ values, are structs
containing 4 elements of the same type, and in the case of `ResRet` a 5th
diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
index 9db18a8476b07f..409a1987709d5c 100644
--- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
+++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
@@ -259,23 +259,21 @@ class OpLowerer {
lowerToBindAndAnnotateHandle(F);
}
- /// Replace uses of \c V with the values in the `dx.ResRet` of \c Op. Since
we
- /// expect to be post-scalarization, make an effort to avoid vectors.
+ /// Replace uses of \c Intrin with the values in the `dx.ResRet` of \c Op.
+ /// Since we expect to be post-scalarization, make an effort to avoid
vectors.
Error replaceResRetUses(CallInst *Intrin, CallInst *Op) {
IRBuilder<> &IRB = OpBuilder.getIRB();
-Type *OldRetTy = Intrin->getType();
+Type *OldTy = Intrin->getType();
// For scalars, we just extract the first element.
-if (!isa(OldRetTy)) {
+if (!isa(OldTy)) {
Value *EVI = IRB.CreateExtractValue(Op, 0);
Intrin->replaceAllUsesWith(EVI);
Intrin->eraseFromParent();
return Error::success();
}
-auto *VecTy = cast(OldRetTy);
-unsigned N = VecTy->getNumElements();
std::array Extracts = {};
SmallVector DynamicAccesses;
@@ -296,6 +294,9 @@ class OpLowerer {
}
}
+auto *VecTy = cast(OldTy);
+unsigned N = VecTy->getNumElements();
+
// If there's a dynamic access we need to round trip through stack memory
so
// that we don't leave vectors around.
if (!DynamicAccesses.empty()) {
@@ -331,7 +332,7 @@ class OpLowerer {
if (!Extracts[I])
Extracts[I] = IRB.CreateExtractValue(Op, I);
- Value *Vec = UndefValue::get(OldRetTy);
+ Value *Vec = UndefValue::get(OldTy);
for (int I = 0, E = N; I != E; ++I)
Vec = IRB.CreateInsertElement(Vec, Extracts[I], I);
Intrin->replaceAllUsesWith(Vec);
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[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -267,45 +267,38 @@ Examples:
@llvm.dx.handle.fromHeap.tdx.RawBuffer_v4f32_1_0(
i32 2, i1 false)
-Buffer Loads and Stores
-
-*relevant types: Buffers*
-
-We need to treat buffer loads and stores from "dx.TypedBuffer" and
-"dx.RawBuffer" separately. For TypedBuffer, we have ``llvm.dx.typedBufferLoad``
-and ``llvm.dx.typedBufferStore``, which load and store 16-byte "rows" of data
-via a simple index. For RawBuffer, we have ``llvm.dx.rawBufferPtr``, which
-return a pointer that can be indexed, loaded, and stored to as needed.
-
-The typed load and store operations always operate on exactly 16 bytes of data,
-so there are only a few valid overloads. For types that are 32-bits or smaller,
-we operate on 4-element vectors, such as ``<4 x i32>``, ``<4 x float>``, or
-``<4 x half>``. Note that in 16-bit cases each 16-bit value occupies 32-bits of
-storage. For 64-bit types we operate on 2-element vectors - ``<2 x double>`` or
-``<2 x i64>``. When a type like `Buffer` is used at the HLSL level, it
-is expected that this will operate on a single float in each 16 byte row - that
-is, a load would use the ``<4 x float>`` variant and then extract the first
-element.
-
-.. note:: In DXC, trying to operate on a ``Buffer`` crashes the
- compiler. We should probably just reject this in the frontend.
-
-The TypedBuffer intrinsics are lowered to the `bufferLoad`_ and `bufferStore`_
-operations, and the operations on the memory accessed by RawBufferPtr are
-lowered to `rawBufferLoad`_ and `rawBufferStore`_. Note that if we want to
-support DXIL versions prior to 1.2 we'll need to lower the RawBuffer loads and
-stores to the non-raw operations as well.
-
-.. note:: TODO: We need to account for `CheckAccessFullyMapped`_ here.
-
- In DXIL the load operations always return an ``i32`` status value, but this
- isn't very ergonomic when it isn't used. We can (1) bite the bullet and have
- the loads return `{%ret_type, %i32}` all the time, (2) create a variant or
- update the signature iff the status is used, or (3) hide this in a sideband
- channel somewhere. I'm leaning towards (2), but could probably be convinced
- that the ugliness of (1) is worth the simplicity.
-
+16-byte Loads, Samples, and Gathers
+---
+
+*relevant types: TypedBuffer, CBuffer, and Textures*
+
+TypedBuffer, CBuffer, and Texture loads, as well as samples and gathers, can
+return 1 to 4 elements from the given resource, to a maximum of 16 bytes of
+data. DXIL's modeling of this is influenced by DirectX and DXBC's history and
+it generally treats these operations as returning 4 32-bit values. For 16-bit
+elements the values are 16-bit values, and for 64-bit values the operations
+return 4 32-bit integers and combine them with further operations.
bogner wrote:
Updated to say that it emits code to construct a double
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -259,6 +259,114 @@ class OpLowerer {
lowerToBindAndAnnotateHandle(F);
}
+ /// Replace uses of \c V with the values in the `dx.ResRet` of \c Op. Since
we
bogner wrote:
Nice catch, should be "Intrin", the name of the first parameter. Updated.
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
https://github.com/bogner updated
https://github.com/llvm/llvm-project/pull/104252
>From 2f317012985068f7130cdf4976d8821924d404c3 Mon Sep 17 00:00:00 2001
From: Justin Bogner
Date: Mon, 9 Sep 2024 12:16:36 -0700
Subject: [PATCH 1/2] Improve comments, move code for clarity
Created using spr 1.3.5-bogner
---
llvm/docs/DirectX/DXILResources.rst| 2 +-
llvm/lib/Target/DirectX/DXILOpLowering.cpp | 15 ---
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/docs/DirectX/DXILResources.rst
b/llvm/docs/DirectX/DXILResources.rst
index 07fba4ac644eca..8e43bfaaaf32ea 100644
--- a/llvm/docs/DirectX/DXILResources.rst
+++ b/llvm/docs/DirectX/DXILResources.rst
@@ -277,7 +277,7 @@ return 1 to 4 elements from the given resource, to a
maximum of 16 bytes of
data. DXIL's modeling of this is influenced by DirectX and DXBC's history and
it generally treats these operations as returning 4 32-bit values. For 16-bit
elements the values are 16-bit values, and for 64-bit values the operations
-return 4 32-bit integers and combine them with further operations.
+return 4 32-bit integers and emit further code to construct the double.
In DXIL, these operations return `ResRet`_ and `CBufRet`_ values, are structs
containing 4 elements of the same type, and in the case of `ResRet` a 5th
diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
index 9db18a8476b07f..409a1987709d5c 100644
--- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
+++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
@@ -259,23 +259,21 @@ class OpLowerer {
lowerToBindAndAnnotateHandle(F);
}
- /// Replace uses of \c V with the values in the `dx.ResRet` of \c Op. Since
we
- /// expect to be post-scalarization, make an effort to avoid vectors.
+ /// Replace uses of \c Intrin with the values in the `dx.ResRet` of \c Op.
+ /// Since we expect to be post-scalarization, make an effort to avoid
vectors.
Error replaceResRetUses(CallInst *Intrin, CallInst *Op) {
IRBuilder<> &IRB = OpBuilder.getIRB();
-Type *OldRetTy = Intrin->getType();
+Type *OldTy = Intrin->getType();
// For scalars, we just extract the first element.
-if (!isa(OldRetTy)) {
+if (!isa(OldTy)) {
Value *EVI = IRB.CreateExtractValue(Op, 0);
Intrin->replaceAllUsesWith(EVI);
Intrin->eraseFromParent();
return Error::success();
}
-auto *VecTy = cast(OldRetTy);
-unsigned N = VecTy->getNumElements();
std::array Extracts = {};
SmallVector DynamicAccesses;
@@ -296,6 +294,9 @@ class OpLowerer {
}
}
+auto *VecTy = cast(OldTy);
+unsigned N = VecTy->getNumElements();
+
// If there's a dynamic access we need to round trip through stack memory
so
// that we don't leave vectors around.
if (!DynamicAccesses.empty()) {
@@ -331,7 +332,7 @@ class OpLowerer {
if (!Extracts[I])
Extracts[I] = IRB.CreateExtractValue(Op, I);
- Value *Vec = UndefValue::get(OldRetTy);
+ Value *Vec = UndefValue::get(OldTy);
for (int I = 0, E = N; I != E; ++I)
Vec = IRB.CreateInsertElement(Vec, Extracts[I], I);
Intrin->replaceAllUsesWith(Vec);
>From 94a48e9e7cd9b4d135015114f21d5f030f0808ca Mon Sep 17 00:00:00 2001
From: Justin Bogner
Date: Mon, 9 Sep 2024 12:20:52 -0700
Subject: [PATCH 2/2] Make VecTy and N const for clarity
Created using spr 1.3.5-bogner
---
llvm/lib/Target/DirectX/DXILOpLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
index 409a1987709d5c..df2751d99576a8 100644
--- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
+++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
@@ -294,8 +294,8 @@ class OpLowerer {
}
}
-auto *VecTy = cast(OldTy);
-unsigned N = VecTy->getNumElements();
+const auto *VecTy = cast(OldTy);
+const unsigned N = VecTy->getNumElements();
// If there's a dynamic access we need to round trip through stack memory
so
// that we don't leave vectors around.
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[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferLoad` to DXIL ops (PR #104252)
@@ -259,6 +259,114 @@ class OpLowerer {
lowerToBindAndAnnotateHandle(F);
}
+ /// Replace uses of \c V with the values in the `dx.ResRet` of \c Op. Since
we
+ /// expect to be post-scalarization, make an effort to avoid vectors.
+ Error replaceResRetUses(CallInst *Intrin, CallInst *Op) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+
+Type *OldRetTy = Intrin->getType();
+
+// For scalars, we just extract the first element.
+if (!isa(OldRetTy)) {
+ Value *EVI = IRB.CreateExtractValue(Op, 0);
+ Intrin->replaceAllUsesWith(EVI);
+ Intrin->eraseFromParent();
+ return Error::success();
+}
+
+auto *VecTy = cast(OldRetTy);
+unsigned N = VecTy->getNumElements();
bogner wrote:
I moved them closer to the use and made them const to try to make this a bit
clearer.
https://github.com/llvm/llvm-project/pull/104252
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
+ IRB.SetInsertPoint(CI);
+
+ Value *Handle =
+ createTmpHandleCast(CI->getArgOperand(0), OpBuilder.getHandleType());
+ Value *Index0 = CI->getArgOperand(1);
+ Value *Index1 = UndefValue::get(Int32Ty);
+ // For typed stores, the mask must always cover all four elements.
+ Constant *Mask = ConstantInt::get(Int8Ty, 0xF);
+
+ Value *Data = CI->getArgOperand(2);
bogner wrote:
For SPIR-V we'll generate SPIR-V operations, not DXIL ones.
`dx.typedBufferStore` is only on the DXIL path.
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
bogner wrote: Please take another look - specifically I'd like some review on the doc changes to make sure they're clear. https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/damyanp approved this pull request. https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -388,10 +432,13 @@ class OpLowerer {
case Intrinsic::dx_typedBufferLoad:
lowerTypedBufferLoad(F);
break;
+ case Intrinsic::dx_typedBufferStore:
+lowerTypedBufferStore(F);
+break;
}
Updated = true;
}
-if (Updated)
+if (Updated && !HasErrors)
damyanp wrote:
So dx_typedBufferLoad cannot fail?
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -388,10 +432,13 @@ class OpLowerer {
case Intrinsic::dx_typedBufferLoad:
lowerTypedBufferLoad(F);
break;
+ case Intrinsic::dx_typedBufferStore:
+lowerTypedBufferStore(F);
+break;
}
Updated = true;
}
-if (Updated)
+if (Updated && !HasErrors)
bogner wrote:
It can fail in the same ways any of the op lowering can fail (like say if we
just give it completely incorrect types) but I think it happens to always fail
in such a way that the cleanup wouldn't crash. The HasErrors check is added
here so that we can carry on and finish the pass and just let LLVM's error
handling propagate the error afterwards, because when `lowerTypedBufferStore`
fails it can leave the temporary casts in a bad state.
All that said, we can and should add some tests for cases where lowering loads
fails. I'll do that in a follow up change.
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [mlir] [mlir][GPU] Plumb range information through the NVVM lowterings (PR #107659)
@@ -1784,53 +1799,53 @@ def NVVM_CpAsyncBulkWaitGroupOp :
NVVM_Op<"cp.async.bulk.wait_group">,
}];
}
-def NVVM_CpAsyncBulkTensorGlobalToSharedClusterOp :
- NVVM_Op<"cp.async.bulk.tensor.shared.cluster.global",
- [DeclareOpInterfaceMethods,
+def NVVM_CpAsyncBulkTensorGlobalToSharedClusterOp :
+ NVVM_Op<"cp.async.bulk.tensor.shared.cluster.global",
+ [DeclareOpInterfaceMethods,
AttrSizedOperandSegments]>,
Arguments<(ins LLVM_PointerShared:$dstMem,
LLVM_AnyPointer:$tmaDescriptor,
Variadic:$coordinates,
- LLVM_PointerShared:$mbar,
+ LLVM_PointerShared:$mbar,
Variadic:$im2colOffsets,
Optional:$multicastMask,
Optional:$l2CacheHint,
PtxPredicate:$predicate)> {
let description = [{
-Initiates an asynchronous copy operation on the tensor data from global
-memory to shared memory.
+Initiates an asynchronous copy operation on the tensor data from global
krzysz00 wrote:
Darn editor settings, done
https://github.com/llvm/llvm-project/pull/107659
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[llvm-branch-commits] [mlir] [mlir][GPU] Plumb range information through the NVVM lowterings (PR #107659)
@@ -209,7 +209,12 @@ struct GPULaneIdOpToNVVM :
ConvertOpToLLVMPattern {
ConversionPatternRewriter &rewriter) const override {
auto loc = op->getLoc();
MLIRContext *context = rewriter.getContext();
-Value newOp = rewriter.create(loc, rewriter.getI32Type());
+LLVM::ConstantRangeAttr bounds = nullptr;
+if (std::optional upperBound = op.getUpperBound())
krzysz00 wrote:
User code - I'll have some tests shortly
https://github.com/llvm/llvm-project/pull/107659
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[llvm-branch-commits] [mlir] [mlir][GPU] Plumb range information through the NVVM lowterings (PR #107659)
@@ -699,9 +699,21 @@ gpu.module @test_module_32 {
}
gpu.module @test_module_33 {
-// CHECK-LABEL: func @kernel_with_block_size()
-// CHECK: attributes {gpu.kernel, gpu.known_block_size = array, nvvm.kernel, nvvm.maxntid = array}
- gpu.func @kernel_with_block_size() kernel attributes {known_block_size =
array} {
+// CHECK-LABEL: func @kernel_with_block_size(
+// CHECK: attributes {gpu.kernel, gpu.known_block_size = array,
nvvm.kernel, nvvm.maxntid = array}
+ gpu.func @kernel_with_block_size(%arg0: !llvm.ptr) kernel attributes
{known_block_size = array} {
krzysz00 wrote:
Yep, that code works generally
https://github.com/llvm/llvm-project/pull/107659
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -361,11 +361,60 @@ Examples: - ``i32`` - Index into the buffer +Texture and Typed Buffer Stores +--- + +*relevant types: Textures and TypedBuffer* + +The `TextureStore`_ and `BufferStore`_ DXIL operations can only be used to farzonl wrote: ```suggestion The `TextureStore`_ and `BufferStore`_ DXIL operations are only allowed to ``` https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -361,11 +361,60 @@ Examples: - ``i32`` - Index into the buffer +Texture and Typed Buffer Stores +--- + +*relevant types: Textures and TypedBuffer* + +The `TextureStore`_ and `BufferStore`_ DXIL operations can only be used to +write all 4 32-bit elements to a texture or a typed buffer. Note that both of farzonl wrote: ```suggestion write all four 32-bit elements (components) at once to a texture or a typed buffer. ``` https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -361,11 +361,60 @@ Examples: - ``i32`` - Index into the buffer +Texture and Typed Buffer Stores +--- + +*relevant types: Textures and TypedBuffer* + +The `TextureStore`_ and `BufferStore`_ DXIL operations can only be used to +write all 4 32-bit elements to a texture or a typed buffer. Note that both of +these operations do have a mask parameter, but it is documented that it must farzonl wrote: ```suggestion While both operations include a mask parameter, it is specified that the mask must ``` https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -361,11 +361,60 @@ Examples: - ``i32`` - Index into the buffer +Texture and Typed Buffer Stores +--- + +*relevant types: Textures and TypedBuffer* + +The `TextureStore`_ and `BufferStore`_ DXIL operations can only be used to +write all 4 32-bit elements to a texture or a typed buffer. Note that both of +these operations do have a mask parameter, but it is documented that it must +cover all components for these types. farzonl wrote: ```suggestion always cover all components when used with these types. ``` https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Plumb range information through the NVVM lowterings (PR #107659)
https://github.com/krzysz00 updated
https://github.com/llvm/llvm-project/pull/107659
>From c7d3804afe9a7e6325f6af230f060c19aceca09b Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak
Date: Fri, 6 Sep 2024 23:45:52 +
Subject: [PATCH 1/3] [mlir][GPU] Plumb range information through the NVVM
lowterings
Update the GPU to NVVM lowerings to correctly propagate range
information on IDs and dimension queries, etiher from
known_{block,grid}_size attributes or from `upperBound` annotations on
the operations themselves.
---
mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 283 +-
.../GPUToNVVM/LowerGpuOpsToNVVMOps.cpp| 50 +++-
.../Dialect/NVVM/LLVMIRToNVVMTranslation.cpp | 1 +
.../Conversion/GPUToNVVM/gpu-to-nvvm.mlir | 18 +-
mlir/test/Target/LLVMIR/Import/nvvmir.ll | 3 +
mlir/test/Target/LLVMIR/nvvmir.mlir | 7 +-
6 files changed, 207 insertions(+), 155 deletions(-)
diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
index 709dd922b8fa2f..66ac9f289d233b 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
@@ -86,8 +86,8 @@ class NVVM_Op traits = []> :
LLVM_OpBase {
}
-/// Base class that defines BasicPtxBuilderOpInterface.
-class NVVM_PTXBuilder_Op traits =
[DeclareOpInterfaceMethods]> :
LLVM_OpBase {
}
@@ -123,52 +123,67 @@ class NVVM_SpecialRegisterOp
traits = []> :
let assemblyFormat = "attr-dict `:` type($res)";
}
+class NVVM_SpecialRangeableRegisterOp traits =
[]> :
+ NVVM_SpecialRegisterOp {
+ let arguments = (ins OptionalAttr:$range);
+ let assemblyFormat = "(`range` $range^)? attr-dict `:` type($res)";
+ let llvmBuilder = baseLlvmBuilder # setRangeRetAttrCode #
baseLlvmBuilderCoda;
+ let mlirBuilder = baseMlirBuilder # importRangeRetAttrCode #
baseMlirBuilderCoda;
+
+ // Backwards-compatibility builder for an unspecified range.
+ let builders = [
+OpBuilder<(ins "Type":$resultType), [{
+ build($_builder, $_state, resultType, ::mlir::LLVM::ConstantRangeAttr{});
+}]>
+ ];
+}
+
//===--===//
// Lane index and range
-def NVVM_LaneIdOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.laneid">;
-def NVVM_WarpSizeOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.warpsize">;
+def NVVM_LaneIdOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.laneid">;
+def NVVM_WarpSizeOp :
NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.warpsize">;
//===--===//
// Thread index and range
-def NVVM_ThreadIdXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.tid.x">;
-def NVVM_ThreadIdYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.tid.y">;
-def NVVM_ThreadIdZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.tid.z">;
-def NVVM_BlockDimXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.x">;
-def NVVM_BlockDimYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.y">;
-def NVVM_BlockDimZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.z">;
+def NVVM_ThreadIdXOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.tid.x">;
+def NVVM_ThreadIdYOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.tid.y">;
+def NVVM_ThreadIdZOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.tid.z">;
+def NVVM_BlockDimXOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.ntid.x">;
+def NVVM_BlockDimYOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.ntid.y">;
+def NVVM_BlockDimZOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.ntid.z">;
//===--===//
// Block index and range
-def NVVM_BlockIdXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ctaid.x">;
-def NVVM_BlockIdYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ctaid.y">;
-def NVVM_BlockIdZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ctaid.z">;
-def NVVM_GridDimXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.nctaid.x">;
-def NVVM_GridDimYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.nctaid.y">;
-def NVVM_GridDimZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.nctaid.z">;
+def NVVM_BlockIdXOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.ctaid.x">;
+def NVVM_BlockIdYOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.ctaid.y">;
+def NVVM_BlockIdZOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.ctaid.z">;
+def NVVM_GridDimXOp :
NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.nctaid.x">;
+def NVVM_GridDimYOp :
NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.nctaid.y">;
+def NVVM_GridDimZOp :
NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.nctaid.z">;
//===--===//
// CTA Cluster index and range
-def NVVM_ClusterIdXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.clusterid.x">;
-def NVVM_ClusterIdYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.clusterid.y">;
-def NVVM_ClusterIdZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.clusterid.z">;
-def NVVM_ClusterDimXOp : NVVM_SpecialRegisterOp<"read
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] release/19.x: [lldb] Fix some tests that fail with system libstdc++ (#106885) (PR #107938)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/107938 Backport adf44d5c3ea03569f019740e1140c3205810b3fa Requested by: @tstellar >From ceccb786ea6247de6681ba5c37289305f06d2a08 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 6 Sep 2024 17:05:32 -0700 Subject: [PATCH] [lldb] Fix some tests that fail with system libstdc++ (#106885) This is a revert of b1fcc1840c312472cb9ccb8c4e5e02ca13b31113. These tests weren't working on Ubuntu 22.04 or Fedora 37-40. I'm not sure exactly why, but it seems like they may be incompatible with libstdc++. Also, despite the fact that the tests were using the system libstdc++, the tests were only run when libcxx was enabled. I tested this with a RelWithDebInfo build and the tests passed. Fixes #106475 (cherry picked from commit adf44d5c3ea03569f019740e1140c3205810b3fa) --- .../import-std-module/deque-dbg-info-content/Makefile | 4 +--- .../import-std-module/list-dbg-info-content/Makefile | 4 +--- .../import-std-module/vector-dbg-info-content/Makefile| 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile b/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile index 98638c56f0b98f..f938f7428468ab 100644 --- a/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile +++ b/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile @@ -1,5 +1,3 @@ -# FIXME: once the expression evaluator can handle std libraries with debug -# info, change this to USE_LIBCPP=1 -USE_SYSTEM_STDLIB := 1 +USE_LIBCPP := 1 CXX_SOURCES := main.cpp include Makefile.rules diff --git a/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile b/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile index 98638c56f0b98f..f938f7428468ab 100644 --- a/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile +++ b/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile @@ -1,5 +1,3 @@ -# FIXME: once the expression evaluator can handle std libraries with debug -# info, change this to USE_LIBCPP=1 -USE_SYSTEM_STDLIB := 1 +USE_LIBCPP := 1 CXX_SOURCES := main.cpp include Makefile.rules diff --git a/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile b/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile index 98638c56f0b98f..f938f7428468ab 100644 --- a/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile +++ b/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile @@ -1,5 +1,3 @@ -# FIXME: once the expression evaluator can handle std libraries with debug -# info, change this to USE_LIBCPP=1 -USE_SYSTEM_STDLIB := 1 +USE_LIBCPP := 1 CXX_SOURCES := main.cpp include Makefile.rules ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] release/19.x: [lldb] Fix some tests that fail with system libstdc++ (#106885) (PR #107938)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/107938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] release/19.x: [lldb] Fix some tests that fail with system libstdc++ (#106885) (PR #107938)
llvmbot wrote: @felipepiovezan What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/107938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] release/19.x: [lldb] Fix some tests that fail with system libstdc++ (#106885) (PR #107938)
llvmbot wrote: @llvm/pr-subscribers-lldb Author: None (llvmbot) Changes Backport adf44d5c3ea03569f019740e1140c3205810b3fa Requested by: @tstellar --- Full diff: https://github.com/llvm/llvm-project/pull/107938.diff 3 Files Affected: - (modified) lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile (+1-3) - (modified) lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile (+1-3) - (modified) lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile (+1-3) ``diff diff --git a/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile b/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile index 98638c56f0b98f..f938f7428468ab 100644 --- a/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile +++ b/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/Makefile @@ -1,5 +1,3 @@ -# FIXME: once the expression evaluator can handle std libraries with debug -# info, change this to USE_LIBCPP=1 -USE_SYSTEM_STDLIB := 1 +USE_LIBCPP := 1 CXX_SOURCES := main.cpp include Makefile.rules diff --git a/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile b/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile index 98638c56f0b98f..f938f7428468ab 100644 --- a/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile +++ b/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/Makefile @@ -1,5 +1,3 @@ -# FIXME: once the expression evaluator can handle std libraries with debug -# info, change this to USE_LIBCPP=1 -USE_SYSTEM_STDLIB := 1 +USE_LIBCPP := 1 CXX_SOURCES := main.cpp include Makefile.rules diff --git a/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile b/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile index 98638c56f0b98f..f938f7428468ab 100644 --- a/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile +++ b/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/Makefile @@ -1,5 +1,3 @@ -# FIXME: once the expression evaluator can handle std libraries with debug -# info, change this to USE_LIBCPP=1 -USE_SYSTEM_STDLIB := 1 +USE_LIBCPP := 1 CXX_SOURCES := main.cpp include Makefile.rules `` https://github.com/llvm/llvm-project/pull/107938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -94,6 +95,7 @@ class OpLowerer {
DiagnosticInfoUnsupported Diag(*CI->getFunction(), Message,
CI->getDebugLoc());
M.getContext().diagnose(Diag);
+HasErrors = true;
farzonl wrote:
`HasErrors ` updated in `replaceFunction` but being used in `lowerIntrinsics`
seems like it forces synchronization. That should be fine because we don't do
parallel code gen.
That said would it complicate things to much to propagate up the error from
`replaceFunction` to `lowerTypedBufferStore` to `lowerIntrinsics`? That way we
don't have behavior dependent on side effects.
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [sanitizer] Add CHECKs to validate calculated TLS range (PR #107941)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/107941 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [sanitizer] Add CHECKs to validate calculated TLS range (PR #107941)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/107941.diff
1 Files Affected:
- (modified) compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp (+4)
``diff
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp
index 666e6f3b351067..a1107ff7d24737 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp
@@ -151,6 +151,10 @@ DTLS::DTV *DTLS_on_tls_get_addr(void *arg_void, void *res,
// This may happen inside the DTOR of main thread, so just ignore it.
tls_size = 0;
}
+ if (tls_size) {
+CHECK_LE(tls_beg, reinterpret_cast(res));
+CHECK_LT(reinterpret_cast(res), tls_beg + tls_size);
+ }
dtv->beg = tls_beg;
dtv->size = tls_size;
return dtv;
``
https://github.com/llvm/llvm-project/pull/107941
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[llvm-branch-commits] [sanitizer] Add CHECKs to validate calculated TLS range (PR #107941)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/107941 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
farzonl wrote:
The thing that's throwing me here is that we have a bunch of `replaceFunction`
Lambda's and we have a replaceFunction method in `OpLowerer` and what I'm
wondering is why do we do methods sometimes and lambdas others times. further
can `lowerTypedBufferLoad` share anything with `lowerTypedBufferStore`
`replaceFunction ` if they weren't lambdas?
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [sanitizer] Add CHECKs to validate calculated TLS range (PR #107941)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/107941 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/hekota approved this pull request. https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
bogner wrote:
We aren't doing methods sometimes and lambdas others, we have a method on the
`OpLowerer` called `replaceFunction` that takes a lambda `ReplaceCall` that
replaces an individual call, and then each kind of function we want to replace
specializes behaviour through that. The idea here is that we can share the
boilerplate for looping through the users, constructing an error message, and
erasing the function itself once it's been replaced.
The other "obvious" way to structure this would be to have some kind of
"FunctionReplacer" class that does the boilerplate and then subclass it for
each of what are currently lambdas. I don't like this as much since it makes it
harder to access the shared state of the OpLowerer in that model.
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
farzonl wrote:
It would help with clarity if `OpLowerer::replaceFunction` and the specialized
replace function behaviors had different names.
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/104253 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -94,6 +95,7 @@ class OpLowerer {
DiagnosticInfoUnsupported Diag(*CI->getFunction(), Message,
CI->getDebugLoc());
M.getContext().diagnose(Diag);
+HasErrors = true;
bogner wrote:
Even if we did parallel codegen we'd surely have different instances of the
`OpLowerer` in different threads, no? In any case, I do like this suggestion
for readability reasons since updating a member variable like this is harder to
follow than control flow.
One thing that makes it tricky is that it really is easiest to turn the error
into a diagnostic in `replaceFunction` - that's where we have the context of
which call couldn't be replaced and access to its `DebugInfo`. So there are a
couple of options:
1. Create a custom `ErrorInfo` subclass so that we can propagate info about the
call instruction up. This would need to live somewhere shared between
`DXILOpLowering` and `DXILOpBuilder`.
2. Keep handling the error in `replaceFunction` but also return a `bool` to
indicate success/failure
3. Handle the error in `replaceFunction` but then return an Error anyway. This
would probably need a different `ErrorInfo` subclass so we could differentiate
between errors we handled and one's we didn't.
Option (3) just seems too messy, and option (1) adds quite a bit of code
without a lot of advantage. Option (2) is very simple but `bool Success` return
values make me sad.
Thoughts?
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
bogner wrote:
I don't understand what you mean. The lambdas don't have names, they're
arguments to `replaceFunction`.
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
https://github.com/bogner updated
https://github.com/llvm/llvm-project/pull/104253
>From d49a863313c30d3e75205dbffddc8f81980ed25b Mon Sep 17 00:00:00 2001
From: Justin Bogner
Date: Mon, 9 Sep 2024 17:55:15 -0700
Subject: [PATCH] Propagate HasErrors through return values
Created using spr 1.3.5-bogner
---
llvm/lib/Target/DirectX/DXILOpLowering.cpp | 49 --
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
index 02909c41016c72..f968cab1dccf1e 100644
--- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp
+++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp
@@ -78,13 +78,15 @@ class OpLowerer {
DXILOpBuilder OpBuilder;
DXILResourceMap &DRM;
SmallVector CleanupCasts;
- bool HasErrors = false;
public:
OpLowerer(Module &M, DXILResourceMap &DRM) : M(M), OpBuilder(M), DRM(DRM) {}
- void replaceFunction(Function &F,
- llvm::function_ref ReplaceCall) {
+ /// Replace every call to \c F using \c ReplaceCall, and then erase \c F. If
+ /// there is an error replacing a call, we emit a diagnostic and return true.
+ [[nodiscard]] bool
+ replaceFunction(Function &F,
+ llvm::function_ref ReplaceCall) {
for (User *U : make_early_inc_range(F.users())) {
CallInst *CI = dyn_cast(U);
if (!CI)
@@ -95,17 +97,18 @@ class OpLowerer {
DiagnosticInfoUnsupported Diag(*CI->getFunction(), Message,
CI->getDebugLoc());
M.getContext().diagnose(Diag);
-HasErrors = true;
-continue;
+return true;
}
}
if (F.user_empty())
F.eraseFromParent();
+return false;
}
- void replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp) {
+ [[nodiscard]]
+ bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp) {
bool IsVectorArgExpansion = isVectorArgExpansion(F);
-replaceFunction(F, [&](CallInst *CI) -> Error {
+return replaceFunction(F, [&](CallInst *CI) -> Error {
SmallVector Args;
OpBuilder.getIRB().SetInsertPoint(CI);
if (IsVectorArgExpansion) {
@@ -177,12 +180,12 @@ class OpLowerer {
CleanupCasts.clear();
}
- void lowerToCreateHandle(Function &F) {
+ [[nodiscard]] bool lowerToCreateHandle(Function &F) {
IRBuilder<> &IRB = OpBuilder.getIRB();
Type *Int8Ty = IRB.getInt8Ty();
Type *Int32Ty = IRB.getInt32Ty();
-replaceFunction(F, [&](CallInst *CI) -> Error {
+return replaceFunction(F, [&](CallInst *CI) -> Error {
IRB.SetInsertPoint(CI);
auto *It = DRM.find(CI);
@@ -207,10 +210,10 @@ class OpLowerer {
});
}
- void lowerToBindAndAnnotateHandle(Function &F) {
+ [[nodiscard]] bool lowerToBindAndAnnotateHandle(Function &F) {
IRBuilder<> &IRB = OpBuilder.getIRB();
-replaceFunction(F, [&](CallInst *CI) -> Error {
+return replaceFunction(F, [&](CallInst *CI) -> Error {
IRB.SetInsertPoint(CI);
auto *It = DRM.find(CI);
@@ -253,12 +256,11 @@ class OpLowerer {
/// Lower `dx.handle.fromBinding` intrinsics depending on the shader model
and
/// taking into account binding information from DXILResourceAnalysis.
- void lowerHandleFromBinding(Function &F) {
+ bool lowerHandleFromBinding(Function &F) {
Triple TT(Triple(M.getTargetTriple()));
if (TT.getDXILVersion() < VersionTuple(1, 6))
- lowerToCreateHandle(F);
-else
- lowerToBindAndAnnotateHandle(F);
+ return lowerToCreateHandle(F);
+return lowerToBindAndAnnotateHandle(F);
}
/// Replace uses of \c Intrin with the values in the `dx.ResRet` of \c Op.
@@ -344,11 +346,11 @@ class OpLowerer {
return Error::success();
}
- void lowerTypedBufferLoad(Function &F) {
+ [[nodiscard]] bool lowerTypedBufferLoad(Function &F) {
IRBuilder<> &IRB = OpBuilder.getIRB();
Type *Int32Ty = IRB.getInt32Ty();
-replaceFunction(F, [&](CallInst *CI) -> Error {
+return replaceFunction(F, [&](CallInst *CI) -> Error {
IRB.SetInsertPoint(CI);
Value *Handle =
@@ -370,12 +372,12 @@ class OpLowerer {
});
}
- void lowerTypedBufferStore(Function &F) {
+ [[nodiscard]] bool lowerTypedBufferStore(Function &F) {
IRBuilder<> &IRB = OpBuilder.getIRB();
Type *Int8Ty = IRB.getInt8Ty();
Type *Int32Ty = IRB.getInt32Ty();
-replaceFunction(F, [&](CallInst *CI) -> Error {
+return replaceFunction(F, [&](CallInst *CI) -> Error {
IRB.SetInsertPoint(CI);
Value *Handle =
@@ -414,6 +416,7 @@ class OpLowerer {
bool lowerIntrinsics() {
bool Updated = false;
+bool HasErrors = false;
for (Function &F : make_early_inc_range(M.functions())) {
if (!F.isDeclaration())
@@ -424,17 +427,17 @@ class OpLowerer {
continue;
#define DXIL_OP_INTRINSIC(OpCode, Intrin)
\
case Intrin:
[llvm-branch-commits] [llvm] [DirectX] Lower `@llvm.dx.typedBufferStore` to DXIL ops (PR #104253)
@@ -94,6 +95,7 @@ class OpLowerer {
DiagnosticInfoUnsupported Diag(*CI->getFunction(), Message,
CI->getDebugLoc());
M.getContext().diagnose(Diag);
+HasErrors = true;
bogner wrote:
I pushed the `bool` version for now because it's by far the simplest
https://github.com/llvm/llvm-project/pull/104253
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[llvm-branch-commits] [llvm] release/19.x: [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432) (PR #107945)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/107945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432) (PR #107945)
llvmbot wrote: @wangleiat What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/107945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432) (PR #107945)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/107945
Backport a111f9119a5ec77c19a514ec09454218f739454f
Requested by: @dtcxzyw
>From 7b4ab2233655a30cf04d52ba98a707d1b6cb3036 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 10 Sep 2024 09:19:39 +0800
Subject: [PATCH] [LoongArch][ISel] Check the number of sign bits in
`PatGprGpr_32` (#107432)
After https://github.com/llvm/llvm-project/pull/92205, LoongArch ISel
selects `div.w` for `trunc i64 (sdiv i64 3202030857, (sext i32 X to
i64)) to i32`. It is incorrect since `3202030857` is not a signed 32-bit
constant. It will produce wrong result when `X == 2`:
https://alive2.llvm.org/ce/z/pzfGZZ
This patch adds additional `sexti32` checks to operands of
`PatGprGpr_32`.
Alive2 proof: https://alive2.llvm.org/ce/z/AkH5Mp
Fix #107414.
(cherry picked from commit a111f9119a5ec77c19a514ec09454218f739454f)
---
.../Target/LoongArch/LoongArchInstrInfo.td| 5 +-
.../ir-instruction/sdiv-udiv-srem-urem.ll | 67 ++-
2 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index ef647a42778737..339d50bd819217 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -1065,10 +1065,13 @@ def RDTIME_D : RDTIME_2R<0x6800>;
/// Generic pattern classes
+def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
+ return cast(N->getOperand(1))->getVT().bitsLE(MVT::i32);
+}]>;
class PatGprGpr
: Pat<(OpNode GPR:$rj, GPR:$rk), (Inst GPR:$rj, GPR:$rk)>;
class PatGprGpr_32
-: Pat<(sext_inreg (OpNode GPR:$rj, GPR:$rk), i32), (Inst GPR:$rj,
GPR:$rk)>;
+: Pat<(sext_inreg (OpNode (assertsexti32 GPR:$rj), (assertsexti32
GPR:$rk)), i32), (Inst GPR:$rj, GPR:$rk)>;
class PatGpr
: Pat<(OpNode GPR:$rj), (Inst GPR:$rj)>;
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
b/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
index ab3eec240db3c1..c22acdb4969071 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
@@ -191,7 +191,8 @@ define signext i32 @sdiv_si32_ui32_ui32(i32 %a, i32 %b) {
; LA64: # %bb.0: # %entry
; LA64-NEXT:addi.w $a1, $a1, 0
; LA64-NEXT:addi.w $a0, $a0, 0
-; LA64-NEXT:div.w $a0, $a0, $a1
+; LA64-NEXT:div.d $a0, $a0, $a1
+; LA64-NEXT:addi.w $a0, $a0, 0
; LA64-NEXT:ret
;
; LA32-TRAP-LABEL: sdiv_si32_ui32_ui32:
@@ -207,11 +208,12 @@ define signext i32 @sdiv_si32_ui32_ui32(i32 %a, i32 %b) {
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT:addi.w $a1, $a1, 0
; LA64-TRAP-NEXT:addi.w $a0, $a0, 0
-; LA64-TRAP-NEXT:div.w $a0, $a0, $a1
+; LA64-TRAP-NEXT:div.d $a0, $a0, $a1
; LA64-TRAP-NEXT:bnez $a1, .LBB5_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT:break 7
; LA64-TRAP-NEXT: .LBB5_2: # %entry
+; LA64-TRAP-NEXT:addi.w $a0, $a0, 0
; LA64-TRAP-NEXT:ret
entry:
%r = sdiv i32 %a, %b
@@ -1151,3 +1153,64 @@ entry:
%r = urem i64 %a, %b
ret i64 %r
}
+
+define signext i32 @pr107414(i32 signext %x) {
+; LA32-LABEL: pr107414:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:move $a2, $a0
+; LA32-NEXT:srai.w $a3, $a0, 31
+; LA32-NEXT:lu12i.w $a0, -266831
+; LA32-NEXT:ori $a0, $a0, 3337
+; LA32-NEXT:move $a1, $zero
+; LA32-NEXT:bl %plt(__divdi3)
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: pr107414:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT:lu12i.w $a1, -266831
+; LA64-NEXT:ori $a1, $a1, 3337
+; LA64-NEXT:lu32i.d $a1, 0
+; LA64-NEXT:div.d $a0, $a1, $a0
+; LA64-NEXT:addi.w $a0, $a0, 0
+; LA64-NEXT:ret
+;
+; LA32-TRAP-LABEL: pr107414:
+; LA32-TRAP: # %bb.0: # %entry
+; LA32-TRAP-NEXT:addi.w $sp, $sp, -16
+; LA32-TRAP-NEXT:.cfi_def_cfa_offset 16
+; LA32-TRAP-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-TRAP-NEXT:.cfi_offset 1, -4
+; LA32-TRAP-NEXT:move $a2, $a0
+; LA32-TRAP-NEXT:srai.w $a3, $a0, 31
+; LA32-TRAP-NEXT:lu12i.w $a0, -266831
+; LA32-TRAP-NEXT:ori $a0, $a0, 3337
+; LA32-TRAP-NEXT:move $a1, $zero
+; LA32-TRAP-NEXT:bl %plt(__divdi3)
+; LA32-TRAP-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-TRAP-NEXT:addi.w $sp, $sp, 16
+; LA32-TRAP-NEXT:ret
+;
+; LA64-TRAP-LABEL: pr107414:
+; LA64-TRAP: # %bb.0: # %entry
+; LA64-TRAP-NEXT:lu12i.w $a1, -266831
+; LA64-TRAP-NEXT:ori $a1, $a1, 3337
+; LA64-TRAP-NEXT:lu32i.d $a1, 0
+; LA64-TRAP-NEXT:div.d $a1, $a1, $a0
+; LA64-TRAP-NEXT:bnez $a0,
[llvm-branch-commits] [llvm] release/19.x: [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432) (PR #107945)
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: None (llvmbot)
Changes
Backport a111f9119a5ec77c19a514ec09454218f739454f
Requested by: @dtcxzyw
---
Full diff: https://github.com/llvm/llvm-project/pull/107945.diff
2 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.td (+4-1)
- (modified) llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
(+65-2)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index ef647a42778737..339d50bd819217 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -1065,10 +1065,13 @@ def RDTIME_D : RDTIME_2R<0x6800>;
/// Generic pattern classes
+def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
+ return cast(N->getOperand(1))->getVT().bitsLE(MVT::i32);
+}]>;
class PatGprGpr
: Pat<(OpNode GPR:$rj, GPR:$rk), (Inst GPR:$rj, GPR:$rk)>;
class PatGprGpr_32
-: Pat<(sext_inreg (OpNode GPR:$rj, GPR:$rk), i32), (Inst GPR:$rj,
GPR:$rk)>;
+: Pat<(sext_inreg (OpNode (assertsexti32 GPR:$rj), (assertsexti32
GPR:$rk)), i32), (Inst GPR:$rj, GPR:$rk)>;
class PatGpr
: Pat<(OpNode GPR:$rj), (Inst GPR:$rj)>;
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
b/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
index ab3eec240db3c1..c22acdb4969071 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
@@ -191,7 +191,8 @@ define signext i32 @sdiv_si32_ui32_ui32(i32 %a, i32 %b) {
; LA64: # %bb.0: # %entry
; LA64-NEXT:addi.w $a1, $a1, 0
; LA64-NEXT:addi.w $a0, $a0, 0
-; LA64-NEXT:div.w $a0, $a0, $a1
+; LA64-NEXT:div.d $a0, $a0, $a1
+; LA64-NEXT:addi.w $a0, $a0, 0
; LA64-NEXT:ret
;
; LA32-TRAP-LABEL: sdiv_si32_ui32_ui32:
@@ -207,11 +208,12 @@ define signext i32 @sdiv_si32_ui32_ui32(i32 %a, i32 %b) {
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT:addi.w $a1, $a1, 0
; LA64-TRAP-NEXT:addi.w $a0, $a0, 0
-; LA64-TRAP-NEXT:div.w $a0, $a0, $a1
+; LA64-TRAP-NEXT:div.d $a0, $a0, $a1
; LA64-TRAP-NEXT:bnez $a1, .LBB5_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT:break 7
; LA64-TRAP-NEXT: .LBB5_2: # %entry
+; LA64-TRAP-NEXT:addi.w $a0, $a0, 0
; LA64-TRAP-NEXT:ret
entry:
%r = sdiv i32 %a, %b
@@ -1151,3 +1153,64 @@ entry:
%r = urem i64 %a, %b
ret i64 %r
}
+
+define signext i32 @pr107414(i32 signext %x) {
+; LA32-LABEL: pr107414:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:move $a2, $a0
+; LA32-NEXT:srai.w $a3, $a0, 31
+; LA32-NEXT:lu12i.w $a0, -266831
+; LA32-NEXT:ori $a0, $a0, 3337
+; LA32-NEXT:move $a1, $zero
+; LA32-NEXT:bl %plt(__divdi3)
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: pr107414:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT:lu12i.w $a1, -266831
+; LA64-NEXT:ori $a1, $a1, 3337
+; LA64-NEXT:lu32i.d $a1, 0
+; LA64-NEXT:div.d $a0, $a1, $a0
+; LA64-NEXT:addi.w $a0, $a0, 0
+; LA64-NEXT:ret
+;
+; LA32-TRAP-LABEL: pr107414:
+; LA32-TRAP: # %bb.0: # %entry
+; LA32-TRAP-NEXT:addi.w $sp, $sp, -16
+; LA32-TRAP-NEXT:.cfi_def_cfa_offset 16
+; LA32-TRAP-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-TRAP-NEXT:.cfi_offset 1, -4
+; LA32-TRAP-NEXT:move $a2, $a0
+; LA32-TRAP-NEXT:srai.w $a3, $a0, 31
+; LA32-TRAP-NEXT:lu12i.w $a0, -266831
+; LA32-TRAP-NEXT:ori $a0, $a0, 3337
+; LA32-TRAP-NEXT:move $a1, $zero
+; LA32-TRAP-NEXT:bl %plt(__divdi3)
+; LA32-TRAP-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-TRAP-NEXT:addi.w $sp, $sp, 16
+; LA32-TRAP-NEXT:ret
+;
+; LA64-TRAP-LABEL: pr107414:
+; LA64-TRAP: # %bb.0: # %entry
+; LA64-TRAP-NEXT:lu12i.w $a1, -266831
+; LA64-TRAP-NEXT:ori $a1, $a1, 3337
+; LA64-TRAP-NEXT:lu32i.d $a1, 0
+; LA64-TRAP-NEXT:div.d $a1, $a1, $a0
+; LA64-TRAP-NEXT:bnez $a0, .LBB32_2
+; LA64-TRAP-NEXT: # %bb.1: # %entry
+; LA64-TRAP-NEXT:break 7
+; LA64-TRAP-NEXT: .LBB32_2: # %entry
+; LA64-TRAP-NEXT:addi.w $a0, $a1, 0
+; LA64-TRAP-NEXT:ret
+entry:
+ %conv = sext i32 %x to i64
+ %div = sdiv i64 3202030857, %conv
+ %conv1 = trunc i64 %div to i32
+ ret i32 %conv1
+}
``
https://github.com/llvm/llvm-project/pull/107945
___
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[llvm-branch-commits] [llvm] release/19.x: [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432) (PR #107945)
https://github.com/wangleiat approved this pull request. https://github.com/llvm/llvm-project/pull/107945 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Codegen for concat_vectors with LASX (PR #107948)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/107948
Backport 1ca411ca451e0e86caf9207779616f32ed9fd908
Requested by: @wangleiat
>From 9cd12fa1c545bea1c61bb1d85b451b5f391aac4e Mon Sep 17 00:00:00 2001
From: wanglei
Date: Tue, 10 Sep 2024 09:28:15 +0800
Subject: [PATCH] [LoongArch] Codegen for concat_vectors with LASX
Fixes: #107355
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/107523
(cherry picked from commit 1ca411ca451e0e86caf9207779616f32ed9fd908)
---
.../LoongArch/LoongArchISelLowering.cpp | 1 +
.../LoongArch/LoongArchLASXInstrInfo.td | 6
.../CodeGen/LoongArch/lasx/issue107355.ll | 35 +++
3 files changed, 42 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index d80509cf39849e..93edafaff553ba 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -295,6 +295,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+ setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index 6f1969bf8cae05..0a220a0319bc3b 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1789,6 +1789,12 @@ def : Pat<(v4i32 (fp_to_uint (v4f64 LASX256:$vj))),
v4f64:$vj)),
sub_128)>;
+// XVPERMI_Q
+foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in
+def : Pat<(vt (concat_vectors LSX128:$vd, LSX128:$vj)),
+ (XVPERMI_Q (SUBREG_TO_REG (i64 0), LSX128:$vd, sub_128),
+ (SUBREG_TO_REG (i64 0), LSX128:$vj, sub_128), 2)>;
+
} // Predicates = [HasExtLASX]
/// Intrinsic pattern
diff --git a/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
new file mode 100644
index 00..818bd4311615d3
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+;; Without this patch(codegen for concat_vectors), the test will hang.
+@g_156 = external global [12 x i32]
+@g_490 = external global i32
+@g_813 = external global i32
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:pcalau12i $a0, %got_pc_hi20(g_156)
+; CHECK-NEXT:ld.d $a0, $a0, %got_pc_lo12(g_156)
+; CHECK-NEXT:pcalau12i $a1, %got_pc_hi20(g_490)
+; CHECK-NEXT:ld.d $a1, $a1, %got_pc_lo12(g_490)
+; CHECK-NEXT:ld.w $a2, $a0, 24
+; CHECK-NEXT:pcalau12i $a3, %got_pc_hi20(g_813)
+; CHECK-NEXT:ld.d $a3, $a3, %got_pc_lo12(g_813)
+; CHECK-NEXT:st.w $zero, $a1, 0
+; CHECK-NEXT:st.w $a2, $a3, 0
+; CHECK-NEXT:vrepli.b $vr0, 0
+; CHECK-NEXT:vst $vr0, $a0, 32
+; CHECK-NEXT:xvpermi.q $xr0, $xr0, 2
+; CHECK-NEXT:xvst $xr0, $a0, 0
+; CHECK-NEXT:st.w $zero, $a0, 20
+; CHECK-NEXT:ret
+entry:
+ store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
+ store i32 0, ptr @g_490, align 4
+ %0 = load i32, ptr getelementptr inbounds (i8, ptr @g_156, i64 24), align 4
+ store i32 %0, ptr @g_813, align 4
+ tail call void @llvm.memset.p0.i64(ptr @g_156, i8 0, i64 48, i1 false)
+ store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
+ ret void
+}
___
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[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Codegen for concat_vectors with LASX (PR #107948)
llvmbot wrote: @SixWeining What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/107948 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Codegen for concat_vectors with LASX (PR #107948)
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: None (llvmbot)
Changes
Backport 1ca411ca451e0e86caf9207779616f32ed9fd908
Requested by: @wangleiat
---
Full diff: https://github.com/llvm/llvm-project/pull/107948.diff
3 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+1)
- (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+6)
- (added) llvm/test/CodeGen/LoongArch/lasx/issue107355.ll (+35)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index d80509cf39849e..93edafaff553ba 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -295,6 +295,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+ setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index 6f1969bf8cae05..0a220a0319bc3b 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1789,6 +1789,12 @@ def : Pat<(v4i32 (fp_to_uint (v4f64 LASX256:$vj))),
v4f64:$vj)),
sub_128)>;
+// XVPERMI_Q
+foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in
+def : Pat<(vt (concat_vectors LSX128:$vd, LSX128:$vj)),
+ (XVPERMI_Q (SUBREG_TO_REG (i64 0), LSX128:$vd, sub_128),
+ (SUBREG_TO_REG (i64 0), LSX128:$vj, sub_128), 2)>;
+
} // Predicates = [HasExtLASX]
/// Intrinsic pattern
diff --git a/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
new file mode 100644
index 00..818bd4311615d3
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+;; Without this patch(codegen for concat_vectors), the test will hang.
+@g_156 = external global [12 x i32]
+@g_490 = external global i32
+@g_813 = external global i32
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:pcalau12i $a0, %got_pc_hi20(g_156)
+; CHECK-NEXT:ld.d $a0, $a0, %got_pc_lo12(g_156)
+; CHECK-NEXT:pcalau12i $a1, %got_pc_hi20(g_490)
+; CHECK-NEXT:ld.d $a1, $a1, %got_pc_lo12(g_490)
+; CHECK-NEXT:ld.w $a2, $a0, 24
+; CHECK-NEXT:pcalau12i $a3, %got_pc_hi20(g_813)
+; CHECK-NEXT:ld.d $a3, $a3, %got_pc_lo12(g_813)
+; CHECK-NEXT:st.w $zero, $a1, 0
+; CHECK-NEXT:st.w $a2, $a3, 0
+; CHECK-NEXT:vrepli.b $vr0, 0
+; CHECK-NEXT:vst $vr0, $a0, 32
+; CHECK-NEXT:xvpermi.q $xr0, $xr0, 2
+; CHECK-NEXT:xvst $xr0, $a0, 0
+; CHECK-NEXT:st.w $zero, $a0, 20
+; CHECK-NEXT:ret
+entry:
+ store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
+ store i32 0, ptr @g_490, align 4
+ %0 = load i32, ptr getelementptr inbounds (i8, ptr @g_156, i64 24), align 4
+ store i32 %0, ptr @g_813, align 4
+ tail call void @llvm.memset.p0.i64(ptr @g_156, i8 0, i64 48, i1 false)
+ store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
+ ret void
+}
``
https://github.com/llvm/llvm-project/pull/107948
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[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Codegen for concat_vectors with LASX (PR #107948)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/107948 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Codegen for concat_vectors with LASX (PR #107948)
https://github.com/SixWeining approved this pull request. https://github.com/llvm/llvm-project/pull/107948 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] release/19.x: [lldb] Fix some tests that fail with system libstdc++ (#106885) (PR #107938)
JDevlieghere wrote: I'm supportive of merging this but only once we've decorated the test accordingly (CC @Michael137). Currently this causes a test failure on Apple Silicon: https://ci.swift.org/view/all/job/llvm.org/view/LLDB/job/as-lldb-cmake/ https://github.com/llvm/llvm-project/pull/107938 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Drop blocks without profile in BAT YAML (PR #107970)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/107970 Align BAT YAML (DataAggregator) to YAMLProfileWriter which drops blocks without profile: https://github.com/llvm/llvm-project/blob/main/bolt/lib/Profile/YAMLProfileWriter.cpp#L162-L176 Test Plan: NFCI ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Drop blocks without profile in BAT YAML (PR #107970)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
Align BAT YAML (DataAggregator) to YAMLProfileWriter which drops blocks
without profile:
https://github.com/llvm/llvm-project/blob/main/bolt/lib/Profile/YAMLProfileWriter.cpp#L162-L176
Test Plan: NFCI
---
Full diff: https://github.com/llvm/llvm-project/pull/107970.diff
1 Files Affected:
- (modified) bolt/lib/Profile/DataAggregator.cpp (+9-5)
``diff
diff --git a/bolt/lib/Profile/DataAggregator.cpp
b/bolt/lib/Profile/DataAggregator.cpp
index 10d745cc69824b..4aeeb1daab1b94 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -2427,11 +2427,15 @@ std::error_code
DataAggregator::writeBATYAML(BinaryContext &BC,
}
}
}
- // Drop blocks without a hash, won't be useful for stale matching.
- llvm::erase_if(YamlBF.Blocks,
- [](const yaml::bolt::BinaryBasicBlockProfile &YamlBB) {
- return YamlBB.Hash == (yaml::Hex64)0;
- });
+ // Skip printing if there's no profile data
+ llvm::erase_if(
+ YamlBF.Blocks, [](const yaml::bolt::BinaryBasicBlockProfile &YamlBB)
{
+auto HasCount = [](const auto &SI) { return SI.Count; };
+bool HasAnyCount = YamlBB.ExecCount ||
+ llvm::any_of(YamlBB.Successors, HasCount) ||
+ llvm::any_of(YamlBB.CallSites, HasCount);
+return !HasAnyCount;
+ });
BP.Functions.emplace_back(YamlBF);
}
}
``
https://github.com/llvm/llvm-project/pull/107970
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[llvm-branch-commits] [llvm] [BOLT] Add pseudo probe inline tree to YAML profile (PR #107137)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/107137
>From 50c021b09950cf7d6a8f25b1ac0dec246f2325f5 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Tue, 3 Sep 2024 11:38:04 -0700
Subject: [PATCH] update pseudoprobe-decoding-inline.test
Created using spr 1.3.4
---
.../test/X86/pseudoprobe-decoding-inline.test | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/bolt/test/X86/pseudoprobe-decoding-inline.test
b/bolt/test/X86/pseudoprobe-decoding-inline.test
index 1fdd00c7ef6c4b..629dd84ab8e1dc 100644
--- a/bolt/test/X86/pseudoprobe-decoding-inline.test
+++ b/bolt/test/X86/pseudoprobe-decoding-inline.test
@@ -14,29 +14,38 @@
# RUN: FileCheck --input-file %t.yaml2 %s --check-prefix CHECK-YAML
# CHECK-YAML: name: bar
# CHECK-YAML: - bid: 0
-# CHECK-YAML: pseudo_probes: [ { guid: 0xE413754A191DB537, id: 1, type: 0 },
{ guid: 0xE413754A191DB537, id: 4, type: 0 } ]
-# CHECK-YAML: guid: 0xE413754A191DB537
-# CHECK-YAML: pseudo_probe_desc_hash: 0x10E852DA94
+# CHECK-YAML: pseudo_probes:
+# CHECK-YAML-NEXT: - { id: 1, type: 0
+# CHECK-YAML-NEXT: - { id: 4, type: 0
+# CHECK-YAML: inline_tree:
+# CHECK-YAML-NEXT: - { guid: 0xE413754A191DB537, hash: 0x10E852DA94, id: 0 }
#
# CHECK-YAML: name: foo
# CHECK-YAML: - bid: 0
-# CHECK-YAML: pseudo_probes: [ { guid: 0x5CF8C24CDB18BDAC, id: 1, type: 0 },
{ guid: 0x5CF8C24CDB18BDAC, id: 2, type: 0 } ]
-# CHECK-YAML: guid: 0x5CF8C24CDB18BDAC
-# CHECK-YAML: pseudo_probe_desc_hash: 0x200205A19C5B4
+# CHECK-YAML: pseudo_probes:
+# CHECK-YAML-NEXT: - { id: 1, type: 0 }
+# CHECK-YAML-NEXT: - { id: 2, type: 0 }
+# CHECK-YAML: inline_tree:
+# CHECK-YAML-NEXT: - { guid: 0x5CF8C24CDB18BDAC, hash: 0x200205A19C5B4, id:
0 }
+# CHECK-YAML-NEXT: - { guid: 0xE413754A191DB537, hash: 0x10E852DA94, id: 1,
callsite: 8 }
#
# CHECK-YAML: name: main
# CHECK-YAML: - bid: 0
-# CHECK-YAML: pseudo_probes: [ { guid: 0xDB956436E78DD5FA, id: 1, type: 0 },
{ guid: 0x5CF8C24CDB18BDAC, id: 1, type: 0 }, { guid: 0x5CF8C24CDB18BDAC, id:
2, type: 0 } ]
-# CHECK-YAML: guid: 0xDB956436E78DD5FA
-# CHECK-YAML: pseudo_probe_desc_hash: 0x1
+# CHECK-YAML: pseudo_probes:
+# CHECK-YAML-NEXT: - { id: 1, type: 0 }
+# CHECK-YAML-NEXT: - { id: 1, type: 0, inline_tree_id: 1 }
+# CHECK-YAML-NEXT: - { id: 2, type: 0, inline_tree_id: 1 }
+# CHECK-YAML: inline_tree:
+# CHECK-YAML-NEXT: - { guid: 0xDB956436E78DD5FA, hash: 0x1, id:
0 }
+# CHECK-YAML-NEXT: - { guid: 0x5CF8C24CDB18BDAC, hash: 0x200205A19C5B4, id:
1, callsite: 2 }
+# CHECK-YAML-NEXT: - { guid: 0xE413754A191DB537, hash: 0x10E852DA94, id: 2,
parent: 1, callsite: 8 }
#
## Check that without --profile-write-pseudo-probes option, no pseudo probes
are
## generated
# RUN: perf2bolt
%S/../../../llvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfbin
-p %t.preagg --pa -w %t.yaml -o %t.fdata
# RUN: FileCheck --input-file %t.yaml %s --check-prefix CHECK-NO-OPT
# CHECK-NO-OPT-NOT: pseudo_probes
-# CHECK-NO-OPT-NOT: guid
-# CHECK-NO-OPT-NOT: pseudo_probe_desc_hash
+# CHECK-NO-OPT-NOT: inline_tree
CHECK: Report of decoding input pseudo probe binaries
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[llvm-branch-commits] [llvm] [BOLT] Add pseudo probe inline tree to YAML profile (PR #107137)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/107137
>From 50c021b09950cf7d6a8f25b1ac0dec246f2325f5 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Tue, 3 Sep 2024 11:38:04 -0700
Subject: [PATCH] update pseudoprobe-decoding-inline.test
Created using spr 1.3.4
---
.../test/X86/pseudoprobe-decoding-inline.test | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/bolt/test/X86/pseudoprobe-decoding-inline.test
b/bolt/test/X86/pseudoprobe-decoding-inline.test
index 1fdd00c7ef6c4b..629dd84ab8e1dc 100644
--- a/bolt/test/X86/pseudoprobe-decoding-inline.test
+++ b/bolt/test/X86/pseudoprobe-decoding-inline.test
@@ -14,29 +14,38 @@
# RUN: FileCheck --input-file %t.yaml2 %s --check-prefix CHECK-YAML
# CHECK-YAML: name: bar
# CHECK-YAML: - bid: 0
-# CHECK-YAML: pseudo_probes: [ { guid: 0xE413754A191DB537, id: 1, type: 0 },
{ guid: 0xE413754A191DB537, id: 4, type: 0 } ]
-# CHECK-YAML: guid: 0xE413754A191DB537
-# CHECK-YAML: pseudo_probe_desc_hash: 0x10E852DA94
+# CHECK-YAML: pseudo_probes:
+# CHECK-YAML-NEXT: - { id: 1, type: 0
+# CHECK-YAML-NEXT: - { id: 4, type: 0
+# CHECK-YAML: inline_tree:
+# CHECK-YAML-NEXT: - { guid: 0xE413754A191DB537, hash: 0x10E852DA94, id: 0 }
#
# CHECK-YAML: name: foo
# CHECK-YAML: - bid: 0
-# CHECK-YAML: pseudo_probes: [ { guid: 0x5CF8C24CDB18BDAC, id: 1, type: 0 },
{ guid: 0x5CF8C24CDB18BDAC, id: 2, type: 0 } ]
-# CHECK-YAML: guid: 0x5CF8C24CDB18BDAC
-# CHECK-YAML: pseudo_probe_desc_hash: 0x200205A19C5B4
+# CHECK-YAML: pseudo_probes:
+# CHECK-YAML-NEXT: - { id: 1, type: 0 }
+# CHECK-YAML-NEXT: - { id: 2, type: 0 }
+# CHECK-YAML: inline_tree:
+# CHECK-YAML-NEXT: - { guid: 0x5CF8C24CDB18BDAC, hash: 0x200205A19C5B4, id:
0 }
+# CHECK-YAML-NEXT: - { guid: 0xE413754A191DB537, hash: 0x10E852DA94, id: 1,
callsite: 8 }
#
# CHECK-YAML: name: main
# CHECK-YAML: - bid: 0
-# CHECK-YAML: pseudo_probes: [ { guid: 0xDB956436E78DD5FA, id: 1, type: 0 },
{ guid: 0x5CF8C24CDB18BDAC, id: 1, type: 0 }, { guid: 0x5CF8C24CDB18BDAC, id:
2, type: 0 } ]
-# CHECK-YAML: guid: 0xDB956436E78DD5FA
-# CHECK-YAML: pseudo_probe_desc_hash: 0x1
+# CHECK-YAML: pseudo_probes:
+# CHECK-YAML-NEXT: - { id: 1, type: 0 }
+# CHECK-YAML-NEXT: - { id: 1, type: 0, inline_tree_id: 1 }
+# CHECK-YAML-NEXT: - { id: 2, type: 0, inline_tree_id: 1 }
+# CHECK-YAML: inline_tree:
+# CHECK-YAML-NEXT: - { guid: 0xDB956436E78DD5FA, hash: 0x1, id:
0 }
+# CHECK-YAML-NEXT: - { guid: 0x5CF8C24CDB18BDAC, hash: 0x200205A19C5B4, id:
1, callsite: 2 }
+# CHECK-YAML-NEXT: - { guid: 0xE413754A191DB537, hash: 0x10E852DA94, id: 2,
parent: 1, callsite: 8 }
#
## Check that without --profile-write-pseudo-probes option, no pseudo probes
are
## generated
# RUN: perf2bolt
%S/../../../llvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfbin
-p %t.preagg --pa -w %t.yaml -o %t.fdata
# RUN: FileCheck --input-file %t.yaml %s --check-prefix CHECK-NO-OPT
# CHECK-NO-OPT-NOT: pseudo_probes
-# CHECK-NO-OPT-NOT: guid
-# CHECK-NO-OPT-NOT: pseudo_probe_desc_hash
+# CHECK-NO-OPT-NOT: inline_tree
CHECK: Report of decoding input pseudo probe binaries
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