[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
@@ -841,6 +866,9 @@ void CodeGenVTables::addVTableComponent(ConstantArrayBuilder &builder, if (FnAS != GVAS) fnPtr = llvm::ConstantExpr::getAddrSpaceCast(fnPtr, CGM.GlobalsInt8PtrTy); + if (auto &schema = asl wrote: ```suggestion if (const auto &Schema = ``` https://github.com/llvm/llvm-project/pull/94056 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
@@ -841,6 +866,9 @@ void CodeGenVTables::addVTableComponent(ConstantArrayBuilder &builder, if (FnAS != GVAS) fnPtr = llvm::ConstantExpr::getAddrSpaceCast(fnPtr, CGM.GlobalsInt8PtrTy); + if (auto &schema = + CGM.getCodeGenOpts().PointerAuth.CXXVirtualFunctionPointers) +return builder.addSignedPointer(fnPtr, schema, GD, QualType()); asl wrote: ```suggestion return builder.addSignedPointer(fnPtr, Schema, GD, QualType()); ``` https://github.com/llvm/llvm-project/pull/94056 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
https://github.com/asl edited https://github.com/llvm/llvm-project/pull/94056 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
@@ -3063,3 +3063,66 @@ void CodeGenFunction::EmitPointerAuthOperandBundle(
llvm::Value *args[] = {key, discriminator};
bundles.emplace_back("ptrauth", args);
}
+
+static llvm::Value *EmitPointerAuthCommon(CodeGenFunction &CGF,
asl wrote:
ditto about code style
https://github.com/llvm/llvm-project/pull/94056
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[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
@@ -2456,10 +2456,20 @@ class CodeGenFunction : public CodeGenTypeCache {
void InitializeVTablePointers(const CXXRecordDecl *ClassDecl);
+ // VTableTrapMode - whether we guarantee that loading the
+ // vtable is guaranteed to trap on authentication failure,
+ // even if the resulting vtable pointer is unused.
+ enum class VTableAuthMode {
+Authenticate,
+MustTrap,
+UnsafeUbsanStrip // Should only be used for Vptr UBSan check
+ };
/// GetVTablePtr - Return the Value of the vtable pointer member pointed
/// to by This.
- llvm::Value *GetVTablePtr(Address This, llvm::Type *VTableTy,
-const CXXRecordDecl *VTableClass);
+ llvm::Value *
+ GetVTablePtr(Address This, llvm::Type *VTableTy,
+ const CXXRecordDecl *VTableClass,
+ VTableAuthMode authMode = VTableAuthMode::Authenticate);
asl wrote:
```suggestion
VTableAuthMode AuthMode = VTableAuthMode::Authenticate);
```
https://github.com/llvm/llvm-project/pull/94056
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[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
@@ -4406,10 +4416,19 @@ class CodeGenFunction : public CodeGenTypeCache {
}
bool isPointerKnownNonNull(const Expr *E);
+
+ /// Create the discriminator from the storage address and the entity hash.
+ llvm::Value *EmitPointerAuthBlendDiscriminator(llvm::Value *storageAddress,
asl wrote:
```suggestion
llvm::Value *EmitPointerAuthBlendDiscriminator(llvm::Value *StorageAddress,
```
https://github.com/llvm/llvm-project/pull/94056
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[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
@@ -4406,10 +4416,19 @@ class CodeGenFunction : public CodeGenTypeCache {
}
bool isPointerKnownNonNull(const Expr *E);
+
+ /// Create the discriminator from the storage address and the entity hash.
+ llvm::Value *EmitPointerAuthBlendDiscriminator(llvm::Value *storageAddress,
+ llvm::Value *discriminator);
asl wrote:
```suggestion
llvm::Value *Discriminator);
```
https://github.com/llvm/llvm-project/pull/94056
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[llvm-branch-commits] [llvm] [Support] Integrate SipHash.cpp into libSupport. (PR #94394)
kbeyls wrote: > So, regarding big-endian things. Original siphash is always "little-endian" > regardless of the host platform. On big endian hosts it essentially does byte > swap in the end. We do not have it here, so we will end with different hashes > on platforms with different endianness. > > From the pauth perspective this is not a problem, as we do not do > cross-platform hash calculation and further comparison. The hash output > (discriminator value) is always compiled on compiler side and left as-is. > > So, we can either keep the present code as-is. Or we can just sprinkle few > calls from `Endian.h` to do byteswap on BE platforms. I was thinking that it is important that on both big and little endian platforms, the same hash is produced? Otherwise it becomes impossible to cross-compile from an other-endian host to an other-endian target? That basically would break ABI? It would surface when combining libraries built on differently-endian platforms. Maybe this doesn't happen often in practice, but LLVM remains supported on big-endian platforms, so I would think it's important that those platforms can cross-compile correctly to other targets? https://github.com/llvm/llvm-project/pull/94394 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Implement pointer authentication for C++ virtual functions, v-tables, and VTTs (PR #94056)
Endilll wrote: @asl It would be nice if you submit the next round of review as a single review, instead of 29 individual comments. https://github.com/llvm/llvm-project/pull/94056 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang][test] add testing for the AST matcher reference (PR #94248)
5chmidti wrote: - added a file-level comment in the ASTMatcher.h file on how the syntax works (basically the pr description) - replaced some `type=name` matches with explicit code matches where applicable, to be more expressive - added comments to `count=` matches when they didn't explain why or if there were multiple matches https://github.com/llvm/llvm-project/pull/94248 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [msan] Implement shadow propagation for _mm_dp_pd, _mm_dp_ps, _mm256_dp_ps (PR #94875)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/94875 Default intrinsic handling was to report any uninitialized part of argument. However intrinsics use mask which allow to ignore parts of input, so it's OK to have vectors partially initialized. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [msan] Implement shadow propagation for _mm_dp_pd, _mm_dp_ps, _mm256_dp_ps (PR #94875)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
Default intrinsic handling was to report any
uninitialized part of argument. However intrinsics
use mask which allow to ignore parts of input, so
it's OK to have vectors partially initialized.
---
Patch is 30.68 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/94875.diff
3 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+77-1)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll (+40-39)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/sse41-intrinsics-x86.ll (+23-31)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index b352558a1c0d2..43b2dee4572a9 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -3287,6 +3287,76 @@ struct MemorySanitizerVisitor : public
InstVisitor {
setOriginForNaryOp(I);
}
+ // Convert `Mask` into ``.
+ Constant *createDppMask(unsigned Width, unsigned Mask) {
+SmallVector R;
+R.assign(Width, ConstantInt::getFalse(F.getContext()));
+for (auto &M : R) {
+ if (Mask & 1)
+M = ConstantInt::getTrue(F.getContext());
+ Mask >>= 1;
+}
+return ConstantVector::get(R);
+ }
+
+ // Calculate output shadow as array of booleans ``, assuming if any
+ // arg is poisoned, entire dot product is poisoned.
+ Value *makeDppShadowI1(IRBuilder<> &IRB, Value *S, unsigned SrcMask,
+ unsigned DstMask) {
+const unsigned Width =
+cast(S->getType())->getNumElements();
+
+S = IRB.CreateSelect(createDppMask(Width, SrcMask), S,
+ Constant::getNullValue(S->getType()));
+Value *SElem = IRB.CreateOrReduce(S);
+Value *IsClean = IRB.CreateIsNull(SElem, "_msdpp");
+Value *DstMaskV = createDppMask(Width, DstMask);
+
+return IRB.CreateSelect(
+IsClean, Constant::getNullValue(DstMaskV->getType()), DstMaskV);
+ }
+
+ // See `Intel Intrinsics Guide` for `_dp_p*` instructions.
+ //
+ // 2 and 4 element versions produce single scalar of dot product, and then
+ // puts it into elements of output vector, selected by 4 lowest bits of the
+ // mask. Top 4 bits of the mask control which elements of input to use for
dot
+ // product.
+ //
+ // 8 element version mask still has only 4 bit for input, and 4 bit for
output
+ // mask. According to the spec it just operates as 4 element version on first
+ // 4 elements of inputs and output, and then on last 4 elements of inputs and
+ // output.
+ void handleDppIntrinsic(IntrinsicInst &I) {
+IRBuilder<> IRB(&I);
+
+Value *S0 = getShadow(&I, 0);
+Value *S1 = getShadow(&I, 1);
+Value *S = IRB.CreateOr(S0, S1);
+
+const unsigned Width =
+cast(S->getType())->getNumElements();
+assert(Width == 2 || Width == 4 || Width == 8);
+
+const unsigned Mask =
cast(I.getArgOperand(2))->getZExtValue();
+const unsigned SrcMask = Mask >> 4;
+const unsigned DstMask = Mask & 0xf;
+
+// Calculate shadow as ``.
+Value *SI1 = makeDppShadowI1(IRB, S, SrcMask, DstMask);
+if (Width == 8) {
+ // First 4 elements of shadow are already calculated. `makeDppShadow`
+ // operats on 32 bit masks, so we can just shift masks, and repeat.
+ SI1 = IRB.CreateOr(SI1,
+ makeDppShadowI1(IRB, S, SrcMask << 4, DstMask << 4));
+}
+// Extend to real size of shadow, poisoning all no none bits of an element.
+S = IRB.CreateSExt(SI1, S->getType(), "_msdpp");
+
+setShadow(&I, S);
+setOriginForNaryOp(I);
+ }
+
// Instrument sum-of-absolute-differences intrinsic.
void handleVectorSadIntrinsic(IntrinsicInst &I) {
const unsigned SignificantBitsPerResultElement = 16;
@@ -3642,7 +3712,7 @@ struct MemorySanitizerVisitor : public
InstVisitor {
setOriginForNaryOp(I);
}
- SmallVector getPclmulMask(unsigned Width, bool OddElements) {
+ static SmallVector getPclmulMask(unsigned Width, bool OddElements) {
SmallVector Mask;
for (unsigned X = OddElements ? 1 : 0; X < Width; X += 2) {
Mask.append(2, X);
@@ -3958,6 +4028,12 @@ struct MemorySanitizerVisitor : public
InstVisitor {
handleVectorPackIntrinsic(I);
break;
+case Intrinsic::x86_avx_dp_ps_256:
+case Intrinsic::x86_sse41_dppd:
+case Intrinsic::x86_sse41_dpps:
+ handleDppIntrinsic(I);
+ break;
+
case Intrinsic::x86_mmx_packsswb:
case Intrinsic::x86_mmx_packuswb:
handleVectorPackIntrinsic(I, 16);
diff --git
a/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
b/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
index f2db831c0dbd9..b33d4845cdd25 100644
--- a/
[llvm-branch-commits] [NFC][msan] Prepare function to extract main logic (PR #94880)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/94880 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][msan] Extract `handleSelectLikeInst` (PR #94881)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/94881 `blendv` instructions are very similar to `select`. We will add support for them in followup patches. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [msan] Handle blendv intrinsics (PR #94882)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/94882 Then are very similar to select, so we adjust arguments and forward them into select handler. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][msan] Prepare function to extract main logic (PR #94880)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/94880.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+6-4)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 43b2dee4572a9..d312b0107932b 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -4562,10 +4562,15 @@ struct MemorySanitizerVisitor : public
InstVisitor {
Value *B = I.getCondition();
Value *C = I.getTrueValue();
Value *D = I.getFalseValue();
+
Value *Sb = getShadow(B);
Value *Sc = getShadow(C);
Value *Sd = getShadow(D);
+Value *Ob = MS.TrackOrigins ? getOrigin(B) : nullptr;
+Value *Oc = MS.TrackOrigins ? getOrigin(C) : nullptr;
+Value *Od = MS.TrackOrigins ? getOrigin(D) : nullptr;
+
// Result shadow if condition shadow is 0.
Value *Sa0 = IRB.CreateSelect(B, Sc, Sd);
Value *Sa1;
@@ -4598,10 +4603,7 @@ struct MemorySanitizerVisitor : public
InstVisitor {
}
// a = select b, c, d
// Oa = Sb ? Ob : (b ? Oc : Od)
- setOrigin(
- &I, IRB.CreateSelect(Sb, getOrigin(I.getCondition()),
- IRB.CreateSelect(B, getOrigin(I.getTrueValue()),
-
getOrigin(I.getFalseValue();
+ setOrigin(&I, IRB.CreateSelect(Sb, Ob, IRB.CreateSelect(B, Oc, Od)));
}
}
``
https://github.com/llvm/llvm-project/pull/94880
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[llvm-branch-commits] [NFC][msan] Extract `handleSelectLikeInst` (PR #94881)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
`blendv` instructions are very similar to `select`.
We will add support for them in followup patches.
---
Full diff: https://github.com/llvm/llvm-project/pull/94881.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+6-1)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index d312b0107932b..3993a9290607d 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -4557,12 +4557,17 @@ struct MemorySanitizerVisitor : public
InstVisitor {
}
void visitSelectInst(SelectInst &I) {
-IRBuilder<> IRB(&I);
// a = select b, c, d
Value *B = I.getCondition();
Value *C = I.getTrueValue();
Value *D = I.getFalseValue();
+handleSelectLikeInst(I, B, C, D);
+ }
+
+ void handleSelectLikeInst(Instruction &I, Value *B, Value *C, Value *D) {
+IRBuilder<> IRB(&I);
+
Value *Sb = getShadow(B);
Value *Sc = getShadow(C);
Value *Sd = getShadow(D);
``
https://github.com/llvm/llvm-project/pull/94881
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[llvm-branch-commits] [msan] Handle blendv intrinsics (PR #94882)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
Then are very similar to select, so we adjust
arguments and forward them into select handler.
---
Patch is 20.02 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/94882.diff
4 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+40)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll (+32-12)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll (+19-12)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/sse41-intrinsics-x86.ll (+45-18)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 3993a9290607d..bc45ae820e3c6 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -3357,6 +3357,37 @@ struct MemorySanitizerVisitor : public
InstVisitor {
setOriginForNaryOp(I);
}
+ Value *convertBlendvToSelectMask(IRBuilder<> &IRB, Value *C) {
+C = CreateAppToShadowCast(IRB, C);
+FixedVectorType *FVT = cast(C->getType());
+unsigned ElSize = FVT->getElementType()->getPrimitiveSizeInBits();
+C = IRB.CreateAShr(C, ElSize - 1);
+FVT = FixedVectorType::get(IRB.getInt1Ty(), FVT->getNumElements());
+return IRB.CreateTrunc(C, FVT);
+ }
+
+ // `blendv(f, t, c)` is effectively `select(c[top_bit], t, f)`.
+ void handleBlendvIntrinsic(IntrinsicInst &I) {
+Value *C = I.getOperand(2);
+Value *T = I.getOperand(1);
+Value *F = I.getOperand(0);
+
+Value *Sc = getShadow(&I, 2);
+Value *Oc = MS.TrackOrigins ? getOrigin(C) : nullptr;
+
+{
+ IRBuilder<> IRB(&I);
+ // Extract top bit from condition and its shadow.
+ C = convertBlendvToSelectMask(IRB, C);
+ Sc = convertBlendvToSelectMask(IRB, Sc);
+
+ setShadow(C, Sc);
+ setOrigin(C, Oc);
+}
+
+handleSelectLikeInst(I, C, T, F);
+ }
+
// Instrument sum-of-absolute-differences intrinsic.
void handleVectorSadIntrinsic(IntrinsicInst &I) {
const unsigned SignificantBitsPerResultElement = 16;
@@ -4028,6 +4059,15 @@ struct MemorySanitizerVisitor : public
InstVisitor {
handleVectorPackIntrinsic(I);
break;
+case Intrinsic::x86_sse41_pblendvb:
+case Intrinsic::x86_sse41_blendvpd:
+case Intrinsic::x86_sse41_blendvps:
+case Intrinsic::x86_avx_blendv_pd_256:
+case Intrinsic::x86_avx_blendv_ps_256:
+case Intrinsic::x86_avx2_pblendvb:
+ handleBlendvIntrinsic(I);
+ break;
+
case Intrinsic::x86_avx_dp_ps_256:
case Intrinsic::x86_sse41_dppd:
case Intrinsic::x86_sse41_dpps:
diff --git
a/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
b/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
index b33d4845cdd25..d101192956a23 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
@@ -38,14 +38,24 @@ declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x
float>, <8 x float>) nounwi
define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double>
%a1, <4 x double> %a2) #0 {
; CHECK-LABEL: @test_x86_avx_blendv_pd_256(
-; CHECK-NEXT:[[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
+; CHECK-NEXT:[[TMP1:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64
ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
; CHECK-NEXT:[[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64
ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
-; CHECK-NEXT:[[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64
ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
+; CHECK-NEXT:[[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; CHECK-NEXT:call void @llvm.donothing()
-; CHECK-NEXT:[[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]]
-; CHECK-NEXT:[[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]
-; CHECK-NEXT:[[RES:%.*]] = call <4 x double>
@llvm.x86.avx.blendv.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]],
<4 x double> [[A2:%.*]])
-; CHECK-NEXT:store <4 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast <4 x double> [[A2:%.*]] to <4 x i64>
+; CHECK-NEXT:[[TMP5:%.*]] = ashr <4 x i64> [[TMP4]],
+; CHECK-NEXT:[[TMP6:%.*]] = trunc <4 x i64> [[TMP5]] to <4 x i1>
+; CHECK-NEXT:[[TMP7:%.*]] = ashr <4 x i64> [[TMP1]],
+; CHECK-NEXT:[[TMP8:%.*]] = trunc <4 x i64> [[TMP7]] to <4 x i1>
+; CHECK-NEXT:[[TMP9:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP2]],
<4 x i64> [[TMP3]]
+; CHECK-NEXT:[[TMP10:%.*]] = bitcast <4 x double> [[A1:%.*]] to <4 x i64>
+; CHECK-NEXT:[[TMP11:%.*]] = bitcast <4 x
[llvm-branch-commits] [NFC][msan] Prepare function to extract main logic (PR #94880)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/94880.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+6-4)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 43b2dee4572a9..d312b0107932b 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -4562,10 +4562,15 @@ struct MemorySanitizerVisitor : public
InstVisitor {
Value *B = I.getCondition();
Value *C = I.getTrueValue();
Value *D = I.getFalseValue();
+
Value *Sb = getShadow(B);
Value *Sc = getShadow(C);
Value *Sd = getShadow(D);
+Value *Ob = MS.TrackOrigins ? getOrigin(B) : nullptr;
+Value *Oc = MS.TrackOrigins ? getOrigin(C) : nullptr;
+Value *Od = MS.TrackOrigins ? getOrigin(D) : nullptr;
+
// Result shadow if condition shadow is 0.
Value *Sa0 = IRB.CreateSelect(B, Sc, Sd);
Value *Sa1;
@@ -4598,10 +4603,7 @@ struct MemorySanitizerVisitor : public
InstVisitor {
}
// a = select b, c, d
// Oa = Sb ? Ob : (b ? Oc : Od)
- setOrigin(
- &I, IRB.CreateSelect(Sb, getOrigin(I.getCondition()),
- IRB.CreateSelect(B, getOrigin(I.getTrueValue()),
-
getOrigin(I.getFalseValue();
+ setOrigin(&I, IRB.CreateSelect(Sb, Ob, IRB.CreateSelect(B, Oc, Od)));
}
}
``
https://github.com/llvm/llvm-project/pull/94880
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[llvm-branch-commits] [msan] Handle blendv intrinsics (PR #94882)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
Then are very similar to select, so we adjust
arguments and forward them into select handler.
---
Patch is 20.02 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/94882.diff
4 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+40)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll (+32-12)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll (+19-12)
- (modified)
llvm/test/Instrumentation/MemorySanitizer/X86/sse41-intrinsics-x86.ll (+45-18)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 3993a9290607d..bc45ae820e3c6 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -3357,6 +3357,37 @@ struct MemorySanitizerVisitor : public
InstVisitor {
setOriginForNaryOp(I);
}
+ Value *convertBlendvToSelectMask(IRBuilder<> &IRB, Value *C) {
+C = CreateAppToShadowCast(IRB, C);
+FixedVectorType *FVT = cast(C->getType());
+unsigned ElSize = FVT->getElementType()->getPrimitiveSizeInBits();
+C = IRB.CreateAShr(C, ElSize - 1);
+FVT = FixedVectorType::get(IRB.getInt1Ty(), FVT->getNumElements());
+return IRB.CreateTrunc(C, FVT);
+ }
+
+ // `blendv(f, t, c)` is effectively `select(c[top_bit], t, f)`.
+ void handleBlendvIntrinsic(IntrinsicInst &I) {
+Value *C = I.getOperand(2);
+Value *T = I.getOperand(1);
+Value *F = I.getOperand(0);
+
+Value *Sc = getShadow(&I, 2);
+Value *Oc = MS.TrackOrigins ? getOrigin(C) : nullptr;
+
+{
+ IRBuilder<> IRB(&I);
+ // Extract top bit from condition and its shadow.
+ C = convertBlendvToSelectMask(IRB, C);
+ Sc = convertBlendvToSelectMask(IRB, Sc);
+
+ setShadow(C, Sc);
+ setOrigin(C, Oc);
+}
+
+handleSelectLikeInst(I, C, T, F);
+ }
+
// Instrument sum-of-absolute-differences intrinsic.
void handleVectorSadIntrinsic(IntrinsicInst &I) {
const unsigned SignificantBitsPerResultElement = 16;
@@ -4028,6 +4059,15 @@ struct MemorySanitizerVisitor : public
InstVisitor {
handleVectorPackIntrinsic(I);
break;
+case Intrinsic::x86_sse41_pblendvb:
+case Intrinsic::x86_sse41_blendvpd:
+case Intrinsic::x86_sse41_blendvps:
+case Intrinsic::x86_avx_blendv_pd_256:
+case Intrinsic::x86_avx_blendv_ps_256:
+case Intrinsic::x86_avx2_pblendvb:
+ handleBlendvIntrinsic(I);
+ break;
+
case Intrinsic::x86_avx_dp_ps_256:
case Intrinsic::x86_sse41_dppd:
case Intrinsic::x86_sse41_dpps:
diff --git
a/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
b/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
index b33d4845cdd25..d101192956a23 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
@@ -38,14 +38,24 @@ declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x
float>, <8 x float>) nounwi
define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double>
%a1, <4 x double> %a2) #0 {
; CHECK-LABEL: @test_x86_avx_blendv_pd_256(
-; CHECK-NEXT:[[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
+; CHECK-NEXT:[[TMP1:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64
ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
; CHECK-NEXT:[[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64
ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
-; CHECK-NEXT:[[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64
ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
+; CHECK-NEXT:[[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; CHECK-NEXT:call void @llvm.donothing()
-; CHECK-NEXT:[[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]]
-; CHECK-NEXT:[[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]
-; CHECK-NEXT:[[RES:%.*]] = call <4 x double>
@llvm.x86.avx.blendv.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]],
<4 x double> [[A2:%.*]])
-; CHECK-NEXT:store <4 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast <4 x double> [[A2:%.*]] to <4 x i64>
+; CHECK-NEXT:[[TMP5:%.*]] = ashr <4 x i64> [[TMP4]],
+; CHECK-NEXT:[[TMP6:%.*]] = trunc <4 x i64> [[TMP5]] to <4 x i1>
+; CHECK-NEXT:[[TMP7:%.*]] = ashr <4 x i64> [[TMP1]],
+; CHECK-NEXT:[[TMP8:%.*]] = trunc <4 x i64> [[TMP7]] to <4 x i1>
+; CHECK-NEXT:[[TMP9:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP2]],
<4 x i64> [[TMP3]]
+; CHECK-NEXT:[[TMP10:%.*]] = bitcast <4 x double> [[A1:%.*]] to <4 x i64>
+; CHECK-NEXT:[[TMP11:%.*]] = bitcast <4 x double
[llvm-branch-commits] [msan] Handle blendv intrinsics (PR #94882)
https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/94882 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SPARC][IAS] Add support for %uhi and %ulo extensions (PR #94246)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/94246
>From 04bfa20fbeba63f405d12f49a5a75c0903b252b8 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Mon, 3 Jun 2024 23:28:19 +0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?=
=?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
[skip ci]
---
llvm/lib/Target/Sparc/SparcInstrAliases.td | 11 ---
llvm/test/MC/Sparc/sparcv9-instructions.s | 10 ++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td
b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index db4c05cf18062..2b9244519f154 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -560,11 +560,16 @@ def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0,
simm13Op:$simm13), 0>;
// End of Section A.3
-// or imm, reg, rd -> or reg, imm, rd
-// Nonstandard GNU extension.
-let EmitPriority = 0 in
+
+// Nonstandard GNU extensions.
+let EmitPriority = 0 in {
+ // or imm, reg, rd -> or reg, imm, rd
def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1,
simm13Op:$simm13)>;
+ // addc/addx imm, reg, rd -> or reg, imm, rd
+ def : InstAlias<"addx $simm13, $rs1, $rd", (ADDCri IntRegs:$rd,
IntRegs:$rs1, simm13Op:$simm13)>;
+}
+
// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
// (aka: omit the first arg when it's g0. This is not in the manual, but is
// supported by gnu and solaris as)
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s
b/llvm/test/MC/Sparc/sparcv9-instructions.s
index 0ca2e50989ca9..b947243f8258f 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -6,6 +6,16 @@
! V9: addx %g2, %g1, %g3 ! encoding:
[0x86,0x40,0x80,0x01]
addc %g2, %g1, %g3
+! V8: error: invalid instruction mnemonic
+! V8-NEXT: addc %g2, 1, %g3
+! V9: addx %g2, 1, %g3 ! encoding:
[0x86,0x40,0xa0,0x01]
+addc %g2, 1, %g3
+
+! V8: error: invalid instruction mnemonic
+! V8-NEXT: addc 1, %g2, %g3
+! V9: addx %g2, 1, %g3 ! encoding:
[0x86,0x40,0xa0,0x01]
+addc 1, %g2, %g3
+
! V8: error: invalid instruction mnemonic
! V8-NEXT: addccc %g1, %g2, %g3
! V9: addxcc %g1, %g2, %g3! encoding:
[0x86,0xc0,0x40,0x02]
___
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[llvm-branch-commits] [llvm] [SPARC][IAS] Add aliases for %asr20-21 as defined in JPS1 (PR #94247)
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/94247
>From 74aec4b8d79f1691ee3f7de7ad777eb00bc2f58f Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Mon, 3 Jun 2024 23:28:34 +0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?=
=?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
[skip ci]
---
.../Target/Sparc/MCTargetDesc/SparcMCExpr.cpp | 78 ++-
llvm/lib/Target/Sparc/SparcInstrAliases.td| 11 ++-
llvm/test/MC/Sparc/sparc-relocations.s| 10 +++
llvm/test/MC/Sparc/sparcv9-instructions.s | 10 +++
4 files changed, 68 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
index 522a8877a1c60..4688837e435e5 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
@@ -93,44 +93,46 @@ bool SparcMCExpr::printVariantKind(raw_ostream &OS,
VariantKind Kind)
SparcMCExpr::VariantKind SparcMCExpr::parseVariantKind(StringRef name)
{
return StringSwitch(name)
-.Case("lo", VK_Sparc_LO)
-.Case("hi", VK_Sparc_HI)
-.Case("h44", VK_Sparc_H44)
-.Case("m44", VK_Sparc_M44)
-.Case("l44", VK_Sparc_L44)
-.Case("hh", VK_Sparc_HH)
-.Case("hm", VK_Sparc_HM)
-.Case("lm", VK_Sparc_LM)
-.Case("pc22", VK_Sparc_PC22)
-.Case("pc10", VK_Sparc_PC10)
-.Case("got22", VK_Sparc_GOT22)
-.Case("got10", VK_Sparc_GOT10)
-.Case("got13", VK_Sparc_GOT13)
-.Case("r_disp32", VK_Sparc_R_DISP32)
-.Case("tgd_hi22", VK_Sparc_TLS_GD_HI22)
-.Case("tgd_lo10", VK_Sparc_TLS_GD_LO10)
-.Case("tgd_add",VK_Sparc_TLS_GD_ADD)
-.Case("tgd_call", VK_Sparc_TLS_GD_CALL)
-.Case("tldm_hi22", VK_Sparc_TLS_LDM_HI22)
-.Case("tldm_lo10", VK_Sparc_TLS_LDM_LO10)
-.Case("tldm_add", VK_Sparc_TLS_LDM_ADD)
-.Case("tldm_call", VK_Sparc_TLS_LDM_CALL)
-.Case("tldo_hix22", VK_Sparc_TLS_LDO_HIX22)
-.Case("tldo_lox10", VK_Sparc_TLS_LDO_LOX10)
-.Case("tldo_add", VK_Sparc_TLS_LDO_ADD)
-.Case("tie_hi22", VK_Sparc_TLS_IE_HI22)
-.Case("tie_lo10", VK_Sparc_TLS_IE_LO10)
-.Case("tie_ld", VK_Sparc_TLS_IE_LD)
-.Case("tie_ldx",VK_Sparc_TLS_IE_LDX)
-.Case("tie_add",VK_Sparc_TLS_IE_ADD)
-.Case("tle_hix22", VK_Sparc_TLS_LE_HIX22)
-.Case("tle_lox10", VK_Sparc_TLS_LE_LOX10)
-.Case("hix",VK_Sparc_HIX22)
-.Case("lox",VK_Sparc_LOX10)
-.Case("gdop_hix22", VK_Sparc_GOTDATA_HIX22)
-.Case("gdop_lox10", VK_Sparc_GOTDATA_LOX10)
-.Case("gdop", VK_Sparc_GOTDATA_OP)
-.Default(VK_Sparc_None);
+ .Case("lo", VK_Sparc_LO)
+ .Case("hi", VK_Sparc_HI)
+ .Case("h44", VK_Sparc_H44)
+ .Case("m44", VK_Sparc_M44)
+ .Case("l44", VK_Sparc_L44)
+ .Case("hh", VK_Sparc_HH)
+ .Case("uhi", VK_Sparc_HH) // Nonstandard GNU extension
+ .Case("hm", VK_Sparc_HM)
+ .Case("ulo", VK_Sparc_HM) // Nonstandard GNU extension
+ .Case("lm", VK_Sparc_LM)
+ .Case("pc22", VK_Sparc_PC22)
+ .Case("pc10", VK_Sparc_PC10)
+ .Case("got22", VK_Sparc_GOT22)
+ .Case("got10", VK_Sparc_GOT10)
+ .Case("got13", VK_Sparc_GOT13)
+ .Case("r_disp32", VK_Sparc_R_DISP32)
+ .Case("tgd_hi22", VK_Sparc_TLS_GD_HI22)
+ .Case("tgd_lo10", VK_Sparc_TLS_GD_LO10)
+ .Case("tgd_add", VK_Sparc_TLS_GD_ADD)
+ .Case("tgd_call", VK_Sparc_TLS_GD_CALL)
+ .Case("tldm_hi22", VK_Sparc_TLS_LDM_HI22)
+ .Case("tldm_lo10", VK_Sparc_TLS_LDM_LO10)
+ .Case("tldm_add", VK_Sparc_TLS_LDM_ADD)
+ .Case("tldm_call", VK_Sparc_TLS_LDM_CALL)
+ .Case("tldo_hix22", VK_Sparc_TLS_LDO_HIX22)
+ .Case("tldo_lox10", VK_Sparc_TLS_LDO_LOX10)
+ .Case("tldo_add", VK_Sparc_TLS_LDO_ADD)
+ .Case("tie_hi22", VK_Sparc_TLS_IE_HI22)
+ .Case("tie_lo10", VK_Sparc_TLS_IE_LO10)
+ .Case("tie_ld", VK_Sparc_TLS_IE_LD)
+ .Case("tie_ldx", VK_Sparc_TLS_IE_LDX)
+ .Case("tie_add", VK_Sparc_TLS_IE_ADD)
+ .Case("tle_hix22", VK_Sparc_TLS_LE_HIX22)
+ .Case("tle_lox10", VK_Sparc_TLS_LE_LOX10)
+ .Case("hix", VK_Sparc_HIX22)
+ .Case("lox", VK_Sparc_LOX10)
+ .Case("gdop_hix22", VK_Sparc_GOTDATA_HIX22)
+ .Case("gdop_lox10", VK_Sparc_GOTDATA_LOX10)
+ .Case("gdop", VK_Sparc_GOTDATA_OP)
+ .Default(VK_Sparc_None);
}
Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td
b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index db4c05cf18062..2b9244519f154 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -560,11 +560,16 @@ def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0,
simm13Op:$simm13), 0>;
// End of Section A.3
-// or imm, reg, r
