[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/92221
Backport d6ee7e8481fbaee30f37d82778ef12e135db5e67
Requested by: @nikic
>From 9dbc8e21ea0f27537c9183e8e1dc118338957654 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Wed, 15 May 2024 08:36:26 +0200
Subject: [PATCH] [SystemZ] Handle address clobbering in splitMove(). (#92105)
When expanding an L128 (which is used to reload i128) it is
possible that the quadword destination register clobbers an
address register. This patch adds an assertion against the case
where both of the expanded parts clobber the address, and in the
case where one of the expanded parts do so puts it last.
Fixes #91437
(cherry picked from commit d6ee7e8481fbaee30f37d82778ef12e135db5e67)
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 65 +++
.../CodeGen/SystemZ/splitMove_addressReg.mir | 26
2 files changed, 65 insertions(+), 26 deletions(-)
create mode 100644 llvm/test/CodeGen/SystemZ/splitMove_addressReg.mir
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bf6547cc87ec5..2f2dc6b807921 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -70,49 +70,62 @@ void
SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- // Get two load or store instructions. Use the original instruction for one
- // of them (arbitrarily the second here) and create a clone for the other.
- MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
- MBB->insert(MI, EarlierMI);
+ // Get two load or store instructions. Use the original instruction for
+ // one of them and create a clone for the other.
+ MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);
+ MachineInstr *LowPartMI = &*MI;
+ MBB->insert(LowPartMI, HighPartMI);
// Set up the two 64-bit registers and remember super reg and its flags.
- MachineOperand &HighRegOp = EarlierMI->getOperand(0);
- MachineOperand &LowRegOp = MI->getOperand(0);
+ MachineOperand &HighRegOp = HighPartMI->getOperand(0);
+ MachineOperand &LowRegOp = LowPartMI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
- if (MI->mayStore()) {
-// Add implicit uses of the super register in case one of the subregs is
-// undefined. We could track liveness and skip storing an undefined
-// subreg, but this is hopefully rare (discovered with llvm-stress).
-// If Reg128 was killed, set kill flag on MI.
-unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
-MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
-MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
- }
-
// The address in the first (high) instruction is already correct.
// Adjust the offset in the second (low) instruction.
- MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
- MachineOperand &LowOffsetOp = MI->getOperand(2);
+ MachineOperand &HighOffsetOp = HighPartMI->getOperand(2);
+ MachineOperand &LowOffsetOp = LowPartMI->getOperand(2);
LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
- // Clear the kill flags on the registers in the first instruction.
- if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
-EarlierMI->getOperand(0).setIsKill(false);
- EarlierMI->getOperand(1).setIsKill(false);
- EarlierMI->getOperand(3).setIsKill(false);
-
// Set the opcodes.
unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
assert(HighOpcode && LowOpcode && "Both offsets should be in range");
+ HighPartMI->setDesc(get(HighOpcode));
+ LowPartMI->setDesc(get(LowOpcode));
+
+ MachineInstr *FirstMI = HighPartMI;
+ if (MI->mayStore()) {
+FirstMI->getOperand(0).setIsKill(false);
+// Add implicit uses of the super register in case one of the subregs is
+// undefined. We could track liveness and skip storing an undefined
+// subreg, but this is hopefully rare (discovered with llvm-stress).
+// If Reg128 was killed, set kill flag on MI.
+unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
+MachineInstrBuilder(MF, HighPartMI).addReg(Reg128, Reg128UndefImpl);
+MachineInstrBuilder(MF, LowPartMI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
+ } else {
+// If HighPartMI clobbers any of the address registers, it needs to come
+// after LowPartMI.
+auto overlapsAddressReg = [&](Register Reg) -> bool {
+ return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||
+
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
llvmbot wrote: @uweigand What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/JonPsson1 approved this pull request. https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
https://github.com/wangleiat created https://github.com/llvm/llvm-project/pull/92223 The previous logic did not consider whether the architectural features meet the requirements of the ABI, resulting in the generation of incorrect object files in some cases. For example: ``` llc -mtriple=loongarch64 -filetype=obj test/CodeGen/LoongArch/ir-instruction/fadd.ll -o t.o llvm-readelf -h t.o ``` The object file indicates the ABI as lp64d, however, the generated code is lp64s. The new logic introduces the `feature-implied` ABI. When both target-abi and triple-implied ABI are invalid, the feature-implied ABI is used. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: wanglei (wangleiat)
Changes
The previous logic did not consider whether the architectural features
meet the requirements of the ABI, resulting in the generation of
incorrect object files in some cases. For example:
```
llc -mtriple=loongarch64 -filetype=obj
test/CodeGen/LoongArch/ir-instruction/fadd.ll -o t.o
llvm-readelf -h t.o
```
The object file indicates the ABI as lp64d, however, the generated code
is lp64s.
The new logic introduces the `feature-implied` ABI. When both target-abi
and triple-implied ABI are invalid, the feature-implied ABI is used.
---
Full diff: https://github.com/llvm/llvm-project/pull/92223.diff
6 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp (+1-1)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp
(+102-35)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h (+2-1)
- (modified) llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
(+2-1)
- (modified) llvm/test/CodeGen/LoongArch/e_flags.ll (+3-3)
- (modified) llvm/test/CodeGen/LoongArch/target-abi-from-triple-edge-cases.ll
(+23)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
b/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
index ffcde7dd1fa74..57babfc917f89 100644
--- a/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
@@ -50,7 +50,7 @@ LoongArchSubtarget
&LoongArchSubtarget::initializeSubtargetDependencies(
if (!Is64Bit && HasLA64)
report_fatal_error("Feature 64bit should be used for loongarch64 target.");
- TargetABI = LoongArchABI::computeTargetABI(TT, ABIName);
+ TargetABI = LoongArchABI::computeTargetABI(TT, getFeatureBits(), ABIName);
return *this;
}
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp
b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp
index 7fd2526a57c94..a8f3b8b079c08 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp
@@ -12,6 +12,7 @@
//===--===//
#include "LoongArchBaseInfo.h"
+#include "LoongArchMCTargetDesc.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
wangleiat wrote: @xen0n https://github.com/llvm/llvm-project/pull/92223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [LV, LAA] Don't vectorize loops with load and store to invar address. (PR #91092)
fhahn wrote: SGTM https://github.com/llvm/llvm-project/pull/91092 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
https://github.com/xen0n edited https://github.com/llvm/llvm-project/pull/92223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
xen0n wrote:
```suggestion
// If target-abi is not specified, use the valid triple-implied ABI.
```
https://github.com/llvm/llvm-project/pull/92223
___
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llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
https://github.com/xen0n commented: Maybe unify all warning messages' format into `warning: blah blah`? LGTM apart from the natural language usages. https://github.com/llvm/llvm-project/pull/92223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
+if (ABIName.empty())
+ return checkABIStandardized(TripleABI);
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
+switch (ArgProvidedABI) {
+case ABI_Unknown:
+ // Fallback to the triple-implied ABI if ABI name is specified and
+ // invalid.
errs() << "'" << ABIName
<< "' is not a recognized ABI for this target, ignoring and using
"
"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
-
- case LoongArchABI::ABI_ILP32S:
- case LoongArchABI::ABI_ILP32F:
- case LoongArchABI::ABI_ILP32D:
-if (Is64Bit) {
- errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
return checkABIStandardized(TripleABI);
+case ABI_ILP32S:
+case ABI_ILP32F:
+case ABI_ILP32D:
+ if (Is64Bit) {
+errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
+case ABI_LP64S:
+case ABI_LP64F:
+case ABI_LP64D:
+ if (!Is64Bit) {
+errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
}
-break;
- case LoongArchABI::ABI_LP64S:
- case LoongArchABI::ABI_LP64F:
- case LoongArchABI::ABI_LP64D:
-if (!Is64Bit) {
- errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
- return checkABIStandardized(TripleABI);
+switch (ArgProvidedABI) {
+case ABI_ILP32F:
+case ABI_LP64F:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'F'
"
+"instruction set, ignoring target-abi and using triple-implied
"
+"ABI\n";
+ break;
+case ABI_ILP32D:
+case ABI_LP64D:
+ errs() << "'" << ABIName
xen0n wrote:
same here
https://github.com/llvm/llvm-project/pull/92223
_
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
+if (ABIName.empty())
+ return checkABIStandardized(TripleABI);
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
+switch (ArgProvidedABI) {
+case ABI_Unknown:
+ // Fallback to the triple-implied ABI if ABI name is specified and
xen0n wrote:
```suggestion
// Fallback to the triple-implied ABI if ABI name is specified but
```
https://github.com/llvm/llvm-project/pull/92223
___
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[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
+if (ABIName.empty())
+ return checkABIStandardized(TripleABI);
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
+switch (ArgProvidedABI) {
+case ABI_Unknown:
+ // Fallback to the triple-implied ABI if ABI name is specified and
+ // invalid.
errs() << "'" << ABIName
<< "' is not a recognized ABI for this target, ignoring and using
"
"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
-
- case LoongArchABI::ABI_ILP32S:
- case LoongArchABI::ABI_ILP32F:
- case LoongArchABI::ABI_ILP32D:
-if (Is64Bit) {
- errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
return checkABIStandardized(TripleABI);
+case ABI_ILP32S:
+case ABI_ILP32F:
+case ABI_ILP32D:
+ if (Is64Bit) {
+errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
+case ABI_LP64S:
+case ABI_LP64F:
+case ABI_LP64D:
+ if (!Is64Bit) {
+errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
}
-break;
- case LoongArchABI::ABI_LP64S:
- case LoongArchABI::ABI_LP64F:
- case LoongArchABI::ABI_LP64D:
-if (!Is64Bit) {
- errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
- return checkABIStandardized(TripleABI);
+switch (ArgProvidedABI) {
+case ABI_ILP32F:
+case ABI_LP64F:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'F'
"
+"instruction set, ignoring target-abi and using triple-implied
"
+"ABI\n";
+ break;
+case ABI_ILP32D:
+case ABI_LP64D:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'D'
"
+"instru
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
xen0n wrote:
name this `IsABIValidForFeature` for extra clarity?
https://github.com/llvm/llvm-project/pull/92223
___
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[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
+if (ABIName.empty())
+ return checkABIStandardized(TripleABI);
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
+switch (ArgProvidedABI) {
+case ABI_Unknown:
+ // Fallback to the triple-implied ABI if ABI name is specified and
+ // invalid.
errs() << "'" << ABIName
<< "' is not a recognized ABI for this target, ignoring and using
"
"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
-
- case LoongArchABI::ABI_ILP32S:
- case LoongArchABI::ABI_ILP32F:
- case LoongArchABI::ABI_ILP32D:
-if (Is64Bit) {
- errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
return checkABIStandardized(TripleABI);
+case ABI_ILP32S:
+case ABI_ILP32F:
+case ABI_ILP32D:
+ if (Is64Bit) {
+errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
+case ABI_LP64S:
+case ABI_LP64F:
+case ABI_LP64D:
+ if (!Is64Bit) {
+errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
}
-break;
- case LoongArchABI::ABI_LP64S:
- case LoongArchABI::ABI_LP64F:
- case LoongArchABI::ABI_LP64D:
-if (!Is64Bit) {
- errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
- return checkABIStandardized(TripleABI);
+switch (ArgProvidedABI) {
+case ABI_ILP32F:
+case ABI_LP64F:
+ errs() << "'" << ABIName
xen0n wrote:
```suggestion
errs() << "warning: the '" << ABIName
```
https://github.com/llvm/llvm-project/pull/92223
___
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[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
+if (ABIName.empty())
+ return checkABIStandardized(TripleABI);
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
+switch (ArgProvidedABI) {
+case ABI_Unknown:
+ // Fallback to the triple-implied ABI if ABI name is specified and
+ // invalid.
errs() << "'" << ABIName
<< "' is not a recognized ABI for this target, ignoring and using
"
"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
-
- case LoongArchABI::ABI_ILP32S:
- case LoongArchABI::ABI_ILP32F:
- case LoongArchABI::ABI_ILP32D:
-if (Is64Bit) {
- errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
return checkABIStandardized(TripleABI);
+case ABI_ILP32S:
+case ABI_ILP32F:
+case ABI_ILP32D:
+ if (Is64Bit) {
+errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
+case ABI_LP64S:
+case ABI_LP64F:
+case ABI_LP64D:
+ if (!Is64Bit) {
+errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
}
-break;
- case LoongArchABI::ABI_LP64S:
- case LoongArchABI::ABI_LP64F:
- case LoongArchABI::ABI_LP64D:
-if (!Is64Bit) {
- errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
- return checkABIStandardized(TripleABI);
+switch (ArgProvidedABI) {
+case ABI_ILP32F:
+case ABI_LP64F:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'F'
"
+"instruction set, ignoring target-abi and using triple-implied
"
+"ABI\n";
+ break;
+case ABI_ILP32D:
+case ABI_LP64D:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'D'
"
+"instru
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -52,63 +53,129 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
+
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
+if (FeatureBits[LoongArch::FeatureBasicD])
+ return Is64Bit ? ABI_LP64D : ABI_ILP32D;
+if (FeatureBits[LoongArch::FeatureBasicF])
+ return Is64Bit ? ABI_LP64F : ABI_ILP32F;
+return Is64Bit ? ABI_LP64S : ABI_ILP32S;
+ };
+ auto IsValidABI = [=](ABI Abi) {
+switch (Abi) {
+default:
+ return false;
+case ABI_ILP32S:
+ return !Is64Bit;
+case ABI_ILP32F:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_ILP32D:
+ return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+case ABI_LP64S:
+ return Is64Bit;
+case ABI_LP64F:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicF];
+case ABI_LP64D:
+ return Is64Bit && FeatureBits[LoongArch::FeatureBasicD];
+}
+ };
+
+ // 1. If the '-target-abi' is valid, use it.
+ if (IsValidABI(ArgProvidedABI)) {
+if (TT.hasEnvironment() && ArgProvidedABI != TripleABI)
+ errs()
+ << "warning: triple-implied ABI conflicts with provided target-abi '"
+ << ABIName << "', using target-abi\n";
+return checkABIStandardized(ArgProvidedABI);
+ }
+
+ // 2. If the triple-implied ABI is valid, use it.
+ if (IsValidABI(TripleABI)) {
+// If not specifie target-abi, use the valid triple-implied ABI.
+if (ABIName.empty())
+ return checkABIStandardized(TripleABI);
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
+switch (ArgProvidedABI) {
+case ABI_Unknown:
+ // Fallback to the triple-implied ABI if ABI name is specified and
+ // invalid.
errs() << "'" << ABIName
<< "' is not a recognized ABI for this target, ignoring and using
"
"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
-
- case LoongArchABI::ABI_ILP32S:
- case LoongArchABI::ABI_ILP32F:
- case LoongArchABI::ABI_ILP32D:
-if (Is64Bit) {
- errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
return checkABIStandardized(TripleABI);
+case ABI_ILP32S:
+case ABI_ILP32F:
+case ABI_ILP32D:
+ if (Is64Bit) {
+errs() << "32-bit ABIs are not supported for 64-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
+case ABI_LP64S:
+case ABI_LP64F:
+case ABI_LP64D:
+ if (!Is64Bit) {
+errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
+ "target-abi and using triple-implied ABI\n";
+return checkABIStandardized(TripleABI);
+ }
+ break;
}
-break;
- case LoongArchABI::ABI_LP64S:
- case LoongArchABI::ABI_LP64F:
- case LoongArchABI::ABI_LP64D:
-if (!Is64Bit) {
- errs() << "64-bit ABIs are not supported for 32-bit targets, ignoring "
-"target-abi and using triple-implied ABI\n";
- return checkABIStandardized(TripleABI);
+switch (ArgProvidedABI) {
+case ABI_ILP32F:
+case ABI_LP64F:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'F'
"
+"instruction set, ignoring target-abi and using triple-implied
"
+"ABI\n";
+ break;
+case ABI_ILP32D:
+case ABI_LP64D:
+ errs() << "'" << ABIName
+ << "' ABI can't be used for a target that doesn't support the 'D'
"
+"instru
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/alexey-bataev approved this pull request. LG https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
https://github.com/wangleiat updated https://github.com/llvm/llvm-project/pull/92223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
https://github.com/wangleiat updated https://github.com/llvm/llvm-project/pull/92223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/uweigand approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 57ac757 - Revert "[ExceptionDemo] Correct and update example ExceptionDemo (#69485)"
Author: Kamlesh Kumar
Date: 2024-05-15T18:21:25+05:30
New Revision: 57ac757310a6283e2a9cb8fdd01af3bc4535c055
URL:
https://github.com/llvm/llvm-project/commit/57ac757310a6283e2a9cb8fdd01af3bc4535c055
DIFF:
https://github.com/llvm/llvm-project/commit/57ac757310a6283e2a9cb8fdd01af3bc4535c055.diff
LOG: Revert "[ExceptionDemo] Correct and update example ExceptionDemo (#69485)"
This reverts commit 2ece5cc2bb1b4cc787e33e24a6582043d441a572.
Added:
Modified:
llvm/examples/ExceptionDemo/CMakeLists.txt
llvm/examples/ExceptionDemo/ExceptionDemo.cpp
Removed:
diff --git a/llvm/examples/ExceptionDemo/CMakeLists.txt
b/llvm/examples/ExceptionDemo/CMakeLists.txt
index 0a60ad848dd40..793cf291ca6f1 100644
--- a/llvm/examples/ExceptionDemo/CMakeLists.txt
+++ b/llvm/examples/ExceptionDemo/CMakeLists.txt
@@ -1,7 +1,9 @@
set(LLVM_LINK_COMPONENTS
Core
ExecutionEngine
- ORCJIT
+ MC
+ MCJIT
+ RuntimeDyld
Support
Target
nativecodegen
diff --git a/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
b/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
index 41fa0cf626bf3..0afc6b30d140e 100644
--- a/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
+++ b/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
@@ -49,9 +49,8 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/BinaryFormat/Dwarf.h"
-#include "llvm/ExecutionEngine/Orc/Core.h"
-#include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h"
-#include "llvm/ExecutionEngine/Orc/LLJIT.h"
+#include "llvm/ExecutionEngine/MCJIT.h"
+#include "llvm/ExecutionEngine/SectionMemoryManager.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/IRBuilder.h"
@@ -85,8 +84,6 @@
#define USE_GLOBAL_STR_CONSTS true
#endif
-llvm::ExitOnError ExitOnErr;
-
//
// Example types
//
@@ -145,7 +142,6 @@ static llvm::ConstantInt *ourExceptionCaughtState;
typedef std::vector ArgNames;
typedef std::vector ArgTypes;
-typedef llvm::ArrayRef TypeArray;
//
// Code Generation Utilities
@@ -896,10 +892,13 @@ void generateStringPrint(llvm::LLVMContext &context,
///generated, and is used to hold the constant string. A value of
///false indicates that the constant string will be stored on the
///stack.
-void generateIntegerPrint(llvm::LLVMContext &context, llvm::Module &module,
+void generateIntegerPrint(llvm::LLVMContext &context,
+ llvm::Module &module,
llvm::IRBuilder<> &builder,
- llvm::Function &printFunct, llvm::Value *toPrint,
- std::string format, bool useGlobal = true) {
+ llvm::Function &printFunct,
+ llvm::Value &toPrint,
+ std::string format,
+ bool useGlobal = true) {
llvm::Constant *stringConstant =
llvm::ConstantDataArray::getString(context, format);
llvm::Value *stringVar;
@@ -921,9 +920,10 @@ void generateIntegerPrint(llvm::LLVMContext &context,
llvm::Module &module,
llvm::Value *cast = builder.CreateBitCast(stringVar,
builder.getPtrTy());
- builder.CreateCall(&printFunct, {toPrint, cast});
+ builder.CreateCall(&printFunct, {&toPrint, cast});
}
+
/// Generates code to handle finally block type semantics: always runs
/// regardless of whether a thrown exception is passing through or the
/// parent function is simply exiting. In addition to printing some state
@@ -997,10 +997,10 @@ static llvm::BasicBlock
*createFinallyBlock(llvm::LLVMContext &context,
bufferToPrint.str(),
USE_GLOBAL_STR_CONSTS);
- llvm::SwitchInst *theSwitch = builder.CreateSwitch(
- builder.CreateLoad(ourExceptionNotThrownState->getType(),
- *exceptionCaughtFlag),
- &terminatorBlock, 2);
+ llvm::SwitchInst *theSwitch = builder.CreateSwitch(builder.CreateLoad(
+ *exceptionCaughtFlag),
+ &terminatorBlock,
+ 2);
theSwitch->addCase(ourExceptionCaughtState, &terminatorBlock);
theSwitch->addCase(ourExceptionThrownState, &unwindResumeBlock);
@@ -1186,7 +1186,7 @@ static llvm::Function *createCatchWrappedInvokeFunction(
// Note: function handles NULL exceptions
builder.CreateCall(deleteOurException,
- builder.CreateLoad(builder.getPtrTy(), exceptionStorage));
+ builder.CreateLoad(exceptionStorage));
builder.CreateRetVoid();
// Normal Block
@@ -1206,8 +1206,7 @@ static llvm::Function *createCatchWrappedInvokeFunction(
builder.SetInsertPoint(unwindResumeBlock);
- builder.CreateResume(
- builder.CreateLoad(ourCaughtResultType, caughtResultStorage));
+ builder.CreateResume(
[llvm-branch-commits] [llvm] release/18.x: [workflows] Fix libclang-abi-tests to work with new version scheme (#91865) (PR #92258)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/92258
Backport d06270ee00e37b247eb99268fb2f106dbeee08ff
Requested by: @tstellar
>From 392149d03f1c2e9f6cd636d349a16494bf53caf2 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Wed, 15 May 2024 06:08:29 -0700
Subject: [PATCH] [workflows] Fix libclang-abi-tests to work with new version
scheme (#91865)
(cherry picked from commit d06270ee00e37b247eb99268fb2f106dbeee08ff)
---
.github/workflows/libclang-abi-tests.yml | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ccfc1e5fb8a74..972d21c3bcedf 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -33,7 +33,6 @@ jobs:
ABI_HEADERS: ${{ steps.vars.outputs.ABI_HEADERS }}
ABI_LIBS: ${{ steps.vars.outputs.ABI_LIBS }}
BASELINE_VERSION_MAJOR: ${{ steps.vars.outputs.BASELINE_VERSION_MAJOR }}
- BASELINE_VERSION_MINOR: ${{ steps.vars.outputs.BASELINE_VERSION_MINOR }}
LLVM_VERSION_MAJOR: ${{ steps.version.outputs.LLVM_VERSION_MAJOR }}
LLVM_VERSION_MINOR: ${{ steps.version.outputs.LLVM_VERSION_MINOR }}
LLVM_VERSION_PATCH: ${{ steps.version.outputs.LLVM_VERSION_PATCH }}
@@ -51,9 +50,9 @@ jobs:
id: vars
run: |
remote_repo='https://github.com/llvm/llvm-project'
- if [ ${{ steps.version.outputs.LLVM_VERSION_MINOR }} -ne 0 ] || [
${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then
+ if [ ${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then
major_version=$(( ${{ steps.version.outputs.LLVM_VERSION_MAJOR }}
- 1))
-baseline_ref="llvmorg-$major_version.0.0"
+baseline_ref="llvmorg-$major_version.1.0"
# If there is a minor release, we want to use that as the base
line.
minor_ref=$(git ls-remote --refs -t "$remote_repo"
llvmorg-"$major_version".[1-9].[0-9] | tail -n1 | grep -o 'llvmorg-.\+' || true)
@@ -75,7 +74,7 @@ jobs:
else
{
echo "BASELINE_VERSION_MAJOR=${{
steps.version.outputs.LLVM_VERSION_MAJOR }}"
- echo "BASELINE_REF=llvmorg-${{
steps.version.outputs.LLVM_VERSION_MAJOR }}.0.0"
+ echo "BASELINE_REF=llvmorg-${{
steps.version.outputs.LLVM_VERSION_MAJOR }}.1.0"
echo "ABI_HEADERS=."
echo "ABI_LIBS=libclang.so libclang-cpp.so"
} >> "$GITHUB_OUTPUT"
___
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[llvm-branch-commits] [llvm] release/18.x: [workflows] Fix libclang-abi-tests to work with new version scheme (#91865) (PR #92258)
llvmbot wrote: @boomanaiden154 What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/92258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [workflows] Fix libclang-abi-tests to work with new version scheme (#91865) (PR #92258)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/92258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [workflows] Fix libclang-abi-tests to work with new version scheme (#91865) (PR #92258)
llvmbot wrote:
@llvm/pr-subscribers-github-workflow
Author: None (llvmbot)
Changes
Backport d06270ee00e37b247eb99268fb2f106dbeee08ff
Requested by: @tstellar
---
Full diff: https://github.com/llvm/llvm-project/pull/92258.diff
1 Files Affected:
- (modified) .github/workflows/libclang-abi-tests.yml (+3-4)
``diff
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ccfc1e5fb8a74..972d21c3bcedf 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -33,7 +33,6 @@ jobs:
ABI_HEADERS: ${{ steps.vars.outputs.ABI_HEADERS }}
ABI_LIBS: ${{ steps.vars.outputs.ABI_LIBS }}
BASELINE_VERSION_MAJOR: ${{ steps.vars.outputs.BASELINE_VERSION_MAJOR }}
- BASELINE_VERSION_MINOR: ${{ steps.vars.outputs.BASELINE_VERSION_MINOR }}
LLVM_VERSION_MAJOR: ${{ steps.version.outputs.LLVM_VERSION_MAJOR }}
LLVM_VERSION_MINOR: ${{ steps.version.outputs.LLVM_VERSION_MINOR }}
LLVM_VERSION_PATCH: ${{ steps.version.outputs.LLVM_VERSION_PATCH }}
@@ -51,9 +50,9 @@ jobs:
id: vars
run: |
remote_repo='https://github.com/llvm/llvm-project'
- if [ ${{ steps.version.outputs.LLVM_VERSION_MINOR }} -ne 0 ] || [
${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then
+ if [ ${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then
major_version=$(( ${{ steps.version.outputs.LLVM_VERSION_MAJOR }}
- 1))
-baseline_ref="llvmorg-$major_version.0.0"
+baseline_ref="llvmorg-$major_version.1.0"
# If there is a minor release, we want to use that as the base
line.
minor_ref=$(git ls-remote --refs -t "$remote_repo"
llvmorg-"$major_version".[1-9].[0-9] | tail -n1 | grep -o 'llvmorg-.\+' || true)
@@ -75,7 +74,7 @@ jobs:
else
{
echo "BASELINE_VERSION_MAJOR=${{
steps.version.outputs.LLVM_VERSION_MAJOR }}"
- echo "BASELINE_REF=llvmorg-${{
steps.version.outputs.LLVM_VERSION_MAJOR }}.0.0"
+ echo "BASELINE_REF=llvmorg-${{
steps.version.outputs.LLVM_VERSION_MAJOR }}.1.0"
echo "ABI_HEADERS=."
echo "ABI_LIBS=libclang.so libclang-cpp.so"
} >> "$GITHUB_OUTPUT"
``
https://github.com/llvm/llvm-project/pull/92258
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[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT:[[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nsw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
tstellar wrote:
@nikic No, it's not. The problem is that you need two different types of
permissions to be able to set that feature (write access to the branch and
write access to the PR). Because these both have different scopes (the branch
is in the forked repository and the PR is in the main repository) it's not
possible to use fine-grained tokens. We'll have to switch back to the classic
token to get it to work. I'm planning to do this for the next release cycle.
https://github.com/llvm/llvm-project/pull/91917
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[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT:[[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nsw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
tstellar wrote:
@dtcxzyw I've enabled maintainer edits for this PR, so you can push directly
now.
https://github.com/llvm/llvm-project/pull/91917
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[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91553
>From 1665723044ec1db5a2ca68ea911155c01e815515 Mon Sep 17 00:00:00 2001
From: Thomas Debesse
Date: Thu, 9 May 2024 05:18:35 +0200
Subject: [PATCH] release/18.x: [libclc] Fix linking against libIRReader
Fixes https://github.com/llvm/llvm-project/issues/91551
---
libclc/CMakeLists.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index fa1d8e4adbcc4..b7f8bb18c2288 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -114,6 +114,7 @@ include_directories( ${LLVM_INCLUDE_DIRS} )
set(LLVM_LINK_COMPONENTS
BitReader
BitWriter
+ IRReader
Core
Support
)
___
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[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
https://github.com/tstellar approved this pull request. https://github.com/llvm/llvm-project/pull/91553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclc] 1665723 - release/18.x: [libclc] Fix linking against libIRReader
Author: Thomas Debesse
Date: 2024-05-15T06:37:42-07:00
New Revision: 1665723044ec1db5a2ca68ea911155c01e815515
URL:
https://github.com/llvm/llvm-project/commit/1665723044ec1db5a2ca68ea911155c01e815515
DIFF:
https://github.com/llvm/llvm-project/commit/1665723044ec1db5a2ca68ea911155c01e815515.diff
LOG: release/18.x: [libclc] Fix linking against libIRReader
Fixes https://github.com/llvm/llvm-project/issues/91551
Added:
Modified:
libclc/CMakeLists.txt
Removed:
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index fa1d8e4adbcc4..b7f8bb18c2288 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -114,6 +114,7 @@ include_directories( ${LLVM_INCLUDE_DIRS} )
set(LLVM_LINK_COMPONENTS
BitReader
BitWriter
+ IRReader
Core
Support
)
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[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
tstellar wrote: @illwieckz (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
tstellar wrote: Should we still try to backport this? https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
topperc wrote: > @topperc Do you have any strong objections to backporting this? This looks > small to me and I think it's OK to fix long-standing bugs. No objection. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: Maybe I could make fast-unaligned-access only apply to scalar to avoid a name change. And give a new flag for vector? There's not a lot of RISC-V vector hardware available yet. One of the CPUs that is available only supports unaligned scalars and not vectors. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
@@ -216,7 +216,8 @@ void gatherImportedSummariesForModule( StringRef ModulePath, const DenseMap &ModuleToDefinedGVSummaries, const FunctionImporter::ImportMapTy &ImportList, -std::map &ModuleToSummariesForIndex); +std::map &ModuleToSummariesForIndex, +GVSummaryPtrSet &DecSummaries); jvoung wrote: Can you add a documentation for the DecSummaries parameter here too? (similar to the ThinLTOCodeGenerator.h comment, might be useful to indicate it's a subset of ModuleToSummariesForIndex). https://github.com/llvm/llvm-project/pull/87600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
preames wrote: I don't think we need to backport this at all. None of the in tree cpus fall into the category where the distinction is important, and I don't feel we have any obligation to backport support for our of tree forks. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > I don't think we need to backport this at all. None of the in tree cpus fall > into the category where the distinction is important, and I don't feel we > have any obligation to backport support for our of tree forks. There's no out of tree fork involved here. The bug reporter was using stock LLVM to compile for the Kendryte K230 board. A developer from the RISE System Libraries group reported this same issue in a presentation yesterday. It is impacting their work on chromium zlib on the same K230 board. zlib does scalar unaligned accesses. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MTE] add stack frame history buffer (PR #86356)
https://github.com/fmayer ready_for_review https://github.com/llvm/llvm-project/pull/86356 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/92293
Backport be10746
Requested by: @Ericson2314
>From 5b09e6bf5aaeb21256e86455f8d6c42d01f71b95 Mon Sep 17 00:00:00 2001
From: John Ericson
Date: Wed, 15 May 2024 12:43:55 -0400
Subject: [PATCH] [clang] Don't assume location of compiler-rt for OpenBSD
(#92183)
If the `/usr/lib/...` path where compiler-rt is conventionally installed
on OpenBSD does not exist, fall back to the regular logic to find it.
This is a minimal change to allow OpenBSD cross compilation from a
toolchain that doesn't adopt all of OpenBSD's monorepo's conventions.
(cherry picked from commit be10746f3a4381456eb5082a968766201c17ab5d)
---
clang/lib/Driver/ToolChains/OpenBSD.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp
b/clang/lib/Driver/ToolChains/OpenBSD.cpp
index fd6aa4d7e6844..00b6c520fcdd7 100644
--- a/clang/lib/Driver/ToolChains/OpenBSD.cpp
+++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp
@@ -371,7 +371,8 @@ std::string OpenBSD::getCompilerRT(const ArgList &Args,
StringRef Component,
if (Component == "builtins") {
SmallString<128> Path(getDriver().SysRoot);
llvm::sys::path::append(Path, "/usr/lib/libcompiler_rt.a");
-return std::string(Path);
+if (getVFS().exists(Path))
+ return std::string(Path);
}
SmallString<128> P(getDriver().ResourceDir);
std::string CRTBasename =
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[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/92293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport be10746
Requested by: @Ericson2314
---
Full diff: https://github.com/llvm/llvm-project/pull/92293.diff
1 Files Affected:
- (modified) clang/lib/Driver/ToolChains/OpenBSD.cpp (+2-1)
``diff
diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp
b/clang/lib/Driver/ToolChains/OpenBSD.cpp
index fd6aa4d7e6844..00b6c520fcdd7 100644
--- a/clang/lib/Driver/ToolChains/OpenBSD.cpp
+++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp
@@ -371,7 +371,8 @@ std::string OpenBSD::getCompilerRT(const ArgList &Args,
StringRef Component,
if (Component == "builtins") {
SmallString<128> Path(getDriver().SysRoot);
llvm::sys::path::append(Path, "/usr/lib/libcompiler_rt.a");
-return std::string(Path);
+if (getVFS().exists(Path))
+ return std::string(Path);
}
SmallString<128> P(getDriver().ResourceDir);
std::string CRTBasename =
``
https://github.com/llvm/llvm-project/pull/92293
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[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
Ericson2314 wrote: (I read https://llvm.org/docs/HowToReleaseLLVM.html#release-patch-rules and believe it qualifies) https://github.com/llvm/llvm-project/pull/92293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
tstellar wrote: @AtariDreams I've noticed you've filed a lot of backport requests. How are you choosing which fixes to backport? Is there a specific use case you care about? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
AtariDreams wrote: > @AtariDreams I've noticed you've filed a lot of backport requests. How are > you choosing which fixes to backport? Is there a specific use case you care > about? There a particular LLVM miscompile bug in WebKit I'm trying to figure out. It's been there since 2019. Backports is literally just avoiding miscompilations https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
tstellar wrote: @brad0 What do you think about backporting this? https://github.com/llvm/llvm-project/pull/92293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92129
>From e6e68660ab3868d99710be8e492fa61e3bb0a34d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?=
Date: Tue, 14 May 2024 15:54:05 +0200
Subject: [PATCH] [GlobalIsel][AArch64] fix out of range access in
regbankselect (#92072)
Fixes https://github.com/llvm/llvm-project/issues/92062
(cherry picked from commit d422e90fcb68749918ddd86c94188807efce)
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 5 -
llvm/test/CodeGen/AArch64/pr92062.ll | 21 +++
2 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/pr92062.ll
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const
MachineInstr &MI) const {
EltTy = GV->getValueType();
// Look at the first element of the struct to determine the type we are
// loading
-while (StructType *StructEltTy = dyn_cast(EltTy))
+while (StructType *StructEltTy = dyn_cast(EltTy)) {
+ if (StructEltTy->getNumElements() == 0)
+break;
EltTy = StructEltTy->getTypeAtIndex(0U);
+}
// Look at the first element of the array to determine its type
if (isa(EltTy))
EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll
b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+@p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %bb
+; CHECK-NEXT:adrp x8, :got:p
+; CHECK-NEXT:ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:ldr x8, [x8]
+; CHECK-NEXT:mov x9, xzr
+; CHECK-NEXT:str x8, [x9]
+; CHECK-NEXT:ret
+bb:
+ %i1 = load ptr, ptr @p, align 8
+ store ptr %i1, ptr null, align 8
+ ret void
+}
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[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
https://github.com/minglotus-6 updated
https://github.com/llvm/llvm-project/pull/87600
>From 001a785f664e3a16e61d1e350ea060b829f1856c Mon Sep 17 00:00:00 2001
From: mingmingl
Date: Mon, 13 May 2024 20:51:25 -0700
Subject: [PATCH 1/3] update this patch as the second one
---
llvm/include/llvm/Bitcode/BitcodeWriter.h | 9 +++--
.../llvm/LTO/legacy/ThinLTOCodeGenerator.h| 5 ++-
.../llvm/Transforms/IPO/FunctionImport.h | 3 +-
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 38 +++
llvm/lib/LTO/LTO.cpp | 7 +++-
llvm/lib/LTO/ThinLTOCodeGenerator.cpp | 11 --
llvm/lib/Transforms/IPO/FunctionImport.cpp| 5 ++-
.../ThinLTO/X86/import_callee_declaration.ll | 13 +++
llvm/tools/llvm-lto/llvm-lto.cpp | 5 ++-
9 files changed, 66 insertions(+), 30 deletions(-)
diff --git a/llvm/include/llvm/Bitcode/BitcodeWriter.h
b/llvm/include/llvm/Bitcode/BitcodeWriter.h
index 248d33f4502ef..a343f0e057631 100644
--- a/llvm/include/llvm/Bitcode/BitcodeWriter.h
+++ b/llvm/include/llvm/Bitcode/BitcodeWriter.h
@@ -102,7 +102,8 @@ class raw_ostream;
void writeIndex(
const ModuleSummaryIndex *Index,
-const std::map
*ModuleToSummariesForIndex);
+const std::map *ModuleToSummariesForIndex,
+const GVSummaryPtrSet *DecSummaries);
};
/// Write the specified module to the specified raw output stream.
@@ -147,10 +148,12 @@ class raw_ostream;
/// where it will be written in a new bitcode block. This is used when
/// writing the combined index file for ThinLTO. When writing a subset of the
/// index for a distributed backend, provide the \p ModuleToSummariesForIndex
- /// map.
+ /// map. \p DecSummaries specifies the set of summaries for which the
+ /// corresponding value should be imported as a declaration (prototype).
void writeIndexToFile(const ModuleSummaryIndex &Index, raw_ostream &Out,
const std::map
-*ModuleToSummariesForIndex = nullptr);
+*ModuleToSummariesForIndex = nullptr,
+const GVSummaryPtrSet *DecSummaries = nullptr);
/// If EmbedBitcode is set, save a copy of the llvm IR as data in the
/// __LLVM,__bitcode section (.llvmbc on non-MacOS).
diff --git a/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
b/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
index c450acda82ad0..f1337e82485c9 100644
--- a/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
+++ b/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
@@ -271,12 +271,13 @@ class ThinLTOCodeGenerator {
const lto::InputFile &File);
/**
- * Compute the list of summaries needed for importing into module.
+ * Compute the list of summaries and the subset of declaration summaries
+ * needed for importing into module.
*/
void gatherImportedSummariesForModule(
Module &Module, ModuleSummaryIndex &Index,
std::map &ModuleToSummariesForIndex,
- const lto::InputFile &File);
+ GVSummaryPtrSet &DecSummaries, const lto::InputFile &File);
/**
* Perform internalization. Index is updated to reflect linkage changes.
diff --git a/llvm/include/llvm/Transforms/IPO/FunctionImport.h
b/llvm/include/llvm/Transforms/IPO/FunctionImport.h
index 024bba8105b89..f8b98d5f81770 100644
--- a/llvm/include/llvm/Transforms/IPO/FunctionImport.h
+++ b/llvm/include/llvm/Transforms/IPO/FunctionImport.h
@@ -216,7 +216,8 @@ void gatherImportedSummariesForModule(
StringRef ModulePath,
const DenseMap &ModuleToDefinedGVSummaries,
const FunctionImporter::ImportMapTy &ImportList,
-std::map &ModuleToSummariesForIndex);
+std::map &ModuleToSummariesForIndex,
+GVSummaryPtrSet &DecSummaries);
/// Emit into \p OutputFilename the files module \p ModulePath will import
from.
std::error_code EmitImportsFiles(
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index 6d01e3b4d8218..7b89424194f9b 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -428,6 +428,11 @@ class IndexBitcodeWriter : public BitcodeWriterBase {
/// The combined index to write to bitcode.
const ModuleSummaryIndex &Index;
+ /// When writing combined summaries, provides the set of global value
+ /// summaries for which the value (function, function alias, etc) should be
+ /// imported as a declaration.
+ const GVSummaryPtrSet *DecSummaries = nullptr;
+
/// When writing a subset of the index for distributed backends, client
/// provides a map of modules to the corresponding GUIDs/summaries to write.
const std::map *ModuleToSummariesForIndex;
@@ -452,11 +457,16 @@ class IndexBitcodeWriter : public BitcodeWriterBase {
/// Constructs a IndexBitcodeWriter object for the given combined index,
/// writing to the provided \p Buffer. When writing a subset of the
[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
@@ -216,7 +216,8 @@ void gatherImportedSummariesForModule( StringRef ModulePath, const DenseMap &ModuleToDefinedGVSummaries, const FunctionImporter::ImportMapTy &ImportList, -std::map &ModuleToSummariesForIndex); +std::map &ModuleToSummariesForIndex, +GVSummaryPtrSet &DecSummaries); minglotus-6 wrote: done. https://github.com/llvm/llvm-project/pull/87600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
https://github.com/jvoung edited https://github.com/llvm/llvm-project/pull/87600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
@@ -1399,18 +1399,21 @@ class lto::ThinBackendProc {
llvm::StringRef ModulePath,
const std::string &NewModulePath) {
std::map ModuleToSummariesForIndex;
+GVSummaryPtrSet DeclarationSummaries;
std::error_code EC;
gatherImportedSummariesForModule(ModulePath, ModuleToDefinedGVSummaries,
- ImportList, ModuleToSummariesForIndex);
+ ImportList, ModuleToSummariesForIndex,
+ DeclarationSummaries);
raw_fd_ostream OS(NewModulePath + ".thinlto.bc", EC,
sys::fs::OpenFlags::OF_None);
if (EC)
return errorCodeToError(EC);
// TODO: Serialize declaration bits to bitcode.
jvoung wrote:
Can the TODO be removed?
https://github.com/llvm/llvm-project/pull/87600
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[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
https://github.com/jvoung commented: Nice! https://github.com/llvm/llvm-project/pull/87600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
@@ -48,20 +48,20 @@
; First disassemble per-module summary and find out the GUID for {large_func,
large_indirect_callee}.
;
; RUN: llvm-dis lib.bc -o - | FileCheck %s --check-prefix=LIB-DIS
+; LIB-DIS: [[LIBMOD:\^[0-9]+]] = module: (path: "lib.bc", hash: (0, 0, 0, 0,
0))
; LIB-DIS: [[LARGEFUNC:\^[0-9]+]] = gv: (name: "large_func", summaries:
{{.*}}) ; guid = 2418497564662708935
; LIB-DIS: [[LARGEINDIRECT:\^[0-9]+]] = gv: (name: "large_indirect_callee",
summaries: {{.*}}) ; guid = 14343440786664691134
; LIB-DIS: [[LARGEINDIRECTALIAS:\^[0-9]+]] = gv: (name:
"large_indirect_callee_alias", summaries: {{.*}}, aliasee: [[LARGEINDIRECT]]
;
-; Secondly disassemble main's combined summary and test that large callees are
-; not imported as declarations yet.
-; TODO: Serialize declaration bit and test declaration bits are correctly set.
+; Secondly disassemble main's combined summary and verify the import type of
+; these two GUIDs are declaration.
;
; RUN: llvm-dis main.bc.thinlto.bc -o - | FileCheck %s --check-prefix=MAIN-DIS
;
; MAIN-DIS: [[LIBMOD:\^[0-9]+]] = module: (path: "lib.bc", hash: (0, 0, 0, 0,
0))
-; MAIN-DIS-NOT: [[LARGEFUNC:\^[0-9]+]] = gv: (guid: 2418497564662708935,
summaries: (function: (module: [[LIBMOD]], flags: ({{.*}} importType:
declaration), insts: 8, {{.*}})))
-; MAIN-DIS-NOT: [[LARGEINDIRECT:\^[0-9]+]] = gv: (guid: 14343440786664691134,
summaries: (function: (module: [[LIBMOD]], flags: ({{.*}} importType:
declaration), insts: 8, {{.*}})))
-; MAIN-DIS-NOT: [[LARGEINDIRECTALIAS:\^[0-9]+]] = gv: (guid:
16730173943625350469, summaries: (alias: (module: [[LIBMOD]], flags: ({{.*}}
importType: declaration)
+; MAIN-DIS: [[LARGEFUNC:\^[0-9]+]] = gv: (guid: 2418497564662708935,
summaries: (function: (module: [[LIBMOD]], flags: ({{.*}} importType:
declaration), insts: 8, {{.*}})))
jvoung wrote:
It might be interesting to test happens if "calleeAddrs" had just an alias of a
function and not the original function (right now both large_indirect_callee
and large_indirect_callee_alias are there?), but could be okay to test that
later too.
https://github.com/llvm/llvm-project/pull/87600
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[llvm-branch-commits] [llvm] dffee4d - Revert "[NewPM] Add pass options for `InternalizePass` to preserve GVs. (#91334)"
Author: Mehdi Amini
Date: 2024-05-15T15:05:04-07:00
New Revision: dffee4d14dc6c6dad97b060ea748116bd1c85d4b
URL:
https://github.com/llvm/llvm-project/commit/dffee4d14dc6c6dad97b060ea748116bd1c85d4b
DIFF:
https://github.com/llvm/llvm-project/commit/dffee4d14dc6c6dad97b060ea748116bd1c85d4b.diff
LOG: Revert "[NewPM] Add pass options for `InternalizePass` to preserve GVs.
(#91334)"
This reverts commit ee765b0c94df7e636d9739216b1646d3a2d3b5db.
Added:
Modified:
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Passes/PassRegistry.def
llvm/test/Transforms/Internalize/lists.ll
Removed:
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 91c5b65c03511..e4131706aba01 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1142,24 +1142,6 @@ Expected
parseGlobalMergeOptions(StringRef Params) {
return Result;
}
-Expected> parseInternalizeGVs(StringRef Params) {
- SmallVector PreservedGVs;
- while (!Params.empty()) {
-StringRef ParamName;
-std::tie(ParamName, Params) = Params.split(';');
-
-if (ParamName.consume_front("preserve-gv=")) {
- PreservedGVs.push_back(ParamName.str());
-} else {
- return make_error(
- formatv("invalid Internalize pass parameter '{0}' ",
ParamName).str(),
- inconvertibleErrorCode());
-}
- }
-
- return PreservedGVs;
-}
-
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Passes/PassRegistry.def
b/llvm/lib/Passes/PassRegistry.def
index 50682ca4970f1..e5ce6cb7da649 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -78,6 +78,7 @@ MODULE_PASS("insert-gcov-profiling", GCOVProfilerPass())
MODULE_PASS("instrorderfile", InstrOrderFilePass())
MODULE_PASS("instrprof", InstrProfilingLoweringPass())
MODULE_PASS("ctx-instr-lower", PGOCtxProfLoweringPass())
+MODULE_PASS("internalize", InternalizePass())
MODULE_PASS("invalidate", InvalidateAllAnalysesPass())
MODULE_PASS("iroutliner", IROutlinerPass())
MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass())
@@ -174,20 +175,6 @@ MODULE_PASS_WITH_PARAMS(
"hwasan", "HWAddressSanitizerPass",
[](HWAddressSanitizerOptions Opts) { return HWAddressSanitizerPass(Opts);
},
parseHWASanPassOptions, "kernel;recover")
-MODULE_PASS_WITH_PARAMS(
-"internalize", "InternalizePass",
-[](SmallVector PreservedGVs) {
- if (PreservedGVs.empty())
-return InternalizePass();
- auto MustPreserveGV = [=](const GlobalValue &GV) {
-for (auto &PreservedGV : PreservedGVs)
- if (GV.getName() == PreservedGV)
-return true;
-return false;
- };
- return InternalizePass(MustPreserveGV);
-},
-parseInternalizeGVs, "preserve-gv=GV")
MODULE_PASS_WITH_PARAMS(
"ipsccp", "IPSCCPPass", [](IPSCCPOptions Opts) { return IPSCCPPass(Opts);
},
parseIPSCCPOptions, "no-func-spec;func-spec")
diff --git a/llvm/test/Transforms/Internalize/lists.ll
b/llvm/test/Transforms/Internalize/lists.ll
index 83dad03d75eae..df408f906b780 100644
--- a/llvm/test/Transforms/Internalize/lists.ll
+++ b/llvm/test/Transforms/Internalize/lists.ll
@@ -13,11 +13,6 @@
; -file and -list options should be merged, the apifile contains foo and j
; RUN: opt < %s -passes=internalize -internalize-public-api-list bar
-internalize-public-api-file %S/apifile -S | FileCheck
--check-prefix=FOO_J_AND_BAR %s
-; specifying through pass builder option
-; RUN: opt < %s -passes='internalize' -S |
FileCheck --check-prefix=FOO_AND_J %s
-; RUN: opt < %s -passes='internalize' -S |
FileCheck --check-prefix=FOO_AND_BAR %s
-; RUN: opt < %s
-passes='internalize' -S |
FileCheck --check-prefix=FOO_J_AND_BAR %s
-
; ALL: @i = internal global
; FOO_AND_J: @i = internal global
; FOO_AND_BAR: @i = internal global
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [LV, LAA] Don't vectorize loops with load and store to invar address. (PR #91092)
https://github.com/nikic closed https://github.com/llvm/llvm-project/pull/91092 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
nikic wrote: @tstellar AtariDreams is requesting backports for random commits that somehow mention miscompilations or crashes, without having any understanding of what the changes are about or how they relate to other changes. They have submitted a large amount of invalid or nonsensical backports for that reason, despite many requests to stop doing so. When there is any doubt, you should not merge backport PRs created by this user. That said, this specific one does look harmless to me. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91917
>From e4bbaa67ac5bb4aa0c6a4699aaa164f58ab5ae61 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 13 May 2024 14:27:59 +0800
Subject: [PATCH 1/2] [InstCombine] Drop nuw flag when CtlzOp is a sub nuw
(#91776)
See the following case:
```
define i32 @src1(i32 %x) {
%dec = sub nuw i32 -2, %x
%ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
%sub = sub nsw i32 32, %ctlz
%shl = shl i32 1, %sub
%ugt = icmp ult i32 %x, -2
%sel = select i1 %ugt, i32 %shl, i32 1
ret i32 %sel
}
define i32 @tgt1(i32 %x) {
%dec = sub nuw i32 -2, %x
%ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
%sub = sub nsw i32 32, %ctlz
%and = and i32 %sub, 31
%shl = shl nuw i32 1, %and
ret i32 %shl
}
```
`nuw` in `%dec` should be dropped after the select instruction is
eliminated.
Alive2: https://alive2.llvm.org/ce/z/7S9529
Fixes https://github.com/llvm/llvm-project/issues/91691.
(cherry picked from commit b5f4210e9f51f938ae517f219f04f9ab431a2684)
---
.../InstCombine/InstCombineSelect.cpp | 14 ++--
llvm/test/Transforms/InstCombine/bit_ceil.ll | 36 +++
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 8cc7901cbac7f..86a39cf2ee93f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -3201,7 +3201,8 @@ Instruction
*InstCombinerImpl::foldSelectOfBools(SelectInst &SI) {
// pattern.
static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
const APInt *Cond1, Value *CtlzOp,
-unsigned BitWidth) {
+unsigned BitWidth,
+bool &ShouldDropNUW) {
// The challenge in recognizing std::bit_ceil(X) is that the operand is used
// for the CTLZ proper and select condition, each possibly with some
// operation like add and sub.
@@ -3224,6 +3225,8 @@ static bool
isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
ConstantRange CR = ConstantRange::makeExactICmpRegion(
CmpInst::getInversePredicate(Pred), *Cond1);
+ ShouldDropNUW = false;
+
// Match the operation that's used to compute CtlzOp from CommonAncestor. If
// CtlzOp == CommonAncestor, return true as no operation is needed. If a
// match is found, execute the operation on CR, update CR, and return true.
@@ -3237,6 +3240,7 @@ static bool
isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
return true;
}
if (match(CtlzOp, m_Sub(m_APInt(C), m_Specific(CommonAncestor {
+ ShouldDropNUW = true;
CR = ConstantRange(*C).sub(CR);
return true;
}
@@ -3306,14 +3310,20 @@ static Instruction *foldBitCeil(SelectInst &SI,
IRBuilderBase &Builder) {
Pred = CmpInst::getInversePredicate(Pred);
}
+ bool ShouldDropNUW;
+
if (!match(FalseVal, m_One()) ||
!match(TrueVal,
m_OneUse(m_Shl(m_One(), m_OneUse(m_Sub(m_SpecificInt(BitWidth),
m_Value(Ctlz)) ||
!match(Ctlz, m_Intrinsic(m_Value(CtlzOp), m_Zero())) ||
- !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth))
+ !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth,
+ ShouldDropNUW))
return nullptr;
+ if (ShouldDropNUW)
+cast(CtlzOp)->setHasNoUnsignedWrap(false);
+
// Build 1 << (-CTLZ & (BitWidth-1)). The negation likely corresponds to a
// single hardware instruction as opposed to BitWidth - CTLZ, where BitWidth
// is an integer constant. Masking with BitWidth-1 comes free on some
diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll
b/llvm/test/Transforms/InstCombine/bit_ceil.ll
index 52e70c78ba542..63a5ae012eeb6 100644
--- a/llvm/test/Transforms/InstCombine/bit_ceil.ll
+++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT
[llvm-branch-commits] [llvm] [ThinLTO][Bitcode] Generate import type in bitcode (PR #87600)
https://github.com/teresajohnson approved this pull request. https://github.com/llvm/llvm-project/pull/87600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
https://github.com/nikic approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91917 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92221
>From 9acb41b1e4bb897cbc70301824acf1da4c46a51d Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Wed, 15 May 2024 08:36:26 +0200
Subject: [PATCH] [SystemZ] Handle address clobbering in splitMove(). (#92105)
When expanding an L128 (which is used to reload i128) it is
possible that the quadword destination register clobbers an
address register. This patch adds an assertion against the case
where both of the expanded parts clobber the address, and in the
case where one of the expanded parts do so puts it last.
Fixes #91437
(cherry picked from commit d6ee7e8481fbaee30f37d82778ef12e135db5e67)
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 65 +++
.../CodeGen/SystemZ/splitMove_addressReg.mir | 26
2 files changed, 65 insertions(+), 26 deletions(-)
create mode 100644 llvm/test/CodeGen/SystemZ/splitMove_addressReg.mir
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bf6547cc87ec5..2f2dc6b807921 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -70,49 +70,62 @@ void
SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- // Get two load or store instructions. Use the original instruction for one
- // of them (arbitrarily the second here) and create a clone for the other.
- MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
- MBB->insert(MI, EarlierMI);
+ // Get two load or store instructions. Use the original instruction for
+ // one of them and create a clone for the other.
+ MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);
+ MachineInstr *LowPartMI = &*MI;
+ MBB->insert(LowPartMI, HighPartMI);
// Set up the two 64-bit registers and remember super reg and its flags.
- MachineOperand &HighRegOp = EarlierMI->getOperand(0);
- MachineOperand &LowRegOp = MI->getOperand(0);
+ MachineOperand &HighRegOp = HighPartMI->getOperand(0);
+ MachineOperand &LowRegOp = LowPartMI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
- if (MI->mayStore()) {
-// Add implicit uses of the super register in case one of the subregs is
-// undefined. We could track liveness and skip storing an undefined
-// subreg, but this is hopefully rare (discovered with llvm-stress).
-// If Reg128 was killed, set kill flag on MI.
-unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
-MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
-MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
- }
-
// The address in the first (high) instruction is already correct.
// Adjust the offset in the second (low) instruction.
- MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
- MachineOperand &LowOffsetOp = MI->getOperand(2);
+ MachineOperand &HighOffsetOp = HighPartMI->getOperand(2);
+ MachineOperand &LowOffsetOp = LowPartMI->getOperand(2);
LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
- // Clear the kill flags on the registers in the first instruction.
- if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
-EarlierMI->getOperand(0).setIsKill(false);
- EarlierMI->getOperand(1).setIsKill(false);
- EarlierMI->getOperand(3).setIsKill(false);
-
// Set the opcodes.
unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
assert(HighOpcode && LowOpcode && "Both offsets should be in range");
+ HighPartMI->setDesc(get(HighOpcode));
+ LowPartMI->setDesc(get(LowOpcode));
+
+ MachineInstr *FirstMI = HighPartMI;
+ if (MI->mayStore()) {
+FirstMI->getOperand(0).setIsKill(false);
+// Add implicit uses of the super register in case one of the subregs is
+// undefined. We could track liveness and skip storing an undefined
+// subreg, but this is hopefully rare (discovered with llvm-stress).
+// If Reg128 was killed, set kill flag on MI.
+unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
+MachineInstrBuilder(MF, HighPartMI).addReg(Reg128, Reg128UndefImpl);
+MachineInstrBuilder(MF, LowPartMI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
+ } else {
+// If HighPartMI clobbers any of the address registers, it needs to come
+// after LowPartMI.
+auto overlapsAddressReg = [&](Register Reg) -> bool {
+ return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||
+ RI.regsOverlap(Reg, MI->getOperand(3).getReg());
+};
+
[llvm-branch-commits] [llvm] 9acb41b - [SystemZ] Handle address clobbering in splitMove(). (#92105)
Author: Jonas Paulsson
Date: 2024-05-15T19:01:13-07:00
New Revision: 9acb41b1e4bb897cbc70301824acf1da4c46a51d
URL:
https://github.com/llvm/llvm-project/commit/9acb41b1e4bb897cbc70301824acf1da4c46a51d
DIFF:
https://github.com/llvm/llvm-project/commit/9acb41b1e4bb897cbc70301824acf1da4c46a51d.diff
LOG: [SystemZ] Handle address clobbering in splitMove(). (#92105)
When expanding an L128 (which is used to reload i128) it is
possible that the quadword destination register clobbers an
address register. This patch adds an assertion against the case
where both of the expanded parts clobber the address, and in the
case where one of the expanded parts do so puts it last.
Fixes #91437
(cherry picked from commit d6ee7e8481fbaee30f37d82778ef12e135db5e67)
Added:
llvm/test/CodeGen/SystemZ/splitMove_addressReg.mir
Modified:
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bf6547cc87ec5..2f2dc6b807921 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -70,49 +70,62 @@ void
SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- // Get two load or store instructions. Use the original instruction for one
- // of them (arbitrarily the second here) and create a clone for the other.
- MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
- MBB->insert(MI, EarlierMI);
+ // Get two load or store instructions. Use the original instruction for
+ // one of them and create a clone for the other.
+ MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);
+ MachineInstr *LowPartMI = &*MI;
+ MBB->insert(LowPartMI, HighPartMI);
// Set up the two 64-bit registers and remember super reg and its flags.
- MachineOperand &HighRegOp = EarlierMI->getOperand(0);
- MachineOperand &LowRegOp = MI->getOperand(0);
+ MachineOperand &HighRegOp = HighPartMI->getOperand(0);
+ MachineOperand &LowRegOp = LowPartMI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
- if (MI->mayStore()) {
-// Add implicit uses of the super register in case one of the subregs is
-// undefined. We could track liveness and skip storing an undefined
-// subreg, but this is hopefully rare (discovered with llvm-stress).
-// If Reg128 was killed, set kill flag on MI.
-unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
-MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
-MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
- }
-
// The address in the first (high) instruction is already correct.
// Adjust the offset in the second (low) instruction.
- MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
- MachineOperand &LowOffsetOp = MI->getOperand(2);
+ MachineOperand &HighOffsetOp = HighPartMI->getOperand(2);
+ MachineOperand &LowOffsetOp = LowPartMI->getOperand(2);
LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
- // Clear the kill flags on the registers in the first instruction.
- if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
-EarlierMI->getOperand(0).setIsKill(false);
- EarlierMI->getOperand(1).setIsKill(false);
- EarlierMI->getOperand(3).setIsKill(false);
-
// Set the opcodes.
unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
assert(HighOpcode && LowOpcode && "Both offsets should be in range");
+ HighPartMI->setDesc(get(HighOpcode));
+ LowPartMI->setDesc(get(LowOpcode));
+
+ MachineInstr *FirstMI = HighPartMI;
+ if (MI->mayStore()) {
+FirstMI->getOperand(0).setIsKill(false);
+// Add implicit uses of the super register in case one of the subregs is
+// undefined. We could track liveness and skip storing an undefined
+// subreg, but this is hopefully rare (discovered with llvm-stress).
+// If Reg128 was killed, set kill flag on MI.
+unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
+MachineInstrBuilder(MF, HighPartMI).addReg(Reg128, Reg128UndefImpl);
+MachineInstrBuilder(MF, LowPartMI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
+ } else {
+// If HighPartMI clobbers any of the address registers, it needs to come
+// after LowPartMI.
+auto overlapsAddressReg = [&](Register Reg) -> bool {
+ return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||
+ RI.regsOverlap(Reg, MI->get
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
tstellar wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92129
>From c6d5546189311e81aeee251d0d40dd970ae2f70e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?=
Date: Tue, 14 May 2024 15:54:05 +0200
Subject: [PATCH] [GlobalIsel][AArch64] fix out of range access in
regbankselect (#92072)
Fixes https://github.com/llvm/llvm-project/issues/92062
(cherry picked from commit d422e90fcb68749918ddd86c94188807efce)
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 5 -
llvm/test/CodeGen/AArch64/pr92062.ll | 21 +++
2 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/pr92062.ll
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const
MachineInstr &MI) const {
EltTy = GV->getValueType();
// Look at the first element of the struct to determine the type we are
// loading
-while (StructType *StructEltTy = dyn_cast(EltTy))
+while (StructType *StructEltTy = dyn_cast(EltTy)) {
+ if (StructEltTy->getNumElements() == 0)
+break;
EltTy = StructEltTy->getTypeAtIndex(0U);
+}
// Look at the first element of the array to determine its type
if (isa(EltTy))
EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll
b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+@p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %bb
+; CHECK-NEXT:adrp x8, :got:p
+; CHECK-NEXT:ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:ldr x8, [x8]
+; CHECK-NEXT:mov x9, xzr
+; CHECK-NEXT:str x8, [x9]
+; CHECK-NEXT:ret
+bb:
+ %i1 = load ptr, ptr @p, align 8
+ store ptr %i1, ptr null, align 8
+ ret void
+}
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[llvm-branch-commits] [llvm] c6d5546 - [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072)
Author: Thorsten Schütt
Date: 2024-05-15T19:08:49-07:00
New Revision: c6d5546189311e81aeee251d0d40dd970ae2f70e
URL:
https://github.com/llvm/llvm-project/commit/c6d5546189311e81aeee251d0d40dd970ae2f70e
DIFF:
https://github.com/llvm/llvm-project/commit/c6d5546189311e81aeee251d0d40dd970ae2f70e.diff
LOG: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072)
Fixes https://github.com/llvm/llvm-project/issues/92062
(cherry picked from commit d422e90fcb68749918ddd86c94188807efce)
Added:
llvm/test/CodeGen/AArch64/pr92062.ll
Modified:
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Removed:
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const
MachineInstr &MI) const {
EltTy = GV->getValueType();
// Look at the first element of the struct to determine the type we are
// loading
-while (StructType *StructEltTy = dyn_cast(EltTy))
+while (StructType *StructEltTy = dyn_cast(EltTy)) {
+ if (StructEltTy->getNumElements() == 0)
+break;
EltTy = StructEltTy->getTypeAtIndex(0U);
+}
// Look at the first element of the array to determine its type
if (isa(EltTy))
EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll
b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+@p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %bb
+; CHECK-NEXT:adrp x8, :got:p
+; CHECK-NEXT:ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:ldr x8, [x8]
+; CHECK-NEXT:mov x9, xzr
+; CHECK-NEXT:str x8, [x9]
+; CHECK-NEXT:ret
+bb:
+ %i1 = load ptr, ptr @p, align 8
+ store ptr %i1, ptr null, align 8
+ ret void
+}
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[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
tstellar wrote: @DianQK (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91682
>From aa2549e2bf1297af5fe2bc1903025e5d30e18f54 Mon Sep 17 00:00:00 2001
From: Rose
Date: Thu, 9 May 2024 19:52:24 -0400
Subject: [PATCH] Revert "[SLP]Fix a crash if the argument of call was affected
by minbitwidth analysis."
After reconsidering the words of @nikic, I have decided to revisit the patches
I suggested be backported. Upon further analysis, I think there is a high
likelihood that this change added to release 18.x was referencing a crash that
was caused by a PR that isn't added.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
---
.../Transforms/Vectorize/SLPVectorizer.cpp| 21 +--
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
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[llvm-branch-commits] [llvm] aa2549e - Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis."
Author: Rose
Date: 2024-05-15T19:11:07-07:00
New Revision: aa2549e2bf1297af5fe2bc1903025e5d30e18f54
URL:
https://github.com/llvm/llvm-project/commit/aa2549e2bf1297af5fe2bc1903025e5d30e18f54
DIFF:
https://github.com/llvm/llvm-project/commit/aa2549e2bf1297af5fe2bc1903025e5d30e18f54.diff
LOG: Revert "[SLP]Fix a crash if the argument of call was affected by
minbitwidth analysis."
After reconsidering the words of @nikic, I have decided to revisit the patches
I suggested be backported. Upon further analysis, I think there is a high
likelihood that this change added to release 18.x was referencing a crash that
was caused by a PR that isn't added.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
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[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
DianQK wrote: > @DianQK (or anyone else). If you would like to add a note about this fix in > the release notes (completely optional). Please reply to this comment with a > one or two sentence description of the fix. When you are done, please add the > release:note label to this PR. Perhaps @tschuett will provide? https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)
@@ -49,63 +50,127 @@ static ABI checkABIStandardized(ABI Abi) {
return Abi;
}
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
- ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
bool Is64Bit = TT.isArch64Bit();
ABI TripleABI;
-
- // Figure out the ABI explicitly requested via the triple's environment type.
switch (TT.getEnvironment()) {
case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
break;
case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
break;
-
// Let the fallback case behave like {ILP32,LP64}D.
case llvm::Triple::EnvironmentType::GNUF64:
default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
break;
}
+ return TripleABI;
+}
- switch (ArgProvidedABI) {
- case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
- errs() << "'" << ABIName
- << "' is not a recognized ABI for this target, ignoring and using
"
-"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+ bool Is64Bit = TT.isArch64Bit();
+ ABI ArgProvidedABI = getTargetABI(ABIName);
+ ABI TripleABI = getTripleABI(TT);
+
+ auto GetFeatureABI = [=]() {
SixWeining wrote:
Maybe move it to where it is called (i.e. line 173) for better readability?
https://github.com/llvm/llvm-project/pull/92223
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