[llvm-branch-commits] [llvm] release/18.x: [PPCMergeStringPool] Avoid replacing constant with instruction (#88846) (PR #91557)
https://github.com/nikic updated https://github.com/llvm/llvm-project/pull/91557
>From d17c08705c750388a4ae586dc9fb892d81dba5ca Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Thu, 9 May 2024 13:27:20 +0900
Subject: [PATCH] [PPCMergeStringPool] Avoid replacing constant with
instruction (#88846)
String pool merging currently, for a reason that's not entirely clear to
me, tries to create GEP instructions instead of GEP constant expressions
when replacing constant references. It only uses constant expressions in
cases where this is required. However, it does not catch all cases where
such a requirement exists. For example, the landingpad catch clause has
to be a constant.
Fix this by always using the constant expression variant, which also
makes the implementation simpler.
Additionally, there are some edge cases where even replacement with a
constant GEP is not legal. The one I am aware of is the
llvm.eh.typeid.for intrinsic, so add a special case to forbid
replacements for it.
Fixes https://github.com/llvm/llvm-project/issues/88844.
(cherry picked from commit 3a3aeb8eba40e981d3a9ff92175f949c2f3d4434)
---
.../lib/Target/PowerPC/PPCMergeStringPool.cpp | 57 ++-
.../mergeable-string-pool-exceptions.ll | 47 +++
.../PowerPC/mergeable-string-pool-large.ll| 14 ++---
.../mergeable-string-pool-pass-only.mir | 18 +++---
.../CodeGen/PowerPC/mergeable-string-pool.ll | 14 ++---
5 files changed, 87 insertions(+), 63 deletions(-)
create mode 100644
llvm/test/CodeGen/PowerPC/mergeable-string-pool-exceptions.ll
diff --git a/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp
b/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp
index d9465e86d8966..ebd876d50c44e 100644
--- a/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp
@@ -23,6 +23,7 @@
#include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/ValueSymbolTable.h"
#include "llvm/Pass.h"
@@ -116,9 +117,20 @@ class PPCMergeStringPool : public ModulePass {
// sure that they can be replaced.
static bool hasReplaceableUsers(GlobalVariable &GV) {
for (User *CurrentUser : GV.users()) {
-// Instruction users are always valid.
-if (isa(CurrentUser))
+if (auto *I = dyn_cast(CurrentUser)) {
+ // Do not merge globals in exception pads.
+ if (I->isEHPad())
+return false;
+
+ if (auto *II = dyn_cast(I)) {
+// Some intrinsics require a plain global.
+if (II->getIntrinsicID() == Intrinsic::eh_typeid_for)
+ return false;
+ }
+
+ // Other instruction users are always valid.
continue;
+}
// We cannot replace GlobalValue users because they are not just nodes
// in IR. To replace a user like this we would need to create a new
@@ -302,14 +314,6 @@ void PPCMergeStringPool::replaceUsesWithGEP(GlobalVariable
*GlobalToReplace,
Users.push_back(CurrentUser);
for (User *CurrentUser : Users) {
-Instruction *UserInstruction = dyn_cast(CurrentUser);
-Constant *UserConstant = dyn_cast(CurrentUser);
-
-// At this point we expect that the user is either an instruction or a
-// constant.
-assert((UserConstant || UserInstruction) &&
- "Expected the user to be an instruction or a constant.");
-
// The user was not found so it must have been replaced earlier.
if (!userHasOperand(CurrentUser, GlobalToReplace))
continue;
@@ -318,38 +322,13 @@ void
PPCMergeStringPool::replaceUsesWithGEP(GlobalVariable *GlobalToReplace,
if (isa(CurrentUser))
continue;
-if (!UserInstruction) {
- // User is a constant type.
- Constant *ConstGEP = ConstantExpr::getInBoundsGetElementPtr(
- PooledStructType, GPool, Indices);
- UserConstant->handleOperandChange(GlobalToReplace, ConstGEP);
- continue;
-}
-
-if (PHINode *UserPHI = dyn_cast(UserInstruction)) {
- // GEP instructions cannot be added before PHI nodes.
- // With getInBoundsGetElementPtr we create the GEP and then replace it
- // inline into the PHI.
- Constant *ConstGEP = ConstantExpr::getInBoundsGetElementPtr(
- PooledStructType, GPool, Indices);
- UserPHI->replaceUsesOfWith(GlobalToReplace, ConstGEP);
- continue;
-}
-// The user is a valid instruction that is not a PHINode.
-GetElementPtrInst *GEPInst =
-GetElementPtrInst::Create(PooledStructType, GPool, Indices);
-GEPInst->insertBefore(UserInstruction);
-
-LLVM_DEBUG(dbgs() << "Inserting GEP before:\n");
-LLVM_DEBUG(UserInstruction->dump());
-
+Constant *ConstGEP = ConstantExpr::getInBoundsGetElementPtr(
+PooledStructType, GPool, Indices);
LLVM_DEBUG(dbgs() << "Replacing this global:\n");
LLVM_DEBUG(GlobalToReplace->dump());
LLVM_DEBUG(dbgs() << "with this:\n");
-
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
https://github.com/marcauberer created
https://github.com/llvm/llvm-project/pull/91580
Backport c482fad2c1de367f8fef2b40361dec00523707f7
This cherry-pick includes some ref fixes due to the incompatibility between
`main` and `release/18.x`.
>From 39f3ca9677a63ddc404e7ee13edace2bbf72fc93 Mon Sep 17 00:00:00 2001
From: Marc Auberer
Date: Thu, 28 Mar 2024 23:08:38 +0100
Subject: [PATCH 1/2] [AArch64][GISEL] Consider fcmp true and fcmp false in
cond code selection (#86972)
Fixes #86917
`FCMP_TRUE` and `FCMP_FALSE` were previously not considered and we ended
up in an llvm_unreachable assertion.
---
.../AArch64/GISel/AArch64GlobalISelUtils.cpp | 6 ++
.../CodeGen/AArch64/GlobalISel/select.mir | 20
.../AArch64/neon-compare-instructions.ll | 101 ++
3 files changed, 127 insertions(+)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index 92db89cc0915b..80fe4bcb8b58f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -147,6 +147,12 @@ void AArch64GISelUtils::changeFCMPPredToAArch64CC(
case CmpInst::FCMP_UNE:
CondCode = AArch64CC::NE;
break;
+ case CmpInst::FCMP_TRUE:
+CondCode = AArch64CC::AL;
+break;
+ case CmpInst::FCMP_FALSE:
+CondCode = AArch64CC::NV;
+break;
}
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 60cddbf794bc7..ae78d4be0f88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -183,6 +183,14 @@ registers:
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
+ - { id: 8, class: fpr }
+ - { id: 9, class: gpr }
+ - { id: 10, class: fpr }
+ - { id: 11, class: gpr }
+ - { id: 12, class: gpr }
+ - { id: 13, class: gpr }
+ - { id: 14, class: gpr }
+ - { id: 15, class: gpr }
# CHECK: body:
# CHECK:nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
@@ -209,6 +217,18 @@ body: |
%7(s32) = G_ANYEXT %5
$w0 = COPY %7(s32)
+%8(s32) = COPY $s0
+%9(s32) = G_FCMP floatpred(true), %8, %8
+%12(s8) = G_TRUNC %9(s32)
+%14(s32) = G_ANYEXT %12
+$w0 = COPY %14(s32)
+
+%10(s64) = COPY $d0
+%11(s32) = G_FCMP floatpred(false), %10, %10
+%13(s8) = G_TRUNC %11(s32)
+%15(s32) = G_ANYEXT %13
+$w0 = COPY %15(s32)
+
...
---
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 765c81e26e13c..c4c00f8e97942 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -2870,6 +2870,107 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x
double> %B) {
ret <2 x i64> %tmp4
}
+define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-SD-LABEL: fcmal2xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:shl v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:sshr v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmal4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:mov w8, #1 // =0x1
+; CHECK-GI-NEXT:fmov s0, w8
+; CHECK-GI-NEXT:mov v1.16b, v0.16b
+; CHECK-GI-NEXT:mov v1.h[1], v0.h[0]
+; CHECK-GI-NEXT:mov v0.h[1], v0.h[0]
+; CHECK-GI-NEXT:ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT:ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT:mov v1.d[1], v0.d[0]
+; CHECK-GI-NEXT:shl v0.4s, v1.4s, #31
+; CHECK-GI-NEXT:sshr v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <4 x float> %A, %B
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) {
+; CHECK-SD-LABEL: fcmal2xdouble:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xdouble:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:adrp x8, .LCPI221_0
+; CHECK-GI-NEXT:ldr q0, [x8, :lo12:.LCPI221_0]
+; CHECK-GI-NEXT:shl v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:sshr v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x double> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: fcmnv2xfloat:
+; CHECK: //
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
https://github.com/marcauberer milestoned https://github.com/llvm/llvm-project/pull/91580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Marc Auberer (marcauberer)
Changes
Backport c482fad2c1de367f8fef2b40361dec00523707f7
This cherry-pick includes some ref fixes due to the incompatibility between
`main` and `release/18.x`.
---
Full diff: https://github.com/llvm/llvm-project/pull/91580.diff
3 Files Affected:
- (modified) llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp (+6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select.mir (+20)
- (modified) llvm/test/CodeGen/AArch64/neon-compare-instructions.ll (+89)
``diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index 92db89cc0915b..80fe4bcb8b58f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -147,6 +147,12 @@ void AArch64GISelUtils::changeFCMPPredToAArch64CC(
case CmpInst::FCMP_UNE:
CondCode = AArch64CC::NE;
break;
+ case CmpInst::FCMP_TRUE:
+CondCode = AArch64CC::AL;
+break;
+ case CmpInst::FCMP_FALSE:
+CondCode = AArch64CC::NV;
+break;
}
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 60cddbf794bc7..ae78d4be0f88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -183,6 +183,14 @@ registers:
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
+ - { id: 8, class: fpr }
+ - { id: 9, class: gpr }
+ - { id: 10, class: fpr }
+ - { id: 11, class: gpr }
+ - { id: 12, class: gpr }
+ - { id: 13, class: gpr }
+ - { id: 14, class: gpr }
+ - { id: 15, class: gpr }
# CHECK: body:
# CHECK:nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
@@ -209,6 +217,18 @@ body: |
%7(s32) = G_ANYEXT %5
$w0 = COPY %7(s32)
+%8(s32) = COPY $s0
+%9(s32) = G_FCMP floatpred(true), %8, %8
+%12(s8) = G_TRUNC %9(s32)
+%14(s32) = G_ANYEXT %12
+$w0 = COPY %14(s32)
+
+%10(s64) = COPY $d0
+%11(s32) = G_FCMP floatpred(false), %10, %10
+%13(s8) = G_TRUNC %11(s32)
+%15(s32) = G_ANYEXT %13
+$w0 = COPY %15(s32)
+
...
---
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 765c81e26e13c..f398a7f8b8caa 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -2870,6 +2870,95 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x
double> %B) {
ret <2 x i64> %tmp4
}
+define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-SD-LABEL: fcmal2xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:shl v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:sshr v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmal4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:mov v0.d[1], v0.d[0]
+; CHECK-GI-NEXT:shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:sshr v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <4 x float> %A, %B
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) {
+; CHECK-SD-LABEL: fcmal2xdouble:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xdouble:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:adrp x8, .LCPI221_0
+; CHECK-GI-NEXT:ldr q0, [x8, :lo12:.LCPI221_0]
+; CHECK-GI-NEXT:shl v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:sshr v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x double> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: fcmnv2xfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:movi v0.2d, #
+; CHECK-NEXT:ret
+ %tmp3 = fcmp false <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmnv4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmnv4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmnv4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2d, #0
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Marc Auberer (marcauberer)
Changes
Backport c482fad2c1de367f8fef2b40361dec00523707f7
This cherry-pick includes some ref fixes due to the incompatibility between
`main` and `release/18.x`.
---
Full diff: https://github.com/llvm/llvm-project/pull/91580.diff
3 Files Affected:
- (modified) llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp (+6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select.mir (+20)
- (modified) llvm/test/CodeGen/AArch64/neon-compare-instructions.ll (+89)
``diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index 92db89cc0915b..80fe4bcb8b58f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -147,6 +147,12 @@ void AArch64GISelUtils::changeFCMPPredToAArch64CC(
case CmpInst::FCMP_UNE:
CondCode = AArch64CC::NE;
break;
+ case CmpInst::FCMP_TRUE:
+CondCode = AArch64CC::AL;
+break;
+ case CmpInst::FCMP_FALSE:
+CondCode = AArch64CC::NV;
+break;
}
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 60cddbf794bc7..ae78d4be0f88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -183,6 +183,14 @@ registers:
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
+ - { id: 8, class: fpr }
+ - { id: 9, class: gpr }
+ - { id: 10, class: fpr }
+ - { id: 11, class: gpr }
+ - { id: 12, class: gpr }
+ - { id: 13, class: gpr }
+ - { id: 14, class: gpr }
+ - { id: 15, class: gpr }
# CHECK: body:
# CHECK:nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
@@ -209,6 +217,18 @@ body: |
%7(s32) = G_ANYEXT %5
$w0 = COPY %7(s32)
+%8(s32) = COPY $s0
+%9(s32) = G_FCMP floatpred(true), %8, %8
+%12(s8) = G_TRUNC %9(s32)
+%14(s32) = G_ANYEXT %12
+$w0 = COPY %14(s32)
+
+%10(s64) = COPY $d0
+%11(s32) = G_FCMP floatpred(false), %10, %10
+%13(s8) = G_TRUNC %11(s32)
+%15(s32) = G_ANYEXT %13
+$w0 = COPY %15(s32)
+
...
---
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 765c81e26e13c..f398a7f8b8caa 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -2870,6 +2870,95 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x
double> %B) {
ret <2 x i64> %tmp4
}
+define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-SD-LABEL: fcmal2xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:shl v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:sshr v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmal4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:mov v0.d[1], v0.d[0]
+; CHECK-GI-NEXT:shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:sshr v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <4 x float> %A, %B
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) {
+; CHECK-SD-LABEL: fcmal2xdouble:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xdouble:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:adrp x8, .LCPI221_0
+; CHECK-GI-NEXT:ldr q0, [x8, :lo12:.LCPI221_0]
+; CHECK-GI-NEXT:shl v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:sshr v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x double> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: fcmnv2xfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:movi v0.2d, #
+; CHECK-NEXT:ret
+ %tmp3 = fcmp false <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmnv4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmnv4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmnv4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2d, #0
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 0f71196 - Revert "[AArch64] Add intrinsics for multi-vector to ZA array vector accumula…"
Author: Momchil Velikov
Date: 2024-05-09T15:01:53+01:00
New Revision: 0f71196108d1c3c1bb44305a3a8392f406ae71e9
URL:
https://github.com/llvm/llvm-project/commit/0f71196108d1c3c1bb44305a3a8392f406ae71e9
DIFF:
https://github.com/llvm/llvm-project/commit/0f71196108d1c3c1bb44305a3a8392f406ae71e9.diff
LOG: Revert "[AArch64] Add intrinsics for multi-vector to ZA array vector
accumula…"
This reverts commit e88ba6d975d887ca001cae30bfa0c53d91165148.
Added:
Modified:
clang/include/clang/Basic/arm_sme.td
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
Removed:
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
diff --git a/clang/include/clang/Basic/arm_sme.td
b/clang/include/clang/Basic/arm_sme.td
index 000bd97a4b25d..1ac6d5170ea28 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -298,16 +298,6 @@ multiclass ZAAddSub {
def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2",
"vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming,
IsInOutZA], []>;
def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4",
"vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming,
IsInOutZA], []>;
}
-
- let TargetGuard = "sme-f16f16|sme-f8f16" in {
-def NAME # _ZA16_VG1X2_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2",
"vm2", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming,
IsInOutZA], []>;
-def NAME # _ZA16_VG1X4_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4",
"vm4", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming,
IsInOutZA], []>;
- }
-
- let TargetGuard = "sme2,b16b16" in {
-def NAME # _ZA16_VG1X2_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2",
"vm2", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming,
IsInOutZA], []>;
-def NAME # _ZA16_VG1X4_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4",
"vm4", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming,
IsInOutZA], []>;
- }
}
defm SVADD : ZAAddSub<"add">;
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
deleted file mode 100644
index d98427fac610b..0
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
+++ /dev/null
@@ -1,193 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
-// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1-x c++ -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s -check-prefix CHECK-CXX
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS-fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s -check-prefix CHECK-CXX
-
-// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -o /dev/null
-
-// REQUIRES: aarch64-registered-target
-
-#include
-
-#ifdef SVE_OVERLOADED_FORMS
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3
-#endif
-
-// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_f16(
-// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call
@llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0)
-// CHECK-NEXT:[[TMP1:%.*]] = tail call
@llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8)
-// CHECK-NEXT:tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32
[[SLICE]], [[TMP0]], [[TMP1]])
-// CHECK-NEXT:ret void
-//
-// CHECK-CXX-LABEL: define dso_local void
@_Z25test_svadd_za16_vg1x2_f16j13svfloat16x2_t(
-// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// CHECK-CXX-NEXT: entry:
-// CHECK-CXX-NEXT:[[
[llvm-branch-commits] [lld] [llvm] release/18.x: [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols (PR #91632)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/91632
Backport f6f474c4ef9694a4ca8f08d59fd112c250fb9c73
Requested by: @tstellar
>From 57b98e6ec41f5f095ebcbe9daf42ea30fea69702 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 20 Mar 2024 13:39:39 -0700
Subject: [PATCH] [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols
Currently, we mistakenly mark the local labels used in RISC-V TLSDESC as
TLS symbols, when they should not be. This patch adds tests with the
current incorrect behavior, and subsequent patches will address the
issue.
Reviewers: MaskRay, topperc
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/85816
(cherry picked from commit f6f474c4ef9694a4ca8f08d59fd112c250fb9c73)
---
lld/test/ELF/riscv-tlsdesc.s | 25 +++
llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll | 24 ++
2 files changed, 49 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index 1738f86256caa..c583e15cf30ce 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,6 +29,12 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
+# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
+# RUN: not ld.lld -shared -soname=d.64.so -o d.64.so d.64.o 2>&1 | FileCheck
%s --check-prefix=BADTLSLABEL
+
+# RUN: llvm-mc -triple=riscv32 -filetype=obj d.s -o d.32.o --defsym ELF32=1
+# RUN: not ld.lld -shared -soname=d.32.so -o d.32.so d.32.o 2>&1 | FileCheck
%s --check-prefix=BADTLSLABEL
+
# GD64-RELA: .rela.dyn {
# GD64-RELA-NEXT: 0x2408 R_RISCV_TLSDESC - 0x7FF
# GD64-RELA-NEXT: 0x23E8 R_RISCV_TLSDESC a 0x0
@@ -150,6 +156,9 @@
# IE32-NEXT: lw a0, 0x80(a0)
# IE32-NEXT: add a0, a0, tp
+## FIXME This should not pass, but the code MC layer needs a fix to prevent
this.
+# BADTLSLABEL: error: d.{{.*}}.o has an STT_TLS symbol but doesn't have an
SHF_TLS section
+
#--- a.s
.macro load dst, src
.ifdef ELF32
@@ -192,3 +201,19 @@ b:
.tbss
.globl c
c: .zero 4
+
+#--- d.s
+.macro load dst, src
+.ifdef ELF32
+lw \dst, \src
+.else
+ld \dst, \src
+.endif
+.endm
+
+.Ltlsdesc_hi0:
+ auipca0, %tlsdesc_hi(foo)
+ load a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0)
+ addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0)
+ jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0)
+ add a1, a0, tp
diff --git a/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
b/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
new file mode 100644
index 0..23ba2ffb1ad76
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
@@ -0,0 +1,24 @@
+;; The test in this file do not appear in tls-models.ll because
+;; they are not auto-generated.
+; RUN: llc -mtriple=riscv64 -relocation-model=pic -enable-tlsdesc < %s \
+; RUN: | llvm-mc -triple=riscv64 -filetype=obj -o - \
+; RUN: | llvm-readelf --symbols - \
+; RUN: | FileCheck %s
+
+; RUN: llc -mtriple=riscv32 -relocation-model=pic -enable-tlsdesc < %s \
+; RUN: | llvm-mc -triple=riscv32 -filetype=obj -o - \
+; RUN: | llvm-readelf --symbols - \
+; RUN: | FileCheck %s
+
+; Check that TLS symbols are lowered correctly based on the specified
+; model. Make sure they're external to avoid them all being optimised to Local
+; Exec for the executable.
+
+@unspecified = external thread_local global i32
+
+define ptr @f1() nounwind {
+entry:
+ ret ptr @unspecified
+ ; CHECK: Symbol table '.symtab' contains 7 entries:
+ ; CHECK: TLS {{.*}} unspecified
+}
___
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[llvm-branch-commits] [lld] [llvm] release/18.x: [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols (PR #91632)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/91632 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols (PR #91632)
llvmbot wrote: @MaskRay What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/91632 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols (PR #91632)
llvmbot wrote:
@llvm/pr-subscribers-lld
Author: None (llvmbot)
Changes
Backport f6f474c4ef9694a4ca8f08d59fd112c250fb9c73
Requested by: @tstellar
---
Full diff: https://github.com/llvm/llvm-project/pull/91632.diff
2 Files Affected:
- (modified) lld/test/ELF/riscv-tlsdesc.s (+25)
- (added) llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll (+24)
``diff
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index 1738f86256caa..c583e15cf30ce 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,6 +29,12 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
+# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
+# RUN: not ld.lld -shared -soname=d.64.so -o d.64.so d.64.o 2>&1 | FileCheck
%s --check-prefix=BADTLSLABEL
+
+# RUN: llvm-mc -triple=riscv32 -filetype=obj d.s -o d.32.o --defsym ELF32=1
+# RUN: not ld.lld -shared -soname=d.32.so -o d.32.so d.32.o 2>&1 | FileCheck
%s --check-prefix=BADTLSLABEL
+
# GD64-RELA: .rela.dyn {
# GD64-RELA-NEXT: 0x2408 R_RISCV_TLSDESC - 0x7FF
# GD64-RELA-NEXT: 0x23E8 R_RISCV_TLSDESC a 0x0
@@ -150,6 +156,9 @@
# IE32-NEXT: lw a0, 0x80(a0)
# IE32-NEXT: add a0, a0, tp
+## FIXME This should not pass, but the code MC layer needs a fix to prevent
this.
+# BADTLSLABEL: error: d.{{.*}}.o has an STT_TLS symbol but doesn't have an
SHF_TLS section
+
#--- a.s
.macro load dst, src
.ifdef ELF32
@@ -192,3 +201,19 @@ b:
.tbss
.globl c
c: .zero 4
+
+#--- d.s
+.macro load dst, src
+.ifdef ELF32
+lw \dst, \src
+.else
+ld \dst, \src
+.endif
+.endm
+
+.Ltlsdesc_hi0:
+ auipca0, %tlsdesc_hi(foo)
+ load a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0)
+ addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0)
+ jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0)
+ add a1, a0, tp
diff --git a/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
b/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
new file mode 100644
index 0..23ba2ffb1ad76
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
@@ -0,0 +1,24 @@
+;; The test in this file do not appear in tls-models.ll because
+;; they are not auto-generated.
+; RUN: llc -mtriple=riscv64 -relocation-model=pic -enable-tlsdesc < %s \
+; RUN: | llvm-mc -triple=riscv64 -filetype=obj -o - \
+; RUN: | llvm-readelf --symbols - \
+; RUN: | FileCheck %s
+
+; RUN: llc -mtriple=riscv32 -relocation-model=pic -enable-tlsdesc < %s \
+; RUN: | llvm-mc -triple=riscv32 -filetype=obj -o - \
+; RUN: | llvm-readelf --symbols - \
+; RUN: | FileCheck %s
+
+; Check that TLS symbols are lowered correctly based on the specified
+; model. Make sure they're external to avoid them all being optimised to Local
+; Exec for the executable.
+
+@unspecified = external thread_local global i32
+
+define ptr @f1() nounwind {
+entry:
+ ret ptr @unspecified
+ ; CHECK: Symbol table '.symtab' contains 7 entries:
+ ; CHECK: TLS {{.*}} unspecified
+}
``
https://github.com/llvm/llvm-project/pull/91632
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[llvm-branch-commits] [llvm] [NFC][CallPromotionUtils]Extract a helper function versionCallSiteWithCond from versionCallSite (PR #81181)
https://github.com/minglotus-6 edited https://github.com/llvm/llvm-project/pull/81181 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [openmp] [Clang][OpenMP][Tile] Allow non-constant tile sizes. (PR #91345)
@@ -15197,6 +15202,36 @@ StmtResult
SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses,
// Once the original iteration values are set, append the innermost body.
Stmt *Inner = Body;
+ auto MakeDimTileSize = [&SemaRef = this->SemaRef, &CopyTransformer, &Context,
+ SizesClause, CurScope](int I) -> Expr * {
+Expr *DimTileSizeExpr = SizesClause->getSizesRefs()[I];
+if (isa(DimTileSizeExpr))
+ return AssertSuccess(CopyTransformer.TransformExpr(DimTileSizeExpr));
+
+// When the tile size is not a constant but a variable, it is possible to
+// pass non-positive numbers. To preserve the invariant that every loop
alexey-bataev wrote:
Sure. I'm just saying that it is better to clarify this comment.
https://github.com/llvm/llvm-project/pull/91345
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[llvm-branch-commits] [clang] [openmp] [Clang][OpenMP][Tile] Allow non-constant tile sizes. (PR #91345)
@@ -17432,16 +17457,54 @@ OMPClause
*SemaOpenMP::ActOnOpenMPSizesClause(ArrayRef SizeExprs,
SourceLocation StartLoc,
SourceLocation LParenLoc,
SourceLocation EndLoc) {
- for (Expr *SizeExpr : SizeExprs) {
-ExprResult NumForLoopsResult = VerifyPositiveIntegerConstantInClause(
-SizeExpr, OMPC_sizes, /*StrictlyPositive=*/true);
-if (!NumForLoopsResult.isUsable())
- return nullptr;
+ SmallVector SanitizedSizeExprs;
+ llvm::append_range(SanitizedSizeExprs, SizeExprs);
+
+ for (Expr *&SizeExpr : SanitizedSizeExprs) {
+// Skip if already sanitized, e.g. during a partial template instantiation.
+if (!SizeExpr)
+ continue;
+
+bool IsValid = isNonNegativeIntegerValue(SizeExpr, SemaRef, OMPC_sizes,
+ /*StrictlyPositive=*/true);
+
+// isNonNegativeIntegerValue returns true for non-integral types (but still
+// emits error diagnostic), so check for the expected type explicitly.
+QualType SizeTy = SizeExpr->getType();
+if (!SizeTy->isIntegerType())
+ IsValid = false;
+
+// Handling in templates is tricky. There are four possibilities to
+// consider:
+//
+// 1a. The expression is valid and we are in a instantiated template or not
+// in a template:
+// Pass valid expression to be further analysed later in Sema.
+// 1b. The expression is valid and we are in a template (including partial
+// instantiation):
+// isNonNegativeIntegerValue skipped any checks so there is no
+// guarantee it will be correct after instantiation.
+// ActOnOpenMPSizesClause will be called again at instantiation when
+// it is not in a dependent context anymore. This may cause warnings
+// to be emitted multiple times.
+// 2a. The expression is invalid and we are in an instantiated template or
+// not in a template:
+// Invalidate the expression with a clearly wrong value (nullptr) so
+// later in Sema we do not have to do the same validity analysis
again
+// or crash from unexpected data. Error diagnostics have already been
+// emitted.
+// 2b. The expression is invalid and we are in a template (including
partial
+// instantiation):
+// Pass the invalid expression as-is, template instantiation may
+// replace unexpected types/values with valid ones. The directives
+// with this clause must not try to use these expressions in
dependent
+// contexts.
alexey-bataev wrote:
Sure, delaying is a good approach. If the analysis is delayed till actual
instantiation, it does not mean that the templates are not handled.
https://github.com/llvm/llvm-project/pull/91345
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[llvm-branch-commits] [llvm] [ThinLTO] Generate import status in per-module combined summary (PR #88024)
@@ -276,7 +276,7 @@ class ThinLTOCodeGenerator {
void gatherImportedSummariesForModule(
Module &Module, ModuleSummaryIndex &Index,
std::map &ModuleToSummariesForIndex,
- const lto::InputFile &File);
+ const lto::InputFile &File, GVSummaryPtrSet &DecSummaries);
jvoung wrote:
nit: consider keeping the outparams together (so DecSummaries next to
ModuleToSummariesForIndex, and File after?)
https://github.com/llvm/llvm-project/pull/88024
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[llvm-branch-commits] [llvm] [ThinLTO] Generate import status in per-module combined summary (PR #88024)
@@ -833,9 +833,14 @@ void ThinLTOCodeGenerator::emitImports(Module &TheModule, StringRef OutputName, ExportLists); std::map ModuleToSummariesForIndex; + // 'EmitImportsFiles' emits the list of modules from which to import from, and + // the set of keys in `ModuleToSummariesForIndex` should be a superset of keys + // in `ModuleToDecSummaries`, so no need to use `ModuleToDecSummaries` in jvoung wrote: nit: update DecSummaries in comment https://github.com/llvm/llvm-project/pull/88024 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [ThinLTO] Generate import status in per-module combined summary (PR #88024)
@@ -207,11 +211,16 @@ bool convertToDeclaration(GlobalValue &GV); /// \p ModuleToSummariesForIndex will be populated with the needed summaries /// from each required module path. Use a std::map instead of StringMap to get /// stable order for bitcode emission. +/// +/// \p ModuleToDecSummaries will be populated with the set of declarations \p +/// ModulePath need from other modules. They key is module path, and the value jvoung wrote: nit: ModuleToDecSummaries -> DecSummaries now and update the "The key is ..." part https://github.com/llvm/llvm-project/pull/88024 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)
tstellar wrote: @aemerson Did you submit a new pull request with a fix? https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't remove parentheses of fold expressions (#91045) (PR #91165)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91165
>From 0abb89a80f5c0736843950dc39f2454ab312b319 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Sun, 5 May 2024 21:33:41 -0700
Subject: [PATCH] [clang-format] Don't remove parentheses of fold expressions
(#91045)
Fixes #90966.
(cherry picked from commit db0ed5533368414b1c4e1c884eef651c66359da2)
---
clang/lib/Format/UnwrappedLineParser.cpp | 7 ++-
clang/unittests/Format/FormatTest.cpp| 9 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index a6eb18bb2b322..f70affb732a0d 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2510,6 +2510,7 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
assert(FormatTok->is(tok::l_paren) && "'(' expected.");
auto *LeftParen = FormatTok;
bool SeenEqual = false;
+ bool MightBeFoldExpr = false;
const bool MightBeStmtExpr = Tokens->peekNextToken()->is(tok::l_brace);
nextToken();
do {
@@ -2521,7 +2522,7 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
parseChildBlock();
break;
case tok::r_paren:
- if (!MightBeStmtExpr && !Line->InMacroBody &&
+ if (!MightBeStmtExpr && !MightBeFoldExpr && !Line->InMacroBody &&
Style.RemoveParentheses > FormatStyle::RPS_Leave) {
const auto *Prev = LeftParen->Previous;
const auto *Next = Tokens->peekNextToken();
@@ -2564,6 +2565,10 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
parseBracedList();
}
break;
+case tok::ellipsis:
+ MightBeFoldExpr = true;
+ nextToken();
+ break;
case tok::equal:
SeenEqual = true;
if (Style.isCSharp() && FormatTok->is(TT_FatArrow))
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index 88877e53d014c..923128672c316 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -26894,8 +26894,14 @@ TEST_F(FormatTest, RemoveParentheses) {
"if ((({ a; })))\n"
" b;",
Style);
+ verifyFormat("static_assert((std::is_constructible_v && ...));",
+ "static_assert(((std::is_constructible_v &&
...)));",
+ Style);
verifyFormat("return (0);", "return (((0)));", Style);
verifyFormat("return (({ 0; }));", "return ((({ 0; })));", Style);
+ verifyFormat("return ((... && std::is_convertible_v));",
+ "return (((... && std::is_convertible_v)));",
+ Style);
Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement;
verifyFormat("#define Return0 return (0);", Style);
@@ -26903,6 +26909,9 @@ TEST_F(FormatTest, RemoveParentheses) {
verifyFormat("co_return 0;", "co_return ((0));", Style);
verifyFormat("return 0;", "return (((0)));", Style);
verifyFormat("return ({ 0; });", "return ((({ 0; })));", Style);
+ verifyFormat("return (... && std::is_convertible_v);",
+ "return (((... && std::is_convertible_v)));",
+ Style);
verifyFormat("inline decltype(auto) f() {\n"
" if (a) {\n"
"return (a);\n"
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[llvm-branch-commits] [clang] 0abb89a - [clang-format] Don't remove parentheses of fold expressions (#91045)
Author: Owen Pan
Date: 2024-05-09T12:16:32-07:00
New Revision: 0abb89a80f5c0736843950dc39f2454ab312b319
URL:
https://github.com/llvm/llvm-project/commit/0abb89a80f5c0736843950dc39f2454ab312b319
DIFF:
https://github.com/llvm/llvm-project/commit/0abb89a80f5c0736843950dc39f2454ab312b319.diff
LOG: [clang-format] Don't remove parentheses of fold expressions (#91045)
Fixes #90966.
(cherry picked from commit db0ed5533368414b1c4e1c884eef651c66359da2)
Added:
Modified:
clang/lib/Format/UnwrappedLineParser.cpp
clang/unittests/Format/FormatTest.cpp
Removed:
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index a6eb18bb2b322..f70affb732a0d 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2510,6 +2510,7 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
assert(FormatTok->is(tok::l_paren) && "'(' expected.");
auto *LeftParen = FormatTok;
bool SeenEqual = false;
+ bool MightBeFoldExpr = false;
const bool MightBeStmtExpr = Tokens->peekNextToken()->is(tok::l_brace);
nextToken();
do {
@@ -2521,7 +2522,7 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
parseChildBlock();
break;
case tok::r_paren:
- if (!MightBeStmtExpr && !Line->InMacroBody &&
+ if (!MightBeStmtExpr && !MightBeFoldExpr && !Line->InMacroBody &&
Style.RemoveParentheses > FormatStyle::RPS_Leave) {
const auto *Prev = LeftParen->Previous;
const auto *Next = Tokens->peekNextToken();
@@ -2564,6 +2565,10 @@ bool UnwrappedLineParser::parseParens(TokenType
AmpAmpTokenType) {
parseBracedList();
}
break;
+case tok::ellipsis:
+ MightBeFoldExpr = true;
+ nextToken();
+ break;
case tok::equal:
SeenEqual = true;
if (Style.isCSharp() && FormatTok->is(TT_FatArrow))
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index 88877e53d014c..923128672c316 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -26894,8 +26894,14 @@ TEST_F(FormatTest, RemoveParentheses) {
"if ((({ a; })))\n"
" b;",
Style);
+ verifyFormat("static_assert((std::is_constructible_v && ...));",
+ "static_assert(((std::is_constructible_v &&
...)));",
+ Style);
verifyFormat("return (0);", "return (((0)));", Style);
verifyFormat("return (({ 0; }));", "return ((({ 0; })));", Style);
+ verifyFormat("return ((... && std::is_convertible_v));",
+ "return (((... && std::is_convertible_v)));",
+ Style);
Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement;
verifyFormat("#define Return0 return (0);", Style);
@@ -26903,6 +26909,9 @@ TEST_F(FormatTest, RemoveParentheses) {
verifyFormat("co_return 0;", "co_return ((0));", Style);
verifyFormat("return 0;", "return (((0)));", Style);
verifyFormat("return ({ 0; });", "return ((({ 0; })));", Style);
+ verifyFormat("return (... && std::is_convertible_v);",
+ "return (((... && std::is_convertible_v)));",
+ Style);
verifyFormat("inline decltype(auto) f() {\n"
" if (a) {\n"
"return (a);\n"
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[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't remove parentheses of fold expressions (#91045) (PR #91165)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91165 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [FunctionAttrs] Fix incorrect nonnull inference for non-inbounds GEP (#91180) (PR #91286)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91286
>From 4a28f8e3c625e168c1cb9203150e3dc6495bb0fa Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Tue, 7 May 2024 09:47:28 +0900
Subject: [PATCH] [FunctionAttrs] Fix incorrect nonnull inference for
non-inbounds GEP (#91180)
For inbounds GEPs, if the source pointer is non-null, the result must
also be non-null. However, this does not hold for non-inbounds GEPs.
Fixes https://github.com/llvm/llvm-project/issues/91177.
(cherry picked from commit f34d30cdae0f59698f660d5cc8fb993fb3441064)
---
llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 7 +-
.../Transforms/FunctionAttrs/nocapture.ll | 2 +-
llvm/test/Transforms/FunctionAttrs/nonnull.ll | 23 +++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 7ebf265e17ba1..27c411250d53c 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -1186,10 +1186,15 @@ static bool isReturnNonNull(Function *F, const
SCCNodeSet &SCCNodes,
switch (RVI->getOpcode()) {
// Extend the analysis by looking upwards.
case Instruction::BitCast:
-case Instruction::GetElementPtr:
case Instruction::AddrSpaceCast:
FlowsToReturn.insert(RVI->getOperand(0));
continue;
+case Instruction::GetElementPtr:
+ if (cast(RVI)->isInBounds()) {
+FlowsToReturn.insert(RVI->getOperand(0));
+continue;
+ }
+ return false;
case Instruction::Select: {
SelectInst *SI = cast(RVI);
FlowsToReturn.insert(SI->getTrueValue());
diff --git a/llvm/test/Transforms/FunctionAttrs/nocapture.ll
b/llvm/test/Transforms/FunctionAttrs/nocapture.ll
index 3d483f671b1af..8d6f6a7c73f80 100644
--- a/llvm/test/Transforms/FunctionAttrs/nocapture.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nocapture.ll
@@ -197,7 +197,7 @@ declare i32 @__gxx_personality_v0(...)
define ptr @lookup_bit(ptr %q, i32 %bitno) readnone nounwind {
; FNATTRS: Function Attrs: mustprogress nofree norecurse nosync nounwind
willreturn memory(none)
-; FNATTRS-LABEL: define nonnull ptr @lookup_bit
+; FNATTRS-LABEL: define ptr @lookup_bit
; FNATTRS-SAME: (ptr [[Q:%.*]], i32 [[BITNO:%.*]]) #[[ATTR0]] {
; FNATTRS-NEXT:[[TMP:%.*]] = ptrtoint ptr [[Q]] to i32
; FNATTRS-NEXT:[[TMP2:%.*]] = lshr i32 [[TMP]], [[BITNO]]
diff --git a/llvm/test/Transforms/FunctionAttrs/nonnull.ll
b/llvm/test/Transforms/FunctionAttrs/nonnull.ll
index d9bdb6298ed0f..ec5545b969e55 100644
--- a/llvm/test/Transforms/FunctionAttrs/nonnull.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nonnull.ll
@@ -905,26 +905,26 @@ define i1 @parent8(ptr %a, ptr %bogus1, ptr %b)
personality ptr @esfp{
; FNATTRS-SAME: ptr nonnull [[A:%.*]], ptr nocapture readnone [[BOGUS1:%.*]],
ptr nonnull [[B:%.*]]) #[[ATTR7]] personality ptr @esfp {
; FNATTRS-NEXT: entry:
; FNATTRS-NEXT:invoke void @use2nonnull(ptr [[A]], ptr [[B]])
-; FNATTRS-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
+; FNATTRS-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
; FNATTRS: cont:
; FNATTRS-NEXT:[[NULL_CHECK:%.*]] = icmp eq ptr [[B]], null
; FNATTRS-NEXT:ret i1 [[NULL_CHECK]]
; FNATTRS: exc:
; FNATTRS-NEXT:[[LP:%.*]] = landingpad { ptr, i32 }
-; FNATTRS-NEXT:filter [0 x ptr] zeroinitializer
+; FNATTRS-NEXT:filter [0 x ptr] zeroinitializer
; FNATTRS-NEXT:unreachable
;
; ATTRIBUTOR-LABEL: define i1 @parent8(
; ATTRIBUTOR-SAME: ptr nonnull [[A:%.*]], ptr nocapture nofree readnone
[[BOGUS1:%.*]], ptr nonnull [[B:%.*]]) #[[ATTR8]] personality ptr @esfp {
; ATTRIBUTOR-NEXT: entry:
; ATTRIBUTOR-NEXT:invoke void @use2nonnull(ptr nonnull [[A]], ptr nonnull
[[B]])
-; ATTRIBUTOR-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
+; ATTRIBUTOR-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
; ATTRIBUTOR: cont:
; ATTRIBUTOR-NEXT:[[NULL_CHECK:%.*]] = icmp eq ptr [[B]], null
; ATTRIBUTOR-NEXT:ret i1 [[NULL_CHECK]]
; ATTRIBUTOR: exc:
; ATTRIBUTOR-NEXT:[[LP:%.*]] = landingpad { ptr, i32 }
-; ATTRIBUTOR-NEXT:filter [0 x ptr] zeroinitializer
+; ATTRIBUTOR-NEXT:filter [0 x ptr] zeroinitializer
; ATTRIBUTOR-NEXT:unreachable
;
@@ -1415,5 +1415,20 @@ define void @PR43833_simple(ptr %0, i32 %1) {
br i1 %11, label %7, label %8
}
+define ptr @pr91177_non_inbounds_gep(ptr nonnull %arg) {
+; FNATTRS-LABEL: define ptr @pr91177_non_inbounds_gep(
+; FNATTRS-SAME: ptr nonnull readnone [[ARG:%.*]]) #[[ATTR0]] {
+; FNATTRS-NEXT:[[RES:%.*]] = getelementptr i8, ptr [[ARG]], i64 -8
+; FNATTRS-NEXT:ret ptr [[RES]]
+;
+; ATTRIBUTOR-LABEL: define ptr @pr91177_non_inbounds_gep(
+; ATTRIBUTOR-SAME: ptr nofree nonnull readnone [[ARG:%.*]]) #[[ATTR0]] {
+; ATTRIBUTOR-NEXT:[[RES:%.*]] = getelementptr i8, ptr [[ARG]], i64 -8
+; ATTRIBUT
[llvm-branch-commits] [llvm] 4a28f8e - [FunctionAttrs] Fix incorrect nonnull inference for non-inbounds GEP (#91180)
Author: Nikita Popov
Date: 2024-05-09T12:18:19-07:00
New Revision: 4a28f8e3c625e168c1cb9203150e3dc6495bb0fa
URL:
https://github.com/llvm/llvm-project/commit/4a28f8e3c625e168c1cb9203150e3dc6495bb0fa
DIFF:
https://github.com/llvm/llvm-project/commit/4a28f8e3c625e168c1cb9203150e3dc6495bb0fa.diff
LOG: [FunctionAttrs] Fix incorrect nonnull inference for non-inbounds GEP
(#91180)
For inbounds GEPs, if the source pointer is non-null, the result must
also be non-null. However, this does not hold for non-inbounds GEPs.
Fixes https://github.com/llvm/llvm-project/issues/91177.
(cherry picked from commit f34d30cdae0f59698f660d5cc8fb993fb3441064)
Added:
Modified:
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Transforms/FunctionAttrs/nocapture.ll
llvm/test/Transforms/FunctionAttrs/nonnull.ll
Removed:
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 7ebf265e17ba1..27c411250d53c 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -1186,10 +1186,15 @@ static bool isReturnNonNull(Function *F, const
SCCNodeSet &SCCNodes,
switch (RVI->getOpcode()) {
// Extend the analysis by looking upwards.
case Instruction::BitCast:
-case Instruction::GetElementPtr:
case Instruction::AddrSpaceCast:
FlowsToReturn.insert(RVI->getOperand(0));
continue;
+case Instruction::GetElementPtr:
+ if (cast(RVI)->isInBounds()) {
+FlowsToReturn.insert(RVI->getOperand(0));
+continue;
+ }
+ return false;
case Instruction::Select: {
SelectInst *SI = cast(RVI);
FlowsToReturn.insert(SI->getTrueValue());
diff --git a/llvm/test/Transforms/FunctionAttrs/nocapture.ll
b/llvm/test/Transforms/FunctionAttrs/nocapture.ll
index 3d483f671b1af..8d6f6a7c73f80 100644
--- a/llvm/test/Transforms/FunctionAttrs/nocapture.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nocapture.ll
@@ -197,7 +197,7 @@ declare i32 @__gxx_personality_v0(...)
define ptr @lookup_bit(ptr %q, i32 %bitno) readnone nounwind {
; FNATTRS: Function Attrs: mustprogress nofree norecurse nosync nounwind
willreturn memory(none)
-; FNATTRS-LABEL: define nonnull ptr @lookup_bit
+; FNATTRS-LABEL: define ptr @lookup_bit
; FNATTRS-SAME: (ptr [[Q:%.*]], i32 [[BITNO:%.*]]) #[[ATTR0]] {
; FNATTRS-NEXT:[[TMP:%.*]] = ptrtoint ptr [[Q]] to i32
; FNATTRS-NEXT:[[TMP2:%.*]] = lshr i32 [[TMP]], [[BITNO]]
diff --git a/llvm/test/Transforms/FunctionAttrs/nonnull.ll
b/llvm/test/Transforms/FunctionAttrs/nonnull.ll
index d9bdb6298ed0f..ec5545b969e55 100644
--- a/llvm/test/Transforms/FunctionAttrs/nonnull.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nonnull.ll
@@ -905,26 +905,26 @@ define i1 @parent8(ptr %a, ptr %bogus1, ptr %b)
personality ptr @esfp{
; FNATTRS-SAME: ptr nonnull [[A:%.*]], ptr nocapture readnone [[BOGUS1:%.*]],
ptr nonnull [[B:%.*]]) #[[ATTR7]] personality ptr @esfp {
; FNATTRS-NEXT: entry:
; FNATTRS-NEXT:invoke void @use2nonnull(ptr [[A]], ptr [[B]])
-; FNATTRS-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
+; FNATTRS-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
; FNATTRS: cont:
; FNATTRS-NEXT:[[NULL_CHECK:%.*]] = icmp eq ptr [[B]], null
; FNATTRS-NEXT:ret i1 [[NULL_CHECK]]
; FNATTRS: exc:
; FNATTRS-NEXT:[[LP:%.*]] = landingpad { ptr, i32 }
-; FNATTRS-NEXT:filter [0 x ptr] zeroinitializer
+; FNATTRS-NEXT:filter [0 x ptr] zeroinitializer
; FNATTRS-NEXT:unreachable
;
; ATTRIBUTOR-LABEL: define i1 @parent8(
; ATTRIBUTOR-SAME: ptr nonnull [[A:%.*]], ptr nocapture nofree readnone
[[BOGUS1:%.*]], ptr nonnull [[B:%.*]]) #[[ATTR8]] personality ptr @esfp {
; ATTRIBUTOR-NEXT: entry:
; ATTRIBUTOR-NEXT:invoke void @use2nonnull(ptr nonnull [[A]], ptr nonnull
[[B]])
-; ATTRIBUTOR-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
+; ATTRIBUTOR-NEXT:to label [[CONT:%.*]] unwind label [[EXC:%.*]]
; ATTRIBUTOR: cont:
; ATTRIBUTOR-NEXT:[[NULL_CHECK:%.*]] = icmp eq ptr [[B]], null
; ATTRIBUTOR-NEXT:ret i1 [[NULL_CHECK]]
; ATTRIBUTOR: exc:
; ATTRIBUTOR-NEXT:[[LP:%.*]] = landingpad { ptr, i32 }
-; ATTRIBUTOR-NEXT:filter [0 x ptr] zeroinitializer
+; ATTRIBUTOR-NEXT:filter [0 x ptr] zeroinitializer
; ATTRIBUTOR-NEXT:unreachable
;
@@ -1415,5 +1415,20 @@ define void @PR43833_simple(ptr %0, i32 %1) {
br i1 %11, label %7, label %8
}
+define ptr @pr91177_non_inbounds_gep(ptr nonnull %arg) {
+; FNATTRS-LABEL: define ptr @pr91177_non_inbounds_gep(
+; FNATTRS-SAME: ptr nonnull readnone [[ARG:%.*]]) #[[ATTR0]] {
+; FNATTRS-NEXT:[[RES:%.*]] = getelementptr i8, ptr [[ARG]], i64 -8
+; FNATTRS-NEXT:ret ptr [[RES]]
+;
+; ATTRIBUTOR-LABEL: define ptr @pr91177_non_inbounds_gep(
+; ATTRIBUTOR-SAME: ptr nofree nonnull readnone [[ARG
[llvm-branch-commits] [llvm] release/18.x: [FunctionAttrs] Fix incorrect nonnull inference for non-inbounds GEP (#91180) (PR #91286)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91286 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91580
>From 1ffa00a01e5db29cb5c1b2cb6baed8e2b9381f81 Mon Sep 17 00:00:00 2001
From: Marc Auberer
Date: Thu, 28 Mar 2024 23:08:38 +0100
Subject: [PATCH 1/2] [AArch64][GISEL] Consider fcmp true and fcmp false in
cond code selection (#86972)
Fixes #86917
`FCMP_TRUE` and `FCMP_FALSE` were previously not considered and we ended
up in an llvm_unreachable assertion.
---
.../AArch64/GISel/AArch64GlobalISelUtils.cpp | 6 ++
.../CodeGen/AArch64/GlobalISel/select.mir | 20
.../AArch64/neon-compare-instructions.ll | 101 ++
3 files changed, 127 insertions(+)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index 92db89cc0915b..80fe4bcb8b58f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -147,6 +147,12 @@ void AArch64GISelUtils::changeFCMPPredToAArch64CC(
case CmpInst::FCMP_UNE:
CondCode = AArch64CC::NE;
break;
+ case CmpInst::FCMP_TRUE:
+CondCode = AArch64CC::AL;
+break;
+ case CmpInst::FCMP_FALSE:
+CondCode = AArch64CC::NV;
+break;
}
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 60cddbf794bc7..ae78d4be0f88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -183,6 +183,14 @@ registers:
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
+ - { id: 8, class: fpr }
+ - { id: 9, class: gpr }
+ - { id: 10, class: fpr }
+ - { id: 11, class: gpr }
+ - { id: 12, class: gpr }
+ - { id: 13, class: gpr }
+ - { id: 14, class: gpr }
+ - { id: 15, class: gpr }
# CHECK: body:
# CHECK:nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
@@ -209,6 +217,18 @@ body: |
%7(s32) = G_ANYEXT %5
$w0 = COPY %7(s32)
+%8(s32) = COPY $s0
+%9(s32) = G_FCMP floatpred(true), %8, %8
+%12(s8) = G_TRUNC %9(s32)
+%14(s32) = G_ANYEXT %12
+$w0 = COPY %14(s32)
+
+%10(s64) = COPY $d0
+%11(s32) = G_FCMP floatpred(false), %10, %10
+%13(s8) = G_TRUNC %11(s32)
+%15(s32) = G_ANYEXT %13
+$w0 = COPY %15(s32)
+
...
---
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 765c81e26e13c..c4c00f8e97942 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -2870,6 +2870,107 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x
double> %B) {
ret <2 x i64> %tmp4
}
+define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-SD-LABEL: fcmal2xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:shl v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:sshr v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmal4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:mov w8, #1 // =0x1
+; CHECK-GI-NEXT:fmov s0, w8
+; CHECK-GI-NEXT:mov v1.16b, v0.16b
+; CHECK-GI-NEXT:mov v1.h[1], v0.h[0]
+; CHECK-GI-NEXT:mov v0.h[1], v0.h[0]
+; CHECK-GI-NEXT:ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT:ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT:mov v1.d[1], v0.d[0]
+; CHECK-GI-NEXT:shl v0.4s, v1.4s, #31
+; CHECK-GI-NEXT:sshr v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <4 x float> %A, %B
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) {
+; CHECK-SD-LABEL: fcmal2xdouble:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xdouble:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:adrp x8, .LCPI221_0
+; CHECK-GI-NEXT:ldr q0, [x8, :lo12:.LCPI221_0]
+; CHECK-GI-NEXT:shl v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:sshr v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x double> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: fcmnv2xfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:movi v0.2d, #
+; CHECK-NEXT:ret
+ %tmp3 = fcmp false <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i3
[llvm-branch-commits] [llvm] 0a045c9 - [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (#91580)
Author: Marc Auberer
Date: 2024-05-09T12:42:33-07:00
New Revision: 0a045c9d83bb75050ae66fe5db5cbb767fc40202
URL:
https://github.com/llvm/llvm-project/commit/0a045c9d83bb75050ae66fe5db5cbb767fc40202
DIFF:
https://github.com/llvm/llvm-project/commit/0a045c9d83bb75050ae66fe5db5cbb767fc40202.diff
LOG: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection
(#86972) (#91580)
Fixes #86917
`FCMP_TRUE` and `FCMP_FALSE` were previously not considered and we ended up in
an llvm_unreachable assertion.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
llvm/test/CodeGen/AArch64/GlobalISel/select.mir
llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index 92db89cc0915b..80fe4bcb8b58f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -147,6 +147,12 @@ void AArch64GISelUtils::changeFCMPPredToAArch64CC(
case CmpInst::FCMP_UNE:
CondCode = AArch64CC::NE;
break;
+ case CmpInst::FCMP_TRUE:
+CondCode = AArch64CC::AL;
+break;
+ case CmpInst::FCMP_FALSE:
+CondCode = AArch64CC::NV;
+break;
}
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 60cddbf794bc7..ae78d4be0f88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -183,6 +183,14 @@ registers:
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
+ - { id: 8, class: fpr }
+ - { id: 9, class: gpr }
+ - { id: 10, class: fpr }
+ - { id: 11, class: gpr }
+ - { id: 12, class: gpr }
+ - { id: 13, class: gpr }
+ - { id: 14, class: gpr }
+ - { id: 15, class: gpr }
# CHECK: body:
# CHECK:nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
@@ -209,6 +217,18 @@ body: |
%7(s32) = G_ANYEXT %5
$w0 = COPY %7(s32)
+%8(s32) = COPY $s0
+%9(s32) = G_FCMP floatpred(true), %8, %8
+%12(s8) = G_TRUNC %9(s32)
+%14(s32) = G_ANYEXT %12
+$w0 = COPY %14(s32)
+
+%10(s64) = COPY $d0
+%11(s32) = G_FCMP floatpred(false), %10, %10
+%13(s8) = G_TRUNC %11(s32)
+%15(s32) = G_ANYEXT %13
+$w0 = COPY %15(s32)
+
...
---
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index 765c81e26e13c..f398a7f8b8caa 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -2870,6 +2870,95 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x
double> %B) {
ret <2 x i64> %tmp4
}
+define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-SD-LABEL: fcmal2xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:shl v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:sshr v0.2s, v0.2s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) {
+; CHECK-SD-LABEL: fcmal4xfloat:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal4xfloat:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:movi v0.2s, #1
+; CHECK-GI-NEXT:mov v0.d[1], v0.d[0]
+; CHECK-GI-NEXT:shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:sshr v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <4 x float> %A, %B
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) {
+; CHECK-SD-LABEL: fcmal2xdouble:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT:movi v0.2d, #0x
+; CHECK-SD-NEXT:ret
+;
+; CHECK-GI-LABEL: fcmal2xdouble:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT:adrp x8, .LCPI221_0
+; CHECK-GI-NEXT:ldr q0, [x8, :lo12:.LCPI221_0]
+; CHECK-GI-NEXT:shl v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:sshr v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:ret
+ %tmp3 = fcmp true <2 x double> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: fcmnv2xfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT:movi v0.2d, #
+; CHECK-NEXT:ret
+ %tmp3 = fcmp false <2 x float> %A, %B
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmnv4xfloat(<4 x float> %A, <4 x float> %B) {
+;
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/90805
>From d9a7e5179a89624f23d8d6993e7e9ec8887063fc Mon Sep 17 00:00:00 2001
From: Nikita Popov
Date: Thu, 2 May 2024 09:38:09 +0900
Subject: [PATCH] [InterleavedLoadCombine] Bail out on non-byte-sized vector
element type (#90705)
Vectors are always tightly packed, and elements of non-byte-sized
usually do not have a well-defined (byte) offset.
Fixes https://github.com/llvm/llvm-project/issues/90695.
(cherry picked from commit d484c4d3501a7ff3d00a6e0cfad026a3b01d320c)
---
.../CodeGen/InterleavedLoadCombinePass.cpp| 3 +++
.../interleaved-load-combine-pr90695.ll | 19 +++
2 files changed, 22 insertions(+)
create mode 100644
llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index f2d5c3c867c2d..bbb0b654dc67b 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -877,6 +877,9 @@ struct VectorInfo {
if (LI->isAtomic())
return false;
+if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType()))
+ return false;
+
// Get the base polynomial
computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr,
DL);
diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
new file mode 100644
index 0..ee75b3a083f71
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
+; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-windows-gnu"
+
+; Make sure we don't crash on loads of vectors of non-byte-sized types.
+define <4 x i1> @test(ptr %p) {
+; CHECK-LABEL: define <4 x i1> @test(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1
+; CHECK-NEXT:[[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1>
zeroinitializer, <4 x i32>
+; CHECK-NEXT:ret <4 x i1> [[SHUF]]
+;
+entry:
+ %load = load <2 x i1>, ptr %p, align 1
+ %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32>
+ ret <4 x i1> %shuf
+}
___
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[llvm-branch-commits] [llvm] d9a7e51 - [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705)
Author: Nikita Popov
Date: 2024-05-09T12:48:52-07:00
New Revision: d9a7e5179a89624f23d8d6993e7e9ec8887063fc
URL:
https://github.com/llvm/llvm-project/commit/d9a7e5179a89624f23d8d6993e7e9ec8887063fc
DIFF:
https://github.com/llvm/llvm-project/commit/d9a7e5179a89624f23d8d6993e7e9ec8887063fc.diff
LOG: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type
(#90705)
Vectors are always tightly packed, and elements of non-byte-sized
usually do not have a well-defined (byte) offset.
Fixes https://github.com/llvm/llvm-project/issues/90695.
(cherry picked from commit d484c4d3501a7ff3d00a6e0cfad026a3b01d320c)
Added:
llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
Modified:
llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
Removed:
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index f2d5c3c867c2d..bbb0b654dc67b 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -877,6 +877,9 @@ struct VectorInfo {
if (LI->isAtomic())
return false;
+if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType()))
+ return false;
+
// Get the base polynomial
computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr,
DL);
diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
new file mode 100644
index 0..ee75b3a083f71
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
+; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-windows-gnu"
+
+; Make sure we don't crash on loads of vectors of non-byte-sized types.
+define <4 x i1> @test(ptr %p) {
+; CHECK-LABEL: define <4 x i1> @test(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1
+; CHECK-NEXT:[[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1>
zeroinitializer, <4 x i32>
+; CHECK-NEXT:ret <4 x i1> [[SHUF]]
+;
+entry:
+ %load = load <2 x i1>, ptr %p, align 1
+ %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32>
+ ret <4 x i1> %shuf
+}
___
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/90805 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91126)
https://github.com/marcauberer closed https://github.com/llvm/llvm-project/pull/91126 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] 70d452c - Revert "[libc][NFC] adjust time related implementations (#91485)"
Author: Schrodinger ZHU Yifan Date: 2024-05-09T17:09:50-04:00 New Revision: 70d452c501215b583d03207499ebdfd917272beb URL: https://github.com/llvm/llvm-project/commit/70d452c501215b583d03207499ebdfd917272beb DIFF: https://github.com/llvm/llvm-project/commit/70d452c501215b583d03207499ebdfd917272beb.diff LOG: Revert "[libc][NFC] adjust time related implementations (#91485)" This reverts commit 8ac928fea8d561261133e0337a2777fcda99f7ba. Added: libc/src/time/linux/clockGetTimeImpl.h Modified: libc/hdr/CMakeLists.txt libc/hdr/types/CMakeLists.txt libc/src/__support/CMakeLists.txt libc/src/time/clock.h libc/src/time/clock_gettime.h libc/src/time/gettimeofday.h libc/src/time/linux/CMakeLists.txt libc/src/time/linux/clock.cpp libc/src/time/linux/clock_gettime.cpp libc/src/time/linux/gettimeofday.cpp libc/src/time/linux/time.cpp libc/src/time/nanosleep.h libc/src/time/time_func.h Removed: libc/hdr/time_macros.h libc/hdr/types/clock_t.h libc/hdr/types/clockid_t.h libc/hdr/types/struct_timeval.h libc/hdr/types/suseconds_t.h libc/hdr/types/time_t.h libc/src/__support/time/CMakeLists.txt libc/src/__support/time/clock_gettime.h libc/src/__support/time/linux/CMakeLists.txt libc/src/__support/time/linux/clock_gettime.cpp libc/src/__support/time/units.h diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 7549342514304..179b05e6ee966 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -68,13 +68,4 @@ add_proxy_header_library( libc.include.llvm-libc-macros.sys_epoll_macros ) -add_proxy_header_library( - time_macros - HDRS -time_macros.h - FULL_BUILD_DEPENDS -libc.include.time -libc.include.llvm-libc-macros.time_macros -) - add_subdirectory(types) diff --git a/libc/hdr/time_macros.h b/libc/hdr/time_macros.h deleted file mode 100644 index dc36fe66f7a80..0 --- a/libc/hdr/time_macros.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Definition of macros from time.h --===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===--===// - -#ifndef LLVM_LIBC_HDR_TIME_MACROS_H -#define LLVM_LIBC_HDR_TIME_MACROS_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-macros/time-macros.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TIME_MACROS_H diff --git a/libc/hdr/types/CMakeLists.txt b/libc/hdr/types/CMakeLists.txt index 3a1bb2f3c340f..46a66ec590202 100644 --- a/libc/hdr/types/CMakeLists.txt +++ b/libc/hdr/types/CMakeLists.txt @@ -63,48 +63,3 @@ add_proxy_header_library( libc.include.llvm-libc-types.fexcept_t libc.include.fenv ) - -add_proxy_header_library( - time_t - HDRS -time_t.h - FULL_BUILD_DEPENDS -libc.include.llvm-libc-types.time_t -libc.include.time -) - -add_proxy_header_library( - clockid_t - HDRS -clockid_t.h - FULL_BUILD_DEPENDS -libc.include.llvm-libc-types.clockid_t -libc.include.sys_types -) - -add_proxy_header_library( - clock_t - HDRS -clock_t.h - FULL_BUILD_DEPENDS -libc.include.llvm-libc-types.clock_t -libc.include.time -) - -add_proxy_header_library( - suseconds_t - HDRS -suseconds_t.h - FULL_BUILD_DEPENDS -libc.include.llvm-libc-types.suseconds_t -libc.include.sys_time -) - -add_proxy_header_library( - struct_timeval - HDRS -struct_timeval.h - FULL_BUILD_DEPENDS -libc.include.llvm-libc-types.struct_timeval -libc.include.sys_time -) diff --git a/libc/hdr/types/clock_t.h b/libc/hdr/types/clock_t.h deleted file mode 100644 index b0b658e96c3db..0 --- a/libc/hdr/types/clock_t.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Proxy for clock_t -===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===--===// - -#ifndef LLVM_LIBC_HDR_TYPES_CLOCK_T_H -#define LLVM_LIBC_HDR_TYPES_CLOCK_T_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-types/clock_t.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TYPES_CLOCK_T_H diff --git a/libc/hdr/types/clockid_t.h b/libc/hdr/types/clockid_t.h deleted file mode 100644 index 42072a2ff..0 --- a/libc/hdr/types/clockid_t.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Proxy for clockid_t ---===// -// -// Part of the LLVM Pr
[llvm-branch-commits] [BOLT][NFC] Simplify analyzeIndirectBranch (PR #91662)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/91662 Simplify mutually exclusive sanity checks in analyzeIndirectBranch, where an UNKNOWN IndirectBranchType is to be returned. Reduces confusion and code duplication when adding a new IndirectBranchType (to be added in a follow-up diff). Test Plan: NFC ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][NFC] Simplify analyzeIndirectBranch (PR #91662)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
Simplify mutually exclusive sanity checks in analyzeIndirectBranch,
where an UNKNOWN IndirectBranchType is to be returned. Reduces confusion
and code duplication when adding a new IndirectBranchType (to be added
in a follow-up diff).
Test Plan: NFC
---
Full diff: https://github.com/llvm/llvm-project/pull/91662.diff
1 Files Affected:
- (modified) bolt/lib/Target/X86/X86MCPlusBuilder.cpp (+9-7)
``diff
diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
index e7cabdabce90..86e7d4dfaed8 100644
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -2115,13 +2115,15 @@ class X86MCPlusBuilder : public MCPlusBuilder {
return IndirectBranchType::POSSIBLE_FIXED_BRANCH;
}
-if (Type == IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE &&
-(MO->ScaleImm != 1 || MO->BaseRegNum != RIPRegister))
- return IndirectBranchType::UNKNOWN;
-
-if (Type != IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE &&
-MO->ScaleImm != PtrSize)
- return IndirectBranchType::UNKNOWN;
+switch (Type) {
+case IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE:
+ if (MO->ScaleImm != 1 || MO->BaseRegNum != RIPRegister)
+return IndirectBranchType::UNKNOWN;
+ break;
+default:
+ if (MO->ScaleImm != PtrSize)
+return IndirectBranchType::UNKNOWN;
+}
MemLocInstrOut = MemLocInstr;
``
https://github.com/llvm/llvm-project/pull/91662
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[llvm-branch-commits] [BOLT][NFC] Define getExprValue helper (PR #91663)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/91663 Move out common code extracting the address of a MCExpr. To be reused in a follow-up diff. Test Plan: NFC ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][NFC] Define getExprValue helper (PR #91663)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
Move out common code extracting the address of a MCExpr. To be reused in
a follow-up diff.
Test Plan: NFC
---
Full diff: https://github.com/llvm/llvm-project/pull/91663.diff
1 Files Affected:
- (modified) bolt/lib/Core/BinaryFunction.cpp (+10-6)
``diff
diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
index de34421ebeb08..11103f7bdce8b 100644
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -851,15 +851,19 @@ BinaryFunction::processIndirectBranch(MCInst
&Instruction, unsigned Size,
return IndirectBranchType::UNKNOWN;
}
- // RIP-relative addressing should be converted to symbol form by now
- // in processed instructions (but not in jump).
- if (DispExpr) {
+ auto getExprValue = [&](const MCExpr *Expr) {
const MCSymbol *TargetSym;
uint64_t TargetOffset;
-std::tie(TargetSym, TargetOffset) = BC.MIB->getTargetSymbolInfo(DispExpr);
+std::tie(TargetSym, TargetOffset) = BC.MIB->getTargetSymbolInfo(Expr);
ErrorOr SymValueOrError = BC.getSymbolValue(*TargetSym);
-assert(SymValueOrError && "global symbol needs a value");
-ArrayStart = *SymValueOrError + TargetOffset;
+assert(SymValueOrError && "Global symbol needs a value");
+return *SymValueOrError + TargetOffset;
+ };
+
+ // RIP-relative addressing should be converted to symbol form by now
+ // in processed instructions (but not in jump).
+ if (DispExpr) {
+ArrayStart = getExprValue(DispExpr);
BaseRegNum = BC.MIB->getNoRegister();
if (BC.isAArch64()) {
ArrayStart &= ~0xFFFULL;
``
https://github.com/llvm/llvm-project/pull/91663
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[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)
aemerson wrote: > @aemerson Did you submit a new pull request with a fix? I have not yet, will do so now... https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][NFCI] Fix return type of BC::getSignedValueAtAddress (PR #91664)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/91664 getSignedValueAtAddress calls DataExtractor::getSigned which naturally returns a signed value. Test Plan: NFCI ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][NFCI] Fix return type of BC::getSignedValueAtAddress (PR #91664)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
getSignedValueAtAddress calls DataExtractor::getSigned which naturally
returns a signed value.
Test Plan: NFCI
---
Full diff: https://github.com/llvm/llvm-project/pull/91664.diff
3 Files Affected:
- (modified) bolt/include/bolt/Core/BinaryContext.h (+1-2)
- (modified) bolt/lib/Core/BinaryContext.cpp (+1-1)
- (modified) bolt/lib/Rewrite/LinuxKernelRewriter.cpp (+1-1)
``diff
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 75765819ac464..4a59a581dfedb 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -1217,8 +1217,7 @@ class BinaryContext {
/// Return a signed value of \p Size stored at \p Address. The address has
/// to be a valid statically allocated address for the binary.
- ErrorOr getSignedValueAtAddress(uint64_t Address,
-size_t Size) const;
+ ErrorOr getSignedValueAtAddress(uint64_t Address, size_t Size)
const;
/// Special case of getUnsignedValueAtAddress() that uses a pointer size.
ErrorOr getPointerAtAddress(uint64_t Address) const {
diff --git a/bolt/lib/Core/BinaryContext.cpp b/bolt/lib/Core/BinaryContext.cpp
index ad2eb18caf109..507b203ea9d8b 100644
--- a/bolt/lib/Core/BinaryContext.cpp
+++ b/bolt/lib/Core/BinaryContext.cpp
@@ -2212,7 +2212,7 @@ ErrorOr
BinaryContext::getUnsignedValueAtAddress(uint64_t Address,
return DE.getUnsigned(&ValueOffset, Size);
}
-ErrorOr BinaryContext::getSignedValueAtAddress(uint64_t Address,
+ErrorOr BinaryContext::getSignedValueAtAddress(uint64_t Address,
size_t Size) const {
const ErrorOr Section = getSectionForAddress(Address);
if (!Section)
diff --git a/bolt/lib/Rewrite/LinuxKernelRewriter.cpp
b/bolt/lib/Rewrite/LinuxKernelRewriter.cpp
index 99775ccfe38d3..b2c8b2446f7e1 100644
--- a/bolt/lib/Rewrite/LinuxKernelRewriter.cpp
+++ b/bolt/lib/Rewrite/LinuxKernelRewriter.cpp
@@ -393,7 +393,7 @@ void LinuxKernelRewriter::processLKKSymtab(bool IsGPL) {
for (uint64_t I = 0; I < SectionSize; I += 4) {
const uint64_t EntryAddress = SectionAddress + I;
-ErrorOr Offset = BC.getSignedValueAtAddress(EntryAddress, 4);
+ErrorOr Offset = BC.getSignedValueAtAddress(EntryAddress, 4);
assert(Offset && "Reading valid PC-relative offset for a ksymtab entry");
const int32_t SignedOffset = *Offset;
const uint64_t RefAddress = EntryAddress + SignedOffset;
``
https://github.com/llvm/llvm-project/pull/91664
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[llvm-branch-commits] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/91666 Dead jump tables such as those arising from FIXED_PIC_BRANCH optimization don't need to be updated or moved. Further, if any jump table entry points to a block removed by unreachable code elimination, we would be unable to update it and jump table emission would fail. Identify non-referenced jump tables and delete them to prevent that. Test Plan: NFC for existing tests. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Eliminate dead jump tables (PR #91666)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
Dead jump tables such as those arising from FIXED_PIC_BRANCH
optimization don't need to be updated or moved. Further, if any jump
table entry points to a block removed by unreachable code elimination,
we would be unable to update it and jump table emission would fail.
Identify non-referenced jump tables and delete them to prevent that.
Test Plan: NFC for existing tests.
---
Full diff: https://github.com/llvm/llvm-project/pull/91666.diff
1 Files Affected:
- (modified) bolt/lib/Core/BinaryFunction.cpp (+20)
``diff
diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
index 11103f7bdce8..f74ecea8ac0a 100644
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -1697,6 +1697,26 @@ void BinaryFunction::postProcessEntryPoints() {
}
void BinaryFunction::postProcessJumpTables() {
+ // Set of JTs accessed from this function.
+ std::unordered_set LiveJTs;
+ for (auto &JTSite : JTSites)
+LiveJTs.emplace(JTSite.second);
+
+ // Remove dead jump tables (reference removed as a result of
+ // POSSIBLE_PIC_FIXED_BRANCH optimization).
+ for (auto JTI = JumpTables.begin(), JTE = JumpTables.end(); JTI != JTE; ) {
+const uint64_t Address = JTI->first;
+JumpTable *JT = JTI->second;
+bool HasOneParent = JT->Parents.size() == 1;
+if (LiveJTs.count(Address) == 0 && HasOneParent) {
+ BC.deregisterJumpTable(Address);
+ delete JT;
+ JTI = JumpTables.erase(JTI);
+ continue;
+}
+++JTI;
+ }
+
// Create labels for all entries.
for (auto &JTI : JumpTables) {
JumpTable &JT = *JTI.second;
``
https://github.com/llvm/llvm-project/pull/91666
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[llvm-branch-commits] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/91667 Detect and support fixed PIC indirect jumps of the following form: ``` movslq En(%rip), %r1 leaq PIC_JUMP_TABLE(%rip), %r2 addq %r2, %r1 jmpq *%r1 ``` with PIC_JUMP_TABLE that looks like following: ``` JT: -- E1:| L1 - JT | |--| E2:| L2 - JT | |--| | | .. En:| Ln - JT | -- ``` The code could be produced by compilers, see https://github.com/llvm/llvm-project/issues/91648. Test Plan: updated jump-table-fixed-ref-pic.test ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
Detect and support fixed PIC indirect jumps of the following form:
```
movslq En(%rip), %r1
leaq PIC_JUMP_TABLE(%rip), %r2
addq %r2, %r1
jmpq *%r1
```
with PIC_JUMP_TABLE that looks like following:
```
JT: --
E1:| L1 - JT |
|--|
E2:| L2 - JT |
|--|
| |
..
En:| Ln - JT |
--
```
The code could be produced by compilers, see
https://github.com/llvm/llvm-project/issues/91648.
Test Plan: updated jump-table-fixed-ref-pic.test
---
Full diff: https://github.com/llvm/llvm-project/pull/91667.diff
8 Files Affected:
- (modified) bolt/include/bolt/Core/BinaryContext.h (+5)
- (modified) bolt/include/bolt/Core/MCPlusBuilder.h (+4-1)
- (modified) bolt/lib/Core/BinaryFunction.cpp (+45-2)
- (modified) bolt/lib/Passes/IndirectCallPromotion.cpp (+2-1)
- (modified) bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp (+9-5)
- (modified) bolt/lib/Target/X86/X86MCPlusBuilder.cpp (+60-28)
- (modified) bolt/test/X86/Inputs/jump-table-fixed-ref-pic.s (+1-1)
- (modified) bolt/test/X86/jump-table-fixed-ref-pic.test (+11-4)
``diff
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 4a59a581dfedb..f8bf29c674b54 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -430,6 +430,11 @@ class BinaryContext {
return nullptr;
}
+ /// Deregister JumpTable registered at a given \p Address.
+ bool deregisterJumpTable(uint64_t Address) {
+return JumpTables.erase(Address);
+ }
+
unsigned getDWARFEncodingSize(unsigned Encoding) {
if (Encoding == dwarf::DW_EH_PE_omit)
return 0;
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h
b/bolt/include/bolt/Core/MCPlusBuilder.h
index f7614cf9ac977..42ec006fba9f1 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -58,6 +58,8 @@ enum class IndirectBranchType : char {
POSSIBLE_PIC_JUMP_TABLE, /// Possibly a jump table for PIC.
POSSIBLE_GOTO, /// Possibly a gcc's computed goto.
POSSIBLE_FIXED_BRANCH, /// Possibly an indirect branch to a fixed location.
+ POSSIBLE_PIC_FIXED_BRANCH, /// Possibly an indirect jump to a fixed entry in
a
+ /// PIC jump table.
};
class MCPlusBuilder {
@@ -1472,7 +1474,8 @@ class MCPlusBuilder {
InstructionIterator End, const unsigned PtrSize,
MCInst *&MemLocInstr, unsigned &BaseRegNum,
unsigned &IndexRegNum, int64_t &DispValue,
-const MCExpr *&DispExpr, MCInst *&PCRelBaseOut) const {
+const MCExpr *&DispExpr, MCInst *&PCRelBaseOut,
+MCInst *&FixedEntryLoadInst) const {
llvm_unreachable("not implemented");
return IndirectBranchType::UNKNOWN;
}
diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
index f74ecea8ac0a1..799065a6f194e 100644
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -779,6 +779,9 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction,
unsigned Size,
// setting the value of the register used by the branch.
MCInst *MemLocInstr;
+ // The instruction loading the fixed PIC jump table entry value.
+ MCInst *FixedEntryLoadInstr;
+
// Address of the table referenced by MemLocInstr. Could be either an
// array of function pointers, or a jump table.
uint64_t ArrayStart = 0;
@@ -810,7 +813,7 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction,
unsigned Size,
IndirectBranchType BranchType = BC.MIB->analyzeIndirectBranch(
Instruction, Begin, Instructions.end(), PtrSize, MemLocInstr, BaseRegNum,
- IndexRegNum, DispValue, DispExpr, PCRelBaseInstr);
+ IndexRegNum, DispValue, DispExpr, PCRelBaseInstr, FixedEntryLoadInstr);
if (BranchType == IndirectBranchType::UNKNOWN && !MemLocInstr)
return BranchType;
@@ -876,6 +879,43 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction,
unsigned Size,
if (BaseRegNum == BC.MRI->getProgramCounter())
ArrayStart += getAddress() + Offset + Size;
+ if (FixedEntryLoadInstr) {
+assert(BranchType == IndirectBranchType::POSSIBLE_PIC_FIXED_BRANCH &&
+ "Invalid IndirectBranch type");
+const MCExpr *FixedEntryDispExpr =
+BC.MIB->getMemOperandDisp(*FixedEntryLoadInstr)->getExpr();
+const uint64_t EntryAddress = getExprValue(FixedEntryDispExpr);
+uint64_t EntrySize = BC.getJumpTableEntrySize(JumpTable::JTT_PIC);
+ErrorOr Value = BC.getSignedValueAtAddress(EntryAddress,
EntrySize);
+if (!Value)
+ return IndirectBranchType::UNKNOWN;
+
+BC.outs() << "BOLT-INFO: fixed PIC indirect branch detected in " << *this
+ << " at 0x" << Twine::utohexstr(getAddress() + Offset)
+
[llvm-branch-commits] [BOLT][NFC] Simplify analyzeIndirectBranch (PR #91662)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/91662 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][NFC] Define getExprValue helper (PR #91663)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/91663 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)
https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)
https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols (PR #91632)
MaskRay wrote: LGTM https://github.com/llvm/llvm-project/pull/91632 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)
https://github.com/aemerson ready_for_review https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)
https://github.com/aemerson closed https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)
aemerson wrote: New PR: https://github.com/llvm/llvm-project/pull/91672 https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Amara Emerson (aemerson)
Changes
Backport
https://github.com/llvm/llvm-project/commit/a01e9ce86f4c1bc9af819902db9f287b6d23f54f
- **[AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT**
---
Full diff: https://github.com/llvm/llvm-project/pull/91672.diff
2 Files Affected:
- (modified) llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (+1)
- (modified)
llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir (+68-1)
``diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 4b9d549e79114..de3c89e925a2a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -877,6 +877,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const
AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
+ .moreElementsToNextPow2(0)
.widenVectorEltsToVectorMinSize(0, 64);
getActionDefinitionsBuilder(G_BUILD_VECTOR)
diff --git
a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
index 6f6cf2cc165b9..563d3d3e26edf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o -
-global-isel-abort=1 | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o -
-global-isel-abort=2 | FileCheck %s
---
name:pr63826_v2s16
body: |
@@ -216,3 +216,70 @@ body: |
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR
...
+---
+name:v3s8_crash
+body: |
+ ; CHECK-LABEL: name: v3s8_crash
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x8000)
+ ; CHECK-NEXT: liveins: $w1, $w2, $w3, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR
[[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3
x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s8>) = G_BUILD_VECTOR
[[C1]](s8), [[DEF]](s8), [[DEF]](s8)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x8000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s8>) = G_INSERT_VECTOR_ELT
[[TRUNC]], [[C3]](s8), [[C2]](s64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<12 x s8>) = G_SHUFFLE_VECTOR [[IVEC]](<3
x s8>), [[BUILD_VECTOR1]], shufflemask(0, 3, 3, 3, 1, 3, 3, 3, 2, 3, 3, 3)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[SHUF]](<12 x
s8>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32),
[[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<3 x s32>)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR
[[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[DEF1]](s32)
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP
[[BUILD_VECTOR2]](<4 x s32>)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32),
[[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UITOFP]](<4
x s32>)
+ ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR
[[UV3]](s32), [[UV4]](s32), [[UV5]](s32)
+ ; CHECK-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32),
[[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)
+ ; CHECK-NEXT: G_STORE [[UV7]](s32), [[COPY]](p0) :: (store (s32), align 16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; CHECK-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD]](p0) :: (store (s32) into
unknown-address + 4)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
+ ; CHECK-NEXT: G_STORE [[UV9]](s32), [[PTR_ADD1]](p0) :: (store (s32) into
unknown-address + 8, align 8)
+ ; CHECK-NEXT: G_BR %bb.1
+ bb.1:
+liveins: $w1, $w2, $w3, $x0
+
+%0:_(p0)
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)
aemerson wrote: Test has been changed from original commit due to a fallback in a G_BITCAST. Added abort=2 so we can see partial legalization and check no crash. https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)
https://github.com/aemerson milestoned https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/91678
Backport f6f474c4ef9694a4ca8f08d59fd112c250fb9c73
dfe4ca9b7f4a422500d78280dc5eefd1979939e6
Requested by: @ilovepi
>From fe4854d3b2e49c816aaf37a7f3421bde55215ba1 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 20 Mar 2024 13:39:39 -0700
Subject: [PATCH 1/2] [llvm][lld] Pre-commit tests for RISCV TLSDESC symbols
Currently, we mistakenly mark the local labels used in RISC-V TLSDESC as
TLS symbols, when they should not be. This patch adds tests with the
current incorrect behavior, and subsequent patches will address the
issue.
Reviewers: MaskRay, topperc
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/85816
(cherry picked from commit f6f474c4ef9694a4ca8f08d59fd112c250fb9c73)
---
lld/test/ELF/riscv-tlsdesc.s | 25 +++
llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll | 24 ++
2 files changed, 49 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index 1738f86256caa..c583e15cf30ce 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,6 +29,12 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
+# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
+# RUN: not ld.lld -shared -soname=d.64.so -o d.64.so d.64.o 2>&1 | FileCheck
%s --check-prefix=BADTLSLABEL
+
+# RUN: llvm-mc -triple=riscv32 -filetype=obj d.s -o d.32.o --defsym ELF32=1
+# RUN: not ld.lld -shared -soname=d.32.so -o d.32.so d.32.o 2>&1 | FileCheck
%s --check-prefix=BADTLSLABEL
+
# GD64-RELA: .rela.dyn {
# GD64-RELA-NEXT: 0x2408 R_RISCV_TLSDESC - 0x7FF
# GD64-RELA-NEXT: 0x23E8 R_RISCV_TLSDESC a 0x0
@@ -150,6 +156,9 @@
# IE32-NEXT: lw a0, 0x80(a0)
# IE32-NEXT: add a0, a0, tp
+## FIXME This should not pass, but the code MC layer needs a fix to prevent
this.
+# BADTLSLABEL: error: d.{{.*}}.o has an STT_TLS symbol but doesn't have an
SHF_TLS section
+
#--- a.s
.macro load dst, src
.ifdef ELF32
@@ -192,3 +201,19 @@ b:
.tbss
.globl c
c: .zero 4
+
+#--- d.s
+.macro load dst, src
+.ifdef ELF32
+lw \dst, \src
+.else
+ld \dst, \src
+.endif
+.endm
+
+.Ltlsdesc_hi0:
+ auipca0, %tlsdesc_hi(foo)
+ load a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0)
+ addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0)
+ jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0)
+ add a1, a0, tp
diff --git a/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
b/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
new file mode 100644
index 0..23ba2ffb1ad76
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll
@@ -0,0 +1,24 @@
+;; The test in this file do not appear in tls-models.ll because
+;; they are not auto-generated.
+; RUN: llc -mtriple=riscv64 -relocation-model=pic -enable-tlsdesc < %s \
+; RUN: | llvm-mc -triple=riscv64 -filetype=obj -o - \
+; RUN: | llvm-readelf --symbols - \
+; RUN: | FileCheck %s
+
+; RUN: llc -mtriple=riscv32 -relocation-model=pic -enable-tlsdesc < %s \
+; RUN: | llvm-mc -triple=riscv32 -filetype=obj -o - \
+; RUN: | llvm-readelf --symbols - \
+; RUN: | FileCheck %s
+
+; Check that TLS symbols are lowered correctly based on the specified
+; model. Make sure they're external to avoid them all being optimised to Local
+; Exec for the executable.
+
+@unspecified = external thread_local global i32
+
+define ptr @f1() nounwind {
+entry:
+ ret ptr @unspecified
+ ; CHECK: Symbol table '.symtab' contains 7 entries:
+ ; CHECK: TLS {{.*}} unspecified
+}
>From f7b87341e88e26fa90acd36dac0f139ca46961bb Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:27:41 -0700
Subject: [PATCH 2/2] [RISCV][lld] Set the type of TLSDESC relocation's
referenced local symbol to STT_NOTYPE
When adding fixups for RISCV_TLSDESC_ADD_LO and RISCV_TLSDESC_LOAD_LO,
the local label added for RISCV TLSDESC relocations have STT_TLS set,
which is incorrect. Instead, these labels should have `STT_NOTYPE`.
This patch stops adding such fixups and avoid setting the STT_TLS on
these symbols. Failing to do so can cause LLD to emit an error `has an
STT_TLS symbol but doesn't have an SHF_TLS section`. We additionally,
adjust how LLD services these relocations to avoid errors with
incompatible relocation and symbol types.
Reviewers: topperc, MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/85817
(cherry picked from commit dfe4ca9b7f4a422500d78280dc5eefd1979939e6)
---
lld/ELF/Relocations.cpp | 5 +++-
lld/test/ELF/riscv-tlsdesc-relax.s| 8 ++
lld/test/ELF/riscv-tlsdesc.s | 27 +++
.../Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 2 --
4 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/ll
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/91678 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
llvmbot wrote: @MaskRay @ilovepi What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/91678 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
llvmbot wrote:
@llvm/pr-subscribers-lld-elf
Author: None (llvmbot)
Changes
Backport f6f474c4ef9694a4ca8f08d59fd112c250fb9c73
dfe4ca9b7f4a422500d78280dc5eefd1979939e6
Requested by: @ilovepi
---
Full diff: https://github.com/llvm/llvm-project/pull/91678.diff
5 Files Affected:
- (modified) lld/ELF/Relocations.cpp (+4-1)
- (modified) lld/test/ELF/riscv-tlsdesc-relax.s (+8)
- (modified) lld/test/ELF/riscv-tlsdesc.s (+35-5)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp (-2)
- (added) llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll (+24)
``diff
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 619fbaf5dc545..92a1b9baaca3d 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1480,7 +1480,10 @@ template void
RelocationScanner::scanOne(RelTy *&i) {
// Process TLS relocations, including TLS optimizations. Note that
// R_TPREL and R_TPREL_NEG relocations are resolved in processAux.
- if (sym.isTls()) {
+ //
+ // Some RISCV TLSDESC relocations reference a local NOTYPE symbol,
+ // but we need to process them in handleTlsRelocation.
+ if (sym.isTls() || oneof(expr)) {
if (unsigned processed =
handleTlsRelocation(type, sym, *sec, offset, addend, expr)) {
i += processed - 1;
diff --git a/lld/test/ELF/riscv-tlsdesc-relax.s
b/lld/test/ELF/riscv-tlsdesc-relax.s
index fb24317e6535c..5718d4175be11 100644
--- a/lld/test/ELF/riscv-tlsdesc-relax.s
+++ b/lld/test/ELF/riscv-tlsdesc-relax.s
@@ -33,12 +33,14 @@
# GD64-NEXT: c.add a0, tp
# GD64-NEXT: jal {{.*}}
## &.got[c]-. = 0x20c0+8 - 0x1020 = 0x10a8
+# GD64-LABEL: <.Ltlsdesc_hi1>:
# GD64-NEXT: 1020: auipc a4, 0x1
# GD64-NEXT: ld a5, 0xa8(a4)
# GD64-NEXT: addia0, a4, 0xa8
# GD64-NEXT: jalrt0, 0x0(a5)
# GD64-NEXT: c.add a0, tp
## &.got[c]-. = 0x20c0+8 - 0x1032 = 0x1096
+# GD64-LABEL: <.Ltlsdesc_hi2>:
# GD64-NEXT: 1032: auipc a6, 0x1
# GD64-NEXT: ld a7, 0x96(a6)
# GD64-NEXT: addia0, a6, 0x96
@@ -64,6 +66,7 @@
# LE64-NEXT: jal {{.*}}
# LE64-NEXT: R_RISCV_JAL foo
# LE64-NEXT: R_RISCV_RELAX *ABS*
+# LE64-LABEL: <.Ltlsdesc_hi1>:
# LE64-NEXT: addia0, zero, 0x7ff
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: R_RISCV_RELAX *ABS*
@@ -71,6 +74,7 @@
# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi1
# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi1
# LE64-NEXT: c.add a0, tp
+# LE64-LABEL: <.Ltlsdesc_hi2>:
# LE64-NEXT: addizero, zero, 0x0
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: addizero, zero, 0x0
@@ -93,9 +97,11 @@
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
# LE64A-NEXT: jal {{.*}}
+# LE64A-LABEL: <.Ltlsdesc_hi1>:
# LE64A-NEXT: lui a0, 0x2
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
+# LE64A-LABEL: <.Ltlsdesc_hi2>:
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: lui a0, 0x2
@@ -115,10 +121,12 @@
# IE64-NEXT: c.add a0, tp
# IE64-NEXT: jal {{.*}}
## &.got[c]-. = 0x120e0+8 - 0x11018 = 0x10d0
+# IE64-LABEL: <.Ltlsdesc_hi1>:
# IE64-NEXT: 11018: auipc a0, 0x1
# IE64-NEXT: ld a0, 0xd0(a0)
# IE64-NEXT: c.add a0, tp
## &.got[c]-. = 0x120e0+8 - 0x1102a = 0x10be
+# IE64-LABEL: <.Ltlsdesc_hi2>:
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: 1102a: auipc a0, 0x1
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index 1738f86256caa..935ecbddfbfff 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,6 +29,14 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
+## Prior to https://github.com/llvm/llvm-project/pull/85817 the local TLSDESC
+## labels would be marked STT_TLS, resulting in an error "has an STT_TLS
symbol but doesn't have an SHF_TLS section"
+
+# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
+# RUN: ld.lld -shared -soname=d.64.so -o d.64.so d.64.o --fatal-warnings
+# RUN: llvm-mc -triple=riscv32 -filetype=obj d.s -o d.32.o --defsym ELF32=1
+# RUN: ld.lld -shared -soname=d.32.so -o d.32.so d.32.o --fatal-warnings
+
# GD64-RELA: .rela.dyn {
# GD64-RELA-NEXT: 0x2408 R_RISCV_TLSDESC - 0x7FF
# GD64-RELA-NEXT: 0x23E8 R_RISCV_TLSDESC a 0x0
@@ -68,14 +76,14 @@
# GD64-NEXT: add a0, a0, tp
## &.got[b]-. = 0x23e0+40 - 0x12f4 = 0x1114
-# GD64-NEXT: 12f4: auipc a2, 0x1
+# GD64:12f4: auipc a2, 0x1
# GD64-NEXT: ld a3, 0x114(a2)
# GD64-NEXT: addia0, a2, 0x114
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: None (llvmbot)
Changes
Backport f6f474c4ef9694a4ca8f08d59fd112c250fb9c73
dfe4ca9b7f4a422500d78280dc5eefd1979939e6
Requested by: @ilovepi
---
Full diff: https://github.com/llvm/llvm-project/pull/91678.diff
5 Files Affected:
- (modified) lld/ELF/Relocations.cpp (+4-1)
- (modified) lld/test/ELF/riscv-tlsdesc-relax.s (+8)
- (modified) lld/test/ELF/riscv-tlsdesc.s (+35-5)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp (-2)
- (added) llvm/test/CodeGen/RISCV/tlsdesc-symbol.ll (+24)
``diff
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 619fbaf5dc545..92a1b9baaca3d 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1480,7 +1480,10 @@ template void
RelocationScanner::scanOne(RelTy *&i) {
// Process TLS relocations, including TLS optimizations. Note that
// R_TPREL and R_TPREL_NEG relocations are resolved in processAux.
- if (sym.isTls()) {
+ //
+ // Some RISCV TLSDESC relocations reference a local NOTYPE symbol,
+ // but we need to process them in handleTlsRelocation.
+ if (sym.isTls() || oneof(expr)) {
if (unsigned processed =
handleTlsRelocation(type, sym, *sec, offset, addend, expr)) {
i += processed - 1;
diff --git a/lld/test/ELF/riscv-tlsdesc-relax.s
b/lld/test/ELF/riscv-tlsdesc-relax.s
index fb24317e6535c..5718d4175be11 100644
--- a/lld/test/ELF/riscv-tlsdesc-relax.s
+++ b/lld/test/ELF/riscv-tlsdesc-relax.s
@@ -33,12 +33,14 @@
# GD64-NEXT: c.add a0, tp
# GD64-NEXT: jal {{.*}}
## &.got[c]-. = 0x20c0+8 - 0x1020 = 0x10a8
+# GD64-LABEL: <.Ltlsdesc_hi1>:
# GD64-NEXT: 1020: auipc a4, 0x1
# GD64-NEXT: ld a5, 0xa8(a4)
# GD64-NEXT: addia0, a4, 0xa8
# GD64-NEXT: jalrt0, 0x0(a5)
# GD64-NEXT: c.add a0, tp
## &.got[c]-. = 0x20c0+8 - 0x1032 = 0x1096
+# GD64-LABEL: <.Ltlsdesc_hi2>:
# GD64-NEXT: 1032: auipc a6, 0x1
# GD64-NEXT: ld a7, 0x96(a6)
# GD64-NEXT: addia0, a6, 0x96
@@ -64,6 +66,7 @@
# LE64-NEXT: jal {{.*}}
# LE64-NEXT: R_RISCV_JAL foo
# LE64-NEXT: R_RISCV_RELAX *ABS*
+# LE64-LABEL: <.Ltlsdesc_hi1>:
# LE64-NEXT: addia0, zero, 0x7ff
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: R_RISCV_RELAX *ABS*
@@ -71,6 +74,7 @@
# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi1
# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi1
# LE64-NEXT: c.add a0, tp
+# LE64-LABEL: <.Ltlsdesc_hi2>:
# LE64-NEXT: addizero, zero, 0x0
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: addizero, zero, 0x0
@@ -93,9 +97,11 @@
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
# LE64A-NEXT: jal {{.*}}
+# LE64A-LABEL: <.Ltlsdesc_hi1>:
# LE64A-NEXT: lui a0, 0x2
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
+# LE64A-LABEL: <.Ltlsdesc_hi2>:
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: lui a0, 0x2
@@ -115,10 +121,12 @@
# IE64-NEXT: c.add a0, tp
# IE64-NEXT: jal {{.*}}
## &.got[c]-. = 0x120e0+8 - 0x11018 = 0x10d0
+# IE64-LABEL: <.Ltlsdesc_hi1>:
# IE64-NEXT: 11018: auipc a0, 0x1
# IE64-NEXT: ld a0, 0xd0(a0)
# IE64-NEXT: c.add a0, tp
## &.got[c]-. = 0x120e0+8 - 0x1102a = 0x10be
+# IE64-LABEL: <.Ltlsdesc_hi2>:
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: 1102a: auipc a0, 0x1
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index 1738f86256caa..935ecbddfbfff 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,6 +29,14 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
+## Prior to https://github.com/llvm/llvm-project/pull/85817 the local TLSDESC
+## labels would be marked STT_TLS, resulting in an error "has an STT_TLS
symbol but doesn't have an SHF_TLS section"
+
+# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
+# RUN: ld.lld -shared -soname=d.64.so -o d.64.so d.64.o --fatal-warnings
+# RUN: llvm-mc -triple=riscv32 -filetype=obj d.s -o d.32.o --defsym ELF32=1
+# RUN: ld.lld -shared -soname=d.32.so -o d.32.so d.32.o --fatal-warnings
+
# GD64-RELA: .rela.dyn {
# GD64-RELA-NEXT: 0x2408 R_RISCV_TLSDESC - 0x7FF
# GD64-RELA-NEXT: 0x23E8 R_RISCV_TLSDESC a 0x0
@@ -68,14 +76,14 @@
# GD64-NEXT: add a0, a0, tp
## &.got[b]-. = 0x23e0+40 - 0x12f4 = 0x1114
-# GD64-NEXT: 12f4: auipc a2, 0x1
+# GD64:12f4: auipc a2, 0x1
# GD64-NEXT: ld a3, 0x114(a2)
# GD64-NEXT: addia0, a2
[llvm-branch-commits] [llvm] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91666
>From 0166eb8ee85e2cdcb472502206ea4c13f49a6724 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 16:31:17 -0700
Subject: [PATCH] deregisterJumpTable
Created using spr 1.3.4
---
bolt/include/bolt/Core/BinaryContext.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 4a59a581dfedb..f8bf29c674b54 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -430,6 +430,11 @@ class BinaryContext {
return nullptr;
}
+ /// Deregister JumpTable registered at a given \p Address.
+ bool deregisterJumpTable(uint64_t Address) {
+return JumpTables.erase(Address);
+ }
+
unsigned getDWARFEncodingSize(unsigned Encoding) {
if (Encoding == dwarf::DW_EH_PE_omit)
return 0;
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/91667 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/91667 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT][NFCI] Fix return type of BC::getSignedValueAtAddress (PR #91664)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91664
>From 8d97606325c0620edb2e7a169442e370a569be74 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 16:35:22 -0700
Subject: [PATCH] clang-format
Created using spr 1.3.4
---
bolt/lib/Core/BinaryContext.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bolt/lib/Core/BinaryContext.cpp b/bolt/lib/Core/BinaryContext.cpp
index 507b203ea9d8b..0a0c827c3a962 100644
--- a/bolt/lib/Core/BinaryContext.cpp
+++ b/bolt/lib/Core/BinaryContext.cpp
@@ -2213,7 +2213,7 @@ ErrorOr
BinaryContext::getUnsignedValueAtAddress(uint64_t Address,
}
ErrorOr BinaryContext::getSignedValueAtAddress(uint64_t Address,
- size_t Size) const {
+size_t Size) const {
const ErrorOr Section = getSectionForAddress(Address);
if (!Section)
return std::make_error_code(std::errc::bad_address);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91419
>From d3ff5d5bf1d6ec8530ea478951d7b9193792ad8a Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Wed, 8 May 2024 10:04:09 +0800
Subject: [PATCH] [InstSimplify] Do not simplify freeze in
`simplifyWithOpReplaced` (#91215)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
Revert "[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced`
(#91215)"
This reverts commit 1c2eb18d52976fef89972e89c52d2ec5ed7e4868.
[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
---
llvm/lib/Analysis/InstructionSimplify.cpp | 4 +++
llvm/test/Transforms/InstCombine/icmp.ll | 15 ++
llvm/test/Transforms/InstCombine/select.ll | 32 ++
llvm/test/Transforms/PGOProfile/chr.ll | 7 +++--
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 72b6dfa181e86..8dcffe45c644b 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4322,6 +4322,10 @@ static Value *simplifyWithOpReplaced(Value *V, Value
*Op, Value *RepOp,
if (match(I, m_Intrinsic()))
return nullptr;
+ // Don't simplify freeze.
+ if (isa(I))
+return nullptr;
+
// Replace Op with RepOp in instruction operands.
SmallVector NewOps;
bool AnyReplaced = false;
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll
b/llvm/test/Transforms/InstCombine/icmp.ll
index 10ab1fe118348..9ac35745742bb 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5183,3 +5183,18 @@ entry:
%cmp = icmp eq i8 %add2, %add1
ret i1 %cmp
}
+
+define i1 @icmp_freeze_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: @icmp_freeze_sext(
+; CHECK-NEXT:[[CMP1:%.*]] = icmp uge i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:[[CMP1_FR:%.*]] = freeze i1 [[CMP1]]
+; CHECK-NEXT:[[TMP1:%.*]] = icmp eq i16 [[Y]], 0
+; CHECK-NEXT:[[CMP2:%.*]] = or i1 [[TMP1]], [[CMP1_FR]]
+; CHECK-NEXT:ret i1 [[CMP2]]
+;
+ %cmp1 = icmp uge i16 %x, %y
+ %ext = sext i1 %cmp1 to i16
+ %ext.fr = freeze i16 %ext
+ %cmp2 = icmp uge i16 %ext.fr, %y
+ ret i1 %cmp2
+}
diff --git a/llvm/test/Transforms/InstCombine/select.ll
b/llvm/test/Transforms/InstCombine/select.ll
index 888e7d28f78af..1909f9b0daf82 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3708,3 +3708,35 @@ define i32 @src_select_xxory_eq0_xorxy_y(i32 %x, i32 %y)
{
%cond = select i1 %xor0, i32 %xor, i32 %y
ret i32 %cond
}
+
+define i8 @test_replace_freeze_multiuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_multiuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:[[ADD:%.*]] = add i8 [[SHL_FR]], [[SEL]]
+; CHECK-NEXT:ret i8 [[ADD]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ %add = add i8 %shl.fr, %sel
+ ret i8 %add
+}
+
+define i8 @test_replace_freeze_oneuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_oneuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:ret i8 [[SEL]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ ret i8 %sel
+}
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll
b/llvm/test/Transforms/PGOProfile/chr.ll
index 0551a171091ca..38e8f8536a19c 100644
--- a/llvm/test/Transforms/PGOProfile/chr.ll
+++ b/llvm/test/Transforms/PGOProfile/chr.ll
@@ -12
[llvm-branch-commits] [llvm] release/18.x: [LV, LAA] Don't vectorize loops with load and store to invar address. (PR #91092)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91092
>From 0c830c3f2ec1982859b195d4615fb53581227c2f Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Sat, 4 May 2024 20:53:53 +0100
Subject: [PATCH] [LV,LAA] Don't vectorize loops with load and store to invar
address.
Code checking stores to invariant addresses and reductions made an
incorrect assumption that the case of both a load & store to the same
invariant address does not need to be handled.
In some cases when vectorizing with runtime checks, there may be
dependences with a load and store to the same address, storing a
reduction value.
Update LAA to separately track if there was a store-store and a
load-store dependence with an invariant addresses.
Bail out early if there as a load-store dependence with invariant
address. If there was a store-store one, still apply the logic checking
if they all store a reduction.
(cherry picked from commit b54a78d69be1952884462cb897abb9cf60a33978)
---
.../llvm/Analysis/LoopAccessAnalysis.h| 28 +++
llvm/lib/Analysis/LoopAccessAnalysis.cpp | 14 +---
.../Vectorize/LoopVectorizationLegality.cpp | 16 ++---
.../reduction-with-invariant-store.ll | 34 +++
4 files changed, 76 insertions(+), 16 deletions(-)
diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
index e39c371b41ec5..1d67a71f43edd 100644
--- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
@@ -579,7 +579,11 @@ class LoopAccessInfo {
AAResults *AA, DominatorTree *DT, LoopInfo *LI);
/// Return true we can analyze the memory accesses in the loop and there are
- /// no memory dependence cycles.
+ /// no memory dependence cycles. Note that for dependences between loads &
+ /// stores with uniform addresses,
+ /// hasStoreStoreDependenceInvolvingLoopInvariantAddress and
+ /// hasLoadStoreDependenceInvolvingLoopInvariantAddress also need to be
+ /// checked.
bool canVectorizeMemory() const { return CanVecMem; }
/// Return true if there is a convergent operation in the loop. There may
@@ -632,10 +636,16 @@ class LoopAccessInfo {
/// Print the information about the memory accesses in the loop.
void print(raw_ostream &OS, unsigned Depth = 0) const;
- /// If the loop has memory dependence involving an invariant address, i.e.
two
- /// stores or a store and a load, then return true, else return false.
- bool hasDependenceInvolvingLoopInvariantAddress() const {
-return HasDependenceInvolvingLoopInvariantAddress;
+ /// Return true if the loop has memory dependence involving two stores to an
+ /// invariant address, else return false.
+ bool hasStoreStoreDependenceInvolvingLoopInvariantAddress() const {
+return HasStoreStoreDependenceInvolvingLoopInvariantAddress;
+ }
+
+ /// Return true if the loop has memory dependence involving a load and a
store
+ /// to an invariant address, else return false.
+ bool hasLoadStoreDependenceInvolvingLoopInvariantAddress() const {
+return HasLoadStoreDependenceInvolvingLoopInvariantAddress;
}
/// Return the list of stores to invariant addresses.
@@ -697,8 +707,12 @@ class LoopAccessInfo {
bool CanVecMem = false;
bool HasConvergentOp = false;
- /// Indicator that there are non vectorizable stores to a uniform address.
- bool HasDependenceInvolvingLoopInvariantAddress = false;
+ /// Indicator that there are two non vectorizable stores to the same uniform
+ /// address.
+ bool HasStoreStoreDependenceInvolvingLoopInvariantAddress = false;
+ /// Indicator that there is non vectorizable load and store to the same
+ /// uniform address.
+ bool HasLoadStoreDependenceInvolvingLoopInvariantAddress = false;
/// List of stores to invariant addresses.
SmallVector StoresToInvariantAddresses;
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index dd6b88fee415a..fc9e82015e44f 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -2465,7 +2465,7 @@ void LoopAccessInfo::analyzeLoop(AAResults *AA, LoopInfo
*LI,
if (isInvariant(Ptr)) {
// Record store instructions to loop invariant addresses
StoresToInvariantAddresses.push_back(ST);
- HasDependenceInvolvingLoopInvariantAddress |=
+ HasStoreStoreDependenceInvolvingLoopInvariantAddress |=
!UniformStores.insert(Ptr).second;
}
@@ -2521,7 +2521,7 @@ void LoopAccessInfo::analyzeLoop(AAResults *AA, LoopInfo
*LI,
if (UniformStores.count(Ptr)) {
LLVM_DEBUG(dbgs() << "LAA: Found an unsafe dependency between a uniform "
"load and uniform store to the same address!\n");
- HasDependenceInvolvingLoopInvariantAddress = true;
+ HasLoadStoreDependenceInvolvingLoopInvariantAddress = true;
}
MemoryLocation L
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91038
>From 4f8b0b5ef6a16648aa42a10bbf8c0e18ddd1a577 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Fri, 3 May 2024 09:59:33 -0700
Subject: [PATCH] [DAGCombiner] In mergeTruncStore, make sure we aren't storing
shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4
llvm/test/CodeGen/AArch64/pr90936.ll | 20 +++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/pr90936.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
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[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91151
>From b3d50315c9cda097b881d06e23c1e71e945658f6 Mon Sep 17 00:00:00 2001
From: Weihang Fan <134108011+weihangf-ap...@users.noreply.github.com>
Date: Sun, 5 May 2024 04:01:13 -0700
Subject: [PATCH] [AArch64][SelectionDAG] Mask for SUBS with multiple users
cannot be elided (#90911)
In DAGCombiner, the `performCONDCombine` function attempts to remove AND
instructions in front of SUBS (cmp) instructions for which the AND is
transparent. The rules for that are correct, but it fails to take into
account the case where the SUBS instruction has multiple users with
different condition codes for comparison and simply removes the AND for
all of them. This causes a miscompilation in the attached test case.
(cherry picked from commit 72eaa0ed9934bfaa2449091bbc6e45648d1396d6)
---
.../Target/AArch64/AArch64ISelLowering.cpp| 3 ++-
llvm/test/CodeGen/AArch64/and-mask-removal.ll | 22 +++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 95d8ab95b2c09..bcfd0253e73c8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -22122,7 +22122,8 @@ SDValue performCONDCombine(SDNode *N,
SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
unsigned CondOpcode = SubsNode->getOpcode();
- if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0))
+ if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0) ||
+ !SubsNode->hasOneUse())
return SDValue();
// There is a SUBS feeding this condition. Is it fed by a mask we can
diff --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
index 17ff015970168..a31355549ba87 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
@@ -526,4 +526,26 @@ define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {
ret i64 %4
}
+define i64 @test_2_selects(i8 zeroext %a) {
+; CHECK-LABEL: test_2_selects:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:add w9, w0, #24
+; CHECK-NEXT:mov w8, #131
+; CHECK-NEXT:and w9, w9, #0xff
+; CHECK-NEXT:cmp w9, #81
+; CHECK-NEXT:mov w9, #57
+; CHECK-NEXT:csel x8, x8, xzr, lo
+; CHECK-NEXT:csel x9, xzr, x9, eq
+; CHECK-NEXT:add x0, x8, x9
+; CHECK-NEXT:ret
+ %1 = add i8 %a, 24
+ %2 = zext i8 %1 to i64
+ %3 = icmp ult i8 %1, 81
+ %4 = select i1 %3, i64 131, i64 0
+ %5 = icmp eq i8 %1, 81
+ %6 = select i1 %5, i64 0, i64 57
+ %7 = add i64 %4, %6
+ ret i64 %7
+}
+
declare i8 @llvm.usub.sat.i8(i8, i8) #0
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: AtariDreams (AtariDreams)
Changes
When looking through a right shift, we need to make sure that all of the bits
we are using from the shift come from the shift input and not the sign or zero
bits that are shifted in.
Fixes #90936.
(cherry picked from commit 3563af6c06ebc92bcaacef0e33285148ef0f75bd)
---
Full diff: https://github.com/llvm/llvm-project/pull/91038.diff
2 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+4)
- (added) llvm/test/CodeGen/AArch64/pr90936.ll (+20)
``diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5038f8a1fc156..4951e45edb9ed 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8952,6 +8952,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
if (ShiftAmtC % NarrowNumBits != 0)
return SDValue();
+ // Make sure we aren't reading bits that are shifted in.
+ if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits)
+return SDValue();
+
Offset = ShiftAmtC / NarrowNumBits;
WideVal = WideVal.getOperand(0);
}
diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll
b/llvm/test/CodeGen/AArch64/pr90936.ll
new file mode 100644
index 0..38cda8d388945
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr90936.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define void @f(i16 %arg, ptr %arg1) {
+; CHECK-LABEL: f:
+; CHECK: // %bb.0:
+; CHECK-NEXT:ubfx w8, w0, #8, #6
+; CHECK-NEXT:strb w0, [x1]
+; CHECK-NEXT:strb w8, [x1, #1]
+; CHECK-NEXT:ret
+bb:
+ %i = trunc i16 %arg to i8
+ %i2 = trunc i16 %arg to i14
+ %i3 = lshr i14 %i2, 8
+ store i8 %i, ptr %arg1, align 1
+ %i4 = getelementptr i8, ptr %arg1, i64 1
+ %i5 = trunc i14 %i3 to i8
+ store i8 %i5, ptr %i4, align 1
+ ret void
+}
``
https://github.com/llvm/llvm-project/pull/91038
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[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/AtariDreams created
https://github.com/llvm/llvm-project/pull/91682
After reconsidering the words of @nikic, I have decided to revisit the patches
I suggested be backported. Upon further analysis, I think there is a high
likelihood that this change added to release 18.x was referencing a crash that
was caused by a PR that isn't added.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
>From 4a701c9109c255acadd68ab20cb3aebeefc045c6 Mon Sep 17 00:00:00 2001
From: Rose
Date: Thu, 9 May 2024 19:52:24 -0400
Subject: [PATCH] Revert "[SLP]Fix a crash if the argument of call was affected
by minbitwidth analysis."
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
---
.../Transforms/Vectorize/SLPVectorizer.cpp| 21 +
.../X86/call-arg-reduced-by-minbitwidth.ll| 82 ---
2 files changed, 1 insertion(+), 102 deletions(-)
delete mode 100644
llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
diff --git
a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
deleted file mode 100644
index 49e89feb475b9..0
--- a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
+++ /dev/null
@@ -1,82 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
-; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-pc-windows-msvc19.34.0 <
%s | FileCheck %s
-
-define void @test(ptr %0, i8 %1, i1 %cmp12.i) {
-; CHECK-LABEL: define void @test(
-; CHECK-SAME: ptr [[TMP0:%.*]], i8 [[TMP1:%.*]], i1 [[CMP12_I:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT:[[TMP2:%.*]] = insertelement <8 x i1> poison, i1 [[CMP12_I]],
i32 0
-; CHECK-NEXT:[[TMP3:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1>
poison, <8 x i32> zeroinitializer
-; CHECK-NEXT:[[TMP4:%.*]] = insertelement <8 x i8> poison, i8 [[TMP1]],
i32 0
-; CHECK-NEXT:[[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8>
poison, <8 x i32> zeroinitializer
-; CHECK-NEXT:br label [[PRE:%.*]]
-; CHECK: pre:
-; CHECK-NEXT:[[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i32>
-; CHECK-NEXT:[[TMP7:%.*]] = call <8 x i32> @llvm.umax.v8i32(<8 x i32>
[[TMP6]], <8 x i32> )
-; CHECK-NEXT:[[TMP8:%.*]] = add <8 x i32> [[TMP7]],
-; CHECK-NEXT:[[TMP9:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[TMP8]],
<8 x i32> [[TMP6]]
-; CHECK-NEXT:[[TMP10:%.*]] = trunc <8 x i32> [[TMP9]] to <8 x i8>
-; CHECK-NEXT:store <8 x i8> [[TMP10]], ptr [[TMP0]], align 1
-; CHECK-NEXT:br label [[PRE]]
-;
-entry:
- %idx11
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/AtariDreams edited https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: AtariDreams (AtariDreams)
Changes
After reconsidering the words of @nikic, I have decided to revisit the
patches I suggested be backported. Upon further analysis, I think there is a
high likelihood that this change added to release 18.x was referencing a crash
that was caused by a PR that isn't added, and would therefore like to be safe
and therefore ask to retract this PR.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
---
Full diff: https://github.com/llvm/llvm-project/pull/91682.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (+1-20)
- (removed)
llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll (-82)
``diff
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
diff --git
a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
deleted file mode 100644
index 49e89feb475b9..0
--- a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
+++ /dev/null
@@ -1,82 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
-; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-pc-windows-msvc19.34.0 <
%s | FileCheck %s
-
-define void @test(ptr %0, i8 %1, i1 %cmp12.i) {
-; CHECK-LABEL: define void @test(
-; CHECK-SAME: ptr [[TMP0:%.*]], i8 [[TMP1:%.*]], i1 [[CMP12_I:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT:[[TMP2:%.*]] = insertelement <8 x i1> poison, i1 [[CMP12_I]],
i32 0
-; CHECK-NEXT:[[TMP3:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1>
poison, <8 x i32> zeroinitializer
-; CHECK-NEXT:[[TMP4:%.*]] = insertelement <8 x i8> poison, i8 [[TMP1]],
i32 0
-; CHECK-NEXT:[[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8>
poison, <8 x i32> zeroinitializer
-; CHECK-NEXT:br label [[PRE:%.*]]
-; CHECK: pre:
-; CHECK-NEXT:[[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i32>
-; CHECK-NEXT:[[TMP7:%.*]] = call <8 x i32> @llvm.umax.v8i32(<8 x i32>
[[TMP6]], <8 x i32> )
-; CHECK-NEXT:[[TMP8:%.*]] = add <8 x i32> [[TMP7]],
-; CHECK-NEXT:[[TMP9:%.*]] = select <8 x i1> [[TMP3]], <8 x i32> [[TMP8]],
<8 x i32> [[TMP6]]
-; CHECK-NEXT:[[TMP10:%.*]] = trunc <8 x i32> [[TMP9]] to <8 x i8>
-; CHECK-NEXT:store <8 x i8> [[TMP10]], ptr [[TMP0]], align 1
-; CHECK-NEXT:br label [[PRE]]
-;
-entry:
- %idx11 = getelementptr i8, ptr %0, i64 1
- %idx22 = getelementptr i8, ptr %0, i64 2
- %idx33 = getelementptr i8, ptr %0, i64 3
- %idx44 = getelementptr i8, ptr %0, i64 4
- %idx55 = getelementptr i8, ptr %0, i64 5
-
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/AtariDreams updated
https://github.com/llvm/llvm-project/pull/91682
>From add985216713a67b47e72ad967e21fd14df3e1d4 Mon Sep 17 00:00:00 2001
From: Rose
Date: Thu, 9 May 2024 19:52:24 -0400
Subject: [PATCH] Revert "[SLP]Fix a crash if the argument of call was affected
by minbitwidth analysis."
After reconsidering the words of @nikic, I have decided to revisit the patches
I suggested be backported. Upon further analysis, I think there is a high
likelihood that this change added to release 18.x was referencing a crash that
was caused by a PR that isn't added.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
---
.../Transforms/Vectorize/SLPVectorizer.cpp| 21 +--
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
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[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
AtariDreams wrote: > @AtariDreams This bug has existed since at least LLVM 10. What makes it a > candidate for backporting? At best, if the code triggers, we abort the fold, so there is no risk of anything crazy going on if this is added. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
AtariDreams wrote: We do not need to know how to fold every single possible permutation that comes our way, especially if they are so rare that writing compile code optimizing it isn't even worth it. We do, however, need to strive to avoid miscompiles wherever we can, no matter how esoteric the code is. Now, this isn't always possible, but in this case, the alternative codepath given just bails the transform, which is preferable to folding something that should not be. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)
dtcxzyw wrote: @AtariDreams Please don't rebase your patch unless there are some conflicts to be resolved. At least you should tell us what you did. https://github.com/llvm/llvm-project/pull/91419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (PR #90267)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/90267 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (PR #90267)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/90267 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] a102e89 - Revert "Revert "[libc][NFC] adjust time related implementations" (#91657)"
Author: Schrodinger ZHU Yifan Date: 2024-05-09T20:42:55-04:00 New Revision: a102e89bb4334b6cadb7e1b11455d09ffe16b5de URL: https://github.com/llvm/llvm-project/commit/a102e89bb4334b6cadb7e1b11455d09ffe16b5de DIFF: https://github.com/llvm/llvm-project/commit/a102e89bb4334b6cadb7e1b11455d09ffe16b5de.diff LOG: Revert "Revert "[libc][NFC] adjust time related implementations" (#91657)" This reverts commit 5a0e0b659fb5c652c66a083224bf300b4ae32452. Added: libc/hdr/time_macros.h libc/hdr/types/clock_t.h libc/hdr/types/clockid_t.h libc/hdr/types/struct_timeval.h libc/hdr/types/suseconds_t.h libc/hdr/types/time_t.h libc/src/__support/time/CMakeLists.txt libc/src/__support/time/clock_gettime.h libc/src/__support/time/linux/CMakeLists.txt libc/src/__support/time/linux/clock_gettime.cpp libc/src/__support/time/units.h Modified: libc/hdr/CMakeLists.txt libc/hdr/types/CMakeLists.txt libc/src/__support/CMakeLists.txt libc/src/time/clock.h libc/src/time/clock_gettime.h libc/src/time/gettimeofday.h libc/src/time/linux/CMakeLists.txt libc/src/time/linux/clock.cpp libc/src/time/linux/clock_gettime.cpp libc/src/time/linux/gettimeofday.cpp libc/src/time/linux/time.cpp libc/src/time/nanosleep.h libc/src/time/time_func.h Removed: libc/src/time/linux/clockGetTimeImpl.h diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 179b05e6ee966..7549342514304 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -68,4 +68,13 @@ add_proxy_header_library( libc.include.llvm-libc-macros.sys_epoll_macros ) +add_proxy_header_library( + time_macros + HDRS +time_macros.h + FULL_BUILD_DEPENDS +libc.include.time +libc.include.llvm-libc-macros.time_macros +) + add_subdirectory(types) diff --git a/libc/hdr/time_macros.h b/libc/hdr/time_macros.h new file mode 100644 index 0..dc36fe66f7a80 --- /dev/null +++ b/libc/hdr/time_macros.h @@ -0,0 +1,22 @@ +//===-- Definition of macros from time.h --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// + +#ifndef LLVM_LIBC_HDR_TIME_MACROS_H +#define LLVM_LIBC_HDR_TIME_MACROS_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-macros/time-macros.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TIME_MACROS_H diff --git a/libc/hdr/types/CMakeLists.txt b/libc/hdr/types/CMakeLists.txt index 46a66ec590202..3a1bb2f3c340f 100644 --- a/libc/hdr/types/CMakeLists.txt +++ b/libc/hdr/types/CMakeLists.txt @@ -63,3 +63,48 @@ add_proxy_header_library( libc.include.llvm-libc-types.fexcept_t libc.include.fenv ) + +add_proxy_header_library( + time_t + HDRS +time_t.h + FULL_BUILD_DEPENDS +libc.include.llvm-libc-types.time_t +libc.include.time +) + +add_proxy_header_library( + clockid_t + HDRS +clockid_t.h + FULL_BUILD_DEPENDS +libc.include.llvm-libc-types.clockid_t +libc.include.sys_types +) + +add_proxy_header_library( + clock_t + HDRS +clock_t.h + FULL_BUILD_DEPENDS +libc.include.llvm-libc-types.clock_t +libc.include.time +) + +add_proxy_header_library( + suseconds_t + HDRS +suseconds_t.h + FULL_BUILD_DEPENDS +libc.include.llvm-libc-types.suseconds_t +libc.include.sys_time +) + +add_proxy_header_library( + struct_timeval + HDRS +struct_timeval.h + FULL_BUILD_DEPENDS +libc.include.llvm-libc-types.struct_timeval +libc.include.sys_time +) diff --git a/libc/hdr/types/clock_t.h b/libc/hdr/types/clock_t.h new file mode 100644 index 0..b0b658e96c3db --- /dev/null +++ b/libc/hdr/types/clock_t.h @@ -0,0 +1,22 @@ +//===-- Proxy for clock_t -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// + +#ifndef LLVM_LIBC_HDR_TYPES_CLOCK_T_H +#define LLVM_LIBC_HDR_TYPES_CLOCK_T_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/clock_t.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_CLOCK_T_H diff --git a/libc/hdr/types/clockid_t.h b/libc/hdr/types/clockid_t.h new file mode 100644 index 0..42072a2ff --- /dev/null +++ b/libc/hdr/types/clockid_t.h @@ -0,0 +1,22 @@ +//===-- Proxy for clockid_t ---===// +// +// Part of the LLVM Proje
[llvm-branch-commits] [libc] c8d3f1c - fix
Author: Schrodinger ZHU Yifan
Date: 2024-05-09T21:20:40-04:00
New Revision: c8d3f1c80b8b1d2caf53174539c0f17f24a80bef
URL:
https://github.com/llvm/llvm-project/commit/c8d3f1c80b8b1d2caf53174539c0f17f24a80bef
DIFF:
https://github.com/llvm/llvm-project/commit/c8d3f1c80b8b1d2caf53174539c0f17f24a80bef.diff
LOG: fix
Added:
libc/src/__support/time/linux/clock_gettime.h
Modified:
libc/src/__support/time/CMakeLists.txt
libc/src/__support/time/clock_gettime.h
libc/src/__support/time/linux/CMakeLists.txt
libc/src/__support/time/linux/clock_gettime.cpp
Removed:
diff --git a/libc/src/__support/time/CMakeLists.txt
b/libc/src/__support/time/CMakeLists.txt
index 36ce4f9dadb2c..e934ef7b9224a 100644
--- a/libc/src/__support/time/CMakeLists.txt
+++ b/libc/src/__support/time/CMakeLists.txt
@@ -2,9 +2,10 @@ if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS})
add_subdirectory(${LIBC_TARGET_OS})
endif()
-add_object_library(
+add_header_library(
clock_gettime
- ALIAS
+ HDRS
+clock_gettime.h
DEPENDS
.${LIBC_TARGET_OS}.clock_gettime
)
diff --git a/libc/src/__support/time/clock_gettime.h
b/libc/src/__support/time/clock_gettime.h
index 0655ccdc0028b..ef99339a4805e 100644
--- a/libc/src/__support/time/clock_gettime.h
+++ b/libc/src/__support/time/clock_gettime.h
@@ -8,16 +8,11 @@
#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H
#define LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H
-#include "hdr/types/clockid_t.h"
-#include "hdr/types/struct_timespec.h"
-#include "src/__support/common.h"
-#include "src/__support/error_or.h"
-
-namespace LIBC_NAMESPACE {
-namespace internal {
-ErrorOr clock_gettime(clockid_t clockid, timespec *ts);
-}
-} // namespace LIBC_NAMESPACE
+#ifdef __linux__
+#include "src/__support/time/linux/clock_gettime.h"
+#else
+#error "clock_gettime is not supported on this platform"
+#endif
#endif // LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H
diff --git a/libc/src/__support/time/linux/CMakeLists.txt
b/libc/src/__support/time/linux/CMakeLists.txt
index 034fa317ff6df..f04d550555e19 100644
--- a/libc/src/__support/time/linux/CMakeLists.txt
+++ b/libc/src/__support/time/linux/CMakeLists.txt
@@ -1,7 +1,7 @@
add_object_library(
clock_gettime
HDRS
-../clock_gettime.h
+clock_gettime.h
SRCS
clock_gettime.cpp
DEPENDS
diff --git a/libc/src/__support/time/linux/clock_gettime.cpp
b/libc/src/__support/time/linux/clock_gettime.cpp
index 6a131df9ba593..7f266b282a391 100644
--- a/libc/src/__support/time/linux/clock_gettime.cpp
+++ b/libc/src/__support/time/linux/clock_gettime.cpp
@@ -6,9 +6,7 @@
//
//===--===//
-#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
-#define LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
-#include "src/__support/time/clock_gettime.h"
+#include "src/__support/time/linux/clock_gettime.h"
#include "src/__support/OSUtil/syscall.h"
#include
namespace LIBC_NAMESPACE {
@@ -35,5 +33,3 @@ ErrorOr clock_gettime(clockid_t clockid, timespec *ts) {
} // namespace internal
} // namespace LIBC_NAMESPACE
-
-#endif // LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
diff --git a/libc/src/__support/time/linux/clock_gettime.h
b/libc/src/__support/time/linux/clock_gettime.h
new file mode 100644
index 0..b1572726f6301
--- /dev/null
+++ b/libc/src/__support/time/linux/clock_gettime.h
@@ -0,0 +1,23 @@
+//===--- clock_gettime linux implementation -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
+#define LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
+#include "hdr/types/clockid_t.h"
+#include "hdr/types/struct_timespec.h"
+#include "src/__support/common.h"
+
+#include "src/__support/error_or.h"
+
+namespace LIBC_NAMESPACE {
+namespace internal {
+ErrorOr clock_gettime(clockid_t clockid, timespec *ts);
+}
+} // namespace LIBC_NAMESPACE
+
+#endif // LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
___
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[llvm-branch-commits] [libc] 43d2554 - fix
Author: Schrodinger ZHU Yifan
Date: 2024-05-09T21:40:00-04:00
New Revision: 43d25545abc2a5feef7b7d7ec8918059042ab3ba
URL:
https://github.com/llvm/llvm-project/commit/43d25545abc2a5feef7b7d7ec8918059042ab3ba
DIFF:
https://github.com/llvm/llvm-project/commit/43d25545abc2a5feef7b7d7ec8918059042ab3ba.diff
LOG: fix
Added:
Modified:
libc/src/time/gpu/CMakeLists.txt
libc/src/time/gpu/clock.cpp
libc/src/time/gpu/time_utils.h
Removed:
diff --git a/libc/src/time/gpu/CMakeLists.txt
b/libc/src/time/gpu/CMakeLists.txt
index bb79d92399b37..beaf3427504a5 100644
--- a/libc/src/time/gpu/CMakeLists.txt
+++ b/libc/src/time/gpu/CMakeLists.txt
@@ -4,6 +4,8 @@ add_object_library(
time_utils.cpp
HDRS
time_utils.h
+ DEPENDS
+libc.hdr.types.clock_t
)
add_entrypoint_object(
diff --git a/libc/src/time/gpu/clock.cpp b/libc/src/time/gpu/clock.cpp
index 86cc97e2a3bfb..8ddfc27975bba 100644
--- a/libc/src/time/gpu/clock.cpp
+++ b/libc/src/time/gpu/clock.cpp
@@ -6,9 +6,8 @@
//
//===--===//
-#include "time_utils.h"
-
#include "src/time/clock.h"
+#include "src/time/gpu/time_utils.h"
namespace LIBC_NAMESPACE {
diff --git a/libc/src/time/gpu/time_utils.h b/libc/src/time/gpu/time_utils.h
index 8a9a5f0f65b89..3f1fd11c1791c 100644
--- a/libc/src/time/gpu/time_utils.h
+++ b/libc/src/time/gpu/time_utils.h
@@ -9,8 +9,9 @@
#ifndef LLVM_LIBC_SRC_TIME_GPU_TIME_UTILS_H
#define LLVM_LIBC_SRC_TIME_GPU_TIME_UTILS_H
+#include "hdr/time_macros.h"
+#include "hdr/types/clock_t.h"
#include "src/__support/GPU/utils.h"
-
namespace LIBC_NAMESPACE {
#if defined(LIBC_TARGET_ARCH_IS_AMDGPU)
___
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[llvm-branch-commits] [libc] b331275 - one more fix
Author: Schrodinger ZHU Yifan Date: 2024-05-09T21:41:58-04:00 New Revision: b331275547c807418cdf07a8950e6dc31bff530d URL: https://github.com/llvm/llvm-project/commit/b331275547c807418cdf07a8950e6dc31bff530d DIFF: https://github.com/llvm/llvm-project/commit/b331275547c807418cdf07a8950e6dc31bff530d.diff LOG: one more fix Added: Modified: libc/src/time/gpu/CMakeLists.txt Removed: diff --git a/libc/src/time/gpu/CMakeLists.txt b/libc/src/time/gpu/CMakeLists.txt index beaf3427504a5..088271d881911 100644 --- a/libc/src/time/gpu/CMakeLists.txt +++ b/libc/src/time/gpu/CMakeLists.txt @@ -6,6 +6,7 @@ add_object_library( time_utils.h DEPENDS libc.hdr.types.clock_t +libc.hdr.time_macros ) add_entrypoint_object( ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] ad34b79 - fix
Author: Schrodinger ZHU Yifan
Date: 2024-05-09T21:42:30-04:00
New Revision: ad34b7954b7e1ca82660108709c793b251785728
URL:
https://github.com/llvm/llvm-project/commit/ad34b7954b7e1ca82660108709c793b251785728
DIFF:
https://github.com/llvm/llvm-project/commit/ad34b7954b7e1ca82660108709c793b251785728.diff
LOG: fix
Added:
libc/src/__support/time/linux/clock_gettime.h
Modified:
libc/src/__support/time/CMakeLists.txt
libc/src/__support/time/clock_gettime.h
libc/src/__support/time/linux/CMakeLists.txt
libc/src/__support/time/linux/clock_gettime.cpp
libc/src/time/gpu/CMakeLists.txt
libc/src/time/gpu/clock.cpp
libc/src/time/gpu/time_utils.h
Removed:
diff --git a/libc/src/__support/time/CMakeLists.txt
b/libc/src/__support/time/CMakeLists.txt
index 36ce4f9dadb2c..e934ef7b9224a 100644
--- a/libc/src/__support/time/CMakeLists.txt
+++ b/libc/src/__support/time/CMakeLists.txt
@@ -2,9 +2,10 @@ if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS})
add_subdirectory(${LIBC_TARGET_OS})
endif()
-add_object_library(
+add_header_library(
clock_gettime
- ALIAS
+ HDRS
+clock_gettime.h
DEPENDS
.${LIBC_TARGET_OS}.clock_gettime
)
diff --git a/libc/src/__support/time/clock_gettime.h
b/libc/src/__support/time/clock_gettime.h
index 0655ccdc0028b..ef99339a4805e 100644
--- a/libc/src/__support/time/clock_gettime.h
+++ b/libc/src/__support/time/clock_gettime.h
@@ -8,16 +8,11 @@
#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H
#define LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H
-#include "hdr/types/clockid_t.h"
-#include "hdr/types/struct_timespec.h"
-#include "src/__support/common.h"
-#include "src/__support/error_or.h"
-
-namespace LIBC_NAMESPACE {
-namespace internal {
-ErrorOr clock_gettime(clockid_t clockid, timespec *ts);
-}
-} // namespace LIBC_NAMESPACE
+#ifdef __linux__
+#include "src/__support/time/linux/clock_gettime.h"
+#else
+#error "clock_gettime is not supported on this platform"
+#endif
#endif // LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H
diff --git a/libc/src/__support/time/linux/CMakeLists.txt
b/libc/src/__support/time/linux/CMakeLists.txt
index 034fa317ff6df..f04d550555e19 100644
--- a/libc/src/__support/time/linux/CMakeLists.txt
+++ b/libc/src/__support/time/linux/CMakeLists.txt
@@ -1,7 +1,7 @@
add_object_library(
clock_gettime
HDRS
-../clock_gettime.h
+clock_gettime.h
SRCS
clock_gettime.cpp
DEPENDS
diff --git a/libc/src/__support/time/linux/clock_gettime.cpp
b/libc/src/__support/time/linux/clock_gettime.cpp
index 6a131df9ba593..7f266b282a391 100644
--- a/libc/src/__support/time/linux/clock_gettime.cpp
+++ b/libc/src/__support/time/linux/clock_gettime.cpp
@@ -6,9 +6,7 @@
//
//===--===//
-#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
-#define LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
-#include "src/__support/time/clock_gettime.h"
+#include "src/__support/time/linux/clock_gettime.h"
#include "src/__support/OSUtil/syscall.h"
#include
namespace LIBC_NAMESPACE {
@@ -35,5 +33,3 @@ ErrorOr clock_gettime(clockid_t clockid, timespec *ts) {
} // namespace internal
} // namespace LIBC_NAMESPACE
-
-#endif // LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
diff --git a/libc/src/__support/time/linux/clock_gettime.h
b/libc/src/__support/time/linux/clock_gettime.h
new file mode 100644
index 0..b1572726f6301
--- /dev/null
+++ b/libc/src/__support/time/linux/clock_gettime.h
@@ -0,0 +1,23 @@
+//===--- clock_gettime linux implementation -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
+#define LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
+#include "hdr/types/clockid_t.h"
+#include "hdr/types/struct_timespec.h"
+#include "src/__support/common.h"
+
+#include "src/__support/error_or.h"
+
+namespace LIBC_NAMESPACE {
+namespace internal {
+ErrorOr clock_gettime(clockid_t clockid, timespec *ts);
+}
+} // namespace LIBC_NAMESPACE
+
+#endif // LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H
diff --git a/libc/src/time/gpu/CMakeLists.txt
b/libc/src/time/gpu/CMakeLists.txt
index bb79d92399b37..088271d881911 100644
--- a/libc/src/time/gpu/CMakeLists.txt
+++ b/libc/src/time/gpu/CMakeLists.txt
@@ -4,6 +4,9 @@ add_object_library(
time_utils.cpp
HDRS
time_utils.h
+ DEPENDS
+libc.hdr.types.clock_t
+libc.hdr.time_macros
)
add_entrypoint_object(
diff --git a/libc/src/time/gpu/clock.cpp b/libc/src/time/gpu/clock.cpp
index 86cc97e2a3bfb..8ddfc27975bba 100644
[llvm-branch-commits] [llvm] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91666
>From 0166eb8ee85e2cdcb472502206ea4c13f49a6724 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 16:31:17 -0700
Subject: [PATCH] deregisterJumpTable
Created using spr 1.3.4
---
bolt/include/bolt/Core/BinaryContext.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 4a59a581dfedb..f8bf29c674b54 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -430,6 +430,11 @@ class BinaryContext {
return nullptr;
}
+ /// Deregister JumpTable registered at a given \p Address.
+ bool deregisterJumpTable(uint64_t Address) {
+return JumpTables.erase(Address);
+ }
+
unsigned getDWARFEncodingSize(unsigned Encoding) {
if (Encoding == dwarf::DW_EH_PE_omit)
return 0;
___
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[llvm-branch-commits] [llvm] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91666
>From 0166eb8ee85e2cdcb472502206ea4c13f49a6724 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 16:31:17 -0700
Subject: [PATCH] deregisterJumpTable
Created using spr 1.3.4
---
bolt/include/bolt/Core/BinaryContext.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 4a59a581dfedb..f8bf29c674b54 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -430,6 +430,11 @@ class BinaryContext {
return nullptr;
}
+ /// Deregister JumpTable registered at a given \p Address.
+ bool deregisterJumpTable(uint64_t Address) {
+return JumpTables.erase(Address);
+ }
+
unsigned getDWARFEncodingSize(unsigned Encoding) {
if (Encoding == dwarf::DW_EH_PE_omit)
return 0;
___
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[llvm-branch-commits] [llvm] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91666
>From 0166eb8ee85e2cdcb472502206ea4c13f49a6724 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 16:31:17 -0700
Subject: [PATCH] deregisterJumpTable
Created using spr 1.3.4
---
bolt/include/bolt/Core/BinaryContext.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 4a59a581dfedb..f8bf29c674b54 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -430,6 +430,11 @@ class BinaryContext {
return nullptr;
}
+ /// Deregister JumpTable registered at a given \p Address.
+ bool deregisterJumpTable(uint64_t Address) {
+return JumpTables.erase(Address);
+ }
+
unsigned getDWARFEncodingSize(unsigned Encoding) {
if (Encoding == dwarf::DW_EH_PE_omit)
return 0;
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[llvm-branch-commits] [llvm] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91666
>From 0166eb8ee85e2cdcb472502206ea4c13f49a6724 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 16:31:17 -0700
Subject: [PATCH] deregisterJumpTable
Created using spr 1.3.4
---
bolt/include/bolt/Core/BinaryContext.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index 4a59a581dfedb..f8bf29c674b54 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -430,6 +430,11 @@ class BinaryContext {
return nullptr;
}
+ /// Deregister JumpTable registered at a given \p Address.
+ bool deregisterJumpTable(uint64_t Address) {
+return JumpTables.erase(Address);
+ }
+
unsigned getDWARFEncodingSize(unsigned Encoding) {
if (Encoding == dwarf::DW_EH_PE_omit)
return 0;
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[llvm-branch-commits] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/91667 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/91667 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Support POSSIBLE_PIC_FIXED_BRANCH (PR #91667)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/91667
>From dd4d0de42048c063d5e5095a0c2594c7cc578df5 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 9 May 2024 19:35:26 -0700
Subject: [PATCH] Fix RISCVMCPlusBuilder
Created using spr 1.3.4
---
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
index 74f2f0aae91e6..020e62463ee2f 100644
--- a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+++ b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
@@ -177,13 +177,14 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
MCInst &Instruction, InstructionIterator Begin, InstructionIterator End,
const unsigned PtrSize, MCInst *&MemLocInstr, unsigned &BaseRegNum,
unsigned &IndexRegNum, int64_t &DispValue, const MCExpr *&DispExpr,
- MCInst *&PCRelBaseOut) const override {
+ MCInst *&PCRelBaseOut, MCInst *&FixedEntryLoadInst) const override {
MemLocInstr = nullptr;
BaseRegNum = 0;
IndexRegNum = 0;
DispValue = 0;
DispExpr = nullptr;
PCRelBaseOut = nullptr;
+FixedEntryLoadInst = nullptr;
// Check for the following long tail call sequence:
// 1: auipc xi, %pcrel_hi(sym)
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[llvm-branch-commits] [llvm] [BOLT] Eliminate dead jump tables (PR #91666)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/91666 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Enhance s_waitcnt insertion before barrier for gfx12 (#90595) (PR #90719)
tstellar wrote: @jayfoad (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/90719 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Add `HasEVEX512` when `NoVLX` used for 512-bit patterns (#91106) (PR #91118)
tstellar wrote: @phoebewang (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91118 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Mark frame index as "aliased" at argument copy elison (PR #91035)
tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91035 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91425)
tstellar wrote: @phoebewang (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91425 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622) (PR #91034)
tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91034 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't remove parentheses of fold expressions (#91045) (PR #91165)
tstellar wrote: @owenca (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91165 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [FunctionAttrs] Fix incorrect nonnull inference for non-inbounds GEP (#91180) (PR #91286)
tstellar wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91286 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)
tstellar wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/90805 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)
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[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a crash with AlignArrayOfStructures option (#86420) (PR #91049)
https://github.com/owenca approved this pull request. https://github.com/llvm/llvm-project/pull/91049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
