[llvm-branch-commits] [libc] c874f0d - Revert "[libc] Refactor `BigInt` (#86137)"
Author: Guillaume Chatelet
Date: 2024-04-04T11:07:55+02:00
New Revision: c874f0dbfc76f0c5b83e70eb6b8f810fcefb6592
URL:
https://github.com/llvm/llvm-project/commit/c874f0dbfc76f0c5b83e70eb6b8f810fcefb6592
DIFF:
https://github.com/llvm/llvm-project/commit/c874f0dbfc76f0c5b83e70eb6b8f810fcefb6592.diff
LOG: Revert "[libc] Refactor `BigInt` (#86137)"
This reverts commit a2306b65d223212dcfafe12c7299262d8d4fdcb4.
Added:
Modified:
libc/fuzzing/CMakeLists.txt
libc/src/__support/FPUtil/dyadic_float.h
libc/src/__support/UInt.h
libc/src/__support/float_to_string.h
libc/src/__support/integer_literals.h
libc/src/__support/math_extras.h
libc/src/__support/number_pair.h
libc/test/src/__support/integer_literals_test.cpp
libc/test/src/__support/math_extras_test.cpp
libc/test/src/__support/uint_test.cpp
utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel
Removed:
libc/fuzzing/__support/CMakeLists.txt
libc/fuzzing/__support/uint_fuzz.cpp
diff --git a/libc/fuzzing/CMakeLists.txt b/libc/fuzzing/CMakeLists.txt
index 816691b4bd4403..82487688af1162 100644
--- a/libc/fuzzing/CMakeLists.txt
+++ b/libc/fuzzing/CMakeLists.txt
@@ -1,7 +1,6 @@
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fsanitize=fuzzer")
add_custom_target(libc-fuzzer)
-add_subdirectory(__support)
# TODO(#85680): Re-enable math fuzzing after headers are sorted out
# add_subdirectory(math)
add_subdirectory(stdlib)
diff --git a/libc/fuzzing/__support/CMakeLists.txt
b/libc/fuzzing/__support/CMakeLists.txt
deleted file mode 100644
index 278e914e3fbe95..00
--- a/libc/fuzzing/__support/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-add_libc_fuzzer(
- uint_fuzz
- SRCS
-uint_fuzz.cpp
- DEPENDS
-libc.src.__support.uint
-)
diff --git a/libc/fuzzing/__support/uint_fuzz.cpp
b/libc/fuzzing/__support/uint_fuzz.cpp
deleted file mode 100644
index f48f00d3b4ba11..00
--- a/libc/fuzzing/__support/uint_fuzz.cpp
+++ /dev/null
@@ -1,70 +0,0 @@
-#include "src/__support/CPP/bit.h"
-#include "src/__support/UInt.h"
-#include "src/string/memory_utils/inline_memcpy.h"
-
-using namespace LIBC_NAMESPACE;
-
-// Helper function when using gdb / lldb to set a breakpoint and inspect
values.
-template void debug_and_trap(const char *msg, T a, T b) {
- __builtin_trap();
-}
-
-#define DEBUG_AND_TRAP()
-
-#define TEST_BINOP(OP)
\
- if ((a OP b) != (static_cast(BigInt(a) OP BigInt(b
\
-debug_and_trap(#OP, a, b);
-
-#define TEST_SHIFTOP(OP)
\
- if ((a OP b) != (static_cast(BigInt(a) OP b)))
\
-debug_and_trap(#OP, a, b);
-
-#define TEST_FUNCTION(FUN)
\
- if (FUN(a) != FUN(BigInt(a)))
\
-debug_and_trap(#FUN, a, b);
-
-// Test that basic arithmetic operations of BigInt behave like their scalar
-// counterparts.
-template void run_tests(T a, T b) {
- TEST_BINOP(+)
- TEST_BINOP(-)
- TEST_BINOP(*)
- if (b != 0)
-TEST_BINOP(/)
- if (b >= 0 && b < cpp::numeric_limits::digits) {
-TEST_SHIFTOP(<<)
-TEST_SHIFTOP(>>)
- }
- if constexpr (!BigInt::SIGNED) {
-TEST_FUNCTION(cpp::has_single_bit)
-TEST_FUNCTION(cpp::countr_zero)
-TEST_FUNCTION(cpp::countl_zero)
-TEST_FUNCTION(cpp::countl_one)
-TEST_FUNCTION(cpp::countr_one)
- }
-}
-
-// Reads a T from libfuzzer data.
-template T read(const uint8_t *data, size_t &remainder) {
- T out = 0;
- constexpr size_t T_SIZE = sizeof(T);
- const size_t copy_size = remainder < T_SIZE ? remainder : T_SIZE;
- inline_memcpy(&out, data, copy_size);
- remainder -= copy_size;
- return out;
-}
-
-template
-void run_tests(const uint8_t *data, size_t size) {
- const auto a = read(data, size);
- const auto b = read(data, size);
- run_tests(a, b);
-}
-
-extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) {
- // unsigned
- run_tests>(data, size);
- // signed
- run_tests>(data, size);
- return 0;
-}
diff --git a/libc/src/__support/FPUtil/dyadic_float.h
b/libc/src/__support/FPUtil/dyadic_float.h
index e0c205f52383ba..73fd7381c3c838 100644
--- a/libc/src/__support/FPUtil/dyadic_float.h
+++ b/libc/src/__support/FPUtil/dyadic_float.h
@@ -58,9 +58,9 @@ template struct DyadicFloat {
// significant bit.
LIBC_INLINE constexpr DyadicFloat &normalize() {
if (!mantissa.is_zero()) {
- int shift_length = cpp::countl_zero(mantissa);
+ int shift_length = static_cast(mantissa.clz());
exponent -= shift_length;
- mantissa <<= static_cast(shift_length);
+ mantissa.shift_left(static_cast(shift_length));
}
return *this;
}
@@ -233,7 +233,7 @@ LIBC_INLINE constexpr DyadicFloat
quick_add(DyadicFloat a,
[llvm-branch-commits] [flang] 52d27ee - Revert "[flang][runtime] Enable I/O APIs in F18 runtime offload builds. (#87543)"
Author: Mehdi Amini Date: 2024-04-04T14:38:10+02:00 New Revision: 52d27eeec510052a80851f5ee416d61d7f07253a URL: https://github.com/llvm/llvm-project/commit/52d27eeec510052a80851f5ee416d61d7f07253a DIFF: https://github.com/llvm/llvm-project/commit/52d27eeec510052a80851f5ee416d61d7f07253a.diff LOG: Revert "[flang][runtime] Enable I/O APIs in F18 runtime offload builds. (#87543)" This reverts commit 718638d44d3f1033c1ea395244c07d971ec33a90. Added: Modified: flang/include/flang/Runtime/io-api.h flang/runtime/environment.cpp flang/runtime/environment.h flang/runtime/freestanding-tools.h flang/runtime/io-api.cpp flang/runtime/io-error.cpp flang/runtime/io-error.h flang/runtime/namelist.cpp Removed: diff --git a/flang/include/flang/Runtime/io-api.h b/flang/include/flang/Runtime/io-api.h index 328afc715a3f1e..1b6c4f5d6a65ca 100644 --- a/flang/include/flang/Runtime/io-api.h +++ b/flang/include/flang/Runtime/io-api.h @@ -92,18 +92,18 @@ constexpr std::size_t RecommendedInternalIoScratchAreaBytes( // Internal I/O to/from character arrays &/or non-default-kind character // requires a descriptor, which is copied. -Cookie IODECL(BeginInternalArrayListOutput)(const Descriptor &, +Cookie IONAME(BeginInternalArrayListOutput)(const Descriptor &, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginInternalArrayListInput)(const Descriptor &, +Cookie IONAME(BeginInternalArrayListInput)(const Descriptor &, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginInternalArrayFormattedOutput)(const Descriptor &, +Cookie IONAME(BeginInternalArrayFormattedOutput)(const Descriptor &, const char *format, std::size_t formatLength, const Descriptor *formatDescriptor = nullptr, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginInternalArrayFormattedInput)(const Descriptor &, +Cookie IONAME(BeginInternalArrayFormattedInput)(const Descriptor &, const char *format, std::size_t formatLength, const Descriptor *formatDescriptor = nullptr, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, @@ -111,20 +111,20 @@ Cookie IODECL(BeginInternalArrayFormattedInput)(const Descriptor &, // Internal I/O to/from a default-kind character scalar can avoid a // descriptor. -Cookie IODECL(BeginInternalListOutput)(char *internal, +Cookie IONAME(BeginInternalListOutput)(char *internal, std::size_t internalLength, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginInternalListInput)(const char *internal, +Cookie IONAME(BeginInternalListInput)(const char *internal, std::size_t internalLength, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginInternalFormattedOutput)(char *internal, +Cookie IONAME(BeginInternalFormattedOutput)(char *internal, std::size_t internalLength, const char *format, std::size_t formatLength, const Descriptor *formatDescriptor = nullptr, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginInternalFormattedInput)(const char *internal, +Cookie IONAME(BeginInternalFormattedInput)(const char *internal, std::size_t internalLength, const char *format, std::size_t formatLength, const Descriptor *formatDescriptor = nullptr, void **scratchArea = nullptr, std::size_t scratchBytes = 0, const char *sourceFile = nullptr, @@ -139,63 +139,63 @@ Cookie IODECL(BeginInternalFormattedInput)(const char *internal, // If handleError is false, and the unit number is out of range, the program // will be terminated. Otherwise, if unit is out of range, a nonzero Iostat // code is returned and ioMsg is set if it is not a nullptr. -enum Iostat IODECL(CheckUnitNumberInRange64)(std::int64_t unit, +enum Iostat IONAME(CheckUnitNumberInRange64)(std::int64_t unit, bool handleError, char *ioMsg = nullptr, std::size_t ioMsgLength = 0, const char *sourceFile = nullptr, int sourceLine = 0); -enum Iostat IODECL(CheckUnitNumberInRange128)(common::int128_t unit, +enum Iostat IONAME(CheckUnitNumberInRange128)(common::int128_t unit, bool handleError, char *ioMsg = nullptr, std::size_t ioMsgLength = 0, const char *sourceFile = nullptr, int sourceLine = 0); // External synchronous I/O initiation Cookie IODECL(BeginExternalListOutput)(ExternalUnit = DefaultOutputUnit, const char *sourceFile = nullptr, int sourceLine = 0); -Cookie IODECL(BeginExternalListInpu
[llvm-branch-commits] [NFC][HWASAN][UBSAN] Remove cl:init from few opts (PR #87692)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/87692 They are supposed to be used with `getNumOccurrences`. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][HWASAN][UBSAN] Remove cl:init from few opts (PR #87692)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
They are supposed to be used with `getNumOccurrences`.
---
Full diff: https://github.com/llvm/llvm-project/pull/87692.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (+1-1)
- (modified) llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp (+1-1)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index 8562e2efd33e10..ee7301f90f5389 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -191,7 +191,7 @@ static cl::opt
ClHotPercentileCutoff("hwasan-percentile-cutoff-hot",
cl::desc("Hot percentile cuttoff."));
static cl::opt
-ClRandomSkipRate("hwasan-random-skip-rate", cl::init(0),
+ClRandomSkipRate("hwasan-random-skip-rate",
cl::desc("Probability value in the range [0.0, 1.0] "
"to skip instrumentation of a function."));
diff --git a/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
b/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
index 6bcbccda031cec..694dd3c04407f7 100644
--- a/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
+++ b/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
@@ -26,7 +26,7 @@ static cl::opt
HotPercentileCutoff("remove-traps-percentile-cutoff-hot",
cl::desc("Hot percentile cuttoff."));
static cl::opt
-RandomRate("remove-traps-random-rate", cl::init(0.0),
+RandomRate("remove-traps-random-rate",
cl::desc("Probability value in the range [0.0, 1.0] of "
"unconditional pseudo-random checks removal."));
``
https://github.com/llvm/llvm-project/pull/87692
___
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Simplify the implementation of (#86843) (PR #87374)
ian-twilightcoder wrote: @tstellar what do you think? I'm a little nervous someone else will run into mysterious errors where `rsize_t` isn't declared in C++ mode, and if they aren't intimately familiar with the workings of the clang header they're going to be very confused for a very long time. But on the other hand no one else has run into that yet as far as we know, and stddef.h _is_ particularly touchy. I would err on the side of taking this, at it effectively fixes a C++ regression caused by https://reviews.llvm.org/D157757 https://github.com/llvm/llvm-project/pull/87374 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
asb wrote: Thanks for splitting this out. The changes look good to me, but could you please add a brief release note to llvm/docs/ReleaseNotes? Perhaps something like "The default [atomics mapping](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc) was changed to emit an additional trailing fence for sequentially consistent stores, offering compatibility with a future mapping using load-acquire and store-release instructions while remaining fully compatible with objects produced prior to this change. The mapping (ABI) used is recorded [as an ELF attribute](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version). " https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [Headers] Don't declare unreachable() from stddef.h in C++ (#86748) (PR #87696)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/87696 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [Headers] Don't declare unreachable() from stddef.h in C++ (#86748) (PR #87696)
llvmbot wrote: @AaronBallman What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/87696 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [Headers] Don't declare unreachable() from stddef.h in C++ (#86748) (PR #87696)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/87696 Backport df69a305253f1d1b4a4066055a07101a4cc03e55 Requested by: @ian-twilightcoder >From b397b076cf69a6095fec1cc85c465fd65f0493da Mon Sep 17 00:00:00 2001 From: Ian Anderson Date: Thu, 4 Apr 2024 13:01:49 -0700 Subject: [PATCH] [Headers] Don't declare unreachable() from stddef.h in C++ (#86748) Even if __need_unreachable is set, stddef.h should not declare unreachable() in C++ because it conflicts with the declaration in \. (cherry picked from commit df69a305253f1d1b4a4066055a07101a4cc03e55) --- clang/lib/Headers/__stddef_unreachable.h | 4 1 file changed, 4 insertions(+) diff --git a/clang/lib/Headers/__stddef_unreachable.h b/clang/lib/Headers/__stddef_unreachable.h index 518580c92d3f5d..61df43e9732f8a 100644 --- a/clang/lib/Headers/__stddef_unreachable.h +++ b/clang/lib/Headers/__stddef_unreachable.h @@ -7,6 +7,8 @@ *===---=== */ +#ifndef __cplusplus + /* * When -fbuiltin-headers-in-system-modules is set this is a non-modular header * and needs to behave as if it was textual. @@ -15,3 +17,5 @@ (__has_feature(modules) && !__building_module(_Builtin_stddef)) #define unreachable() __builtin_unreachable() #endif + +#endif ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [Headers] Don't declare unreachable() from stddef.h in C++ (#86748) (PR #87696)
llvmbot wrote: @llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-clang Author: None (llvmbot) Changes Backport df69a305253f1d1b4a4066055a07101a4cc03e55 Requested by: @ian-twilightcoder --- Full diff: https://github.com/llvm/llvm-project/pull/87696.diff 1 Files Affected: - (modified) clang/lib/Headers/__stddef_unreachable.h (+4) ``diff diff --git a/clang/lib/Headers/__stddef_unreachable.h b/clang/lib/Headers/__stddef_unreachable.h index 518580c92d3f5d..61df43e9732f8a 100644 --- a/clang/lib/Headers/__stddef_unreachable.h +++ b/clang/lib/Headers/__stddef_unreachable.h @@ -7,6 +7,8 @@ *===---=== */ +#ifndef __cplusplus + /* * When -fbuiltin-headers-in-system-modules is set this is a non-modular header * and needs to behave as if it was textual. @@ -15,3 +17,5 @@ (__has_feature(modules) && !__building_module(_Builtin_stddef)) #define unreachable() __builtin_unreachable() #endif + +#endif `` https://github.com/llvm/llvm-project/pull/87696 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [Headers] Don't declare unreachable() from stddef.h in C++ (#86748) (PR #87696)
ian-twilightcoder wrote: Nominating for backport because this is a C++ regression that was caused by https://reviews.llvm.org/D157757 https://github.com/llvm/llvm-project/pull/87696 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 2476576 - Revert "[ARM][Thumb2] Mark BTI-clearing instructions as scheduling region bou…"
Author: Victor Campos
Date: 2024-04-04T21:26:00+01:00
New Revision: 2476576ce2c5f74eb9252f5016d86adb3a3be9d3
URL:
https://github.com/llvm/llvm-project/commit/2476576ce2c5f74eb9252f5016d86adb3a3be9d3
DIFF:
https://github.com/llvm/llvm-project/commit/2476576ce2c5f74eb9252f5016d86adb3a3be9d3.diff
LOG: Revert "[ARM][Thumb2] Mark BTI-clearing instructions as scheduling region
bou…"
This reverts commit 5ad320abe36357e3290007d3ab353e8637f33720.
Added:
Modified:
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.h
Removed:
llvm/test/CodeGen/ARM/misched-branch-targets.mir
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index fc2834cb0b45c7..083f25f49dec45 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -286,25 +286,6 @@ MachineInstr
*Thumb2InstrInfo::commuteInstructionImpl(MachineInstr &MI,
return ARMBaseInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
}
-bool Thumb2InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
- const MachineBasicBlock *MBB,
- const MachineFunction &MF) const {
- // BTI clearing instructions shall not take part in scheduling regions as
- // they must stay in their intended place. Although PAC isn't BTI clearing,
- // it can be transformed into PACBTI after the pre-RA Machine Scheduling
- // has taken place, so its movement must also be restricted.
- switch (MI.getOpcode()) {
- case ARM::t2BTI:
- case ARM::t2PAC:
- case ARM::t2PACBTI:
- case ARM::t2SG:
-return true;
- default:
-break;
- }
- return ARMBaseInstrInfo::isSchedulingBoundary(MI, MBB, MF);
-}
-
void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
const DebugLoc &dl, Register DestReg,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 8915da8c5bf3c8..4bb412f09dcbeb 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -68,10 +68,6 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
unsigned OpIdx1,
unsigned OpIdx2) const override;
- bool isSchedulingBoundary(const MachineInstr &MI,
-const MachineBasicBlock *MBB,
-const MachineFunction &MF) const override;
-
private:
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
};
diff --git a/llvm/test/CodeGen/ARM/misched-branch-targets.mir
b/llvm/test/CodeGen/ARM/misched-branch-targets.mir
deleted file mode 100644
index b071fbd4538a6d..00
--- a/llvm/test/CodeGen/ARM/misched-branch-targets.mir
+++ /dev/null
@@ -1,166 +0,0 @@
-# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
-
|
- target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
- target triple = "thumbv8.1m.main-arm-none-eabi"
-
- define i32 @foo_bti() #0 {
- entry:
-ret i32 0
- }
-
- define i32 @foo_pac() #0 {
- entry:
-ret i32 0
- }
-
- define i32 @foo_pacbti() #0 {
- entry:
-ret i32 0
- }
-
- define i32 @foo_setjmp() #0 {
- entry:
-ret i32 0
- if.then:
-ret i32 0
- }
-
- define i32 @foo_sg() #0 {
- entry:
-ret i32 0
- }
-
- declare i32 @setjmp(ptr noundef) #1
- declare void @longjmp(ptr noundef, i32 noundef) #2
-
- attributes #0 = { "frame-pointer"="all" "target-cpu"="cortex-m55"
"target-features"="+armv8.1-m.main" }
- attributes #1 = { nounwind returns_twice "frame-pointer"="all"
"target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main" }
- attributes #2 = { noreturn nounwind "frame-pointer"="all"
"target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main" }
-
-...
-name:foo_bti
-tracksRegLiveness: true
-body: |
- bb.0.entry:
-liveins: $r0
-
-t2BTI
-renamable $r0, dead $cpsr = nsw tADDi8 killed renamable $r0, 1, 14 /*
CC::al */, $noreg
-tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
-
-...
-
-# CHECK-LABEL: name:foo_bti
-# CHECK: body:
-# CHECK-NEXT: bb.0.entry:
-# CHECK-NEXT: liveins: $r0
-# CHECK-NEXT: {{^ +$}}
-# CHECK-NEXT: t2BTI
-
-name:foo_pac
-tracksRegLiveness: true
-body: |
- bb.0.entry:
-liveins: $r0, $lr, $r12
-
-frame-setup t2PAC implicit-def $r12, implicit $lr, implicit $sp
-renamable $r2 = nsw t2ADDri $r0, 3, 14 /* CC::al */, $noreg, $noreg
-$sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7,
killed $lr
-$r7 = frame-setup tMOVr killed $sp, 14 /* CC::al */, $noreg
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/84598
>From 7c9298eea6d8239f9afedc3d6aabb1ec0f71e273 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Mon, 11 Mar 2024 15:35:59 -0700
Subject: [PATCH 1/3] Update callsite parameter
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index b2e0ba17e4efe5..5eb2ce3d64513a 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1228,8 +1228,8 @@ mergeAttributesSection(const SmallVector §ions) {
if (r.second) {
firstX3RegUse = sec;
} else {
-mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
- r.first->getSecond(), *i);
+mergeX3RegUse(r.first, firstX3RegUse, sec, r.first->getSecond(),
+ *i);
}
}
continue;
>From c39aca073491f06127eadd8c69cc15e23ea4bc2d Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:44:27 -0700
Subject: [PATCH 2/3] Fix typos
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 09db69286c5e9a..173afce454f382 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1139,8 +1139,8 @@ static void mergeX3RegUse(DenseMap::iterator it,
const InputSectionBase *oldSection,
const InputSectionBase *newSection,
unsigned int oldTag, unsigned int newTag) {
- // X3/GP register usage ar incompatible and cannot be merged, with the
- // exception of the UNKNOWN or 0 value
+ // X3/GP register usage are incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value.
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
if (newTag == X3RegUsage::UNKNOWN)
return;
>From 86bb4a866953c886e586f61da0ec74c9e1129cfa Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 29 Mar 2024 16:15:38 -0700
Subject: [PATCH 3/3] Fix windows test failure
Created using spr 1.3.4
---
llvm/test/CodeGen/RISCV/attributes.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index eecab162eb31c8..9bd730003f0e72 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -519,7 +519,6 @@
; X3SCS: .attribute 16, 2
; X3TMP: .attribute 16, 3
; X3ERR: LLVM ERROR: Cannot set multiple ABIs for X3/GP
-; X3ERR: error: Aborted
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/84598
>From 7c9298eea6d8239f9afedc3d6aabb1ec0f71e273 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Mon, 11 Mar 2024 15:35:59 -0700
Subject: [PATCH 1/3] Update callsite parameter
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index b2e0ba17e4efe5..5eb2ce3d64513a 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1228,8 +1228,8 @@ mergeAttributesSection(const SmallVector §ions) {
if (r.second) {
firstX3RegUse = sec;
} else {
-mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
- r.first->getSecond(), *i);
+mergeX3RegUse(r.first, firstX3RegUse, sec, r.first->getSecond(),
+ *i);
}
}
continue;
>From c39aca073491f06127eadd8c69cc15e23ea4bc2d Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:44:27 -0700
Subject: [PATCH 2/3] Fix typos
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 09db69286c5e9a..173afce454f382 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1139,8 +1139,8 @@ static void mergeX3RegUse(DenseMap::iterator it,
const InputSectionBase *oldSection,
const InputSectionBase *newSection,
unsigned int oldTag, unsigned int newTag) {
- // X3/GP register usage ar incompatible and cannot be merged, with the
- // exception of the UNKNOWN or 0 value
+ // X3/GP register usage are incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value.
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
if (newTag == X3RegUsage::UNKNOWN)
return;
>From 86bb4a866953c886e586f61da0ec74c9e1129cfa Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 29 Mar 2024 16:15:38 -0700
Subject: [PATCH 3/3] Fix windows test failure
Created using spr 1.3.4
---
llvm/test/CodeGen/RISCV/attributes.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index eecab162eb31c8..9bd730003f0e72 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -519,7 +519,6 @@
; X3SCS: .attribute 16, 2
; X3TMP: .attribute 16, 3
; X3ERR: LLVM ERROR: Cannot set multiple ABIs for X3/GP
-; X3ERR: error: Aborted
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
___
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[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Paul Kirth (ilovepi)
Changes
With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to the recommendation in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc
This tag changes the default for the feature flag, and moves to more
consistent naming with respect to existing features.
---
Full diff: https://github.com/llvm/llvm-project/pull/87376.diff
7 Files Affected:
- (modified) llvm/docs/ReleaseNotes.rst (+5)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp (+3-3)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4-4)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-1)
- (modified) llvm/test/CodeGen/RISCV/atomic-load-store.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/forced-atomics.ll (+6-6)
``diff
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 01ecbdba5060b0..821886e3d6f843 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -109,6 +109,11 @@ Changes to the RISC-V Backend
* The experimental Ssqosid extension is supported.
* Zacas is no longer experimental.
* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi)
extension.
+* The default atomics mapping was changed to emit an additional trailing fence
+ for sequentially consistent stores, offering compatibility with a future
+ mapping using load-acquire and store-release instructions while remaining
+ fully compatible with objects produced prior to this change. The mapping
+ (ABI) used is recorded as an ELF attribute.
Changes to the WebAssembly Backend
--
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 9a2621516b3468..532d4e19b98412 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -77,9 +77,9 @@ void RISCVTargetStreamer::emitTargetAttributes(const
MCSubtargetInfo &STI,
}
if (STI.hasFeature(RISCV::FeatureStdExtA)) {
-unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence)
-? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S
-:
RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C;
+unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureNoTrailingSeqCstFence)
+? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C
+:
RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S;
emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f3e641e250182b..e2cc15d4109946 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1178,10 +1178,10 @@ foreach i = {1-31} in
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
"true", "Enable save/restore.">;
-def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
- "EnableSeqCstTrailingFence",
- "true",
- "Enable trailing fence for seq-cst
store.">;
+def FeatureNoTrailingSeqCstFence :
SubtargetFeature<"no-trailing-seq-cst-fence",
+ "EnableTrailingSeqCstFence",
+ "false",
+ "Disable trailing fence for seq-cst
store.">;
def FeatureFastUnalignedAccess
: SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess",
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5a2fb0239e0af2..3f25de8dff649d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -19909,7 +19909,7 @@ Instruction
*RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
if (isa(Inst) && isAcquireOrStronger(Ord))
return Builder.CreateFence(AtomicOrdering::Acquire);
- if (Subtarget.enableSeqCstTrailingFence() && isa(Inst) &&
+ if (Subtarget.enableTrailingSeqCstFence() && isa(Inst) &&
Ord == AtomicOrdering::SequentiallyConsistent)
return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
return nullptr;
diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll
b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
index 2d1fc21cda89b0..1586a133568b35 100644
--- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
@@ -1,26 +1,26 @@
; NOTE: Assertions have been autogenerat
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
ilovepi wrote: > Thanks for splitting this out. The changes look good to me, but could you > please add a brief release note to llvm/docs/ReleaseNotes? Perhaps something > like "The default [atomics > mapping](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc) > was changed to emit an additional trailing fence for sequentially consistent > stores, offering compatibility with a future mapping using load-acquire and > store-release instructions while remaining fully compatible with objects > produced prior to this change. The mapping (ABI) used is recorded [as an ELF > attribute](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version). > " That's a great suggestion. Thanks! https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/84598
>From 7c9298eea6d8239f9afedc3d6aabb1ec0f71e273 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Mon, 11 Mar 2024 15:35:59 -0700
Subject: [PATCH 1/3] Update callsite parameter
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index b2e0ba17e4efe5..5eb2ce3d64513a 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1228,8 +1228,8 @@ mergeAttributesSection(const SmallVector §ions) {
if (r.second) {
firstX3RegUse = sec;
} else {
-mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
- r.first->getSecond(), *i);
+mergeX3RegUse(r.first, firstX3RegUse, sec, r.first->getSecond(),
+ *i);
}
}
continue;
>From c39aca073491f06127eadd8c69cc15e23ea4bc2d Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:44:27 -0700
Subject: [PATCH 2/3] Fix typos
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 09db69286c5e9a..173afce454f382 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1139,8 +1139,8 @@ static void mergeX3RegUse(DenseMap::iterator it,
const InputSectionBase *oldSection,
const InputSectionBase *newSection,
unsigned int oldTag, unsigned int newTag) {
- // X3/GP register usage ar incompatible and cannot be merged, with the
- // exception of the UNKNOWN or 0 value
+ // X3/GP register usage are incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value.
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
if (newTag == X3RegUsage::UNKNOWN)
return;
>From 86bb4a866953c886e586f61da0ec74c9e1129cfa Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 29 Mar 2024 16:15:38 -0700
Subject: [PATCH 3/3] Fix windows test failure
Created using spr 1.3.4
---
llvm/test/CodeGen/RISCV/attributes.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index eecab162eb31c8..9bd730003f0e72 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -519,7 +519,6 @@
; X3SCS: .attribute 16, 2
; X3TMP: .attribute 16, 3
; X3ERR: LLVM ERROR: Cannot set multiple ABIs for X3/GP
-; X3ERR: error: Aborted
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
___
llvm-branch-commits mailing list
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https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/84598
>From 7c9298eea6d8239f9afedc3d6aabb1ec0f71e273 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Mon, 11 Mar 2024 15:35:59 -0700
Subject: [PATCH 1/3] Update callsite parameter
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index b2e0ba17e4efe5..5eb2ce3d64513a 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1228,8 +1228,8 @@ mergeAttributesSection(const SmallVector §ions) {
if (r.second) {
firstX3RegUse = sec;
} else {
-mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
- r.first->getSecond(), *i);
+mergeX3RegUse(r.first, firstX3RegUse, sec, r.first->getSecond(),
+ *i);
}
}
continue;
>From c39aca073491f06127eadd8c69cc15e23ea4bc2d Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:44:27 -0700
Subject: [PATCH 2/3] Fix typos
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 09db69286c5e9a..173afce454f382 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1139,8 +1139,8 @@ static void mergeX3RegUse(DenseMap::iterator it,
const InputSectionBase *oldSection,
const InputSectionBase *newSection,
unsigned int oldTag, unsigned int newTag) {
- // X3/GP register usage ar incompatible and cannot be merged, with the
- // exception of the UNKNOWN or 0 value
+ // X3/GP register usage are incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value.
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
if (newTag == X3RegUsage::UNKNOWN)
return;
>From 86bb4a866953c886e586f61da0ec74c9e1129cfa Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 29 Mar 2024 16:15:38 -0700
Subject: [PATCH 3/3] Fix windows test failure
Created using spr 1.3.4
---
llvm/test/CodeGen/RISCV/attributes.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index eecab162eb31c8..9bd730003f0e72 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -519,7 +519,6 @@
; X3SCS: .attribute 16, 2
; X3TMP: .attribute 16, 3
; X3ERR: LLVM ERROR: Cannot set multiple ABIs for X3/GP
-; X3ERR: error: Aborted
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
___
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[llvm-branch-commits] [NFC][HWASAN][UBSAN] Remove cl:init from few opts (PR #87692)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/87692 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][HWASAN][UBSAN] Remove cl:init from few opts (PR #87692)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/87692 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [UBSAN][HWASAN] Remove redundant flags (PR #87709)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/87709 Presense of `cutoff-hot` or `random-skip-rate` should be enough to trigger optimization. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [UBSAN][HWASAN] Remove redundant flags (PR #87709)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Vitaly Buka (vitalybuka)
Changes
Presense of `cutoff-hot` or `random-skip-rate`
should be enough to trigger optimization.
---
Full diff: https://github.com/llvm/llvm-project/pull/87709.diff
7 Files Affected:
- (modified) clang/lib/CodeGen/BackendUtil.cpp (+1-4)
- (modified) clang/test/CodeGen/remote-traps.c (+1-1)
- (modified) llvm/include/llvm/Transforms/Instrumentation/RemoveTrapsPass.h
(+2)
- (modified) llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (+3-6)
- (modified) llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp (+6)
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out-no-ps.ll
(+2-4)
- (modified) llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll (+4-8)
``diff
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index c8b2a93ae47add..e25a17658a3487 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -100,9 +100,6 @@ using namespace llvm;
namespace llvm {
extern cl::opt PrintPipelinePasses;
-static cl::opt ClRemoveTraps("clang-remove-traps", cl::Optional,
- cl::desc("Insert remove-traps pass."));
-
// Experiment to move sanitizers earlier.
static cl::opt ClSanitizeOnOptimizerEarlyEP(
"sanitizer-early-opt-ep", cl::Optional,
@@ -750,7 +747,7 @@ static void addSanitizers(const Triple &TargetTriple,
PB.registerOptimizerLastEPCallback(SanitizersCallback);
}
- if (ClRemoveTraps) {
+ if (RemoveTrapsPass::IsRequested()) {
// We can optimize after inliner, and PGO profile matching. The hook below
// is called at the end `buildFunctionSimplificationPipeline`, which called
// from `buildInlinerPipeline`, which called after profile matching.
diff --git a/clang/test/CodeGen/remote-traps.c
b/clang/test/CodeGen/remote-traps.c
index 6751afb96d25f2..6983ddbca89291 100644
--- a/clang/test/CodeGen/remote-traps.c
+++ b/clang/test/CodeGen/remote-traps.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -O1 -emit-llvm -fsanitize=signed-integer-overflow
-fsanitize-trap=signed-integer-overflow %s -o - | FileCheck %s
-// RUN: %clang_cc1 -O1 -emit-llvm -fsanitize=signed-integer-overflow
-fsanitize-trap=signed-integer-overflow -mllvm -clang-remove-traps -mllvm
-remove-traps-random-rate=1 %s -o - | FileCheck %s --implicit-check-not="call
void @llvm.ubsantrap" --check-prefixes=REMOVE
+// RUN: %clang_cc1 -O1 -emit-llvm -fsanitize=signed-integer-overflow
-fsanitize-trap=signed-integer-overflow -mllvm -remove-traps-random-rate=1 %s
-o - | FileCheck %s --implicit-check-not="call void @llvm.ubsantrap"
--check-prefixes=REMOVE
int test(int x) {
return x + 123;
diff --git a/llvm/include/llvm/Transforms/Instrumentation/RemoveTrapsPass.h
b/llvm/include/llvm/Transforms/Instrumentation/RemoveTrapsPass.h
index 58f6bbcec5dc9d..bae15840f99282 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/RemoveTrapsPass.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/RemoveTrapsPass.h
@@ -25,6 +25,8 @@ namespace llvm {
class RemoveTrapsPass : public PassInfoMixin {
public:
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+
+ static bool IsRequested();
};
} // namespace llvm
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index ee7301f90f5389..ad1cd9c1f6bf12 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -182,11 +182,6 @@ static cl::opt ClWithTls(
"platforms that support this"),
cl::Hidden, cl::init(true));
-static cl::opt
-CSelectiveInstrumentation("hwasan-selective-instrumentation",
- cl::desc("Use selective instrumentation"),
- cl::Hidden, cl::init(false));
-
static cl::opt ClHotPercentileCutoff("hwasan-percentile-cutoff-hot",
cl::desc("Hot percentile cuttoff."));
@@ -1503,6 +1498,8 @@ bool
HWAddressSanitizer::selectiveInstrumentationShouldSkip(
std::bernoulli_distribution D(ClRandomSkipRate);
return (D(*Rng));
}
+ if (!ClHotPercentileCutoff.getNumOccurrences())
+return false;
auto &MAMProxy = FAM.getResult(F);
ProfileSummaryInfo *PSI =
MAMProxy.getCachedResult(*F.getParent());
@@ -1527,7 +1524,7 @@ void HWAddressSanitizer::sanitizeFunction(Function &F,
NumTotalFuncs++;
- if (CSelectiveInstrumentation && selectiveInstrumentationShouldSkip(F, FAM))
+ if (selectiveInstrumentationShouldSkip(F, FAM))
return;
NumInstrumentedFuncs++;
diff --git a/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
b/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
index 694dd3c04407f7..436ccdc7205bad 100644
--- a/llvm/lib/Transforms/Instrumentation/RemoveTrapsPass.cpp
+++ b/llvm/lib/Transforms/Instr
[llvm-branch-commits] [UBSAN][HWASAN] Remove redundant flags (PR #87709)
https://github.com/fmayer approved this pull request. https://github.com/llvm/llvm-project/pull/87709 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [UBSAN][HWASAN] Remove redundant flags (PR #87709)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/87709 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [UBSAN][HWASAN] Remove redundant flags (PR #87709)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/87709 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SPARC] Implement L and H inline asm argument modifiers (#87259) (PR #87714)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/87714
Backport 697dd93ae30f489e5bcdac74c2ef2d876e3ca064
Requested by: @brad0
>From e2518f696980a2be7ebeff0aef83f05250ddaeca Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Fri, 5 Apr 2024 04:34:07 +0700
Subject: [PATCH] [SPARC] Implement L and H inline asm argument modifiers
(#87259)
This adds support for using the L and H argument modifiers for twinword
operands in inline asm code, such as in:
```
%1 = tail call i64 asm sideeffect "rd %pc, ${0:L} ; srlx ${0:L}, 32, ${0:H}",
"={o4}"()
```
This is needed by the Linux kernel.
(cherry picked from commit 697dd93ae30f489e5bcdac74c2ef2d876e3ca064)
---
llvm/docs/LangRef.rst | 2 ++
llvm/lib/Target/Sparc/SparcAsmPrinter.cpp | 44 +++
llvm/test/CodeGen/SPARC/inlineasm-bad.ll | 9 +
llvm/test/CodeGen/SPARC/inlineasm.ll | 9 +
4 files changed, 64 insertions(+)
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 7a7ddc59ba985d..74b0439da7fc58 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5499,6 +5499,8 @@ RISC-V:
Sparc:
+- ``L``: Print the low-order register of a two-register operand.
+- ``H``: Print the high-order register of a two-register operand.
- ``r``: No effect.
SystemZ:
diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
index 215a8ea8319046..6855471840e9db 100644
--- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -434,6 +434,50 @@ bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr
*MI, unsigned OpNo,
default:
// See if this is a generic print operand
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
+case 'L': // Low order register of a twin word register operand
+case 'H': // High order register of a twin word register operand
+{
+ const SparcSubtarget &Subtarget = MF->getSubtarget();
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ const SparcRegisterInfo *RegisterInfo = Subtarget.getRegisterInfo();
+ Register MOReg = MO.getReg();
+
+ Register HiReg, LoReg;
+ if (!SP::IntPairRegClass.contains(MOReg)) {
+// If we aren't given a register pair already, find out which pair it
+// belongs to. Note that here, the specified register operand, which
+// refers to the high part of the twinword, needs to be an
even-numbered
+// register.
+MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even,
+ &SP::IntPairRegClass);
+if (!MOReg) {
+ SMLoc Loc;
+ OutContext.reportError(
+ Loc, "Hi part of pair should point to an even-numbered
register");
+ OutContext.reportError(
+ Loc, "(note that in some cases it might be necessary to manually
"
+ "bind the input/output registers instead of relying on "
+ "automatic allocation)");
+ return true;
+}
+ }
+
+ HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even);
+ LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd);
+
+ Register Reg;
+ switch (ExtraCode[0]) {
+ case 'L':
+Reg = LoReg;
+break;
+ case 'H':
+Reg = HiReg;
+break;
+ }
+
+ O << '%' << SparcInstPrinter::getRegisterName(Reg);
+ return false;
+}
case 'f':
case 'r':
break;
diff --git a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
index 5bf2adbeb75c95..07eb67df6e5f7e 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
@@ -11,3 +11,12 @@ entry:
tail call void asm sideeffect "faddq $0,$1,$2", "{f38},{f0},{f0}"(fp128
0xL0, fp128 0xL0, fp128 0xL0)
ret void
}
+
+; CHECK-label:test_twinword_error
+; CHECK: error: Hi part of pair should point to an even-numbered register
+; CHECK: error: (note that in some cases it might be necessary to manually
bind the input/output registers instead of relying on automatic allocation)
+
+define i64 @test_twinword_error(){
+ %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32,
${0:H}", "={i1}"()
+ ret i64 %1
+}
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll
b/llvm/test/CodeGen/SPARC/inlineasm.ll
index 8bf34bf1609c18..efb7f7c15220c2 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm.ll
@@ -143,3 +143,12 @@ entry:
%1 = call double asm sideeffect "faddd $1, $2, $0", "=f,f,e"(i64 0, i64 0)
ret void
}
+
+; CHECK-label:test_twinword
+; CHECK: rd %asr5, %i1
+; CHECK: srlx %i1, 32, %i0
+
+define i64 @test_twinword(){
+ %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32,
${0:H}", "={i0}"()
+ ret i64 %1
+}
___
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llvm-br
[llvm-branch-commits] [llvm] release/18.x: [SPARC] Implement L and H inline asm argument modifiers (#87259) (PR #87714)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/87714 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SPARC] Implement L and H inline asm argument modifiers (#87259) (PR #87714)
llvmbot wrote: @koachan What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/87714 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SPARC] Implement L and H inline asm argument modifiers (#87259) (PR #87714)
llvmbot wrote:
@llvm/pr-subscribers-backend-sparc
Author: None (llvmbot)
Changes
Backport 697dd93ae30f489e5bcdac74c2ef2d876e3ca064
Requested by: @brad0
---
Full diff: https://github.com/llvm/llvm-project/pull/87714.diff
4 Files Affected:
- (modified) llvm/docs/LangRef.rst (+2)
- (modified) llvm/lib/Target/Sparc/SparcAsmPrinter.cpp (+44)
- (modified) llvm/test/CodeGen/SPARC/inlineasm-bad.ll (+9)
- (modified) llvm/test/CodeGen/SPARC/inlineasm.ll (+9)
``diff
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 7a7ddc59ba985d..74b0439da7fc58 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5499,6 +5499,8 @@ RISC-V:
Sparc:
+- ``L``: Print the low-order register of a two-register operand.
+- ``H``: Print the high-order register of a two-register operand.
- ``r``: No effect.
SystemZ:
diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
index 215a8ea8319046..6855471840e9db 100644
--- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -434,6 +434,50 @@ bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr
*MI, unsigned OpNo,
default:
// See if this is a generic print operand
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
+case 'L': // Low order register of a twin word register operand
+case 'H': // High order register of a twin word register operand
+{
+ const SparcSubtarget &Subtarget = MF->getSubtarget();
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ const SparcRegisterInfo *RegisterInfo = Subtarget.getRegisterInfo();
+ Register MOReg = MO.getReg();
+
+ Register HiReg, LoReg;
+ if (!SP::IntPairRegClass.contains(MOReg)) {
+// If we aren't given a register pair already, find out which pair it
+// belongs to. Note that here, the specified register operand, which
+// refers to the high part of the twinword, needs to be an
even-numbered
+// register.
+MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even,
+ &SP::IntPairRegClass);
+if (!MOReg) {
+ SMLoc Loc;
+ OutContext.reportError(
+ Loc, "Hi part of pair should point to an even-numbered
register");
+ OutContext.reportError(
+ Loc, "(note that in some cases it might be necessary to manually
"
+ "bind the input/output registers instead of relying on "
+ "automatic allocation)");
+ return true;
+}
+ }
+
+ HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even);
+ LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd);
+
+ Register Reg;
+ switch (ExtraCode[0]) {
+ case 'L':
+Reg = LoReg;
+break;
+ case 'H':
+Reg = HiReg;
+break;
+ }
+
+ O << '%' << SparcInstPrinter::getRegisterName(Reg);
+ return false;
+}
case 'f':
case 'r':
break;
diff --git a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
index 5bf2adbeb75c95..07eb67df6e5f7e 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
@@ -11,3 +11,12 @@ entry:
tail call void asm sideeffect "faddq $0,$1,$2", "{f38},{f0},{f0}"(fp128
0xL0, fp128 0xL0, fp128 0xL0)
ret void
}
+
+; CHECK-label:test_twinword_error
+; CHECK: error: Hi part of pair should point to an even-numbered register
+; CHECK: error: (note that in some cases it might be necessary to manually
bind the input/output registers instead of relying on automatic allocation)
+
+define i64 @test_twinword_error(){
+ %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32,
${0:H}", "={i1}"()
+ ret i64 %1
+}
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll
b/llvm/test/CodeGen/SPARC/inlineasm.ll
index 8bf34bf1609c18..efb7f7c15220c2 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm.ll
@@ -143,3 +143,12 @@ entry:
%1 = call double asm sideeffect "faddd $1, $2, $0", "=f,f,e"(i64 0, i64 0)
ret void
}
+
+; CHECK-label:test_twinword
+; CHECK: rd %asr5, %i1
+; CHECK: srlx %i1, 32, %i0
+
+define i64 @test_twinword(){
+ %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32,
${0:H}", "={i0}"()
+ ret i64 %1
+}
``
https://github.com/llvm/llvm-project/pull/87714
___
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[llvm-branch-commits] [llvm] Bump version to 18.1.4 (PR #87715)
https://github.com/tstellar created https://github.com/llvm/llvm-project/pull/87715 None >From 5c580d287d3422bf7295b16e577717c01ad47ff7 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 4 Apr 2024 14:49:17 -0700 Subject: [PATCH] Bump version to 18.1.4 --- llvm/CMakeLists.txt| 2 +- llvm/utils/lit/lit/__init__.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 253f3943c3b51f..98dbab810bacbf 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 1) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 3) + set(LLVM_VERSION_PATCH 4) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX) diff --git a/llvm/utils/lit/lit/__init__.py b/llvm/utils/lit/lit/__init__.py index 9165056a56bd4d..fcf4a9d8b5f398 100644 --- a/llvm/utils/lit/lit/__init__.py +++ b/llvm/utils/lit/lit/__init__.py @@ -2,7 +2,7 @@ __author__ = "Daniel Dunbar" __email__ = "dan...@minormatter.com" -__versioninfo__ = (18, 1, 3) +__versioninfo__ = (18, 1, 4) __version__ = ".".join(str(v) for v in __versioninfo__) + "dev" __all__ = [] ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Bump version to 18.1.4 (PR #87715)
llvmbot wrote: @llvm/pr-subscribers-testing-tools Author: Tom Stellard (tstellar) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/87715.diff 2 Files Affected: - (modified) llvm/CMakeLists.txt (+1-1) - (modified) llvm/utils/lit/lit/__init__.py (+1-1) ``diff diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 253f3943c3b51f..98dbab810bacbf 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 1) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 3) + set(LLVM_VERSION_PATCH 4) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX) diff --git a/llvm/utils/lit/lit/__init__.py b/llvm/utils/lit/lit/__init__.py index 9165056a56bd4d..fcf4a9d8b5f398 100644 --- a/llvm/utils/lit/lit/__init__.py +++ b/llvm/utils/lit/lit/__init__.py @@ -2,7 +2,7 @@ __author__ = "Daniel Dunbar" __email__ = "dan...@minormatter.com" -__versioninfo__ = (18, 1, 3) +__versioninfo__ = (18, 1, 4) __version__ = ".".join(str(v) for v in __versioninfo__) + "dev" __all__ = [] `` https://github.com/llvm/llvm-project/pull/87715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)
topperc wrote: > s/master/main/ in the url to get the current version. (master "works" but > it's frozen in time; main will track future changes.) > > otherwise lgtm... Probably someone should update AArch64 which has the same comment? https://github.com/llvm/llvm-project/pull/87672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)
https://github.com/rprichard approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/87672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/84598
>From 7c9298eea6d8239f9afedc3d6aabb1ec0f71e273 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Mon, 11 Mar 2024 15:35:59 -0700
Subject: [PATCH 1/3] Update callsite parameter
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index b2e0ba17e4efe5..5eb2ce3d64513a 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1228,8 +1228,8 @@ mergeAttributesSection(const SmallVector §ions) {
if (r.second) {
firstX3RegUse = sec;
} else {
-mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
- r.first->getSecond(), *i);
+mergeX3RegUse(r.first, firstX3RegUse, sec, r.first->getSecond(),
+ *i);
}
}
continue;
>From c39aca073491f06127eadd8c69cc15e23ea4bc2d Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:44:27 -0700
Subject: [PATCH 2/3] Fix typos
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 09db69286c5e9a..173afce454f382 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1139,8 +1139,8 @@ static void mergeX3RegUse(DenseMap::iterator it,
const InputSectionBase *oldSection,
const InputSectionBase *newSection,
unsigned int oldTag, unsigned int newTag) {
- // X3/GP register usage ar incompatible and cannot be merged, with the
- // exception of the UNKNOWN or 0 value
+ // X3/GP register usage are incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value.
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
if (newTag == X3RegUsage::UNKNOWN)
return;
>From 86bb4a866953c886e586f61da0ec74c9e1129cfa Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 29 Mar 2024 16:15:38 -0700
Subject: [PATCH 3/3] Fix windows test failure
Created using spr 1.3.4
---
llvm/test/CodeGen/RISCV/attributes.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index eecab162eb31c8..9bd730003f0e72 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -519,7 +519,6 @@
; X3SCS: .attribute 16, 2
; X3TMP: .attribute 16, 3
; X3ERR: LLVM ERROR: Cannot set multiple ABIs for X3/GP
-; X3ERR: error: Aborted
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
___
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[llvm-branch-commits] [lld] [llvm] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/84598
>From 7c9298eea6d8239f9afedc3d6aabb1ec0f71e273 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Mon, 11 Mar 2024 15:35:59 -0700
Subject: [PATCH 1/3] Update callsite parameter
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index b2e0ba17e4efe5..5eb2ce3d64513a 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1228,8 +1228,8 @@ mergeAttributesSection(const SmallVector §ions) {
if (r.second) {
firstX3RegUse = sec;
} else {
-mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
- r.first->getSecond(), *i);
+mergeX3RegUse(r.first, firstX3RegUse, sec, r.first->getSecond(),
+ *i);
}
}
continue;
>From c39aca073491f06127eadd8c69cc15e23ea4bc2d Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:44:27 -0700
Subject: [PATCH 2/3] Fix typos
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 09db69286c5e9a..173afce454f382 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1139,8 +1139,8 @@ static void mergeX3RegUse(DenseMap::iterator it,
const InputSectionBase *oldSection,
const InputSectionBase *newSection,
unsigned int oldTag, unsigned int newTag) {
- // X3/GP register usage ar incompatible and cannot be merged, with the
- // exception of the UNKNOWN or 0 value
+ // X3/GP register usage are incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value.
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
if (newTag == X3RegUsage::UNKNOWN)
return;
>From 86bb4a866953c886e586f61da0ec74c9e1129cfa Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 29 Mar 2024 16:15:38 -0700
Subject: [PATCH 3/3] Fix windows test failure
Created using spr 1.3.4
---
llvm/test/CodeGen/RISCV/attributes.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index eecab162eb31c8..9bd730003f0e72 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -519,7 +519,6 @@
; X3SCS: .attribute 16, 2
; X3TMP: .attribute 16, 3
; X3ERR: LLVM ERROR: Cannot set multiple ABIs for X3/GP
-; X3ERR: error: Aborted
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
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[llvm-branch-commits] [llvm][IR] Extend BranchWeightMetadata to track provenance of weights (PR #86609)
ilovepi wrote: ping. https://github.com/llvm/llvm-project/pull/86609 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][IR] Extend BranchWeightMetadata to track provenance of weights (PR #86609)
https://github.com/ilovepi edited https://github.com/llvm/llvm-project/pull/86609 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][CodeGen] Precommit test for #84858 (PR #87732)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/87732 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][CodeGen] Precommit test for #84858 (PR #87732)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Vitaly Buka (vitalybuka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/87732.diff
1 Files Affected:
- (modified) clang/test/CodeGen/remote-traps.c (+20-1)
``diff
diff --git a/clang/test/CodeGen/remote-traps.c
b/clang/test/CodeGen/remote-traps.c
index b12c2c6e23b2d1..4be72ab0ea6eea 100644
--- a/clang/test/CodeGen/remote-traps.c
+++ b/clang/test/CodeGen/remote-traps.c
@@ -9,7 +9,7 @@
// CHECK-NEXT:[[TMP1:%.*]] = extractvalue { i32, i1 } [[TMP0]], 1,
!nosanitize [[META2]]
// CHECK-NEXT:br i1 [[TMP1]], label [[TRAP:%.*]], label [[CONT:%.*]],
!nosanitize [[META2]]
// CHECK: trap:
-// CHECK-NEXT:tail call void @llvm.ubsantrap(i8 0) #[[ATTR3:[0-9]+]],
!nosanitize [[META2]]
+// CHECK-NEXT:tail call void @llvm.ubsantrap(i8 0) #[[ATTR5:[0-9]+]],
!nosanitize [[META2]]
// CHECK-NEXT:unreachable, !nosanitize [[META2]]
// CHECK: cont:
// CHECK-NEXT:[[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP0]], 0,
!nosanitize [[META2]]
@@ -29,9 +29,28 @@ int test(int x) {
return x + 123;
}
+// CHECK-LABEL: define dso_local noundef i32 @test_runtime(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR3:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1
@llvm.allow.runtime.check(metadata [[META3:![0-9]+]])
+// CHECK-NEXT:[[CONV:%.*]] = zext i1 [[TMP0]] to i32
+// CHECK-NEXT:ret i32 [[CONV]]
+//
+// REMOVE-LABEL: define dso_local noundef i32 @test_runtime(
+// REMOVE-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// REMOVE-NEXT: entry:
+// REMOVE-NEXT:[[TMP0:%.*]] = tail call i1
@llvm.allow.runtime.check(metadata [[META3:![0-9]+]])
+// REMOVE-NEXT:[[CONV:%.*]] = zext i1 [[TMP0]] to i32
+// REMOVE-NEXT:ret i32 [[CONV]]
+//
+int test_runtime() {
+ return __builtin_allow_runtime_check("mycheck");
+}
//.
// CHECK: [[META2]] = !{}
+// CHECK: [[META3]] = !{!"mycheck"}
//.
// REMOVE: [[META2]] = !{}
+// REMOVE: [[META3]] = !{!"mycheck"}
//.
``
https://github.com/llvm/llvm-project/pull/87732
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[llvm-branch-commits] [NFC][CodeGen] Precommit test for #84858 (PR #87732)
vitalybuka wrote: Not needed https://github.com/llvm/llvm-project/pull/87732 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][CodeGen] Precommit test for #84858 (PR #87732)
https://github.com/vitalybuka closed https://github.com/llvm/llvm-project/pull/87732 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Use BAT interfaces in YAMLProfileWriter::convert (PR #86219)
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/86219
>From 685d3f5fa6ae75d6c3e22873a52ea8347e170c1e Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 28 Mar 2024 10:16:15 -0700
Subject: [PATCH 1/5] Get rid of std::map::at
Created using spr 1.3.4
---
bolt/lib/Profile/BoltAddressTranslation.cpp | 5 -
bolt/lib/Profile/YAMLProfileWriter.cpp | 3 ++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/bolt/lib/Profile/BoltAddressTranslation.cpp
b/bolt/lib/Profile/BoltAddressTranslation.cpp
index 6d3f83efbe5f5a..7c54ba1971cbac 100644
--- a/bolt/lib/Profile/BoltAddressTranslation.cpp
+++ b/bolt/lib/Profile/BoltAddressTranslation.cpp
@@ -600,7 +600,10 @@ BoltAddressTranslation::getBFBranches(uint64_t
OutputAddress) const {
unsigned
BoltAddressTranslation::getSecondaryEntryPointId(uint64_t Address,
uint32_t Offset) const {
- const std::vector &Offsets = SecondaryEntryPointsMap.at(Address);
+ auto FunctionIt = SecondaryEntryPointsMap.find(Address);
+ if (FunctionIt == SecondaryEntryPointsMap.end())
+return UINT_MAX;
+ const std::vector &Offsets = FunctionIt->second;
auto OffsetIt = std::find(Offsets.begin(), Offsets.end(), Offset);
if (OffsetIt == Offsets.end())
return UINT_MAX;
diff --git a/bolt/lib/Profile/YAMLProfileWriter.cpp
b/bolt/lib/Profile/YAMLProfileWriter.cpp
index 78fb1e8539d477..bacee136de3f87 100644
--- a/bolt/lib/Profile/YAMLProfileWriter.cpp
+++ b/bolt/lib/Profile/YAMLProfileWriter.cpp
@@ -48,7 +48,8 @@ setCSIDestination(const BinaryContext &BC,
yaml::bolt::CallSiteInfo &CSI,
if (SymbolValue.getError())
return Callee;
if (uint32_t Offset = SymbolValue.get() - Callee->getAddress())
- EntryID = (*GetBATSecondaryEntryPointId)(Callee->getAddress(), Offset);
+ EntryID =
+ (*GetBATSecondaryEntryPointId)(Callee->getAddress(), Offset) + 1;
} else {
BC.getFunctionForSymbol(Symbol, &EntryID);
}
>From 03520283ff38a47bc44cfa395534837d8da66934 Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Thu, 28 Mar 2024 22:37:24 -0700
Subject: [PATCH 2/5] Fixed setting of BAT secondary entry point, updated test
Created using spr 1.3.4
---
bolt/include/bolt/Profile/YAMLProfileWriter.h | 11 +--
bolt/lib/Profile/DataAggregator.cpp | 11 +--
bolt/lib/Profile/YAMLProfileWriter.cpp| 71 ---
.../X86/yaml-secondary-entry-discriminator.s | 52 +-
4 files changed, 97 insertions(+), 48 deletions(-)
diff --git a/bolt/include/bolt/Profile/YAMLProfileWriter.h
b/bolt/include/bolt/Profile/YAMLProfileWriter.h
index 7db581652a5b73..0db2e3fd90f9f1 100644
--- a/bolt/include/bolt/Profile/YAMLProfileWriter.h
+++ b/bolt/include/bolt/Profile/YAMLProfileWriter.h
@@ -15,6 +15,7 @@
namespace llvm {
namespace bolt {
+class BoltAddressTranslation;
class RewriteInstance;
class YAMLProfileWriter {
@@ -31,17 +32,9 @@ class YAMLProfileWriter {
/// Save execution profile for that instance.
std::error_code writeProfile(const RewriteInstance &RI);
- /// Callback to determine if a function is covered by BAT.
- using IsBATCallbackTy = std::optional>;
- /// Callback to get secondary entry point id for a given function and offset.
- using GetBATSecondaryEntryPointIdCallbackTy =
- std::optional>;
-
static yaml::bolt::BinaryFunctionProfile
convert(const BinaryFunction &BF, bool UseDFS,
- IsBATCallbackTy IsBATFunction = std::nullopt,
- GetBATSecondaryEntryPointIdCallbackTy GetBATSecondaryEntryPointId =
- std::nullopt);
+ const BoltAddressTranslation *BAT = nullptr);
};
} // namespace bolt
diff --git a/bolt/lib/Profile/DataAggregator.cpp
b/bolt/lib/Profile/DataAggregator.cpp
index 5b5ce5532ffdb9..71824e2cc0e97a 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -2324,13 +2324,6 @@ std::error_code
DataAggregator::writeBATYAML(BinaryContext &BC,
BP.Header.Flags = opts::BasicAggregation ? BinaryFunction::PF_SAMPLE
: BinaryFunction::PF_LBR;
- auto IsBATFunction = [&](uint64_t Address) {
-return BAT->isBATFunction(Address);
- };
- auto GetSecondaryEntryPointId = [&](uint64_t Address, uint32_t Offset) {
-return BAT->getSecondaryEntryPointId(Address, Offset);
- };
-
if (!opts::BasicAggregation) {
// Convert profile for functions not covered by BAT
for (auto &BFI : BC.getBinaryFunctions()) {
@@ -2339,8 +2332,8 @@ std::error_code
DataAggregator::writeBATYAML(BinaryContext &BC,
continue;
if (BAT->isBATFunction(Function.getAddress()))
continue;
- BP.Functions.emplace_back(YAMLProfileWriter::convert(
- Function, /*UseDFS=*/false, IsBATFunction,
GetSecondaryEntryPointId));
+ BP.Functions.emplace_back(
+ YAMLProfileWriter::convert(Function, /*UseDFS=*/false, BAT));
}
for (const auto &KV : Names
[llvm-branch-commits] [llvm] [BOLT] Use BAT interfaces in YAMLProfileWriter::convert (PR #86219)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/86219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Use BAT interfaces in YAMLProfileWriter::convert (PR #86219)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/86219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Use BAT for YAML profile call target information (PR #86219)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/86219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang][CodeGen] Remove SimplifyCFGPass preceding RemoveTrapsPass (PR #84852)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84852 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang][CodeGen] Remove SimplifyCFGPass preceding RemoveTrapsPass (PR #84852)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84852 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Rename `remove-traps` to `lower-builtin-hot` (PR #84853)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84853 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] release/18.x: [lld/ELF][X86] Respect outSecOff when checking if GOTPCREL can be relaxed (#86334) (PR #86688)
aeubanks wrote: I think (not 100% sure) that this fixes a regression that was introduced between 17 and 18, so it shouldn't require release notes. https://github.com/llvm/llvm-project/pull/86688 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Rename `remove-traps` to `lower-builtin-hot` (PR #84853)
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/84853 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [polly] release/18.x: [clang-format] Correctly annotate braces of empty ctors/dtors (#82097) (PR #87735)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/87735 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [polly] release/18.x: [clang-format] Correctly annotate braces of empty ctors/dtors (#82097) (PR #87735)
llvmbot wrote: @mydeveloperday What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/87735 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [polly] release/18.x: [clang-format] Correctly annotate braces of empty ctors/dtors (#82097) (PR #87735)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/87735
Backport 8de230093f58
Requested by: @owenca
>From dbe3aa6188d4f0b3718c1562c32ef67fa18d638c Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Mon, 19 Feb 2024 12:41:22 -0800
Subject: [PATCH] [clang-format] Correctly annotate braces of empty ctors/dtors
(#82097)
Also reformat Polly.
Fixes #79834.
(cherry picked from commit 8de230093f585b64fcd642b46e6560131e95b394)
---
clang/lib/Format/TokenAnnotator.cpp | 20 +--
clang/unittests/Format/TokenAnnotatorTest.cpp | 14 +
polly/lib/Exchange/JSONExporter.cpp | 2 +-
polly/lib/Transform/DeLICM.cpp| 2 +-
polly/lib/Transform/FlattenSchedule.cpp | 2 +-
polly/lib/Transform/ForwardOpTree.cpp | 2 +-
6 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/clang/lib/Format/TokenAnnotator.cpp
b/clang/lib/Format/TokenAnnotator.cpp
index d0c4273cfc7e58..4d482e6543d6f5 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -3450,10 +3450,11 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
for (AnnotatedLine *ChildLine : Line.Children)
calculateFormattingInformation(*ChildLine);
- Line.First->TotalLength =
- Line.First->IsMultiline ? Style.ColumnLimit
- : Line.FirstStartColumn +
Line.First->ColumnWidth;
- FormatToken *Current = Line.First->Next;
+ auto *First = Line.First;
+ First->TotalLength = First->IsMultiline
+ ? Style.ColumnLimit
+ : Line.FirstStartColumn + First->ColumnWidth;
+ FormatToken *Current = First->Next;
bool InFunctionDecl = Line.MightBeFunctionDecl;
bool AlignArrayOfStructures =
(Style.AlignArrayOfStructures != FormatStyle::AIAS_None &&
@@ -3475,16 +3476,15 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
if (const bool IsCtorOrDtor = Tok->is(TT_CtorDtorDeclName);
IsCtorOrDtor ||
isFunctionDeclarationName(Style.isCpp(), *Tok, Line, ClosingParen)) {
- if (!IsCtorOrDtor) {
-LineIsFunctionDeclaration = true;
+ if (!IsCtorOrDtor)
Tok->setFinalizedType(TT_FunctionDeclarationName);
- }
+ LineIsFunctionDeclaration = true;
SeenName = true;
break;
}
}
- if (IsCpp && LineIsFunctionDeclaration &&
+ if (IsCpp && (LineIsFunctionDeclaration || First->is(TT_CtorDtorDeclName)) &&
Line.endsWith(tok::semi, tok::r_brace)) {
auto *Tok = Line.Last->Previous;
while (Tok->isNot(tok::r_brace))
@@ -3507,7 +3507,7 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
if (IsCpp) {
if (!LineIsFunctionDeclaration) {
// Annotate */&/&& in `operator` function calls as binary operators.
- for (const auto *Tok = Line.First; Tok; Tok = Tok->Next) {
+ for (const auto *Tok = First; Tok; Tok = Tok->Next) {
if (Tok->isNot(tok::kw_operator))
continue;
do {
@@ -3644,7 +3644,7 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
calculateUnbreakableTailLengths(Line);
unsigned IndentLevel = Line.Level;
- for (Current = Line.First; Current; Current = Current->Next) {
+ for (Current = First; Current; Current = Current->Next) {
if (Current->Role)
Current->Role->precomputeFormattingInfos(Current);
if (Current->MatchingParen &&
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp
b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 67678c18963b1f..c72c9384ff91d6 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -2595,6 +2595,20 @@ TEST_F(TokenAnnotatorTest, BraceKind) {
EXPECT_TOKEN(Tokens[4], tok::l_brace, TT_FunctionLBrace);
EXPECT_BRACE_KIND(Tokens[4], BK_Block);
EXPECT_BRACE_KIND(Tokens[6], BK_Block);
+
+ Tokens = annotate("struct Foo {\n"
+" Foo() {};\n"
+" ~Foo() {};\n"
+"};");
+ ASSERT_EQ(Tokens.size(), 19u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_CtorDtorDeclName);
+ EXPECT_TOKEN(Tokens[6], tok::l_brace, TT_FunctionLBrace);
+ EXPECT_BRACE_KIND(Tokens[6], BK_Block);
+ EXPECT_BRACE_KIND(Tokens[7], BK_Block);
+ EXPECT_TOKEN(Tokens[10], tok::identifier, TT_CtorDtorDeclName);
+ EXPECT_TOKEN(Tokens[13], tok::l_brace, TT_FunctionLBrace);
+ EXPECT_BRACE_KIND(Tokens[13], BK_Block);
+ EXPECT_BRACE_KIND(Tokens[14], BK_Block);
}
TEST_F(TokenAnnotatorTest, StreamOperator) {
diff --git a/polly/lib/Exchange/JSONExporter.cpp
b/polly/lib/Exchange/JSONExporter.cpp
index 74d4e6c7993fa3..63fb06a634cc12 100644
--- a/polly/lib/Exchange/JSONExporter.cpp
+++ b/polly/lib/Exchange/JSONExporter.cpp
@@ -842,7 +842,7 @@ class JSONImporterPrinterLegacyPass final : public ScopPass
{
public:
static char ID;
[llvm-branch-commits] [clang] [polly] release/18.x: [clang-format] Correctly annotate braces of empty ctors/dtors (#82097) (PR #87735)
llvmbot wrote:
@llvm/pr-subscribers-clang-format
Author: None (llvmbot)
Changes
Backport 8de230093f58
Requested by: @owenca
---
Full diff: https://github.com/llvm/llvm-project/pull/87735.diff
6 Files Affected:
- (modified) clang/lib/Format/TokenAnnotator.cpp (+10-10)
- (modified) clang/unittests/Format/TokenAnnotatorTest.cpp (+14)
- (modified) polly/lib/Exchange/JSONExporter.cpp (+1-1)
- (modified) polly/lib/Transform/DeLICM.cpp (+1-1)
- (modified) polly/lib/Transform/FlattenSchedule.cpp (+1-1)
- (modified) polly/lib/Transform/ForwardOpTree.cpp (+1-1)
``diff
diff --git a/clang/lib/Format/TokenAnnotator.cpp
b/clang/lib/Format/TokenAnnotator.cpp
index d0c4273cfc7e58..4d482e6543d6f5 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -3450,10 +3450,11 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
for (AnnotatedLine *ChildLine : Line.Children)
calculateFormattingInformation(*ChildLine);
- Line.First->TotalLength =
- Line.First->IsMultiline ? Style.ColumnLimit
- : Line.FirstStartColumn +
Line.First->ColumnWidth;
- FormatToken *Current = Line.First->Next;
+ auto *First = Line.First;
+ First->TotalLength = First->IsMultiline
+ ? Style.ColumnLimit
+ : Line.FirstStartColumn + First->ColumnWidth;
+ FormatToken *Current = First->Next;
bool InFunctionDecl = Line.MightBeFunctionDecl;
bool AlignArrayOfStructures =
(Style.AlignArrayOfStructures != FormatStyle::AIAS_None &&
@@ -3475,16 +3476,15 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
if (const bool IsCtorOrDtor = Tok->is(TT_CtorDtorDeclName);
IsCtorOrDtor ||
isFunctionDeclarationName(Style.isCpp(), *Tok, Line, ClosingParen)) {
- if (!IsCtorOrDtor) {
-LineIsFunctionDeclaration = true;
+ if (!IsCtorOrDtor)
Tok->setFinalizedType(TT_FunctionDeclarationName);
- }
+ LineIsFunctionDeclaration = true;
SeenName = true;
break;
}
}
- if (IsCpp && LineIsFunctionDeclaration &&
+ if (IsCpp && (LineIsFunctionDeclaration || First->is(TT_CtorDtorDeclName)) &&
Line.endsWith(tok::semi, tok::r_brace)) {
auto *Tok = Line.Last->Previous;
while (Tok->isNot(tok::r_brace))
@@ -3507,7 +3507,7 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
if (IsCpp) {
if (!LineIsFunctionDeclaration) {
// Annotate */&/&& in `operator` function calls as binary operators.
- for (const auto *Tok = Line.First; Tok; Tok = Tok->Next) {
+ for (const auto *Tok = First; Tok; Tok = Tok->Next) {
if (Tok->isNot(tok::kw_operator))
continue;
do {
@@ -3644,7 +3644,7 @@ void
TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
calculateUnbreakableTailLengths(Line);
unsigned IndentLevel = Line.Level;
- for (Current = Line.First; Current; Current = Current->Next) {
+ for (Current = First; Current; Current = Current->Next) {
if (Current->Role)
Current->Role->precomputeFormattingInfos(Current);
if (Current->MatchingParen &&
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp
b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 67678c18963b1f..c72c9384ff91d6 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -2595,6 +2595,20 @@ TEST_F(TokenAnnotatorTest, BraceKind) {
EXPECT_TOKEN(Tokens[4], tok::l_brace, TT_FunctionLBrace);
EXPECT_BRACE_KIND(Tokens[4], BK_Block);
EXPECT_BRACE_KIND(Tokens[6], BK_Block);
+
+ Tokens = annotate("struct Foo {\n"
+" Foo() {};\n"
+" ~Foo() {};\n"
+"};");
+ ASSERT_EQ(Tokens.size(), 19u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_CtorDtorDeclName);
+ EXPECT_TOKEN(Tokens[6], tok::l_brace, TT_FunctionLBrace);
+ EXPECT_BRACE_KIND(Tokens[6], BK_Block);
+ EXPECT_BRACE_KIND(Tokens[7], BK_Block);
+ EXPECT_TOKEN(Tokens[10], tok::identifier, TT_CtorDtorDeclName);
+ EXPECT_TOKEN(Tokens[13], tok::l_brace, TT_FunctionLBrace);
+ EXPECT_BRACE_KIND(Tokens[13], BK_Block);
+ EXPECT_BRACE_KIND(Tokens[14], BK_Block);
}
TEST_F(TokenAnnotatorTest, StreamOperator) {
diff --git a/polly/lib/Exchange/JSONExporter.cpp
b/polly/lib/Exchange/JSONExporter.cpp
index 74d4e6c7993fa3..63fb06a634cc12 100644
--- a/polly/lib/Exchange/JSONExporter.cpp
+++ b/polly/lib/Exchange/JSONExporter.cpp
@@ -842,7 +842,7 @@ class JSONImporterPrinterLegacyPass final : public ScopPass
{
public:
static char ID;
- JSONImporterPrinterLegacyPass() : JSONImporterPrinterLegacyPass(outs()){};
+ JSONImporterPrinterLegacyPass() : JSONImporterPrinterLegacyPass(outs()) {}
explicit JSONImporterPrinterLegacyPass(llvm::raw_ostream &OS)
: ScopPass(ID), OS(OS) {}
diff --git a/poll
[llvm-branch-commits] [BOLT][BAT] Fix handling of split functions (PR #87569)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/87569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][BAT] Fix handling of split functions (PR #87569)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/87569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Cover all call sites in writeBATYAML (PR #87743)
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/87743 Combine blocks from cold fragments in getBFBranches. Depends on https://github.com/llvm/llvm-project/pull/87569 Test Plan: Updated bolt/test/X86/yaml-secondary-entry-discriminator.s ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][BAT] Fix handling of split functions (PR #87569)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/87569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][BAT] Fix handling of split functions (PR #87569)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/87569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT][BAT] Fix handling of split functions (PR #87569)
https://github.com/aaupov ready_for_review https://github.com/llvm/llvm-project/pull/87569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Cover all call sites in writeBATYAML (PR #87743)
https://github.com/aaupov edited https://github.com/llvm/llvm-project/pull/87743 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Cover all call sites in writeBATYAML (PR #87743)
https://github.com/aaupov ready_for_review https://github.com/llvm/llvm-project/pull/87743 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
