date:20240324

[llvm-branch-commits] [flang] [flang][OpenMP] Support tasks' implicit firstprivate DSA (PR #85989)

2024-03-24 Thread Kiran Chandramohan via llvm-branch-commits


kiranchandramohan wrote:

I am away this week, will come back to this next week.

https://github.com/llvm/llvm-project/pull/85989
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[llvm-branch-commits] [llvm] release/18.x: [PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098) (PR #86375)

2024-03-24 Thread Chen Zheng via llvm-branch-commits


https://github.com/chenzheng1030 approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/86375
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[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits


wangpc-pp wrote:

Ping.

https://github.com/llvm/llvm-project/pull/84448
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits


wangpc-pp wrote:

Ping.

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits


wangpc-pp wrote:

Ping.

https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

2024-03-24 Thread Craig Topper via llvm-branch-commits



@@ -483,90 +482,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   }
 
   // VR->VR copies.
-  if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1);
-return;
-  }
-
-  if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2);
-return;
-  }
-
-  if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4);
-return;
-  }
-
-  if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_8);
-return;
-  }
-
-  if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/2);
-return;
-  }
-
-  if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
-  /*NF=*/2);
-return;
-  }
-
-  if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4,
-  /*NF=*/2);
-return;
-  }
-
-  if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/3);
-return;
-  }
-
-  if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
-  /*NF=*/3);
-return;
-  }
-
-  if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/4);
-return;
-  }
-
-  if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
-  /*NF=*/4);
-return;
-  }
-
-  if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/5);
-return;
-  }
-
-  if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/6);
-return;
-  }
-
-  if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/7);
-return;
-  }
-
-  if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
-  /*NF=*/8);
-return;
+  for (const auto &RegClass :
+   {RISCV::VRRegClass, RISCV::VRM2RegClass, RISCV::VRM4RegClass,

topperc wrote:

What is the type of this initializer list? Is it making copies of all of the 
register classes?

https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

2024-03-24 Thread Craig Topper via llvm-branch-commits


https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/84448
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits



@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
&MBB,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc &Desc = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](MCRegister SrcReg, MCRegister DstReg)
+  -> std::tuple {
+unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)

lukel97 wrote:

Is this the same as `SrcEncoding % 8 == 0 && DstEncoding % 8 == 0`?

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

2024-03-24 Thread Luke Lau via llvm-branch-commits


https://github.com/lukel97 approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/84448
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits



@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
&MBB,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc &Desc = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](MCRegister SrcReg, MCRegister DstReg)
+  -> std::tuple {
+unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)

wangpc-pp wrote:

Yes! Using masks is an optimization here. But I think the compiler can do the 
favor, so using division will be OK too.

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

2024-03-24 Thread Luke Lau via llvm-branch-commits



@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
   [RV32,  RV64],
   [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+  bit IsVRegClass = 0;
+  int VLMul = 1;
+  int NF = 1;

lukel97 wrote:

Should these default to 0 since 0 is an invalid LMUL/NF?

https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits



@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
&MBB,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc &Desc = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](MCRegister SrcReg, MCRegister DstReg)
+  -> std::tuple {
+unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)

lukel97 wrote:

Ah ok, just wanted to check. I found it a bit hard to read but I'm not strongly 
opinionated

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits



@@ -146,16 +127,12 @@ body: |
 ; CHECK-NEXT: $v7 = VMV1R_V $v12
 ; CHECK-NEXT: $v8 = VMV1R_V $v13
 ; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-; CHECK-NEXT: $v9 = VMV1R_V $v13
-; CHECK-NEXT: $v10 = VMV1R_V $v14
-; CHECK-NEXT: $v18 = VMV1R_V $v14
-; CHECK-NEXT: $v17 = VMV1R_V $v13
-; CHECK-NEXT: $v16 = VMV1R_V $v12
-; CHECK-NEXT: $v15 = VMV1R_V $v11
-; CHECK-NEXT: $v14 = VMV1R_V $v10
+; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2
+; CHECK-NEXT: $v8 = VMV1R_V $v14

lukel97 wrote:

Shouldn't this be `$v10 = VMV1R_V $v14`?

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits



@@ -146,16 +127,12 @@ body: |
 ; CHECK-NEXT: $v7 = VMV1R_V $v12
 ; CHECK-NEXT: $v8 = VMV1R_V $v13
 ; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-; CHECK-NEXT: $v9 = VMV1R_V $v13
-; CHECK-NEXT: $v10 = VMV1R_V $v14
-; CHECK-NEXT: $v18 = VMV1R_V $v14
-; CHECK-NEXT: $v17 = VMV1R_V $v13
-; CHECK-NEXT: $v16 = VMV1R_V $v12
-; CHECK-NEXT: $v15 = VMV1R_V $v11
-; CHECK-NEXT: $v14 = VMV1R_V $v10
+; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2
+; CHECK-NEXT: $v8 = VMV1R_V $v14
+; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v12m2 = VMV2R_V $v8m2
+; CHECK-NEXT: $v8 = VMV1R_V $v4

lukel97 wrote:

And this should be like?
```
$v18 = VMV1R_V $v14
$v16 = VMV2R_V $v12m2
$v14 = VMV2R_V $v10m2
```

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)

2024-03-24 Thread Brad Smith via llvm-branch-commits


brad0 wrote:

@topperc 

https://github.com/llvm/llvm-project/pull/86424
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits



@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
   [RV32,  RV64],
   [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+  bit IsVRegClass = 0;
+  int VLMul = 1;
+  int NF = 1;

wangpc-pp wrote:

VLMul can't be 0 because `!logtwo(VLMul=0)` is illegal.
We use `bits<3>` to store `NF-1` (which is in range `[1, 7]`). NF is in range 
`[2, 8]`, but we will need 4 bits if we store its raw value. The default NF 
being 1 (NF-1==0) is a compromise, which is OK I think.
These fields are legal iff `IsVegClass` is true. 

https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits



@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
   [RV32,  RV64],
   [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+  bit IsVRegClass = 0;
+  int VLMul = 1;
+  int NF = 1;

wangpc-pp wrote:

And `NF=1` means no segment, I think it's obvious. :-)

https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Wang Pengcheng via llvm-branch-commits



@@ -146,16 +127,12 @@ body: |
 ; CHECK-NEXT: $v7 = VMV1R_V $v12
 ; CHECK-NEXT: $v8 = VMV1R_V $v13
 ; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-; CHECK-NEXT: $v9 = VMV1R_V $v13
-; CHECK-NEXT: $v10 = VMV1R_V $v14
-; CHECK-NEXT: $v18 = VMV1R_V $v14
-; CHECK-NEXT: $v17 = VMV1R_V $v13
-; CHECK-NEXT: $v16 = VMV1R_V $v12
-; CHECK-NEXT: $v15 = VMV1R_V $v11
-; CHECK-NEXT: $v14 = VMV1R_V $v10
+; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2
+; CHECK-NEXT: $v8 = VMV1R_V $v14
+; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v12m2 = VMV2R_V $v8m2
+; CHECK-NEXT: $v8 = VMV1R_V $v4

wangpc-pp wrote:

Thanks for catching this! Obviously, I used the wrong register number here. I 
will check.

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [flang] [flang][OpenMP] Support tasks' implicit firstprivate DSA (PR #85989)

[llvm-branch-commits] [llvm] release/18.x: [PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098) (PR #86375)

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

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