[llvm-branch-commits] [mlir] [mlir][Arith] `ValueBoundsOpInterface`: Support `arith.select` (PR #86383)
https://github.com/matthias-springer created
https://github.com/llvm/llvm-project/pull/86383
This commit adds a `ValueBoundsOpInterface` implementation for `arith.select`.
The implementation is almost identical to `scf.if` (#85895), but there is one
special case: if the condition is a shaped value, the selection is applied
element-wise and the result shape can be inferred from either operand.
>From 680d04d71e663aac51ea8f4dc4885d0bfd050b19 Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Sat, 23 Mar 2024 08:24:46 +
Subject: [PATCH] [mlir][Arith] `ValueBoundsOpInterface`: Support
`arith.select`
This commit adds a `ValueBoundsOpInterface` implementation for `arith.select`.
The implementation is almost identical to `scf.if` (#85895), but there is one
special case: if the condition is a shaped value, the selection is applied
element-wise and the result shape can be inferred from either operand.
---
.../Arith/IR/ValueBoundsOpInterfaceImpl.cpp | 70 +++
.../Arith/value-bounds-op-interface-impl.mlir | 31
2 files changed, 101 insertions(+)
diff --git a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
index 9c6b50e767ea26..bb7b9c939fcb09 100644
--- a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
+++ b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
@@ -66,6 +66,75 @@ struct MulIOpInterface
}
};
+struct SelectOpInterface
+: public ValueBoundsOpInterface::ExternalModel {
+
+ static void populateBounds(SelectOp selectOp, std::optional dim,
+ ValueBoundsConstraintSet &cstr) {
+Value value = selectOp.getResult();
+Value condition = selectOp.getCondition();
+Value trueValue = selectOp.getTrueValue();
+Value falseValue = selectOp.getFalseValue();
+
+if (isa(condition.getType())) {
+ // If the condition is a shaped type, the condition is applied
+ // element-wise. All three operands must have the same shape.
+ cstr.bound(value)[*dim] == cstr.getExpr(trueValue, dim);
+ cstr.bound(value)[*dim] == cstr.getExpr(falseValue, dim);
+ cstr.bound(value)[*dim] == cstr.getExpr(condition, dim);
+ return;
+}
+
+// Populate constraints for the true/false values (and all values on the
+// backward slice, as long as the current stop condition is not satisfied).
+cstr.populateConstraints(trueValue, dim);
+cstr.populateConstraints(falseValue, dim);
+auto boundsBuilder = cstr.bound(value);
+if (dim)
+ boundsBuilder[*dim];
+
+// Compare yielded values.
+// If trueValue <= falseValue:
+// * result <= falseValue
+// * result >= trueValue
+if (cstr.compare(trueValue, dim,
+ ValueBoundsConstraintSet::ComparisonOperator::LE,
+ falseValue, dim)) {
+ if (dim) {
+cstr.bound(value)[*dim] >= cstr.getExpr(trueValue, dim);
+cstr.bound(value)[*dim] <= cstr.getExpr(falseValue, dim);
+ } else {
+cstr.bound(value) >= trueValue;
+cstr.bound(value) <= falseValue;
+ }
+}
+// If falseValue <= trueValue:
+// * result <= trueValue
+// * result >= falseValue
+if (cstr.compare(falseValue, dim,
+ ValueBoundsConstraintSet::ComparisonOperator::LE,
+ trueValue, dim)) {
+ if (dim) {
+cstr.bound(value)[*dim] >= cstr.getExpr(falseValue, dim);
+cstr.bound(value)[*dim] <= cstr.getExpr(trueValue, dim);
+ } else {
+cstr.bound(value) >= falseValue;
+cstr.bound(value) <= trueValue;
+ }
+}
+ }
+
+ void populateBoundsForIndexValue(Operation *op, Value value,
+ ValueBoundsConstraintSet &cstr) const {
+populateBounds(cast(op), /*dim=*/std::nullopt, cstr);
+ }
+
+ void populateBoundsForShapedValueDim(Operation *op, Value value, int64_t dim,
+ ValueBoundsConstraintSet &cstr) const {
+populateBounds(cast(op), dim, cstr);
+ }
+};
} // namespace
} // namespace arith
} // namespace mlir
@@ -77,5 +146,6 @@ void
mlir::arith::registerValueBoundsOpInterfaceExternalModels(
arith::ConstantOp::attachInterface(*ctx);
arith::SubIOp::attachInterface(*ctx);
arith::MulIOp::attachInterface(*ctx);
+arith::SelectOp::attachInterface(*ctx);
});
}
diff --git a/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
b/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
index 83d5f1c9c9e86c..8fb3ba1a1eccef 100644
--- a/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
+++ b/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
@@ -74,3 +74,34 @@ func.func @arith_const() -> index {
%0 = "test.reify_bound"(%c5) : (index) -> (index)
return %0 : index
}
+
+// -
+
+// CHECK-LABEL: func @arith_select(
+func.func @arith_select(%c: i1) -> (index, index) {
+ // CHECK: arith.constant 5 : index
+
[llvm-branch-commits] [mlir] [mlir][Arith] `ValueBoundsOpInterface`: Support `arith.select` (PR #86383)
llvmbot wrote:
@llvm/pr-subscribers-mlir-arith
Author: Matthias Springer (matthias-springer)
Changes
This commit adds a `ValueBoundsOpInterface` implementation for `arith.select`.
The implementation is almost identical to `scf.if` (#85895), but there
is one special case: if the condition is a shaped value, the selection is
applied element-wise and the result shape can be inferred from either operand.
---
Full diff: https://github.com/llvm/llvm-project/pull/86383.diff
2 Files Affected:
- (modified) mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp (+70)
- (modified) mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir (+31)
``diff
diff --git a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
index 9c6b50e767ea26..bb7b9c939fcb09 100644
--- a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
+++ b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
@@ -66,6 +66,75 @@ struct MulIOpInterface
}
};
+struct SelectOpInterface
+: public ValueBoundsOpInterface::ExternalModel {
+
+ static void populateBounds(SelectOp selectOp, std::optional dim,
+ ValueBoundsConstraintSet &cstr) {
+Value value = selectOp.getResult();
+Value condition = selectOp.getCondition();
+Value trueValue = selectOp.getTrueValue();
+Value falseValue = selectOp.getFalseValue();
+
+if (isa(condition.getType())) {
+ // If the condition is a shaped type, the condition is applied
+ // element-wise. All three operands must have the same shape.
+ cstr.bound(value)[*dim] == cstr.getExpr(trueValue, dim);
+ cstr.bound(value)[*dim] == cstr.getExpr(falseValue, dim);
+ cstr.bound(value)[*dim] == cstr.getExpr(condition, dim);
+ return;
+}
+
+// Populate constraints for the true/false values (and all values on the
+// backward slice, as long as the current stop condition is not satisfied).
+cstr.populateConstraints(trueValue, dim);
+cstr.populateConstraints(falseValue, dim);
+auto boundsBuilder = cstr.bound(value);
+if (dim)
+ boundsBuilder[*dim];
+
+// Compare yielded values.
+// If trueValue <= falseValue:
+// * result <= falseValue
+// * result >= trueValue
+if (cstr.compare(trueValue, dim,
+ ValueBoundsConstraintSet::ComparisonOperator::LE,
+ falseValue, dim)) {
+ if (dim) {
+cstr.bound(value)[*dim] >= cstr.getExpr(trueValue, dim);
+cstr.bound(value)[*dim] <= cstr.getExpr(falseValue, dim);
+ } else {
+cstr.bound(value) >= trueValue;
+cstr.bound(value) <= falseValue;
+ }
+}
+// If falseValue <= trueValue:
+// * result <= trueValue
+// * result >= falseValue
+if (cstr.compare(falseValue, dim,
+ ValueBoundsConstraintSet::ComparisonOperator::LE,
+ trueValue, dim)) {
+ if (dim) {
+cstr.bound(value)[*dim] >= cstr.getExpr(falseValue, dim);
+cstr.bound(value)[*dim] <= cstr.getExpr(trueValue, dim);
+ } else {
+cstr.bound(value) >= falseValue;
+cstr.bound(value) <= trueValue;
+ }
+}
+ }
+
+ void populateBoundsForIndexValue(Operation *op, Value value,
+ ValueBoundsConstraintSet &cstr) const {
+populateBounds(cast(op), /*dim=*/std::nullopt, cstr);
+ }
+
+ void populateBoundsForShapedValueDim(Operation *op, Value value, int64_t dim,
+ ValueBoundsConstraintSet &cstr) const {
+populateBounds(cast(op), dim, cstr);
+ }
+};
} // namespace
} // namespace arith
} // namespace mlir
@@ -77,5 +146,6 @@ void
mlir::arith::registerValueBoundsOpInterfaceExternalModels(
arith::ConstantOp::attachInterface(*ctx);
arith::SubIOp::attachInterface(*ctx);
arith::MulIOp::attachInterface(*ctx);
+arith::SelectOp::attachInterface(*ctx);
});
}
diff --git a/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
b/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
index 83d5f1c9c9e86c..8fb3ba1a1eccef 100644
--- a/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
+++ b/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
@@ -74,3 +74,34 @@ func.func @arith_const() -> index {
%0 = "test.reify_bound"(%c5) : (index) -> (index)
return %0 : index
}
+
+// -
+
+// CHECK-LABEL: func @arith_select(
+func.func @arith_select(%c: i1) -> (index, index) {
+ // CHECK: arith.constant 5 : index
+ %c5 = arith.constant 5 : index
+ // CHECK: arith.constant 9 : index
+ %c9 = arith.constant 9 : index
+ %r = arith.select %c, %c5, %c9 : index
+ // CHECK: %[[c5:.*]] = arith.constant 5 : index
+ // CHECK: %[[c10:.*]] = arith.constant 10 : index
+ %0 = "test.reify_bound"(%r) {type = "LB"} : (index) -> (index)
+ %1 = "test.reify_bound"(%r) {type = "UB"} : (index) -> (index)
+ // CHECK: return %[[c5]], %[[c10]]
+
[llvm-branch-commits] [clang] release/18.x: backport PR84230 (PR #86106)
https://github.com/AaronBallman milestoned https://github.com/llvm/llvm-project/pull/86106 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [ARM] Update IsRestored for LR based on all returns (#82745) (PR #83129)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/83129
>From 6f8016fda7d56013a26d6f9bf2bd157aff4b13fa Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Fri, 23 Feb 2024 09:31:25 +
Subject: [PATCH 1/2] Pre-commit test showing bug #80287
This test shows the bug where LR is used as a general-purpose register
on a code path where it is not spilled to the stack.
(cherry picked from commit 8779cf68e80dcc0b15e8034f39e6ce18b08352b6)
---
llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll | 55 +++
1 file changed, 55 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
diff --git a/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
new file mode 100644
index 00..883a812139ded1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple thumbv7a-none-eabi < %s | FileCheck %s
+
+@val0 = global i32 0, align 4
+@val1 = global i32 0, align 4
+@val2 = global i32 0, align 4
+
+define i32 @foo(ptr %ctx) {
+; CHECK-LABEL: foo:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT:cbz r0, .LBB0_2
+; CHECK-NEXT: @ %bb.1: @ %if.end
+; CHECK-NEXT:movw r2, :lower16:val0
+; CHECK-NEXT:mov r1, r0
+; CHECK-NEXT:movs r0, #0
+; CHECK-NEXT:movw r12, :lower16:val2
+; CHECK-NEXT:movw r3, :lower16:val1
+; CHECK-NEXT:movt r2, :upper16:val0
+; CHECK-NEXT:add.w lr, r1, #4
+; CHECK-NEXT:movt r12, :upper16:val2
+; CHECK-NEXT:movt r3, :upper16:val1
+; CHECK-NEXT:stm.w lr, {r2, r3, r12}
+; CHECK-NEXT:str r0, [r1, #16]
+; CHECK-NEXT:bx lr
+; CHECK-NEXT: .LBB0_2: @ %if.then
+; CHECK-NEXT:.save {r7, lr}
+; CHECK-NEXT:push {r7, lr}
+; CHECK-NEXT:bl bar
+; CHECK-NEXT:mov.w r0, #-1
+; CHECK-NEXT:pop {r7, pc}
+entry:
+ %tobool.not = icmp eq ptr %ctx, null
+ br i1 %tobool.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() #2
+ br label %return
+
+if.end: ; preds = %entry
+ %cmd_a = getelementptr inbounds i8, ptr %ctx, i32 4
+ store ptr @val0, ptr %cmd_a, align 4
+ %cmd_b = getelementptr inbounds i8, ptr %ctx, i32 8
+ store ptr @val1, ptr %cmd_b, align 4
+ %cmd_c = getelementptr inbounds i8, ptr %ctx, i32 12
+ store ptr @val2, ptr %cmd_c, align 4
+ %cmd_d = getelementptr inbounds i8, ptr %ctx, i32 16
+ store ptr null, ptr %cmd_d, align 4
+ br label %return
+
+return: ; preds = %if.end, %if.then
+ %retval.0 = phi i32 [ 0, %if.end ], [ -1, %if.then ]
+ ret i32 %retval.0
+}
+
+declare void @bar()
>From 0e16af8e4cf3a66ad5d078d52744ae2776f9c4b2 Mon Sep 17 00:00:00 2001
From: ostannard
Date: Mon, 26 Feb 2024 12:23:25 +
Subject: [PATCH 2/2] [ARM] Update IsRestored for LR based on all returns
(#82745)
PR #75527 fixed ARMFrameLowering to set the IsRestored flag for LR based
on all of the return instructions in the function, not just one.
However, there is also code in ARMLoadStoreOptimizer which changes
return instructions, but it set IsRestored based on the one instruction
it changed, not the whole function.
The fix is to factor out the code added in #75527, and also call it from
ARMLoadStoreOptimizer if it made a change to return instructions.
Fixes #80287.
(cherry picked from commit 749384c08e042739342c88b521c8ba5dac1b9276)
---
llvm/lib/Target/ARM/ARMFrameLowering.cpp | 11 +
llvm/lib/Target/ARM/ARMFrameLowering.h| 4
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 23 ---
llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll | 11 +
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index eeb7f64aa5810e..9b54dd4e4e618d 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -2781,10 +2781,7 @@ void
ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
}
-void ARMFrameLowering::processFunctionBeforeFrameFinalized(
-MachineFunction &MF, RegScavenger *RS) const {
- TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
-
+void ARMFrameLowering::updateLRRestored(MachineFunction &MF) {
MachineFrameInfo &MFI = MF.getFrameInfo();
if (!MFI.isCalleeSavedInfoValid())
return;
@@ -2808,6 +2805,12 @@ void
ARMFrameLowering::processFunctionBeforeFrameFinalized(
}
}
+void ARMFrameLowering::processFunctionBeforeFrameFinalized(
+MachineFunction &MF, RegScavenger *RS) const {
+ TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
+ updateLRRestored(MF);
+}
+
void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF,
[llvm-branch-commits] [llvm] 0e16af8 - [ARM] Update IsRestored for LR based on all returns (#82745)
Author: ostannard
Date: 2024-03-23T15:34:54-07:00
New Revision: 0e16af8e4cf3a66ad5d078d52744ae2776f9c4b2
URL:
https://github.com/llvm/llvm-project/commit/0e16af8e4cf3a66ad5d078d52744ae2776f9c4b2
DIFF:
https://github.com/llvm/llvm-project/commit/0e16af8e4cf3a66ad5d078d52744ae2776f9c4b2.diff
LOG: [ARM] Update IsRestored for LR based on all returns (#82745)
PR #75527 fixed ARMFrameLowering to set the IsRestored flag for LR based
on all of the return instructions in the function, not just one.
However, there is also code in ARMLoadStoreOptimizer which changes
return instructions, but it set IsRestored based on the one instruction
it changed, not the whole function.
The fix is to factor out the code added in #75527, and also call it from
ARMLoadStoreOptimizer if it made a change to return instructions.
Fixes #80287.
(cherry picked from commit 749384c08e042739342c88b521c8ba5dac1b9276)
Added:
Modified:
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMFrameLowering.h
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
Removed:
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index eeb7f64aa5810e..9b54dd4e4e618d 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -2781,10 +2781,7 @@ void
ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
}
-void ARMFrameLowering::processFunctionBeforeFrameFinalized(
-MachineFunction &MF, RegScavenger *RS) const {
- TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
-
+void ARMFrameLowering::updateLRRestored(MachineFunction &MF) {
MachineFrameInfo &MFI = MF.getFrameInfo();
if (!MFI.isCalleeSavedInfoValid())
return;
@@ -2808,6 +2805,12 @@ void
ARMFrameLowering::processFunctionBeforeFrameFinalized(
}
}
+void ARMFrameLowering::processFunctionBeforeFrameFinalized(
+MachineFunction &MF, RegScavenger *RS) const {
+ TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
+ updateLRRestored(MF);
+}
+
void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF,
BitVector &SavedRegs) const {
TargetFrameLowering::getCalleeSaves(MF, SavedRegs);
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h
b/llvm/lib/Target/ARM/ARMFrameLowering.h
index 8d2b8beb9a58fb..3c7358d8cd53e2 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.h
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.h
@@ -59,6 +59,10 @@ class ARMFrameLowering : public TargetFrameLowering {
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS) const override;
+ /// Update the IsRestored flag on LR if it is spilled, based on the return
+ /// instructions.
+ static void updateLRRestored(MachineFunction &MF);
+
void processFunctionBeforeFrameFinalized(
MachineFunction &MF, RegScavenger *RS = nullptr) const override;
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index ed9d30c3c3ab90..6121055eb02176 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -2062,17 +2062,6 @@ bool
ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
MO.setReg(ARM::PC);
PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
MBB.erase(MBBI);
- // We now restore LR into PC so it is not live-out of the return block
- // anymore: Clear the CSI Restored bit.
- MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
- // CSI should be fixed after PrologEpilog Insertion
- assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid");
- for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
-if (Info.getReg() == ARM::LR) {
- Info.setRestored(false);
- break;
-}
- }
return true;
}
}
@@ -2120,14 +2109,22 @@ bool
ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
isThumb2 = AFI->isThumb2Function();
isThumb1 = AFI->isThumbFunction() && !isThumb2;
- bool Modified = false;
+ bool Modified = false, ModifiedLDMReturn = false;
for (MachineBasicBlock &MBB : Fn) {
Modified |= LoadStoreMultipleOpti(MBB);
if (STI->hasV5TOps() && !AFI->shouldSignReturnAddress())
- Modified |= MergeReturnIntoLDM(MBB);
+ ModifiedLDMReturn |= MergeReturnIntoLDM(MBB);
if (isThumb1)
Modified |= CombineMovBx(MBB);
}
+ Modified |= ModifiedLDMReturn;
+
+ // If we merged a BX instruction into an LDM, we need to re-calculate whether
+ // LR is restored. This check needs to consider the whole function, not just
+ // the instruction(s) we changed, because there may be other BX returns which
+ // still need LR
[llvm-branch-commits] [llvm] 6f8016f - Pre-commit test showing bug #80287
Author: Oliver Stannard
Date: 2024-03-23T15:34:54-07:00
New Revision: 6f8016fda7d56013a26d6f9bf2bd157aff4b13fa
URL:
https://github.com/llvm/llvm-project/commit/6f8016fda7d56013a26d6f9bf2bd157aff4b13fa
DIFF:
https://github.com/llvm/llvm-project/commit/6f8016fda7d56013a26d6f9bf2bd157aff4b13fa.diff
LOG: Pre-commit test showing bug #80287
This test shows the bug where LR is used as a general-purpose register
on a code path where it is not spilled to the stack.
(cherry picked from commit 8779cf68e80dcc0b15e8034f39e6ce18b08352b6)
Added:
llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
new file mode 100644
index 00..883a812139ded1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple thumbv7a-none-eabi < %s | FileCheck %s
+
+@val0 = global i32 0, align 4
+@val1 = global i32 0, align 4
+@val2 = global i32 0, align 4
+
+define i32 @foo(ptr %ctx) {
+; CHECK-LABEL: foo:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT:cbz r0, .LBB0_2
+; CHECK-NEXT: @ %bb.1: @ %if.end
+; CHECK-NEXT:movw r2, :lower16:val0
+; CHECK-NEXT:mov r1, r0
+; CHECK-NEXT:movs r0, #0
+; CHECK-NEXT:movw r12, :lower16:val2
+; CHECK-NEXT:movw r3, :lower16:val1
+; CHECK-NEXT:movt r2, :upper16:val0
+; CHECK-NEXT:add.w lr, r1, #4
+; CHECK-NEXT:movt r12, :upper16:val2
+; CHECK-NEXT:movt r3, :upper16:val1
+; CHECK-NEXT:stm.w lr, {r2, r3, r12}
+; CHECK-NEXT:str r0, [r1, #16]
+; CHECK-NEXT:bx lr
+; CHECK-NEXT: .LBB0_2: @ %if.then
+; CHECK-NEXT:.save {r7, lr}
+; CHECK-NEXT:push {r7, lr}
+; CHECK-NEXT:bl bar
+; CHECK-NEXT:mov.w r0, #-1
+; CHECK-NEXT:pop {r7, pc}
+entry:
+ %tobool.not = icmp eq ptr %ctx, null
+ br i1 %tobool.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() #2
+ br label %return
+
+if.end: ; preds = %entry
+ %cmd_a = getelementptr inbounds i8, ptr %ctx, i32 4
+ store ptr @val0, ptr %cmd_a, align 4
+ %cmd_b = getelementptr inbounds i8, ptr %ctx, i32 8
+ store ptr @val1, ptr %cmd_b, align 4
+ %cmd_c = getelementptr inbounds i8, ptr %ctx, i32 12
+ store ptr @val2, ptr %cmd_c, align 4
+ %cmd_d = getelementptr inbounds i8, ptr %ctx, i32 16
+ store ptr null, ptr %cmd_d, align 4
+ br label %return
+
+return: ; preds = %if.end, %if.then
+ %retval.0 = phi i32 [ 0, %if.end ], [ -1, %if.then ]
+ ret i32 %retval.0
+}
+
+declare void @bar()
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[llvm-branch-commits] [llvm] release/18.x: [ARM] Update IsRestored for LR based on all returns (#82745) (PR #83129)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/83129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SROA]: Only defer trying partial sized ptr or ptr vector types (PR #86114)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/86114
>From 368dc8553c5a9c1f8685ad399c353dd865b62d9b Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes
Date: Mon, 19 Feb 2024 12:59:13 -0800
Subject: [PATCH] [SROA]: Only defer trying partial sized ptr or ptr vector
types
Change-Id: Ic77f87290905addadd5819dff2d0c62f031022ab
(cherry picked from commit 1e828f838cc0f15074f3dbbb04929c06ef0c9729)
---
llvm/lib/Transforms/Scalar/SROA.cpp | 80 ---
llvm/test/Transforms/SROA/vector-promotion.ll | 62 ++
2 files changed, 115 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp
b/llvm/lib/Transforms/Scalar/SROA.cpp
index bdbaf4f55c96d0..17a94f9381bf8e 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -2257,6 +2257,41 @@ checkVectorTypesForPromotion(Partition &P, const
DataLayout &DL,
return nullptr;
}
+static VectorType *createAndCheckVectorTypesForPromotion(
+SetVector &OtherTys, ArrayRef CandidateTysCopy,
+function_ref CheckCandidateType, Partition &P,
+const DataLayout &DL, SmallVectorImpl &CandidateTys,
+bool &HaveCommonEltTy, Type *&CommonEltTy, bool &HaveVecPtrTy,
+bool &HaveCommonVecPtrTy, VectorType *&CommonVecPtrTy) {
+ [[maybe_unused]] VectorType *OriginalElt =
+ CandidateTysCopy.size() ? CandidateTysCopy[0] : nullptr;
+ // Consider additional vector types where the element type size is a
+ // multiple of load/store element size.
+ for (Type *Ty : OtherTys) {
+if (!VectorType::isValidElementType(Ty))
+ continue;
+unsigned TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue();
+// Make a copy of CandidateTys and iterate through it, because we
+// might append to CandidateTys in the loop.
+for (VectorType *const VTy : CandidateTysCopy) {
+ // The elements in the copy should remain invariant throughout the loop
+ assert(CandidateTysCopy[0] == OriginalElt && "Different Element");
+ unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue();
+ unsigned ElementSize =
+ DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue();
+ if (TypeSize != VectorSize && TypeSize != ElementSize &&
+ VectorSize % TypeSize == 0) {
+VectorType *NewVTy = VectorType::get(Ty, VectorSize / TypeSize, false);
+CheckCandidateType(NewVTy);
+ }
+}
+ }
+
+ return checkVectorTypesForPromotion(P, DL, CandidateTys, HaveCommonEltTy,
+ CommonEltTy, HaveVecPtrTy,
+ HaveCommonVecPtrTy, CommonVecPtrTy);
+}
+
/// Test whether the given alloca partitioning and range of slices can be
/// promoted to a vector.
///
@@ -2271,6 +2306,7 @@ static VectorType *isVectorPromotionViable(Partition &P,
const DataLayout &DL) {
// we have different element types.
SmallVector CandidateTys;
SetVector LoadStoreTys;
+ SetVector DeferredTys;
Type *CommonEltTy = nullptr;
VectorType *CommonVecPtrTy = nullptr;
bool HaveVecPtrTy = false;
@@ -2314,42 +2350,32 @@ static VectorType *isVectorPromotionViable(Partition
&P, const DataLayout &DL) {
Ty = SI->getValueOperand()->getType();
else
continue;
+
+auto CandTy = Ty->getScalarType();
+if (CandTy->isPointerTy() && (S.beginOffset() != P.beginOffset() ||
+ S.endOffset() != P.endOffset())) {
+ DeferredTys.insert(Ty);
+ continue;
+}
+
LoadStoreTys.insert(Ty);
// Consider any loads or stores that are the exact size of the slice.
if (S.beginOffset() == P.beginOffset() && S.endOffset() == P.endOffset())
CheckCandidateType(Ty);
}
- if (auto *VTy = checkVectorTypesForPromotion(
- P, DL, CandidateTys, HaveCommonEltTy, CommonEltTy, HaveVecPtrTy,
+ SmallVector CandidateTysCopy = CandidateTys;
+ if (auto *VTy = createAndCheckVectorTypesForPromotion(
+ LoadStoreTys, CandidateTysCopy, CheckCandidateType, P, DL,
+ CandidateTys, HaveCommonEltTy, CommonEltTy, HaveVecPtrTy,
HaveCommonVecPtrTy, CommonVecPtrTy))
return VTy;
- // Consider additional vector types where the element type size is a
- // multiple of load/store element size.
- for (Type *Ty : LoadStoreTys) {
-if (!VectorType::isValidElementType(Ty))
- continue;
-unsigned TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue();
-// Make a copy of CandidateTys and iterate through it, because we might
-// append to CandidateTys in the loop.
-SmallVector CandidateTysCopy = CandidateTys;
-CandidateTys.clear();
-for (VectorType *&VTy : CandidateTysCopy) {
- unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue();
- unsigned ElementSize =
- DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue();
- if (TypeSize != VectorSize && TypeSize != ElementSize &&
- VectorSize % TypeSize == 0) {
-VectorType
[llvm-branch-commits] [llvm] release/18.x: [SROA]: Only defer trying partial sized ptr or ptr vector types (PR #86114)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/86114 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 368dc85 - [SROA]: Only defer trying partial sized ptr or ptr vector types
Author: Jeffrey Byrnes
Date: 2024-03-23T15:39:23-07:00
New Revision: 368dc8553c5a9c1f8685ad399c353dd865b62d9b
URL:
https://github.com/llvm/llvm-project/commit/368dc8553c5a9c1f8685ad399c353dd865b62d9b
DIFF:
https://github.com/llvm/llvm-project/commit/368dc8553c5a9c1f8685ad399c353dd865b62d9b.diff
LOG: [SROA]: Only defer trying partial sized ptr or ptr vector types
Change-Id: Ic77f87290905addadd5819dff2d0c62f031022ab
(cherry picked from commit 1e828f838cc0f15074f3dbbb04929c06ef0c9729)
Added:
Modified:
llvm/lib/Transforms/Scalar/SROA.cpp
llvm/test/Transforms/SROA/vector-promotion.ll
Removed:
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp
b/llvm/lib/Transforms/Scalar/SROA.cpp
index bdbaf4f55c96d0..17a94f9381bf8e 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -2257,6 +2257,41 @@ checkVectorTypesForPromotion(Partition &P, const
DataLayout &DL,
return nullptr;
}
+static VectorType *createAndCheckVectorTypesForPromotion(
+SetVector &OtherTys, ArrayRef CandidateTysCopy,
+function_ref CheckCandidateType, Partition &P,
+const DataLayout &DL, SmallVectorImpl &CandidateTys,
+bool &HaveCommonEltTy, Type *&CommonEltTy, bool &HaveVecPtrTy,
+bool &HaveCommonVecPtrTy, VectorType *&CommonVecPtrTy) {
+ [[maybe_unused]] VectorType *OriginalElt =
+ CandidateTysCopy.size() ? CandidateTysCopy[0] : nullptr;
+ // Consider additional vector types where the element type size is a
+ // multiple of load/store element size.
+ for (Type *Ty : OtherTys) {
+if (!VectorType::isValidElementType(Ty))
+ continue;
+unsigned TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue();
+// Make a copy of CandidateTys and iterate through it, because we
+// might append to CandidateTys in the loop.
+for (VectorType *const VTy : CandidateTysCopy) {
+ // The elements in the copy should remain invariant throughout the loop
+ assert(CandidateTysCopy[0] == OriginalElt && "Different Element");
+ unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue();
+ unsigned ElementSize =
+ DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue();
+ if (TypeSize != VectorSize && TypeSize != ElementSize &&
+ VectorSize % TypeSize == 0) {
+VectorType *NewVTy = VectorType::get(Ty, VectorSize / TypeSize, false);
+CheckCandidateType(NewVTy);
+ }
+}
+ }
+
+ return checkVectorTypesForPromotion(P, DL, CandidateTys, HaveCommonEltTy,
+ CommonEltTy, HaveVecPtrTy,
+ HaveCommonVecPtrTy, CommonVecPtrTy);
+}
+
/// Test whether the given alloca partitioning and range of slices can be
/// promoted to a vector.
///
@@ -2271,6 +2306,7 @@ static VectorType *isVectorPromotionViable(Partition &P,
const DataLayout &DL) {
// we have
diff erent element types.
SmallVector CandidateTys;
SetVector LoadStoreTys;
+ SetVector DeferredTys;
Type *CommonEltTy = nullptr;
VectorType *CommonVecPtrTy = nullptr;
bool HaveVecPtrTy = false;
@@ -2314,42 +2350,32 @@ static VectorType *isVectorPromotionViable(Partition
&P, const DataLayout &DL) {
Ty = SI->getValueOperand()->getType();
else
continue;
+
+auto CandTy = Ty->getScalarType();
+if (CandTy->isPointerTy() && (S.beginOffset() != P.beginOffset() ||
+ S.endOffset() != P.endOffset())) {
+ DeferredTys.insert(Ty);
+ continue;
+}
+
LoadStoreTys.insert(Ty);
// Consider any loads or stores that are the exact size of the slice.
if (S.beginOffset() == P.beginOffset() && S.endOffset() == P.endOffset())
CheckCandidateType(Ty);
}
- if (auto *VTy = checkVectorTypesForPromotion(
- P, DL, CandidateTys, HaveCommonEltTy, CommonEltTy, HaveVecPtrTy,
+ SmallVector CandidateTysCopy = CandidateTys;
+ if (auto *VTy = createAndCheckVectorTypesForPromotion(
+ LoadStoreTys, CandidateTysCopy, CheckCandidateType, P, DL,
+ CandidateTys, HaveCommonEltTy, CommonEltTy, HaveVecPtrTy,
HaveCommonVecPtrTy, CommonVecPtrTy))
return VTy;
- // Consider additional vector types where the element type size is a
- // multiple of load/store element size.
- for (Type *Ty : LoadStoreTys) {
-if (!VectorType::isValidElementType(Ty))
- continue;
-unsigned TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue();
-// Make a copy of CandidateTys and iterate through it, because we might
-// append to CandidateTys in the loop.
-SmallVector CandidateTysCopy = CandidateTys;
-CandidateTys.clear();
-for (VectorType *&VTy : CandidateTysCopy) {
- unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue();
- unsigned ElementSize =
- DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue();
- if (TypeSize != VectorSize
[llvm-branch-commits] [libcxx] release/18.x: Reapply [libcxx] [modules] Fix relative paths with absolute LIBCXX_INSTALL_MODULES_DIR (#86020) (PR #86197)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/86197
>From 6fd34566b6766c364bbfc75de77c444ae492c624 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Storsj=C3=B6?=
Date: Thu, 21 Mar 2024 17:29:15 +0200
Subject: [PATCH] Reapply [libcxx] [modules] Fix relative paths with absolute
LIBCXX_INSTALL_MODULES_DIR (#86020)
This reapplies 272d1b44efdedb68c194970a610f0ca1b7b769c5 (from #85756),
which was reverted in
407937036fa7640f61f225474b1ea6623a40dbdd.
In the previous attempt, empty CMAKE_INSTALL_PREFIX was handled by
quoting them, in d209d1340b99d4fbd325dffb5e13b757ab8264ea. That made the
calls to cmake_path(ABSOLUTE_PATH) succeed, but the output paths of that
weren't actually absolute, which was required by file(RELATIVE_PATH).
Avoid this issue by constructing a non-empty base directory variable
to use for calculating the relative path.
(cherry picked from commit 50801f1095d33e712c3a51fdeef82569bd09007f)
---
libcxx/modules/CMakeLists.txt | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/libcxx/modules/CMakeLists.txt b/libcxx/modules/CMakeLists.txt
index 0dea8cfca94ac3..d47d19a4755317 100644
--- a/libcxx/modules/CMakeLists.txt
+++ b/libcxx/modules/CMakeLists.txt
@@ -206,9 +206,20 @@ add_custom_target(generate-cxx-modules
# Configure the modules manifest.
# Use the relative path between the installation and the module in the json
# file. This allows moving the entire installation to a different location.
+if("${CMAKE_INSTALL_PREFIX}" STREQUAL "")
+ set(BASE_DIRECTORY "/")
+else()
+ set(BASE_DIRECTORY ${CMAKE_INSTALL_PREFIX})
+endif()
+cmake_path(ABSOLUTE_PATH LIBCXX_INSTALL_LIBRARY_DIR
+ BASE_DIRECTORY ${BASE_DIRECTORY}
+ OUTPUT_VARIABLE ABS_LIBRARY_DIR)
+cmake_path(ABSOLUTE_PATH LIBCXX_INSTALL_MODULES_DIR
+ BASE_DIRECTORY ${BASE_DIRECTORY}
+ OUTPUT_VARIABLE ABS_MODULES_DIR)
file(RELATIVE_PATH LIBCXX_MODULE_RELATIVE_PATH
- ${CMAKE_INSTALL_PREFIX}/${LIBCXX_INSTALL_LIBRARY_DIR}
- ${CMAKE_INSTALL_PREFIX}/${LIBCXX_INSTALL_MODULES_DIR})
+ ${ABS_LIBRARY_DIR}
+ ${ABS_MODULES_DIR})
configure_file(
"modules.json.in"
"${LIBCXX_LIBRARY_DIR}/libc++.modules.json"
___
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[llvm-branch-commits] [compiler-rt] release/18.x: [msan] Re-exec with no ASLR if memory layout is incompatible on Linux (#85142) (PR #86201)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/86201
>From 3f231bcec9bda977d6fca08bc754a4358de6716a Mon Sep 17 00:00:00 2001
From: Thurston Dang
Date: Thu, 14 Mar 2024 16:19:30 -0700
Subject: [PATCH 1/2] [msan] Add 'MappingDesc::ALLOCATOR' type and check it is
available (#85153)
MSan divides the virtual address space into APP, INVALID, SHADOW and
ORIGIN memory. The allocator usually just steals a bit of the APP
address space: typically the bottom portion of the PIE binaries section,
which works because the Linux kernel maps from the top of the PIE
binaries section. However, if ASLR is very aggressive, the binary may
end up mapped in the same location where the allocator wants to live;
this results in a segfault.
This patch adds in a MappingDesc::ALLOCATOR type and enforces that the
memory range for the allocator is not occupied by anything else.
Since the allocator range information is not readily available in
msan.h, we duplicate the information from msan_allocator.cpp.
Note: aggressive ASLR can also lead to a different type of failure,
where the PIE binaries/libraries are mapped entirely outside of the
APP/ALLOCATOR sections; that will be addressed in a separate patch
(https://github.com/llvm/llvm-project/pull/85142).
(cherry picked from commit af2bf86a372cacf5f536bae06e2f2d3886eefb7b)
---
compiler-rt/lib/msan/msan.h | 33 +
compiler-rt/lib/msan/msan_allocator.cpp | 3 +++
compiler-rt/lib/msan/msan_linux.cpp | 11 ++---
3 files changed, 34 insertions(+), 13 deletions(-)
diff --git a/compiler-rt/lib/msan/msan.h b/compiler-rt/lib/msan/msan.h
index 710447a3e1a357..00f448fb377d59 100644
--- a/compiler-rt/lib/msan/msan.h
+++ b/compiler-rt/lib/msan/msan.h
@@ -33,12 +33,18 @@ struct MappingDesc {
uptr start;
uptr end;
enum Type {
-INVALID, APP, SHADOW, ORIGIN
+INVALID = 1,
+ALLOCATOR = 2,
+APP = 4,
+SHADOW = 8,
+ORIGIN = 16,
} type;
const char *name;
};
-
+// Note: MappingDesc::ALLOCATOR entries are only used to check for memory
+// layout compatibility. The actual allocation settings are in
+// msan_allocator.cpp, which need to be kept in sync.
#if SANITIZER_LINUX && defined(__mips64)
// MIPS64 maps:
@@ -84,7 +90,8 @@ const MappingDesc kMemoryLayout[] = {
{0X0B000, 0X0C000, MappingDesc::SHADOW, "shadow-10-13"},
{0X0C000, 0X0D000, MappingDesc::INVALID, "invalid"},
{0X0D000, 0X0E000, MappingDesc::ORIGIN, "origin-10-13"},
-{0X0E000, 0X1, MappingDesc::APP, "app-15"},
+{0x0E000, 0x0E400, MappingDesc::ALLOCATOR, "allocator"},
+{0X0E400, 0X1, MappingDesc::APP, "app-15"},
};
# define MEM_TO_SHADOW(mem) ((uptr)mem ^ 0xB000ULL)
# define SHADOW_TO_ORIGIN(shadow) (((uptr)(shadow)) + 0x2000ULL)
@@ -106,7 +113,8 @@ const MappingDesc kMemoryLayout[] = {
{0x5100ULL, 0x6000ULL, MappingDesc::APP, "app-2"},
{0x6000ULL, 0x6100ULL, MappingDesc::ORIGIN, "origin-1"},
{0x6100ULL, 0x7000ULL, MappingDesc::INVALID, "invalid"},
-{0x7000ULL, 0x8000ULL, MappingDesc::APP, "app-3"}};
+{0x7000ULL, 0x7400ULL, MappingDesc::ALLOCATOR,
"allocator"},
+{0x7400ULL, 0x8000ULL, MappingDesc::APP, "app-3"}};
# define MEM_TO_SHADOW(mem) (((uptr)(mem)) ^ 0x5000ULL)
# define SHADOW_TO_ORIGIN(shadow) (((uptr)(shadow)) + 0x1000ULL)
@@ -118,7 +126,8 @@ const MappingDesc kMemoryLayout[] = {
{0x1802ULL, 0x1C00ULL, MappingDesc::INVALID, "invalid"},
{0x1C00ULL, 0x2C02ULL, MappingDesc::ORIGIN, "origin"},
{0x2C02ULL, 0x3000ULL, MappingDesc::INVALID, "invalid"},
-{0x3000ULL, 0x8000ULL, MappingDesc::APP, "high memory"}};
+{0x3000ULL, 0x3200ULL, MappingDesc::ALLOCATOR,
"allocator"},
+{0x3200ULL, 0x8000ULL, MappingDesc::APP, "high memory"}};
// Various kernels use different low end ranges but we can combine them into
one
// big range. They also use different high end ranges but we can map them all
to
@@ -141,7 +150,8 @@ const MappingDesc kMemoryLayout[] = {
{0x1800ULL, 0x1C00ULL, MappingDesc::INVALID, "invalid"},
{0x1C00ULL, 0x2C00ULL, MappingDesc::ORIGIN, "origin"},
{0x2C00ULL, 0x4400ULL, MappingDesc::INVALID, "invalid"},
-{0x4400ULL, 0x5000ULL, MappingDesc::APP, "high memory"}};
+{0x4400ULL, 0x4600ULL, MappingDesc::ALLOCATOR,
"allocator"},
+{0x4600ULL, 0x5000ULL, MappingDesc::APP, "high memory"}};
#define MEM_TO_SHADOW(mem) \
uptr)(mem)) & ~0xC000ULL) + 0x0800ULL)
@@ -208,7 +218,8 @@ const MappingDesc kMemoryLayout[] = {
{0x5100ULL, 0x6000ULL, Mapping
[llvm-branch-commits] [BOLT] Emit intra-function control flow in YAMLBAT (PR #76911)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/76911 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Emit intra-function control flow in YAMLBAT (PR #76911)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/76911 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Add secondary entry points to BAT (PR #86218)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/86218 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [BOLT] Add secondary entry points to BAT (PR #86218)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/86218 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Add secondary entry points to BAT (PR #86218)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/86218 >From 6bc606b39044876a883aebc68fc5bbc8699094c5 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Sat, 23 Mar 2024 16:36:36 -0700 Subject: [PATCH] Fix test Created using spr 1.3.4 --- bolt/test/X86/bolt-address-translation-yaml.test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bolt/test/X86/bolt-address-translation-yaml.test b/bolt/test/X86/bolt-address-translation-yaml.test index be3bcb2a0c6dd1..306050a1c97e2b 100644 --- a/bolt/test/X86/bolt-address-translation-yaml.test +++ b/bolt/test/X86/bolt-address-translation-yaml.test @@ -18,7 +18,7 @@ RUN: | FileCheck --check-prefix CHECK-BOLT-YAML %s WRITE-BAT-CHECK: BOLT-INFO: Wrote 5 BAT maps WRITE-BAT-CHECK: BOLT-INFO: Wrote 4 function and 22 basic block hashes -WRITE-BAT-CHECK: BOLT-INFO: BAT section size (bytes): 380 +WRITE-BAT-CHECK: BOLT-INFO: BAT section size (bytes): 384 READ-BAT-CHECK-NOT: BOLT-ERROR: unable to save profile in YAML format for input file processed by BOLT READ-BAT-CHECK: BOLT-INFO: Parsed 5 BAT entries ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Assume no-op addrspacecasts by default (#82332) (PR #86372)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/86372
>From 2498e3a07f3df2272fec885f53f09ae13214ca38 Mon Sep 17 00:00:00 2001
From: hev
Date: Wed, 21 Feb 2024 21:15:17 +0800
Subject: [PATCH] [LoongArch] Assume no-op addrspacecasts by default (#82332)
This PR indicates that `addrspacecasts` are always no-ops on LoongArch.
Fixes #82330
(cherry picked from commit dd3e0a4643670f33850278ad281a358bbdd04e92)
---
.../Target/LoongArch/LoongArchTargetMachine.h | 5 ++
llvm/test/CodeGen/LoongArch/addrspacecast.ll | 47 +++
2 files changed, 52 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/addrspacecast.ll
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index 7d39d47e86b363..fa9bc7608e7d2c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -45,6 +45,11 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
MachineFunctionInfo *
createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
const TargetSubtargetInfo *STI) const override;
+
+ // Addrspacecasts are always noops.
+ bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+return true;
+ }
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/LoongArch/addrspacecast.ll
b/llvm/test/CodeGen/LoongArch/addrspacecast.ll
new file mode 100644
index 00..7875562331be09
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/addrspacecast.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
--check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
--check-prefix=LA64
+
+define void @cast0(ptr addrspace(1) %ptr) {
+; LA32-LABEL: cast0:
+; LA32: # %bb.0:
+; LA32-NEXT:st.w $zero, $a0, 0
+; LA32-NEXT:ret
+;
+; LA64-LABEL: cast0:
+; LA64: # %bb.0:
+; LA64-NEXT:st.w $zero, $a0, 0
+; LA64-NEXT:ret
+ %ptr0 = addrspacecast ptr addrspace(1) %ptr to ptr addrspace(0)
+ store i32 0, ptr %ptr0
+ ret void
+}
+
+define void @cast1(ptr %ptr) {
+; LA32-LABEL: cast1:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:bl %plt(foo)
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: cast1:
+; LA64: # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:.cfi_def_cfa_offset 16
+; LA64-NEXT:st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:.cfi_offset 1, -8
+; LA64-NEXT:bl %plt(foo)
+; LA64-NEXT:ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+ %castptr = addrspacecast ptr %ptr to ptr addrspace(10)
+ call void @foo(ptr addrspace(10) %castptr)
+ ret void
+}
+
+declare void @foo(ptr addrspace(10))
___
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[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Assume no-op addrspacecasts by default (#82332) (PR #86372)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/86372 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 2498e3a - [LoongArch] Assume no-op addrspacecasts by default (#82332)
Author: hev
Date: 2024-03-23T18:44:31-07:00
New Revision: 2498e3a07f3df2272fec885f53f09ae13214ca38
URL:
https://github.com/llvm/llvm-project/commit/2498e3a07f3df2272fec885f53f09ae13214ca38
DIFF:
https://github.com/llvm/llvm-project/commit/2498e3a07f3df2272fec885f53f09ae13214ca38.diff
LOG: [LoongArch] Assume no-op addrspacecasts by default (#82332)
This PR indicates that `addrspacecasts` are always no-ops on LoongArch.
Fixes #82330
(cherry picked from commit dd3e0a4643670f33850278ad281a358bbdd04e92)
Added:
llvm/test/CodeGen/LoongArch/addrspacecast.ll
Modified:
llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
Removed:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index 7d39d47e86b363..fa9bc7608e7d2c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -45,6 +45,11 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
MachineFunctionInfo *
createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
const TargetSubtargetInfo *STI) const override;
+
+ // Addrspacecasts are always noops.
+ bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+return true;
+ }
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/LoongArch/addrspacecast.ll
b/llvm/test/CodeGen/LoongArch/addrspacecast.ll
new file mode 100644
index 00..7875562331be09
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/addrspacecast.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
--check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
--check-prefix=LA64
+
+define void @cast0(ptr addrspace(1) %ptr) {
+; LA32-LABEL: cast0:
+; LA32: # %bb.0:
+; LA32-NEXT:st.w $zero, $a0, 0
+; LA32-NEXT:ret
+;
+; LA64-LABEL: cast0:
+; LA64: # %bb.0:
+; LA64-NEXT:st.w $zero, $a0, 0
+; LA64-NEXT:ret
+ %ptr0 = addrspacecast ptr addrspace(1) %ptr to ptr addrspace(0)
+ store i32 0, ptr %ptr0
+ ret void
+}
+
+define void @cast1(ptr %ptr) {
+; LA32-LABEL: cast1:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:bl %plt(foo)
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: cast1:
+; LA64: # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:.cfi_def_cfa_offset 16
+; LA64-NEXT:st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:.cfi_offset 1, -8
+; LA64-NEXT:bl %plt(foo)
+; LA64-NEXT:ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+ %castptr = addrspacecast ptr %ptr to ptr addrspace(10)
+ call void @foo(ptr addrspace(10) %castptr)
+ ret void
+}
+
+declare void @foo(ptr addrspace(10))
___
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[llvm-branch-commits] [llvm] [BOLT] Add secondary entry points to BAT (PR #86218)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/86218 >From 6bc606b39044876a883aebc68fc5bbc8699094c5 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Sat, 23 Mar 2024 16:36:36 -0700 Subject: [PATCH] Fix test Created using spr 1.3.4 --- bolt/test/X86/bolt-address-translation-yaml.test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bolt/test/X86/bolt-address-translation-yaml.test b/bolt/test/X86/bolt-address-translation-yaml.test index be3bcb2a0c6dd1..306050a1c97e2b 100644 --- a/bolt/test/X86/bolt-address-translation-yaml.test +++ b/bolt/test/X86/bolt-address-translation-yaml.test @@ -18,7 +18,7 @@ RUN: | FileCheck --check-prefix CHECK-BOLT-YAML %s WRITE-BAT-CHECK: BOLT-INFO: Wrote 5 BAT maps WRITE-BAT-CHECK: BOLT-INFO: Wrote 4 function and 22 basic block hashes -WRITE-BAT-CHECK: BOLT-INFO: BAT section size (bytes): 380 +WRITE-BAT-CHECK: BOLT-INFO: BAT section size (bytes): 384 READ-BAT-CHECK-NOT: BOLT-ERROR: unable to save profile in YAML format for input file processed by BOLT READ-BAT-CHECK: BOLT-INFO: Parsed 5 BAT entries ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Add secondary entry points to BAT (PR #86218)
https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/86218 >From 6bc606b39044876a883aebc68fc5bbc8699094c5 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Sat, 23 Mar 2024 16:36:36 -0700 Subject: [PATCH] Fix test Created using spr 1.3.4 --- bolt/test/X86/bolt-address-translation-yaml.test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bolt/test/X86/bolt-address-translation-yaml.test b/bolt/test/X86/bolt-address-translation-yaml.test index be3bcb2a0c6dd1..306050a1c97e2b 100644 --- a/bolt/test/X86/bolt-address-translation-yaml.test +++ b/bolt/test/X86/bolt-address-translation-yaml.test @@ -18,7 +18,7 @@ RUN: | FileCheck --check-prefix CHECK-BOLT-YAML %s WRITE-BAT-CHECK: BOLT-INFO: Wrote 5 BAT maps WRITE-BAT-CHECK: BOLT-INFO: Wrote 4 function and 22 basic block hashes -WRITE-BAT-CHECK: BOLT-INFO: BAT section size (bytes): 380 +WRITE-BAT-CHECK: BOLT-INFO: BAT section size (bytes): 384 READ-BAT-CHECK-NOT: BOLT-ERROR: unable to save profile in YAML format for input file processed by BOLT READ-BAT-CHECK: BOLT-INFO: Parsed 5 BAT entries ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)
https://github.com/brad0 closed https://github.com/llvm/llvm-project/pull/84566 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/86424 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)
llvmbot wrote: @topperc @topperc What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/86424 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/86424
Backport 755b439694432d4f68e20e979b479cbc30602bb1
5d7fd6a04a6748936dece9d90481b2ba4ec97e53
Requested by: @brad0
>From 27130993eeca747b72e19ce500a38d6d8067362a Mon Sep 17 00:00:00 2001
From: yingopq <115543042+ying...@users.noreply.github.com>
Date: Sat, 9 Mar 2024 04:41:31 +0800
Subject: [PATCH 1/2] [Mips] Fix missing sign extension in expansion of
sub-word atomic max (#77072)
Add sign extension "SEB/SEH" before compare.
Fix #61881
(cherry picked from commit 755b439694432d4f68e20e979b479cbc30602bb1)
---
llvm/lib/Target/Mips/MipsExpandPseudo.cpp | 51 +-
llvm/test/CodeGen/Mips/atomic-min-max.ll | 655 ++
2 files changed, 577 insertions(+), 129 deletions(-)
diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index 2c2554b5b4bc3b..bded59439a736a 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -388,18 +388,32 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
Opcode = Mips::XOR;
break;
case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA:
+IsUnsigned = true;
+IsMin = true;
+break;
case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA:
IsUnsigned = true;
-[[fallthrough]];
+IsMin = true;
+break;
case Mips::ATOMIC_LOAD_MIN_I8_POSTRA:
+SEOp = Mips::SEB;
+IsMin = true;
+break;
case Mips::ATOMIC_LOAD_MIN_I16_POSTRA:
IsMin = true;
break;
case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA:
+IsUnsigned = true;
+IsMax = true;
+break;
case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA:
IsUnsigned = true;
-[[fallthrough]];
+IsMax = true;
+break;
case Mips::ATOMIC_LOAD_MAX_I8_POSTRA:
+SEOp = Mips::SEB;
+IsMax = true;
+break;
case Mips::ATOMIC_LOAD_MAX_I16_POSTRA:
IsMax = true;
break;
@@ -461,14 +475,33 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
// For little endian we need to clear uninterested bits.
if (STI->isLittle()) {
- // and OldVal, OldVal, Mask
- // and Incr, Incr, Mask
- BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal)
- .addReg(OldVal)
- .addReg(Mask);
- BuildMI(loopMBB, DL, TII->get(Mips::AND),
Incr).addReg(Incr).addReg(Mask);
+ if (!IsUnsigned) {
+BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal)
+.addReg(OldVal)
+.addReg(ShiftAmnt);
+BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr)
+.addReg(Incr)
+.addReg(ShiftAmnt);
+if (STI->hasMips32r2()) {
+ BuildMI(loopMBB, DL, TII->get(SEOp), OldVal).addReg(OldVal);
+ BuildMI(loopMBB, DL, TII->get(SEOp), Incr).addReg(Incr);
+} else {
+ const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
+ BuildMI(loopMBB, DL, TII->get(Mips::SLL), OldVal)
+ .addReg(OldVal, RegState::Kill)
+ .addImm(ShiftImm);
+ BuildMI(loopMBB, DL, TII->get(Mips::SRA), OldVal)
+ .addReg(OldVal, RegState::Kill)
+ .addImm(ShiftImm);
+ BuildMI(loopMBB, DL, TII->get(Mips::SLL), Incr)
+ .addReg(Incr, RegState::Kill)
+ .addImm(ShiftImm);
+ BuildMI(loopMBB, DL, TII->get(Mips::SRA), Incr)
+ .addReg(Incr, RegState::Kill)
+ .addImm(ShiftImm);
+}
+ }
}
-
// unsigned: sltu Scratch4, oldVal, Incr
// signed: slt Scratch4, oldVal, Incr
BuildMI(loopMBB, DL, TII->get(SLTScratch4), Scratch4)
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll
b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index f953c885ea7345..bc3643f3947a40 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -3,6 +3,7 @@
; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - |
FileCheck %s --check-prefix=MIPSR6
; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips
-verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips
-verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6
+; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - |
FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - |
FileCheck %s --check-prefix=MIPSEL
; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - |
FileCheck %s --check-prefix=MIPSELR6
; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips
-verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL
@@ -77,6 +78,23 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext
%val) {
; MMR6-NEXT:sync
; MMR6-NEXT:jrc $ra
;
+; MIPS32-LABEL: test_max_32:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT:sync
+; MIPS32-NEXT: $BB0_1: # %entry
+; MIPS32-NEXT:# =>This Inner Loop Header: Depth=1
+; MIPS32-NEXT:
