[llvm-branch-commits] [clang] release/18.x: [clang][CodeGen] Keep processing the rest of AST after encountering unsupported MC/DC expressions (#82464) (PR #82866)
https://github.com/evodius96 approved this pull request. This should also be on 18.x https://github.com/llvm/llvm-project/pull/82866 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 12573c7 - Revert "[llvm-ar] Use COFF archive format for COFF targets. (#82642)"
Author: Jacek Caban
Date: 2024-02-24T17:41:21+01:00
New Revision: 12573c717e2e4b7c8cafe008b8fff8922295fe4a
URL:
https://github.com/llvm/llvm-project/commit/12573c717e2e4b7c8cafe008b8fff8922295fe4a
DIFF:
https://github.com/llvm/llvm-project/commit/12573c717e2e4b7c8cafe008b8fff8922295fe4a.diff
LOG: Revert "[llvm-ar] Use COFF archive format for COFF targets. (#82642)"
This reverts commit cf9201cfdbc10f4606fc4ca22bf1ccaf5ee841b3.
Added:
Modified:
llvm/include/llvm/Object/Archive.h
llvm/lib/Object/Archive.cpp
llvm/lib/Object/ArchiveWriter.cpp
llvm/tools/llvm-ar/llvm-ar.cpp
Removed:
llvm/test/tools/llvm-ar/coff-symtab.test
diff --git a/llvm/include/llvm/Object/Archive.h
b/llvm/include/llvm/Object/Archive.h
index 66f07939b11050..3dd99a46507a24 100644
--- a/llvm/include/llvm/Object/Archive.h
+++ b/llvm/include/llvm/Object/Archive.h
@@ -339,7 +339,6 @@ class Archive : public Binary {
Kind kind() const { return (Kind)Format; }
bool isThin() const { return IsThin; }
static object::Archive::Kind getDefaultKindForHost();
- static object::Archive::Kind getDefaultKindForTriple(Triple &T);
child_iterator child_begin(Error &Err, bool SkipInternal = true) const;
child_iterator child_end() const;
diff --git a/llvm/lib/Object/Archive.cpp b/llvm/lib/Object/Archive.cpp
index d3fdcd9ee88111..e447e5b23316f1 100644
--- a/llvm/lib/Object/Archive.cpp
+++ b/llvm/lib/Object/Archive.cpp
@@ -969,19 +969,12 @@ Archive::Archive(MemoryBufferRef Source, Error &Err)
Err = Error::success();
}
-object::Archive::Kind Archive::getDefaultKindForTriple(Triple &T) {
- if (T.isOSDarwin())
-return object::Archive::K_DARWIN;
- if (T.isOSAIX())
-return object::Archive::K_AIXBIG;
- if (T.isOSWindows())
-return object::Archive::K_COFF;
- return object::Archive::K_GNU;
-}
-
object::Archive::Kind Archive::getDefaultKindForHost() {
Triple HostTriple(sys::getProcessTriple());
- return getDefaultKindForTriple(HostTriple);
+ return HostTriple.isOSDarwin()
+ ? object::Archive::K_DARWIN
+ : (HostTriple.isOSAIX() ? object::Archive::K_AIXBIG
+ : object::Archive::K_GNU);
}
Archive::child_iterator Archive::child_begin(Error &Err,
diff --git a/llvm/lib/Object/ArchiveWriter.cpp
b/llvm/lib/Object/ArchiveWriter.cpp
index 02f72521c8b544..155926a8c5949d 100644
--- a/llvm/lib/Object/ArchiveWriter.cpp
+++ b/llvm/lib/Object/ArchiveWriter.cpp
@@ -62,16 +62,12 @@ object::Archive::Kind
NewArchiveMember::detectKindFromObject() const {
Expected> OptionalObject =
object::ObjectFile::createObjectFile(MemBufferRef);
- if (OptionalObject) {
-if (isa(**OptionalObject))
- return object::Archive::K_DARWIN;
-if (isa(**OptionalObject))
- return object::Archive::K_AIXBIG;
-if (isa(**OptionalObject) ||
-isa(**OptionalObject))
- return object::Archive::K_COFF;
-return object::Archive::K_GNU;
- }
+ if (OptionalObject)
+return isa(**OptionalObject)
+ ? object::Archive::K_DARWIN
+ : (isa(**OptionalObject)
+ ? object::Archive::K_AIXBIG
+ : object::Archive::K_GNU);
// Squelch the error in case we had a non-object file.
consumeError(OptionalObject.takeError());
@@ -84,7 +80,10 @@ object::Archive::Kind
NewArchiveMember::detectKindFromObject() const {
MemBufferRef, file_magic::bitcode, &Context)) {
auto &IRObject = cast(**ObjOrErr);
auto TargetTriple = Triple(IRObject.getTargetTriple());
- return object::Archive::getDefaultKindForTriple(TargetTriple);
+ return TargetTriple.isOSDarwin()
+ ? object::Archive::K_DARWIN
+ : (TargetTriple.isOSAIX() ? object::Archive::K_AIXBIG
+ : object::Archive::K_GNU);
} else {
// Squelch the error in case this was not a SymbolicFile.
consumeError(ObjOrErr.takeError());
diff --git a/llvm/test/tools/llvm-ar/coff-symtab.test
b/llvm/test/tools/llvm-ar/coff-symtab.test
deleted file mode 100644
index 50d08fba3b02f6..00
--- a/llvm/test/tools/llvm-ar/coff-symtab.test
+++ /dev/null
@@ -1,85 +0,0 @@
-Verify that llvm-ar uses COFF archive format by ensuring that archive map is
sorted.
-
-RUN: rm -rf %t.dif && split-file %s %t.dir && cd %t.dir
-
-RUN: yaml2obj coff-symtab.yaml -o coff-symtab.obj
-RUN: llvm-ar crs out.a coff-symtab.obj
-RUN: llvm-nm --print-armap out.a | FileCheck %s
-
-RUN: llvm-as coff-symtab.ll -o coff-symtab.bc
-RUN: llvm-ar crs out2.a coff-symtab.bc
-RUN: llvm-nm --print-armap out2.a | FileCheck %s
-
-RUN: yaml2obj elf.yaml -o coff-symtab.o
-RUN: llvm-ar crs --format coff out3.a coff-symtab.o
-RUN: llvm-nm --print-armap out3.a | FileCheck %s
-
-CHECK: Archive map
-CHECK-NEXT: a in coff-symtab
-CHECK-NEXT: b in coff-symtab
-CHECK-NEXT: c in coff-symt
[llvm-branch-commits] [llvm] d1e98bf - Revert "[AArch64] Intrinsics aarch64_{get, set}_fpsr (#81867)"
Author: Serge Pavlov
Date: 2024-02-25T02:04:21+07:00
New Revision: d1e98bf0beb7f1d480710c93432fe6095269
URL:
https://github.com/llvm/llvm-project/commit/d1e98bf0beb7f1d480710c93432fe6095269
DIFF:
https://github.com/llvm/llvm-project/commit/d1e98bf0beb7f1d480710c93432fe6095269.diff
LOG: Revert "[AArch64] Intrinsics aarch64_{get,set}_fpsr (#81867)"
This reverts commit 00c0638b5613912a7d1b65c8789bbb8ad1003115.
Added:
Modified:
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/test/CodeGen/AArch64/preserve.ll
Removed:
llvm/test/CodeGen/AArch64/arm64-fpenv.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td
b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 5a9a7c4b43a1ff..6b045e412cd519 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -703,19 +703,17 @@ def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
let TargetPrefix = "aarch64" in {
- class FPENV_Get_Intrinsic
+ class FPCR_Get_Intrinsic
: DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem,
IntrHasSideEffects]>;
- class FPENV_Set_Intrinsic
+ class FPCR_Set_Intrinsic
: DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem,
IntrHasSideEffects]>;
class RNDR_Intrinsic
: DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem,
IntrHasSideEffects]>;
}
-// FP environment registers.
-def int_aarch64_get_fpcr : FPENV_Get_Intrinsic;
-def int_aarch64_set_fpcr : FPENV_Set_Intrinsic;
-def int_aarch64_get_fpsr : FPENV_Get_Intrinsic;
-def int_aarch64_set_fpsr : FPENV_Set_Intrinsic;
+// FPCR
+def int_aarch64_get_fpcr : FPCR_Get_Intrinsic;
+def int_aarch64_set_fpcr : FPCR_Set_Intrinsic;
// Armv8.5-A Random number generation intrinsics
def int_aarch64_rndr : RNDR_Intrinsic;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e73bc0d89e4c9d..8e73f57ced42b8 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1805,7 +1805,7 @@ def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
// The virtual cycle counter register is CNTVCT_EL0.
def : Pat<(readcyclecounter), (MRS 0xdf02)>;
-// FPCR and FPSR registers.
+// FPCR register
let Uses = [FPCR] in
def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins),
[(set GPR64:$dst, (int_aarch64_get_fpcr))]>,
@@ -1817,17 +1817,6 @@ def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val),
PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>,
Sched<[WriteSys]>;
-let Uses = [FPSR] in
-def MRS_FPSR : Pseudo<(outs GPR64:$dst), (ins),
- [(set GPR64:$dst, (int_aarch64_get_fpsr))]>,
- PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>,
- Sched<[WriteSys]>;
-let Defs = [FPSR] in
-def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
- [(int_aarch64_set_fpsr i64:$val)]>,
- PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
- Sched<[WriteSys]>;
-
// Generic system instructions
def SYSxt : SystemXtI<0, "sys">;
def SYSLxt : SystemLXtI<1, "sysl">;
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index fef1748021b07c..569944e0e660b7 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -147,9 +147,6 @@ def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
// Floating-point control register
def FPCR : AArch64Reg<0, "fpcr">;
-// Floating-point status register.
-def FPSR : AArch64Reg<0, "fpsr">;
-
// GPR register classes with the intersections of GPR32/GPR32sp and
// GPR64/GPR64sp for use by the coalescer.
def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)>
{
diff --git a/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
b/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
deleted file mode 100644
index 030809caee3394..00
--- a/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
+++ /dev/null
@@ -1,45 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
-
-define i64 @get_fpcr() #0 {
-; CHECK-LABEL: get_fpcr:
-; CHECK: // %bb.0:
-; CHECK-NEXT:mrs x0, FPCR
-; CHECK-NEXT:ret
- %1 = tail call i64 @llvm.aarch64.get.fpcr()
- ret i64 %1
-}
-
-define void @set_fpcr(i64 %cr) {
-; CHECK-LABEL: set_fpcr:
-; CHECK: // %bb.0:
-; CHECK-NEXT:msr FPCR, x0
-; CHECK-NEXT:ret
- call void @llvm.aarch64.set.fpcr(i64 %cr)
- ret void
-}
-
-define i64 @get_fpsr() {
-; CHECK-LABEL: get_fpsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT:mrs x0, FPSR
-; CHECK-NEXT:ret
- %1 = tail call i64 @llvm.aarch64
[llvm-branch-commits] [openmp] release/18.x: Fix build on musl by including stdint.h (#81434) (PR #82897)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/82897 Backport 45fe67dd61a6ac7df84d3a586e41c36a4767757f Requested by: @Calandracas606 >From b8e4939ddf6fef001be433c873c95185ac6d1a94 Mon Sep 17 00:00:00 2001 From: Daniel Martinez Date: Thu, 22 Feb 2024 21:14:27 + Subject: [PATCH] Fix build on musl by including stdint.h (#81434) openmp fails to build on musl since it lacks the defines for int32_t Co-authored-by: Daniel Martinez (cherry picked from commit 45fe67dd61a6ac7df84d3a586e41c36a4767757f) --- openmp/libomptarget/include/Shared/SourceInfo.h | 1 + 1 file changed, 1 insertion(+) diff --git a/openmp/libomptarget/include/Shared/SourceInfo.h b/openmp/libomptarget/include/Shared/SourceInfo.h index 7ce5fd43efc07f..711f06a04d017f 100644 --- a/openmp/libomptarget/include/Shared/SourceInfo.h +++ b/openmp/libomptarget/include/Shared/SourceInfo.h @@ -13,6 +13,7 @@ #ifndef OMPTARGET_SHARED_SOURCE_INFO_H #define OMPTARGET_SHARED_SOURCE_INFO_H +#include #include #ifdef _WIN32 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [openmp] release/18.x: Fix build on musl by including stdint.h (#81434) (PR #82897)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/82897 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [openmp] release/18.x: Fix build on musl by including stdint.h (#81434) (PR #82897)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/82897 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/18.x: Unbreak *tf builtins for hexfloat (#82208) (PR #82904)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/82904 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/18.x: Unbreak *tf builtins for hexfloat (#82208) (PR #82904)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/82904
Backport 99c457dc2ef395872d7448c85609f6cb73a7f89b
Requested by: @brad0
>From 4de7aeb2176f6a05e427d57149596c376d5b148d Mon Sep 17 00:00:00 2001
From: Alexander Richardson
Date: Wed, 21 Feb 2024 12:59:56 -0800
Subject: [PATCH] Unbreak *tf builtins for hexfloat (#82208)
This re-lands cc0065a7d082f0bd322a538cf62cfaef1c8f89f8 in a way that
keeps existing targets working.
-
Original commit message:
#68132 ended up removing
__multc3 & __divtc3 from compiler-rt library builds that have
QUAD_PRECISION but not TF_MODE due to missing int128 support.
I added support for QUAD_PRECISION to use the native hex float long double
representation.
-
Co-authored-by: Sean Perry
(cherry picked from commit 99c457dc2ef395872d7448c85609f6cb73a7f89b)
---
compiler-rt/lib/builtins/divtc3.c| 2 +-
compiler-rt/lib/builtins/fp_lib.h| 41 ++--
compiler-rt/lib/builtins/int_types.h | 8 --
compiler-rt/lib/builtins/multc3.c| 2 +-
4 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/compiler-rt/lib/builtins/divtc3.c
b/compiler-rt/lib/builtins/divtc3.c
index e970cef574b21d..099de5802daf0e 100644
--- a/compiler-rt/lib/builtins/divtc3.c
+++ b/compiler-rt/lib/builtins/divtc3.c
@@ -13,7 +13,7 @@
#define QUAD_PRECISION
#include "fp_lib.h"
-#if defined(CRT_HAS_TF_MODE)
+#if defined(CRT_HAS_F128)
// Returns: the quotient of (a + ib) / (c + id)
diff --git a/compiler-rt/lib/builtins/fp_lib.h
b/compiler-rt/lib/builtins/fp_lib.h
index af406e760497a4..c4f0a5b9587f77 100644
--- a/compiler-rt/lib/builtins/fp_lib.h
+++ b/compiler-rt/lib/builtins/fp_lib.h
@@ -22,6 +22,7 @@
#include "int_lib.h"
#include "int_math.h"
+#include "int_types.h"
#include
#include
#include
@@ -93,13 +94,14 @@ static __inline void wideMultiply(rep_t a, rep_t b, rep_t
*hi, rep_t *lo) {
COMPILER_RT_ABI fp_t __adddf3(fp_t a, fp_t b);
#elif defined QUAD_PRECISION
-#if defined(CRT_HAS_TF_MODE)
+#if defined(CRT_HAS_F128) && defined(CRT_HAS_128BIT)
typedef uint64_t half_rep_t;
typedef __uint128_t rep_t;
typedef __int128_t srep_t;
typedef tf_float fp_t;
#define HALF_REP_C UINT64_C
#define REP_C (__uint128_t)
+#if defined(CRT_HAS_IEEE_TF)
// Note: Since there is no explicit way to tell compiler the constant is a
// 128-bit integer, we let the constant be casted to 128-bit integer
#define significandBits 112
@@ -188,7 +190,10 @@ static __inline void wideMultiply(rep_t a, rep_t b, rep_t
*hi, rep_t *lo) {
#undef Word_HiMask
#undef Word_LoMask
#undef Word_FullMask
-#endif // defined(CRT_HAS_TF_MODE)
+#endif // defined(CRT_HAS_IEEE_TF)
+#else
+typedef long double fp_t;
+#endif // defined(CRT_HAS_F128) && defined(CRT_HAS_128BIT)
#else
#error SINGLE_PRECISION, DOUBLE_PRECISION or QUAD_PRECISION must be defined.
#endif
@@ -196,19 +201,6 @@ static __inline void wideMultiply(rep_t a, rep_t b, rep_t
*hi, rep_t *lo) {
#if defined(SINGLE_PRECISION) || defined(DOUBLE_PRECISION) ||
\
(defined(QUAD_PRECISION) && defined(CRT_HAS_TF_MODE))
#define typeWidth (sizeof(rep_t) * CHAR_BIT)
-#define exponentBits (typeWidth - significandBits - 1)
-#define maxExponent ((1 << exponentBits) - 1)
-#define exponentBias (maxExponent >> 1)
-
-#define implicitBit (REP_C(1) << significandBits)
-#define significandMask (implicitBit - 1U)
-#define signBit (REP_C(1) << (significandBits + exponentBits))
-#define absMask (signBit - 1U)
-#define exponentMask (absMask ^ significandMask)
-#define oneRep ((rep_t)exponentBias << significandBits)
-#define infRep exponentMask
-#define quietBit (implicitBit >> 1)
-#define qnanRep (exponentMask | quietBit)
static __inline rep_t toRep(fp_t x) {
const union {
@@ -226,6 +218,21 @@ static __inline fp_t fromRep(rep_t x) {
return rep.f;
}
+#if !defined(QUAD_PRECISION) || defined(CRT_HAS_IEEE_TF)
+#define exponentBits (typeWidth - significandBits - 1)
+#define maxExponent ((1 << exponentBits) - 1)
+#define exponentBias (maxExponent >> 1)
+
+#define implicitBit (REP_C(1) << significandBits)
+#define significandMask (implicitBit - 1U)
+#define signBit (REP_C(1) << (significandBits + exponentBits))
+#define absMask (signBit - 1U)
+#define exponentMask (absMask ^ significandMask)
+#define oneRep ((rep_t)exponentBias << significandBits)
+#define infRep exponentMask
+#define quietBit (implicitBit >> 1)
+#define qnanRep (exponentMask | quietBit)
+
static __inline int normalize(rep_t *significand) {
const int shift = rep_clz(*significand) - rep_clz(implicitBit);
*significand <<= shift;
@@ -328,6 +335,8 @@ static __inline fp_t __compiler_rt_scalbnX(fp_t x, int y) {
return fromRep(sign | ((rep_t)exp << significandBits) | sig);
}
+#endif // !defined(QUAD_PRECISION) || defined(CRT_HAS_IEEE_TF)
+
// Avoid using fmax from libm.
static __inline fp_t __compiler_rt_fmaxX(fp_t x, fp_t y) {
// If either argument is NaN, return the other argument. If bot
