[llvm-branch-commits] [clang] 04caadc - [Driver] Enable __float128 support on X86 on FreeBSD / NetBSD (#72788)
Author: Brad Smith
Date: 2023-11-28T09:51:27+01:00
New Revision: 04caadc61fa221002018d32174f945d2904c2fae
URL:
https://github.com/llvm/llvm-project/commit/04caadc61fa221002018d32174f945d2904c2fae
DIFF:
https://github.com/llvm/llvm-project/commit/04caadc61fa221002018d32174f945d2904c2fae.diff
LOG: [Driver] Enable __float128 support on X86 on FreeBSD / NetBSD (#72788)
(cherry picked from commit 23c47eba879769a29772c999be2991201c2fe399)
Added:
Modified:
clang/lib/Basic/Targets/OSTargets.h
clang/test/CodeGenCXX/float128-declarations.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/OSTargets.h
b/clang/lib/Basic/Targets/OSTargets.h
index 8f4331b02f3b734..cf8cc8e61c498ae 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -217,6 +217,8 @@ class LLVM_LIBRARY_VISIBILITY FreeBSDTargetInfo : public
OSTargetInfo {
Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
DefineStd(Builder, "unix", Opts);
+if (this->HasFloat128)
+ Builder.defineMacro("__FLOAT128__");
// On FreeBSD, wchar_t contains the number of the code point as
// used by the character set of the locale. These character sets are
@@ -234,9 +236,11 @@ class LLVM_LIBRARY_VISIBILITY FreeBSDTargetInfo : public
OSTargetInfo {
FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: OSTargetInfo(Triple, Opts) {
switch (Triple.getArch()) {
-default:
case llvm::Triple::x86:
case llvm::Triple::x86_64:
+ this->HasFloat128 = true;
+ [[fallthrough]];
+default:
this->MCountName = ".mcount";
break;
case llvm::Triple::mips:
@@ -425,12 +429,22 @@ class LLVM_LIBRARY_VISIBILITY NetBSDTargetInfo : public
OSTargetInfo {
Builder.defineMacro("__unix__");
if (Opts.POSIXThreads)
Builder.defineMacro("_REENTRANT");
+if (this->HasFloat128)
+ Builder.defineMacro("__FLOAT128__");
}
public:
NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: OSTargetInfo(Triple, Opts) {
this->MCountName = "__mcount";
+switch (Triple.getArch()) {
+default:
+ break;
+case llvm::Triple::x86:
+case llvm::Triple::x86_64:
+ this->HasFloat128 = true;
+ break;
+}
}
};
diff --git a/clang/test/CodeGenCXX/float128-declarations.cpp
b/clang/test/CodeGenCXX/float128-declarations.cpp
index ddfe9dce109c81e..84b8f7f33036b59 100644
--- a/clang/test/CodeGenCXX/float128-declarations.cpp
+++ b/clang/test/CodeGenCXX/float128-declarations.cpp
@@ -6,9 +6,17 @@
// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
// RUN: %clang_cc1 -emit-llvm -triple x86_64-unknown-linux-gnu -std=c++11 \
// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
-// RUN: %clang_cc1 -emit-llvm -triple i686-pc-openbsd -std=c++11 \
+// RUN: %clang_cc1 -emit-llvm -triple i386-unknown-freebsd -std=c++11 \
// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
-// RUN: %clang_cc1 -emit-llvm -triple amd64-pc-openbsd -std=c++11 \
+// RUN: %clang_cc1 -emit-llvm -triple amd64-unknown-freebsd -std=c++11 \
+// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
+// RUN: %clang_cc1 -emit-llvm -triple i386-unknown-netbsd -std=c++11 \
+// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
+// RUN: %clang_cc1 -emit-llvm -triple amd64-unknown-netbsd -std=c++11 \
+// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
+// RUN: %clang_cc1 -emit-llvm -triple i386-unknown-openbsd -std=c++11 \
+// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
+// RUN: %clang_cc1 -emit-llvm -triple amd64-unknown-openbsd -std=c++11 \
// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
// RUN: %clang_cc1 -emit-llvm -triple i386-pc-solaris2.11 -std=c++11 \
// RUN: %s -o - | FileCheck %s -check-prefix=CHECK-X86
___
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[llvm-branch-commits] [llvm] 6009708 - Revert "[runtimes] Add missing test dependencies to check-all (#72955)"
Author: Tobias Hieta
Date: 2023-11-28T09:52:28+01:00
New Revision: 6009708b4367171ccdbf4b5905cb6a803753fe18
URL:
https://github.com/llvm/llvm-project/commit/6009708b4367171ccdbf4b5905cb6a803753fe18
DIFF:
https://github.com/llvm/llvm-project/commit/6009708b4367171ccdbf4b5905cb6a803753fe18.diff
LOG: Revert "[runtimes] Add missing test dependencies to check-all (#72955)"
This reverts commit e957e6dcb29d94e4e1678da9829b77009be88926.
The commit was reverted on main because of issues. We will not carry
this in the release branch for 17.x
Added:
Modified:
llvm/CMakeLists.txt
Removed:
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index be0fc6c2ad76cef..79de9eb2e3e71be 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -1215,7 +1215,6 @@ if( LLVM_INCLUDE_TESTS )
add_custom_target(test-depends
DEPENDS ${LLVM_ALL_LIT_DEPENDS} ${LLVM_ALL_ADDITIONAL_TEST_DEPENDS})
set_target_properties(test-depends PROPERTIES FOLDER "Tests")
- add_dependencies(check-all test-depends)
endif()
if (LLVM_INCLUDE_DOCS)
___
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[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
qcolombet wrote: I haven't looked closely to the patch, but I share @MatzeB's concerns here. Essentially this patch is reverting https://reviews.llvm.org/D36160, which was fixing a modeling issue with LR on ARM to begin with! https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
fhahn wrote: > I haven't looked closely to the patch, but I share @MatzeB's concerns here. > > Essentially this patch is reverting https://reviews.llvm.org/D36160, which > was fixing a modeling issue with LR on ARM to begin with! Thanks for sharing the additional context and where `IsRestored` is actually set. Taking a look at the original patch, it seems like it doesn't properly account for the fact that there could be multiple return blocks which may not be using `POP` to restore LR to PC. This could be due to shrink-wrapping + tail-calls in some exit blocks (like in `outlined-fn-may-clobber-lr-in-caller.ll`) or possibly some return instructions not using POP. IIUC D36160 tries to track LR liveness more accurately and doesn't fix a miscompile, but potentially introduced an mis-compile due to underestimating liveness of LR. I don't think the current interface allows to properly check if all exit blocks are covered by POP insts in `restoreCalleeSavedRegisters`, as it works on single return blocks only. Without changing the API, we could check if LR is marked as not restored, and if it is check if there are multiple return blocks, as sketched in https://gist.github.com/fhahn/67937125b64440a8a414909c4a1b7973. This could be further refined to check if POP could be used for all returns (not sure if it is worth it given the small impact on the tests) or the API could be changed to pass all return blocks to avoid re-scanning for returns on each call (not sure if we should extend the general API even more for this workaround though). WDYT https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 21b30e1 - [NFC][TLI] Improve tests for ArmPL and SLEEF Intrinsics.
Author: Paschalis Mpeis
Date: 2023-11-24T16:49:05Z
New Revision: 21b30e18814016dc61b1a1ed87609e53454e3553
URL:
https://github.com/llvm/llvm-project/commit/21b30e18814016dc61b1a1ed87609e53454e3553
DIFF:
https://github.com/llvm/llvm-project/commit/21b30e18814016dc61b1a1ed87609e53454e3553.diff
LOG: [NFC][TLI] Improve tests for ArmPL and SLEEF Intrinsics.
Auto-generate test `armpl-intrinsics.ll`, and use active lane mask to
have shorter `shufflevector` check lines.
Update scripts now add `@llvm.compiler.used` instead of using the regex:
`@[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]]`
Added:
Modified:
llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll
Removed:
diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
index a38d4a53407c5d2..18431ae021f9766 100644
--- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
+++ b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
@@ -15,7 +15,7 @@ declare @llvm.cos.nxv2f64()
declare @llvm.cos.nxv4f32()
;.
-; CHECK: @[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [16 x
ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_vsinq_f64, ptr
@armpl_vsinq_f32, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr
@armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_vexp10q_f64, ptr
@armpl_vexp10q_f32, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr
@armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_vlog10q_f64, ptr
@armpl_vlog10q_f32], section "llvm.metadata"
+; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr
@armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_vsinq_f64, ptr
@armpl_vsinq_f32, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr
@armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_vexp10q_f64, ptr
@armpl_vexp10q_f32, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr
@armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_vlog10q_f64, ptr
@armpl_vlog10q_f32], section "llvm.metadata"
;.
define <2 x double> @llvm_cos_f64(<2 x double> %in) {
; CHECK-LABEL: define <2 x double> @llvm_cos_f64
diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
index cedb7dd85149d00..be247de368056e7 100644
--- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
+++ b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
@@ -4,7 +4,7 @@
target triple = "aarch64-unknown-linux-gnu"
;.
-; CHECK: @[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [16 x
ptr] [ptr @_ZGVnN2v_cos, ptr @_ZGVnN4v_cosf, ptr @_ZGVnN2v_exp, ptr
@_ZGVnN4v_expf, ptr @_ZGVnN2v_exp2, ptr @_ZGVnN4v_exp2f, ptr @_ZGVnN2v_exp10,
ptr @_ZGVnN4v_exp10f, ptr @_ZGVnN2v_log, ptr @_ZGVnN4v_logf, ptr
@_ZGVnN2v_log10, ptr @_ZGVnN4v_log10f, ptr @_ZGVnN2v_log2, ptr @_ZGVnN4v_log2f,
ptr @_ZGVnN2v_sin, ptr @_ZGVnN4v_sinf], section "llvm.metadata"
+; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr @_ZGVnN2v_cos,
ptr @_ZGVnN4v_cosf, ptr @_ZGVnN2v_exp, ptr @_ZGVnN4v_expf, ptr @_ZGVnN2v_exp2,
ptr @_ZGVnN4v_exp2f, ptr @_ZGVnN2v_exp10, ptr @_ZGVnN4v_exp10f, ptr
@_ZGVnN2v_log, ptr @_ZGVnN4v_logf, ptr @_ZGVnN2v_log10, ptr @_ZGVnN4v_log10f,
ptr @_ZGVnN2v_log2, ptr @_ZGVnN4v_log2f, ptr @_ZGVnN2v_sin, ptr
@_ZGVnN4v_sinf], section "llvm.metadata"
;.
define <2 x double> @llvm_ceil_f64(<2 x double> %in) {
; CHECK-LABEL: @llvm_ceil_f64(
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
b/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
index 03d959c928577d5..07b1402b4697fa2 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
@@ -1,10 +1,9 @@
-; RUN: opt -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize -S
< %s | FileCheck %s --check-prefixes=CHECK,NEON
-; RUN: opt -mattr=+sve -vector-library=ArmPL
-passes=inject-tli-mappings,loop-vectorize -S < %s | FileCheck %s
--check-prefixes=CHECK,SVE
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --filter
"(\.|_v|_sv)(ceil|copysign|cos|exp\.|expf?\(|exp2|exp10|fabs|floor|fma|log|m..num|pow|nearbyint|rint|round|sin|sqrt|trunc)|(ret)"
--version 2
+; RUN: opt -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize
-prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck
%s --check-prefixes=NEON
+; RUN: opt -mattr=+sve -vector-library=ArmPL
-passes=inject-tli-mappings,loop-vectorize
-prefer-predicate-over-epilogue=predicate-dont-v
[llvm-branch-commits] [llvm] cace1ec - Add `simplifycfg` pass and `noalias` to ensure tail folding.
Author: Paschalis Mpeis
Date: 2023-11-27T17:40:30Z
New Revision: cace1ec7346d3dfee9fcc5d67d79bce989b207d1
URL:
https://github.com/llvm/llvm-project/commit/cace1ec7346d3dfee9fcc5d67d79bce989b207d1
DIFF:
https://github.com/llvm/llvm-project/commit/cace1ec7346d3dfee9fcc5d67d79bce989b207d1.diff
LOG: Add `simplifycfg` pass and `noalias` to ensure tail folding.
`noalias` attribute was added only to the `%in.ptr` parameter of the
ArmPL Intrinsics.
Added:
Modified:
llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll
Removed:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
b/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
index 07b1402b4697fa2..96d94f72fabf06d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --filter
"(\.|_v|_sv)(ceil|copysign|cos|exp\.|expf?\(|exp2|exp10|fabs|floor|fma|log|m..num|pow|nearbyint|rint|round|sin|sqrt|trunc)|(ret)"
--version 2
-; RUN: opt -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize
-prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck
%s --check-prefixes=NEON
-; RUN: opt -mattr=+sve -vector-library=ArmPL
-passes=inject-tli-mappings,loop-vectorize
-prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s
--check-prefixes=SVE
+; RUN: opt -vector-library=ArmPL
-passes=inject-tli-mappings,loop-vectorize,simplifycfg
-prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck
%s --check-prefixes=NEON
+; RUN: opt -mattr=+sve -vector-library=ArmPL
-passes=inject-tli-mappings,loop-vectorize,simplifycfg
-prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s
--check-prefixes=SVE
target triple = "aarch64-unknown-linux-gnu"
@@ -10,18 +10,16 @@ target triple = "aarch64-unknown-linux-gnu"
declare double @llvm.cos.f64(double)
declare float @llvm.cos.f32(float)
-define void @cos_f64(ptr nocapture %in.ptr, ptr %out.ptr) {
+define void @cos_f64(ptr noalias %in.ptr, ptr %out.ptr) {
;
; NEON-LABEL: define void @cos_f64
-; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) {
-; NEON:[[TMP4:%.*]] = call <2 x double> @armpl_vcosq_f64(<2 x double>
[[WIDE_LOAD:%.*]])
-; NEON:[[CALL:%.*]] = tail call double @llvm.cos.f64(double [[IN:%.*]])
#[[ATTR1:[0-9]+]]
+; NEON-SAME: (ptr noalias [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) {
+; NEON:[[TMP3:%.*]] = call <2 x double> @armpl_vcosq_f64(<2 x double>
[[WIDE_LOAD:%.*]])
; NEON:ret void
;
; SVE-LABEL: define void @cos_f64
-; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]])
#[[ATTR1:[0-9]+]] {
-; SVE:[[TMP17:%.*]] = call
@armpl_svcos_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]])
-; SVE:[[CALL:%.*]] = tail call double @llvm.cos.f64(double [[IN:%.*]])
#[[ATTR5:[0-9]+]]
+; SVE-SAME: (ptr noalias [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]])
#[[ATTR1:[0-9]+]] {
+; SVE:[[TMP13:%.*]] = call
@armpl_svcos_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]])
; SVE:ret void
;
entry:
@@ -42,17 +40,15 @@ define void @cos_f64(ptr nocapture %in.ptr, ptr %out.ptr) {
ret void
}
-define void @cos_f32(ptr nocapture %in.ptr, ptr %out.ptr) {
+define void @cos_f32(ptr noalias %in.ptr, ptr %out.ptr) {
; NEON-LABEL: define void @cos_f32
-; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) {
-; NEON:[[TMP4:%.*]] = call <4 x float> @armpl_vcosq_f32(<4 x float>
[[WIDE_LOAD:%.*]])
-; NEON:[[CALL:%.*]] = tail call float @llvm.cos.f32(float [[IN:%.*]])
#[[ATTR2:[0-9]+]]
+; NEON-SAME: (ptr noalias [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) {
+; NEON:[[TMP3:%.*]] = call <4 x float> @armpl_vcosq_f32(<4 x float>
[[WIDE_LOAD:%.*]])
; NEON:ret void
;
; SVE-LABEL: define void @cos_f32
-; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] {
-; SVE:[[TMP17:%.*]] = call @armpl_svcos_f32_x( [[WIDE_MASKED_LOAD:%.*]],
[[ACTIVE_LANE_MASK:%.*]])
-; SVE:[[CALL:%.*]] = tail call float @llvm.cos.f32(float [[IN:%.*]])
#[[ATTR6:[0-9]+]]
+; SVE-SAME: (ptr noalias [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] {
+; SVE:[[TMP13:%.*]] = call @armpl_svcos_f32_x( [[WIDE_MASKED_LOAD:%.*]],
[[ACTIVE_LANE_MASK:%.*]])
; SVE:ret void
;
entry:
@@ -76,15 +72,13 @@ define void @cos_f32(ptr nocapture %in.ptr, ptr %out.ptr) {
declare double @llvm.exp.f64(double)
declare float @llvm.exp.f32(float)
-define void @exp_f64(ptr nocapture %in.ptr, ptr %out.ptr) {
+define void @exp_f64(ptr noalias %in.ptr, ptr %out.ptr) {
; NEON-LABEL: define void @exp_f64
-; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr
[llvm-branch-commits] [llvm] 6f79792 - [TLI] Pass replace-with-veclib works with Scalable Vectors.
Author: Paschalis Mpeis
Date: 2023-11-28T12:02:12Z
New Revision: 6f797921e23fe9a4500222e69ebd75aa7ba53ec1
URL:
https://github.com/llvm/llvm-project/commit/6f797921e23fe9a4500222e69ebd75aa7ba53ec1
DIFF:
https://github.com/llvm/llvm-project/commit/6f797921e23fe9a4500222e69ebd75aa7ba53ec1.diff
LOG: [TLI] Pass replace-with-veclib works with Scalable Vectors.
The pass uses the Masked variant of TLI method when the Intrinsic
operates on Scalable Vectors and it fails to find a non-Masked variant.
Added:
Modified:
llvm/lib/Analysis/VFABIDemangling.cpp
llvm/lib/CodeGen/ReplaceWithVeclib.cpp
llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll
Removed:
diff --git a/llvm/lib/Analysis/VFABIDemangling.cpp
b/llvm/lib/Analysis/VFABIDemangling.cpp
index 88f61cfeb9ba4e5..85880257a320860 100644
--- a/llvm/lib/Analysis/VFABIDemangling.cpp
+++ b/llvm/lib/Analysis/VFABIDemangling.cpp
@@ -126,7 +126,7 @@ static ParseRet
tryParseLinearTokenWithRuntimeStep(StringRef &ParseString,
return ParseRet::None;
}
-/// The function looks for the following stringt at the beginning of
+/// The function looks for the following string at the beginning of
/// the input string `ParseString`:
///
///
diff --git a/llvm/lib/CodeGen/ReplaceWithVeclib.cpp
b/llvm/lib/CodeGen/ReplaceWithVeclib.cpp
index 36c91b7fa97e462..d31a793556dfded 100644
--- a/llvm/lib/CodeGen/ReplaceWithVeclib.cpp
+++ b/llvm/lib/CodeGen/ReplaceWithVeclib.cpp
@@ -105,6 +105,7 @@ static bool replaceWithCallToVeclib(const TargetLibraryInfo
&TLI,
// all vector operands have identical vector width.
ElementCount VF = ElementCount::getFixed(0);
SmallVector ScalarTypes;
+ bool MayBeMasked = false;
for (auto Arg : enumerate(CI.args())) {
auto *ArgType = Arg.value()->getType();
// Vector calls to intrinsics can still have
@@ -121,17 +122,13 @@ static bool replaceWithCallToVeclib(const
TargetLibraryInfo &TLI,
return false;
}
ElementCount NumElements = VectorArgTy->getElementCount();
- if (NumElements.isScalable()) {
-// The current implementation does not support
-// scalable vectors.
-return false;
- }
- if (VF.isNonZero() && VF != NumElements) {
-// The
diff erent arguments
diff er in vector size.
+ if (NumElements.isScalable())
+MayBeMasked = true;
+
+ // The
diff erent arguments
diff er in vector size.
+ if (VF.isNonZero() && VF != NumElements)
return false;
- } else {
-VF = NumElements;
- }
+ VF = NumElements;
ScalarTypes.push_back(VectorArgTy->getElementType());
}
}
@@ -152,11 +149,14 @@ static bool replaceWithCallToVeclib(const
TargetLibraryInfo &TLI,
return false;
}
+ // Assume it has a mask when that is a possibility and has no mapping for
+ // a Non-Masked variant.
+ const bool IsMasked =
+ MayBeMasked && !TLI.getVectorMappingInfo(ScalarName, VF, false);
// Try to find the mapping for the scalar version of this intrinsic
// and the exact vector width of the call operands in the
// TargetLibraryInfo.
- StringRef TLIName = TLI.getVectorizedFunction(ScalarName, VF);
-
+ StringRef TLIName = TLI.getVectorizedFunction(ScalarName, VF, IsMasked);
LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": Looking up TLI mapping for `"
<< ScalarName << "` and vector width " << VF << ".\n");
diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
index 18431ae021f9766..633cb220f52464c 100644
--- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
+++ b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
@@ -15,7 +15,7 @@ declare @llvm.cos.nxv2f64()
declare @llvm.cos.nxv4f32()
;.
-; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr
@armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_vsinq_f64, ptr
@armpl_vsinq_f32, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr
@armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_vexp10q_f64, ptr
@armpl_vexp10q_f32, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr
@armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_vlog10q_f64, ptr
@armpl_vlog10q_f32], section "llvm.metadata"
+; CHECK: @llvm.compiler.used = appending global [32 x ptr] [ptr
@armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_svcos_f64_x, ptr
@armpl_svcos_f32_x, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr
@armpl_svsin_f64_x, ptr @armpl_svsin_f32_x, ptr @armpl_vexpq_f64, ptr
@armpl_vexpq_f32, ptr @armpl_svexp_f64_x, ptr @armpl_svexp_f32_x, ptr
@armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_svexp2_f64_x, ptr
@armpl_svexp2_f32_x, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr
@armpl_svexp10_f64_x, ptr @armpl_
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
kparzysz wrote: I think we should get rid of the "restored" flag. The problem is specific to LR, and how LR is handled depends on the calling convention. If the convention expects the caller to preserve its LR, then LR is never live out of the call. If the callee restores the LR to the value before the call (e.g. by popping it from the stack), then LR is a live-out. I haven't looked at the updated testcases in detail, but I see that most of the changes are in treating LR as live (whereas it was dead before). At the first glance that doesn't look right. https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
fhahn wrote: @kparzysz please take a loo at https://gist.github.com/fhahn/67937125b64440a8a414909c4a1b7973, which has much more limited impact. > I haven't looked at the updated testcases in detail, but I see that most of > the changes are in treating LR as live (whereas it was dead before). At the > first glance that doesn't look right. We might now overestimate liveness, which only results in missed perf correct? Although I think this is mostly theoretical at this point, as there's no test cases that show that. The issue is that underestimating as we currently do leads to incorrect results, in particular with tail calls that use LR implicitly. If LR isn't marked as live in that case, other passes are free to clobber LR (e.g. the machine-outliner by introducing calls using BL, as in https://github.com/llvm/llvm-project/blob/20f634f275b431ff256ba45cbcbb6dc5bd945fb3/llvm/test/CodeGen/Thumb2/outlined-fn-may-clobber-lr-in-caller.ll https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] c41b11a - [BPF] lowering target address leaf nodes (tconstpool, tblockaddr, tjumptable)
Author: Yingchi Long
Date: 2023-11-29T00:19:18+08:00
New Revision: c41b11adba30a630832561200d7095be90b1515f
URL:
https://github.com/llvm/llvm-project/commit/c41b11adba30a630832561200d7095be90b1515f
DIFF:
https://github.com/llvm/llvm-project/commit/c41b11adba30a630832561200d7095be90b1515f.diff
LOG: [BPF] lowering target address leaf nodes (tconstpool, tblockaddr,
tjumptable)
Added:
Modified:
llvm/lib/Target/BPF/BPFISelLowering.cpp
llvm/lib/Target/BPF/BPFISelLowering.h
llvm/lib/Target/BPF/BPFInstrInfo.td
llvm/lib/Target/BPF/BPFMCInstLower.cpp
Removed:
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp
b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index f3368b8979d6f5b..32383260e647a89 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -69,7 +69,9 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
- setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction({ISD::GlobalAddress, ISD::BlockAddress, ISD::ConstantPool,
+ ISD::JumpTable},
+ MVT::i64, Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
@@ -305,6 +307,12 @@ SDValue BPFTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return LowerBR_CC(Op, DAG);
case ISD::GlobalAddress:
return LowerGlobalAddress(Op, DAG);
+ case ISD::BlockAddress:
+return LowerBlockAddress(Op, DAG);
+ case ISD::ConstantPool:
+return LowerConstantPool(Op, DAG);
+ case ISD::JumpTable:
+return LowerJumpTable(Op, DAG);
case ISD::SELECT_CC:
return LowerSELECT_CC(Op, DAG);
case ISD::DYNAMIC_STACKALLOC:
@@ -670,18 +678,65 @@ const char *BPFTargetLowering::getTargetNodeName(unsigned
Opcode) const {
return nullptr;
}
+static SDValue getTargetNode(GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty,
+ SelectionDAG &DAG, unsigned Flags) {
+ return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
+}
+
+static SDValue getTargetNode(BlockAddressSDNode *N, const SDLoc &DL, EVT Ty,
+ SelectionDAG &DAG, unsigned Flags) {
+ return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
+ Flags);
+}
+
+static SDValue getTargetNode(ConstantPoolSDNode *N, const SDLoc &DL, EVT Ty,
+ SelectionDAG &DAG, unsigned Flags) {
+ return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
+ N->getOffset(), Flags);
+}
+
+static SDValue getTargetNode(JumpTableSDNode *N, const SDLoc &DL, EVT Ty,
+ SelectionDAG &DAG, unsigned Flags) {
+ return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
+}
+
+template
+SDValue BPFTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
+ unsigned Flags) const {
+ SDLoc DL(N);
+
+ SDValue GA = getTargetNode(N, DL, MVT::i64, DAG, Flags);
+
+ return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
+}
+
SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
- auto *N = cast(Op);
+ GlobalAddressSDNode *N = cast(Op);
if (N->getOffset() != 0)
report_fatal_error("invalid offset for global address: " +
Twine(N->getOffset()));
+ return getAddr(N, DAG);
+}
- SDLoc DL(Op);
- const GlobalValue *GV = N->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
+SDValue BPFTargetLowering::LowerBlockAddress(SDValue Op,
+ SelectionDAG &DAG) const {
+ BlockAddressSDNode *N = cast(Op);
- return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
+ return getAddr(N, DAG);
+}
+
+SDValue BPFTargetLowering::LowerConstantPool(SDValue Op,
+ SelectionDAG &DAG) const {
+ ConstantPoolSDNode *N = cast(Op);
+
+ return getAddr(N, DAG);
+}
+
+SDValue BPFTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
{
+ JumpTableSDNode *N = cast(Op);
+
+ return getAddr(N, DAG);
}
unsigned
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.h
b/llvm/lib/Target/BPF/BPFISelLowering.h
index 3be1c04bca3d654..7e7355a8ae65b71 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.h
+++ b/llvm/lib/Target/BPF/BPFISelLowering.h
@@ -75,7 +75,14 @@ class BPFTargetLowering : public TargetLowering {
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
+
+ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) cons
[llvm-branch-commits] [llvm] [BPF] expand cttz, ctlz for i32, i64 (PR #73668)
https://github.com/inclyc created
https://github.com/llvm/llvm-project/pull/73668
Fixes: https://github.com/llvm/llvm-project/issues/62252
Depends on: #73667
>From bfdbfe517e0928e8dbc9fa736a9137c533cd899c Mon Sep 17 00:00:00 2001
From: Yingchi Long
Date: Wed, 29 Nov 2023 00:23:49 +0800
Subject: [PATCH] [BPF] expand cttz, ctlz for i32, i64
Fixes: https://github.com/llvm/llvm-project/issues/62252
---
llvm/lib/Target/BPF/BPFISelLowering.cpp | 9 +-
llvm/test/CodeGen/BPF/cttz-ctlz.ll | 304
2 files changed, 308 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/BPF/cttz-ctlz.ll
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp
b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index 32383260e647a89..b188e4bc5d9d59d 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -113,6 +113,10 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine
&TM,
setOperationAction(ISD::SRL_PARTS, VT, Expand);
setOperationAction(ISD::SRA_PARTS, VT, Expand);
setOperationAction(ISD::CTPOP, VT, Expand);
+setOperationAction(ISD::CTTZ, VT, Expand);
+setOperationAction(ISD::CTLZ, VT, Expand);
+setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
+setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
setOperationAction(ISD::SETCC, VT, Expand);
setOperationAction(ISD::SELECT, VT, Expand);
@@ -125,11 +129,6 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine
&TM,
STI.getHasJmp32() ? Custom : Promote);
}
- setOperationAction(ISD::CTTZ, MVT::i64, Custom);
- setOperationAction(ISD::CTLZ, MVT::i64, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
-
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
if (!STI.hasMovsx()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
diff --git a/llvm/test/CodeGen/BPF/cttz-ctlz.ll
b/llvm/test/CodeGen/BPF/cttz-ctlz.ll
new file mode 100644
index 000..f42b2e2d10871bb
--- /dev/null
+++ b/llvm/test/CodeGen/BPF/cttz-ctlz.ll
@@ -0,0 +1,304 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+; test that we can expand CTTZ & CTLZ
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define i32 @cttz_i32_zdef(i32 %a) {
+; CHECK-LABEL: cttz_i32_zdef:
+; CHECK: # %bb.0:
+; CHECK-NEXT:r2 = r1
+; CHECK-NEXT:r2 = -r2
+; CHECK-NEXT:r1 &= r2
+; CHECK-NEXT:r1 *= 125613361
+; CHECK-NEXT:r2 = 4160749568 ll
+; CHECK-NEXT:r1 &= r2
+; CHECK-NEXT:r1 >>= 27
+; CHECK-NEXT:r2 = {{\.?LCPI[0-9]+_[0-9]+}} ll
+; CHECK-NEXT:r2 += r1
+; CHECK-NEXT:r0 = *(u8 *)(r2 + 0)
+; CHECK-NEXT:exit
+%ret = call i32 @llvm.cttz.i32(i32 %a, i1 1)
+ret i32 %ret
+}
+
+
+define i32 @cttz_i32(i32 %a) {
+; CHECK-LABEL: cttz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT:r0 = 32
+; CHECK-NEXT:r2 = r1
+; CHECK-NEXT:r2 <<= 32
+; CHECK-NEXT:r2 >>= 32
+; CHECK-NEXT:if r2 == 0 goto LBB1_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT:r2 = r1
+; CHECK-NEXT:r2 = -r2
+; CHECK-NEXT:r1 &= r2
+; CHECK-NEXT:r1 *= 125613361
+; CHECK-NEXT:r2 = 4160749568 ll
+; CHECK-NEXT:r1 &= r2
+; CHECK-NEXT:r1 >>= 27
+; CHECK-NEXT:r2 = {{\.?LCPI[0-9]+_[0-9]+}} ll
+; CHECK-NEXT:r2 += r1
+; CHECK-NEXT:r0 = *(u8 *)(r2 + 0)
+; CHECK-NEXT: LBB1_2: # %cond.end
+; CHECK-NEXT:exit
+%ret = call i32 @llvm.cttz.i32(i32 %a, i1 0)
+ret i32 %ret
+}
+
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i64 @cttz_i64_zdef(i64 %a) {
+; CHECK-LABEL: cttz_i64_zdef:
+; CHECK: # %bb.0:
+; CHECK-NEXT:r2 = r1
+; CHECK-NEXT:r2 = -r2
+; CHECK-NEXT:r1 &= r2
+; CHECK-NEXT:r2 = 151050438420815295 ll
+; CHECK-NEXT:r1 *= r2
+; CHECK-NEXT:r1 >>= 58
+; CHECK-NEXT:r2 = {{\.?LCPI[0-9]+_[0-9]+}} ll
+; CHECK-NEXT:r2 += r1
+; CHECK-NEXT:r0 = *(u8 *)(r2 + 0)
+; CHECK-NEXT:exit
+%ret = call i64 @llvm.cttz.i64(i64 %a, i1 1)
+ret i64 %ret
+}
+
+
+define i64 @cttz_i64(i64 %a) {
+; CHECK-LABEL: cttz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT:r0 = 64
+; CHECK-NEXT:if r1 == 0 goto LBB3_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT:r2 = r1
+; CHECK-NEXT:r2 = -r2
+; CHECK-NEXT:r1 &= r2
+; CHECK-NEXT:r2 = 151050438420815295 ll
+; CHECK-NEXT:r1 *= r2
+; CHECK-NEXT:r1 >>= 58
+; CHECK-NEXT:r2 = {{\.?LCPI[0-9]+_[0-9]+}} ll
+; CHECK-NEXT:r2 += r1
+; CHECK-NEXT:r0 = *(u8 *)(r2 + 0)
+; CHECK-NEXT: LBB3_2: # %cond.end
+; CHECK-NEXT:exit
+%ret = call i64 @llvm.cttz.i64(i64 %a, i1 0)
+ret i64 %ret
+}
+
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define i32 @ctlz_i32_zdef(i32 %a) {
+; CHECK-LABEL: ctlz_i32_zdef:
+; CHECK: # %bb.0:
+; CHECK-NEXT:r2 = 4294967294 ll
+; CHECK-NEXT:r3 = r1
+
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
kparzysz wrote: > @kparzysz please take a loo at > https://gist.github.com/fhahn/67937125b64440a8a414909c4a1b7973, which has > much more limited impact. If it's an urgent issue, then it's fine to have a limited-impact fix. I think the root issue still remains though. > If LR isn't marked as live in that case, other passes are free to clobber LR > (e.g. the machine-outliner by introducing calls using BL, as in > https://github.com/llvm/llvm-project/blob/20f634f275b431ff256ba45cbcbb6dc5bd945fb3/llvm/test/CodeGen/Thumb2/outlined-fn-may-clobber-lr-in-caller.ll Does the outliner run after PEI? If the callee has to ensure the correct value of the LR before returning (via a tail call for example), then the PEI code should take care of that. It would see the call to the outlined procedure and do the right thing. After PEI the liveness of LR needs to be accurately reflected and tail calls could (should?) always "use" LR. That would either prevent outlining or cause the outliner to preserve LR across introduced calls. On the caller side, the call instruction clobbers LR, so it can't really be considered live-out (unless the calling convention requires it to be preserved, which I think it doesn't). https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] cd2a197 - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:24:11-08:00
New Revision: cd2a197bc2491d53d222eb67be18b741785c1f12
URL:
https://github.com/llvm/llvm-project/commit/cd2a197bc2491d53d222eb67be18b741785c1f12
DIFF:
https://github.com/llvm/llvm-project/commit/cd2a197bc2491d53d222eb67be18b741785c1f12.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [llvm] 7e4d36f - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:25:29-08:00
New Revision: 7e4d36f8a6babb62d734b125c5910987f352e51e
URL:
https://github.com/llvm/llvm-project/commit/7e4d36f8a6babb62d734b125c5910987f352e51e
DIFF:
https://github.com/llvm/llvm-project/commit/7e4d36f8a6babb62d734b125c5910987f352e51e.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [llvm] 1c14bde - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:28:21-08:00
New Revision: 1c14bde6e41ac375b2107a97b71b92f12e0bdf00
URL:
https://github.com/llvm/llvm-project/commit/1c14bde6e41ac375b2107a97b71b92f12e0bdf00
DIFF:
https://github.com/llvm/llvm-project/commit/1c14bde6e41ac375b2107a97b71b92f12e0bdf00.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [llvm] 52c44ee - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:31:52-08:00
New Revision: 52c44ee01b2a76062eb332a302c6bacc64e550f5
URL:
https://github.com/llvm/llvm-project/commit/52c44ee01b2a76062eb332a302c6bacc64e550f5
DIFF:
https://github.com/llvm/llvm-project/commit/52c44ee01b2a76062eb332a302c6bacc64e550f5.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [llvm] e132c89 - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:33:10-08:00
New Revision: e132c8909e40c9f61bfdbd90dd8cee30c2dbe074
URL:
https://github.com/llvm/llvm-project/commit/e132c8909e40c9f61bfdbd90dd8cee30c2dbe074
DIFF:
https://github.com/llvm/llvm-project/commit/e132c8909e40c9f61bfdbd90dd8cee30c2dbe074.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [llvm] 461b9b7 - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:34:59-08:00
New Revision: 461b9b7b6723fdb11aafeb410be3d9173538677d
URL:
https://github.com/llvm/llvm-project/commit/461b9b7b6723fdb11aafeb410be3d9173538677d
DIFF:
https://github.com/llvm/llvm-project/commit/461b9b7b6723fdb11aafeb410be3d9173538677d.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [llvm] 24f8f63 - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:38:32-08:00
New Revision: 24f8f639f9fb654838b78d8f14a06805e4772628
URL:
https://github.com/llvm/llvm-project/commit/24f8f639f9fb654838b78d8f14a06805e4772628
DIFF:
https://github.com/llvm/llvm-project/commit/24f8f639f9fb654838b78d8f14a06805e4772628.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
compiler-rt/lib/builtins/cpu_model.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO:
[llvm-branch-commits] [compiler-rt] [llvm] [clang] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
https://github.com/jroelofs created https://github.com/llvm/llvm-project/pull/73685 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [llvm] [clang] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Jon Roelofs (jroelofs)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/73685.diff
2 Files Affected:
- (modified) compiler-rt/lib/builtins/cpu_model.c (+76-6)
- (modified) llvm/lib/Target/X86/X86AsmPrinter.cpp (+2)
``diff
diff --git a/compiler-rt/lib/builtins/cpu_model.c
b/compiler-rt/lib/builtins/cpu_model.c
index b0ec5e51e96d491..b0306f5f36baabf 100644
--- a/compiler-rt/lib/builtins/cpu_model.c
+++ b/compiler-rt/lib/builtins/cpu_model.c
@@ -948,6 +948,8 @@ _Bool __aarch64_have_lse_atomics
#if defined(__has_include)
#if __has_include()
#include
+#define HAVE_SYS_AUXV
+#endif
#if __has_include()
#include
@@ -961,6 +963,8 @@ typedef struct __ifunc_arg_t {
#if __has_include()
#include
+#include HAVE_SYS_HWCAP
+#endif
#if defined(__ANDROID__)
#include
@@ -997,6 +1001,9 @@ typedef struct __ifunc_arg_t {
#ifndef HWCAP_SHA2
#define HWCAP_SHA2 (1 << 6)
#endif
+#ifndef HWCAP_CRC32
+#define HWCAP_CRC32 (1 << 7)
+#endif
#ifndef HWCAP_ATOMICS
#define HWCAP_ATOMICS (1 << 8)
#endif
@@ -1149,6 +1156,7 @@ typedef struct __ifunc_arg_t {
if (__system_property_get("ro.arch", arch) > 0 &&
\
strncmp(arch, "exynos9810", sizeof("exynos9810") - 1) == 0)
+#if !defined(__APPLE__)
static void CONSTRUCTOR_ATTRIBUTE init_have_lse_atomics(void) {
#if defined(__FreeBSD__)
unsigned long hwcap;
@@ -1162,7 +1170,7 @@ static void CONSTRUCTOR_ATTRIBUTE
init_have_lse_atomics(void) {
zx_status_t status = _zx_system_get_features(ZX_FEATURE_KIND_CPU, &features);
__aarch64_have_lse_atomics =
status == ZX_OK && (features & ZX_ARM64_FEATURE_ISA_ATOMICS) != 0;
-#else
+#elif defined(HAVE_SYS_AUXV)
unsigned long hwcap = getauxval(AT_HWCAP);
_Bool result = (hwcap & HWCAP_ATOMICS) != 0;
#if defined(__ANDROID__)
@@ -1180,8 +1188,11 @@ static void CONSTRUCTOR_ATTRIBUTE
init_have_lse_atomics(void) {
}
#endif // defined(__ANDROID__)
__aarch64_have_lse_atomics = result;
+#else
+#error No support for checking for lse atomics on this platfrom yet.
#endif // defined(__FreeBSD__)
}
+#endif // !defined(__APPLE__)
#if !defined(DISABLE_AARCH64_FMV)
// CPUFeatures must correspond to the same AArch64 features in
@@ -1259,6 +1270,64 @@ struct {
// As features grows new fields could be added
} __aarch64_cpu_features __attribute__((visibility("hidden"), nocommon));
+#if defined(__APPLE__)
+#include
+#if TARGET_OS_OSX || TARGET_OS_IPHONE
+#include
+#include
+
+static bool isKnownAndSupported(const char *name) {
+ int32_t val = 0;
+ size_t size = sizeof(val);
+ if (sysctlbyname(name, &val, &size, NULL, 0))
+return false;
+ return val;
+}
+
+void __init_cpu_features_resolver(void) {
+ static dispatch_once_t onceToken = 0;
+ dispatch_once(&onceToken, ^{
+//
https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics
+static struct {
+ const char *sysctl_name;
+ enum CPUFeatures feature;
+} Features[] = {
+{"hw.optional.arm.FEAT_FlagM", FEAT_FLAGM},
+{"hw.optional.arm.FEAT_FlagM2", FEAT_FLAGM2},
+{"hw.optional.arm.FEAT_FHM", FEAT_FP16FML},
+{"hw.optional.arm.FEAT_DotProd", FEAT_DOTPROD},
+{"hw.optional.arm.FEAT_RDM", FEAT_RDM},
+{"hw.optional.arm.FEAT_LSE", FEAT_LSE},
+{"hw.optional.floatingpoint", FEAT_FP},
+{"hw.optional.AdvSIMD", FEAT_SIMD},
+{"hw.optional.armv8_crc32", FEAT_CRC},
+{"hw.optional.arm.FEAT_SHA1", FEAT_SHA1},
+{"hw.optional.arm.FEAT_SHA256", FEAT_SHA2},
+{"hw.optional.armv8_2_sha3", FEAT_SHA3},
+{"hw.optional.arm.FEAT_AES", FEAT_AES},
+{"hw.optional.arm.FEAT_PMULL", FEAT_PMULL},
+{"hw.optional.arm.FEAT_FP16", FEAT_FP16},
+{"hw.optional.arm.FEAT_JSCVT", FEAT_JSCVT},
+{"hw.optional.arm.FEAT_FCMA", FEAT_FCMA},
+{"hw.optional.arm.FEAT_LRCPC", FEAT_RCPC},
+{"hw.optional.arm.FEAT_LRCPC2", FEAT_RCPC2},
+{"hw.optional.arm.FEAT_FRINTTS", FEAT_FRINTTS},
+{"hw.optional.arm.FEAT_I8MM", FEAT_I8MM},
+{"hw.optional.arm.FEAT_BF16", FEAT_BF16},
+{"hw.optional.arm.FEAT_SB", FEAT_SB},
+{"hw.optional.arm.FEAT_SSBS", FEAT_SSBS2},
+{"hw.optional.arm.FEAT_BTI", FEAT_BTI},
+};
+
+for (size_t I = 0, E = sizeof(Features) / sizeof(Features[0]); I != E; ++I)
+ if (isKnownAndSupported(Features[I].sysctl_name))
+__aarch64_cpu_features.features |= (1ULL << Features[I].feature);
+
+__aarch64_cpu_features.features |= (1ULL << FEAT_INIT);
+ });
+}
+#endif // TARGET_OS_OSX || TARGET_OS_IPHONE
+#else // defined(__APPLE__)
static void __init_cpu_features_constructor(unsigned long hwcap,
const __ifunc_arg_t *arg) {
#define setCPUFeature(F) __aarch64_cpu_features.features |= 1ULL << F
@@ -1467,8 +1536,8 @@ void __init_cpu_features_r
[llvm-branch-commits] [llvm] bc15209 - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:39:44-08:00
New Revision: bc152095691b32d1ad8539dfd60f5089df5eed8d
URL:
https://github.com/llvm/llvm-project/commit/bc152095691b32d1ad8539dfd60f5089df5eed8d
DIFF:
https://github.com/llvm/llvm-project/commit/bc152095691b32d1ad8539dfd60f5089df5eed8d.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index e448c5ed5c5d947..cb222e979db29d4 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -934,10 +934,11 @@ IFuncs
---
IFuncs, like as aliases, don't create any new data or func. They are just a new
-symbol that dynamic linker resolves at runtime by calling a resolver function.
+symbol that is resolved at runtime by calling a resolver function.
-IFuncs have a name and a resolver that is a function called by dynamic linker
-that returns address of another function associated with the name.
+On ELF platforms, IFuncs are resolved by the dynamic linker at load time. On
+MachO platforms, they are lowered in terms of ``.symbol_resolver``s, which
+lazily resolve the callee the first time they are called.
IFunc may have an optional :ref:`linkage type ` and an optional
:ref:`visibility style `.
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 2731ef452c79cbb..48fa6c478464c73 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -882,7 +882,11 @@ class AsmPrinter : public MachineFunctionPass {
GCMetadataPrinter *getOrCreateGCPrinter(GCStrategy &S);
void emitGlobalAlias(Module &M, const GlobalAlias &GA);
- void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
+
+protected:
+ virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
+
+private:
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 2527b1431289677..e0080b145d4f995 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -144,7 +144,12 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
// Try looking through a bitcast from one function type to another.
// Commonly happens with calls to objc_msgSend().
const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
- if (const Function *F = dyn_cast(CalleeV))
+ if (const GlobalIFunc *IF = dyn_cast(CalleeV);
+ IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
+// ld64 requires that .symbol_resolvers to be called via a stub, so these
+// must always be a diret call.
+Info.Callee = MachineOperand::CreateGA(IF, 0);
+ } else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
else
Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 5560c037aa3ee6b..94e76a43bf38d6d 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,6 +959,7 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
+
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2239,13 +2240,10 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features")) {
-Triple T(M.getTargetTriple());
-if (T.isX86()) {
- StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
- Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
-"512-bit vector arguments require 'evex512' for AVX512", V);
-}
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
+Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
+ "512-bit vector arguments require 'evex512' for AVX512", V);
}
checkUnsignedBaseTenFuncAttr
[llvm-branch-commits] [llvm] d4d16df - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:39:49-08:00
New Revision: d4d16df26295dfe69706332e26ae017283c1e36b
URL:
https://github.com/llvm/llvm-project/commit/d4d16df26295dfe69706332e26ae017283c1e36b
DIFF:
https://github.com/llvm/llvm-project/commit/d4d16df26295dfe69706332e26ae017283c1e36b.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/test/CodeGen/ifunc.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/test/CodeGen/ifunc.c b/clang/test/CodeGen/ifunc.c
index 0b0a0549620f8b8..99d60dc0ea85dbd 100644
--- a/clang/test/CodeGen/ifunc.c
+++ b/clang/test/CodeGen/ifunc.c
@@ -3,6 +3,10 @@
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=thread -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=address -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=memory -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -emit-llvm -o - %s | FileCheck
%s
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -O2 -emit-llvm -o - %s |
FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -fsanitize=thread -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=MACSAN
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -fsanitize=address -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=MACSAN
int foo(int) __attribute__ ((ifunc("foo_ifunc")));
@@ -44,9 +48,13 @@ void* goo_ifunc(void) {
// CHECK: call void @goo()
// SAN: define internal nonnull ptr @foo_ifunc() #[[#FOO_IFUNC:]] {
+// MACSAN: define internal nonnull ptr @foo_ifunc() #[[#FOO_IFUNC:]] {
// SAN: define dso_local noalias ptr @goo_ifunc() #[[#GOO_IFUNC:]] {
+// MACSAN: define noalias ptr @goo_ifunc() #[[#GOO_IFUNC:]] {
// SAN-DAG: attributes #[[#FOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
+// MACSAN-DAG: attributes #[[#FOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
// SAN-DAG: attributes #[[#GOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
+// MACSAN-DAG: attributes #[[#GOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index e448c5ed5c5d947..cb222e979db29d4 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -934,10 +934,11 @@ IFuncs
---
IFuncs, like as aliases, don't create any new data or func. They are just a new
-symbol that dynamic linker resolves at runtime by calling a resolver function.
+symbol that is resolved at runtime by calling a resolver function.
-IFuncs
[llvm-branch-commits] [llvm] [clang] [clang] Support __attribute__((ifunc(...))) on Darwin platforms (PR #73687)
https://github.com/jroelofs created https://github.com/llvm/llvm-project/pull/73687 Unlike ELF targets, MachO does not support the same kind of dynamic symbol resolution at load time. Instead, the corresponding MachO feature resolves symbols lazily on first call. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [clang] [clang] Function Multi Versioning supports IFunc lowerings on Darwin platforms (PR #73688)
https://github.com/jroelofs created https://github.com/llvm/llvm-project/pull/73688 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 60bbb99 - [𝘀𝗽𝗿] initial version
Author: Jon Roelofs
Date: 2023-11-28T10:39:54-08:00
New Revision: 60bbb996f2e9251b288e2230c671cdcf997720ed
URL:
https://github.com/llvm/llvm-project/commit/60bbb996f2e9251b288e2230c671cdcf997720ed
DIFF:
https://github.com/llvm/llvm-project/commit/60bbb996f2e9251b288e2230c671cdcf997720ed.diff
LOG: [𝘀𝗽𝗿] initial version
Created using spr 1.3.4
Added:
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
llvm/test/Verifier/ifunc-macho.ll
Modified:
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/TargetInfo.h
clang/test/CodeGen/attr-target-mv-va-args.c
clang/test/CodeGen/ifunc.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/X86/ifunc-asm.ll
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly
diff erent semantics: the resolver is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO: call i32 (i32, ...) @foo.ifunc(i32 nound
[llvm-branch-commits] [llvm] [clang] [clang] Support __attribute__((ifunc(...))) on Darwin platforms (PR #73687)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Jon Roelofs (jroelofs)
Changes
Unlike ELF targets, MachO does not support the same kind of dynamic symbol
resolution at load time. Instead, the corresponding MachO feature resolves
symbols lazily on first call.
---
Full diff: https://github.com/llvm/llvm-project/pull/73687.diff
3 Files Affected:
- (modified) clang/include/clang/Basic/Attr.td (+4-1)
- (modified) clang/include/clang/Basic/AttrDocs.td (+3-1)
- (modified) clang/test/CodeGen/ifunc.c (+8)
``diff
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 03ed6accf700c4e..cef9f5578fa2baa 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -455,6 +455,9 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64",
"arm", "thumb", "aarch6
def TargetELF : TargetSpec {
let ObjectFormats = ["ELF"];
}
+def TargetELFOrMachO : TargetSpec {
+ let ObjectFormats = ["ELF", "MachO"];
+}
def TargetSupportsInitPriority : TargetSpec {
let CustomCode = [{ !Target.getTriple().isOSzOS() }];
@@ -1665,7 +1668,7 @@ def IBOutletCollection : InheritableAttr {
let Documentation = [Undocumented];
}
-def IFunc : Attr, TargetSpecificAttr {
+def IFunc : Attr, TargetSpecificAttr {
let Spellings = [GCC<"ifunc">];
let Args = [StringArgument<"Resolver">];
let Subjects = SubjectList<[Function]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index be74535e28d8a60..4c4c4eb606fb0dc 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5408,7 +5408,9 @@ considered inline.
Not all targets support this attribute. ELF target support depends on both the
linker and runtime linker, and is available in at least lld 4.0 and later,
binutils 2.20.1 and later, glibc v2.11.1 and later, and FreeBSD 9.1 and later.
-Non-ELF targets currently do not support this attribute.
+MachO targets support it, but with slightly different semantics: the resolver
is
+run at first call, instead of at load time by the runtime linker. Targets other
+than ELF and MachO currently do not support this attribute.
}];
}
diff --git a/clang/test/CodeGen/ifunc.c b/clang/test/CodeGen/ifunc.c
index 0b0a0549620f8b8..99d60dc0ea85dbd 100644
--- a/clang/test/CodeGen/ifunc.c
+++ b/clang/test/CodeGen/ifunc.c
@@ -3,6 +3,10 @@
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=thread -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=address -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=memory -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -emit-llvm -o - %s | FileCheck
%s
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -O2 -emit-llvm -o - %s |
FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -fsanitize=thread -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=MACSAN
+// RUN: %clang_cc1 -triple x86_64-apple-macosx -fsanitize=address -O2
-emit-llvm -o - %s | FileCheck %s --check-prefix=MACSAN
int foo(int) __attribute__ ((ifunc("foo_ifunc")));
@@ -44,9 +48,13 @@ void* goo_ifunc(void) {
// CHECK: call void @goo()
// SAN: define internal nonnull ptr @foo_ifunc() #[[#FOO_IFUNC:]] {
+// MACSAN: define internal nonnull ptr @foo_ifunc() #[[#FOO_IFUNC:]] {
// SAN: define dso_local noalias ptr @goo_ifunc() #[[#GOO_IFUNC:]] {
+// MACSAN: define noalias ptr @goo_ifunc() #[[#GOO_IFUNC:]] {
// SAN-DAG: attributes #[[#FOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
+// MACSAN-DAG: attributes #[[#FOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
// SAN-DAG: attributes #[[#GOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
+// MACSAN-DAG: attributes #[[#GOO_IFUNC]] = {{{.*}}
disable_sanitizer_instrumentation {{.*}}
``
https://github.com/llvm/llvm-project/pull/73687
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [clang] [clang] Function Multi Versioning supports IFunc lowerings on Darwin platforms (PR #73688)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Jon Roelofs (jroelofs)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/73688.diff
2 Files Affected:
- (modified) clang/include/clang/Basic/TargetInfo.h (+2)
- (modified) clang/test/CodeGen/attr-target-mv-va-args.c (+19)
``diff
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbef6..1fe2a18cd5dc9cc 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1424,6 +1424,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports IFuncs.
bool supportsIFunc() const {
+if (getTriple().isOSBinFormatMachO())
+ return true;
return getTriple().isOSBinFormatELF() &&
((getTriple().isOSLinux() && !getTriple().isMusl()) ||
getTriple().isOSFreeBSD());
diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c
b/clang/test/CodeGen/attr-target-mv-va-args.c
index 96821c610235bdc..dbf5a74205c4c19 100644
--- a/clang/test/CodeGen/attr-target-mv-va-args.c
+++ b/clang/test/CodeGen/attr-target-mv-va-args.c
@@ -3,6 +3,7 @@
// RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,WINDOWS
// RUN: %clang_cc1 -triple x86_64-linux-musl -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
// RUN: %clang_cc1 -triple x86_64-fuchsia -emit-llvm %s -o - | FileCheck %s
--check-prefixes=NO-IFUNC,NO-IFUNC-ELF
+// RUN: %clang_cc1 -triple x86_64-apple-macho -emit-llvm %s -o - | FileCheck
%s --check-prefix=IFUNC-MACHO
int __attribute__((target("sse4.2"))) foo(int i, ...) { return 0; }
int __attribute__((target("arch=sandybridge"))) foo(int i, ...);
int __attribute__((target("arch=ivybridge"))) foo(int i, ...) {return 1;}
@@ -30,6 +31,24 @@ int bar(void) {
// IFUNC-ELF: ret ptr @foo
// IFUNC-ELF: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+// IFUNC-MACHO: @foo.ifunc = weak_odr ifunc i32 (i32, ...), ptr @foo.resolver
+// IFUNC-MACHO: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 0
+// IFUNC-MACHO: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 1
+// IFUNC-MACHO: define{{.*}} i32 @foo(i32 noundef %i, ...)
+// IFUNC-MACHO: ret i32 2
+// IFUNC-MACHO: define{{.*}} i32 @bar()
+// IFUNC-MACHO: call i32 (i32, ...) @foo.ifunc(i32 noundef 1, i32 noundef 97,
double
+// IFUNC-MACHO: call i32 (i32, ...) @foo.ifunc(i32 noundef 2, double noundef
2.2{{[0-9Ee+]+}}, ptr noundef
+
+// IFUNC-MACHO: define weak_odr ptr @foo.resolver()
+// IFUNC-MACHO: ret ptr @foo.arch_sandybridge
+// IFUNC-MACHO: ret ptr @foo.arch_ivybridge
+// IFUNC-MACHO: ret ptr @foo.sse4.2
+// IFUNC-MACHO: ret ptr @foo
+// IFUNC-MACHO: declare i32 @foo.arch_sandybridge(i32 noundef, ...)
+
// NO-IFUNC: define dso_local i32 @foo.sse4.2(i32 noundef %i, ...)
// NO-IFUNC: ret i32 0
// NO-IFUNC: define dso_local i32 @foo.arch_ivybridge(i32 noundef %i, ...)
``
https://github.com/llvm/llvm-project/pull/73688
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[llvm-branch-commits] [llvm] [clang] [compiler-rt] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 802e1c6b0b6e343d97a2549d05e0cb33dec09363
24f8f639f9fb654838b78d8f14a06805e4772628 --
compiler-rt/lib/builtins/cpu_model.c llvm/lib/Target/X86/X86AsmPrinter.cpp
``
View the diff from clang-format here.
``diff
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 37158900d2..e7a242d029 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp
@@ -557,7 +557,8 @@ void X86AsmPrinter::emitGlobalIFunc(Module &M, const
GlobalIFunc &GI) {
JMP.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(;
OutStreamer->emitInstruction(JMP, *Subtarget);
- // FIXME: do the manual .symbol_resolver lowering that we did in
AArch64AsmPrinter.
+ // FIXME: do the manual .symbol_resolver lowering that we did in
+ // AArch64AsmPrinter.
}
static bool printAsmMRegister(const X86AsmPrinter &P, const MachineOperand &MO,
``
https://github.com/llvm/llvm-project/pull/73685
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[llvm-branch-commits] [llvm] [clang] [compiler-rt] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
@@ -556,6 +556,8 @@ void X86AsmPrinter::emitGlobalIFunc(Module &M, const
GlobalIFunc &GI) {
JMP.setOpcode(X86::JMP_4);
JMP.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(;
OutStreamer->emitInstruction(JMP, *Subtarget);
+
+ // FIXME: do the manual .symbol_resolver lowering that we did in
AArch64AsmPrinter.
jroelofs wrote:
- [ ] FIXME: This comment belongs in a different commit in the patch stack.
https://github.com/llvm/llvm-project/pull/73685
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[llvm-branch-commits] [llvm] 8f6755e - git clang-format
Author: Jon Roelofs
Date: 2023-11-28T11:04:43-08:00
New Revision: 8f6755e6b211c9b0206197f65304443e26e244eb
URL:
https://github.com/llvm/llvm-project/commit/8f6755e6b211c9b0206197f65304443e26e244eb
DIFF:
https://github.com/llvm/llvm-project/commit/8f6755e6b211c9b0206197f65304443e26e244eb.diff
LOG: git clang-format
Created using spr 1.3.4
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 5241aa6e1c0eade..37158900d2404dd 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++
[llvm-branch-commits] [llvm] 0d426a9 - [𝘀𝗽𝗿] changes introduced through rebase
Author: Jon Roelofs
Date: 2023-11-28T11:04:46-08:00
New Revision: 0d426a93450c7bdc9868c6106e01efafa549eb86
URL:
https://github.com/llvm/llvm-project/commit/0d426a93450c7bdc9868c6106e01efafa549eb86
DIFF:
https://github.com/llvm/llvm-project/commit/0d426a93450c7bdc9868c6106e01efafa549eb86.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 5241aa6e1c0eade..37158900d2404dd 100644
--- a/llvm/lib
[llvm-branch-commits] [llvm] 15d50f3 - rebase
Author: Jon Roelofs
Date: 2023-11-28T11:04:55-08:00
New Revision: 15d50f3463a535112df427ef5213b0d939608e94
URL:
https://github.com/llvm/llvm-project/commit/15d50f3463a535112df427ef5213b0d939608e94
DIFF:
https://github.com/llvm/llvm-project/commit/15d50f3463a535112df427ef5213b0d939608e94.diff
LOG: rebase
Created using spr 1.3.4
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 5241aa6e1c0eade..37158900d2404dd 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib
[llvm-branch-commits] [llvm] [clang] [clang] Support __attribute__((ifunc(...))) on Darwin platforms (PR #73687)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73687 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [clang] [clang] Support __attribute__((ifunc(...))) on Darwin platforms (PR #73687)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73687 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 7695f68 - rebase
Author: Jon Roelofs
Date: 2023-11-28T11:05:21-08:00
New Revision: 7695f68612c300a6b539d251f499cf22fdddb8f8
URL:
https://github.com/llvm/llvm-project/commit/7695f68612c300a6b539d251f499cf22fdddb8f8
DIFF:
https://github.com/llvm/llvm-project/commit/7695f68612c300a6b539d251f499cf22fdddb8f8.diff
LOG: rebase
Created using spr 1.3.4
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 5241aa6e1c0eade..37158900d2404dd 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib
[llvm-branch-commits] [llvm] fac7c3d - [𝘀𝗽𝗿] changes introduced through rebase
Author: Jon Roelofs
Date: 2023-11-28T11:04:59-08:00
New Revision: fac7c3d46800fc109f257d42341b621d10a9ccb7
URL:
https://github.com/llvm/llvm-project/commit/fac7c3d46800fc109f257d42341b621d10a9ccb7
DIFF:
https://github.com/llvm/llvm-project/commit/fac7c3d46800fc109f257d42341b621d10a9ccb7.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 5241aa6e1c0eade..37158900d2404dd 100644
--- a/llvm/lib
[llvm-branch-commits] [llvm] [clang] [clang] Function Multi Versioning supports IFunc lowerings on Darwin platforms (PR #73688)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73688 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [clang] [clang] Function Multi Versioning supports IFunc lowerings on Darwin platforms (PR #73688)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73688 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] de74c62 - [𝘀𝗽𝗿] changes introduced through rebase
Author: Jon Roelofs
Date: 2023-11-28T11:05:25-08:00
New Revision: de74c62118d9c2c9372a6ba862113f299ac6eb3a
URL:
https://github.com/llvm/llvm-project/commit/de74c62118d9c2c9372a6ba862113f299ac6eb3a
DIFF:
https://github.com/llvm/llvm-project/commit/de74c62118d9c2c9372a6ba862113f299ac6eb3a.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp
b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 5241aa6e1c0eade..37158900d2404dd 100644
--- a/llvm/lib
[llvm-branch-commits] [llvm] 413e538 - rebase
Author: Jon Roelofs
Date: 2023-11-28T11:05:28-08:00
New Revision: 413e538a113187663f413d20c354e8018cddca30
URL:
https://github.com/llvm/llvm-project/commit/413e538a113187663f413d20c354e8018cddca30
DIFF:
https://github.com/llvm/llvm-project/commit/413e538a113187663f413d20c354e8018cddca30.diff
LOG: rebase
Created using spr 1.3.4
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h
b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 48fa6c478464c73..07b92871a0f0868 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -887,7 +887,6 @@ class AsmPrinter : public MachineFunctionPass {
virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
private:
-
/// This method decides whether the specified basic block requires a label.
bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const;
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 94e76a43bf38d6d..bd90047a411a654 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -959,7 +959,6 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
GlobalIFunc::getResolverFunctionType(GI.getValueType());
Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()),
"IFunc resolver has incorrect type", &GI);
-
}
void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
@@ -2240,7 +2239,8 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
}
// Check EVEX512 feature.
- if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
TT.isX86()) {
+ if (MaxParameterWidth >= 512 && Attrs.hasFnAttr("target-features") &&
+ TT.isX86()) {
StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
"512-bit vector arguments require 'evex512' for AVX512", V);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 2dab8e126c9abd0..f4128332008fb83 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -71,10 +71,15 @@ using namespace llvm;
namespace {
-enum class IFuncLowering { SymbolResolverIfSupported, SymbolResolverAlways,
SymbolResolverNever };
+enum class IFuncLowering {
+ SymbolResolverIfSupported,
+ SymbolResolverAlways,
+ SymbolResolverNever
+};
static cl::opt PreferredIFuncLowering(
-"arm64-darwin-ifunc-symbol_resolver",
cl::init(IFuncLowering::SymbolResolverNever),
+"arm64-darwin-ifunc-symbol_resolver",
+cl::init(IFuncLowering::SymbolResolverNever),
cl::desc("Pick the lowering for ifuncs on darwin platforms"), cl::Hidden,
cl::values(
clEnumValN(
@@ -1853,8 +1858,8 @@ void AArch64AsmPrinter::emitLinkerSymbolResolver(Module
&M,
OutStreamer->emitSymbolAttribute(Name, MCSA_SymbolResolver);
emitVisibility(Name, GI.getVisibility());
- // ld-prime does not seem to support aliases of symbol resolvers, so we have
to
- // tail call the resolver manually.
+ // ld-prime does not seem to support aliases of symbol resolvers, so we have
+ // to tail call the resolver manually.
OutStreamer->emitInstruction(
MCInstBuilder(AArch64::B)
.addOperand(MCOperand::createExpr(lowerConstant(GI.getResolver(,
@@ -1887,8 +1892,9 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
assert(GI.hasLocalLinkage() && "Invalid ifunc linkage");
};
- MCSymbol *LazyPointer =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
- "_" + GI.getName() + ".lazy_pointer");
+ MCSymbol *LazyPointer =
+ TM.getObjFileLowering()->getContext().getOrCreateSymbol(
+ "_" + GI.getName() + ".lazy_pointer");
MCSymbol *StubHelper =
TM.getObjFileLowering()->getContext().getOrCreateSymbol(
"_" + GI.getName() + ".stub_helper");
@@ -1943,9 +1949,10 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
}
OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRXui)
-.addReg(AArch64::X16)
-.addReg(AArch64::X16)
-.addImm(0), *STI);
+ .addReg(AArch64::X16)
+ .addReg(AArch64::X16)
+ .addImm(0),
+ *STI);
OutStreamer->emitInstruction(MCInstBuilder(TM.getTargetTriple().isArm64e()
? AArch64::BRAAZ
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [llvm] [clang] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73685 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [compiler-rt] [clang] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
https://github.com/jroelofs edited https://github.com/llvm/llvm-project/pull/73685 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] a03c81b - Fix review comments and squash tests
Author: Andrés Villegas
Date: 2023-11-28T21:17:10Z
New Revision: a03c81be070eccb0e064af314d02216e76bab854
URL:
https://github.com/llvm/llvm-project/commit/a03c81be070eccb0e064af314d02216e76bab854
DIFF:
https://github.com/llvm/llvm-project/commit/a03c81be070eccb0e064af314d02216e76bab854.diff
LOG: Fix review comments and squash tests
Created using spr 1.3.4
Added:
compiler-rt/test/sanitizer_common/TestCases/print-stack-trace-markup.cpp
Modified:
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
Removed:
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
index fe9933e942eba55..cbd111e975781a3 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
@@ -19,7 +19,6 @@
#include "sanitizer_symbolizer_markup.h"
#include "sanitizer_common.h"
-#include "sanitizer_stacktrace_printer.h"
#include "sanitizer_symbolizer.h"
#include "sanitizer_symbolizer_markup_constants.h"
@@ -73,13 +72,6 @@ const char *MarkupSymbolizerTool::Demangle(const char *name)
{
// symbolization and pretty-print the markup.
#if !SANITIZER_FUCHSIA
-// Simplier view of a LoadedModule. It only holds information necessary to
-// identify unique modules.
-struct RenderedModule {
- char *full_name;
- uptr base_address;
- u8 uuid[kModuleUUIDSize]; // BuildId
-};
static bool ModulesEq(const LoadedModule &module,
const RenderedModule &renderedModule) {
@@ -136,39 +128,31 @@ static void RenderMmaps(InternalScopedString *buffer,
}
void MarkupStackTracePrinter::RenderContext(InternalScopedString *buffer) {
- // Keeps track of the modules that have been rendered.
- static bool initialized = false;
- static InternalMmapVectorNoCtor renderedModules;
- if (!initialized) {
-// arbitrary initial size, counting the main module plus some important
libs
-// like libc.
-renderedModules.Initialize(3);
-initialized = true;
- }
-
- if (renderedModules.size() == 0)
+ if (renderedModules_.size() == 0)
buffer->Append("{{{reset}}}\n");
const auto &modules = Symbolizer::GetOrInit()->GetRefreshedListOfModules();
for (const auto &module : modules) {
-if (ModuleHasBeenRendered(module, renderedModules))
+if (ModuleHasBeenRendered(module, renderedModules_))
continue;
// symbolizer markup id, used to refer to this modules from other
contextual
// elements
-uptr moduleId = renderedModules.size();
+uptr moduleId = renderedModules_.size();
RenderModule(buffer, module, moduleId);
RenderMmaps(buffer, module, moduleId);
-RenderedModule renderedModule{
-internal_strdup(module.full_name()), module.base_address(), {}};
+renderedModules_.push_back({
+internal_strdup(module.full_name()),
+module.base_address(),
+{},
+});
// kModuleUUIDSize is the size of curModule.uuid
CHECK_GE(kModuleUUIDSize, module.uuid_size());
-internal_memcpy(renderedModule.uuid, module.uuid(), module.uuid_size());
-renderedModules.push_back(renderedModule);
+internal_memcpy(renderedModules_.back().uuid, module.uuid(),
module.uuid_size());
}
}
#endif // !SANITIZER_FUCHSIA
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
index 07630d0b3bdf417..bc2ab24d625bb5a 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
@@ -20,6 +20,14 @@
namespace __sanitizer {
+// Simplier view of a LoadedModule. It only holds information necessary to
+// identify unique modules.
+struct RenderedModule {
+ char *full_name;
+ uptr base_address;
+ u8 uuid[kModuleUUIDSize]; // BuildId
+};
+
class MarkupStackTracePrinter : public StackTracePrinter {
public:
// We don't support the stack_trace_format flag at all.
@@ -35,6 +43,9 @@ class MarkupStackTracePrinter : public StackTracePrinter {
const char *strip_path_prefix = "") override;
private:
+ // Keeps track of the modules that have been rendered to avoid re-rendering
+ // them
+ InternalMmapVector renderedModules_;
void RenderContext(InternalScopedString *buffer);
protected:
diff --git
a/compiler-rt/test/sanitizer_common/TestCases/print-stack-trace-markup.cpp
b/compiler-rt/test/sanitizer_common/TestCases/print-stack-trace-markup.cpp
new file mode 100644
index 000..15d89d091a99e33
--- /dev/null
+++ b/compiler-rt/test/sanitizer_common/TestCases/print-stack-trace-markup.cpp
@@ -0,0 +1,38 @@
+// RUN: %clangxx %s -o %t
+// RUN: %env_tool_opts=enable_symbolizer_markup=1 %run %t 2
[llvm-branch-commits] [compiler-rt] [mlir] [libc] [clang] [llvm] [clang-tools-extra] [flang] [libcxx] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
https://github.com/avillega closed https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [libcxx] [clang] [mlir] [compiler-rt] [llvm] [flang] [libc] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
avillega wrote: I've squashed this test into the change that introduces the Rendering of Contextual elements #73194 https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] 5331cd8 - run git clang-format
Author: Andrés Villegas
Date: 2023-11-28T21:23:29Z
New Revision: 5331cd8d7b873d79b516c2e47272d705d73e695d
URL:
https://github.com/llvm/llvm-project/commit/5331cd8d7b873d79b516c2e47272d705d73e695d
DIFF:
https://github.com/llvm/llvm-project/commit/5331cd8d7b873d79b516c2e47272d705d73e695d.diff
LOG: run git clang-format
Created using spr 1.3.4
Added:
Modified:
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
Removed:
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
index cbd111e975781a3..b2a1069a9a61cc1 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
@@ -72,7 +72,6 @@ const char *MarkupSymbolizerTool::Demangle(const char *name) {
// symbolization and pretty-print the markup.
#if !SANITIZER_FUCHSIA
-
static bool ModulesEq(const LoadedModule &module,
const RenderedModule &renderedModule) {
return module.base_address() == renderedModule.base_address &&
@@ -152,7 +151,8 @@ void
MarkupStackTracePrinter::RenderContext(InternalScopedString *buffer) {
// kModuleUUIDSize is the size of curModule.uuid
CHECK_GE(kModuleUUIDSize, module.uuid_size());
-internal_memcpy(renderedModules_.back().uuid, module.uuid(),
module.uuid_size());
+internal_memcpy(renderedModules_.back().uuid, module.uuid(),
+module.uuid_size());
}
}
#endif // !SANITIZER_FUCHSIA
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] dc1fcb4 - avoid writeback stp's
Author: Jon Roelofs
Date: 2023-11-28T14:24:45-08:00
New Revision: dc1fcb464e3d9e8dd37a5bda1aa8894e127654e9
URL:
https://github.com/llvm/llvm-project/commit/dc1fcb464e3d9e8dd37a5bda1aa8894e127654e9
DIFF:
https://github.com/llvm/llvm-project/commit/dc1fcb464e3d9e8dd37a5bda1aa8894e127654e9.diff
LOG: avoid writeback stp's
Created using spr 1.3.4
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-16]
+ // sub fp, sp, 16
[llvm-branch-commits] [llvm] 3b44869 - [𝘀𝗽𝗿] changes introduced through rebase
Author: Jon Roelofs
Date: 2023-11-28T14:24:48-08:00
New Revision: 3b44869576897de5613e65fa85b867cdc21151d0
URL:
https://github.com/llvm/llvm-project/commit/3b44869576897de5613e65fa85b867cdc21151d0
DIFF:
https://github.com/llvm/llvm-project/commit/3b44869576897de5613e65fa85b867cdc21151d0.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-1
[llvm-branch-commits] [llvm] 8d9c2a2 - rebase
Author: Jon Roelofs
Date: 2023-11-28T14:24:53-08:00
New Revision: 8d9c2a2d30b69f9b4e4411f8bf74117303bea94e
URL:
https://github.com/llvm/llvm-project/commit/8d9c2a2d30b69f9b4e4411f8bf74117303bea94e
DIFF:
https://github.com/llvm/llvm-project/commit/8d9c2a2d30b69f9b4e4411f8bf74117303bea94e.diff
LOG: rebase
Created using spr 1.3.4
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-16]
+ // sub fp, sp, 16
+ // stp
[llvm-branch-commits] [llvm] 27dccd2 - rebase
Author: Jon Roelofs
Date: 2023-11-28T14:24:58-08:00
New Revision: 27dccd2b646ac953d0cf5489324d272db147ac3f
URL:
https://github.com/llvm/llvm-project/commit/27dccd2b646ac953d0cf5489324d272db147ac3f
DIFF:
https://github.com/llvm/llvm-project/commit/27dccd2b646ac953d0cf5489324d272db147ac3f.diff
LOG: rebase
Created using spr 1.3.4
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-16]
+ // sub fp, sp, 16
+ // stp
[llvm-branch-commits] [clang] [llvm] [clang] Support __attribute__((ifunc(...))) on Darwin platforms (PR #73687)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73687 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [clang] Support __attribute__((ifunc(...))) on Darwin platforms (PR #73687)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73687 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 9375c35 - [𝘀𝗽𝗿] changes introduced through rebase
Author: Jon Roelofs
Date: 2023-11-28T14:24:56-08:00
New Revision: 9375c350abda40537ca1db27d2bde3fffb067f90
URL:
https://github.com/llvm/llvm-project/commit/9375c350abda40537ca1db27d2bde3fffb067f90
DIFF:
https://github.com/llvm/llvm-project/commit/9375c350abda40537ca1db27d2bde3fffb067f90.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-1
[llvm-branch-commits] [llvm] 9c8c292 - rebase
Author: Jon Roelofs
Date: 2023-11-28T14:25:02-08:00
New Revision: 9c8c292266cc805a567fa844871e3424429f1bc3
URL:
https://github.com/llvm/llvm-project/commit/9c8c292266cc805a567fa844871e3424429f1bc3
DIFF:
https://github.com/llvm/llvm-project/commit/9c8c292266cc805a567fa844871e3424429f1bc3.diff
LOG: rebase
Created using spr 1.3.4
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-16]
+ // sub fp, sp, 16
+ // stp
[llvm-branch-commits] [llvm] [clang] [clang] Function Multi Versioning supports IFunc lowerings on Darwin platforms (PR #73688)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73688 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [clang] [clang] Function Multi Versioning supports IFunc lowerings on Darwin platforms (PR #73688)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73688 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [clang] [llvm] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73685 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] a34d63c - [𝘀𝗽𝗿] changes introduced through rebase
Author: Jon Roelofs
Date: 2023-11-28T14:25:01-08:00
New Revision: a34d63cab61b3d7bd327b6a90ee4b9e3ed568e85
URL:
https://github.com/llvm/llvm-project/commit/a34d63cab61b3d7bd327b6a90ee4b9e3ed568e85
DIFF:
https://github.com/llvm/llvm-project/commit/a34d63cab61b3d7bd327b6a90ee4b9e3ed568e85.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/test/CodeGen/AArch64/addrsig-macho.ll
llvm/test/CodeGen/AArch64/ifunc-asm.ll
Removed:
llvm/test/Verifier/ifunc-macho.ll
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 15ff39883680369..b4ac0a70e7fde9c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2300,6 +2300,32 @@ bool AsmPrinter::doFinalization(Module &M) {
// through user plugins.
emitStackMaps();
+ // Print aliases in topological order, that is, for each alias a = b,
+ // b must be printed before a.
+ // This is because on some targets (e.g. PowerPC) linker expects aliases in
+ // such an order to generate correct TOC information.
+ SmallVector AliasStack;
+ SmallPtrSet AliasVisited;
+ for (const auto &Alias : M.aliases()) {
+if (Alias.hasAvailableExternallyLinkage())
+ continue;
+for (const GlobalAlias *Cur = &Alias; Cur;
+ Cur = dyn_cast(Cur->getAliasee())) {
+ if (!AliasVisited.insert(Cur).second)
+break;
+ AliasStack.push_back(Cur);
+}
+for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
+ emitGlobalAlias(M, *AncestorAlias);
+AliasStack.clear();
+ }
+
+ // IFuncs must come before deubginfo in case the backend decides to emit them
+ // as actual functions, since on MachO targets, we cannot create regular
+ // sections after DWARF.
+ for (const auto &IFunc : M.ifuncs())
+emitGlobalIFunc(M, IFunc);
+
// Finalize debug and EH information.
for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
@@ -2339,28 +2365,6 @@ bool AsmPrinter::doFinalization(Module &M) {
}
}
- // Print aliases in topological order, that is, for each alias a = b,
- // b must be printed before a.
- // This is because on some targets (e.g. PowerPC) linker expects aliases in
- // such an order to generate correct TOC information.
- SmallVector AliasStack;
- SmallPtrSet AliasVisited;
- for (const auto &Alias : M.aliases()) {
-if (Alias.hasAvailableExternallyLinkage())
- continue;
-for (const GlobalAlias *Cur = &Alias; Cur;
- Cur = dyn_cast(Cur->getAliasee())) {
- if (!AliasVisited.insert(Cur).second)
-break;
- AliasStack.push_back(Cur);
-}
-for (const GlobalAlias *AncestorAlias : llvm::reverse(AliasStack))
- emitGlobalAlias(M, *AncestorAlias);
-AliasStack.clear();
- }
- for (const auto &IFunc : M.ifuncs())
-emitGlobalIFunc(M, IFunc);
-
GCModuleInfo *MI = getAnalysisIfAvailable();
assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index e0080b145d4f995..ce736178afc8b5a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -147,7 +147,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
if (const GlobalIFunc *IF = dyn_cast(CalleeV);
IF && MF.getTarget().getTargetTriple().isOSBinFormatMachO()) {
// ld64 requires that .symbol_resolvers to be called via a stub, so these
-// must always be a diret call.
+// must always be a direct call.
Info.Callee = MachineOperand::CreateGA(IF, 0);
} else if (const Function *F = dyn_cast(CalleeV))
Info.Callee = MachineOperand::CreateGA(F, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f4128332008fb83..26b3a14e22b2ad9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1965,65 +1965,71 @@ void AArch64AsmPrinter::emitManualSymbolResolver(Module
&M,
OutStreamer->emitLabel(StubHelper);
emitVisibility(StubHelper, GI.getVisibility());
- // stp fp, lr, [sp, #-16]!
- // mov fp, sp
- // stp x1, x0, [sp, #-16]!
- // stp x3, x2, [sp, #-16]!
- // stp x5, x4, [sp, #-16]!
- // stp x7, x6, [sp, #-16]!
- // stp d1, d0, [sp, #-16]!
- // stp d3, d2, [sp, #-16]!
- // stp d5, d4, [sp, #-16]!
- // stp d7, d6, [sp, #-16]!
+ // stp fp, lr, [sp, #-1
[llvm-branch-commits] [clang] [compiler-rt] [llvm] [builtins][arm64] Build __init_cpu_features_resolver on Apple platforms (PR #73685)
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/73685 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [msan] Intercept mallinfo2 (PR #73729)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/73729 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [msan] Intercept mallinfo2 (PR #73729)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/73729.diff
3 Files Affected:
- (modified) compiler-rt/lib/msan/msan_interceptors.cpp (+10)
- (modified) compiler-rt/lib/sanitizer_common/sanitizer_mallinfo.h (+4)
- (modified) compiler-rt/test/msan/Linux/mallinfo.cpp (+3)
``diff
diff --git a/compiler-rt/lib/msan/msan_interceptors.cpp
b/compiler-rt/lib/msan/msan_interceptors.cpp
index dfecf6f7c470a6c..680b7d397ff0622 100644
--- a/compiler-rt/lib/msan/msan_interceptors.cpp
+++ b/compiler-rt/lib/msan/msan_interceptors.cpp
@@ -260,9 +260,18 @@ INTERCEPTOR(__sanitizer_struct_mallinfo, mallinfo) {
return sret;
}
+// Interceptor relies on NRVO and assumes that sret will be pre-allocated in
+// caller frame.
+INTERCEPTOR(__sanitizer_struct_mallinfo2, mallinfo2) {
+ __sanitizer_struct_mallinfo2 sret;
+ clear_mallinfo(&sret);
+ return sret;
+}
# define MSAN_MAYBE_INTERCEPT_MALLINFO INTERCEPT_FUNCTION(mallinfo)
+# define MSAN_MAYBE_INTERCEPT_MALLINFO2 INTERCEPT_FUNCTION(mallinfo2)
#else
#define MSAN_MAYBE_INTERCEPT_MALLINFO
+# define MSAN_MAYBE_INTERCEPT_MALLINFO2
#endif
#if !SANITIZER_FREEBSD && !SANITIZER_NETBSD
@@ -1787,6 +1796,7 @@ void InitializeInterceptors() {
MSAN_MAYBE_INTERCEPT_CFREE;
MSAN_MAYBE_INTERCEPT_MALLOC_USABLE_SIZE;
MSAN_MAYBE_INTERCEPT_MALLINFO;
+ MSAN_MAYBE_INTERCEPT_MALLINFO2;
MSAN_MAYBE_INTERCEPT_MALLOPT;
MSAN_MAYBE_INTERCEPT_MALLOC_STATS;
INTERCEPT_FUNCTION(fread);
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_mallinfo.h
b/compiler-rt/lib/sanitizer_common/sanitizer_mallinfo.h
index 4e58c02df835190..1c07e68e55a7d3b 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_mallinfo.h
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_mallinfo.h
@@ -31,6 +31,10 @@ struct __sanitizer_struct_mallinfo {
int v[10];
};
+struct __sanitizer_struct_mallinfo2 {
+ uptr v[10];
+};
+
#endif
} // namespace __sanitizer
diff --git a/compiler-rt/test/msan/Linux/mallinfo.cpp
b/compiler-rt/test/msan/Linux/mallinfo.cpp
index 3c3692969852f9b..f061218c615a3a9 100644
--- a/compiler-rt/test/msan/Linux/mallinfo.cpp
+++ b/compiler-rt/test/msan/Linux/mallinfo.cpp
@@ -8,5 +8,8 @@
int main(void) {
struct mallinfo mi = mallinfo();
assert(__msan_test_shadow(&mi, sizeof(mi)) == -1);
+
+ struct mallinfo2 mi2 = mallinfo2();
+ assert(__msan_test_shadow(&mi2, sizeof(mi2)) == -1);
return 0;
}
``
https://github.com/llvm/llvm-project/pull/73729
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[llvm-branch-commits] [mlir] 79ce123 - Revert "[mlir] Re-Add mlirTranslateModuleToLLVMIR to MLIR-C (#73627)"
Author: Vitaly Buka
Date: 2023-11-28T21:01:09-08:00
New Revision: 79ce1233af3eeac04e1e7f683da267a7005b37aa
URL:
https://github.com/llvm/llvm-project/commit/79ce1233af3eeac04e1e7f683da267a7005b37aa
DIFF:
https://github.com/llvm/llvm-project/commit/79ce1233af3eeac04e1e7f683da267a7005b37aa.diff
LOG: Revert "[mlir] Re-Add mlirTranslateModuleToLLVMIR to MLIR-C (#73627)"
This reverts commit 523160555925ff451e7c6d213a377d191e514805.
Added:
Modified:
mlir/lib/CAPI/CMakeLists.txt
mlir/test/CAPI/CMakeLists.txt
mlir/test/CMakeLists.txt
mlir/test/lit.cfg.py
Removed:
mlir/include/mlir-c/Target/LLVMIR.h
mlir/lib/CAPI/Target/CMakeLists.txt
mlir/lib/CAPI/Target/LLVMIR.cpp
mlir/test/CAPI/translation.c
diff --git a/mlir/include/mlir-c/Target/LLVMIR.h
b/mlir/include/mlir-c/Target/LLVMIR.h
deleted file mode 100644
index effa74b905ce66b..000
--- a/mlir/include/mlir-c/Target/LLVMIR.h
+++ /dev/null
@@ -1,39 +0,0 @@
-//===-- LLVMIR.h - C Interface for MLIR LLVMIR Target -*- C
-*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM
-// Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-//
-// This header declares the C interface to target LLVMIR with MLIR.
-//
-//===--===//
-
-#ifndef MLIR_C_TARGET_LLVMIR_H
-#define MLIR_C_TARGET_LLVMIR_H
-
-#include "mlir-c/IR.h"
-#include "mlir-c/Support.h"
-#include "llvm-c/Support.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// Translate operation that satisfies LLVM dialect module requirements into an
-/// LLVM IR module living in the given context. This translates operations from
-/// any dilalect that has a registered implementation of
-/// LLVMTranslationDialectInterface.
-///
-/// \returns the generated LLVM IR Module from the translated MLIR module, it
is
-/// owned by the caller.
-MLIR_CAPI_EXPORTED LLVMModuleRef
-mlirTranslateModuleToLLVMIR(MlirOperation module, LLVMContextRef context);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // MLIR_C_TARGET_LLVMIR_H
diff --git a/mlir/lib/CAPI/CMakeLists.txt b/mlir/lib/CAPI/CMakeLists.txt
index 6c438508425b7c3..707e78ac3d1ea3c 100644
--- a/mlir/lib/CAPI/CMakeLists.txt
+++ b/mlir/lib/CAPI/CMakeLists.txt
@@ -14,7 +14,6 @@ add_subdirectory(Interfaces)
add_subdirectory(IR)
add_subdirectory(RegisterEverything)
add_subdirectory(Transforms)
-add_subdirectory(Target)
if(MLIR_ENABLE_EXECUTION_ENGINE)
add_subdirectory(ExecutionEngine)
@@ -37,3 +36,4 @@ if(MLIR_BUILD_MLIR_C_DYLIB)
endif()
endif()
endif()
+
diff --git a/mlir/lib/CAPI/Target/CMakeLists.txt
b/mlir/lib/CAPI/Target/CMakeLists.txt
deleted file mode 100644
index ce86fd3def964cb..000
--- a/mlir/lib/CAPI/Target/CMakeLists.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-add_mlir_upstream_c_api_library(MLIRCAPITarget
- LLVMIR.cpp
-
- LINK_COMPONENTS
- Core
-
- LINK_LIBS PUBLIC
- MLIRToLLVMIRTranslationRegistration
- MLIRCAPIIR
- MLIRLLVMToLLVMIRTranslation
- MLIRSupport
-)
diff --git a/mlir/lib/CAPI/Target/LLVMIR.cpp b/mlir/lib/CAPI/Target/LLVMIR.cpp
deleted file mode 100644
index dc798372be74679..000
--- a/mlir/lib/CAPI/Target/LLVMIR.cpp
+++ /dev/null
@@ -1,36 +0,0 @@
-//===-- LLVMIR.h - C Interface for MLIR LLVMIR Target
-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM
-// Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-
-#include "mlir-c/Target/LLVMIR.h"
-#include "llvm-c/Support.h"
-
-#include "llvm/IR/LLVMContext.h"
-#include "llvm/IR/Module.h"
-#include
-
-#include "mlir/CAPI/IR.h"
-#include "mlir/CAPI/Support.h"
-#include "mlir/CAPI/Wrap.h"
-#include "mlir/Target/LLVMIR/ModuleTranslation.h"
-
-using namespace mlir;
-
-LLVMModuleRef mlirTranslateModuleToLLVMIR(MlirOperation module,
- LLVMContextRef context) {
- Operation *moduleOp = unwrap(module);
-
- llvm::LLVMContext *ctx = llvm::unwrap(context);
-
- std::unique_ptr llvmModule =
- mlir::translateModuleToLLVMIR(moduleOp, *ctx);
-
- LLVMModuleRef moduleRef = llvm::wrap(llvmModule.release());
-
- return moduleRef;
-}
diff --git a/mlir/test/CAPI/CMakeLists.txt b/mlir/test/CAPI/CMakeLists.txt
index 1096a3b08066483..16a3d0ed9c62fbf 100644
--- a/mlir/test/CAPI/CMakeLists.txt
+++ b/mlir/test/CAPI/CMakeLists.txt
@@ -85,12 +85,3 @@ _add_capi_test_executable(mlir-capi-transform-test
MLIRCAPIRegisterEverything
MLIRCAPITransformDialect
)
-
-_add_capi_test_executable(mlir-capi-translation-test
- translati
[llvm-branch-commits] [llvm] eae1811 - [docs] Fix issues in SourceLevelDebugging (#73528)
Author: Felipe de Azevedo Piovezan Date: 2023-11-27T15:27:58-08:00 New Revision: eae1811e4f0431ea6336e68a38318a55f7529ef6 URL: https://github.com/llvm/llvm-project/commit/eae1811e4f0431ea6336e68a38318a55f7529ef6 DIFF: https://github.com/llvm/llvm-project/commit/eae1811e4f0431ea6336e68a38318a55f7529ef6.diff LOG: [docs] Fix issues in SourceLevelDebugging (#73528) An SSA register `value` was being defined twice. An "external" link was using the "internal" link syntax. Added: Modified: llvm/docs/SourceLevelDebugging.rst Removed: diff --git a/llvm/docs/SourceLevelDebugging.rst b/llvm/docs/SourceLevelDebugging.rst index da3466a7f51c5fa..e1df7c355ee0921 100644 --- a/llvm/docs/SourceLevelDebugging.rst +++ b/llvm/docs/SourceLevelDebugging.rst @@ -641,7 +641,7 @@ And has the following operands: operand of the ``DBG_VALUE`` instruction above. These variable location operands are inserted into the final DWARF Expression in positions indicated by the DW_OP_LLVM_arg operator in the `DIExpression - `. + `_. The position at which the DBG_VALUEs are inserted should correspond to the positions of their matching ``llvm.dbg.value`` intrinsics in the IR block. As @@ -841,7 +841,7 @@ presents several diff iculties: falsebr: call void @llvm.dbg.value(metadata i32 %input, metadata !30, metadata !DIExpression()), !dbg !24 call void @llvm.dbg.value(metadata i32 2, metadata !23, metadata !DIExpression()), !dbg !24 -%value = add i32 %input, 2 +%value2 = add i32 %input, 2 br label %bb1 exit: ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 8cd7184 - [gn] port 12bb2910c3e3
Author: Nico Weber
Date: 2023-11-28T08:33:41+09:00
New Revision: 8cd7184dc0f1e5e28e39b03c90bc9aeee96d104f
URL:
https://github.com/llvm/llvm-project/commit/8cd7184dc0f1e5e28e39b03c90bc9aeee96d104f
DIFF:
https://github.com/llvm/llvm-project/commit/8cd7184dc0f1e5e28e39b03c90bc9aeee96d104f.diff
LOG: [gn] port 12bb2910c3e3
Added:
Modified:
llvm/utils/gn/secondary/libcxx/include/BUILD.gn
llvm/utils/gn/secondary/libcxx/src/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
index 5017c2888a14093..4a7105f8253234e 100644
--- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
@@ -989,22 +989,12 @@ if (current_toolchain == default_toolchain) {
"experimental/__simd/traits.h",
"experimental/__simd/utility.h",
"experimental/__simd/vec_ext.h",
- "experimental/deque",
- "experimental/forward_list",
"experimental/iterator",
- "experimental/list",
- "experimental/map",
- "experimental/memory_resource",
+ "experimental/memory",
"experimental/propagate_const",
- "experimental/regex",
- "experimental/set",
"experimental/simd",
- "experimental/string",
"experimental/type_traits",
- "experimental/unordered_map",
- "experimental/unordered_set",
"experimental/utility",
- "experimental/vector",
"ext/__hash",
"ext/hash_map",
"ext/hash_set",
diff --git a/llvm/utils/gn/secondary/libcxx/src/BUILD.gn
b/llvm/utils/gn/secondary/libcxx/src/BUILD.gn
index b50e9278e04538f..3cd6e9ef26cb421 100644
--- a/llvm/utils/gn/secondary/libcxx/src/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/src/BUILD.gn
@@ -307,7 +307,7 @@ if (libcxx_enable_experimental) {
static_library("cxx_experimental") {
output_dir = runtimes_dir
output_name = "c++experimental"
-sources = [ "experimental/memory_resource.cpp" ]
+sources = [ "experimental/keep.cpp" ]
if (libcxx_enable_filesystem && libcxx_enable_time_zone_database) {
sources += [
"tz.cpp",
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[llvm-branch-commits] [llvm] ed65602 - [gn] add a bunch of missing libc++ headers
Author: Nico Weber
Date: 2023-11-28T08:40:19+09:00
New Revision: ed6560240d5b0e2faa993e86d0ded0f5be0c8d19
URL:
https://github.com/llvm/llvm-project/commit/ed6560240d5b0e2faa993e86d0ded0f5be0c8d19
DIFF:
https://github.com/llvm/llvm-project/commit/ed6560240d5b0e2faa993e86d0ded0f5be0c8d19.diff
LOG: [gn] add a bunch of missing libc++ headers
Ports:
* fcaccf817d31d (mdspan)
* 73d94b1916135 (source_location)
* b77e50e6aef56 (stop_token)
* 7cc72a0a2ec22 (syncstream)
Added:
Modified:
llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
index 4a7105f8253234e..c698338792e22be 100644
--- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
@@ -1021,6 +1021,7 @@ if (current_toolchain == default_toolchain) {
"locale.h",
"map",
"math.h",
+ "mdspan",
"memory",
"memory_resource",
"mutex",
@@ -1039,6 +1040,7 @@ if (current_toolchain == default_toolchain) {
"semaphore",
"set",
"shared_mutex",
+ "source_location",
"span",
"sstream",
"stack",
@@ -1049,11 +1051,13 @@ if (current_toolchain == default_toolchain) {
"stdint.h",
"stdio.h",
"stdlib.h",
+ "stop_token",
"streambuf",
"string",
"string.h",
"string_view",
"strstream",
+ "syncstream",
"system_error",
"tgmath.h",
"thread",
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[llvm-branch-commits] [llvm] be1e8a6 - [gn] port 12bb2910c3e3 more
Author: Nico Weber
Date: 2023-11-28T08:43:16+09:00
New Revision: be1e8a659df5003fa74e1f55c40acf3667f3cdb9
URL:
https://github.com/llvm/llvm-project/commit/be1e8a659df5003fa74e1f55c40acf3667f3cdb9
DIFF:
https://github.com/llvm/llvm-project/commit/be1e8a659df5003fa74e1f55c40acf3667f3cdb9.diff
LOG: [gn] port 12bb2910c3e3 more
Added:
Modified:
llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
index c698338792e22be..0e878ab39ce93ba 100644
--- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
@@ -62,11 +62,7 @@ if (current_toolchain == default_toolchain) {
output = "$libcxx_generated_include_dir/module.modulemap"
#no = "requires LIBCXX_CONFIGURED_WITHOUT_SUPPORT_FOR_THIS_HEADER"
-values = [
- # An empty value here means the feature is supported.
- # Unsupported values should be set to `$no`.
- "requires_LIBCXX_ENABLE_LOCALIZATION=",
-]
+values = []
}
copy("copy_headers") {
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[llvm-branch-commits] [llvm] b4cf014 - [RISCV][GISel] Select trap and debugtrap. (#73171)
Author: Craig Topper
Date: 2023-11-27T15:52:15-08:00
New Revision: b4cf014991bfa144306a1069ca5c1eabbb456ddd
URL:
https://github.com/llvm/llvm-project/commit/b4cf014991bfa144306a1069ca5c1eabbb456ddd
DIFF:
https://github.com/llvm/llvm-project/commit/b4cf014991bfa144306a1069ca5c1eabbb456ddd.diff
LOG: [RISCV][GISel] Select trap and debugtrap. (#73171)
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
Removed:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index f6527018d7ab828..d37026f00117995 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -71,6 +71,8 @@ class RISCVInstructionSelector : public InstructionSelector {
MachineRegisterInfo &MRI) const;
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
+ bool selectIntrinsicWithSideEffects(MachineInstr &MI, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI) const;
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
@@ -608,6 +610,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectSelect(MI, MIB, MRI);
case TargetOpcode::G_FCMP:
return selectFPCompare(MI, MIB, MRI);
+ case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+return selectIntrinsicWithSideEffects(MI, MIB, MRI);
default:
return false;
}
@@ -1060,6 +1064,29 @@ bool
RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
+MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
+ "Unexpected opcode");
+ // Find the intrinsic ID.
+ unsigned IntrinID = cast(MI).getIntrinsicID();
+
+ // Select the instruction.
+ switch (IntrinID) {
+ default:
+return false;
+ case Intrinsic::trap:
+MIB.buildInstr(RISCV::UNIMP, {}, {});
+break;
+ case Intrinsic::debugtrap:
+MIB.buildInstr(RISCV::EBREAK, {}, {});
+break;
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
new file mode 100644
index 000..11789a030e6fac0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:test_trap
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+; CHECK-LABEL: name: test_trap
+; CHECK: UNIMP
+; CHECK-NEXT: PseudoRET
+G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+PseudoRET
+
+...
+---
+name:test_debugtrap
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+; CHECK-LABEL: name: test_debugtrap
+; CHECK: EBREAK
+; CHECK-NEXT: PseudoRET
+G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.debugtrap)
+PseudoRET
+
+...
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[llvm-branch-commits] [lldb] a6c62bf - [lldb] try to fix build on linux after fc6b72523f3d7
Author: Nico Weber Date: 2023-11-28T08:53:05+09:00 New Revision: a6c62bf1a4717accc852463b664cd1012237d334 URL: https://github.com/llvm/llvm-project/commit/a6c62bf1a4717accc852463b664cd1012237d334 DIFF: https://github.com/llvm/llvm-project/commit/a6c62bf1a4717accc852463b664cd1012237d334.diff LOG: [lldb] try to fix build on linux after fc6b72523f3d7 Tries to fix: ../../lldb/source/Breakpoint/WatchpointResource.cpp:59:12: error: no member named 'find' in namespace 'std'; did you mean 'fill'? std::find(m_constituents.begin(), m_constituents.end(), wp_sp); ~^~~~ fill Added: Modified: lldb/source/Breakpoint/WatchpointResource.cpp Removed: diff --git a/lldb/source/Breakpoint/WatchpointResource.cpp b/lldb/source/Breakpoint/WatchpointResource.cpp index 4b8fbe42c865e25..d0f8dc346f3c024 100644 --- a/lldb/source/Breakpoint/WatchpointResource.cpp +++ b/lldb/source/Breakpoint/WatchpointResource.cpp @@ -10,6 +10,8 @@ #include "lldb/Breakpoint/WatchpointResource.h" +#include + using namespace lldb; using namespace lldb_private; ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 5623c44 - [gn build] Port 4e0c48b907f1
Author: LLVM GN Syncbot
Date: 2023-11-27T23:53:34Z
New Revision: 5623c44f08176cf7c1707786c65c55a20c7fa112
URL:
https://github.com/llvm/llvm-project/commit/5623c44f08176cf7c1707786c65c55a20c7fa112
DIFF:
https://github.com/llvm/llvm-project/commit/5623c44f08176cf7c1707786c65c55a20c7fa112.diff
LOG: [gn build] Port 4e0c48b907f1
Added:
Modified:
llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
index 0e878ab39ce93ba..0e3a264fc185728 100644
--- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
@@ -916,7 +916,6 @@ if (current_toolchain == default_toolchain) {
"__utility/integer_sequence.h",
"__utility/is_pointer_in_range.h",
"__utility/move.h",
- "__utility/no_destroy.h",
"__utility/pair.h",
"__utility/piecewise_construct.h",
"__utility/priority_tag.h",
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[llvm-branch-commits] [openmp] 77aa79d - [OpenMP][Docs] Cleanup libomptarget README
Author: Johannes Doerfert Date: 2023-11-27T16:02:33-08:00 New Revision: 77aa79d4fb646b9fd28176d3845117a6a2da6745 URL: https://github.com/llvm/llvm-project/commit/77aa79d4fb646b9fd28176d3845117a6a2da6745 DIFF: https://github.com/llvm/llvm-project/commit/77aa79d4fb646b9fd28176d3845117a6a2da6745.diff LOG: [OpenMP][Docs] Cleanup libomptarget README Added: Modified: openmp/libomptarget/README.txt Removed: diff --git a/openmp/libomptarget/README.txt b/openmp/libomptarget/README.txt index 8c0a83729fdbea3..4d30c102b7972d0 100644 --- a/openmp/libomptarget/README.txt +++ b/openmp/libomptarget/README.txt @@ -2,27 +2,8 @@ README for the LLVM* OpenMP* Offloading Runtime Library (libomptarget) == -How to Build the LLVM* OpenMP* Offloading Runtime Library (libomptarget) - -In-tree build: - -$ cd where-you-want-to-live -Check out openmp (libomptarget lives under ./libomptarget) into llvm/projects -$ cd where-you-want-to-build -$ mkdir build && cd build -$ cmake path/to/llvm -DCMAKE_C_COMPILER= -DCMAKE_CXX_COMPILER= -$ make omptarget - -Out-of-tree build: - -$ cd where-you-want-to-live -Check out openmp (libomptarget lives under ./libomptarget) -$ cd where-you-want-to-live/openmp/libomptarget -$ mkdir build && cd build -$ cmake path/to/openmp -DCMAKE_C_COMPILER= -DCMAKE_CXX_COMPILER= -$ make - -For details about building, please look at README.rst in the parent directory. +For details about building, please look at README.rst in the parent directory +and the build instructions as well as FAQ at https://openmp.llvm.org. Architectures Supported === @@ -34,40 +15,13 @@ following host architectures: * ARM(R) AArch64 architecture (little endian) The currently supported offloading device architectures are: -* Intel(R) 64 architecture (generic 64-bit plugin - mostly for testing purposes) -* IBM(R) Power architecture (big endian) (generic 64-bit plugin - mostly for testing purposes) -* IBM(R) Power architecture (little endian) (generic 64-bit plugin - mostly for testing purposes) -* ARM(R) AArch64 architecture (little endian) (generic 64-bit plugin - mostly for testing purposes) +* Intel(R) or AMD(R) 64-bit architecture (x86_64) +* IBM(R) Power architecture (big endian) +* IBM(R) Power architecture (little endian) +* ARM(R) AArch64 architecture (little endian) * CUDA(R) enabled 64-bit NVIDIA(R) GPU architectures - -Supported RTL Build Configurations -== -Supported Architectures: Intel(R) 64, IBM(R) Power 7 and Power 8 - - --- - | gcc | clang| ---||| -| Linux* OS | Yes(1)| Yes(2)| -- - -(1) gcc version 4.8.2 or later is supported. -(2) clang version 3.7 or later is supported. - - -Front-end Compilers that work with this RTL -=== - -The following compilers are known to do compatible code generation for -this RTL: - - clang (from https://github.com/clang-ykt ) - - clang (development branch at http://clang.llvm.org - several features still -under development) +* AMD(R) enabled 64-bit AMD(R) GPU architectures --- -Notices -=== -This library and related compiler support is still under development, so the -employed interface is likely to change in the future. - *Other names and brands may be claimed as the property of others. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 295bd6f - [gn build] Port fc6b72523f3d
Author: LLVM GN Syncbot
Date: 2023-11-27T23:53:35Z
New Revision: 295bd6fc4b91fec9eea5456cafb97c14c45107bb
URL:
https://github.com/llvm/llvm-project/commit/295bd6fc4b91fec9eea5456cafb97c14c45107bb
DIFF:
https://github.com/llvm/llvm-project/commit/295bd6fc4b91fec9eea5456cafb97c14c45107bb.diff
LOG: [gn build] Port fc6b72523f3d
Added:
Modified:
llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn
b/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn
index b8a06582e9856f5..84163e47b2b6c86 100644
--- a/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Breakpoint/BUILD.gn
@@ -29,12 +29,14 @@ static_library("Breakpoint") {
"BreakpointResolverName.cpp",
"BreakpointResolverScripted.cpp",
"BreakpointSite.cpp",
-"BreakpointSiteList.cpp",
+"StopPointSiteList.cpp",
"Stoppoint.cpp",
"StoppointCallbackContext.cpp",
"StoppointSite.cpp",
"Watchpoint.cpp",
"WatchpointList.cpp",
"WatchpointOptions.cpp",
+"WatchpointResource.cpp",
+"WatchpointResourceList.cpp",
]
}
___
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[llvm-branch-commits] [openmp] 755e108 - [OpenMP][NFC] Remove unused variable
Author: Johannes Doerfert
Date: 2023-11-27T16:02:33-08:00
New Revision: 755e1088258b030cdd00cfa1b184c58fe41b4287
URL:
https://github.com/llvm/llvm-project/commit/755e1088258b030cdd00cfa1b184c58fe41b4287
DIFF:
https://github.com/llvm/llvm-project/commit/755e1088258b030cdd00cfa1b184c58fe41b4287.diff
LOG: [OpenMP][NFC] Remove unused variable
Added:
Modified:
openmp/libomptarget/DeviceRTL/src/Utils.cpp
Removed:
diff --git a/openmp/libomptarget/DeviceRTL/src/Utils.cpp
b/openmp/libomptarget/DeviceRTL/src/Utils.cpp
index b39465aaa2ace5f..7da4da4ab95e2fc 100644
--- a/openmp/libomptarget/DeviceRTL/src/Utils.cpp
+++ b/openmp/libomptarget/DeviceRTL/src/Utils.cpp
@@ -19,8 +19,6 @@
using namespace ompx;
-extern "C" [[gnu::weak]] int IsSPMDMode;
-
namespace impl {
bool isSharedMemPtr(const void *Ptr) { return false; }
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[llvm-branch-commits] [openmp] 30fbe73 - [OpenMP][NFC] Remove else after return
Author: Johannes Doerfert Date: 2023-11-27T16:02:33-08:00 New Revision: 30fbe73ba9c726acbe0658e4ea98f328724482e5 URL: https://github.com/llvm/llvm-project/commit/30fbe73ba9c726acbe0658e4ea98f328724482e5 DIFF: https://github.com/llvm/llvm-project/commit/30fbe73ba9c726acbe0658e4ea98f328724482e5.diff LOG: [OpenMP][NFC] Remove else after return Added: Modified: openmp/libomptarget/src/interface.cpp Removed: diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index ae9d1c597e15940..79f38ed1a43437f 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -319,9 +319,8 @@ EXTERN int __tgt_target_kernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, if (KernelArgs->Flags.NoWait) return targetKernel( Loc, DeviceId, NumTeams, ThreadLimit, HostPtr, KernelArgs); - else -return targetKernel(Loc, DeviceId, NumTeams, ThreadLimit, - HostPtr, KernelArgs); + return targetKernel(Loc, DeviceId, NumTeams, ThreadLimit, + HostPtr, KernelArgs); } /// Activates the record replay mechanism. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [openmp] d2636dc - [OpenMP][NFC] Fix diagnostic warnings
Author: Johannes Doerfert
Date: 2023-11-27T16:02:34-08:00
New Revision: d2636dc39043f6adda3a6797fc5b7966bd4cb2f0
URL:
https://github.com/llvm/llvm-project/commit/d2636dc39043f6adda3a6797fc5b7966bd4cb2f0
DIFF:
https://github.com/llvm/llvm-project/commit/d2636dc39043f6adda3a6797fc5b7966bd4cb2f0.diff
LOG: [OpenMP][NFC] Fix diagnostic warnings
Added:
Modified:
openmp/libomptarget/src/omptarget.cpp
Removed:
diff --git a/openmp/libomptarget/src/omptarget.cpp
b/openmp/libomptarget/src/omptarget.cpp
index 0da448fdbefa477..318fd77920f6f0e 100644
--- a/openmp/libomptarget/src/omptarget.cpp
+++ b/openmp/libomptarget/src/omptarget.cpp
@@ -71,7 +71,7 @@ int32_t AsyncInfoTy::runPostProcessing() {
// Clear the vector up until the last known function, since post-processing
// procedures might add new procedures themselves.
- const auto PrevBegin = PostProcessingFunctions.begin();
+ const auto *PrevBegin = PostProcessingFunctions.begin();
PostProcessingFunctions.erase(PrevBegin, PrevBegin + Size);
return OFFLOAD_SUCCESS;
@@ -297,8 +297,8 @@ void handleTargetOutcome(bool Success, ident_t *Loc) {
if (PM->RTLs.UsedRTLs.empty()) {
llvm::SmallVector Archs;
llvm::transform(PM->Images, std::back_inserter(Archs),
-[](const auto &x) {
- return !x.second.Arch ? "empty" : x.second.Arch;
+[](const auto &X) {
+ return !X.second.Arch ? "empty" : X.second.Arch;
});
FAILURE_MESSAGE(
"No images found compatible with the installed hardware. ");
@@ -473,7 +473,7 @@ void *targetLockExplicit(void *HostPtr, size_t Size, int
DeviceNum,
return NULL;
}
- void *rc = NULL;
+ void *RC = NULL;
if (!deviceIsReady(DeviceNum)) {
DP("%s returns NULL ptr\n", Name);
@@ -492,16 +492,16 @@ void *targetLockExplicit(void *HostPtr, size_t Size, int
DeviceNum,
DevicePtr = PM->Devices[DeviceNum].get();
}
- int32_t err = 0;
+ int32_t Err = 0;
if (DevicePtr->RTL->data_lock) {
-err = DevicePtr->RTL->data_lock(DeviceNum, HostPtr, Size, &rc);
-if (err) {
+Err = DevicePtr->RTL->data_lock(DeviceNum, HostPtr, Size, &RC);
+if (Err) {
DP("Could not lock ptr %p\n", HostPtr);
return nullptr;
}
}
- DP("%s returns device ptr " DPxMOD "\n", Name, DPxPTR(rc));
- return rc;
+ DP("%s returns device ptr " DPxMOD "\n", Name, DPxPTR(RC));
+ return RC;
}
void targetUnlockExplicit(void *HostPtr, int DeviceNum, const char *Name) {
@@ -1264,7 +1264,7 @@ class PrivateArgumentManagerTy {
FirstPrivateArgInfoTy(int Index, void *HstPtr, uint32_t Size,
uint32_t Alignment, uint32_t Padding,
- const map_var_info_t HstPtrName = nullptr)
+ map_var_info_t HstPtrName = nullptr)
: HstPtrBegin(reinterpret_cast(HstPtr)),
HstPtrEnd(HstPtrBegin + Size), Index(Index), Alignment(Alignment),
Size(Size), Padding(Padding), HstPtrName(HstPtrName) {}
@@ -1298,7 +1298,7 @@ class PrivateArgumentManagerTy {
/// Add a private argument
int addArg(void *HstPtr, int64_t ArgSize, int64_t ArgOffset,
bool IsFirstPrivate, void *&TgtPtr, int TgtArgsIndex,
- const map_var_info_t HstPtrName = nullptr,
+ map_var_info_t HstPtrName = nullptr,
const bool AllocImmediately = false) {
// If the argument is not first-private, or its size is greater than a
// predefined threshold, we will allocate memory and issue the transfer
@@ -1385,7 +1385,7 @@ class PrivateArgumentManagerTy {
assert(FirstPrivateArgSize != 0 &&
"FirstPrivateArgSize is 0 but FirstPrivateArgInfo is empty");
FirstPrivateArgBuffer.resize(FirstPrivateArgSize, 0);
- auto Itr = FirstPrivateArgBuffer.begin();
+ auto *Itr = FirstPrivateArgBuffer.begin();
// Copy all host data to this buffer
for (FirstPrivateArgInfoTy &Info : FirstPrivateArgInfo) {
// First pad the pointer as we (have to) pad it on the device too.
@@ -1725,10 +1725,10 @@ int target(ident_t *Loc, DeviceTy &Device, void
*HostPtr,
/// and informing the record-replayer of whether to store the output
/// in some file.
int target_activate_rr(DeviceTy &Device, uint64_t MemorySize, void *VAddr,
- bool isRecord, bool SaveOutput,
+ bool IsRecord, bool SaveOutput,
uint64_t &ReqPtrArgOffset) {
return Device.RTL->activate_record_replay(Device.DeviceID, MemorySize, VAddr,
-isRecord, SaveOutput,
+IsRecord, SaveOutput,
ReqPtrArgOffset);
}
___
llvm
[llvm-branch-commits] [openmp] e1f911e - [OpenMP][NFC] Simplify code
Author: Johannes Doerfert
Date: 2023-11-27T16:02:34-08:00
New Revision: e1f911e40ce6ad4a7f393ea1b33e65b24940eb84
URL:
https://github.com/llvm/llvm-project/commit/e1f911e40ce6ad4a7f393ea1b33e65b24940eb84
DIFF:
https://github.com/llvm/llvm-project/commit/e1f911e40ce6ad4a7f393ea1b33e65b24940eb84.diff
LOG: [OpenMP][NFC] Simplify code
Added:
Modified:
openmp/libomptarget/src/rtl.cpp
Removed:
diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp
index 3e2c0a64c9151fc..78076dd2c6db13d 100644
--- a/openmp/libomptarget/src/rtl.cpp
+++ b/openmp/libomptarget/src/rtl.cpp
@@ -403,33 +403,30 @@ void RTLsTy::registerRequires(int64_t Flags) {
void RTLsTy::initRTLonce(RTLInfoTy &R) {
// If this RTL is not already in use, initialize it.
- if (!R.IsUsed && R.NumberOfDevices != 0) {
-// Initialize the device information for the RTL we are about to use.
-const size_t Start = PM->Devices.size();
-PM->Devices.reserve(Start + R.NumberOfDevices);
-for (int32_t DeviceId = 0; DeviceId < R.NumberOfDevices; DeviceId++) {
- PM->Devices.push_back(std::make_unique(&R));
- // global device ID
- PM->Devices[Start + DeviceId]->DeviceID = Start + DeviceId;
- // RTL local device ID
- PM->Devices[Start + DeviceId]->RTLDeviceID = DeviceId;
-}
+ if (R.IsUsed || !R.NumberOfDevices)
+return;
-// Initialize the index of this RTL and save it in the used RTLs.
-R.Idx = (UsedRTLs.empty())
-? 0
-: UsedRTLs.back()->Idx + UsedRTLs.back()->NumberOfDevices;
-assert((size_t)R.Idx == Start &&
- "RTL index should equal the number of devices used so far.");
-R.IsUsed = true;
-UsedRTLs.push_back(&R);
+ // Initialize the device information for the RTL we are about to use.
+ const size_t Start = PM->Devices.size();
+ PM->Devices.reserve(Start + R.NumberOfDevices);
+ for (int32_t DeviceId = 0; DeviceId < R.NumberOfDevices; DeviceId++) {
+PM->Devices.push_back(std::make_unique(&R));
+// global device ID
+PM->Devices[Start + DeviceId]->DeviceID = Start + DeviceId;
+// RTL local device ID
+PM->Devices[Start + DeviceId]->RTLDeviceID = DeviceId;
+ }
-// If possible, set the device identifier offset
-if (R.set_device_offset)
- R.set_device_offset(Start);
+ // Initialize the index of this RTL and save it in the used RTLs.
+ R.Idx = Start;
+ R.IsUsed = true;
+ UsedRTLs.push_back(&R);
-DP("RTL " DPxMOD " has index %d!\n", DPxPTR(R.LibraryHandler.get()),
R.Idx);
- }
+ // If possible, set the device identifier offset
+ if (R.set_device_offset)
+R.set_device_offset(Start);
+
+ DP("RTL " DPxMOD " has index %d!\n", DPxPTR(R.LibraryHandler.get()), R.Idx);
}
void RTLsTy::initAllRTLs() {
___
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[llvm-branch-commits] [compiler-rt] 93a2be2 - [NFC sanitizer_symbolizer] Move Fuchsia specific code.
Author: Andres Villegas
Date: 2023-11-27T16:32:23-08:00
New Revision: 93a2be26e7cb54331033aad8f306bdbb5ef4b4c4
URL:
https://github.com/llvm/llvm-project/commit/93a2be26e7cb54331033aad8f306bdbb5ef4b4c4
DIFF:
https://github.com/llvm/llvm-project/commit/93a2be26e7cb54331033aad8f306bdbb5ef4b4c4.diff
LOG: [NFC sanitizer_symbolizer] Move Fuchsia specific code.
Moves sanitizer symbolizer code that is specific for
fuchsia into its own _fuchsia.cpp file.
This is preparation to enable symbolizer markup in
linux.
Reviewers: PiJoules, petrhosek, vitalybuka
Reviewed By: PiJoules, vitalybuka
Pull Request: https://github.com/llvm/llvm-project/pull/73192
Added:
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup_fuchsia.cpp
Modified:
compiler-rt/lib/sanitizer_common/CMakeLists.txt
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
Removed:
diff --git a/compiler-rt/lib/sanitizer_common/CMakeLists.txt
b/compiler-rt/lib/sanitizer_common/CMakeLists.txt
index 61e832a30eb3767..fb7584c298a1c94 100644
--- a/compiler-rt/lib/sanitizer_common/CMakeLists.txt
+++ b/compiler-rt/lib/sanitizer_common/CMakeLists.txt
@@ -88,6 +88,7 @@ set(SANITIZER_SYMBOLIZER_SOURCES
sanitizer_symbolizer_libcdep.cpp
sanitizer_symbolizer_mac.cpp
sanitizer_symbolizer_markup.cpp
+ sanitizer_symbolizer_markup_fuchsia.cpp
sanitizer_symbolizer_posix_libcdep.cpp
sanitizer_symbolizer_report.cpp
sanitizer_symbolizer_report_fuchsia.cpp
@@ -195,6 +196,7 @@ set(SANITIZER_IMPL_HEADERS
sanitizer_symbolizer_internal.h
sanitizer_symbolizer_libbacktrace.h
sanitizer_symbolizer_mac.h
+ sanitizer_symbolizer_markup.h
sanitizer_syscall_generic.inc
sanitizer_syscall_linux_aarch64.inc
sanitizer_syscall_linux_arm.inc
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
index c7332af7d9efd5a..c364e1e300225b9 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
@@ -8,105 +8,41 @@
//
// This file is shared between various sanitizers' runtime libraries.
//
-// Implementation of offline markup symbolizer.
-//===--===//
-
-#include "sanitizer_platform.h"
-
-#if SANITIZER_SYMBOLIZER_MARKUP
-
-# include "sanitizer_common.h"
-# include "sanitizer_stacktrace_printer.h"
-# include "sanitizer_symbolizer.h"
-# include "sanitizer_symbolizer_markup_constants.h"
-
-namespace __sanitizer {
-
// This generic support for offline symbolizing is based on the
// Fuchsia port. We don't do any actual symbolization per se.
// Instead, we emit text containing raw addresses and raw linkage
// symbol names, embedded in Fuchsia's symbolization markup format.
-// Fuchsia's logging infrastructure emits enough information about
-// process memory layout that a post-processing filter can do the
-// symbolization and pretty-print the markup. See the spec at:
-// https://fuchsia.googlesource.com/zircon/+/master/docs/symbolizer_markup.md
+// See the spec at:
+// https://llvm.org/docs/SymbolizerMarkupFormat.html
+//===--===//
-// This is used by UBSan for type names, and by ASan for global variable names.
-// It's expected to return a static buffer that will be reused on each call.
-const char *Symbolizer::Demangle(const char *name) {
- static char buffer[kFormatDemangleMax];
- internal_snprintf(buffer, sizeof(buffer), kFormatDemangle, name);
- return buffer;
-}
+#include "sanitizer_symbolizer_markup.h"
-// This is used mostly for suppression matching. Making it work
-// would enable "interceptor_via_lib" suppressions. It's also used
-// once in UBSan to say "in module ..." in a message that also
-// includes an address in the module, so post-processing can already
-// pretty-print that so as to indicate the module.
-bool Symbolizer::GetModuleNameAndOffsetForPC(uptr pc, const char **module_name,
- uptr *module_address) {
- return false;
-}
+#include "sanitizer_common.h"
+#include "sanitizer_stacktrace_printer.h"
+#include "sanitizer_symbolizer.h"
+#include "sanitizer_symbolizer_markup_constants.h"
-// This is mainly used by hwasan for online symbolization. This isn't needed
-// since hwasan can always just dump stack frames for offline symbolization.
-bool Symbolizer::SymbolizeFrame(uptr addr, FrameInfo *info) { return false; }
-
-// This is used in some places for suppression checking, which we
-// don't really support for Fuchsia. It's also used in UBSan to
-// identify a PC location to a function name, so we always fill in
-// the function member with a string containing markup around
[llvm-branch-commits] [mlir] b823f84 - [mlir] Add support for `memref.alloca` sub-byte emulation (#73138)
Author: Max191
Date: 2023-11-27T16:28:22-08:00
New Revision: b823f8469b5364411cde31a215c9bcbe0d3c08f7
URL:
https://github.com/llvm/llvm-project/commit/b823f8469b5364411cde31a215c9bcbe0d3c08f7
DIFF:
https://github.com/llvm/llvm-project/commit/b823f8469b5364411cde31a215c9bcbe0d3c08f7.diff
LOG: [mlir] Add support for `memref.alloca` sub-byte emulation (#73138)
Adds a similar case to `memref.alloc` for `memref.alloca` in
EmulateNarrowTypes.
Fixes https://github.com/openxla/iree/issues/15515
Added:
Modified:
mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
Removed:
diff --git a/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
b/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
index dec5936fa7e83ce..e5801c3733ed5a8 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
@@ -112,18 +112,22 @@ static Value getOffsetForBitwidth(Location loc,
OpFoldResult srcIdx,
namespace {
//===--===//
-// ConvertMemRefAlloc
+// ConvertMemRefAllocation
//===--===//
-struct ConvertMemRefAlloc final : OpConversionPattern {
- using OpConversionPattern::OpConversionPattern;
+template
+struct ConvertMemRefAllocation final : OpConversionPattern {
+ using OpConversionPattern::OpConversionPattern;
LogicalResult
- matchAndRewrite(memref::AllocOp op, OpAdaptor adaptor,
+ matchAndRewrite(OpTy op, typename OpTy::Adaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
-auto currentType = op.getMemref().getType().cast();
-auto newResultType =
-getTypeConverter()->convertType(op.getType()).dyn_cast();
+static_assert(std::is_same() ||
+ std::is_same(),
+ "expected only memref::AllocOp or memref::AllocaOp");
+auto currentType = cast(op.getMemref().getType());
+auto newResultType = dyn_cast(
+this->getTypeConverter()->convertType(op.getType()));
if (!newResultType) {
return rewriter.notifyMatchFailure(
op->getLoc(),
@@ -132,9 +136,9 @@ struct ConvertMemRefAlloc final :
OpConversionPattern {
// Special case zero-rank memrefs.
if (currentType.getRank() == 0) {
- rewriter.replaceOpWithNewOp(
- op, newResultType, ValueRange{}, adaptor.getSymbolOperands(),
- adaptor.getAlignmentAttr());
+ rewriter.replaceOpWithNewOp(op, newResultType, ValueRange{},
+adaptor.getSymbolOperands(),
+adaptor.getAlignmentAttr());
return success();
}
@@ -156,9 +160,9 @@ struct ConvertMemRefAlloc final :
OpConversionPattern {
rewriter, loc, linearizedMemRefInfo.linearizedSize));
}
-rewriter.replaceOpWithNewOp(
-op, newResultType, dynamicLinearizedSize, adaptor.getSymbolOperands(),
-adaptor.getAlignmentAttr());
+rewriter.replaceOpWithNewOp(op, newResultType, dynamicLinearizedSize,
+ adaptor.getSymbolOperands(),
+ adaptor.getAlignmentAttr());
return success();
}
};
@@ -344,10 +348,11 @@ void memref::populateMemRefNarrowTypeEmulationPatterns(
RewritePatternSet &patterns) {
// Populate `memref.*` conversion patterns.
- patterns
- .add(
- typeConverter, patterns.getContext());
+ patterns.add,
+ ConvertMemRefAllocation, ConvertMemRefLoad,
+ ConvertMemRefAssumeAlignment, ConvertMemRefSubview,
+ ConvertMemRefReinterpretCast>(typeConverter,
+ patterns.getContext());
memref::populateResolveExtractStridedMetadataPatterns(patterns);
}
diff --git a/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
b/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
index 2c411defb47e3ba..dc32a59a1a14931 100644
--- a/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
+++ b/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
@@ -232,3 +232,36 @@ func.func @reinterpret_cast_memref_load_1D(%arg0: index)
-> i4 {
// CHECK32: %[[SHR:.+]] = arith.shrsi %[[LOAD]], %[[CAST]] : i32
// CHECK32: %[[TRUNC:.+]] = arith.trunci %[[SHR]] : i32 to i4
// CHECK32: return %[[TRUNC]]
+
+// -
+
+func.func @memref_alloca_load_i4(%arg0: index) -> i4 {
+%0 = memref.alloca() : memref<5xi4>
+%1 = memref.load %0[%arg0] : memref<5xi4>
+return %1 : i4
+}
+// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 floordiv 2)>
+// CHECK-DAG: #[[MAP1:.+]] = affine_map<()[s0] -> (s0 * 4 - (s0 floordiv 2) *
8)
+// CHECK: func @memref_alloca_load_i4(
+// CHECK-SAME: %[[ARG0:.+]]
[llvm-branch-commits] [mlir] 9a7f4bd - [mlir][arith] doc updates for ub semantics, and int representations (#72932)
Author: Jacob Yu
Date: 2023-11-27T19:48:06-05:00
New Revision: 9a7f4bde2489f6529d336998e2c3fe902a1d864a
URL:
https://github.com/llvm/llvm-project/commit/9a7f4bde2489f6529d336998e2c3fe902a1d864a
DIFF:
https://github.com/llvm/llvm-project/commit/9a7f4bde2489f6529d336998e2c3fe902a1d864a.diff
LOG: [mlir][arith] doc updates for ub semantics, and int representations
(#72932)
Following the discussions in this thread,
https://discourse.llvm.org/t/some-question-on-the-semantics-of-the-arith-dialect/74861,
here are some updates to the documented semantics of Arith.
Added are clarifications on poison behaviour, UBs, overflow semantics,
and the underlying two's complement representation used for integers
Co-authored-by: kuhar
Co-authored-by: math-fehr
Added:
Modified:
mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
Removed:
diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
b/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
index 133af893e4efa74..1e4061392b22d48 100644
--- a/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
+++ b/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
@@ -19,7 +19,12 @@ def Arith_Dialect : Dialect {
The arith dialect is intended to hold basic integer and floating point
mathematical operations. This includes unary, binary, and ternary
arithmetic
ops, bitwise and shift ops, cast ops, and compare ops. Operations in this
-dialect also accept vectors and tensors of integers or floats.
+dialect also accept vectors and tensors of integers or floats. The dialect
+assumes integers are represented by bitvectors with a two's complement
+representation. Unless otherwise stated, the operations within this
dialect
+propagate poison values, i.e., if any of its inputs are poison, then the
+output is poison. Unless otherwise stated, operations applied to `vector`
+and `tensor` values propagates poison elementwise.
}];
let hasConstantMaterializer = 1;
diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
index e382f18340856ff..38cce99679e99dc 100644
--- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
@@ -196,9 +196,9 @@ def Arith_AddIOp : Arith_TotalIntBinaryOp<"addi",
[Commutative]> {
let summary = "integer addition operation";
let description = [{
The `addi` operation takes two operands and returns one result, each of
-these is required to be the same type. This type may be an integer scalar
-type, a vector whose element type is integer, or a tensor of integers. It
-has no standard attributes.
+these is required to be the same type. This type may be an integer scalar
type,
+a vector whose element type is integer, or a tensor of integers. It has no
+standard attributes.
Example:
@@ -273,7 +273,9 @@ def Arith_AddUIExtendedOp : Arith_Op<"addui_extended",
[Pure, Commutative,
//===--===//
def Arith_SubIOp : Arith_TotalIntBinaryOp<"subi"> {
- let summary = "integer subtraction operation";
+ let summary = [{
+Integer subtraction operation.
+ }];
let hasFolder = 1;
let hasCanonicalizer = 1;
}
@@ -283,7 +285,9 @@ def Arith_SubIOp : Arith_TotalIntBinaryOp<"subi"> {
//===--===//
def Arith_MulIOp : Arith_TotalIntBinaryOp<"muli", [Commutative]> {
- let summary = "integer multiplication operation";
+ let summary = [{
+Integer multiplication operation.
+ }];
let hasFolder = 1;
let hasCanonicalizer = 1;
}
@@ -385,8 +389,9 @@ def Arith_DivUIOp : Arith_IntBinaryOp<"divui",
[ConditionallySpeculatable]> {
the most significant, i.e. for `i16` given two's complement representation,
`6 / -2 = 6 / (2^16 - 2) = 0`.
-Note: the semantics of division by zero is TBD; do NOT assume any specific
-behavior.
+Division by zero is undefined behavior. When applied to `vector` and
+`tensor` values, the behavior is undefined if _any_ elements are divided
by
+zero.
Example:
@@ -420,8 +425,10 @@ def Arith_DivSIOp : Arith_IntBinaryOp<"divsi",
[ConditionallySpeculatable]> {
Signed integer division. Rounds towards zero. Treats the leading bit as
sign, i.e. `6 / -2 = -3`.
-Note: the semantics of division by zero or signed division overflow
(minimum
-value divided by -1) is TBD; do NOT assume any specific behavior.
+Divison by zero, or signed division overflow (minimum value divided by -1)
+is undefined behavior. When applied to `vector` and `tensor` values, the
+behavior is undefined if _any_ of its elements are divided by zero or has
a
+signed division overflow.
Example:
@@ -455,10 +462,11 @@ def Arith
[llvm-branch-commits] [llvm] 93e1568 - [DAG] Fix a miscompile in insert_subvector undef (insert_subvector undef, ..), idx combine (#73587)
Author: Philip Reames
Date: 2023-11-27T16:45:29-08:00
New Revision: 93e156833bfadfbabfa5be2afad4f002c019257f
URL:
https://github.com/llvm/llvm-project/commit/93e156833bfadfbabfa5be2afad4f002c019257f
DIFF:
https://github.com/llvm/llvm-project/commit/93e156833bfadfbabfa5be2afad4f002c019257f.diff
LOG: [DAG] Fix a miscompile in insert_subvector undef (insert_subvector undef,
..), idx combine (#73587)
The combine was implicitly assuming that the index on the outer
insert_subvector meant the same thing when the source was switched to be
the index of the inner insert_subvector. This is not true if the
innermost sub-vector is fixed, and the outer subvector is scalable.
I could do a less restrictive fix here - i.e. allow the case where the
scalability of the subvectors are the same - but there's no test
coverage which shows this transform actually has profit. Given that, go
for the simplest fix.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 41d36e7d16d2e14..2a3425a42607e72 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -26153,10 +26153,11 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N)
{
N1, N2);
// Eliminate an intermediate insert into an undef vector:
- // insert_subvector undef, (insert_subvector undef, X, 0), N2 -->
- // insert_subvector undef, X, N2
+ // insert_subvector undef, (insert_subvector undef, X, 0), 0 -->
+ // insert_subvector undef, X, 0
if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
- N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)))
+ N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)) &&
+ isNullConstant(N2))
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
N1.getOperand(1), N2);
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index 57de8341cb89cef..8a368e7161c3f2a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -505,6 +505,33 @@ define @insert_nxv2i64_nxv3i64(<3 x
i64> %sv) #0 {
ret %vec
}
+; This shows a case where we were miscompiling because the index of the
+; outer expects a scalable inner and the inner most subvector is fixed length.
+; The code generated happens to be correct if VLEN=128, but is wrong if
+; VLEN=256.
+define @insert_insert_combine(<2 x i32> %subvec) {
+; CHECK-LABEL: insert_insert_combine:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vmv1r.v v10, v8
+; CHECK-NEXT:ret
+ %inner = call @llvm.vector.insert.nxv4i32.v2i32( undef, <2 x i32> %subvec, i64 0)
+ %outer = call @llvm.vector.insert.nxv4i32.nxv8i32( undef, %inner, i64 4)
+ ret %outer
+}
+
+; We can combine these two (even with non-zero index on the outer) because
+; the vector must be an even multiple.
+define @insert_insert_combine2( %subvec) {
+; CHECK-LABEL: insert_insert_combine2:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vmv1r.v v10, v8
+; CHECK-NEXT:ret
+ %inner = call @llvm.vector.insert.nxv2i32.nxv4i32( undef, %subvec, i64 0)
+ %outer = call @llvm.vector.insert.nxv4i32.nxv8i32( undef, %inner, i64 4)
+ ret %outer
+}
+
+
attributes #0 = { vscale_range(2,1024) }
declare @llvm.vector.insert.nxv1i1.nxv4i1(,
, i64)
@@ -517,6 +544,9 @@ declare
@llvm.vector.insert.nxv2f16.nxv32f16( @llvm.vector.insert.nxv1i8.nxv4i8(,
, i64 %idx)
+declare @llvm.vector.insert.nxv2i32.nxv4i32(, , i64)
+declare @llvm.vector.insert.nxv4i32.v2i32(, <2 x i32>, i64)
+
declare @llvm.vector.insert.nxv2i32.nxv8i32(, , i64 %idx)
declare @llvm.vector.insert.nxv4i32.nxv8i32(, , i64 %idx)
___
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[llvm-branch-commits] [llvm] 52b413f - [RISCV] Precommit tests for buildvector lowering with exact VLEN
Author: Philip Reames
Date: 2023-11-27T16:48:20-08:00
New Revision: 52b413f25ae79b07df88c0224adec4a6d7dabecc
URL:
https://github.com/llvm/llvm-project/commit/52b413f25ae79b07df88c0224adec4a6d7dabecc
DIFF:
https://github.com/llvm/llvm-project/commit/52b413f25ae79b07df88c0224adec4a6d7dabecc.diff
LOG: [RISCV] Precommit tests for buildvector lowering with exact VLEN
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 05aa5f9807b9fc4..31ed3083e05a114 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -1077,13 +1077,252 @@ define <32 x double> @buildvec_v32f64(double %e0,
double %e1, double %e2, double
ret <32 x double> %v31
}
+define <32 x double> @buildvec_v32f64_exact_vlen(double %e0, double %e1,
double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double
%e8, double %e9, double %e10, double %e11, double %e12, double %e13, double
%e14, double %e15, double %e16, double %e17, double %e18, double %e19, double
%e20, double %e21, double %e22, double %e23, double %e24, double %e25, double
%e26, double %e27, double %e28, double %e29, double %e30, double %e31)
vscale_range(2,2) {
+; RV32-LABEL: buildvec_v32f64_exact_vlen:
+; RV32: # %bb.0:
+; RV32-NEXT:addi sp, sp, -512
+; RV32-NEXT:.cfi_def_cfa_offset 512
+; RV32-NEXT:sw ra, 508(sp) # 4-byte Folded Spill
+; RV32-NEXT:sw s0, 504(sp) # 4-byte Folded Spill
+; RV32-NEXT:fsd fs0, 496(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs1, 488(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs2, 480(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs3, 472(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs4, 464(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs5, 456(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs6, 448(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs7, 440(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs8, 432(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs9, 424(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs10, 416(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs11, 408(sp) # 8-byte Folded Spill
+; RV32-NEXT:.cfi_offset ra, -4
+; RV32-NEXT:.cfi_offset s0, -8
+; RV32-NEXT:.cfi_offset fs0, -16
+; RV32-NEXT:.cfi_offset fs1, -24
+; RV32-NEXT:.cfi_offset fs2, -32
+; RV32-NEXT:.cfi_offset fs3, -40
+; RV32-NEXT:.cfi_offset fs4, -48
+; RV32-NEXT:.cfi_offset fs5, -56
+; RV32-NEXT:.cfi_offset fs6, -64
+; RV32-NEXT:.cfi_offset fs7, -72
+; RV32-NEXT:.cfi_offset fs8, -80
+; RV32-NEXT:.cfi_offset fs9, -88
+; RV32-NEXT:.cfi_offset fs10, -96
+; RV32-NEXT:.cfi_offset fs11, -104
+; RV32-NEXT:addi s0, sp, 512
+; RV32-NEXT:.cfi_def_cfa s0, 0
+; RV32-NEXT:andi sp, sp, -128
+; RV32-NEXT:sw a0, 120(sp)
+; RV32-NEXT:sw a1, 124(sp)
+; RV32-NEXT:fld ft0, 120(sp)
+; RV32-NEXT:sw a2, 120(sp)
+; RV32-NEXT:sw a3, 124(sp)
+; RV32-NEXT:fld ft1, 120(sp)
+; RV32-NEXT:sw a4, 120(sp)
+; RV32-NEXT:sw a5, 124(sp)
+; RV32-NEXT:fld ft2, 120(sp)
+; RV32-NEXT:sw a6, 120(sp)
+; RV32-NEXT:sw a7, 124(sp)
+; RV32-NEXT:fld ft3, 120(sp)
+; RV32-NEXT:fld ft4, 0(s0)
+; RV32-NEXT:fld ft5, 8(s0)
+; RV32-NEXT:fld ft6, 16(s0)
+; RV32-NEXT:fld ft7, 24(s0)
+; RV32-NEXT:fld ft8, 32(s0)
+; RV32-NEXT:fld ft9, 40(s0)
+; RV32-NEXT:fld ft10, 48(s0)
+; RV32-NEXT:fld ft11, 56(s0)
+; RV32-NEXT:fld fs0, 64(s0)
+; RV32-NEXT:fld fs1, 72(s0)
+; RV32-NEXT:fld fs2, 80(s0)
+; RV32-NEXT:fld fs3, 88(s0)
+; RV32-NEXT:fld fs4, 96(s0)
+; RV32-NEXT:fld fs5, 104(s0)
+; RV32-NEXT:fld fs6, 112(s0)
+; RV32-NEXT:fld fs7, 120(s0)
+; RV32-NEXT:fld fs8, 152(s0)
+; RV32-NEXT:fld fs9, 144(s0)
+; RV32-NEXT:fld fs10, 136(s0)
+; RV32-NEXT:fld fs11, 128(s0)
+; RV32-NEXT:fsd fs8, 248(sp)
+; RV32-NEXT:fsd fs9, 240(sp)
+; RV32-NEXT:fsd fs10, 232(sp)
+; RV32-NEXT:fsd fs11, 224(sp)
+; RV32-NEXT:fsd fs7, 216(sp)
+; RV32-NEXT:fsd fs6, 208(sp)
+; RV32-NEXT:fsd fs5, 200(sp)
+; RV32-NEXT:fsd fs4, 192(sp)
+; RV32-NEXT:fsd fs3, 184(sp)
+; RV32-NEXT:fsd fs2, 176(sp)
+; RV32-NEXT:fsd fs1, 168(sp)
+; RV32-NEXT:fsd fs0, 160(sp)
+; RV32-NEXT:fsd ft11, 152(sp)
+; RV32-NEXT:fsd ft10, 144(sp)
+; RV32-NEXT:fsd ft9, 136(sp)
+; RV32-NEXT:fsd ft8, 128(sp)
+; RV32-NEXT:fsd ft7, 376(sp)
+; RV32-NEXT:fsd ft6, 368(sp)
+; RV32-NEXT:fsd ft5, 360(sp)
+; RV32-NEXT:fsd ft4, 352(sp)
+; RV32-NEXT:fsd fa7, 312(sp)
+; RV32-NEXT:fsd fa6, 304(sp)
+; RV32-NEXT:fsd fa5, 296(sp)
+; RV32-NEXT:fsd fa4, 288(sp)
+; RV32-NEXT:
