[llvm-branch-commits] [llvm] Fill 17.x/ReleaseNotes with my works (PR #73461)
chapuni wrote: @tru I have created llvm/llvm-project-release-prs#789, thanks! https://github.com/llvm/llvm-project/pull/73461 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] e919a83 - eliminate python SyntaxWarnings from check-all output.
Author: Georgios Eleftheriou
Date: 2023-11-27T15:52:07+01:00
New Revision: e919a83f96fe016378926855cb79f9b86102f6e4
URL:
https://github.com/llvm/llvm-project/commit/e919a83f96fe016378926855cb79f9b86102f6e4
DIFF:
https://github.com/llvm/llvm-project/commit/e919a83f96fe016378926855cb79f9b86102f6e4.diff
LOG: eliminate python SyntaxWarnings from check-all output.
```
src_dir/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py:28: SyntaxWarning:
invalid escape sequence '\*'self.implementationContent += """
src_dir/llvm/utils/lit/lit/TestRunner.py:205: SyntaxWarning: invalid escape
sequence '\c' """
src_dir/llvm/utils/lit/lit/TestRunner.py:1561: SyntaxWarning: invalid escape
sequence '\s' match =
_caching_re_compile("^\s*%else\s*(%{)?").search(ln)
src_dir/libcxx/utils/libcxx/test/format.py:64: SyntaxWarning: invalid escape
sequence '\s' for output in re.split('[$]\s*":"\s*"RUN: at
line \d+"', fullOutput):
src_dir/libcxx/utils/libcxx/test/params.py:121: SyntaxWarning: invalid escape
sequence '\+'AddSubstitution("%{cxx_std}", re.sub("\+",
"x", std)),
src_dir/libcxx/utils/libcxx/test/params.py:214: SyntaxWarning: invalid escape
sequence '\+'AddFeature("stdlib=libc++") if
re.match(".+-libc\+\+", stdlib) else None,
src_dir/compiler-rt/test/lit.common.cfg.py:800: SyntaxWarning: invalid escape
sequence '\$'"-Wl,-z,origin -Wl,-rpath,\$ORIGIN -L%T
-l%xdynamiclib_namespec"
src_dir/compiler-rt/test/lit.common.cfg.py:809: SyntaxWarning: invalid escape
sequence '\$'"-Wl,-rpath,\$ORIGIN -L%T
-l%xdynamiclib_namespec" + postfix,
src_dir/compiler-rt/test/lit.common.cfg.py:817: SyntaxWarning: invalid escape
sequence '\$'"-Wl,-R\$ORIGIN -L%T -l%xdynamiclib_namespec"
+ postfix,
src_dir/llvm/test/lit.cfg.py:275: SyntaxWarning: invalid escape sequence '\d'
match = re.search("release (\d+)\.(\d+)",
ptxas_out)
```
Added:
Modified:
clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py
compiler-rt/test/lit.common.cfg.py
libcxx/utils/libcxx/test/format.py
libcxx/utils/libcxx/test/params.py
llvm/test/lit.cfg.py
llvm/utils/lit/lit/TestRunner.py
Removed:
diff --git a/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py
b/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py
index dafb332961ede86..7671f9691c09610 100755
--- a/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py
+++ b/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py
@@ -25,7 +25,7 @@ def __init__(self, templateClasses):
def GeneratePrologue(self):
-self.implementationContent += """
+self.implementationContent += r"""
/*===- Generated file ---*- C++
-*-===*\
|*
*|
|* Introspection of available AST node SourceLocations
*|
diff --git a/compiler-rt/test/lit.common.cfg.py
b/compiler-rt/test/lit.common.cfg.py
index 3b42da17b0affbe..e95f430f1961a66 100644
--- a/compiler-rt/test/lit.common.cfg.py
+++ b/compiler-rt/test/lit.common.cfg.py
@@ -797,7 +797,7 @@ def is_windows_lto_supported():
config.substitutions.append(
(
"%ld_flags_rpath_exe" + postfix,
-"-Wl,-z,origin -Wl,-rpath,\$ORIGIN -L%T
-l%xdynamiclib_namespec"
+r"-Wl,-z,origin -Wl,-rpath,\$ORIGIN -L%T
-l%xdynamiclib_namespec"
+ postfix,
)
)
@@ -806,7 +806,7 @@ def is_windows_lto_supported():
config.substitutions.append(
(
"%ld_flags_rpath_exe" + postfix,
-"-Wl,-rpath,\$ORIGIN -L%T -l%xdynamiclib_namespec" + postfix,
+r"-Wl,-rpath,\$ORIGIN -L%T -l%xdynamiclib_namespec" + postfix,
)
)
config.substitutions.append(("%ld_flags_rpath_so" + postfix, ""))
@@ -814,7 +814,7 @@ def is_windows_lto_supported():
config.substitutions.append(
(
"%ld_flags_rpath_exe" + postfix,
-"-Wl,-R\$ORIGIN -L%T -l%xdynamiclib_namespec" + postfix,
+r"-Wl,-R\$ORIGIN -L%T -l%xdynamiclib_namespec" + postfix,
)
)
config.substitutions.append(("%ld_flags_rpath_so" + postfix, ""))
diff --git a/libcxx/utils/libcxx/test/format.py
b/libcxx/utils/libcxx/test/format.py
index ddd88f25646eaa8..da8605e06699f69 100644
--- a/libcxx/utils/libcxx/test/format.py
+++ b/libcxx/utils/libcxx/test/format.py
@@ -61,7 +61,7 @@ def _parseLitOutput(fullOutput):
injecting additional Lit output around it.
"""
parsed = ''
-for output in re.split('[$]\s*":"\s*"RUN: at line \d+"', fullOutput):
+for output in re.split(r'[$]\s*":"\s*"RUN: at line \d+"',
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 6f25ae3eec2780bc50d0714b235a400eece1658a
2336350b4e912697a90d0bf269fc95ca8dd4c897 -- llvm/lib/CodeGen/LivePhysRegs.cpp
``
View the diff from clang-format here.
``diff
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp
b/llvm/lib/CodeGen/LivePhysRegs.cpp
index 634f46d9d9..20b517b1e1 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -222,7 +222,7 @@ void LivePhysRegs::addLiveOutsNoPristines(const
MachineBasicBlock &MBB) {
const MachineFrameInfo &MFI = MF.getFrameInfo();
if (MFI.isCalleeSavedInfoValid()) {
for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
- addReg(Info.getReg());
+addReg(Info.getReg());
}
}
}
``
https://github.com/llvm/llvm-project/pull/73553
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[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
MatzeB wrote: Is this about computing *live-outs* of the return block as the code suggests? (The summary currently talks about live-ins?) https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
MatzeB wrote: I don't remember the situation on aarch64, but if by chance LR is modeled with this "pristine register" concept, then maybe the caller needs to use `addLiveIns()` rather than `addLiveInsNoPristines()`? https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
https://github.com/fhahn edited https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
https://github.com/fhahn edited https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
fhahn wrote: > Is this about computing **live-outs** of the return block as the code > suggests? (The summary currently talks about live-ins?) Thanks, it should be **live-outs** in the description, updated! > I don't remember the situation on aarch64, but if by chance LR is modeled > with this "pristine register" concept, then maybe the caller needs to use > addLiveIns() rather than addLiveInsNoPristines()? I am not sure, but looking at `updateLiveness` (https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/PrologEpilogInserter.cpp#L582) it looks like it uses the saved registers from MFI. Pristine registers I think contain all callee-saved registers for the target, which may be overestimating the liveness quite a bit. https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] e59b116 - fixup! fix formatting.
Author: Florian Hahn
Date: 2023-11-27T19:15:33Z
New Revision: e59b116dbc7bf501016c7c68f348c39df8f598a8
URL:
https://github.com/llvm/llvm-project/commit/e59b116dbc7bf501016c7c68f348c39df8f598a8
DIFF:
https://github.com/llvm/llvm-project/commit/e59b116dbc7bf501016c7c68f348c39df8f598a8.diff
LOG: fixup! fix formatting.
Added:
Modified:
llvm/lib/CodeGen/LivePhysRegs.cpp
Removed:
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp
b/llvm/lib/CodeGen/LivePhysRegs.cpp
index 634f46d9d98edc6..20b517b1e1a5c11 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -222,7 +222,7 @@ void LivePhysRegs::addLiveOutsNoPristines(const
MachineBasicBlock &MBB) {
const MachineFrameInfo &MFI = MF.getFrameInfo();
if (MFI.isCalleeSavedInfoValid()) {
for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
- addReg(Info.getReg());
+addReg(Info.getReg());
}
}
}
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[llvm-branch-commits] [compiler-rt] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
https://github.com/vitalybuka approved this pull request. https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [sanitizer_symbolizer] RenderContextual elements for symbolizer markup. (PR #73194)
@@ -64,4 +66,111 @@ const char *MarkupSymbolizerTool::Demangle(const char
*name) {
return buffer;
}
+// Fuchsia's implementation of symbolizer markup doesn't need to emit
contextual
+// elements at this point.
+// Fuchsia's logging infrastructure emits enough information about
+// process memory layout that a post-processing filter can do the
+// symbolization and pretty-print the markup.
+#if !SANITIZER_FUCHSIA
+
+// Simplier view of a LoadedModule. It only holds information necessary to
+// identify unique modules.
+struct RenderedModule {
+ char *full_name;
+ uptr base_address;
+ u8 uuid[kModuleUUIDSize]; // BuildId
+};
+
+static bool ModulesEq(const LoadedModule &module,
+ const RenderedModule &renderedModule) {
+ return module.base_address() == renderedModule.base_address &&
+ internal_memcmp(module.uuid(), renderedModule.uuid,
+ module.uuid_size()) == 0 &&
+ internal_strcmp(module.full_name(), renderedModule.full_name) == 0;
+}
+
+static bool ModuleHasBeenRendered(
+const LoadedModule &module,
+const InternalMmapVectorNoCtor &renderedModules) {
+ for (const auto &renderedModule : renderedModules)
+if (ModulesEq(module, renderedModule))
+ return true;
+
+ return false;
+}
+
+static void RenderModule(InternalScopedString *buffer,
+ const LoadedModule &module, uptr moduleId) {
+ InternalScopedString buildIdBuffer;
+ for (uptr i = 0; i < module.uuid_size(); i++)
+buildIdBuffer.AppendF("%02x", module.uuid()[i]);
+
+ buffer->AppendF(kFormatModule, moduleId, module.full_name(),
+ buildIdBuffer.data());
+ buffer->Append("\n");
+}
+
+static void RenderMmaps(InternalScopedString *buffer,
+const LoadedModule &module, uptr moduleId) {
+ InternalScopedString accessBuffer;
+
+ // All module mmaps are readable at least
+ for (const auto &range : module.ranges()) {
+accessBuffer.Append("r");
+if (range.writable)
+ accessBuffer.Append("w");
+if (range.executable)
+ accessBuffer.Append("x");
+
+
//{{{mmap:%starting_addr:%size_in_hex:load:%moduleId:r%(w|x):%relative_addr}}}
+
+// module.base_address == dlpi_addr
+// range.beg == dlpi_addr + p_vaddr
+// relative address == p_vaddr == range.beg - module.base_address
+buffer->AppendF(kFormatMmap, range.beg, range.end - range.beg, moduleId,
+accessBuffer.data(), range.beg - module.base_address());
+
+buffer->Append("\n");
+accessBuffer.clear();
+ }
+}
+
+void MarkupStackTracePrinter::RenderContext(InternalScopedString *buffer) {
+ // Keeps track of the modules that have been rendered.
+ static bool initialized = false;
+ static InternalMmapVectorNoCtor renderedModules;
vitalybuka wrote:
please move this statics into member of the MarkupStackTracePrinter
also why it can be static at all? modules can change?
https://github.com/llvm/llvm-project/pull/73194
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[llvm-branch-commits] [compiler-rt] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
https://github.com/vitalybuka approved this pull request. LGTM. but looks like it can be squashed with sanitizer_common test https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
MatzeB wrote: I still feel like I am missing something here, and it's been a while since I looked at this. But my impression is that LLVM modeling is "cheating" a bit in that technically all the callee-saves should be implicit-uses of the return instruction (and not live afterwards) but we don't model it that way and instead make them appear as live-outs of the return block? So doesn't seem like overestimating the liveness because of our current modeling? If I'm reading your patch correctly it would mean we would start adding all pristine registers for the return block. I am just confused so far because this is happening in a function called `addLiveOutsNoPristines`... https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
MatzeB wrote: Which code/pass is using `LivePhysRegs` that is causing you trouble here? https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
MatzeB wrote: Looking at the `MachineOutliner` it seems to already be using `addLiveOuts()` so I must be missing something on why this change has any effect anyway... https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines. (PR #73553)
fhahn wrote: > I still feel like I am missing something here, and it's been a while since I > looked at this. But my impression is that LLVM modeling is "cheating" a bit > in that technically all the callee-saves should be implicit-uses of the > return instruction (and not live afterwards) but we don't model it that way > and instead make them appear as live-outs of the return block? So doesn't > seem like overestimating the liveness because of our current modeling? Yep, the current modeling in general may overestimates the liveness. With overestimating I meant that with this patch we overestimate in more places, but that's by design. > > If I'm reading your patch correctly it would mean we would start adding all > pristine registers for the return block[1]. I am just confused so far because > this is happening in a function called `addLiveOutsNoPristines`... > I am not sure what exactly the definition for pristines is (and not super familiar with this code in general), and maybe the function name needs to be changed. The main thing to note is that it won't add all pristines; `addPristines` adds all callee saved registers (via TRI) and removes the ones which are in he machine function's CalleeSavedInfo. The patch adds pristines, but *only* those that have been added to CalleeSavedInfo. > [1] Pristine == "callee saved but happens to be unused and hence not > saved/restored" which is what happens when you remove that > `Info.isRestored()` check? > Which code/pass is using LivePhysRegs that is causing you trouble here? The issue is in `BranchFolding`, where after splitting, the liveness of `LR` isn't preserved in the new or merged blocks. It could be fixed locally there by iterating over the registers in CalleeSavedInfo and checking if they were live-in in the original block (see below), but I am worried that fixing this locally leaves us open for similar issues in other parts of the codebase. https://github.com/llvm/llvm-project/pull/73553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
@@ -275,3 +275,7 @@ COMMON_FLAG(bool, test_only_emulate_no_memorymap, false, // program. COMMON_FLAG(bool, test_only_replace_dlopen_main_program, false, "TEST ONLY replace dlopen(,...) with dlopen(NULL)") + +COMMON_FLAG(bool, enable_symbolizer_markup, SANITIZER_FUCHSIA, +"Use sanitizer symbolizer markup, available on Linux " +"and always set true for fuchsia.") petrhosek wrote: Super minor nit, but `Fuchsia` should be capitalized. https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
avillega wrote: > LGTM. but looks like it can be squashed with sanitizer_common test The tests also test Emitting contextual elements, so I will squash the tests with the RenderContextual elements PR. https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 22078bd - Revert "[CUDA][HIP] ignore implicit host/device attr for override (#72815)"
Author: Yaxun (Sam) Liu
Date: 2023-11-22T21:04:55-05:00
New Revision: 22078bd9f6842411aac2b75196975d68a817a358
URL:
https://github.com/llvm/llvm-project/commit/22078bd9f6842411aac2b75196975d68a817a358
DIFF:
https://github.com/llvm/llvm-project/commit/22078bd9f6842411aac2b75196975d68a817a358.diff
LOG: Revert "[CUDA][HIP] ignore implicit host/device attr for override (#72815)"
This reverts commit a1e2c6566305061c115954b048f2957c8d55cb5b.
Revert this patch due to regression. A testcase is:
`template
class C {
explicit C() {};
};
template <> C::C() {};
`
Added:
Modified:
clang/lib/Sema/SemaOverload.cpp
clang/test/SemaCUDA/implicit-member-target-inherited.cu
clang/test/SemaCUDA/trivial-ctor-dtor.cu
Removed:
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 64607e28b8b35e6..9800d7f1c9cfee9 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -1491,10 +1491,8 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef,
FunctionDecl *New,
// Don't allow overloading of destructors. (In theory we could, but it
// would be a giant change to clang.)
if (!isa(New)) {
- Sema::CUDAFunctionTarget NewTarget = SemaRef.IdentifyCUDATarget(
- New, isa(New)),
- OldTarget = SemaRef.IdentifyCUDATarget(
- Old, isa(New));
+ Sema::CUDAFunctionTarget NewTarget = SemaRef.IdentifyCUDATarget(New),
+ OldTarget = SemaRef.IdentifyCUDATarget(Old);
if (NewTarget != Sema::CFT_InvalidTarget) {
assert((OldTarget != Sema::CFT_InvalidTarget) &&
"Unexpected invalid target.");
diff --git a/clang/test/SemaCUDA/implicit-member-target-inherited.cu
b/clang/test/SemaCUDA/implicit-member-target-inherited.cu
index ceca0891fc9b03c..781199bba6b5a11 100644
--- a/clang/test/SemaCUDA/implicit-member-target-inherited.cu
+++ b/clang/test/SemaCUDA/implicit-member-target-inherited.cu
@@ -39,7 +39,6 @@ struct A2_with_device_ctor {
};
// expected-note@-3 {{candidate constructor (the implicit copy constructor)
not viable}}
// expected-note@-4 {{candidate constructor (the implicit move constructor)
not viable}}
-// expected-note@-4 {{candidate inherited constructor not viable: call to
__device__ function from __host__ function}}
struct B2_with_implicit_default_ctor : A2_with_device_ctor {
using A2_with_device_ctor::A2_with_device_ctor;
diff --git a/clang/test/SemaCUDA/trivial-ctor-dtor.cu
b/clang/test/SemaCUDA/trivial-ctor-dtor.cu
index 21d698d28492ac3..1df8adc62bab590 100644
--- a/clang/test/SemaCUDA/trivial-ctor-dtor.cu
+++ b/clang/test/SemaCUDA/trivial-ctor-dtor.cu
@@ -38,19 +38,3 @@ struct TC : TB {
};
__device__ TC tc; //expected-error {{dynamic initialization is not
supported for __device__, __constant__, __shared__, and __managed__ variables}}
-
-// Check trivial ctor specialization
-template
-struct C { //expected-note {{candidate constructor (the implicit copy
constructor) not viable}}
- //expected-note@-1 {{candidate constructor (the implicit move
constructor) not viable}}
-explicit C() {};
-};
-
-template <> C::C() {};
-__device__ C ci_d;
-C ci_h;
-
-// Check non-trivial ctor specialization
-template <> C::C() { static int nontrivial_ctor = 1; } //expected-note
{{candidate constructor not viable: call to __host__ function from __device__
function}}
-__device__ C cf_d; //expected-error {{no matching constructor for
initialization of 'C'}}
-C cf_h;
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[llvm-branch-commits] [clang] 6b3470b - Revert "[CUDA][HIP] make trivial ctor/dtor host device (#72394)"
Author: Yaxun (Sam) Liu
Date: 2023-11-22T21:20:53-05:00
New Revision: 6b3470b4b83195aeeda60b101e8d3bf8800c321c
URL:
https://github.com/llvm/llvm-project/commit/6b3470b4b83195aeeda60b101e8d3bf8800c321c
DIFF:
https://github.com/llvm/llvm-project/commit/6b3470b4b83195aeeda60b101e8d3bf8800c321c.diff
LOG: Revert "[CUDA][HIP] make trivial ctor/dtor host device (#72394)"
This reverts commit 27e6e4a4d0e3296cebad8db577ec0469a286795e.
This patch is reverted due to regression. A testcase is:
`template
struct ptr {
~ptr() { static int x = 1;}
};
template
struct Abc : ptr {
public:
Abc();
~Abc() {}
};
template
class Abc;
`
Added:
Modified:
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaCUDA.cpp
clang/lib/Sema/SemaDecl.cpp
clang/test/SemaCUDA/call-host-fn-from-device.cu
clang/test/SemaCUDA/default-ctor.cu
clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
clang/test/SemaCUDA/implicit-member-target-collision.cu
clang/test/SemaCUDA/implicit-member-target-inherited.cu
clang/test/SemaCUDA/implicit-member-target.cu
Removed:
clang/test/SemaCUDA/trivial-ctor-dtor.cu
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 59806bcbcbb2dbc..e8914f5fcddf19e 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13466,10 +13466,6 @@ class Sema final {
void maybeAddCUDAHostDeviceAttrs(FunctionDecl *FD,
const LookupResult &Previous);
- /// May add implicit CUDAHostAttr and CUDADeviceAttr attributes to a
- /// trivial cotr/dtor that does not have host and device attributes.
- void maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FunctionDecl *FD);
-
/// May add implicit CUDAConstantAttr attribute to VD, depending on VD
/// and current compilation settings.
void MaybeAddCUDAConstantAttr(VarDecl *VD);
diff --git a/clang/lib/Sema/SemaCUDA.cpp b/clang/lib/Sema/SemaCUDA.cpp
index b94f448dabe7517..318174f7be8fa95 100644
--- a/clang/lib/Sema/SemaCUDA.cpp
+++ b/clang/lib/Sema/SemaCUDA.cpp
@@ -772,22 +772,6 @@ void Sema::maybeAddCUDAHostDeviceAttrs(FunctionDecl *NewD,
NewD->addAttr(CUDADeviceAttr::CreateImplicit(Context));
}
-// If a trivial ctor/dtor has no host/device
-// attributes, make it implicitly host device function.
-void Sema::maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FunctionDecl *FD) {
- bool IsTrivialCtor = false;
- if (auto *CD = dyn_cast(FD))
-IsTrivialCtor = isEmptyCudaConstructor(SourceLocation(), CD);
- bool IsTrivialDtor = false;
- if (auto *DD = dyn_cast(FD))
-IsTrivialDtor = isEmptyCudaDestructor(SourceLocation(), DD);
- if ((IsTrivialCtor || IsTrivialDtor) && !FD->hasAttr() &&
- !FD->hasAttr()) {
-FD->addAttr(CUDAHostAttr::CreateImplicit(Context));
-FD->addAttr(CUDADeviceAttr::CreateImplicit(Context));
- }
-}
-
// TODO: `__constant__` memory may be a limited resource for certain targets.
// A safeguard may be needed at the end of compilation pipeline if
// `__constant__` memory usage goes beyond limit.
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 4e1857b931cc868..23dd8ae15c16583 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -16255,9 +16255,6 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt
*Body,
if (FD && !FD->isDeleted())
checkTypeSupport(FD->getType(), FD->getLocation(), FD);
- if (LangOpts.CUDA)
-maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FD);
-
return dcl;
}
diff --git a/clang/test/SemaCUDA/call-host-fn-from-device.cu
b/clang/test/SemaCUDA/call-host-fn-from-device.cu
index b62de92db02d6de..acdd291b664579b 100644
--- a/clang/test/SemaCUDA/call-host-fn-from-device.cu
+++ b/clang/test/SemaCUDA/call-host-fn-from-device.cu
@@ -12,7 +12,7 @@ extern "C" void host_fn() {}
struct Dummy {};
struct S {
- S() { static int nontrivial_ctor = 1; }
+ S() {}
// expected-note@-1 2 {{'S' declared here}}
~S() { host_fn(); }
// expected-note@-1 {{'~S' declared here}}
diff --git a/clang/test/SemaCUDA/default-ctor.cu
b/clang/test/SemaCUDA/default-ctor.cu
index 31971fe6b3863c7..cbad7a1774c1501 100644
--- a/clang/test/SemaCUDA/default-ctor.cu
+++ b/clang/test/SemaCUDA/default-ctor.cu
@@ -25,7 +25,7 @@ __device__ void fd() {
InD ind;
InH inh; // expected-error{{no matching constructor for initialization of
'InH'}}
InHD inhd;
- Out out;
+ Out out; // expected-error{{no matching constructor for initialization of
'Out'}}
OutD outd;
OutH outh; // expected-error{{no matching constructor for initialization of
'OutH'}}
OutHD outhd;
diff --git a/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
b/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
index edb543f637ccc18..06015ed0d6d8edc 100644
--- a/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
+++ b/clang/
[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.
Author: Craig Topper
Date: 2023-11-22T18:59:41-08:00
New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c
URL:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c
DIFF:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff
LOG: [X86] Reject fpsr in inline asm constraints other than clobber.
Fixes #73197 and #69201.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a2ab093bb86f9..99866c811eb6faf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57236,7 +57236,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
return std::make_pair(X86::DF, &X86::DFCCRRegClass);
// fpsr -> FPSW
-if (StringRef("{fpsr}").equals_insensitive(Constraint))
+// Only allow for clobber.
+if (StringRef("{fpsr}").equals_insensitive(Constraint) && VT == MVT::Other)
return std::make_pair(X86::FPSW, &X86::FPCCRRegClass);
return Res;
___
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[llvm-branch-commits] [compiler-rt] 0e5da2e - [compiler-rt] Fix the HWCAP2_EBF16 and HWCAP2_SVE_EBF16 macro value (#70905)
Author: joyhou-hw
Date: 2023-11-23T10:17:55+08:00
New Revision: 0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc
URL:
https://github.com/llvm/llvm-project/commit/0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc
DIFF:
https://github.com/llvm/llvm-project/commit/0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc.diff
LOG: [compiler-rt] Fix the HWCAP2_EBF16 and HWCAP2_SVE_EBF16 macro value
(#70905)
HWCAP2_EBF16 (1UL << 32)
HWCAP2_SVE_EBF16 (1UL << 33)
this will overflow in aarch64 ilp32 abi, and make func
__init_cpu_features_constructor() wrong.
Added:
Modified:
compiler-rt/lib/builtins/cpu_model.c
Removed:
diff --git a/compiler-rt/lib/builtins/cpu_model.c
b/compiler-rt/lib/builtins/cpu_model.c
index aefa56abcdd9535..b0ec5e51e96d491 100644
--- a/compiler-rt/lib/builtins/cpu_model.c
+++ b/compiler-rt/lib/builtins/cpu_model.c
@@ -1137,10 +1137,10 @@ typedef struct __ifunc_arg_t {
#define HWCAP2_WFXT (1UL << 31)
#endif
#ifndef HWCAP2_EBF16
-#define HWCAP2_EBF16 (1UL << 32)
+#define HWCAP2_EBF16 (1ULL << 32)
#endif
#ifndef HWCAP2_SVE_EBF16
-#define HWCAP2_SVE_EBF16 (1UL << 33)
+#define HWCAP2_SVE_EBF16 (1ULL << 33)
#endif
// Detect Exynos 9810 CPU
___
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[llvm-branch-commits] [clang-tools-extra] [clang] [flang] [llvm] [libc] [compiler-rt] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [libc] [compiler-rt] [clang] [clang-tools-extra] [flang] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] b16f765 - [LinkerWrapper] Accept some needed lld-link linker arguments for COFF targets (#72889)
Author: Joseph Huber
Date: 2023-11-22T20:23:23-06:00
New Revision: b16f765d6fec56a07aecd2056bb1760a9e72d64f
URL:
https://github.com/llvm/llvm-project/commit/b16f765d6fec56a07aecd2056bb1760a9e72d64f
DIFF:
https://github.com/llvm/llvm-project/commit/b16f765d6fec56a07aecd2056bb1760a9e72d64f.diff
LOG: [LinkerWrapper] Accept some needed lld-link linker arguments for COFF
targets (#72889)
Summary:
The linker wrapper is a utility used to create offloading programs from
single-source offloading languages such as OpenMP or CUDA. This is done
by embedding device code into the host object, then feeding it into the
linker wrapper which extracts the accelerator object files, links them,
then wraps them in registration code for the target runtime. This
previously has only worked in Linux / ELF platforms.
This patch attempts to hand Windows / COFF inputs by also accepting COFF
forms of certain linker arguments we use internally. The important
arguments are library search paths, so we can identify libraries which
may contain device code, libraries themselves, and the output name used
for intermediate output.
I am not intimately familiar with the semantics here for the semantics
in how a `lib` file is earched. I am simply treating `foo.lib` as the
GNU equivalent `-l:foo.lib` in the search logic. Similarly, I am
assuming that static libraries will be llvm-ar style libraries. I will
need to investigate the actual deficiencies later, but this should be a
good starting point along with
https://github.com/llvm/llvm-project/pull/72697
Added:
Modified:
clang/test/Driver/linker-wrapper.c
clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
Removed:
diff --git a/clang/test/Driver/linker-wrapper.c
b/clang/test/Driver/linker-wrapper.c
index da7bdc22153ceae..e82febd61823102 100644
--- a/clang/test/Driver/linker-wrapper.c
+++ b/clang/test/Driver/linker-wrapper.c
@@ -140,3 +140,11 @@
// RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s
--check-prefix=CLANG-BACKEND
// CLANG-BACKEND: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa
-mcpu=gfx908 -O2 -Wl,--no-undefined {{.*}}.bc
+
+// RUN: clang-offload-packager -o %t.out \
+// RUN:
--image=file=%t.elf.o,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70
+// RUN: %clang -cc1 %s -triple x86_64-unknown-windows-msvc -emit-obj -o %t.o
-fembed-offload-object=%t.out
+// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-windows-msvc
--dry-run \
+// RUN: --linker-path=/usr/bin/lld-link -- %t.o -libpath:./ -out:a.exe 2>&1
| FileCheck %s --check-prefix=COFF
+
+// COFF: "/usr/bin/lld-link" {{.*}}.o -libpath:./ -out:a.exe
{{.*}}openmp.image.wrapper{{.*}}
diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
index bafe8ace60d1cea..db0ce3e2a190192 100644
--- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
@@ -254,7 +254,7 @@ Error runLinker(ArrayRef Files, const ArgList
&Args) {
continue;
Arg->render(Args, NewLinkerArgs);
-if (Arg->getOption().matches(OPT_o))
+if (Arg->getOption().matches(OPT_o) || Arg->getOption().matches(OPT_out))
llvm::transform(Files, std::back_inserter(NewLinkerArgs),
[&](StringRef Arg) { return Args.MakeArgString(Arg); });
}
@@ -1188,7 +1188,7 @@ searchLibraryBaseName(StringRef Name, StringRef Root,
/// `-lfoo` or `-l:libfoo.a`.
std::optional searchLibrary(StringRef Input, StringRef Root,
ArrayRef SearchPaths) {
- if (Input.startswith(":"))
+ if (Input.startswith(":") || Input.ends_with(".lib"))
return findFromSearchPaths(Input.drop_front(), Root, SearchPaths);
return searchLibraryBaseName(Input, Root, SearchPaths);
}
@@ -1339,7 +1339,7 @@ Expected> getDeviceInput(const
ArgList &Args) {
StringRef Root = Args.getLastArgValue(OPT_sysroot_EQ);
SmallVector LibraryPaths;
- for (const opt::Arg *Arg : Args.filtered(OPT_library_path))
+ for (const opt::Arg *Arg : Args.filtered(OPT_library_path, OPT_libpath))
LibraryPaths.push_back(Arg->getValue());
BumpPtrAllocator Alloc;
@@ -1348,7 +1348,7 @@ Expected> getDeviceInput(const
ArgList &Args) {
// Try to extract device code from the linker input files.
SmallVector InputFiles;
DenseMap> Syms;
- bool WholeArchive = false;
+ bool WholeArchive = Args.hasArg(OPT_wholearchive_flag) ? true : false;
for (const opt::Arg *Arg : Args.filtered(
OPT_INPUT, OPT_library, OPT_whole_archive, OPT_no_whole_archive)) {
if (Arg->getOption().matches(OPT_whole_archive) ||
@@ -1474,9 +1474,17 @@ int main(int Argc, char **Argv) {
Verbose = Args.hasArg(OPT_verbose);
DryRun = Args.hasArg(OPT_dry_run);
SaveTemps = Args.hasArg(OPT_save_te
[llvm-branch-commits] [llvm] 5973272 - [RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
Author: Wang Pengcheng
Date: 2023-11-23T14:05:23+08:00
New Revision: 5973272af796b33b75467ba8fba8b0a98b42757a
URL:
https://github.com/llvm/llvm-project/commit/5973272af796b33b75467ba8fba8b0a98b42757a
DIFF:
https://github.com/llvm/llvm-project/commit/5973272af796b33b75467ba8fba8b0a98b42757a.diff
LOG: [RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
This is like what AArch64 has done in #71166 except that we don't
handle `HasMinSize` case now.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/jumptable.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 97f9fb2223f1ae4..921b93c08ddde11 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1363,8 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
- setMinimumJumpTableEntries(5);
-
// Jumps are expensive, compared to logic
setJumpIsExpensive();
@@ -19701,6 +19699,11 @@ bool
RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
return AndMask.ugt(1024);
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
}
+
+unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
+ return Subtarget.getMinimumJumpTableEntries();
+}
+
namespace llvm::RISCVVIntrinsicsTable {
#define GET_RISCVVIntrinsicsTable_IMPL
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h
b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 3d6cd03c4d08f56..45200b54595a0b9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -962,6 +962,8 @@ class RISCVTargetLowering : public TargetLowering {
bool shouldFoldSelectWithSingleBitTest(EVT VT,
const APInt &AndMask) const override;
+
+ unsigned getMinimumJumpTableEntries() const override;
};
namespace RISCV {
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 95389b07e9c1cdb..90ba99d3f845d38 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -19,6 +19,8 @@ class RISCVTuneInfo {
bits<16> PrefetchDistance = 0;
bits<16> MinPrefetchStride = 1;
bits<32> MaxPrefetchIterationsAhead = -1;
+
+ bits<32> MinimumJumpTableEntries = 5;
}
def RISCVTuneInfoTable : GenericTable {
@@ -26,7 +28,8 @@ def RISCVTuneInfoTable : GenericTable {
let CppTypeName = "RISCVTuneInfo";
let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
"CacheLineSize", "PrefetchDistance",
-"MinPrefetchStride", "MaxPrefetchIterationsAhead"];
+"MinPrefetchStride", "MaxPrefetchIterationsAhead",
+"MinimumJumpTableEntries"];
}
def getRISCVTuneInfo : SearchIndex {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3e6af1abc5d408b..7b64d3cee9c8009 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -57,6 +57,10 @@ static cl::opt RISCVMaxBuildIntsCost(
static cl::opt UseAA("riscv-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));
+static cl::opt RISCVMinimumJumpTableEntries(
+"riscv-min-jump-table-entries", cl::Hidden,
+cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+
void RISCVSubtarget::anchor() {}
RISCVSubtarget &
@@ -189,3 +193,9 @@ void RISCVSubtarget::getPostRAMutations(
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool RISCVSubtarget::useAA() const { return UseAA; }
+
+unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
+ return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
+ ? RISCVMinimumJumpTableEntries
+ : TuneInfo->MinimumJumpTableEntries;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index c135021333acabc..52f00f1f099030c 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -44,6 +44,8 @@ struct RISCVTuneInfo {
uint16_t PrefetchDistance;
uint16_t MinPrefetchStride;
unsigned MaxPrefetchIterationsAhead;
+
+ unsigned MinimumJumpTableEntries;
};
#define GET_RISCVTuneInfoTable_DECL
@@ -270,6 +272,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMaxPrefetchIterationsAhead() const override {
[llvm-branch-commits] [clang] 2eb9c64 - [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (#73091)
Author: Jianjian Guan
Date: 2023-11-23T11:08:27+08:00
New Revision: 2eb9c649f0971aaa05404764d74ee7fff15b83ed
URL:
https://github.com/llvm/llvm-project/commit/2eb9c649f0971aaa05404764d74ee7fff15b83ed
DIFF:
https://github.com/llvm/llvm-project/commit/2eb9c649f0971aaa05404764d74ee7fff15b83ed.diff
LOG: [RISCV] Use Float type instead of Half type for Fixed RVV vector type
mangling (#73091)
Added:
Modified:
clang/lib/AST/ItaniumMangle.cpp
clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
Removed:
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 2a62ac0175afb72..b1678479888eb77 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
case BuiltinType::ULong:
TypeNameOS << "uint64";
break;
- case BuiltinType::Half:
+ case BuiltinType::Float16:
TypeNameOS << "float16";
break;
case BuiltinType::Float:
diff --git a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
index 98fb27b704fd81d..32bd49f4ff725db 100644
--- a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
+++ b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
@@ -1,23 +1,23 @@
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-64
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \
+// RUN: -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \
-// RUN: | FileCheck %s --check-prefix=CHECK-128
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \
+// RUN: -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \
-// RUN: | FileCheck %s --check-prefix=CHECK-256
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \
+// RUN: -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \
-// RUN: | FileCheck %s --check-prefix=CHECK-512
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \
+// RUN: -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \
-// RUN: | FileCheck %s --check-prefix=CHECK-1024
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \
+// RUN: -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024
typedef __rvv_int8mf8_t vint8mf8_t;
typedef __rvv_uint8mf8_t vuint8mf8_t;
@@ -26,6 +26,7 @@ typedef __rvv_int8mf4_t vint8mf4_t;
typedef __rvv_uint8mf4_t vuint8mf4_t;
typedef __rvv_int16mf4_t vint16mf4_t;
typedef __rvv_uint16mf4_t vuint16mf4_t;
+typedef __rvv_float16mf4_t vfloat16mf4_t;
typedef __rvv_int8mf2_t vint8mf2_t;
typedef __rvv_uint8mf2_t vuint8mf2_t;
@@ -33,6 +34,7 @@ typedef __rvv_int16mf2_t vint16mf2_t;
typedef __rvv_uint16mf2_t vuint16mf2_t;
typedef __rvv_int32mf2_t vint32mf2_t;
typedef __rvv_uint32mf2_t vuint32mf2_t;
+typedef __rvv_float16mf2_t vfloat16mf2_t;
typedef __rvv_float32mf2_t vfloat32mf2_t;
typedef __rvv_int8m1_t vint8m1_t;
@@ -43,6 +45,7 @@ typedef __rvv_int32m1_t vint32m1_t;
typedef __rvv_uint32m1_t vuint32m1_t;
typedef __rvv_int64m1_t vint64m1_t;
typedef __rvv_uint64m1_t vuint64m1_t;
+typedef __rvv_float16m1_t vfloat16m1_t;
typedef __rvv_float32m1_t vfloat32m1_t;
typedef __rvv_float64m1_t vfloat64m1_t;
@@ -54,6 +57,7 @@ typedef __rvv_int32m2_t vint32m2_t;
typedef __rvv_uint32m2_t vuint32m2_t;
typedef __rvv_int64m2_t vint64m2_t;
typedef __rvv_uint64m2_t vuint64m2_t;
+typedef __rvv_float16m2_t vfloat16m2_t;
typedef __rvv_float32m2_t vfloat32m2_t;
typedef __rvv_float64m2_t vfloat64m2_t;
@@ -65,6 +69,7 @@ typedef __rvv_int32m4_t vint32m4_t;
typedef __r
[llvm-branch-commits] [llvm] 9ab133b - [nfc][InstrProfTest]Parameterize the edge cases of value profile merge by value kind (#73165)
Author: Mingming Liu
Date: 2023-11-22T21:22:20-08:00
New Revision: 9ab133bd9f9cedb880b453dd830b58857fab41ec
URL:
https://github.com/llvm/llvm-project/commit/9ab133bd9f9cedb880b453dd830b58857fab41ec
DIFF:
https://github.com/llvm/llvm-project/commit/9ab133bd9f9cedb880b453dd830b58857fab41ec.diff
LOG: [nfc][InstrProfTest]Parameterize the edge cases of value profile merge by
value kind (#73165)
There are three test cases to test the merge of value profiles.
'get_icall_data_merge1' tests the basic case;
{get_icall_data_merge1_saturation, get_icall_data_merge_site_trunc} tests the
edge case.
This patch parameterizes the edge case test coverage by value kind and adds the
coverage of 'IPVK_MemOPSize'. Keep the basic test structure as it is. The main
reason is test data construction and test assertions is
clearer for each kind in the basic test.
- Using a loop for different value kinds in one test case doesn't work
very well. The instr-prof-writer is stateful (e.g., keeps track of
per-function profile data in a
[container](https://github.com/llvm/llvm-project/blob/a9c149df7666bb2f8755794b97573134e5cfeb38/llvm/include/llvm/ProfileData/InstrProfWriter.h#L43))
Added:
Modified:
llvm/unittests/ProfileData/InstrProfTest.cpp
Removed:
diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp
b/llvm/unittests/ProfileData/InstrProfTest.cpp
index 875e2d06d839367..e6613a90dc7c53e 100644
--- a/llvm/unittests/ProfileData/InstrProfTest.cpp
+++ b/llvm/unittests/ProfileData/InstrProfTest.cpp
@@ -815,7 +815,7 @@ TEST_P(MaybeSparseInstrProfTest, annotate_vp_data) {
ASSERT_EQ(1U, ValueData[3].Count);
}
-TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1) {
+TEST_P(MaybeSparseInstrProfTest, icall_data_merge) {
static const char caller[] = "caller";
NamedInstrProfRecord Record11(caller, 0x1234, {1, 2});
NamedInstrProfRecord Record12(caller, 0x1234, {1, 2});
@@ -920,8 +920,18 @@ TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1) {
ASSERT_EQ(2U, VD_4[2].Count);
}
-TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1_saturation) {
+struct ValueProfileMergeEdgeCaseTest
+: public InstrProfTest,
+ public ::testing::WithParamInterface> {
+ void SetUp() override { Writer.setOutputSparse(std::get<0>(GetParam())); }
+
+ uint32_t getValueProfileKind() const { return std::get<1>(GetParam()); }
+};
+
+TEST_P(ValueProfileMergeEdgeCaseTest, value_profile_data_merge_saturation) {
+ const uint32_t ValueKind = getValueProfileKind();
static const char bar[] = "bar";
+ const uint64_t ProfiledValue = 0x5678;
const uint64_t MaxValCount = std::numeric_limits::max();
const uint64_t MaxEdgeCount = getInstrMaxCountValue();
@@ -944,18 +954,18 @@ TEST_P(MaybeSparseInstrProfTest,
get_icall_data_merge1_saturation) {
ASSERT_EQ(Result, instrprof_error::success);
NamedInstrProfRecord Record4("baz", 0x5678, {3, 4});
- Record4.reserveSites(IPVK_IndirectCallTarget, 1);
- InstrProfValueData VD4[] = {{uint64_t(bar), 1}};
- Record4.addValueData(IPVK_IndirectCallTarget, 0, VD4, 1, nullptr);
+ Record4.reserveSites(ValueKind, 1);
+ InstrProfValueData VD4[] = {{ProfiledValue, 1}};
+ Record4.addValueData(ValueKind, 0, VD4, 1, nullptr);
Result = instrprof_error::success;
Writer.addRecord(std::move(Record4), Err);
ASSERT_EQ(Result, instrprof_error::success);
// Verify value data counter overflow.
NamedInstrProfRecord Record5("baz", 0x5678, {5, 6});
- Record5.reserveSites(IPVK_IndirectCallTarget, 1);
- InstrProfValueData VD5[] = {{uint64_t(bar), MaxValCount}};
- Record5.addValueData(IPVK_IndirectCallTarget, 0, VD5, 1, nullptr);
+ Record5.reserveSites(ValueKind, 1);
+ InstrProfValueData VD5[] = {{ProfiledValue, MaxValCount}};
+ Record5.addValueData(ValueKind, 0, VD5, 1, nullptr);
Result = instrprof_error::success;
Writer.addRecord(std::move(Record5), Err);
ASSERT_EQ(Result, instrprof_error::counter_overflow);
@@ -966,48 +976,48 @@ TEST_P(MaybeSparseInstrProfTest,
get_icall_data_merge1_saturation) {
// Verify saturation of counts.
Expected ReadRecord1 =
Reader->getInstrProfRecord("foo", 0x1234);
- EXPECT_THAT_ERROR(ReadRecord1.takeError(), Succeeded());
- ASSERT_EQ(MaxEdgeCount, ReadRecord1->Counts[0]);
+ ASSERT_THAT_ERROR(ReadRecord1.takeError(), Succeeded());
+ EXPECT_EQ(MaxEdgeCount, ReadRecord1->Counts[0]);
Expected ReadRecord2 =
Reader->getInstrProfRecord("baz", 0x5678);
ASSERT_TRUE(bool(ReadRecord2));
- ASSERT_EQ(1U, ReadRecord2->getNumValueSites(IPVK_IndirectCallTarget));
+ ASSERT_EQ(1U, ReadRecord2->getNumValueSites(ValueKind));
std::unique_ptr VD =
- ReadRecord2->getValueForSite(IPVK_IndirectCallTarget, 0);
- ASSERT_EQ(StringRef("bar"), StringRef((const char *)VD[0].Value, 3));
- ASSERT_EQ(MaxValCount, VD[0].Count);
+ ReadRecord2->getValueForSite(ValueKind, 0);
+ EXPECT_EQ(ProfiledValue, VD[0].Value);
+ EXPECT
[llvm-branch-commits] [flang] 7f18f9a - [flang][openacc][NFC] Merge acc-declare.f90 tests (#73055)
Author: Valentin Clement (バレンタイン クレメン)
Date: 2023-11-22T22:19:06-08:00
New Revision: 7f18f9a28c73490d09938af1fdb1908eb333a62c
URL:
https://github.com/llvm/llvm-project/commit/7f18f9a28c73490d09938af1fdb1908eb333a62c
DIFF:
https://github.com/llvm/llvm-project/commit/7f18f9a28c73490d09938af1fdb1908eb333a62c.diff
LOG: [flang][openacc][NFC] Merge acc-declare.f90 tests (#73055)
Added:
Modified:
flang/test/Lower/OpenACC/acc-declare.f90
Removed:
flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
diff --git a/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
b/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
deleted file mode 100644
index 17d1e5010d0a663..000
--- a/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
+++ /dev/null
@@ -1,314 +0,0 @@
-! This test checks lowering of OpenACC declare directive in function and
-! subroutine specification parts.
-
-! RUN: bbc -fopenacc -emit-hlfir %s -o - | FileCheck %s
-
-module acc_declare
- contains
-
- subroutine acc_declare_copy()
-integer :: a(100), i
-!$acc declare copy(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_copy()
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xi32> {bindc_name =
"a", uniq_name = "_QMacc_declareFacc_declare_copyEa"}
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) {acc.declare
= #acc.declare, uniq_name =
"_QMacc_declareFacc_declare_copyEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%[[C1]] : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[COPYIN:.*]] = acc.copyin varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {dataClause = #acc, name =
"a"}
-! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[COPYIN]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%{{.*}} = %{{.*}}) -> (index, i32) {
-! CHECK: }
-! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[COPYIN]] :
!fir.ref>)
-! CHECK: acc.copyout accPtr(%[[COPYIN]] : !fir.ref>)
bounds(%[[BOUND]]) to varPtr(%[[DECL]]#1 : !fir.ref>)
{dataClause = #acc, name = "a"}
-! CHECK: return
-
- subroutine acc_declare_create()
-integer :: a(100), i
-!$acc declare create(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_create() {
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xi32> {bindc_name =
"a", uniq_name = "_QMacc_declareFacc_declare_createEa"}
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) {acc.declare
= #acc.declare, uniq_name =
"_QMacc_declareFacc_declare_createEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%[[C1]] : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {name = "a"}
-! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[CREATE]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%{{.*}} = %{{.*}}) -> (index, i32) {
-! CHECK: }
-! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[CREATE]] :
!fir.ref>)
-! CHECK: acc.delete accPtr(%[[CREATE]] : !fir.ref>)
bounds(%[[BOUND]]) {dataClause = #acc, name = "a"}
-! CHECK: return
-
- subroutine acc_declare_present(a)
-integer :: a(100), i
-!$acc declare present(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_present(
-! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name =
"a"})
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare =
#acc.declare, uniq_name =
"_QMacc_declareFacc_declare_presentEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[PRESENT:.*]] = acc.present varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {name = "a"}
-! CHECK: acc.declare_enter dataOperands(%[[PRESENT]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%arg{{.*}} = %{{.*}}) -> (index, i32)
-
- subroutine acc_declare_copyin()
-integer :: a(100), b(10), i
-!$acc declare copyin(a) copyin(readonly: b)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func
[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Author: Craig Topper
Date: 2023-11-22T19:49:52-08:00
New Revision: dc683d2e66de79bbea786f51788961eec5d0b793
URL:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793
DIFF:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff
LOG: [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Added:
Modified:
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 008075163b90a8d..f6fe7c9be7e4f46 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -422,7 +422,6 @@ class X86AsmParser : public MCTargetAsmParser {
IES_RPAREN,
IES_REGISTER,
IES_INTEGER,
-IES_IDENTIFIER,
IES_ERROR
};
___
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llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [clang] 083a539 - clang/CodeGen/RISCV: test lowering of math builtins (#71399)
Author: Ramkumar Ramachandra
Date: 2023-11-23T07:39:32Z
New Revision: 083a53971758c6f9bbd448eeb9c5d839661e3f68
URL:
https://github.com/llvm/llvm-project/commit/083a53971758c6f9bbd448eeb9c5d839661e3f68
DIFF:
https://github.com/llvm/llvm-project/commit/083a53971758c6f9bbd448eeb9c5d839661e3f68.diff
LOG: clang/CodeGen/RISCV: test lowering of math builtins (#71399)
Ever since 98c90a1 (ISel: introduce vector ISD::LRINT, ISD::LLRINT;
custom RISCV lowering) landed, there have been several discussions on
how the lrint and llrint libcalls would lower to LLVM IR via clang on
RV32 and RV64, in an effort to enable vectorization of lrint and llrint
via SLPVectorizer and LoopVectorize. This patch adds a new
math-builtins.c test to the RISC-V target to test the lowering of all
math libcalls, including lrint and llrint.
Added:
clang/test/CodeGen/RISCV/math-builtins.c
clang/test/CodeGen/X86/math-builtins.c
Modified:
Removed:
clang/test/CodeGen/math-builtins.c
diff --git a/clang/test/CodeGen/RISCV/math-builtins.c
b/clang/test/CodeGen/RISCV/math-builtins.c
new file mode 100644
index 000..9630d62f0f48292
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/math-builtins.c
@@ -0,0 +1,459 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck
--check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - | FileCheck
--check-prefix=RV64 %s
+
+float ceilf(float);
+double ceil(double);
+long double ceill(long double);
+float copysignf(float, float);
+double copysign(double, double);
+long double copysignl(long double, long double);
+float cosf(float);
+double cos(double);
+long double cosl(long double);
+float expf(float);
+double exp(double);
+long double expl(long double);
+float exp2f(float);
+double exp2(double);
+long double exp2l(long double);
+float fabsf(float);
+double fabs(double);
+long double fabsl(long double);
+float floorf(float);
+double floor(double);
+long double floorl(long double);
+float fmaxf(float, float);
+double fmax(double, double);
+long double fmaxl(long double, long double);
+float fminf(float, float);
+double fmin(double, double);
+long double fminl(long double, long double);
+float fmodf(float, float);
+double fmod(double, double);
+long double fmodl(long double, long double);
+float logf(float);
+double log(double);
+long double logl(long double);
+float log10f(float);
+double log10(double);
+long double log10l(long double);
+float log2f(float);
+double log2(double);
+long double log2l(long double);
+float nearbyintf(float);
+double nearbyint(double);
+long double nearbyintl(long double);
+float powf(float, float);
+double pow(double, double);
+long double powl(long double, long double);
+float rintf(float);
+double rint(double);
+long double rintl(long double);
+long lrintf(float);
+long lrint(double);
+long lrintl(long double);
+long long llrintf(float);
+long long llrint(double);
+long long llrintl(long double);
+float roundf(float);
+double round(double);
+long double roundl(long double);
+long lroundf(float);
+long lround(double);
+long lroundl(long double);
+long long llroundf(float);
+long long llround(double);
+long long llroundl(long double);
+float roundevenf(float);
+double roundeven(double);
+long double roundevenl(long double);
+float sinf(float);
+double sin(double);
+long double sinl(long double);
+float sqrtf(float);
+double sqrt(double);
+long double sqrtl(long double);
+float truncf(float);
+double trunc(double);
+long double truncl(long double);
+
+// RV32-LABEL: define dso_local void @test(
+// RV32-SAME: float noundef [[FARG:%.*]], double noundef [[DARG:%.*]], fp128
noundef [[LDARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// RV32-NEXT: entry:
+// RV32-NEXT:[[FARG_ADDR:%.*]] = alloca float, align 4
+// RV32-NEXT:[[DARG_ADDR:%.*]] = alloca double, align 8
+// RV32-NEXT:[[LDARG_ADDR:%.*]] = alloca fp128, align 16
+// RV32-NEXT:store float [[FARG]], ptr [[FARG_ADDR]], align 4
+// RV32-NEXT:store double [[DARG]], ptr [[DARG_ADDR]], align 8
+// RV32-NEXT:store fp128 [[LDARG]], ptr [[LDARG_ADDR]], align 16
+// RV32-NEXT:[[TMP0:%.*]] = load float, ptr [[FARG_ADDR]], align 4
+// RV32-NEXT:[[TMP1:%.*]] = call float @llvm.ceil.f32(float [[TMP0]])
+// RV32-NEXT:[[TMP2:%.*]] = load double, ptr [[DARG_ADDR]], align 8
+// RV32-NEXT:[[TMP3:%.*]] = call double @llvm.ceil.f64(double [[TMP2]])
+// RV32-NEXT:[[TMP4:%.*]] = load fp128, ptr [[LDARG_ADDR]], align 16
+// RV32-NEXT:[[TMP5:%.*]] = call fp128 @llvm.ceil.f128(fp128 [[TMP4]])
+// RV32-NEXT:[[TMP6:%.*]] = load float, ptr [[FARG_ADDR]], align 4
+// RV32-NEXT:[[TMP7:%.*]] = load float, ptr [[FARG_ADDR]], align 4
+// RV32-NEXT:[[TMP8:%.*]] = call float @llvm.copysign.f32(float [[TMP6]],
float [[TMP7]])
+// RV32-NEXT:[[TMP9:%.*]] = load double, p
[llvm-branch-commits] [clang] 0d2860b - [clang] Avoid memcopy for small structure with padding under -ftrivial-auto-var-init (#71677)
Author: serge-sans-paille
Date: 2023-11-23T05:38:14Z
New Revision: 0d2860b795879f4dd152963b52f969b53b136899
URL:
https://github.com/llvm/llvm-project/commit/0d2860b795879f4dd152963b52f969b53b136899
DIFF:
https://github.com/llvm/llvm-project/commit/0d2860b795879f4dd152963b52f969b53b136899.diff
LOG: [clang] Avoid memcopy for small structure with padding under
-ftrivial-auto-var-init (#71677)
Added:
Modified:
clang/lib/CodeGen/CGDecl.cpp
clang/test/CodeGenCXX/auto-var-init.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp
index e5795d811c76de7..a5da0aa2965a000 100644
--- a/clang/lib/CodeGen/CGDecl.cpp
+++ b/clang/lib/CodeGen/CGDecl.cpp
@@ -1244,29 +1244,24 @@ static void emitStoresForConstant(CodeGenModule &CGM,
const VarDecl &D,
// If the initializer is small, use a handful of stores.
if (shouldSplitConstantStore(CGM, ConstantSize)) {
if (auto *STy = dyn_cast(Ty)) {
- // FIXME: handle the case when STy != Loc.getElementType().
- if (STy == Loc.getElementType()) {
-for (unsigned i = 0; i != constant->getNumOperands(); i++) {
- Address EltPtr = Builder.CreateStructGEP(Loc, i);
- emitStoresForConstant(
- CGM, D, EltPtr, isVolatile, Builder,
- cast(Builder.CreateExtractValue(constant, i)),
- IsAutoInit);
-}
-return;
+ const llvm::StructLayout *Layout =
+ CGM.getDataLayout().getStructLayout(STy);
+ for (unsigned i = 0; i != constant->getNumOperands(); i++) {
+CharUnits CurOff =
CharUnits::fromQuantity(Layout->getElementOffset(i));
+Address EltPtr = Builder.CreateConstInBoundsByteGEP(
+Loc.withElementType(CGM.Int8Ty), CurOff);
+emitStoresForConstant(CGM, D, EltPtr, isVolatile, Builder,
+ constant->getAggregateElement(i), IsAutoInit);
}
+ return;
} else if (auto *ATy = dyn_cast(Ty)) {
- // FIXME: handle the case when ATy != Loc.getElementType().
- if (ATy == Loc.getElementType()) {
-for (unsigned i = 0; i != ATy->getNumElements(); i++) {
- Address EltPtr = Builder.CreateConstArrayGEP(Loc, i);
- emitStoresForConstant(
- CGM, D, EltPtr, isVolatile, Builder,
- cast(Builder.CreateExtractValue(constant, i)),
- IsAutoInit);
-}
-return;
+ for (unsigned i = 0; i != ATy->getNumElements(); i++) {
+Address EltPtr = Builder.CreateConstGEP(
+Loc.withElementType(ATy->getElementType()), i);
+emitStoresForConstant(CGM, D, EltPtr, isVolatile, Builder,
+ constant->getAggregateElement(i), IsAutoInit);
}
+ return;
}
}
diff --git a/clang/test/CodeGenCXX/auto-var-init.cpp
b/clang/test/CodeGenCXX/auto-var-init.cpp
index 6cb18528ebadcdf..e5a9d015f22f276 100644
--- a/clang/test/CodeGenCXX/auto-var-init.cpp
+++ b/clang/test/CodeGenCXX/auto-var-init.cpp
@@ -89,22 +89,14 @@ struct padded { char c; int i; };
// PATTERN-O1-NOT: @__const.test_paddednullinit_custom.custom
struct paddednullinit { char c = 0; int i = 0; };
// PATTERN-O0: @__const.test_paddedpacked_uninit.uninit = private unnamed_addr
constant %struct.paddedpacked <{ i8 [[I8]], i32 [[I32]] }>, align 1
-// PATTERN: @__const.test_paddedpacked_custom.custom = private unnamed_addr
constant %struct.paddedpacked <{ i8 42, i32 13371337 }>, align 1
-// ZERO: @__const.test_paddedpacked_custom.custom = private unnamed_addr
constant %struct.paddedpacked <{ i8 42, i32 13371337 }>, align 1
struct paddedpacked { char c; int i; } __attribute__((packed));
// PATTERN-O0: @__const.test_paddedpackedarray_uninit.uninit = private
unnamed_addr constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 [[I8]], i32 [[I32]] }>, %struct.paddedpacked <{ i8
[[I8]], i32 [[I32]] }>] }, align 1
-// PATTERN: @__const.test_paddedpackedarray_custom.custom = private
unnamed_addr constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 42, i32 13371337 }>, %struct.paddedpacked <{ i8 43,
i32 13371338 }>] }, align 1
-// ZERO: @__const.test_paddedpackedarray_custom.custom = private unnamed_addr
constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 42, i32 13371337 }>, %struct.paddedpacked <{ i8 43,
i32 13371338 }>] }, align 1
struct paddedpackedarray { struct paddedpacked p[2]; };
// PATTERN-O0: @__const.test_unpackedinpacked_uninit.uninit = private
unnamed_addr constant <{ { i8, [3 x i8], i32 }, i8 }> <{ { i8, [3 x i8], i32 }
{ i8 [[I8]], [3 x i8] c"\[[IC]]\[[IC]]\[[IC]]", i32 [[I32]] }, i8 [[I8]] }>,
align 1
struct unpackedinpacked { padded a; char b; } __attribute__((packed));
// PATTERN-O0: @__const.test_paddednested_uninit.uninit = private unnamed_addr
constant { {
[llvm-branch-commits] [llvm] 7414c0d - [LoongArch] Precommit a test for smul with overflow (NFC) (#73212)
Author: hev
Date: 2023-11-23T15:15:26+08:00
New Revision: 7414c0db962f8a5029fd44c3e0bc93d9ce20be71
URL:
https://github.com/llvm/llvm-project/commit/7414c0db962f8a5029fd44c3e0bc93d9ce20be71
DIFF:
https://github.com/llvm/llvm-project/commit/7414c0db962f8a5029fd44c3e0bc93d9ce20be71.diff
LOG: [LoongArch] Precommit a test for smul with overflow (NFC) (#73212)
Added:
llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
b/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
new file mode 100644
index 000..a53e77e5aa4b342
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+define zeroext i1 @smuloi64(i64 %v1, i64 %v2, ptr %res) {
+; LA32-LABEL: smuloi64:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:st.w $fp, $sp, 8 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:.cfi_offset 22, -8
+; LA32-NEXT:move $fp, $a4
+; LA32-NEXT:st.w $zero, $sp, 4
+; LA32-NEXT:addi.w $a4, $sp, 4
+; LA32-NEXT:bl %plt(__mulodi4)
+; LA32-NEXT:st.w $a1, $fp, 4
+; LA32-NEXT:st.w $a0, $fp, 0
+; LA32-NEXT:ld.w $a0, $sp, 4
+; LA32-NEXT:sltu $a0, $zero, $a0
+; LA32-NEXT:ld.w $fp, $sp, 8 # 4-byte Folded Reload
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: smuloi64:
+; LA64: # %bb.0:
+; LA64-NEXT:mul.d $a3, $a0, $a1
+; LA64-NEXT:st.d $a3, $a2, 0
+; LA64-NEXT:mulh.d $a0, $a0, $a1
+; LA64-NEXT:srai.d $a1, $a3, 63
+; LA64-NEXT:xor $a0, $a0, $a1
+; LA64-NEXT:sltu $a0, $zero, $a0
+; LA64-NEXT:ret
+ %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, ptr %res
+ ret i1 %obit
+}
+
+define zeroext i1 @smuloi128(i128 %v1, i128 %v2, ptr %res) {
+; LA32-LABEL: smuloi128:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -64
+; LA32-NEXT:.cfi_def_cfa_offset 64
+; LA32-NEXT:st.w $ra, $sp, 60 # 4-byte Folded Spill
+; LA32-NEXT:st.w $fp, $sp, 56 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:.cfi_offset 22, -8
+; LA32-NEXT:move $fp, $a2
+; LA32-NEXT:st.w $zero, $sp, 52
+; LA32-NEXT:ld.w $a2, $a1, 12
+; LA32-NEXT:st.w $a2, $sp, 12
+; LA32-NEXT:ld.w $a2, $a1, 8
+; LA32-NEXT:st.w $a2, $sp, 8
+; LA32-NEXT:ld.w $a2, $a1, 4
+; LA32-NEXT:st.w $a2, $sp, 4
+; LA32-NEXT:ld.w $a1, $a1, 0
+; LA32-NEXT:st.w $a1, $sp, 0
+; LA32-NEXT:ld.w $a1, $a0, 12
+; LA32-NEXT:st.w $a1, $sp, 28
+; LA32-NEXT:ld.w $a1, $a0, 8
+; LA32-NEXT:st.w $a1, $sp, 24
+; LA32-NEXT:ld.w $a1, $a0, 4
+; LA32-NEXT:st.w $a1, $sp, 20
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:st.w $a0, $sp, 16
+; LA32-NEXT:addi.w $a0, $sp, 32
+; LA32-NEXT:addi.w $a1, $sp, 16
+; LA32-NEXT:addi.w $a2, $sp, 0
+; LA32-NEXT:addi.w $a3, $sp, 52
+; LA32-NEXT:bl %plt(__muloti4)
+; LA32-NEXT:ld.w $a0, $sp, 44
+; LA32-NEXT:st.w $a0, $fp, 12
+; LA32-NEXT:ld.w $a0, $sp, 40
+; LA32-NEXT:st.w $a0, $fp, 8
+; LA32-NEXT:ld.w $a0, $sp, 36
+; LA32-NEXT:st.w $a0, $fp, 4
+; LA32-NEXT:ld.w $a0, $sp, 32
+; LA32-NEXT:st.w $a0, $fp, 0
+; LA32-NEXT:ld.w $a0, $sp, 52
+; LA32-NEXT:sltu $a0, $zero, $a0
+; LA32-NEXT:ld.w $fp, $sp, 56 # 4-byte Folded Reload
+; LA32-NEXT:ld.w $ra, $sp, 60 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 64
+; LA32-NEXT:ret
+;
+; LA64-LABEL: smuloi128:
+; LA64: # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -32
+; LA64-NEXT:.cfi_def_cfa_offset 32
+; LA64-NEXT:st.d $ra, $sp, 24 # 8-byte Folded Spill
+; LA64-NEXT:st.d $fp, $sp, 16 # 8-byte Folded Spill
+; LA64-NEXT:.cfi_offset 1, -8
+; LA64-NEXT:.cfi_offset 22, -16
+; LA64-NEXT:move $fp, $a4
+; LA64-NEXT:st.d $zero, $sp, 8
+; LA64-NEXT:addi.d $a4, $sp, 8
+; LA64-NEXT:bl %plt(__muloti4)
+; LA64-NEXT:st.d $a1, $fp, 8
+; LA64-NEXT:st.d $a0, $fp, 0
+; LA64-NEXT:ld.d $a0, $sp, 8
+; LA64-NEXT:sltu $a0, $zero, $a0
+; LA64-NEXT:ld.d $fp, $sp, 16 # 8-byte Folded Reload
+; LA64-NEXT:ld.d $ra, $sp, 24 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 32
+; LA64-NEXT:ret
+ %t = call {i128, i1} @llvm.smul.with.overflow.i128(i128 %v1, i128 %v2)
+ %val = extractvalue {i128, i1} %t, 0
+ %obit = extractvalue {i128, i1} %t, 1
+ store i128 %val, ptr %r
[llvm-branch-commits] [llvm] d76d8e5 - [AMDGPU][NFC] Update GISel memory-legalizer-atomic-fence test (#72829)
Author: Pierre van Houtryve
Date: 2023-11-23T09:09:05+01:00
New Revision: d76d8e541dab6d65b2490957707341352eac8320
URL:
https://github.com/llvm/llvm-project/commit/d76d8e541dab6d65b2490957707341352eac8320
DIFF:
https://github.com/llvm/llvm-project/commit/d76d8e541dab6d65b2490957707341352eac8320.diff
LOG: [AMDGPU][NFC] Update GISel memory-legalizer-atomic-fence test (#72829)
Test needs to be moved to MIR checks and use
stop-after=si-memory-legalizer to avoid being optimized out in a future
patch.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
Removed:
diff --git
a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
index 0fbfe4cb6f35f13..601cc791c04141a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
@@ -1,720 +1,1510 @@
-; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx600
-verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx803
-verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803
-verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010
-verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP
%s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010
-mattr=+cumode -verify-machineinstrs < %s | FileCheck
-check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100
-verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP
%s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100
-mattr=+cumode -verify-machineinstrs < %s | FileCheck
-check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
-
-; FUNC-LABEL: {{^}}system_one_as_acquire:
-; GCN:%bb.0
-; GCN-NOT:ATOMIC_FENCE
-; GFX6: s_waitcnt vmcnt(0){{$}}
-; GFX6-NEXT: buffer_wbinvl1{{$}}
-; GFX8: s_waitcnt vmcnt(0){{$}}
-; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
-; GFX10: s_waitcnt vmcnt(0){{$}}
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0{{$}}
-; GFX10-NEXT: buffer_gl0_inv{{$}}
-; GFX10-NEXT: buffer_gl1_inv{{$}}
-; GCN:s_endpgm
-; GFX10: .amdhsa_kernel system_one_as_acquire
-; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
-; GFX10CU: .amdhsa_workgroup_processor_mode 0
-; GFX10-NOT: .amdhsa_memory_ordered 0
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-
-mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer -mtriple=amdgcn-amd-
-mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck
-check-prefix=GFX8 %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck
-check-prefix=GFX10WGP %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs <
%s | FileCheck -check-prefix=GFX10CU %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck
-check-prefix=GFX11WGP %s
+; RUN: llc -global-isel -stop-after=si-memory-legalizer
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+cumode -verify-machineinstrs <
%s | FileCheck -check-prefix=GFX11CU %s
+
+; Note: we use MIR test checks + stop after legalizer to prevent
+; tests from being optimized out.
+
define amdgpu_kernel void @system_one_as_acquire() {
+ ; GFX6-LABEL: name: system_one_as_acquire
+ ; GFX6: bb.0.entry:
+ ; GFX6-NEXT: S_WAITCNT 3952
+ ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0
+ ;
+ ; GFX8-LABEL: name: system_one_as_acquire
+ ; GFX8: bb.0.entry:
+ ; GFX8-NEXT: S_WAITCNT 3952
+ ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec
+ ; GFX8-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10WGP-LABEL: name: system_one_as_acquire
+ ; GFX10WGP: bb.0.entry:
+ ; GFX10WGP-NEXT: S_WAITCNT 16240
+ ; GFX10WGP-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
+ ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec
+ ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec
+ ; GFX10WGP-NEXT: S_ENDPGM 0
+ ;
+ ; GFX10CU-LABEL: name: system_one_as_acquire
+ ; GFX10CU: bb.0.entry:
+ ; GFX10CU-NEXT: S_WAITCNT 16240
+ ; GFX10CU-NEXT: S_WAITCNT_VSC
[llvm-branch-commits] [flang] 49f55d1 - Revert "[Flang] Add partial support for lowering procedure pointer assignment. (#70461)"
Author: Muhammad Omair Javaid
Date: 2023-11-23T12:30:40+05:00
New Revision: 49f55d107548a340992eaec1b9767c0f8fc443cd
URL:
https://github.com/llvm/llvm-project/commit/49f55d107548a340992eaec1b9767c0f8fc443cd
DIFF:
https://github.com/llvm/llvm-project/commit/49f55d107548a340992eaec1b9767c0f8fc443cd.diff
LOG: Revert "[Flang] Add partial support for lowering procedure pointer
assignment. (#70461)"
This reverts commit e07fec10ac208c2868a24c5c0be88e45778b297e.
This change appears to have broken following buildbots:
https://lab.llvm.org/buildbot/#/builders/176
https://lab.llvm.org/buildbot/#/builders/179
https://lab.llvm.org/buildbot/#/builders/184
https://lab.llvm.org/buildbot/#/builders/197
https://lab.llvm.org/buildbot/#/builders/198
All bots fails in testsuite where following tests seems broken:
(eg: https://lab.llvm.org/buildbot/#/builders/176/builds/7131)
test-suite::gfortran-regression-compile-regression__proc_ptr_46_f90.test
test-suite::gfortran-regression-compile-regression__proc_ptr_37_f90.test
Added:
Modified:
flang/include/flang/Lower/BoxAnalyzer.h
flang/include/flang/Lower/CallInterface.h
flang/include/flang/Lower/ConvertProcedureDesignator.h
flang/include/flang/Optimizer/Builder/FIRBuilder.h
flang/include/flang/Optimizer/Builder/HLFIRTools.h
flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h
flang/lib/Lower/Bridge.cpp
flang/lib/Lower/CallInterface.cpp
flang/lib/Lower/ConvertCall.cpp
flang/lib/Lower/ConvertExpr.cpp
flang/lib/Lower/ConvertExprToHLFIR.cpp
flang/lib/Lower/ConvertProcedureDesignator.cpp
flang/lib/Lower/ConvertType.cpp
flang/lib/Lower/ConvertVariable.cpp
flang/lib/Optimizer/Builder/FIRBuilder.cpp
flang/lib/Optimizer/Builder/HLFIRTools.cpp
Removed:
flang/test/Lower/HLFIR/procedure-pointer.f90
diff --git a/flang/include/flang/Lower/BoxAnalyzer.h
b/flang/include/flang/Lower/BoxAnalyzer.h
index 3b8e2455ff273be..52cded8b219d835 100644
--- a/flang/include/flang/Lower/BoxAnalyzer.h
+++ b/flang/include/flang/Lower/BoxAnalyzer.h
@@ -382,8 +382,6 @@ class BoxAnalyzer : public
fir::details::matcher {
/// Run the analysis on `sym`.
void analyze(const Fortran::semantics::Symbol &sym) {
-if (Fortran::semantics::IsProcedurePointer(sym))
- return;
if (symIsArray(sym)) {
bool isConstant = !isAssumedSize(sym);
llvm::SmallVector lbounds;
diff --git a/flang/include/flang/Lower/CallInterface.h
b/flang/include/flang/Lower/CallInterface.h
index c7dca4f8f1348e0..579bdcfd8988792 100644
--- a/flang/include/flang/Lower/CallInterface.h
+++ b/flang/include/flang/Lower/CallInterface.h
@@ -111,8 +111,7 @@ class CallInterface {
CharBoxValueAttribute, // BoxChar with VALUE
// Passing a character procedure as a
// tuple.
-CharProcTuple,
-BoxProcRef
+CharProcTuple
};
/// Different properties of an entity that can be passed/returned.
/// One-to-One mapping with PassEntityBy but for
@@ -125,8 +124,7 @@ class CallInterface {
CharProcTuple,
Box,
MutableBox,
-Value,
-BoxProcRef
+Value
};
using FortranEntity = typename PassedEntityTypes::FortranEntity;
diff --git a/flang/include/flang/Lower/ConvertProcedureDesignator.h
b/flang/include/flang/Lower/ConvertProcedureDesignator.h
index ae772c52e425bc1..86a757a9aadf4f4 100644
--- a/flang/include/flang/Lower/ConvertProcedureDesignator.h
+++ b/flang/include/flang/Lower/ConvertProcedureDesignator.h
@@ -19,8 +19,6 @@
namespace mlir {
class Location;
-class Value;
-class Type;
}
namespace fir {
class ExtendedValue;
@@ -31,9 +29,6 @@ class EntityWithAttributes;
namespace Fortran::evaluate {
struct ProcedureDesignator;
}
-namespace Fortran::semantics {
-class Symbol;
-}
namespace Fortran::lower {
class AbstractConverter;
@@ -55,10 +50,5 @@ hlfir::EntityWithAttributes
convertProcedureDesignatorToHLFIR(
const Fortran::evaluate::ProcedureDesignator &proc,
Fortran::lower::SymMap &symMap, Fortran::lower::StatementContext &stmtCtx);
-/// Generate initialization for procedure pointer to procedure target.
-mlir::Value
-convertProcedureDesignatorInitialTarget(Fortran::lower::AbstractConverter &,
-mlir::Location,
-const Fortran::semantics::Symbol &sym);
} // namespace Fortran::lower
#endif // FORTRAN_LOWER_CONVERT_PROCEDURE_DESIGNATOR_H
diff --git a/flang/include/flang/Optimizer/Builder/FIRBuilder.h
b/flang/include/flang/Optimizer/Builder/FIRBuilder.h
index b5b2c99810b15bb..0b36186d68a4614 100644
--- a/flang/include/flang/Optimizer/Builder/FIRBuilder.h
+++ b/flang/include/flang/Optimizer/Builder/FIRBuilder.h
@@ -677,10 +677,6 @@ mlir::Value genCPtrOrCFunptrValue(fir::FirOpBuilder
&builder,
/// to keep all the lower bound and explicit parameter information.
fir::BoxValue createBoxValue(fir::FirOpBuilder &b
[llvm-branch-commits] [llvm] a3cab1f - [X86][MC] Support encoding/decoding for PUSHP/POPP (#73092)
Author: Shengchen Kan
Date: 2023-11-23T16:17:17+08:00
New Revision: a3cab1fa17ebf29b01fcb566648e2f3fb2955993
URL:
https://github.com/llvm/llvm-project/commit/a3cab1fa17ebf29b01fcb566648e2f3fb2955993
DIFF:
https://github.com/llvm/llvm-project/commit/a3cab1fa17ebf29b01fcb566648e2f3fb2955993.diff
LOG: [X86][MC] Support encoding/decoding for PUSHP/POPP (#73092)
A PUSH and its corresponding POP may be marked with a 1-bit Push-Pop
Acceleration (PPX)
hint to indicate that the POP reads the value written by the PUSH from the
stack. The PPX hint
is encoded by setting REX2.W = 1 and is applicable only to PUSH with opcode
0x50+rd and POP
with opcode 0x58+rd in the legacy space. It is not applicable to any other
variants of PUSH and POP.
Added:
llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt
llvm/test/MC/X86/apx/pushp-popp-att.s
llvm/test/MC/X86/apx/pushp-popp-intel.s
Modified:
llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/lib/Target/X86/X86InstrMisc.td
Removed:
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 3e42499fe6be340..d5218d356a5dec8 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -1257,9 +1257,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask &= ~ATTR_ADSIZE;
}
- // Absolute jump need special handling
+ // Absolute jump and pushp/popp need special handling
if (insn->rex2ExtensionPrefix[0] == 0xd5 && insn->opcodeType == ONEBYTE &&
- insn->opcode == 0xA1)
+ (insn->opcode == 0xA1 || (insn->opcode & 0xf0) == 0x50))
attrMask |= ATTR_REX2;
if (insn->mode == MODE_16BIT) {
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td
b/llvm/lib/Target/X86/X86InstrMisc.td
index 88e7a388713f80e..9812386f594a29b 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -161,6 +161,8 @@ let isCodeGenOnly = 1, ForceDisassemble = 1 in {
def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>,
OpSize32, Requires<[In64BitMode]>;
} // isCodeGenOnly = 1, ForceDisassemble = 1
+def POPP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "popp\t$reg", []>,
+ REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
} // mayLoad, SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in
def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>,
@@ -173,6 +175,8 @@ let isCodeGenOnly = 1, ForceDisassemble = 1 in {
def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>,
OpSize32, Requires<[In64BitMode]>;
} // isCodeGenOnly = 1, ForceDisassemble = 1
+def PUSHP64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "pushp\t$reg", []>,
+ REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
} // mayStore, SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>,
diff --git a/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt
b/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt
new file mode 100644
index 000..4ec534fc9dcf6ec
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s |
FileCheck %s --check-prefix=INTEL
+
+# ATT: pushp %rax
+# INTEL: pushp rax
+0xd5,0x08,0x50
+
+# ATT: pushp %rbx
+# INTEL: pushp rbx
+0xd5,0x08,0x53
+
+# ATT: pushp %r15
+# INTEL: pushp r15
+0xd5,0x09,0x57
+
+# ATT: pushp %r16
+# INTEL: pushp r16
+0xd5,0x18,0x50
+
+# ATT: popp %rax
+# INTEL: popp rax
+0xd5,0x08,0x58
+
+# ATT: popp %rbx
+# INTEL: popp rbx
+0xd5,0x08,0x5b
+
+# ATT: popp %r15
+# INTEL: popp r15
+0xd5,0x09,0x5f
+
+# ATT: popp %r16
+# INTEL: popp r16
+0xd5,0x18,0x58
diff --git a/llvm/test/MC/X86/apx/pushp-popp-att.s
b/llvm/test/MC/X86/apx/pushp-popp-att.s
new file mode 100644
index 000..a8107448bb088f8
--- /dev/null
+++ b/llvm/test/MC/X86/apx/pushp-popp-att.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s
--check-prefix=ERROR
+
+# ERROR-COUNT-8: error:
+# ERROR-NOT: error:
+
+# CHECK: pushp %rax
+# CHECK: encoding: [0xd5,0x08,0x50]
+ pushp %rax
+# CHECK: pushp %rbx
+# CHECK: encoding: [0xd5,0x08,0x53]
+ pushp %rbx
+# CHECK: pushp %r15
+# CHECK: encoding: [0xd5,0x09,0x57]
+ pushp %r15
+# CHECK: pushp %r16
+# CHECK: encoding: [0xd5,0x18,0x50]
+ pushp %r16
+
+# CHECK: popp %rax
+# CHECK: encoding: [0xd5,0x08,0x58]
+ popp %rax
+# CHECK: popp %rbx
+# CHECK: encoding: [0xd5,0x08,0x5b]
+
[llvm-branch-commits] [llvm] 147c5d6 - [AArch64] Allow LDR merge with same destination register by renaming (#71908)
Author: Zhaoxuan Jiang
Date: 2023-11-23T08:21:27Z
New Revision: 147c5d6686b935ecd93f8fa0e2dcf38deb593890
URL:
https://github.com/llvm/llvm-project/commit/147c5d6686b935ecd93f8fa0e2dcf38deb593890
DIFF:
https://github.com/llvm/llvm-project/commit/147c5d6686b935ecd93f8fa0e2dcf38deb593890.diff
LOG: [AArch64] Allow LDR merge with same destination register by renaming
(#71908)
The patch is based on a reverted patch:
https://reviews.llvm.org/D103597. It was trying to rename registers
before alias check, which is not safe and causes miscompiles. This patch
does 2 things:
1. Do the renaming with necessary checks passed, including alias check.
2. Rename the register for the instructions between the pairs and
combine the second load into the first. By doing so we can just check
the renamability between the pairs and avoid scanning unknown amount of
instructions before/after the pairs.
Necessary refactoring has been made in order to reuse as much code
possible with STR renaming.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
llvm/test/CodeGen/AArch64/fexplog.ll
llvm/test/CodeGen/AArch64/fpow.ll
llvm/test/CodeGen/AArch64/frem.ll
llvm/test/CodeGen/AArch64/fsincos.ll
llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
llvm/test/CodeGen/AArch64/neon-dotreduce.ll
llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
llvm/test/CodeGen/AArch64/vecreduce-add.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 7add127e21e3e55..a03a7f8737be0ed 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -874,7 +874,7 @@
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
bool MergeForward = Flags.getMergeForward();
std::optional RenameReg = Flags.getRenameReg();
- if (MergeForward && RenameReg) {
+ if (RenameReg) {
MCRegister RegToRename = getLdStRegOp(*I).getReg();
DefinedInBB.addReg(*RenameReg);
@@ -891,7 +891,8 @@
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
};
std::function UpdateMIs =
-[this, RegToRename, GetMatchingSubReg](MachineInstr &MI, bool IsDef) {
+[this, RegToRename, GetMatchingSubReg, MergeForward](MachineInstr &MI,
+ bool IsDef) {
if (IsDef) {
bool SeenDef = false;
for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); ++OpIdx) {
@@ -899,7 +900,8 @@
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
// Rename the first explicit definition and all implicit
// definitions matching RegToRename.
if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
- (!SeenDef || (MOP.isDef() && MOP.isImplicit())) &&
+ (!MergeForward || !SeenDef ||
+ (MOP.isDef() && MOP.isImplicit())) &&
TRI->regsOverlap(MOP.getReg(), RegToRename)) {
assert((MOP.isImplicit() ||
(MOP.isRenamable() && !MOP.isEarlyClobber())) &&
@@ -926,31 +928,46 @@
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
assert((MOP.isImplicit() ||
(MOP.isRenamable() && !MOP.isEarlyClobber())) &&
"Need renamable operands");
-const TargetRegisterClass *RC =
-MI.getRegClassConstraint(OpIdx, TII, TRI);
-if (!RC)
- continue;
-MOP.setReg(GetMatchingSubReg(RC));
+Register MatchingReg;
+if (const TargetRegisterClass *RC =
+MI.getRegClassConstraint(OpIdx, TII, TRI))
+ MatchingReg = GetMatchingSubReg(RC);
+else
+ MatchingReg = GetMatchingSubReg(
+ TRI->getMinimalPhysRegClass(MOP.getReg()));
+assert(MatchingReg != AArch64::NoRegister &&
+ "Cannot find matching regs for renaming");
+MOP.setReg(MatchingReg);
}
}
}
LLVM_DEBUG(dbgs() << "Renamed " << MI << "\n");
return true;
};
-forAllMIsUntilDef(*I, RegToRename, TRI, LdStLimit, UpdateMIs);
+forAllMIsUntilDef(MergeForward ? *I : *std::prev(Paired), RegToRename, TRI,
+ LdStLimit, UpdateMIs);
#if !defined(NDEBUG)
-// Make sure the register used for renaming is not used between the paired
-// instructions. That would trash the content before the new paired
-// instruction.
+// For forward mergi
[llvm-branch-commits] [mlir] 6367677 - [mlir][linalg] `BufferizeToAllocationOp`: fix side effects (#72986)
Author: Matthias Springer
Date: 2023-11-23T09:22:40+01:00
New Revision: 6367677c9d901f412934b4935c4341dc6d421d36
URL:
https://github.com/llvm/llvm-project/commit/6367677c9d901f412934b4935c4341dc6d421d36
DIFF:
https://github.com/llvm/llvm-project/commit/6367677c9d901f412934b4935c4341dc6d421d36.diff
LOG: [mlir][linalg] `BufferizeToAllocationOp`: fix side effects (#72986)
`bufferize_to_allocation` does not bufferize/replace targeted ops if
`bufferize_destination_only` is set.
Fixes #72931.
Added:
Modified:
mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
Removed:
diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
index de4965f937162ea..ef5d88d46dd28a0 100644
--- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
+++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
@@ -289,7 +289,13 @@ DiagnosedSilenceableFailure
transform::BufferizeToAllocationOp::apply(
void transform::BufferizeToAllocationOp::getEffects(
SmallVectorImpl &effects) {
- consumesHandle(getTarget(), effects);
+ if (getBufferizeDestinationOnly()) {
+// The destination is replaced with a newly allocated buffer, but the op
+// itself remains in place.
+onlyReadsHandle(getTarget(), effects);
+ } else {
+consumesHandle(getTarget(), effects);
+ }
producesHandle(getAllocatedBuffer(), effects);
producesHandle(getNewOps(), effects);
modifiesPayload(effects);
___
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[llvm-branch-commits] [llvm] 93e1568 - [DAG] Fix a miscompile in insert_subvector undef (insert_subvector undef, ..), idx combine (#73587)
Author: Philip Reames
Date: 2023-11-27T16:45:29-08:00
New Revision: 93e156833bfadfbabfa5be2afad4f002c019257f
URL:
https://github.com/llvm/llvm-project/commit/93e156833bfadfbabfa5be2afad4f002c019257f
DIFF:
https://github.com/llvm/llvm-project/commit/93e156833bfadfbabfa5be2afad4f002c019257f.diff
LOG: [DAG] Fix a miscompile in insert_subvector undef (insert_subvector undef,
..), idx combine (#73587)
The combine was implicitly assuming that the index on the outer
insert_subvector meant the same thing when the source was switched to be
the index of the inner insert_subvector. This is not true if the
innermost sub-vector is fixed, and the outer subvector is scalable.
I could do a less restrictive fix here - i.e. allow the case where the
scalability of the subvectors are the same - but there's no test
coverage which shows this transform actually has profit. Given that, go
for the simplest fix.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 41d36e7d16d2e14..2a3425a42607e72 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -26153,10 +26153,11 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N)
{
N1, N2);
// Eliminate an intermediate insert into an undef vector:
- // insert_subvector undef, (insert_subvector undef, X, 0), N2 -->
- // insert_subvector undef, X, N2
+ // insert_subvector undef, (insert_subvector undef, X, 0), 0 -->
+ // insert_subvector undef, X, 0
if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
- N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)))
+ N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)) &&
+ isNullConstant(N2))
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
N1.getOperand(1), N2);
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index 57de8341cb89cef..8a368e7161c3f2a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -505,6 +505,33 @@ define @insert_nxv2i64_nxv3i64(<3 x
i64> %sv) #0 {
ret %vec
}
+; This shows a case where we were miscompiling because the index of the
+; outer expects a scalable inner and the inner most subvector is fixed length.
+; The code generated happens to be correct if VLEN=128, but is wrong if
+; VLEN=256.
+define @insert_insert_combine(<2 x i32> %subvec) {
+; CHECK-LABEL: insert_insert_combine:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vmv1r.v v10, v8
+; CHECK-NEXT:ret
+ %inner = call @llvm.vector.insert.nxv4i32.v2i32( undef, <2 x i32> %subvec, i64 0)
+ %outer = call @llvm.vector.insert.nxv4i32.nxv8i32( undef, %inner, i64 4)
+ ret %outer
+}
+
+; We can combine these two (even with non-zero index on the outer) because
+; the vector must be an even multiple.
+define @insert_insert_combine2( %subvec) {
+; CHECK-LABEL: insert_insert_combine2:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vmv1r.v v10, v8
+; CHECK-NEXT:ret
+ %inner = call @llvm.vector.insert.nxv2i32.nxv4i32( undef, %subvec, i64 0)
+ %outer = call @llvm.vector.insert.nxv4i32.nxv8i32( undef, %inner, i64 4)
+ ret %outer
+}
+
+
attributes #0 = { vscale_range(2,1024) }
declare @llvm.vector.insert.nxv1i1.nxv4i1(,
, i64)
@@ -517,6 +544,9 @@ declare
@llvm.vector.insert.nxv2f16.nxv32f16( @llvm.vector.insert.nxv1i8.nxv4i8(,
, i64 %idx)
+declare @llvm.vector.insert.nxv2i32.nxv4i32(, , i64)
+declare @llvm.vector.insert.nxv4i32.v2i32(, <2 x i32>, i64)
+
declare @llvm.vector.insert.nxv2i32.nxv8i32(, , i64 %idx)
declare @llvm.vector.insert.nxv4i32.nxv8i32(, , i64 %idx)
___
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[llvm-branch-commits] [mlir] 9a7f4bd - [mlir][arith] doc updates for ub semantics, and int representations (#72932)
Author: Jacob Yu
Date: 2023-11-27T19:48:06-05:00
New Revision: 9a7f4bde2489f6529d336998e2c3fe902a1d864a
URL:
https://github.com/llvm/llvm-project/commit/9a7f4bde2489f6529d336998e2c3fe902a1d864a
DIFF:
https://github.com/llvm/llvm-project/commit/9a7f4bde2489f6529d336998e2c3fe902a1d864a.diff
LOG: [mlir][arith] doc updates for ub semantics, and int representations
(#72932)
Following the discussions in this thread,
https://discourse.llvm.org/t/some-question-on-the-semantics-of-the-arith-dialect/74861,
here are some updates to the documented semantics of Arith.
Added are clarifications on poison behaviour, UBs, overflow semantics,
and the underlying two's complement representation used for integers
Co-authored-by: kuhar
Co-authored-by: math-fehr
Added:
Modified:
mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
Removed:
diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
b/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
index 133af893e4efa74..1e4061392b22d48 100644
--- a/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
+++ b/mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
@@ -19,7 +19,12 @@ def Arith_Dialect : Dialect {
The arith dialect is intended to hold basic integer and floating point
mathematical operations. This includes unary, binary, and ternary
arithmetic
ops, bitwise and shift ops, cast ops, and compare ops. Operations in this
-dialect also accept vectors and tensors of integers or floats.
+dialect also accept vectors and tensors of integers or floats. The dialect
+assumes integers are represented by bitvectors with a two's complement
+representation. Unless otherwise stated, the operations within this
dialect
+propagate poison values, i.e., if any of its inputs are poison, then the
+output is poison. Unless otherwise stated, operations applied to `vector`
+and `tensor` values propagates poison elementwise.
}];
let hasConstantMaterializer = 1;
diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
index e382f18340856ff..38cce99679e99dc 100644
--- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
@@ -196,9 +196,9 @@ def Arith_AddIOp : Arith_TotalIntBinaryOp<"addi",
[Commutative]> {
let summary = "integer addition operation";
let description = [{
The `addi` operation takes two operands and returns one result, each of
-these is required to be the same type. This type may be an integer scalar
-type, a vector whose element type is integer, or a tensor of integers. It
-has no standard attributes.
+these is required to be the same type. This type may be an integer scalar
type,
+a vector whose element type is integer, or a tensor of integers. It has no
+standard attributes.
Example:
@@ -273,7 +273,9 @@ def Arith_AddUIExtendedOp : Arith_Op<"addui_extended",
[Pure, Commutative,
//===--===//
def Arith_SubIOp : Arith_TotalIntBinaryOp<"subi"> {
- let summary = "integer subtraction operation";
+ let summary = [{
+Integer subtraction operation.
+ }];
let hasFolder = 1;
let hasCanonicalizer = 1;
}
@@ -283,7 +285,9 @@ def Arith_SubIOp : Arith_TotalIntBinaryOp<"subi"> {
//===--===//
def Arith_MulIOp : Arith_TotalIntBinaryOp<"muli", [Commutative]> {
- let summary = "integer multiplication operation";
+ let summary = [{
+Integer multiplication operation.
+ }];
let hasFolder = 1;
let hasCanonicalizer = 1;
}
@@ -385,8 +389,9 @@ def Arith_DivUIOp : Arith_IntBinaryOp<"divui",
[ConditionallySpeculatable]> {
the most significant, i.e. for `i16` given two's complement representation,
`6 / -2 = 6 / (2^16 - 2) = 0`.
-Note: the semantics of division by zero is TBD; do NOT assume any specific
-behavior.
+Division by zero is undefined behavior. When applied to `vector` and
+`tensor` values, the behavior is undefined if _any_ elements are divided
by
+zero.
Example:
@@ -420,8 +425,10 @@ def Arith_DivSIOp : Arith_IntBinaryOp<"divsi",
[ConditionallySpeculatable]> {
Signed integer division. Rounds towards zero. Treats the leading bit as
sign, i.e. `6 / -2 = -3`.
-Note: the semantics of division by zero or signed division overflow
(minimum
-value divided by -1) is TBD; do NOT assume any specific behavior.
+Divison by zero, or signed division overflow (minimum value divided by -1)
+is undefined behavior. When applied to `vector` and `tensor` values, the
+behavior is undefined if _any_ of its elements are divided by zero or has
a
+signed division overflow.
Example:
@@ -455,10 +462,11 @@ def Arith
[llvm-branch-commits] [mlir] [llvm] [clang-tools-extra] [clang] [libc] [compiler-rt] [flang] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [llvm] [compiler-rt] [libc] [mlir] [flang] [clang] [sanitizer_symbolizer] Add initial symbolizer markup support for linux. (PR #73193)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 22078bd - Revert "[CUDA][HIP] ignore implicit host/device attr for override (#72815)"
Author: Yaxun (Sam) Liu
Date: 2023-11-22T21:04:55-05:00
New Revision: 22078bd9f6842411aac2b75196975d68a817a358
URL:
https://github.com/llvm/llvm-project/commit/22078bd9f6842411aac2b75196975d68a817a358
DIFF:
https://github.com/llvm/llvm-project/commit/22078bd9f6842411aac2b75196975d68a817a358.diff
LOG: Revert "[CUDA][HIP] ignore implicit host/device attr for override (#72815)"
This reverts commit a1e2c6566305061c115954b048f2957c8d55cb5b.
Revert this patch due to regression. A testcase is:
`template
class C {
explicit C() {};
};
template <> C::C() {};
`
Added:
Modified:
clang/lib/Sema/SemaOverload.cpp
clang/test/SemaCUDA/implicit-member-target-inherited.cu
clang/test/SemaCUDA/trivial-ctor-dtor.cu
Removed:
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 64607e28b8b35e6..9800d7f1c9cfee9 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -1491,10 +1491,8 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef,
FunctionDecl *New,
// Don't allow overloading of destructors. (In theory we could, but it
// would be a giant change to clang.)
if (!isa(New)) {
- Sema::CUDAFunctionTarget NewTarget = SemaRef.IdentifyCUDATarget(
- New, isa(New)),
- OldTarget = SemaRef.IdentifyCUDATarget(
- Old, isa(New));
+ Sema::CUDAFunctionTarget NewTarget = SemaRef.IdentifyCUDATarget(New),
+ OldTarget = SemaRef.IdentifyCUDATarget(Old);
if (NewTarget != Sema::CFT_InvalidTarget) {
assert((OldTarget != Sema::CFT_InvalidTarget) &&
"Unexpected invalid target.");
diff --git a/clang/test/SemaCUDA/implicit-member-target-inherited.cu
b/clang/test/SemaCUDA/implicit-member-target-inherited.cu
index ceca0891fc9b03c..781199bba6b5a11 100644
--- a/clang/test/SemaCUDA/implicit-member-target-inherited.cu
+++ b/clang/test/SemaCUDA/implicit-member-target-inherited.cu
@@ -39,7 +39,6 @@ struct A2_with_device_ctor {
};
// expected-note@-3 {{candidate constructor (the implicit copy constructor)
not viable}}
// expected-note@-4 {{candidate constructor (the implicit move constructor)
not viable}}
-// expected-note@-4 {{candidate inherited constructor not viable: call to
__device__ function from __host__ function}}
struct B2_with_implicit_default_ctor : A2_with_device_ctor {
using A2_with_device_ctor::A2_with_device_ctor;
diff --git a/clang/test/SemaCUDA/trivial-ctor-dtor.cu
b/clang/test/SemaCUDA/trivial-ctor-dtor.cu
index 21d698d28492ac3..1df8adc62bab590 100644
--- a/clang/test/SemaCUDA/trivial-ctor-dtor.cu
+++ b/clang/test/SemaCUDA/trivial-ctor-dtor.cu
@@ -38,19 +38,3 @@ struct TC : TB {
};
__device__ TC tc; //expected-error {{dynamic initialization is not
supported for __device__, __constant__, __shared__, and __managed__ variables}}
-
-// Check trivial ctor specialization
-template
-struct C { //expected-note {{candidate constructor (the implicit copy
constructor) not viable}}
- //expected-note@-1 {{candidate constructor (the implicit move
constructor) not viable}}
-explicit C() {};
-};
-
-template <> C::C() {};
-__device__ C ci_d;
-C ci_h;
-
-// Check non-trivial ctor specialization
-template <> C::C() { static int nontrivial_ctor = 1; } //expected-note
{{candidate constructor not viable: call to __host__ function from __device__
function}}
-__device__ C cf_d; //expected-error {{no matching constructor for
initialization of 'C'}}
-C cf_h;
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[llvm-branch-commits] [compiler-rt] 0e5da2e - [compiler-rt] Fix the HWCAP2_EBF16 and HWCAP2_SVE_EBF16 macro value (#70905)
Author: joyhou-hw
Date: 2023-11-23T10:17:55+08:00
New Revision: 0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc
URL:
https://github.com/llvm/llvm-project/commit/0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc
DIFF:
https://github.com/llvm/llvm-project/commit/0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc.diff
LOG: [compiler-rt] Fix the HWCAP2_EBF16 and HWCAP2_SVE_EBF16 macro value
(#70905)
HWCAP2_EBF16 (1UL << 32)
HWCAP2_SVE_EBF16 (1UL << 33)
this will overflow in aarch64 ilp32 abi, and make func
__init_cpu_features_constructor() wrong.
Added:
Modified:
compiler-rt/lib/builtins/cpu_model.c
Removed:
diff --git a/compiler-rt/lib/builtins/cpu_model.c
b/compiler-rt/lib/builtins/cpu_model.c
index aefa56abcdd9535..b0ec5e51e96d491 100644
--- a/compiler-rt/lib/builtins/cpu_model.c
+++ b/compiler-rt/lib/builtins/cpu_model.c
@@ -1137,10 +1137,10 @@ typedef struct __ifunc_arg_t {
#define HWCAP2_WFXT (1UL << 31)
#endif
#ifndef HWCAP2_EBF16
-#define HWCAP2_EBF16 (1UL << 32)
+#define HWCAP2_EBF16 (1ULL << 32)
#endif
#ifndef HWCAP2_SVE_EBF16
-#define HWCAP2_SVE_EBF16 (1UL << 33)
+#define HWCAP2_SVE_EBF16 (1ULL << 33)
#endif
// Detect Exynos 9810 CPU
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[llvm-branch-commits] [clang] 6b3470b - Revert "[CUDA][HIP] make trivial ctor/dtor host device (#72394)"
Author: Yaxun (Sam) Liu
Date: 2023-11-22T21:20:53-05:00
New Revision: 6b3470b4b83195aeeda60b101e8d3bf8800c321c
URL:
https://github.com/llvm/llvm-project/commit/6b3470b4b83195aeeda60b101e8d3bf8800c321c
DIFF:
https://github.com/llvm/llvm-project/commit/6b3470b4b83195aeeda60b101e8d3bf8800c321c.diff
LOG: Revert "[CUDA][HIP] make trivial ctor/dtor host device (#72394)"
This reverts commit 27e6e4a4d0e3296cebad8db577ec0469a286795e.
This patch is reverted due to regression. A testcase is:
`template
struct ptr {
~ptr() { static int x = 1;}
};
template
struct Abc : ptr {
public:
Abc();
~Abc() {}
};
template
class Abc;
`
Added:
Modified:
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaCUDA.cpp
clang/lib/Sema/SemaDecl.cpp
clang/test/SemaCUDA/call-host-fn-from-device.cu
clang/test/SemaCUDA/default-ctor.cu
clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
clang/test/SemaCUDA/implicit-member-target-collision.cu
clang/test/SemaCUDA/implicit-member-target-inherited.cu
clang/test/SemaCUDA/implicit-member-target.cu
Removed:
clang/test/SemaCUDA/trivial-ctor-dtor.cu
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 59806bcbcbb2dbc..e8914f5fcddf19e 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13466,10 +13466,6 @@ class Sema final {
void maybeAddCUDAHostDeviceAttrs(FunctionDecl *FD,
const LookupResult &Previous);
- /// May add implicit CUDAHostAttr and CUDADeviceAttr attributes to a
- /// trivial cotr/dtor that does not have host and device attributes.
- void maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FunctionDecl *FD);
-
/// May add implicit CUDAConstantAttr attribute to VD, depending on VD
/// and current compilation settings.
void MaybeAddCUDAConstantAttr(VarDecl *VD);
diff --git a/clang/lib/Sema/SemaCUDA.cpp b/clang/lib/Sema/SemaCUDA.cpp
index b94f448dabe7517..318174f7be8fa95 100644
--- a/clang/lib/Sema/SemaCUDA.cpp
+++ b/clang/lib/Sema/SemaCUDA.cpp
@@ -772,22 +772,6 @@ void Sema::maybeAddCUDAHostDeviceAttrs(FunctionDecl *NewD,
NewD->addAttr(CUDADeviceAttr::CreateImplicit(Context));
}
-// If a trivial ctor/dtor has no host/device
-// attributes, make it implicitly host device function.
-void Sema::maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FunctionDecl *FD) {
- bool IsTrivialCtor = false;
- if (auto *CD = dyn_cast(FD))
-IsTrivialCtor = isEmptyCudaConstructor(SourceLocation(), CD);
- bool IsTrivialDtor = false;
- if (auto *DD = dyn_cast(FD))
-IsTrivialDtor = isEmptyCudaDestructor(SourceLocation(), DD);
- if ((IsTrivialCtor || IsTrivialDtor) && !FD->hasAttr() &&
- !FD->hasAttr()) {
-FD->addAttr(CUDAHostAttr::CreateImplicit(Context));
-FD->addAttr(CUDADeviceAttr::CreateImplicit(Context));
- }
-}
-
// TODO: `__constant__` memory may be a limited resource for certain targets.
// A safeguard may be needed at the end of compilation pipeline if
// `__constant__` memory usage goes beyond limit.
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 4e1857b931cc868..23dd8ae15c16583 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -16255,9 +16255,6 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt
*Body,
if (FD && !FD->isDeleted())
checkTypeSupport(FD->getType(), FD->getLocation(), FD);
- if (LangOpts.CUDA)
-maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FD);
-
return dcl;
}
diff --git a/clang/test/SemaCUDA/call-host-fn-from-device.cu
b/clang/test/SemaCUDA/call-host-fn-from-device.cu
index b62de92db02d6de..acdd291b664579b 100644
--- a/clang/test/SemaCUDA/call-host-fn-from-device.cu
+++ b/clang/test/SemaCUDA/call-host-fn-from-device.cu
@@ -12,7 +12,7 @@ extern "C" void host_fn() {}
struct Dummy {};
struct S {
- S() { static int nontrivial_ctor = 1; }
+ S() {}
// expected-note@-1 2 {{'S' declared here}}
~S() { host_fn(); }
// expected-note@-1 {{'~S' declared here}}
diff --git a/clang/test/SemaCUDA/default-ctor.cu
b/clang/test/SemaCUDA/default-ctor.cu
index 31971fe6b3863c7..cbad7a1774c1501 100644
--- a/clang/test/SemaCUDA/default-ctor.cu
+++ b/clang/test/SemaCUDA/default-ctor.cu
@@ -25,7 +25,7 @@ __device__ void fd() {
InD ind;
InH inh; // expected-error{{no matching constructor for initialization of
'InH'}}
InHD inhd;
- Out out;
+ Out out; // expected-error{{no matching constructor for initialization of
'Out'}}
OutD outd;
OutH outh; // expected-error{{no matching constructor for initialization of
'OutH'}}
OutHD outhd;
diff --git a/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
b/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
index edb543f637ccc18..06015ed0d6d8edc 100644
--- a/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
+++ b/clang/
[llvm-branch-commits] [llvm] [clang-tools-extra] [clang] [libc] [compiler-rt] [flang] [sanitizer_symbolizer] RenderContextual elements for symbolizer markup. (PR #73194)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 22078bd - Revert "[CUDA][HIP] ignore implicit host/device attr for override (#72815)"
Author: Yaxun (Sam) Liu
Date: 2023-11-22T21:04:55-05:00
New Revision: 22078bd9f6842411aac2b75196975d68a817a358
URL:
https://github.com/llvm/llvm-project/commit/22078bd9f6842411aac2b75196975d68a817a358
DIFF:
https://github.com/llvm/llvm-project/commit/22078bd9f6842411aac2b75196975d68a817a358.diff
LOG: Revert "[CUDA][HIP] ignore implicit host/device attr for override (#72815)"
This reverts commit a1e2c6566305061c115954b048f2957c8d55cb5b.
Revert this patch due to regression. A testcase is:
`template
class C {
explicit C() {};
};
template <> C::C() {};
`
Added:
Modified:
clang/lib/Sema/SemaOverload.cpp
clang/test/SemaCUDA/implicit-member-target-inherited.cu
clang/test/SemaCUDA/trivial-ctor-dtor.cu
Removed:
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 64607e28b8b35e6..9800d7f1c9cfee9 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -1491,10 +1491,8 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef,
FunctionDecl *New,
// Don't allow overloading of destructors. (In theory we could, but it
// would be a giant change to clang.)
if (!isa(New)) {
- Sema::CUDAFunctionTarget NewTarget = SemaRef.IdentifyCUDATarget(
- New, isa(New)),
- OldTarget = SemaRef.IdentifyCUDATarget(
- Old, isa(New));
+ Sema::CUDAFunctionTarget NewTarget = SemaRef.IdentifyCUDATarget(New),
+ OldTarget = SemaRef.IdentifyCUDATarget(Old);
if (NewTarget != Sema::CFT_InvalidTarget) {
assert((OldTarget != Sema::CFT_InvalidTarget) &&
"Unexpected invalid target.");
diff --git a/clang/test/SemaCUDA/implicit-member-target-inherited.cu
b/clang/test/SemaCUDA/implicit-member-target-inherited.cu
index ceca0891fc9b03c..781199bba6b5a11 100644
--- a/clang/test/SemaCUDA/implicit-member-target-inherited.cu
+++ b/clang/test/SemaCUDA/implicit-member-target-inherited.cu
@@ -39,7 +39,6 @@ struct A2_with_device_ctor {
};
// expected-note@-3 {{candidate constructor (the implicit copy constructor)
not viable}}
// expected-note@-4 {{candidate constructor (the implicit move constructor)
not viable}}
-// expected-note@-4 {{candidate inherited constructor not viable: call to
__device__ function from __host__ function}}
struct B2_with_implicit_default_ctor : A2_with_device_ctor {
using A2_with_device_ctor::A2_with_device_ctor;
diff --git a/clang/test/SemaCUDA/trivial-ctor-dtor.cu
b/clang/test/SemaCUDA/trivial-ctor-dtor.cu
index 21d698d28492ac3..1df8adc62bab590 100644
--- a/clang/test/SemaCUDA/trivial-ctor-dtor.cu
+++ b/clang/test/SemaCUDA/trivial-ctor-dtor.cu
@@ -38,19 +38,3 @@ struct TC : TB {
};
__device__ TC tc; //expected-error {{dynamic initialization is not
supported for __device__, __constant__, __shared__, and __managed__ variables}}
-
-// Check trivial ctor specialization
-template
-struct C { //expected-note {{candidate constructor (the implicit copy
constructor) not viable}}
- //expected-note@-1 {{candidate constructor (the implicit move
constructor) not viable}}
-explicit C() {};
-};
-
-template <> C::C() {};
-__device__ C ci_d;
-C ci_h;
-
-// Check non-trivial ctor specialization
-template <> C::C() { static int nontrivial_ctor = 1; } //expected-note
{{candidate constructor not viable: call to __host__ function from __device__
function}}
-__device__ C cf_d; //expected-error {{no matching constructor for
initialization of 'C'}}
-C cf_h;
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[llvm-branch-commits] [clang] b16f765 - [LinkerWrapper] Accept some needed lld-link linker arguments for COFF targets (#72889)
Author: Joseph Huber
Date: 2023-11-22T20:23:23-06:00
New Revision: b16f765d6fec56a07aecd2056bb1760a9e72d64f
URL:
https://github.com/llvm/llvm-project/commit/b16f765d6fec56a07aecd2056bb1760a9e72d64f
DIFF:
https://github.com/llvm/llvm-project/commit/b16f765d6fec56a07aecd2056bb1760a9e72d64f.diff
LOG: [LinkerWrapper] Accept some needed lld-link linker arguments for COFF
targets (#72889)
Summary:
The linker wrapper is a utility used to create offloading programs from
single-source offloading languages such as OpenMP or CUDA. This is done
by embedding device code into the host object, then feeding it into the
linker wrapper which extracts the accelerator object files, links them,
then wraps them in registration code for the target runtime. This
previously has only worked in Linux / ELF platforms.
This patch attempts to hand Windows / COFF inputs by also accepting COFF
forms of certain linker arguments we use internally. The important
arguments are library search paths, so we can identify libraries which
may contain device code, libraries themselves, and the output name used
for intermediate output.
I am not intimately familiar with the semantics here for the semantics
in how a `lib` file is earched. I am simply treating `foo.lib` as the
GNU equivalent `-l:foo.lib` in the search logic. Similarly, I am
assuming that static libraries will be llvm-ar style libraries. I will
need to investigate the actual deficiencies later, but this should be a
good starting point along with
https://github.com/llvm/llvm-project/pull/72697
Added:
Modified:
clang/test/Driver/linker-wrapper.c
clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
Removed:
diff --git a/clang/test/Driver/linker-wrapper.c
b/clang/test/Driver/linker-wrapper.c
index da7bdc22153ceae..e82febd61823102 100644
--- a/clang/test/Driver/linker-wrapper.c
+++ b/clang/test/Driver/linker-wrapper.c
@@ -140,3 +140,11 @@
// RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s
--check-prefix=CLANG-BACKEND
// CLANG-BACKEND: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa
-mcpu=gfx908 -O2 -Wl,--no-undefined {{.*}}.bc
+
+// RUN: clang-offload-packager -o %t.out \
+// RUN:
--image=file=%t.elf.o,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70
+// RUN: %clang -cc1 %s -triple x86_64-unknown-windows-msvc -emit-obj -o %t.o
-fembed-offload-object=%t.out
+// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-windows-msvc
--dry-run \
+// RUN: --linker-path=/usr/bin/lld-link -- %t.o -libpath:./ -out:a.exe 2>&1
| FileCheck %s --check-prefix=COFF
+
+// COFF: "/usr/bin/lld-link" {{.*}}.o -libpath:./ -out:a.exe
{{.*}}openmp.image.wrapper{{.*}}
diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
index bafe8ace60d1cea..db0ce3e2a190192 100644
--- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
@@ -254,7 +254,7 @@ Error runLinker(ArrayRef Files, const ArgList
&Args) {
continue;
Arg->render(Args, NewLinkerArgs);
-if (Arg->getOption().matches(OPT_o))
+if (Arg->getOption().matches(OPT_o) || Arg->getOption().matches(OPT_out))
llvm::transform(Files, std::back_inserter(NewLinkerArgs),
[&](StringRef Arg) { return Args.MakeArgString(Arg); });
}
@@ -1188,7 +1188,7 @@ searchLibraryBaseName(StringRef Name, StringRef Root,
/// `-lfoo` or `-l:libfoo.a`.
std::optional searchLibrary(StringRef Input, StringRef Root,
ArrayRef SearchPaths) {
- if (Input.startswith(":"))
+ if (Input.startswith(":") || Input.ends_with(".lib"))
return findFromSearchPaths(Input.drop_front(), Root, SearchPaths);
return searchLibraryBaseName(Input, Root, SearchPaths);
}
@@ -1339,7 +1339,7 @@ Expected> getDeviceInput(const
ArgList &Args) {
StringRef Root = Args.getLastArgValue(OPT_sysroot_EQ);
SmallVector LibraryPaths;
- for (const opt::Arg *Arg : Args.filtered(OPT_library_path))
+ for (const opt::Arg *Arg : Args.filtered(OPT_library_path, OPT_libpath))
LibraryPaths.push_back(Arg->getValue());
BumpPtrAllocator Alloc;
@@ -1348,7 +1348,7 @@ Expected> getDeviceInput(const
ArgList &Args) {
// Try to extract device code from the linker input files.
SmallVector InputFiles;
DenseMap> Syms;
- bool WholeArchive = false;
+ bool WholeArchive = Args.hasArg(OPT_wholearchive_flag) ? true : false;
for (const opt::Arg *Arg : Args.filtered(
OPT_INPUT, OPT_library, OPT_whole_archive, OPT_no_whole_archive)) {
if (Arg->getOption().matches(OPT_whole_archive) ||
@@ -1474,9 +1474,17 @@ int main(int Argc, char **Argv) {
Verbose = Args.hasArg(OPT_verbose);
DryRun = Args.hasArg(OPT_dry_run);
SaveTemps = Args.hasArg(OPT_save_te
[llvm-branch-commits] [clang] [clang-tools-extra] [llvm] [libc] [compiler-rt] [flang] [sanitizer_symbolizer] RenderContextual elements for symbolizer markup. (PR #73194)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 52b413f - [RISCV] Precommit tests for buildvector lowering with exact VLEN
Author: Philip Reames
Date: 2023-11-27T16:48:20-08:00
New Revision: 52b413f25ae79b07df88c0224adec4a6d7dabecc
URL:
https://github.com/llvm/llvm-project/commit/52b413f25ae79b07df88c0224adec4a6d7dabecc
DIFF:
https://github.com/llvm/llvm-project/commit/52b413f25ae79b07df88c0224adec4a6d7dabecc.diff
LOG: [RISCV] Precommit tests for buildvector lowering with exact VLEN
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 05aa5f9807b9fc4..31ed3083e05a114 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -1077,13 +1077,252 @@ define <32 x double> @buildvec_v32f64(double %e0,
double %e1, double %e2, double
ret <32 x double> %v31
}
+define <32 x double> @buildvec_v32f64_exact_vlen(double %e0, double %e1,
double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double
%e8, double %e9, double %e10, double %e11, double %e12, double %e13, double
%e14, double %e15, double %e16, double %e17, double %e18, double %e19, double
%e20, double %e21, double %e22, double %e23, double %e24, double %e25, double
%e26, double %e27, double %e28, double %e29, double %e30, double %e31)
vscale_range(2,2) {
+; RV32-LABEL: buildvec_v32f64_exact_vlen:
+; RV32: # %bb.0:
+; RV32-NEXT:addi sp, sp, -512
+; RV32-NEXT:.cfi_def_cfa_offset 512
+; RV32-NEXT:sw ra, 508(sp) # 4-byte Folded Spill
+; RV32-NEXT:sw s0, 504(sp) # 4-byte Folded Spill
+; RV32-NEXT:fsd fs0, 496(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs1, 488(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs2, 480(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs3, 472(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs4, 464(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs5, 456(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs6, 448(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs7, 440(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs8, 432(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs9, 424(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs10, 416(sp) # 8-byte Folded Spill
+; RV32-NEXT:fsd fs11, 408(sp) # 8-byte Folded Spill
+; RV32-NEXT:.cfi_offset ra, -4
+; RV32-NEXT:.cfi_offset s0, -8
+; RV32-NEXT:.cfi_offset fs0, -16
+; RV32-NEXT:.cfi_offset fs1, -24
+; RV32-NEXT:.cfi_offset fs2, -32
+; RV32-NEXT:.cfi_offset fs3, -40
+; RV32-NEXT:.cfi_offset fs4, -48
+; RV32-NEXT:.cfi_offset fs5, -56
+; RV32-NEXT:.cfi_offset fs6, -64
+; RV32-NEXT:.cfi_offset fs7, -72
+; RV32-NEXT:.cfi_offset fs8, -80
+; RV32-NEXT:.cfi_offset fs9, -88
+; RV32-NEXT:.cfi_offset fs10, -96
+; RV32-NEXT:.cfi_offset fs11, -104
+; RV32-NEXT:addi s0, sp, 512
+; RV32-NEXT:.cfi_def_cfa s0, 0
+; RV32-NEXT:andi sp, sp, -128
+; RV32-NEXT:sw a0, 120(sp)
+; RV32-NEXT:sw a1, 124(sp)
+; RV32-NEXT:fld ft0, 120(sp)
+; RV32-NEXT:sw a2, 120(sp)
+; RV32-NEXT:sw a3, 124(sp)
+; RV32-NEXT:fld ft1, 120(sp)
+; RV32-NEXT:sw a4, 120(sp)
+; RV32-NEXT:sw a5, 124(sp)
+; RV32-NEXT:fld ft2, 120(sp)
+; RV32-NEXT:sw a6, 120(sp)
+; RV32-NEXT:sw a7, 124(sp)
+; RV32-NEXT:fld ft3, 120(sp)
+; RV32-NEXT:fld ft4, 0(s0)
+; RV32-NEXT:fld ft5, 8(s0)
+; RV32-NEXT:fld ft6, 16(s0)
+; RV32-NEXT:fld ft7, 24(s0)
+; RV32-NEXT:fld ft8, 32(s0)
+; RV32-NEXT:fld ft9, 40(s0)
+; RV32-NEXT:fld ft10, 48(s0)
+; RV32-NEXT:fld ft11, 56(s0)
+; RV32-NEXT:fld fs0, 64(s0)
+; RV32-NEXT:fld fs1, 72(s0)
+; RV32-NEXT:fld fs2, 80(s0)
+; RV32-NEXT:fld fs3, 88(s0)
+; RV32-NEXT:fld fs4, 96(s0)
+; RV32-NEXT:fld fs5, 104(s0)
+; RV32-NEXT:fld fs6, 112(s0)
+; RV32-NEXT:fld fs7, 120(s0)
+; RV32-NEXT:fld fs8, 152(s0)
+; RV32-NEXT:fld fs9, 144(s0)
+; RV32-NEXT:fld fs10, 136(s0)
+; RV32-NEXT:fld fs11, 128(s0)
+; RV32-NEXT:fsd fs8, 248(sp)
+; RV32-NEXT:fsd fs9, 240(sp)
+; RV32-NEXT:fsd fs10, 232(sp)
+; RV32-NEXT:fsd fs11, 224(sp)
+; RV32-NEXT:fsd fs7, 216(sp)
+; RV32-NEXT:fsd fs6, 208(sp)
+; RV32-NEXT:fsd fs5, 200(sp)
+; RV32-NEXT:fsd fs4, 192(sp)
+; RV32-NEXT:fsd fs3, 184(sp)
+; RV32-NEXT:fsd fs2, 176(sp)
+; RV32-NEXT:fsd fs1, 168(sp)
+; RV32-NEXT:fsd fs0, 160(sp)
+; RV32-NEXT:fsd ft11, 152(sp)
+; RV32-NEXT:fsd ft10, 144(sp)
+; RV32-NEXT:fsd ft9, 136(sp)
+; RV32-NEXT:fsd ft8, 128(sp)
+; RV32-NEXT:fsd ft7, 376(sp)
+; RV32-NEXT:fsd ft6, 368(sp)
+; RV32-NEXT:fsd ft5, 360(sp)
+; RV32-NEXT:fsd ft4, 352(sp)
+; RV32-NEXT:fsd fa7, 312(sp)
+; RV32-NEXT:fsd fa6, 304(sp)
+; RV32-NEXT:fsd fa5, 296(sp)
+; RV32-NEXT:fsd fa4, 288(sp)
+; RV32-NEXT:
[llvm-branch-commits] [compiler-rt] 0e5da2e - [compiler-rt] Fix the HWCAP2_EBF16 and HWCAP2_SVE_EBF16 macro value (#70905)
Author: joyhou-hw
Date: 2023-11-23T10:17:55+08:00
New Revision: 0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc
URL:
https://github.com/llvm/llvm-project/commit/0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc
DIFF:
https://github.com/llvm/llvm-project/commit/0e5da2eceb89f1e947e8b9b4aa42804e4ea89acc.diff
LOG: [compiler-rt] Fix the HWCAP2_EBF16 and HWCAP2_SVE_EBF16 macro value
(#70905)
HWCAP2_EBF16 (1UL << 32)
HWCAP2_SVE_EBF16 (1UL << 33)
this will overflow in aarch64 ilp32 abi, and make func
__init_cpu_features_constructor() wrong.
Added:
Modified:
compiler-rt/lib/builtins/cpu_model.c
Removed:
diff --git a/compiler-rt/lib/builtins/cpu_model.c
b/compiler-rt/lib/builtins/cpu_model.c
index aefa56abcdd9535..b0ec5e51e96d491 100644
--- a/compiler-rt/lib/builtins/cpu_model.c
+++ b/compiler-rt/lib/builtins/cpu_model.c
@@ -1137,10 +1137,10 @@ typedef struct __ifunc_arg_t {
#define HWCAP2_WFXT (1UL << 31)
#endif
#ifndef HWCAP2_EBF16
-#define HWCAP2_EBF16 (1UL << 32)
+#define HWCAP2_EBF16 (1ULL << 32)
#endif
#ifndef HWCAP2_SVE_EBF16
-#define HWCAP2_SVE_EBF16 (1UL << 33)
+#define HWCAP2_SVE_EBF16 (1ULL << 33)
#endif
// Detect Exynos 9810 CPU
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[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.
Author: Craig Topper
Date: 2023-11-22T18:59:41-08:00
New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c
URL:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c
DIFF:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff
LOG: [X86] Reject fpsr in inline asm constraints other than clobber.
Fixes #73197 and #69201.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a2ab093bb86f9..99866c811eb6faf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57236,7 +57236,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
return std::make_pair(X86::DF, &X86::DFCCRRegClass);
// fpsr -> FPSW
-if (StringRef("{fpsr}").equals_insensitive(Constraint))
+// Only allow for clobber.
+if (StringRef("{fpsr}").equals_insensitive(Constraint) && VT == MVT::Other)
return std::make_pair(X86::FPSW, &X86::FPCCRRegClass);
return Res;
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[llvm-branch-commits] [clang-tools-extra] [llvm] [compiler-rt] [libc] [flang] [clang] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 6b3470b - Revert "[CUDA][HIP] make trivial ctor/dtor host device (#72394)"
Author: Yaxun (Sam) Liu
Date: 2023-11-22T21:20:53-05:00
New Revision: 6b3470b4b83195aeeda60b101e8d3bf8800c321c
URL:
https://github.com/llvm/llvm-project/commit/6b3470b4b83195aeeda60b101e8d3bf8800c321c
DIFF:
https://github.com/llvm/llvm-project/commit/6b3470b4b83195aeeda60b101e8d3bf8800c321c.diff
LOG: Revert "[CUDA][HIP] make trivial ctor/dtor host device (#72394)"
This reverts commit 27e6e4a4d0e3296cebad8db577ec0469a286795e.
This patch is reverted due to regression. A testcase is:
`template
struct ptr {
~ptr() { static int x = 1;}
};
template
struct Abc : ptr {
public:
Abc();
~Abc() {}
};
template
class Abc;
`
Added:
Modified:
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaCUDA.cpp
clang/lib/Sema/SemaDecl.cpp
clang/test/SemaCUDA/call-host-fn-from-device.cu
clang/test/SemaCUDA/default-ctor.cu
clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
clang/test/SemaCUDA/implicit-member-target-collision.cu
clang/test/SemaCUDA/implicit-member-target-inherited.cu
clang/test/SemaCUDA/implicit-member-target.cu
Removed:
clang/test/SemaCUDA/trivial-ctor-dtor.cu
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 59806bcbcbb2dbc..e8914f5fcddf19e 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -13466,10 +13466,6 @@ class Sema final {
void maybeAddCUDAHostDeviceAttrs(FunctionDecl *FD,
const LookupResult &Previous);
- /// May add implicit CUDAHostAttr and CUDADeviceAttr attributes to a
- /// trivial cotr/dtor that does not have host and device attributes.
- void maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FunctionDecl *FD);
-
/// May add implicit CUDAConstantAttr attribute to VD, depending on VD
/// and current compilation settings.
void MaybeAddCUDAConstantAttr(VarDecl *VD);
diff --git a/clang/lib/Sema/SemaCUDA.cpp b/clang/lib/Sema/SemaCUDA.cpp
index b94f448dabe7517..318174f7be8fa95 100644
--- a/clang/lib/Sema/SemaCUDA.cpp
+++ b/clang/lib/Sema/SemaCUDA.cpp
@@ -772,22 +772,6 @@ void Sema::maybeAddCUDAHostDeviceAttrs(FunctionDecl *NewD,
NewD->addAttr(CUDADeviceAttr::CreateImplicit(Context));
}
-// If a trivial ctor/dtor has no host/device
-// attributes, make it implicitly host device function.
-void Sema::maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FunctionDecl *FD) {
- bool IsTrivialCtor = false;
- if (auto *CD = dyn_cast(FD))
-IsTrivialCtor = isEmptyCudaConstructor(SourceLocation(), CD);
- bool IsTrivialDtor = false;
- if (auto *DD = dyn_cast(FD))
-IsTrivialDtor = isEmptyCudaDestructor(SourceLocation(), DD);
- if ((IsTrivialCtor || IsTrivialDtor) && !FD->hasAttr() &&
- !FD->hasAttr()) {
-FD->addAttr(CUDAHostAttr::CreateImplicit(Context));
-FD->addAttr(CUDADeviceAttr::CreateImplicit(Context));
- }
-}
-
// TODO: `__constant__` memory may be a limited resource for certain targets.
// A safeguard may be needed at the end of compilation pipeline if
// `__constant__` memory usage goes beyond limit.
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 4e1857b931cc868..23dd8ae15c16583 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -16255,9 +16255,6 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt
*Body,
if (FD && !FD->isDeleted())
checkTypeSupport(FD->getType(), FD->getLocation(), FD);
- if (LangOpts.CUDA)
-maybeAddCUDAHostDeviceAttrsToTrivialCtorDtor(FD);
-
return dcl;
}
diff --git a/clang/test/SemaCUDA/call-host-fn-from-device.cu
b/clang/test/SemaCUDA/call-host-fn-from-device.cu
index b62de92db02d6de..acdd291b664579b 100644
--- a/clang/test/SemaCUDA/call-host-fn-from-device.cu
+++ b/clang/test/SemaCUDA/call-host-fn-from-device.cu
@@ -12,7 +12,7 @@ extern "C" void host_fn() {}
struct Dummy {};
struct S {
- S() { static int nontrivial_ctor = 1; }
+ S() {}
// expected-note@-1 2 {{'S' declared here}}
~S() { host_fn(); }
// expected-note@-1 {{'~S' declared here}}
diff --git a/clang/test/SemaCUDA/default-ctor.cu
b/clang/test/SemaCUDA/default-ctor.cu
index 31971fe6b3863c7..cbad7a1774c1501 100644
--- a/clang/test/SemaCUDA/default-ctor.cu
+++ b/clang/test/SemaCUDA/default-ctor.cu
@@ -25,7 +25,7 @@ __device__ void fd() {
InD ind;
InH inh; // expected-error{{no matching constructor for initialization of
'InH'}}
InHD inhd;
- Out out;
+ Out out; // expected-error{{no matching constructor for initialization of
'Out'}}
OutD outd;
OutH outh; // expected-error{{no matching constructor for initialization of
'OutH'}}
OutHD outhd;
diff --git a/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
b/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
index edb543f637ccc18..06015ed0d6d8edc 100644
--- a/clang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
+++ b/clang/
[llvm-branch-commits] [clang] 2eb9c64 - [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (#73091)
Author: Jianjian Guan
Date: 2023-11-23T11:08:27+08:00
New Revision: 2eb9c649f0971aaa05404764d74ee7fff15b83ed
URL:
https://github.com/llvm/llvm-project/commit/2eb9c649f0971aaa05404764d74ee7fff15b83ed
DIFF:
https://github.com/llvm/llvm-project/commit/2eb9c649f0971aaa05404764d74ee7fff15b83ed.diff
LOG: [RISCV] Use Float type instead of Half type for Fixed RVV vector type
mangling (#73091)
Added:
Modified:
clang/lib/AST/ItaniumMangle.cpp
clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
Removed:
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 2a62ac0175afb72..b1678479888eb77 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
case BuiltinType::ULong:
TypeNameOS << "uint64";
break;
- case BuiltinType::Half:
+ case BuiltinType::Float16:
TypeNameOS << "float16";
break;
case BuiltinType::Float:
diff --git a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
index 98fb27b704fd81d..32bd49f4ff725db 100644
--- a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
+++ b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
@@ -1,23 +1,23 @@
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-64
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \
+// RUN: -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \
-// RUN: | FileCheck %s --check-prefix=CHECK-128
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \
+// RUN: -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \
-// RUN: | FileCheck %s --check-prefix=CHECK-256
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \
+// RUN: -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \
-// RUN: | FileCheck %s --check-prefix=CHECK-512
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \
+// RUN: -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \
-// RUN: | FileCheck %s --check-prefix=CHECK-1024
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \
+// RUN: -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024
typedef __rvv_int8mf8_t vint8mf8_t;
typedef __rvv_uint8mf8_t vuint8mf8_t;
@@ -26,6 +26,7 @@ typedef __rvv_int8mf4_t vint8mf4_t;
typedef __rvv_uint8mf4_t vuint8mf4_t;
typedef __rvv_int16mf4_t vint16mf4_t;
typedef __rvv_uint16mf4_t vuint16mf4_t;
+typedef __rvv_float16mf4_t vfloat16mf4_t;
typedef __rvv_int8mf2_t vint8mf2_t;
typedef __rvv_uint8mf2_t vuint8mf2_t;
@@ -33,6 +34,7 @@ typedef __rvv_int16mf2_t vint16mf2_t;
typedef __rvv_uint16mf2_t vuint16mf2_t;
typedef __rvv_int32mf2_t vint32mf2_t;
typedef __rvv_uint32mf2_t vuint32mf2_t;
+typedef __rvv_float16mf2_t vfloat16mf2_t;
typedef __rvv_float32mf2_t vfloat32mf2_t;
typedef __rvv_int8m1_t vint8m1_t;
@@ -43,6 +45,7 @@ typedef __rvv_int32m1_t vint32m1_t;
typedef __rvv_uint32m1_t vuint32m1_t;
typedef __rvv_int64m1_t vint64m1_t;
typedef __rvv_uint64m1_t vuint64m1_t;
+typedef __rvv_float16m1_t vfloat16m1_t;
typedef __rvv_float32m1_t vfloat32m1_t;
typedef __rvv_float64m1_t vfloat64m1_t;
@@ -54,6 +57,7 @@ typedef __rvv_int32m2_t vint32m2_t;
typedef __rvv_uint32m2_t vuint32m2_t;
typedef __rvv_int64m2_t vint64m2_t;
typedef __rvv_uint64m2_t vuint64m2_t;
+typedef __rvv_float16m2_t vfloat16m2_t;
typedef __rvv_float32m2_t vfloat32m2_t;
typedef __rvv_float64m2_t vfloat64m2_t;
@@ -65,6 +69,7 @@ typedef __rvv_int32m4_t vint32m4_t;
typedef __r
[llvm-branch-commits] [llvm] [flang] [compiler-rt] [clang-tools-extra] [clang] [libc] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Author: Craig Topper
Date: 2023-11-22T19:49:52-08:00
New Revision: dc683d2e66de79bbea786f51788961eec5d0b793
URL:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793
DIFF:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff
LOG: [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Added:
Modified:
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 008075163b90a8d..f6fe7c9be7e4f46 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -422,7 +422,6 @@ class X86AsmParser : public MCTargetAsmParser {
IES_RPAREN,
IES_REGISTER,
IES_INTEGER,
-IES_IDENTIFIER,
IES_ERROR
};
___
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[llvm-branch-commits] [clang] b16f765 - [LinkerWrapper] Accept some needed lld-link linker arguments for COFF targets (#72889)
Author: Joseph Huber
Date: 2023-11-22T20:23:23-06:00
New Revision: b16f765d6fec56a07aecd2056bb1760a9e72d64f
URL:
https://github.com/llvm/llvm-project/commit/b16f765d6fec56a07aecd2056bb1760a9e72d64f
DIFF:
https://github.com/llvm/llvm-project/commit/b16f765d6fec56a07aecd2056bb1760a9e72d64f.diff
LOG: [LinkerWrapper] Accept some needed lld-link linker arguments for COFF
targets (#72889)
Summary:
The linker wrapper is a utility used to create offloading programs from
single-source offloading languages such as OpenMP or CUDA. This is done
by embedding device code into the host object, then feeding it into the
linker wrapper which extracts the accelerator object files, links them,
then wraps them in registration code for the target runtime. This
previously has only worked in Linux / ELF platforms.
This patch attempts to hand Windows / COFF inputs by also accepting COFF
forms of certain linker arguments we use internally. The important
arguments are library search paths, so we can identify libraries which
may contain device code, libraries themselves, and the output name used
for intermediate output.
I am not intimately familiar with the semantics here for the semantics
in how a `lib` file is earched. I am simply treating `foo.lib` as the
GNU equivalent `-l:foo.lib` in the search logic. Similarly, I am
assuming that static libraries will be llvm-ar style libraries. I will
need to investigate the actual deficiencies later, but this should be a
good starting point along with
https://github.com/llvm/llvm-project/pull/72697
Added:
Modified:
clang/test/Driver/linker-wrapper.c
clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
Removed:
diff --git a/clang/test/Driver/linker-wrapper.c
b/clang/test/Driver/linker-wrapper.c
index da7bdc22153ceae..e82febd61823102 100644
--- a/clang/test/Driver/linker-wrapper.c
+++ b/clang/test/Driver/linker-wrapper.c
@@ -140,3 +140,11 @@
// RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s
--check-prefix=CLANG-BACKEND
// CLANG-BACKEND: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa
-mcpu=gfx908 -O2 -Wl,--no-undefined {{.*}}.bc
+
+// RUN: clang-offload-packager -o %t.out \
+// RUN:
--image=file=%t.elf.o,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70
+// RUN: %clang -cc1 %s -triple x86_64-unknown-windows-msvc -emit-obj -o %t.o
-fembed-offload-object=%t.out
+// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-windows-msvc
--dry-run \
+// RUN: --linker-path=/usr/bin/lld-link -- %t.o -libpath:./ -out:a.exe 2>&1
| FileCheck %s --check-prefix=COFF
+
+// COFF: "/usr/bin/lld-link" {{.*}}.o -libpath:./ -out:a.exe
{{.*}}openmp.image.wrapper{{.*}}
diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
index bafe8ace60d1cea..db0ce3e2a190192 100644
--- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
@@ -254,7 +254,7 @@ Error runLinker(ArrayRef Files, const ArgList
&Args) {
continue;
Arg->render(Args, NewLinkerArgs);
-if (Arg->getOption().matches(OPT_o))
+if (Arg->getOption().matches(OPT_o) || Arg->getOption().matches(OPT_out))
llvm::transform(Files, std::back_inserter(NewLinkerArgs),
[&](StringRef Arg) { return Args.MakeArgString(Arg); });
}
@@ -1188,7 +1188,7 @@ searchLibraryBaseName(StringRef Name, StringRef Root,
/// `-lfoo` or `-l:libfoo.a`.
std::optional searchLibrary(StringRef Input, StringRef Root,
ArrayRef SearchPaths) {
- if (Input.startswith(":"))
+ if (Input.startswith(":") || Input.ends_with(".lib"))
return findFromSearchPaths(Input.drop_front(), Root, SearchPaths);
return searchLibraryBaseName(Input, Root, SearchPaths);
}
@@ -1339,7 +1339,7 @@ Expected> getDeviceInput(const
ArgList &Args) {
StringRef Root = Args.getLastArgValue(OPT_sysroot_EQ);
SmallVector LibraryPaths;
- for (const opt::Arg *Arg : Args.filtered(OPT_library_path))
+ for (const opt::Arg *Arg : Args.filtered(OPT_library_path, OPT_libpath))
LibraryPaths.push_back(Arg->getValue());
BumpPtrAllocator Alloc;
@@ -1348,7 +1348,7 @@ Expected> getDeviceInput(const
ArgList &Args) {
// Try to extract device code from the linker input files.
SmallVector InputFiles;
DenseMap> Syms;
- bool WholeArchive = false;
+ bool WholeArchive = Args.hasArg(OPT_wholearchive_flag) ? true : false;
for (const opt::Arg *Arg : Args.filtered(
OPT_INPUT, OPT_library, OPT_whole_archive, OPT_no_whole_archive)) {
if (Arg->getOption().matches(OPT_whole_archive) ||
@@ -1474,9 +1474,17 @@ int main(int Argc, char **Argv) {
Verbose = Args.hasArg(OPT_verbose);
DryRun = Args.hasArg(OPT_dry_run);
SaveTemps = Args.hasArg(OPT_save_te
[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.
Author: Craig Topper
Date: 2023-11-22T18:59:41-08:00
New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c
URL:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c
DIFF:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff
LOG: [X86] Reject fpsr in inline asm constraints other than clobber.
Fixes #73197 and #69201.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a2ab093bb86f9..99866c811eb6faf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57236,7 +57236,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
return std::make_pair(X86::DF, &X86::DFCCRRegClass);
// fpsr -> FPSW
-if (StringRef("{fpsr}").equals_insensitive(Constraint))
+// Only allow for clobber.
+if (StringRef("{fpsr}").equals_insensitive(Constraint) && VT == MVT::Other)
return std::make_pair(X86::FPSW, &X86::FPCCRRegClass);
return Res;
___
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[llvm-branch-commits] [llvm] 9ab133b - [nfc][InstrProfTest]Parameterize the edge cases of value profile merge by value kind (#73165)
Author: Mingming Liu
Date: 2023-11-22T21:22:20-08:00
New Revision: 9ab133bd9f9cedb880b453dd830b58857fab41ec
URL:
https://github.com/llvm/llvm-project/commit/9ab133bd9f9cedb880b453dd830b58857fab41ec
DIFF:
https://github.com/llvm/llvm-project/commit/9ab133bd9f9cedb880b453dd830b58857fab41ec.diff
LOG: [nfc][InstrProfTest]Parameterize the edge cases of value profile merge by
value kind (#73165)
There are three test cases to test the merge of value profiles.
'get_icall_data_merge1' tests the basic case;
{get_icall_data_merge1_saturation, get_icall_data_merge_site_trunc} tests the
edge case.
This patch parameterizes the edge case test coverage by value kind and adds the
coverage of 'IPVK_MemOPSize'. Keep the basic test structure as it is. The main
reason is test data construction and test assertions is
clearer for each kind in the basic test.
- Using a loop for different value kinds in one test case doesn't work
very well. The instr-prof-writer is stateful (e.g., keeps track of
per-function profile data in a
[container](https://github.com/llvm/llvm-project/blob/a9c149df7666bb2f8755794b97573134e5cfeb38/llvm/include/llvm/ProfileData/InstrProfWriter.h#L43))
Added:
Modified:
llvm/unittests/ProfileData/InstrProfTest.cpp
Removed:
diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp
b/llvm/unittests/ProfileData/InstrProfTest.cpp
index 875e2d06d839367..e6613a90dc7c53e 100644
--- a/llvm/unittests/ProfileData/InstrProfTest.cpp
+++ b/llvm/unittests/ProfileData/InstrProfTest.cpp
@@ -815,7 +815,7 @@ TEST_P(MaybeSparseInstrProfTest, annotate_vp_data) {
ASSERT_EQ(1U, ValueData[3].Count);
}
-TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1) {
+TEST_P(MaybeSparseInstrProfTest, icall_data_merge) {
static const char caller[] = "caller";
NamedInstrProfRecord Record11(caller, 0x1234, {1, 2});
NamedInstrProfRecord Record12(caller, 0x1234, {1, 2});
@@ -920,8 +920,18 @@ TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1) {
ASSERT_EQ(2U, VD_4[2].Count);
}
-TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1_saturation) {
+struct ValueProfileMergeEdgeCaseTest
+: public InstrProfTest,
+ public ::testing::WithParamInterface> {
+ void SetUp() override { Writer.setOutputSparse(std::get<0>(GetParam())); }
+
+ uint32_t getValueProfileKind() const { return std::get<1>(GetParam()); }
+};
+
+TEST_P(ValueProfileMergeEdgeCaseTest, value_profile_data_merge_saturation) {
+ const uint32_t ValueKind = getValueProfileKind();
static const char bar[] = "bar";
+ const uint64_t ProfiledValue = 0x5678;
const uint64_t MaxValCount = std::numeric_limits::max();
const uint64_t MaxEdgeCount = getInstrMaxCountValue();
@@ -944,18 +954,18 @@ TEST_P(MaybeSparseInstrProfTest,
get_icall_data_merge1_saturation) {
ASSERT_EQ(Result, instrprof_error::success);
NamedInstrProfRecord Record4("baz", 0x5678, {3, 4});
- Record4.reserveSites(IPVK_IndirectCallTarget, 1);
- InstrProfValueData VD4[] = {{uint64_t(bar), 1}};
- Record4.addValueData(IPVK_IndirectCallTarget, 0, VD4, 1, nullptr);
+ Record4.reserveSites(ValueKind, 1);
+ InstrProfValueData VD4[] = {{ProfiledValue, 1}};
+ Record4.addValueData(ValueKind, 0, VD4, 1, nullptr);
Result = instrprof_error::success;
Writer.addRecord(std::move(Record4), Err);
ASSERT_EQ(Result, instrprof_error::success);
// Verify value data counter overflow.
NamedInstrProfRecord Record5("baz", 0x5678, {5, 6});
- Record5.reserveSites(IPVK_IndirectCallTarget, 1);
- InstrProfValueData VD5[] = {{uint64_t(bar), MaxValCount}};
- Record5.addValueData(IPVK_IndirectCallTarget, 0, VD5, 1, nullptr);
+ Record5.reserveSites(ValueKind, 1);
+ InstrProfValueData VD5[] = {{ProfiledValue, MaxValCount}};
+ Record5.addValueData(ValueKind, 0, VD5, 1, nullptr);
Result = instrprof_error::success;
Writer.addRecord(std::move(Record5), Err);
ASSERT_EQ(Result, instrprof_error::counter_overflow);
@@ -966,48 +976,48 @@ TEST_P(MaybeSparseInstrProfTest,
get_icall_data_merge1_saturation) {
// Verify saturation of counts.
Expected ReadRecord1 =
Reader->getInstrProfRecord("foo", 0x1234);
- EXPECT_THAT_ERROR(ReadRecord1.takeError(), Succeeded());
- ASSERT_EQ(MaxEdgeCount, ReadRecord1->Counts[0]);
+ ASSERT_THAT_ERROR(ReadRecord1.takeError(), Succeeded());
+ EXPECT_EQ(MaxEdgeCount, ReadRecord1->Counts[0]);
Expected ReadRecord2 =
Reader->getInstrProfRecord("baz", 0x5678);
ASSERT_TRUE(bool(ReadRecord2));
- ASSERT_EQ(1U, ReadRecord2->getNumValueSites(IPVK_IndirectCallTarget));
+ ASSERT_EQ(1U, ReadRecord2->getNumValueSites(ValueKind));
std::unique_ptr VD =
- ReadRecord2->getValueForSite(IPVK_IndirectCallTarget, 0);
- ASSERT_EQ(StringRef("bar"), StringRef((const char *)VD[0].Value, 3));
- ASSERT_EQ(MaxValCount, VD[0].Count);
+ ReadRecord2->getValueForSite(ValueKind, 0);
+ EXPECT_EQ(ProfiledValue, VD[0].Value);
+ EXPECT
[llvm-branch-commits] [clang] 2eb9c64 - [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (#73091)
Author: Jianjian Guan
Date: 2023-11-23T11:08:27+08:00
New Revision: 2eb9c649f0971aaa05404764d74ee7fff15b83ed
URL:
https://github.com/llvm/llvm-project/commit/2eb9c649f0971aaa05404764d74ee7fff15b83ed
DIFF:
https://github.com/llvm/llvm-project/commit/2eb9c649f0971aaa05404764d74ee7fff15b83ed.diff
LOG: [RISCV] Use Float type instead of Half type for Fixed RVV vector type
mangling (#73091)
Added:
Modified:
clang/lib/AST/ItaniumMangle.cpp
clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
Removed:
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 2a62ac0175afb72..b1678479888eb77 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
case BuiltinType::ULong:
TypeNameOS << "uint64";
break;
- case BuiltinType::Half:
+ case BuiltinType::Float16:
TypeNameOS << "float16";
break;
case BuiltinType::Float:
diff --git a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
index 98fb27b704fd81d..32bd49f4ff725db 100644
--- a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
+++ b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
@@ -1,23 +1,23 @@
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-64
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \
+// RUN: -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \
-// RUN: | FileCheck %s --check-prefix=CHECK-128
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \
+// RUN: -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \
-// RUN: | FileCheck %s --check-prefix=CHECK-256
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \
+// RUN: -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \
-// RUN: | FileCheck %s --check-prefix=CHECK-512
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \
+// RUN: -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \
-// RUN: | FileCheck %s --check-prefix=CHECK-1024
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \
+// RUN: -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024
typedef __rvv_int8mf8_t vint8mf8_t;
typedef __rvv_uint8mf8_t vuint8mf8_t;
@@ -26,6 +26,7 @@ typedef __rvv_int8mf4_t vint8mf4_t;
typedef __rvv_uint8mf4_t vuint8mf4_t;
typedef __rvv_int16mf4_t vint16mf4_t;
typedef __rvv_uint16mf4_t vuint16mf4_t;
+typedef __rvv_float16mf4_t vfloat16mf4_t;
typedef __rvv_int8mf2_t vint8mf2_t;
typedef __rvv_uint8mf2_t vuint8mf2_t;
@@ -33,6 +34,7 @@ typedef __rvv_int16mf2_t vint16mf2_t;
typedef __rvv_uint16mf2_t vuint16mf2_t;
typedef __rvv_int32mf2_t vint32mf2_t;
typedef __rvv_uint32mf2_t vuint32mf2_t;
+typedef __rvv_float16mf2_t vfloat16mf2_t;
typedef __rvv_float32mf2_t vfloat32mf2_t;
typedef __rvv_int8m1_t vint8m1_t;
@@ -43,6 +45,7 @@ typedef __rvv_int32m1_t vint32m1_t;
typedef __rvv_uint32m1_t vuint32m1_t;
typedef __rvv_int64m1_t vint64m1_t;
typedef __rvv_uint64m1_t vuint64m1_t;
+typedef __rvv_float16m1_t vfloat16m1_t;
typedef __rvv_float32m1_t vfloat32m1_t;
typedef __rvv_float64m1_t vfloat64m1_t;
@@ -54,6 +57,7 @@ typedef __rvv_int32m2_t vint32m2_t;
typedef __rvv_uint32m2_t vuint32m2_t;
typedef __rvv_int64m2_t vint64m2_t;
typedef __rvv_uint64m2_t vuint64m2_t;
+typedef __rvv_float16m2_t vfloat16m2_t;
typedef __rvv_float32m2_t vfloat32m2_t;
typedef __rvv_float64m2_t vfloat64m2_t;
@@ -65,6 +69,7 @@ typedef __rvv_int32m4_t vint32m4_t;
typedef __r
[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Author: Craig Topper
Date: 2023-11-22T19:49:52-08:00
New Revision: dc683d2e66de79bbea786f51788961eec5d0b793
URL:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793
DIFF:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff
LOG: [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Added:
Modified:
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 008075163b90a8d..f6fe7c9be7e4f46 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -422,7 +422,6 @@ class X86AsmParser : public MCTargetAsmParser {
IES_RPAREN,
IES_REGISTER,
IES_INTEGER,
-IES_IDENTIFIER,
IES_ERROR
};
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[llvm-branch-commits] [clang] 0d2860b - [clang] Avoid memcopy for small structure with padding under -ftrivial-auto-var-init (#71677)
Author: serge-sans-paille
Date: 2023-11-23T05:38:14Z
New Revision: 0d2860b795879f4dd152963b52f969b53b136899
URL:
https://github.com/llvm/llvm-project/commit/0d2860b795879f4dd152963b52f969b53b136899
DIFF:
https://github.com/llvm/llvm-project/commit/0d2860b795879f4dd152963b52f969b53b136899.diff
LOG: [clang] Avoid memcopy for small structure with padding under
-ftrivial-auto-var-init (#71677)
Added:
Modified:
clang/lib/CodeGen/CGDecl.cpp
clang/test/CodeGenCXX/auto-var-init.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp
index e5795d811c76de7..a5da0aa2965a000 100644
--- a/clang/lib/CodeGen/CGDecl.cpp
+++ b/clang/lib/CodeGen/CGDecl.cpp
@@ -1244,29 +1244,24 @@ static void emitStoresForConstant(CodeGenModule &CGM,
const VarDecl &D,
// If the initializer is small, use a handful of stores.
if (shouldSplitConstantStore(CGM, ConstantSize)) {
if (auto *STy = dyn_cast(Ty)) {
- // FIXME: handle the case when STy != Loc.getElementType().
- if (STy == Loc.getElementType()) {
-for (unsigned i = 0; i != constant->getNumOperands(); i++) {
- Address EltPtr = Builder.CreateStructGEP(Loc, i);
- emitStoresForConstant(
- CGM, D, EltPtr, isVolatile, Builder,
- cast(Builder.CreateExtractValue(constant, i)),
- IsAutoInit);
-}
-return;
+ const llvm::StructLayout *Layout =
+ CGM.getDataLayout().getStructLayout(STy);
+ for (unsigned i = 0; i != constant->getNumOperands(); i++) {
+CharUnits CurOff =
CharUnits::fromQuantity(Layout->getElementOffset(i));
+Address EltPtr = Builder.CreateConstInBoundsByteGEP(
+Loc.withElementType(CGM.Int8Ty), CurOff);
+emitStoresForConstant(CGM, D, EltPtr, isVolatile, Builder,
+ constant->getAggregateElement(i), IsAutoInit);
}
+ return;
} else if (auto *ATy = dyn_cast(Ty)) {
- // FIXME: handle the case when ATy != Loc.getElementType().
- if (ATy == Loc.getElementType()) {
-for (unsigned i = 0; i != ATy->getNumElements(); i++) {
- Address EltPtr = Builder.CreateConstArrayGEP(Loc, i);
- emitStoresForConstant(
- CGM, D, EltPtr, isVolatile, Builder,
- cast(Builder.CreateExtractValue(constant, i)),
- IsAutoInit);
-}
-return;
+ for (unsigned i = 0; i != ATy->getNumElements(); i++) {
+Address EltPtr = Builder.CreateConstGEP(
+Loc.withElementType(ATy->getElementType()), i);
+emitStoresForConstant(CGM, D, EltPtr, isVolatile, Builder,
+ constant->getAggregateElement(i), IsAutoInit);
}
+ return;
}
}
diff --git a/clang/test/CodeGenCXX/auto-var-init.cpp
b/clang/test/CodeGenCXX/auto-var-init.cpp
index 6cb18528ebadcdf..e5a9d015f22f276 100644
--- a/clang/test/CodeGenCXX/auto-var-init.cpp
+++ b/clang/test/CodeGenCXX/auto-var-init.cpp
@@ -89,22 +89,14 @@ struct padded { char c; int i; };
// PATTERN-O1-NOT: @__const.test_paddednullinit_custom.custom
struct paddednullinit { char c = 0; int i = 0; };
// PATTERN-O0: @__const.test_paddedpacked_uninit.uninit = private unnamed_addr
constant %struct.paddedpacked <{ i8 [[I8]], i32 [[I32]] }>, align 1
-// PATTERN: @__const.test_paddedpacked_custom.custom = private unnamed_addr
constant %struct.paddedpacked <{ i8 42, i32 13371337 }>, align 1
-// ZERO: @__const.test_paddedpacked_custom.custom = private unnamed_addr
constant %struct.paddedpacked <{ i8 42, i32 13371337 }>, align 1
struct paddedpacked { char c; int i; } __attribute__((packed));
// PATTERN-O0: @__const.test_paddedpackedarray_uninit.uninit = private
unnamed_addr constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 [[I8]], i32 [[I32]] }>, %struct.paddedpacked <{ i8
[[I8]], i32 [[I32]] }>] }, align 1
-// PATTERN: @__const.test_paddedpackedarray_custom.custom = private
unnamed_addr constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 42, i32 13371337 }>, %struct.paddedpacked <{ i8 43,
i32 13371338 }>] }, align 1
-// ZERO: @__const.test_paddedpackedarray_custom.custom = private unnamed_addr
constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 42, i32 13371337 }>, %struct.paddedpacked <{ i8 43,
i32 13371338 }>] }, align 1
struct paddedpackedarray { struct paddedpacked p[2]; };
// PATTERN-O0: @__const.test_unpackedinpacked_uninit.uninit = private
unnamed_addr constant <{ { i8, [3 x i8], i32 }, i8 }> <{ { i8, [3 x i8], i32 }
{ i8 [[I8]], [3 x i8] c"\[[IC]]\[[IC]]\[[IC]]", i32 [[I32]] }, i8 [[I8]] }>,
align 1
struct unpackedinpacked { padded a; char b; } __attribute__((packed));
// PATTERN-O0: @__const.test_paddednested_uninit.uninit = private unnamed_addr
constant { {
[llvm-branch-commits] [llvm] 9ab133b - [nfc][InstrProfTest]Parameterize the edge cases of value profile merge by value kind (#73165)
Author: Mingming Liu
Date: 2023-11-22T21:22:20-08:00
New Revision: 9ab133bd9f9cedb880b453dd830b58857fab41ec
URL:
https://github.com/llvm/llvm-project/commit/9ab133bd9f9cedb880b453dd830b58857fab41ec
DIFF:
https://github.com/llvm/llvm-project/commit/9ab133bd9f9cedb880b453dd830b58857fab41ec.diff
LOG: [nfc][InstrProfTest]Parameterize the edge cases of value profile merge by
value kind (#73165)
There are three test cases to test the merge of value profiles.
'get_icall_data_merge1' tests the basic case;
{get_icall_data_merge1_saturation, get_icall_data_merge_site_trunc} tests the
edge case.
This patch parameterizes the edge case test coverage by value kind and adds the
coverage of 'IPVK_MemOPSize'. Keep the basic test structure as it is. The main
reason is test data construction and test assertions is
clearer for each kind in the basic test.
- Using a loop for different value kinds in one test case doesn't work
very well. The instr-prof-writer is stateful (e.g., keeps track of
per-function profile data in a
[container](https://github.com/llvm/llvm-project/blob/a9c149df7666bb2f8755794b97573134e5cfeb38/llvm/include/llvm/ProfileData/InstrProfWriter.h#L43))
Added:
Modified:
llvm/unittests/ProfileData/InstrProfTest.cpp
Removed:
diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp
b/llvm/unittests/ProfileData/InstrProfTest.cpp
index 875e2d06d839367..e6613a90dc7c53e 100644
--- a/llvm/unittests/ProfileData/InstrProfTest.cpp
+++ b/llvm/unittests/ProfileData/InstrProfTest.cpp
@@ -815,7 +815,7 @@ TEST_P(MaybeSparseInstrProfTest, annotate_vp_data) {
ASSERT_EQ(1U, ValueData[3].Count);
}
-TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1) {
+TEST_P(MaybeSparseInstrProfTest, icall_data_merge) {
static const char caller[] = "caller";
NamedInstrProfRecord Record11(caller, 0x1234, {1, 2});
NamedInstrProfRecord Record12(caller, 0x1234, {1, 2});
@@ -920,8 +920,18 @@ TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1) {
ASSERT_EQ(2U, VD_4[2].Count);
}
-TEST_P(MaybeSparseInstrProfTest, get_icall_data_merge1_saturation) {
+struct ValueProfileMergeEdgeCaseTest
+: public InstrProfTest,
+ public ::testing::WithParamInterface> {
+ void SetUp() override { Writer.setOutputSparse(std::get<0>(GetParam())); }
+
+ uint32_t getValueProfileKind() const { return std::get<1>(GetParam()); }
+};
+
+TEST_P(ValueProfileMergeEdgeCaseTest, value_profile_data_merge_saturation) {
+ const uint32_t ValueKind = getValueProfileKind();
static const char bar[] = "bar";
+ const uint64_t ProfiledValue = 0x5678;
const uint64_t MaxValCount = std::numeric_limits::max();
const uint64_t MaxEdgeCount = getInstrMaxCountValue();
@@ -944,18 +954,18 @@ TEST_P(MaybeSparseInstrProfTest,
get_icall_data_merge1_saturation) {
ASSERT_EQ(Result, instrprof_error::success);
NamedInstrProfRecord Record4("baz", 0x5678, {3, 4});
- Record4.reserveSites(IPVK_IndirectCallTarget, 1);
- InstrProfValueData VD4[] = {{uint64_t(bar), 1}};
- Record4.addValueData(IPVK_IndirectCallTarget, 0, VD4, 1, nullptr);
+ Record4.reserveSites(ValueKind, 1);
+ InstrProfValueData VD4[] = {{ProfiledValue, 1}};
+ Record4.addValueData(ValueKind, 0, VD4, 1, nullptr);
Result = instrprof_error::success;
Writer.addRecord(std::move(Record4), Err);
ASSERT_EQ(Result, instrprof_error::success);
// Verify value data counter overflow.
NamedInstrProfRecord Record5("baz", 0x5678, {5, 6});
- Record5.reserveSites(IPVK_IndirectCallTarget, 1);
- InstrProfValueData VD5[] = {{uint64_t(bar), MaxValCount}};
- Record5.addValueData(IPVK_IndirectCallTarget, 0, VD5, 1, nullptr);
+ Record5.reserveSites(ValueKind, 1);
+ InstrProfValueData VD5[] = {{ProfiledValue, MaxValCount}};
+ Record5.addValueData(ValueKind, 0, VD5, 1, nullptr);
Result = instrprof_error::success;
Writer.addRecord(std::move(Record5), Err);
ASSERT_EQ(Result, instrprof_error::counter_overflow);
@@ -966,48 +976,48 @@ TEST_P(MaybeSparseInstrProfTest,
get_icall_data_merge1_saturation) {
// Verify saturation of counts.
Expected ReadRecord1 =
Reader->getInstrProfRecord("foo", 0x1234);
- EXPECT_THAT_ERROR(ReadRecord1.takeError(), Succeeded());
- ASSERT_EQ(MaxEdgeCount, ReadRecord1->Counts[0]);
+ ASSERT_THAT_ERROR(ReadRecord1.takeError(), Succeeded());
+ EXPECT_EQ(MaxEdgeCount, ReadRecord1->Counts[0]);
Expected ReadRecord2 =
Reader->getInstrProfRecord("baz", 0x5678);
ASSERT_TRUE(bool(ReadRecord2));
- ASSERT_EQ(1U, ReadRecord2->getNumValueSites(IPVK_IndirectCallTarget));
+ ASSERT_EQ(1U, ReadRecord2->getNumValueSites(ValueKind));
std::unique_ptr VD =
- ReadRecord2->getValueForSite(IPVK_IndirectCallTarget, 0);
- ASSERT_EQ(StringRef("bar"), StringRef((const char *)VD[0].Value, 3));
- ASSERT_EQ(MaxValCount, VD[0].Count);
+ ReadRecord2->getValueForSite(ValueKind, 0);
+ EXPECT_EQ(ProfiledValue, VD[0].Value);
+ EXPECT
[llvm-branch-commits] [llvm] 7414c0d - [LoongArch] Precommit a test for smul with overflow (NFC) (#73212)
Author: hev
Date: 2023-11-23T15:15:26+08:00
New Revision: 7414c0db962f8a5029fd44c3e0bc93d9ce20be71
URL:
https://github.com/llvm/llvm-project/commit/7414c0db962f8a5029fd44c3e0bc93d9ce20be71
DIFF:
https://github.com/llvm/llvm-project/commit/7414c0db962f8a5029fd44c3e0bc93d9ce20be71.diff
LOG: [LoongArch] Precommit a test for smul with overflow (NFC) (#73212)
Added:
llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
b/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
new file mode 100644
index 000..a53e77e5aa4b342
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+define zeroext i1 @smuloi64(i64 %v1, i64 %v2, ptr %res) {
+; LA32-LABEL: smuloi64:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:st.w $fp, $sp, 8 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:.cfi_offset 22, -8
+; LA32-NEXT:move $fp, $a4
+; LA32-NEXT:st.w $zero, $sp, 4
+; LA32-NEXT:addi.w $a4, $sp, 4
+; LA32-NEXT:bl %plt(__mulodi4)
+; LA32-NEXT:st.w $a1, $fp, 4
+; LA32-NEXT:st.w $a0, $fp, 0
+; LA32-NEXT:ld.w $a0, $sp, 4
+; LA32-NEXT:sltu $a0, $zero, $a0
+; LA32-NEXT:ld.w $fp, $sp, 8 # 4-byte Folded Reload
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: smuloi64:
+; LA64: # %bb.0:
+; LA64-NEXT:mul.d $a3, $a0, $a1
+; LA64-NEXT:st.d $a3, $a2, 0
+; LA64-NEXT:mulh.d $a0, $a0, $a1
+; LA64-NEXT:srai.d $a1, $a3, 63
+; LA64-NEXT:xor $a0, $a0, $a1
+; LA64-NEXT:sltu $a0, $zero, $a0
+; LA64-NEXT:ret
+ %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, ptr %res
+ ret i1 %obit
+}
+
+define zeroext i1 @smuloi128(i128 %v1, i128 %v2, ptr %res) {
+; LA32-LABEL: smuloi128:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -64
+; LA32-NEXT:.cfi_def_cfa_offset 64
+; LA32-NEXT:st.w $ra, $sp, 60 # 4-byte Folded Spill
+; LA32-NEXT:st.w $fp, $sp, 56 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:.cfi_offset 22, -8
+; LA32-NEXT:move $fp, $a2
+; LA32-NEXT:st.w $zero, $sp, 52
+; LA32-NEXT:ld.w $a2, $a1, 12
+; LA32-NEXT:st.w $a2, $sp, 12
+; LA32-NEXT:ld.w $a2, $a1, 8
+; LA32-NEXT:st.w $a2, $sp, 8
+; LA32-NEXT:ld.w $a2, $a1, 4
+; LA32-NEXT:st.w $a2, $sp, 4
+; LA32-NEXT:ld.w $a1, $a1, 0
+; LA32-NEXT:st.w $a1, $sp, 0
+; LA32-NEXT:ld.w $a1, $a0, 12
+; LA32-NEXT:st.w $a1, $sp, 28
+; LA32-NEXT:ld.w $a1, $a0, 8
+; LA32-NEXT:st.w $a1, $sp, 24
+; LA32-NEXT:ld.w $a1, $a0, 4
+; LA32-NEXT:st.w $a1, $sp, 20
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:st.w $a0, $sp, 16
+; LA32-NEXT:addi.w $a0, $sp, 32
+; LA32-NEXT:addi.w $a1, $sp, 16
+; LA32-NEXT:addi.w $a2, $sp, 0
+; LA32-NEXT:addi.w $a3, $sp, 52
+; LA32-NEXT:bl %plt(__muloti4)
+; LA32-NEXT:ld.w $a0, $sp, 44
+; LA32-NEXT:st.w $a0, $fp, 12
+; LA32-NEXT:ld.w $a0, $sp, 40
+; LA32-NEXT:st.w $a0, $fp, 8
+; LA32-NEXT:ld.w $a0, $sp, 36
+; LA32-NEXT:st.w $a0, $fp, 4
+; LA32-NEXT:ld.w $a0, $sp, 32
+; LA32-NEXT:st.w $a0, $fp, 0
+; LA32-NEXT:ld.w $a0, $sp, 52
+; LA32-NEXT:sltu $a0, $zero, $a0
+; LA32-NEXT:ld.w $fp, $sp, 56 # 4-byte Folded Reload
+; LA32-NEXT:ld.w $ra, $sp, 60 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 64
+; LA32-NEXT:ret
+;
+; LA64-LABEL: smuloi128:
+; LA64: # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -32
+; LA64-NEXT:.cfi_def_cfa_offset 32
+; LA64-NEXT:st.d $ra, $sp, 24 # 8-byte Folded Spill
+; LA64-NEXT:st.d $fp, $sp, 16 # 8-byte Folded Spill
+; LA64-NEXT:.cfi_offset 1, -8
+; LA64-NEXT:.cfi_offset 22, -16
+; LA64-NEXT:move $fp, $a4
+; LA64-NEXT:st.d $zero, $sp, 8
+; LA64-NEXT:addi.d $a4, $sp, 8
+; LA64-NEXT:bl %plt(__muloti4)
+; LA64-NEXT:st.d $a1, $fp, 8
+; LA64-NEXT:st.d $a0, $fp, 0
+; LA64-NEXT:ld.d $a0, $sp, 8
+; LA64-NEXT:sltu $a0, $zero, $a0
+; LA64-NEXT:ld.d $fp, $sp, 16 # 8-byte Folded Reload
+; LA64-NEXT:ld.d $ra, $sp, 24 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 32
+; LA64-NEXT:ret
+ %t = call {i128, i1} @llvm.smul.with.overflow.i128(i128 %v1, i128 %v2)
+ %val = extractvalue {i128, i1} %t, 0
+ %obit = extractvalue {i128, i1} %t, 1
+ store i128 %val, ptr %r
[llvm-branch-commits] [flang] 7f18f9a - [flang][openacc][NFC] Merge acc-declare.f90 tests (#73055)
Author: Valentin Clement (バレンタイン クレメン)
Date: 2023-11-22T22:19:06-08:00
New Revision: 7f18f9a28c73490d09938af1fdb1908eb333a62c
URL:
https://github.com/llvm/llvm-project/commit/7f18f9a28c73490d09938af1fdb1908eb333a62c
DIFF:
https://github.com/llvm/llvm-project/commit/7f18f9a28c73490d09938af1fdb1908eb333a62c.diff
LOG: [flang][openacc][NFC] Merge acc-declare.f90 tests (#73055)
Added:
Modified:
flang/test/Lower/OpenACC/acc-declare.f90
Removed:
flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
diff --git a/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
b/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
deleted file mode 100644
index 17d1e5010d0a663..000
--- a/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
+++ /dev/null
@@ -1,314 +0,0 @@
-! This test checks lowering of OpenACC declare directive in function and
-! subroutine specification parts.
-
-! RUN: bbc -fopenacc -emit-hlfir %s -o - | FileCheck %s
-
-module acc_declare
- contains
-
- subroutine acc_declare_copy()
-integer :: a(100), i
-!$acc declare copy(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_copy()
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xi32> {bindc_name =
"a", uniq_name = "_QMacc_declareFacc_declare_copyEa"}
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) {acc.declare
= #acc.declare, uniq_name =
"_QMacc_declareFacc_declare_copyEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%[[C1]] : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[COPYIN:.*]] = acc.copyin varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {dataClause = #acc, name =
"a"}
-! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[COPYIN]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%{{.*}} = %{{.*}}) -> (index, i32) {
-! CHECK: }
-! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[COPYIN]] :
!fir.ref>)
-! CHECK: acc.copyout accPtr(%[[COPYIN]] : !fir.ref>)
bounds(%[[BOUND]]) to varPtr(%[[DECL]]#1 : !fir.ref>)
{dataClause = #acc, name = "a"}
-! CHECK: return
-
- subroutine acc_declare_create()
-integer :: a(100), i
-!$acc declare create(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_create() {
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xi32> {bindc_name =
"a", uniq_name = "_QMacc_declareFacc_declare_createEa"}
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) {acc.declare
= #acc.declare, uniq_name =
"_QMacc_declareFacc_declare_createEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%[[C1]] : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {name = "a"}
-! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[CREATE]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%{{.*}} = %{{.*}}) -> (index, i32) {
-! CHECK: }
-! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[CREATE]] :
!fir.ref>)
-! CHECK: acc.delete accPtr(%[[CREATE]] : !fir.ref>)
bounds(%[[BOUND]]) {dataClause = #acc, name = "a"}
-! CHECK: return
-
- subroutine acc_declare_present(a)
-integer :: a(100), i
-!$acc declare present(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_present(
-! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name =
"a"})
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare =
#acc.declare, uniq_name =
"_QMacc_declareFacc_declare_presentEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[PRESENT:.*]] = acc.present varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {name = "a"}
-! CHECK: acc.declare_enter dataOperands(%[[PRESENT]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%arg{{.*}} = %{{.*}}) -> (index, i32)
-
- subroutine acc_declare_copyin()
-integer :: a(100), b(10), i
-!$acc declare copyin(a) copyin(readonly: b)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func
[llvm-branch-commits] [llvm] 5973272 - [RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
Author: Wang Pengcheng
Date: 2023-11-23T14:05:23+08:00
New Revision: 5973272af796b33b75467ba8fba8b0a98b42757a
URL:
https://github.com/llvm/llvm-project/commit/5973272af796b33b75467ba8fba8b0a98b42757a
DIFF:
https://github.com/llvm/llvm-project/commit/5973272af796b33b75467ba8fba8b0a98b42757a.diff
LOG: [RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
This is like what AArch64 has done in #71166 except that we don't
handle `HasMinSize` case now.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/jumptable.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 97f9fb2223f1ae4..921b93c08ddde11 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1363,8 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
- setMinimumJumpTableEntries(5);
-
// Jumps are expensive, compared to logic
setJumpIsExpensive();
@@ -19701,6 +19699,11 @@ bool
RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
return AndMask.ugt(1024);
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
}
+
+unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
+ return Subtarget.getMinimumJumpTableEntries();
+}
+
namespace llvm::RISCVVIntrinsicsTable {
#define GET_RISCVVIntrinsicsTable_IMPL
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h
b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 3d6cd03c4d08f56..45200b54595a0b9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -962,6 +962,8 @@ class RISCVTargetLowering : public TargetLowering {
bool shouldFoldSelectWithSingleBitTest(EVT VT,
const APInt &AndMask) const override;
+
+ unsigned getMinimumJumpTableEntries() const override;
};
namespace RISCV {
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 95389b07e9c1cdb..90ba99d3f845d38 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -19,6 +19,8 @@ class RISCVTuneInfo {
bits<16> PrefetchDistance = 0;
bits<16> MinPrefetchStride = 1;
bits<32> MaxPrefetchIterationsAhead = -1;
+
+ bits<32> MinimumJumpTableEntries = 5;
}
def RISCVTuneInfoTable : GenericTable {
@@ -26,7 +28,8 @@ def RISCVTuneInfoTable : GenericTable {
let CppTypeName = "RISCVTuneInfo";
let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
"CacheLineSize", "PrefetchDistance",
-"MinPrefetchStride", "MaxPrefetchIterationsAhead"];
+"MinPrefetchStride", "MaxPrefetchIterationsAhead",
+"MinimumJumpTableEntries"];
}
def getRISCVTuneInfo : SearchIndex {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3e6af1abc5d408b..7b64d3cee9c8009 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -57,6 +57,10 @@ static cl::opt RISCVMaxBuildIntsCost(
static cl::opt UseAA("riscv-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));
+static cl::opt RISCVMinimumJumpTableEntries(
+"riscv-min-jump-table-entries", cl::Hidden,
+cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+
void RISCVSubtarget::anchor() {}
RISCVSubtarget &
@@ -189,3 +193,9 @@ void RISCVSubtarget::getPostRAMutations(
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool RISCVSubtarget::useAA() const { return UseAA; }
+
+unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
+ return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
+ ? RISCVMinimumJumpTableEntries
+ : TuneInfo->MinimumJumpTableEntries;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index c135021333acabc..52f00f1f099030c 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -44,6 +44,8 @@ struct RISCVTuneInfo {
uint16_t PrefetchDistance;
uint16_t MinPrefetchStride;
unsigned MaxPrefetchIterationsAhead;
+
+ unsigned MinimumJumpTableEntries;
};
#define GET_RISCVTuneInfoTable_DECL
@@ -270,6 +272,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMaxPrefetchIterationsAhead() const override {
[llvm-branch-commits] [clang] 0d2860b - [clang] Avoid memcopy for small structure with padding under -ftrivial-auto-var-init (#71677)
Author: serge-sans-paille
Date: 2023-11-23T05:38:14Z
New Revision: 0d2860b795879f4dd152963b52f969b53b136899
URL:
https://github.com/llvm/llvm-project/commit/0d2860b795879f4dd152963b52f969b53b136899
DIFF:
https://github.com/llvm/llvm-project/commit/0d2860b795879f4dd152963b52f969b53b136899.diff
LOG: [clang] Avoid memcopy for small structure with padding under
-ftrivial-auto-var-init (#71677)
Added:
Modified:
clang/lib/CodeGen/CGDecl.cpp
clang/test/CodeGenCXX/auto-var-init.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp
index e5795d811c76de7..a5da0aa2965a000 100644
--- a/clang/lib/CodeGen/CGDecl.cpp
+++ b/clang/lib/CodeGen/CGDecl.cpp
@@ -1244,29 +1244,24 @@ static void emitStoresForConstant(CodeGenModule &CGM,
const VarDecl &D,
// If the initializer is small, use a handful of stores.
if (shouldSplitConstantStore(CGM, ConstantSize)) {
if (auto *STy = dyn_cast(Ty)) {
- // FIXME: handle the case when STy != Loc.getElementType().
- if (STy == Loc.getElementType()) {
-for (unsigned i = 0; i != constant->getNumOperands(); i++) {
- Address EltPtr = Builder.CreateStructGEP(Loc, i);
- emitStoresForConstant(
- CGM, D, EltPtr, isVolatile, Builder,
- cast(Builder.CreateExtractValue(constant, i)),
- IsAutoInit);
-}
-return;
+ const llvm::StructLayout *Layout =
+ CGM.getDataLayout().getStructLayout(STy);
+ for (unsigned i = 0; i != constant->getNumOperands(); i++) {
+CharUnits CurOff =
CharUnits::fromQuantity(Layout->getElementOffset(i));
+Address EltPtr = Builder.CreateConstInBoundsByteGEP(
+Loc.withElementType(CGM.Int8Ty), CurOff);
+emitStoresForConstant(CGM, D, EltPtr, isVolatile, Builder,
+ constant->getAggregateElement(i), IsAutoInit);
}
+ return;
} else if (auto *ATy = dyn_cast(Ty)) {
- // FIXME: handle the case when ATy != Loc.getElementType().
- if (ATy == Loc.getElementType()) {
-for (unsigned i = 0; i != ATy->getNumElements(); i++) {
- Address EltPtr = Builder.CreateConstArrayGEP(Loc, i);
- emitStoresForConstant(
- CGM, D, EltPtr, isVolatile, Builder,
- cast(Builder.CreateExtractValue(constant, i)),
- IsAutoInit);
-}
-return;
+ for (unsigned i = 0; i != ATy->getNumElements(); i++) {
+Address EltPtr = Builder.CreateConstGEP(
+Loc.withElementType(ATy->getElementType()), i);
+emitStoresForConstant(CGM, D, EltPtr, isVolatile, Builder,
+ constant->getAggregateElement(i), IsAutoInit);
}
+ return;
}
}
diff --git a/clang/test/CodeGenCXX/auto-var-init.cpp
b/clang/test/CodeGenCXX/auto-var-init.cpp
index 6cb18528ebadcdf..e5a9d015f22f276 100644
--- a/clang/test/CodeGenCXX/auto-var-init.cpp
+++ b/clang/test/CodeGenCXX/auto-var-init.cpp
@@ -89,22 +89,14 @@ struct padded { char c; int i; };
// PATTERN-O1-NOT: @__const.test_paddednullinit_custom.custom
struct paddednullinit { char c = 0; int i = 0; };
// PATTERN-O0: @__const.test_paddedpacked_uninit.uninit = private unnamed_addr
constant %struct.paddedpacked <{ i8 [[I8]], i32 [[I32]] }>, align 1
-// PATTERN: @__const.test_paddedpacked_custom.custom = private unnamed_addr
constant %struct.paddedpacked <{ i8 42, i32 13371337 }>, align 1
-// ZERO: @__const.test_paddedpacked_custom.custom = private unnamed_addr
constant %struct.paddedpacked <{ i8 42, i32 13371337 }>, align 1
struct paddedpacked { char c; int i; } __attribute__((packed));
// PATTERN-O0: @__const.test_paddedpackedarray_uninit.uninit = private
unnamed_addr constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 [[I8]], i32 [[I32]] }>, %struct.paddedpacked <{ i8
[[I8]], i32 [[I32]] }>] }, align 1
-// PATTERN: @__const.test_paddedpackedarray_custom.custom = private
unnamed_addr constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 42, i32 13371337 }>, %struct.paddedpacked <{ i8 43,
i32 13371338 }>] }, align 1
-// ZERO: @__const.test_paddedpackedarray_custom.custom = private unnamed_addr
constant %struct.paddedpackedarray { [2 x %struct.paddedpacked]
[%struct.paddedpacked <{ i8 42, i32 13371337 }>, %struct.paddedpacked <{ i8 43,
i32 13371338 }>] }, align 1
struct paddedpackedarray { struct paddedpacked p[2]; };
// PATTERN-O0: @__const.test_unpackedinpacked_uninit.uninit = private
unnamed_addr constant <{ { i8, [3 x i8], i32 }, i8 }> <{ { i8, [3 x i8], i32 }
{ i8 [[I8]], [3 x i8] c"\[[IC]]\[[IC]]\[[IC]]", i32 [[I32]] }, i8 [[I8]] }>,
align 1
struct unpackedinpacked { padded a; char b; } __attribute__((packed));
// PATTERN-O0: @__const.test_paddednested_uninit.uninit = private unnamed_addr
constant { {
[llvm-branch-commits] [llvm] 5973272 - [RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
Author: Wang Pengcheng
Date: 2023-11-23T14:05:23+08:00
New Revision: 5973272af796b33b75467ba8fba8b0a98b42757a
URL:
https://github.com/llvm/llvm-project/commit/5973272af796b33b75467ba8fba8b0a98b42757a
DIFF:
https://github.com/llvm/llvm-project/commit/5973272af796b33b75467ba8fba8b0a98b42757a.diff
LOG: [RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
This is like what AArch64 has done in #71166 except that we don't
handle `HasMinSize` case now.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/jumptable.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 97f9fb2223f1ae4..921b93c08ddde11 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1363,8 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
- setMinimumJumpTableEntries(5);
-
// Jumps are expensive, compared to logic
setJumpIsExpensive();
@@ -19701,6 +19699,11 @@ bool
RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
return AndMask.ugt(1024);
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
}
+
+unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
+ return Subtarget.getMinimumJumpTableEntries();
+}
+
namespace llvm::RISCVVIntrinsicsTable {
#define GET_RISCVVIntrinsicsTable_IMPL
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h
b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 3d6cd03c4d08f56..45200b54595a0b9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -962,6 +962,8 @@ class RISCVTargetLowering : public TargetLowering {
bool shouldFoldSelectWithSingleBitTest(EVT VT,
const APInt &AndMask) const override;
+
+ unsigned getMinimumJumpTableEntries() const override;
};
namespace RISCV {
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 95389b07e9c1cdb..90ba99d3f845d38 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -19,6 +19,8 @@ class RISCVTuneInfo {
bits<16> PrefetchDistance = 0;
bits<16> MinPrefetchStride = 1;
bits<32> MaxPrefetchIterationsAhead = -1;
+
+ bits<32> MinimumJumpTableEntries = 5;
}
def RISCVTuneInfoTable : GenericTable {
@@ -26,7 +28,8 @@ def RISCVTuneInfoTable : GenericTable {
let CppTypeName = "RISCVTuneInfo";
let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
"CacheLineSize", "PrefetchDistance",
-"MinPrefetchStride", "MaxPrefetchIterationsAhead"];
+"MinPrefetchStride", "MaxPrefetchIterationsAhead",
+"MinimumJumpTableEntries"];
}
def getRISCVTuneInfo : SearchIndex {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3e6af1abc5d408b..7b64d3cee9c8009 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -57,6 +57,10 @@ static cl::opt RISCVMaxBuildIntsCost(
static cl::opt UseAA("riscv-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));
+static cl::opt RISCVMinimumJumpTableEntries(
+"riscv-min-jump-table-entries", cl::Hidden,
+cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+
void RISCVSubtarget::anchor() {}
RISCVSubtarget &
@@ -189,3 +193,9 @@ void RISCVSubtarget::getPostRAMutations(
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool RISCVSubtarget::useAA() const { return UseAA; }
+
+unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
+ return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
+ ? RISCVMinimumJumpTableEntries
+ : TuneInfo->MinimumJumpTableEntries;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index c135021333acabc..52f00f1f099030c 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -44,6 +44,8 @@ struct RISCVTuneInfo {
uint16_t PrefetchDistance;
uint16_t MinPrefetchStride;
unsigned MaxPrefetchIterationsAhead;
+
+ unsigned MinimumJumpTableEntries;
};
#define GET_RISCVTuneInfoTable_DECL
@@ -270,6 +272,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMaxPrefetchIterationsAhead() const override {
[llvm-branch-commits] [flang] 7f18f9a - [flang][openacc][NFC] Merge acc-declare.f90 tests (#73055)
Author: Valentin Clement (バレンタイン クレメン)
Date: 2023-11-22T22:19:06-08:00
New Revision: 7f18f9a28c73490d09938af1fdb1908eb333a62c
URL:
https://github.com/llvm/llvm-project/commit/7f18f9a28c73490d09938af1fdb1908eb333a62c
DIFF:
https://github.com/llvm/llvm-project/commit/7f18f9a28c73490d09938af1fdb1908eb333a62c.diff
LOG: [flang][openacc][NFC] Merge acc-declare.f90 tests (#73055)
Added:
Modified:
flang/test/Lower/OpenACC/acc-declare.f90
Removed:
flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
diff --git a/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
b/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
deleted file mode 100644
index 17d1e5010d0a663..000
--- a/flang/test/Lower/OpenACC/HLFIR/acc-declare.f90
+++ /dev/null
@@ -1,314 +0,0 @@
-! This test checks lowering of OpenACC declare directive in function and
-! subroutine specification parts.
-
-! RUN: bbc -fopenacc -emit-hlfir %s -o - | FileCheck %s
-
-module acc_declare
- contains
-
- subroutine acc_declare_copy()
-integer :: a(100), i
-!$acc declare copy(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_copy()
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xi32> {bindc_name =
"a", uniq_name = "_QMacc_declareFacc_declare_copyEa"}
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) {acc.declare
= #acc.declare, uniq_name =
"_QMacc_declareFacc_declare_copyEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%[[C1]] : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[COPYIN:.*]] = acc.copyin varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {dataClause = #acc, name =
"a"}
-! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[COPYIN]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%{{.*}} = %{{.*}}) -> (index, i32) {
-! CHECK: }
-! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[COPYIN]] :
!fir.ref>)
-! CHECK: acc.copyout accPtr(%[[COPYIN]] : !fir.ref>)
bounds(%[[BOUND]]) to varPtr(%[[DECL]]#1 : !fir.ref>)
{dataClause = #acc, name = "a"}
-! CHECK: return
-
- subroutine acc_declare_create()
-integer :: a(100), i
-!$acc declare create(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_create() {
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xi32> {bindc_name =
"a", uniq_name = "_QMacc_declareFacc_declare_createEa"}
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) {acc.declare
= #acc.declare, uniq_name =
"_QMacc_declareFacc_declare_createEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%[[C1]] : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {name = "a"}
-! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[CREATE]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%{{.*}} = %{{.*}}) -> (index, i32) {
-! CHECK: }
-! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[CREATE]] :
!fir.ref>)
-! CHECK: acc.delete accPtr(%[[CREATE]] : !fir.ref>)
bounds(%[[BOUND]]) {dataClause = #acc, name = "a"}
-! CHECK: return
-
- subroutine acc_declare_present(a)
-integer :: a(100), i
-!$acc declare present(a)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_present(
-! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name =
"a"})
-! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
-! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare =
#acc.declare, uniq_name =
"_QMacc_declareFacc_declare_presentEa"} : (!fir.ref>,
!fir.shape<1>) -> (!fir.ref>, !fir.ref>)
-! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index)
upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index)
startIdx(%[[C1]] : index)
-! CHECK: %[[PRESENT:.*]] = acc.present varPtr(%[[DECL]]#1 :
!fir.ref>) bounds(%[[BOUND]]) ->
!fir.ref> {name = "a"}
-! CHECK: acc.declare_enter dataOperands(%[[PRESENT]] :
!fir.ref>)
-! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}}
iter_args(%arg{{.*}} = %{{.*}}) -> (index, i32)
-
- subroutine acc_declare_copyin()
-integer :: a(100), b(10), i
-!$acc declare copyin(a) copyin(readonly: b)
-
-do i = 1, 100
- a(i) = i
-end do
- end subroutine
-
-! CHECK-LABEL: func
[llvm-branch-commits] [llvm] 7414c0d - [LoongArch] Precommit a test for smul with overflow (NFC) (#73212)
Author: hev
Date: 2023-11-23T15:15:26+08:00
New Revision: 7414c0db962f8a5029fd44c3e0bc93d9ce20be71
URL:
https://github.com/llvm/llvm-project/commit/7414c0db962f8a5029fd44c3e0bc93d9ce20be71
DIFF:
https://github.com/llvm/llvm-project/commit/7414c0db962f8a5029fd44c3e0bc93d9ce20be71.diff
LOG: [LoongArch] Precommit a test for smul with overflow (NFC) (#73212)
Added:
llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
b/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
new file mode 100644
index 000..a53e77e5aa4b342
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+define zeroext i1 @smuloi64(i64 %v1, i64 %v2, ptr %res) {
+; LA32-LABEL: smuloi64:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:.cfi_def_cfa_offset 16
+; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:st.w $fp, $sp, 8 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:.cfi_offset 22, -8
+; LA32-NEXT:move $fp, $a4
+; LA32-NEXT:st.w $zero, $sp, 4
+; LA32-NEXT:addi.w $a4, $sp, 4
+; LA32-NEXT:bl %plt(__mulodi4)
+; LA32-NEXT:st.w $a1, $fp, 4
+; LA32-NEXT:st.w $a0, $fp, 0
+; LA32-NEXT:ld.w $a0, $sp, 4
+; LA32-NEXT:sltu $a0, $zero, $a0
+; LA32-NEXT:ld.w $fp, $sp, 8 # 4-byte Folded Reload
+; LA32-NEXT:ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: smuloi64:
+; LA64: # %bb.0:
+; LA64-NEXT:mul.d $a3, $a0, $a1
+; LA64-NEXT:st.d $a3, $a2, 0
+; LA64-NEXT:mulh.d $a0, $a0, $a1
+; LA64-NEXT:srai.d $a1, $a3, 63
+; LA64-NEXT:xor $a0, $a0, $a1
+; LA64-NEXT:sltu $a0, $zero, $a0
+; LA64-NEXT:ret
+ %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, ptr %res
+ ret i1 %obit
+}
+
+define zeroext i1 @smuloi128(i128 %v1, i128 %v2, ptr %res) {
+; LA32-LABEL: smuloi128:
+; LA32: # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -64
+; LA32-NEXT:.cfi_def_cfa_offset 64
+; LA32-NEXT:st.w $ra, $sp, 60 # 4-byte Folded Spill
+; LA32-NEXT:st.w $fp, $sp, 56 # 4-byte Folded Spill
+; LA32-NEXT:.cfi_offset 1, -4
+; LA32-NEXT:.cfi_offset 22, -8
+; LA32-NEXT:move $fp, $a2
+; LA32-NEXT:st.w $zero, $sp, 52
+; LA32-NEXT:ld.w $a2, $a1, 12
+; LA32-NEXT:st.w $a2, $sp, 12
+; LA32-NEXT:ld.w $a2, $a1, 8
+; LA32-NEXT:st.w $a2, $sp, 8
+; LA32-NEXT:ld.w $a2, $a1, 4
+; LA32-NEXT:st.w $a2, $sp, 4
+; LA32-NEXT:ld.w $a1, $a1, 0
+; LA32-NEXT:st.w $a1, $sp, 0
+; LA32-NEXT:ld.w $a1, $a0, 12
+; LA32-NEXT:st.w $a1, $sp, 28
+; LA32-NEXT:ld.w $a1, $a0, 8
+; LA32-NEXT:st.w $a1, $sp, 24
+; LA32-NEXT:ld.w $a1, $a0, 4
+; LA32-NEXT:st.w $a1, $sp, 20
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:st.w $a0, $sp, 16
+; LA32-NEXT:addi.w $a0, $sp, 32
+; LA32-NEXT:addi.w $a1, $sp, 16
+; LA32-NEXT:addi.w $a2, $sp, 0
+; LA32-NEXT:addi.w $a3, $sp, 52
+; LA32-NEXT:bl %plt(__muloti4)
+; LA32-NEXT:ld.w $a0, $sp, 44
+; LA32-NEXT:st.w $a0, $fp, 12
+; LA32-NEXT:ld.w $a0, $sp, 40
+; LA32-NEXT:st.w $a0, $fp, 8
+; LA32-NEXT:ld.w $a0, $sp, 36
+; LA32-NEXT:st.w $a0, $fp, 4
+; LA32-NEXT:ld.w $a0, $sp, 32
+; LA32-NEXT:st.w $a0, $fp, 0
+; LA32-NEXT:ld.w $a0, $sp, 52
+; LA32-NEXT:sltu $a0, $zero, $a0
+; LA32-NEXT:ld.w $fp, $sp, 56 # 4-byte Folded Reload
+; LA32-NEXT:ld.w $ra, $sp, 60 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 64
+; LA32-NEXT:ret
+;
+; LA64-LABEL: smuloi128:
+; LA64: # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -32
+; LA64-NEXT:.cfi_def_cfa_offset 32
+; LA64-NEXT:st.d $ra, $sp, 24 # 8-byte Folded Spill
+; LA64-NEXT:st.d $fp, $sp, 16 # 8-byte Folded Spill
+; LA64-NEXT:.cfi_offset 1, -8
+; LA64-NEXT:.cfi_offset 22, -16
+; LA64-NEXT:move $fp, $a4
+; LA64-NEXT:st.d $zero, $sp, 8
+; LA64-NEXT:addi.d $a4, $sp, 8
+; LA64-NEXT:bl %plt(__muloti4)
+; LA64-NEXT:st.d $a1, $fp, 8
+; LA64-NEXT:st.d $a0, $fp, 0
+; LA64-NEXT:ld.d $a0, $sp, 8
+; LA64-NEXT:sltu $a0, $zero, $a0
+; LA64-NEXT:ld.d $fp, $sp, 16 # 8-byte Folded Reload
+; LA64-NEXT:ld.d $ra, $sp, 24 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 32
+; LA64-NEXT:ret
+ %t = call {i128, i1} @llvm.smul.with.overflow.i128(i128 %v1, i128 %v2)
+ %val = extractvalue {i128, i1} %t, 0
+ %obit = extractvalue {i128, i1} %t, 1
+ store i128 %val, ptr %r
[llvm-branch-commits] [libcxx] 7cbf959 - [libc++][test] Avoid using `allocator` (#73545)
Author: Stephan T. Lavavej
Date: 2023-11-27T17:19:34-08:00
New Revision: 7cbf9598cc6f207a268599cea636533a5c7b2dbd
URL:
https://github.com/llvm/llvm-project/commit/7cbf9598cc6f207a268599cea636533a5c7b2dbd
DIFF:
https://github.com/llvm/llvm-project/commit/7cbf9598cc6f207a268599cea636533a5c7b2dbd.diff
LOG: [libc++][test] Avoid using `allocator` (#73545)
Found while running libc++'s test suite with MSVC's STL.
MSVC's STL rejects `allocator`. This may or may not be
justified by the current Standardese (it was bogus in the C++03 era),
but it's how we reject usage like `vector`.
A bunch of `mdspan` tests are failing for us because some centralized
machinery is using `allocator`. Testing that `mdspan` and its
associated types work properly with `const T` is good and necessary, but
directly allocating `const T` is what's a problem for MSVC's STL. I'd
like to ask for a very targeted change here that preserves all of the
test coverage but changes how `ElementPool` interacts with `allocator`.
This intentionally leaves `ElementPool::get_ptr()` returning `T*`
(pointer-to-possibly-const), so there's no externally visible
difference.
Added:
Modified:
libcxx/test/std/containers/views/mdspan/MinimalElementType.h
Removed:
diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
index b1fbd6ed944d179..fe7f0e1f2383790 100644
--- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
+++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
@@ -9,7 +9,8 @@
#ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
#define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
-#include
+#include
+#include
// Idiosyncratic element type for mdspan
// Make sure we don't assume copyable, default constructible, movable etc.
@@ -25,7 +26,7 @@ struct MinimalElementType {
template
struct ElementPool {
constexpr ElementPool() {
-ptr_ = std::allocator().allocate(N);
+ptr_ = std::allocator>().allocate(N);
for (int i = 0; i != N; ++i)
std::construct_at(ptr_ + i, 42);
}
@@ -35,11 +36,11 @@ struct ElementPool {
constexpr ~ElementPool() {
for (int i = 0; i != N; ++i)
std::destroy_at(ptr_ + i);
-std::allocator().deallocate(ptr_, N);
+std::allocator>().deallocate(ptr_, N);
}
private:
- T* ptr_;
+ std::remove_const_t* ptr_;
};
#endif // TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
___
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[llvm-branch-commits] [mlir] 17ec364 - [mlir][python] enable registering dialects with the default `Context` (#72488)
Author: Maksim Levental
Date: 2023-11-27T19:26:05-06:00
New Revision: 17ec364b1b338b6bee5a65a886d0fe75089e6bb9
URL:
https://github.com/llvm/llvm-project/commit/17ec364b1b338b6bee5a65a886d0fe75089e6bb9
DIFF:
https://github.com/llvm/llvm-project/commit/17ec364b1b338b6bee5a65a886d0fe75089e6bb9.diff
LOG: [mlir][python] enable registering dialects with the default `Context`
(#72488)
Added:
Modified:
mlir/python/mlir/_mlir_libs/__init__.py
mlir/python/mlir/dialects/python_test.py
mlir/python/mlir/ir.py
mlir/test/python/dialects/python_test.py
mlir/test/python/lib/PythonTestModule.cpp
Removed:
diff --git a/mlir/python/mlir/_mlir_libs/__init__.py
b/mlir/python/mlir/_mlir_libs/__init__.py
index 6ce77b4cb93f609..32f46d24cc7392b 100644
--- a/mlir/python/mlir/_mlir_libs/__init__.py
+++ b/mlir/python/mlir/_mlir_libs/__init__.py
@@ -56,6 +56,21 @@ def get_include_dirs() -> Sequence[str]:
#
# This facility allows downstreams to customize Context creation to their
# needs.
+
+_dialect_registry = None
+
+
+def get_dialect_registry():
+global _dialect_registry
+
+if _dialect_registry is None:
+from ._mlir import ir
+
+_dialect_registry = ir.DialectRegistry()
+
+return _dialect_registry
+
+
def _site_initialize():
import importlib
import itertools
@@ -63,7 +78,6 @@ def _site_initialize():
from ._mlir import ir
logger = logging.getLogger(__name__)
-registry = ir.DialectRegistry()
post_init_hooks = []
disable_multithreading = False
@@ -84,7 +98,7 @@ def process_initializer_module(module_name):
logger.debug("Initializing MLIR with module: %s", module_name)
if hasattr(m, "register_dialects"):
logger.debug("Registering dialects from initializer %r", m)
-m.register_dialects(registry)
+m.register_dialects(get_dialect_registry())
if hasattr(m, "context_init_hook"):
logger.debug("Adding context init hook from %r", m)
post_init_hooks.append(m.context_init_hook)
@@ -110,7 +124,7 @@ def process_initializer_module(module_name):
class Context(ir._BaseContext):
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
-self.append_dialect_registry(registry)
+self.append_dialect_registry(get_dialect_registry())
for hook in post_init_hooks:
hook(self)
if not disable_multithreading:
diff --git a/mlir/python/mlir/dialects/python_test.py
b/mlir/python/mlir/dialects/python_test.py
index 6579e02d8549efa..b5baa80bc767fb3 100644
--- a/mlir/python/mlir/dialects/python_test.py
+++ b/mlir/python/mlir/dialects/python_test.py
@@ -11,7 +11,7 @@
)
-def register_python_test_dialect(context, load=True):
+def register_python_test_dialect(registry):
from .._mlir_libs import _mlirPythonTest
-_mlirPythonTest.register_python_test_dialect(context, load)
+_mlirPythonTest.register_dialect(registry)
diff --git a/mlir/python/mlir/ir.py b/mlir/python/mlir/ir.py
index 18526ab8c3c02dc..6d21da3b4179fdf 100644
--- a/mlir/python/mlir/ir.py
+++ b/mlir/python/mlir/ir.py
@@ -5,6 +5,7 @@
from ._mlir_libs._mlir.ir import *
from ._mlir_libs._mlir.ir import _GlobalDebug
from ._mlir_libs._mlir import register_type_caster, register_value_caster
+from ._mlir_libs import get_dialect_registry
# Convenience decorator for registering user-friendly Attribute builders.
diff --git a/mlir/test/python/dialects/python_test.py
b/mlir/test/python/dialects/python_test.py
index f313a400b73c0a5..88761c9d08fe07c 100644
--- a/mlir/test/python/dialects/python_test.py
+++ b/mlir/test/python/dialects/python_test.py
@@ -6,6 +6,8 @@
import mlir.dialects.tensor as tensor
import mlir.dialects.arith as arith
+test.register_python_test_dialect(get_dialect_registry())
+
def run(f):
print("\nTEST:", f.__name__)
@@ -17,7 +19,6 @@ def run(f):
@run
def testAttributes():
with Context() as ctx, Location.unknown():
-test.register_python_test_dialect(ctx)
#
# Check op construction with attributes.
#
@@ -138,7 +139,6 @@ def testAttributes():
@run
def attrBuilder():
with Context() as ctx, Location.unknown():
-test.register_python_test_dialect(ctx)
# CHECK: python_test.attributes_op
op = test.AttributesOp(
# CHECK-DAG: x_affinemap = affine_map<() -> (2)>
@@ -215,7 +215,6 @@ def attrBuilder():
@run
def inferReturnTypes():
with Context() as ctx, Location.unknown(ctx):
-test.register_python_test_dialect(ctx)
module = Module.create()
with InsertionPoint(module.body):
op = test.InferResultsOp()
@@ -260,7 +259,6 @@ def inferReturnTypes():
@run
def resultTypesDefinedByTraits():
with Context() as ctx, Location.unknown(ctx):
-test.register_python_te
[llvm-branch-commits] [clang] [llvm] [libc] [compiler-rt] [mlir] [flang] [libcxx] [clang-tools-extra] [sanitizer_symbolizer] RenderContextual elements for symbolizer markup. (PR #73194)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] 79cb594 - [mlir][sparse] remove unused COO method (#73595)
Author: Aart Bik
Date: 2023-11-27T17:26:45-08:00
New Revision: 79cb594fdf15c4bb8fc357b615210e6e57eb1c26
URL:
https://github.com/llvm/llvm-project/commit/79cb594fdf15c4bb8fc357b615210e6e57eb1c26
DIFF:
https://github.com/llvm/llvm-project/commit/79cb594fdf15c4bb8fc357b615210e6e57eb1c26.diff
LOG: [mlir][sparse] remove unused COO method (#73595)
step closer towards moving all type related methods into encoding and/or
sparse tensor type class
Added:
Modified:
mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Removed:
diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
index f102f0270154264..517c286e0206997 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
@@ -102,12 +102,10 @@ bool isUniqueCOOType(Type tp);
/// the level-rank.
Level getCOOStart(SparseTensorEncodingAttr enc);
-/// Helpers to setup a COO type.
+/// Helper to setup a COO type.
RankedTensorType getCOOFromTypeWithOrdering(RankedTensorType src,
AffineMap ordering, bool ordered);
-RankedTensorType getCOOFromType(RankedTensorType src, bool ordered);
-
/// Returns true iff MLIR operand has any sparse operand.
inline bool hasAnySparseOperand(Operation *op) {
return llvm::any_of(op->getOperands().getTypes(), [](Type t) {
diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index c4a828a20465a80..ff2930008fa093f 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -878,7 +878,7 @@ Level
mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) {
return lvlRank;
}
-// Helpers to setup a COO type.
+// Helper to setup a COO type.
RankedTensorType sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType
rtt,
AffineMap lvlPerm,
bool ordered) {
@@ -911,13 +911,6 @@ RankedTensorType
sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType rtt,
return RankedTensorType::get(src.getDimShape(), src.getElementType(), enc);
}
-RankedTensorType sparse_tensor::getCOOFromType(RankedTensorType src,
- bool ordered) {
- return getCOOFromTypeWithOrdering(
- src, AffineMap::getMultiDimIdentityMap(src.getRank(), src.getContext()),
- ordered);
-}
-
Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) {
if (enc) {
assert(enc.isPermutation() && "Non permutation map not supported");
___
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[llvm-branch-commits] [clang] [libcxx] [clang-tools-extra] [llvm] [libc] [compiler-rt] [mlir] [flang] [sanitizer_symbolizer] RenderContextual elements for symbolizer markup. (PR #73194)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] d3143a0 - Add `REQUIRES: systemz-registered-target` to test added in #68926 (9a38a72).
Author: Douglas Yung
Date: 2023-11-27T17:35:24-08:00
New Revision: d3143a09acb30f9d3978373d20d67d2c78ce07a9
URL:
https://github.com/llvm/llvm-project/commit/d3143a09acb30f9d3978373d20d67d2c78ce07a9
DIFF:
https://github.com/llvm/llvm-project/commit/d3143a09acb30f9d3978373d20d67d2c78ce07a9.diff
LOG: Add `REQUIRES: systemz-registered-target` to test added in #68926
(9a38a72).
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-ppa2.c
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 21ccd0d7b834c19..0ff4cba5edfb6c6 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -10,6 +10,8 @@
// .byte (i.e., the one for the 3) would, it seems, also match
// the .byte line below for the 34.
+// REQUIRES: systemz-registered-target
+
// RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s
--check-prefix CHECK-C
// CHECK-C:[[PPA2:(.L)|(@@)PPA2]]:
// CHECK-C-NEXT: .byte3{{[[:space:]]*}}.byte 0
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[llvm-branch-commits] [libcxx] 7cbf959 - [libc++][test] Avoid using `allocator` (#73545)
Author: Stephan T. Lavavej
Date: 2023-11-27T17:19:34-08:00
New Revision: 7cbf9598cc6f207a268599cea636533a5c7b2dbd
URL:
https://github.com/llvm/llvm-project/commit/7cbf9598cc6f207a268599cea636533a5c7b2dbd
DIFF:
https://github.com/llvm/llvm-project/commit/7cbf9598cc6f207a268599cea636533a5c7b2dbd.diff
LOG: [libc++][test] Avoid using `allocator` (#73545)
Found while running libc++'s test suite with MSVC's STL.
MSVC's STL rejects `allocator`. This may or may not be
justified by the current Standardese (it was bogus in the C++03 era),
but it's how we reject usage like `vector`.
A bunch of `mdspan` tests are failing for us because some centralized
machinery is using `allocator`. Testing that `mdspan` and its
associated types work properly with `const T` is good and necessary, but
directly allocating `const T` is what's a problem for MSVC's STL. I'd
like to ask for a very targeted change here that preserves all of the
test coverage but changes how `ElementPool` interacts with `allocator`.
This intentionally leaves `ElementPool::get_ptr()` returning `T*`
(pointer-to-possibly-const), so there's no externally visible
difference.
Added:
Modified:
libcxx/test/std/containers/views/mdspan/MinimalElementType.h
Removed:
diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
index b1fbd6ed944d179..fe7f0e1f2383790 100644
--- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
+++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
@@ -9,7 +9,8 @@
#ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
#define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
-#include
+#include
+#include
// Idiosyncratic element type for mdspan
// Make sure we don't assume copyable, default constructible, movable etc.
@@ -25,7 +26,7 @@ struct MinimalElementType {
template
struct ElementPool {
constexpr ElementPool() {
-ptr_ = std::allocator().allocate(N);
+ptr_ = std::allocator>().allocate(N);
for (int i = 0; i != N; ++i)
std::construct_at(ptr_ + i, 42);
}
@@ -35,11 +36,11 @@ struct ElementPool {
constexpr ~ElementPool() {
for (int i = 0; i != N; ++i)
std::destroy_at(ptr_ + i);
-std::allocator().deallocate(ptr_, N);
+std::allocator>().deallocate(ptr_, N);
}
private:
- T* ptr_;
+ std::remove_const_t* ptr_;
};
#endif // TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
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[llvm-branch-commits] [mlir] 17ec364 - [mlir][python] enable registering dialects with the default `Context` (#72488)
Author: Maksim Levental
Date: 2023-11-27T19:26:05-06:00
New Revision: 17ec364b1b338b6bee5a65a886d0fe75089e6bb9
URL:
https://github.com/llvm/llvm-project/commit/17ec364b1b338b6bee5a65a886d0fe75089e6bb9
DIFF:
https://github.com/llvm/llvm-project/commit/17ec364b1b338b6bee5a65a886d0fe75089e6bb9.diff
LOG: [mlir][python] enable registering dialects with the default `Context`
(#72488)
Added:
Modified:
mlir/python/mlir/_mlir_libs/__init__.py
mlir/python/mlir/dialects/python_test.py
mlir/python/mlir/ir.py
mlir/test/python/dialects/python_test.py
mlir/test/python/lib/PythonTestModule.cpp
Removed:
diff --git a/mlir/python/mlir/_mlir_libs/__init__.py
b/mlir/python/mlir/_mlir_libs/__init__.py
index 6ce77b4cb93f609..32f46d24cc7392b 100644
--- a/mlir/python/mlir/_mlir_libs/__init__.py
+++ b/mlir/python/mlir/_mlir_libs/__init__.py
@@ -56,6 +56,21 @@ def get_include_dirs() -> Sequence[str]:
#
# This facility allows downstreams to customize Context creation to their
# needs.
+
+_dialect_registry = None
+
+
+def get_dialect_registry():
+global _dialect_registry
+
+if _dialect_registry is None:
+from ._mlir import ir
+
+_dialect_registry = ir.DialectRegistry()
+
+return _dialect_registry
+
+
def _site_initialize():
import importlib
import itertools
@@ -63,7 +78,6 @@ def _site_initialize():
from ._mlir import ir
logger = logging.getLogger(__name__)
-registry = ir.DialectRegistry()
post_init_hooks = []
disable_multithreading = False
@@ -84,7 +98,7 @@ def process_initializer_module(module_name):
logger.debug("Initializing MLIR with module: %s", module_name)
if hasattr(m, "register_dialects"):
logger.debug("Registering dialects from initializer %r", m)
-m.register_dialects(registry)
+m.register_dialects(get_dialect_registry())
if hasattr(m, "context_init_hook"):
logger.debug("Adding context init hook from %r", m)
post_init_hooks.append(m.context_init_hook)
@@ -110,7 +124,7 @@ def process_initializer_module(module_name):
class Context(ir._BaseContext):
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
-self.append_dialect_registry(registry)
+self.append_dialect_registry(get_dialect_registry())
for hook in post_init_hooks:
hook(self)
if not disable_multithreading:
diff --git a/mlir/python/mlir/dialects/python_test.py
b/mlir/python/mlir/dialects/python_test.py
index 6579e02d8549efa..b5baa80bc767fb3 100644
--- a/mlir/python/mlir/dialects/python_test.py
+++ b/mlir/python/mlir/dialects/python_test.py
@@ -11,7 +11,7 @@
)
-def register_python_test_dialect(context, load=True):
+def register_python_test_dialect(registry):
from .._mlir_libs import _mlirPythonTest
-_mlirPythonTest.register_python_test_dialect(context, load)
+_mlirPythonTest.register_dialect(registry)
diff --git a/mlir/python/mlir/ir.py b/mlir/python/mlir/ir.py
index 18526ab8c3c02dc..6d21da3b4179fdf 100644
--- a/mlir/python/mlir/ir.py
+++ b/mlir/python/mlir/ir.py
@@ -5,6 +5,7 @@
from ._mlir_libs._mlir.ir import *
from ._mlir_libs._mlir.ir import _GlobalDebug
from ._mlir_libs._mlir import register_type_caster, register_value_caster
+from ._mlir_libs import get_dialect_registry
# Convenience decorator for registering user-friendly Attribute builders.
diff --git a/mlir/test/python/dialects/python_test.py
b/mlir/test/python/dialects/python_test.py
index f313a400b73c0a5..88761c9d08fe07c 100644
--- a/mlir/test/python/dialects/python_test.py
+++ b/mlir/test/python/dialects/python_test.py
@@ -6,6 +6,8 @@
import mlir.dialects.tensor as tensor
import mlir.dialects.arith as arith
+test.register_python_test_dialect(get_dialect_registry())
+
def run(f):
print("\nTEST:", f.__name__)
@@ -17,7 +19,6 @@ def run(f):
@run
def testAttributes():
with Context() as ctx, Location.unknown():
-test.register_python_test_dialect(ctx)
#
# Check op construction with attributes.
#
@@ -138,7 +139,6 @@ def testAttributes():
@run
def attrBuilder():
with Context() as ctx, Location.unknown():
-test.register_python_test_dialect(ctx)
# CHECK: python_test.attributes_op
op = test.AttributesOp(
# CHECK-DAG: x_affinemap = affine_map<() -> (2)>
@@ -215,7 +215,6 @@ def attrBuilder():
@run
def inferReturnTypes():
with Context() as ctx, Location.unknown(ctx):
-test.register_python_test_dialect(ctx)
module = Module.create()
with InsertionPoint(module.body):
op = test.InferResultsOp()
@@ -260,7 +259,6 @@ def inferReturnTypes():
@run
def resultTypesDefinedByTraits():
with Context() as ctx, Location.unknown(ctx):
-test.register_python_te
[clang] 8795eef - [𝘀𝗽𝗿] changes introduced through rebase
Author: Andres Villegas
Date: 2023-11-28T01:36:59Z
New Revision: 8795eefc5029569b56b757269e4bec19c01a5b63
URL:
https://github.com/llvm/llvm-project/commit/8795eefc5029569b56b757269e4bec19c01a5b63
DIFF:
https://github.com/llvm/llvm-project/commit/8795eefc5029569b56b757269e4bec19c01a5b63.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-ppa2.c
libcxx/test/std/containers/views/mdspan/MinimalElementType.h
mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
mlir/python/mlir/_mlir_libs/__init__.py
mlir/python/mlir/dialects/python_test.py
mlir/python/mlir/ir.py
mlir/test/python/dialects/python_test.py
mlir/test/python/lib/PythonTestModule.cpp
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 21ccd0d7b834c19..0ff4cba5edfb6c6 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -10,6 +10,8 @@
// .byte (i.e., the one for the 3) would, it seems, also match
// the .byte line below for the 34.
+// REQUIRES: systemz-registered-target
+
// RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s
--check-prefix CHECK-C
// CHECK-C:[[PPA2:(.L)|(@@)PPA2]]:
// CHECK-C-NEXT: .byte3{{[[:space:]]*}}.byte 0
diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
index b1fbd6ed944d179..fe7f0e1f2383790 100644
--- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
+++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
@@ -9,7 +9,8 @@
#ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
#define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
-#include
+#include
+#include
// Idiosyncratic element type for mdspan
// Make sure we don't assume copyable, default constructible, movable etc.
@@ -25,7 +26,7 @@ struct MinimalElementType {
template
struct ElementPool {
constexpr ElementPool() {
-ptr_ = std::allocator().allocate(N);
+ptr_ = std::allocator>().allocate(N);
for (int i = 0; i != N; ++i)
std::construct_at(ptr_ + i, 42);
}
@@ -35,11 +36,11 @@ struct ElementPool {
constexpr ~ElementPool() {
for (int i = 0; i != N; ++i)
std::destroy_at(ptr_ + i);
-std::allocator().deallocate(ptr_, N);
+std::allocator>().deallocate(ptr_, N);
}
private:
- T* ptr_;
+ std::remove_const_t* ptr_;
};
#endif // TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
index f102f0270154264..517c286e0206997 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
@@ -102,12 +102,10 @@ bool isUniqueCOOType(Type tp);
/// the level-rank.
Level getCOOStart(SparseTensorEncodingAttr enc);
-/// Helpers to setup a COO type.
+/// Helper to setup a COO type.
RankedTensorType getCOOFromTypeWithOrdering(RankedTensorType src,
AffineMap ordering, bool ordered);
-RankedTensorType getCOOFromType(RankedTensorType src, bool ordered);
-
/// Returns true iff MLIR operand has any sparse operand.
inline bool hasAnySparseOperand(Operation *op) {
return llvm::any_of(op->getOperands().getTypes(), [](Type t) {
diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index c4a828a20465a80..ff2930008fa093f 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -878,7 +878,7 @@ Level
mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) {
return lvlRank;
}
-// Helpers to setup a COO type.
+// Helper to setup a COO type.
RankedTensorType sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType
rtt,
AffineMap lvlPerm,
bool ordered) {
@@ -911,13 +911,6 @@ RankedTensorType
sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType rtt,
return RankedTensorType::get(src.getDimShape(), src.getElementType(), enc);
}
-RankedTensorType sparse_tensor::getCOOFromType(RankedTensorType src,
- bool ordered) {
- return getCOOFromTypeWithOrdering(
- src, AffineMap::getMultiDimIdentityMap(src.getRank(), src.getContext()),
- ordered);
-}
-
Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) {
if (enc) {
assert(enc.isPermuta
[llvm-branch-commits] [clang] [llvm] [libc] [compiler-rt] [mlir] [flang] [libcxx] [clang-tools-extra] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] 79cb594 - [mlir][sparse] remove unused COO method (#73595)
Author: Aart Bik
Date: 2023-11-27T17:26:45-08:00
New Revision: 79cb594fdf15c4bb8fc357b615210e6e57eb1c26
URL:
https://github.com/llvm/llvm-project/commit/79cb594fdf15c4bb8fc357b615210e6e57eb1c26
DIFF:
https://github.com/llvm/llvm-project/commit/79cb594fdf15c4bb8fc357b615210e6e57eb1c26.diff
LOG: [mlir][sparse] remove unused COO method (#73595)
step closer towards moving all type related methods into encoding and/or
sparse tensor type class
Added:
Modified:
mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Removed:
diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
index f102f0270154264..517c286e0206997 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
@@ -102,12 +102,10 @@ bool isUniqueCOOType(Type tp);
/// the level-rank.
Level getCOOStart(SparseTensorEncodingAttr enc);
-/// Helpers to setup a COO type.
+/// Helper to setup a COO type.
RankedTensorType getCOOFromTypeWithOrdering(RankedTensorType src,
AffineMap ordering, bool ordered);
-RankedTensorType getCOOFromType(RankedTensorType src, bool ordered);
-
/// Returns true iff MLIR operand has any sparse operand.
inline bool hasAnySparseOperand(Operation *op) {
return llvm::any_of(op->getOperands().getTypes(), [](Type t) {
diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index c4a828a20465a80..ff2930008fa093f 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -878,7 +878,7 @@ Level
mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) {
return lvlRank;
}
-// Helpers to setup a COO type.
+// Helper to setup a COO type.
RankedTensorType sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType
rtt,
AffineMap lvlPerm,
bool ordered) {
@@ -911,13 +911,6 @@ RankedTensorType
sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType rtt,
return RankedTensorType::get(src.getDimShape(), src.getElementType(), enc);
}
-RankedTensorType sparse_tensor::getCOOFromType(RankedTensorType src,
- bool ordered) {
- return getCOOFromTypeWithOrdering(
- src, AffineMap::getMultiDimIdentityMap(src.getRank(), src.getContext()),
- ordered);
-}
-
Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) {
if (enc) {
assert(enc.isPermutation() && "Non permutation map not supported");
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[llvm-branch-commits] [clang] [mlir] [libcxx] [flang] [clang-tools-extra] [llvm] [libc] [compiler-rt] [sanitizer_common tests] Add tests for sanitizer symbolzier markup. (PR #73195)
https://github.com/avillega updated https://github.com/llvm/llvm-project/pull/73195 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] 8b3944c - [sanitizer_symbolizer] Add initial symbolizer markup support for linux.
Author: Andres Villegas
Date: 2023-11-27T17:36:09-08:00
New Revision: 8b3944ca19645df13b0800336de2bac77ddb60b0
URL:
https://github.com/llvm/llvm-project/commit/8b3944ca19645df13b0800336de2bac77ddb60b0
DIFF:
https://github.com/llvm/llvm-project/commit/8b3944ca19645df13b0800336de2bac77ddb60b0.diff
LOG: [sanitizer_symbolizer] Add initial symbolizer markup support for linux.
This is part of a stack of PRs to add support for symbolizer
markup in linux.
You can check the symbolizer markup specification at:
https://llvm.org/docs/SymbolizerMarkupFormat.html
Reviewers: vitalybuka, PiJoules
Reviewed By: vitalybuka
Pull Request: https://github.com/llvm/llvm-project/pull/73193
Added:
Modified:
compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp
Removed:
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
b/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
index 949bdbd148b6b89..7836347d233add9 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
@@ -275,3 +275,7 @@ COMMON_FLAG(bool, test_only_emulate_no_memorymap, false,
// program.
COMMON_FLAG(bool, test_only_replace_dlopen_main_program, false,
"TEST ONLY replace dlopen(,...) with dlopen(NULL)")
+
+COMMON_FLAG(bool, enable_symbolizer_markup, SANITIZER_FUCHSIA,
+"Use sanitizer symbolizer markup, available on Linux "
+"and always set true for Fuchsia.")
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
index 88f186b9c20c105..748d832ccc211d0 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
@@ -16,6 +16,7 @@
#include "sanitizer_file.h"
#include "sanitizer_flags.h"
#include "sanitizer_fuchsia.h"
+#include "sanitizer_symbolizer_markup.h"
namespace __sanitizer {
@@ -62,6 +63,9 @@ const char *StackTracePrinter::StripFunctionName(const char
*function) {
#if !SANITIZER_SYMBOLIZER_MARKUP
StackTracePrinter *StackTracePrinter::NewStackTracePrinter() {
+ if (common_flags()->enable_symbolizer_markup)
+return new (GetGlobalLowLevelAllocator()) MarkupStackTracePrinter();
+
return new (GetGlobalLowLevelAllocator()) FormattedStackTracePrinter();
}
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
index c364e1e300225b9..1627908185f2009 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
@@ -45,4 +45,23 @@ void
MarkupStackTracePrinter::RenderFrame(InternalScopedString *buffer,
buffer->AppendF(kFormatFrame, frame_no, address);
}
+bool MarkupSymbolizerTool::SymbolizePC(uptr addr, SymbolizedStack *stack) {
+ char buffer[kFormatFunctionMax];
+ internal_snprintf(buffer, sizeof(buffer), kFormatFunction, addr);
+ stack->info.function = internal_strdup(buffer);
+ return true;
+}
+
+bool MarkupSymbolizerTool::SymbolizeData(uptr addr, DataInfo *info) {
+ info->Clear();
+ info->start = addr;
+ return true;
+}
+
+const char *MarkupSymbolizerTool::Demangle(const char *name) {
+ static char buffer[kFormatDemangleMax];
+ internal_snprintf(buffer, sizeof(buffer), kFormatDemangle, name);
+ return buffer;
+}
+
} // namespace __sanitizer
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
index 7cebe520e9bebb4..07630d0b3bdf417 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
@@ -16,6 +16,7 @@
#include "sanitizer_common.h"
#include "sanitizer_stacktrace_printer.h"
#include "sanitizer_symbolizer.h"
+#include "sanitizer_symbolizer_internal.h"
namespace __sanitizer {
@@ -40,6 +41,28 @@ class MarkupStackTracePrinter : public StackTracePrinter {
~MarkupStackTracePrinter() {}
};
+class MarkupSymbolizerTool final : public SymbolizerTool {
+ public:
+ // This is used in some places for suppression checking, which we
+ // don't really support for Fuchsia. It's also used in UBSan to
+ // identify a PC location to a function name, so we always fill in
+ // the function member with a string containing markup around the PC
+ // value.
+ // TODO(mcgrathr): Under SANITIZER_GO, it's currently used by TSan
+ // to render stack frames, but that should be changed to use
+
[llvm-branch-commits] [clang] d3143a0 - Add `REQUIRES: systemz-registered-target` to test added in #68926 (9a38a72).
Author: Douglas Yung
Date: 2023-11-27T17:35:24-08:00
New Revision: d3143a09acb30f9d3978373d20d67d2c78ce07a9
URL:
https://github.com/llvm/llvm-project/commit/d3143a09acb30f9d3978373d20d67d2c78ce07a9
DIFF:
https://github.com/llvm/llvm-project/commit/d3143a09acb30f9d3978373d20d67d2c78ce07a9.diff
LOG: Add `REQUIRES: systemz-registered-target` to test added in #68926
(9a38a72).
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-ppa2.c
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 21ccd0d7b834c19..0ff4cba5edfb6c6 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -10,6 +10,8 @@
// .byte (i.e., the one for the 3) would, it seems, also match
// the .byte line below for the 34.
+// REQUIRES: systemz-registered-target
+
// RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s
--check-prefix CHECK-C
// CHECK-C:[[PPA2:(.L)|(@@)PPA2]]:
// CHECK-C-NEXT: .byte3{{[[:space:]]*}}.byte 0
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[llvm-branch-commits] [clang] 26de7a9 - Rebase main
Author: Andrés Villegas
Date: 2023-11-28T01:37:12Z
New Revision: 26de7a982d361bf860253a606bf15f460d0689b2
URL:
https://github.com/llvm/llvm-project/commit/26de7a982d361bf860253a606bf15f460d0689b2
DIFF:
https://github.com/llvm/llvm-project/commit/26de7a982d361bf860253a606bf15f460d0689b2.diff
LOG: Rebase main
Created using spr 1.3.4
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-ppa2.c
libcxx/test/std/containers/views/mdspan/MinimalElementType.h
mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
mlir/python/mlir/_mlir_libs/__init__.py
mlir/python/mlir/dialects/python_test.py
mlir/python/mlir/ir.py
mlir/test/python/dialects/python_test.py
mlir/test/python/lib/PythonTestModule.cpp
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 21ccd0d7b834c19..0ff4cba5edfb6c6 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -10,6 +10,8 @@
// .byte (i.e., the one for the 3) would, it seems, also match
// the .byte line below for the 34.
+// REQUIRES: systemz-registered-target
+
// RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s
--check-prefix CHECK-C
// CHECK-C:[[PPA2:(.L)|(@@)PPA2]]:
// CHECK-C-NEXT: .byte3{{[[:space:]]*}}.byte 0
diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
index b1fbd6ed944d179..fe7f0e1f2383790 100644
--- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
+++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
@@ -9,7 +9,8 @@
#ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
#define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
-#include
+#include
+#include
// Idiosyncratic element type for mdspan
// Make sure we don't assume copyable, default constructible, movable etc.
@@ -25,7 +26,7 @@ struct MinimalElementType {
template
struct ElementPool {
constexpr ElementPool() {
-ptr_ = std::allocator().allocate(N);
+ptr_ = std::allocator>().allocate(N);
for (int i = 0; i != N; ++i)
std::construct_at(ptr_ + i, 42);
}
@@ -35,11 +36,11 @@ struct ElementPool {
constexpr ~ElementPool() {
for (int i = 0; i != N; ++i)
std::destroy_at(ptr_ + i);
-std::allocator().deallocate(ptr_, N);
+std::allocator>().deallocate(ptr_, N);
}
private:
- T* ptr_;
+ std::remove_const_t* ptr_;
};
#endif // TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
index f102f0270154264..517c286e0206997 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
@@ -102,12 +102,10 @@ bool isUniqueCOOType(Type tp);
/// the level-rank.
Level getCOOStart(SparseTensorEncodingAttr enc);
-/// Helpers to setup a COO type.
+/// Helper to setup a COO type.
RankedTensorType getCOOFromTypeWithOrdering(RankedTensorType src,
AffineMap ordering, bool ordered);
-RankedTensorType getCOOFromType(RankedTensorType src, bool ordered);
-
/// Returns true iff MLIR operand has any sparse operand.
inline bool hasAnySparseOperand(Operation *op) {
return llvm::any_of(op->getOperands().getTypes(), [](Type t) {
diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index c4a828a20465a80..ff2930008fa093f 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -878,7 +878,7 @@ Level
mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) {
return lvlRank;
}
-// Helpers to setup a COO type.
+// Helper to setup a COO type.
RankedTensorType sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType
rtt,
AffineMap lvlPerm,
bool ordered) {
@@ -911,13 +911,6 @@ RankedTensorType
sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType rtt,
return RankedTensorType::get(src.getDimShape(), src.getElementType(), enc);
}
-RankedTensorType sparse_tensor::getCOOFromType(RankedTensorType src,
- bool ordered) {
- return getCOOFromTypeWithOrdering(
- src, AffineMap::getMultiDimIdentityMap(src.getRank(), src.getContext()),
- ordered);
-}
-
Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) {
if (enc) {
assert(enc.isPermutation() && "Non permutation map not supp
[llvm-branch-commits] [compiler-rt] 8b3944c - [sanitizer_symbolizer] Add initial symbolizer markup support for linux.
Author: Andres Villegas
Date: 2023-11-27T17:36:09-08:00
New Revision: 8b3944ca19645df13b0800336de2bac77ddb60b0
URL:
https://github.com/llvm/llvm-project/commit/8b3944ca19645df13b0800336de2bac77ddb60b0
DIFF:
https://github.com/llvm/llvm-project/commit/8b3944ca19645df13b0800336de2bac77ddb60b0.diff
LOG: [sanitizer_symbolizer] Add initial symbolizer markup support for linux.
This is part of a stack of PRs to add support for symbolizer
markup in linux.
You can check the symbolizer markup specification at:
https://llvm.org/docs/SymbolizerMarkupFormat.html
Reviewers: vitalybuka, PiJoules
Reviewed By: vitalybuka
Pull Request: https://github.com/llvm/llvm-project/pull/73193
Added:
Modified:
compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp
Removed:
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
b/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
index 949bdbd148b6b89..7836347d233add9 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
@@ -275,3 +275,7 @@ COMMON_FLAG(bool, test_only_emulate_no_memorymap, false,
// program.
COMMON_FLAG(bool, test_only_replace_dlopen_main_program, false,
"TEST ONLY replace dlopen(,...) with dlopen(NULL)")
+
+COMMON_FLAG(bool, enable_symbolizer_markup, SANITIZER_FUCHSIA,
+"Use sanitizer symbolizer markup, available on Linux "
+"and always set true for Fuchsia.")
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
index 88f186b9c20c105..748d832ccc211d0 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
@@ -16,6 +16,7 @@
#include "sanitizer_file.h"
#include "sanitizer_flags.h"
#include "sanitizer_fuchsia.h"
+#include "sanitizer_symbolizer_markup.h"
namespace __sanitizer {
@@ -62,6 +63,9 @@ const char *StackTracePrinter::StripFunctionName(const char
*function) {
#if !SANITIZER_SYMBOLIZER_MARKUP
StackTracePrinter *StackTracePrinter::NewStackTracePrinter() {
+ if (common_flags()->enable_symbolizer_markup)
+return new (GetGlobalLowLevelAllocator()) MarkupStackTracePrinter();
+
return new (GetGlobalLowLevelAllocator()) FormattedStackTracePrinter();
}
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
index c364e1e300225b9..1627908185f2009 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp
@@ -45,4 +45,23 @@ void
MarkupStackTracePrinter::RenderFrame(InternalScopedString *buffer,
buffer->AppendF(kFormatFrame, frame_no, address);
}
+bool MarkupSymbolizerTool::SymbolizePC(uptr addr, SymbolizedStack *stack) {
+ char buffer[kFormatFunctionMax];
+ internal_snprintf(buffer, sizeof(buffer), kFormatFunction, addr);
+ stack->info.function = internal_strdup(buffer);
+ return true;
+}
+
+bool MarkupSymbolizerTool::SymbolizeData(uptr addr, DataInfo *info) {
+ info->Clear();
+ info->start = addr;
+ return true;
+}
+
+const char *MarkupSymbolizerTool::Demangle(const char *name) {
+ static char buffer[kFormatDemangleMax];
+ internal_snprintf(buffer, sizeof(buffer), kFormatDemangle, name);
+ return buffer;
+}
+
} // namespace __sanitizer
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
index 7cebe520e9bebb4..07630d0b3bdf417 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.h
@@ -16,6 +16,7 @@
#include "sanitizer_common.h"
#include "sanitizer_stacktrace_printer.h"
#include "sanitizer_symbolizer.h"
+#include "sanitizer_symbolizer_internal.h"
namespace __sanitizer {
@@ -40,6 +41,28 @@ class MarkupStackTracePrinter : public StackTracePrinter {
~MarkupStackTracePrinter() {}
};
+class MarkupSymbolizerTool final : public SymbolizerTool {
+ public:
+ // This is used in some places for suppression checking, which we
+ // don't really support for Fuchsia. It's also used in UBSan to
+ // identify a PC location to a function name, so we always fill in
+ // the function member with a string containing markup around the PC
+ // value.
+ // TODO(mcgrathr): Under SANITIZER_GO, it's currently used by TSan
+ // to render stack frames, but that should be changed to use
+
[clang] 358e1a0 - [𝘀𝗽𝗿] changes introduced through rebase
Author: Andrés Villegas
Date: 2023-11-28T01:37:23Z
New Revision: 358e1a03ab4fe767a332f73d512e6462598c619a
URL:
https://github.com/llvm/llvm-project/commit/358e1a03ab4fe767a332f73d512e6462598c619a
DIFF:
https://github.com/llvm/llvm-project/commit/358e1a03ab4fe767a332f73d512e6462598c619a.diff
LOG: [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-ppa2.c
libcxx/test/std/containers/views/mdspan/MinimalElementType.h
mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
mlir/python/mlir/_mlir_libs/__init__.py
mlir/python/mlir/dialects/python_test.py
mlir/python/mlir/ir.py
mlir/test/python/dialects/python_test.py
mlir/test/python/lib/PythonTestModule.cpp
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 21ccd0d7b834c19..0ff4cba5edfb6c6 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -10,6 +10,8 @@
// .byte (i.e., the one for the 3) would, it seems, also match
// the .byte line below for the 34.
+// REQUIRES: systemz-registered-target
+
// RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s
--check-prefix CHECK-C
// CHECK-C:[[PPA2:(.L)|(@@)PPA2]]:
// CHECK-C-NEXT: .byte3{{[[:space:]]*}}.byte 0
diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
index b1fbd6ed944d179..fe7f0e1f2383790 100644
--- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
+++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
@@ -9,7 +9,8 @@
#ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
#define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
-#include
+#include
+#include
// Idiosyncratic element type for mdspan
// Make sure we don't assume copyable, default constructible, movable etc.
@@ -25,7 +26,7 @@ struct MinimalElementType {
template
struct ElementPool {
constexpr ElementPool() {
-ptr_ = std::allocator().allocate(N);
+ptr_ = std::allocator>().allocate(N);
for (int i = 0; i != N; ++i)
std::construct_at(ptr_ + i, 42);
}
@@ -35,11 +36,11 @@ struct ElementPool {
constexpr ~ElementPool() {
for (int i = 0; i != N; ++i)
std::destroy_at(ptr_ + i);
-std::allocator().deallocate(ptr_, N);
+std::allocator>().deallocate(ptr_, N);
}
private:
- T* ptr_;
+ std::remove_const_t* ptr_;
};
#endif // TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
index f102f0270154264..517c286e0206997 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
@@ -102,12 +102,10 @@ bool isUniqueCOOType(Type tp);
/// the level-rank.
Level getCOOStart(SparseTensorEncodingAttr enc);
-/// Helpers to setup a COO type.
+/// Helper to setup a COO type.
RankedTensorType getCOOFromTypeWithOrdering(RankedTensorType src,
AffineMap ordering, bool ordered);
-RankedTensorType getCOOFromType(RankedTensorType src, bool ordered);
-
/// Returns true iff MLIR operand has any sparse operand.
inline bool hasAnySparseOperand(Operation *op) {
return llvm::any_of(op->getOperands().getTypes(), [](Type t) {
diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index c4a828a20465a80..ff2930008fa093f 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -878,7 +878,7 @@ Level
mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) {
return lvlRank;
}
-// Helpers to setup a COO type.
+// Helper to setup a COO type.
RankedTensorType sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType
rtt,
AffineMap lvlPerm,
bool ordered) {
@@ -911,13 +911,6 @@ RankedTensorType
sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType rtt,
return RankedTensorType::get(src.getDimShape(), src.getElementType(), enc);
}
-RankedTensorType sparse_tensor::getCOOFromType(RankedTensorType src,
- bool ordered) {
- return getCOOFromTypeWithOrdering(
- src, AffineMap::getMultiDimIdentityMap(src.getRank(), src.getContext()),
- ordered);
-}
-
Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) {
if (enc) {
assert(enc.isPermuta
[llvm-branch-commits] [clang] 174f095 - Rebase main
Author: Andrés Villegas
Date: 2023-11-28T01:37:24Z
New Revision: 174f095ec57bee03cb2ee44af9deeabf88ee724d
URL:
https://github.com/llvm/llvm-project/commit/174f095ec57bee03cb2ee44af9deeabf88ee724d
DIFF:
https://github.com/llvm/llvm-project/commit/174f095ec57bee03cb2ee44af9deeabf88ee724d.diff
LOG: Rebase main
Created using spr 1.3.4
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-ppa2.c
libcxx/test/std/containers/views/mdspan/MinimalElementType.h
mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
mlir/python/mlir/_mlir_libs/__init__.py
mlir/python/mlir/dialects/python_test.py
mlir/python/mlir/ir.py
mlir/test/python/dialects/python_test.py
mlir/test/python/lib/PythonTestModule.cpp
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 21ccd0d7b834c19..0ff4cba5edfb6c6 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -10,6 +10,8 @@
// .byte (i.e., the one for the 3) would, it seems, also match
// the .byte line below for the 34.
+// REQUIRES: systemz-registered-target
+
// RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s
--check-prefix CHECK-C
// CHECK-C:[[PPA2:(.L)|(@@)PPA2]]:
// CHECK-C-NEXT: .byte3{{[[:space:]]*}}.byte 0
diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
index b1fbd6ed944d179..fe7f0e1f2383790 100644
--- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
+++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h
@@ -9,7 +9,8 @@
#ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
#define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
-#include
+#include
+#include
// Idiosyncratic element type for mdspan
// Make sure we don't assume copyable, default constructible, movable etc.
@@ -25,7 +26,7 @@ struct MinimalElementType {
template
struct ElementPool {
constexpr ElementPool() {
-ptr_ = std::allocator().allocate(N);
+ptr_ = std::allocator>().allocate(N);
for (int i = 0; i != N; ++i)
std::construct_at(ptr_ + i, 42);
}
@@ -35,11 +36,11 @@ struct ElementPool {
constexpr ~ElementPool() {
for (int i = 0; i != N; ++i)
std::destroy_at(ptr_ + i);
-std::allocator().deallocate(ptr_, N);
+std::allocator>().deallocate(ptr_, N);
}
private:
- T* ptr_;
+ std::remove_const_t* ptr_;
};
#endif // TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H
diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
index f102f0270154264..517c286e0206997 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
@@ -102,12 +102,10 @@ bool isUniqueCOOType(Type tp);
/// the level-rank.
Level getCOOStart(SparseTensorEncodingAttr enc);
-/// Helpers to setup a COO type.
+/// Helper to setup a COO type.
RankedTensorType getCOOFromTypeWithOrdering(RankedTensorType src,
AffineMap ordering, bool ordered);
-RankedTensorType getCOOFromType(RankedTensorType src, bool ordered);
-
/// Returns true iff MLIR operand has any sparse operand.
inline bool hasAnySparseOperand(Operation *op) {
return llvm::any_of(op->getOperands().getTypes(), [](Type t) {
diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index c4a828a20465a80..ff2930008fa093f 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -878,7 +878,7 @@ Level
mlir::sparse_tensor::getCOOStart(SparseTensorEncodingAttr enc) {
return lvlRank;
}
-// Helpers to setup a COO type.
+// Helper to setup a COO type.
RankedTensorType sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType
rtt,
AffineMap lvlPerm,
bool ordered) {
@@ -911,13 +911,6 @@ RankedTensorType
sparse_tensor::getCOOFromTypeWithOrdering(RankedTensorType rtt,
return RankedTensorType::get(src.getDimShape(), src.getElementType(), enc);
}
-RankedTensorType sparse_tensor::getCOOFromType(RankedTensorType src,
- bool ordered) {
- return getCOOFromTypeWithOrdering(
- src, AffineMap::getMultiDimIdentityMap(src.getRank(), src.getContext()),
- ordered);
-}
-
Dimension mlir::sparse_tensor::toDim(SparseTensorEncodingAttr enc, Level l) {
if (enc) {
assert(enc.isPermutation() && "Non permutation map not supp
