[llvm-branch-commits] [libcxx] d4e3c50 - [libc++] Define `namespace views` in its own detail header.
Author: Arthur O'Dwyer
Date: 2022-04-11T11:39:16-04:00
New Revision: d4e3c50b2bda796636bb283ab1a615ff75d9
URL:
https://github.com/llvm/llvm-project/commit/d4e3c50b2bda796636bb283ab1a615ff75d9
DIFF:
https://github.com/llvm/llvm-project/commit/d4e3c50b2bda796636bb283ab1a615ff75d9.diff
LOG: [libc++] Define `namespace views` in its own detail header.
Discovered in the comments on D118748: we would like this namespace
to exist anytime Ranges exists, regardless of whether concepts syntax
is supported. Also, we'd like to fully granularize the header,
which means not putting any loose declarations at the top level.
Differential Revision: https://reviews.llvm.org/D118809
(cherry picked from commit 44cdca37c01a58da94087be8ebd0ee2bd2ba724e)
Added:
libcxx/include/__ranges/views.h
libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp
Modified:
libcxx/include/CMakeLists.txt
libcxx/include/module.modulemap
libcxx/include/ranges
Removed:
diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt
index 7fdf2ff27b344..53700fc9e2c46 100644
--- a/libcxx/include/CMakeLists.txt
+++ b/libcxx/include/CMakeLists.txt
@@ -350,6 +350,7 @@ set(files
__ranges/take_view.h
__ranges/transform_view.h
__ranges/view_interface.h
+ __ranges/views.h
__split_buffer
__std_stream
__string
diff --git a/libcxx/include/__ranges/views.h b/libcxx/include/__ranges/views.h
new file mode 100644
index 0..8cc5ba3d2aca5
--- /dev/null
+++ b/libcxx/include/__ranges/views.h
@@ -0,0 +1,35 @@
+// -*- C++ -*-
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef _LIBCPP___RANGES_VIEWS
+#define _LIBCPP___RANGES_VIEWS
+
+#include <__config>
+
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+# pragma GCC system_header
+#endif
+
+_LIBCPP_BEGIN_NAMESPACE_STD
+
+#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES)
+
+namespace ranges {
+
+namespace views { }
+
+} // namespace ranges
+
+namespace views = ranges::views;
+
+#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES)
+
+_LIBCPP_END_NAMESPACE_STD
+
+#endif // _LIBCPP___RANGES_VIEWS
diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap
index 749c17f8bc08f..9e3643faee095 100644
--- a/libcxx/include/module.modulemap
+++ b/libcxx/include/module.modulemap
@@ -817,6 +817,7 @@ module std [system] {
export functional.__functional.perfect_forward
}
module view_interface { private header
"__ranges/view_interface.h" }
+ module views { private header "__ranges/views.h" }
}
}
module ratio {
diff --git a/libcxx/include/ranges b/libcxx/include/ranges
index 82ad7f4d507f2..9b831160d683a 100644
--- a/libcxx/include/ranges
+++ b/libcxx/include/ranges
@@ -223,6 +223,7 @@ namespace std::ranges {
#include <__ranges/take_view.h>
#include <__ranges/transform_view.h>
#include <__ranges/view_interface.h>
+#include <__ranges/views.h>
#include // Required by the standard.
#include // Required by the standard.
#include // Required by the standard.
@@ -233,14 +234,4 @@ namespace std::ranges {
#pragma GCC system_header
#endif
-#if !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES)
-
-_LIBCPP_BEGIN_NAMESPACE_STD
-
-namespace views = ranges::views;
-
-_LIBCPP_END_NAMESPACE_STD
-
-#endif // !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES)
-
#endif // _LIBCPP_RANGES
diff --git
a/libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp
b/libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp
new file mode 100644
index 0..3b5b617096870
--- /dev/null
+++
b/libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp
@@ -0,0 +1,15 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// REQUIRES: modules-build
+
+// WARNING: This test was generated by 'generate_private_header_tests.py'
+// and should not be edited manually.
+
+// expected-error@*:* {{use of private header from outside its module:
'__ranges/views.h'}}
+#include <__ranges/views.h>
___
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[llvm-branch-commits] [llvm] 8475349 - [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77
Author: Ties Stuij
Date: 2022-04-11T16:10:33-07:00
New Revision: 8475349bd6398edb4b2f13dead70e143b71d2263
URL:
https://github.com/llvm/llvm-project/commit/8475349bd6398edb4b2f13dead70e143b71d2263
DIFF:
https://github.com/llvm/llvm-project/commit/8475349bd6398edb4b2f13dead70e143b71d2263.diff
LOG: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c,
cortex-a77
Reviewed By: amilendra
Differential Revision: https://reviews.llvm.org/D121206
Added:
Modified:
clang/test/Driver/aarch64-ssbs.c
clang/test/Preprocessor/aarch64-target-features.c
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
Removed:
diff --git a/clang/test/Driver/aarch64-ssbs.c
b/clang/test/Driver/aarch64-ssbs.c
index 86c93ae926404..209255405d28d 100644
--- a/clang/test/Driver/aarch64-ssbs.c
+++ b/clang/test/Driver/aarch64-ssbs.c
@@ -1,7 +1,11 @@
// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+ssbs %s
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1 %s
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c %s
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-a77 %s
2>&1 | FileCheck %s
// CHECK: "-target-feature" "+ssbs"
// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+nossbs %s
2>&1 | FileCheck %s --check-prefix=NOSSBS
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c+nossbs %s
2>&1 | FileCheck %s --check-prefix=NOSSBS
// NOSSBS: "-target-feature" "-ssbs"
// RUN: %clang -### -target aarch64-none-none-eabi %s
2>&1 | FileCheck %s --check-prefix=ABSENTSSBS
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 3461af3ecbd20..839fc08031c92 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature"
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature"
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature"
"+fullfp16"
// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature"
"+dotprod" "-target-feature" "+fullfp16"
// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp
b/llvm/lib/Support/AArch64TargetParser.cpp
index cdf7c8ade9aac..bb19e2714be10 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
Features.push_back("+mops");
if (Extensions & AArch64::AEK_PERFMON)
Features.push_back("+perfmon");
+ if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index 9a04b28a8b8f1..70a79864d2c56 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -953,7 +953,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureSSBS];
list A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
FeatureNEON, FeatureF
[llvm-branch-commits] [compiler-rt] 6697c5b - [compiler-rt] [scudo] Use -mcrc32 on x86 when available
Author: Michał Górny
Date: 2022-04-11T16:10:33-07:00
New Revision: 6697c5bc3a1e3e7a3ffbee6680b58338df4b5818
URL:
https://github.com/llvm/llvm-project/commit/6697c5bc3a1e3e7a3ffbee6680b58338df4b5818
DIFF:
https://github.com/llvm/llvm-project/commit/6697c5bc3a1e3e7a3ffbee6680b58338df4b5818.diff
LOG: [compiler-rt] [scudo] Use -mcrc32 on x86 when available
Update the hardware CRC32 logic in scudo to support using `-mcrc32`
instead of `-msse4.2`. The CRC32 intrinsics use the former flag
in the newer compiler versions, e.g. in clang since 12fa608af44a.
With these versions of clang, passing `-msse4.2` is insufficient
to enable the instructions and causes build failures when `-march` does
not enable CRC32 implicitly:
/var/tmp/portage/sys-libs/compiler-rt-sanitizers-14.0.0/work/compiler-rt/lib/scudo/scudo_crc32.cpp:20:10:
error: always_inline function '_mm_crc32_u32' requires target feature 'crc32',
but would be inlined into function 'computeHardwareCRC32' that is compiled
without support for 'crc32'
return CRC32_INTRINSIC(Crc, Data);
^
/var/tmp/portage/sys-libs/compiler-rt-sanitizers-14.0.0/work/compiler-rt/lib/scudo/scudo_crc32.h:27:27:
note: expanded from macro 'CRC32_INTRINSIC'
# define CRC32_INTRINSIC FIRST_32_SECOND_64(_mm_crc32_u32, _mm_crc32_u64)
^
/var/tmp/portage/sys-libs/compiler-rt-sanitizers-14.0.0/work/compiler-rt/lib/scudo/../sanitizer_common/sanitizer_platform.h:132:36:
note: expanded from macro 'FIRST_32_SECOND_64'
# define FIRST_32_SECOND_64(a, b) (a)
^
1 error generated.
For backwards compatibility, use `-mcrc32` when available and fall back
to `-msse4.2`. The `` header remains in use as it still
works and is compatible with GCC, while clang's ``
is not.
Use __builtin_ia32*() rather than _mm_crc32*() when using `-mcrc32`
to preserve compatibility with GCC. _mm_crc32*() are aliases
to __builtin_ia32*() in both compilers but GCC requires `-msse4.2`
for the former, while both use `-mcrc32` for the latter.
Originally reported in https://bugs.gentoo.org/835870.
Differential Revision: https://reviews.llvm.org/D122789
(cherry picked from commit fd1da784ac644492f8ca40064baf3ef360352f55)
Added:
Modified:
compiler-rt/cmake/config-ix.cmake
compiler-rt/lib/scudo/CMakeLists.txt
compiler-rt/lib/scudo/scudo_allocator.cpp
compiler-rt/lib/scudo/scudo_crc32.cpp
compiler-rt/lib/scudo/scudo_crc32.h
compiler-rt/lib/scudo/standalone/CMakeLists.txt
compiler-rt/lib/scudo/standalone/checksum.h
compiler-rt/lib/scudo/standalone/chunk.h
compiler-rt/lib/scudo/standalone/crc32_hw.cpp
Removed:
diff --git a/compiler-rt/cmake/config-ix.cmake
b/compiler-rt/cmake/config-ix.cmake
index 4299a0589a7b7..fc62d5ecc0a94 100644
--- a/compiler-rt/cmake/config-ix.cmake
+++ b/compiler-rt/cmake/config-ix.cmake
@@ -78,6 +78,7 @@ check_cxx_compiler_flag(-fno-profile-generate
COMPILER_RT_HAS_FNO_PROFILE_GENERA
check_cxx_compiler_flag(-fno-profile-instr-generate
COMPILER_RT_HAS_FNO_PROFILE_INSTR_GENERATE_FLAG)
check_cxx_compiler_flag(-fno-profile-instr-use
COMPILER_RT_HAS_FNO_PROFILE_INSTR_USE_FLAG)
check_cxx_compiler_flag(-fno-coverage-mapping
COMPILER_RT_HAS_FNO_COVERAGE_MAPPING_FLAG)
+check_cxx_compiler_flag("-Werror -mcrc32"COMPILER_RT_HAS_MCRC32_FLAG)
check_cxx_compiler_flag("-Werror -msse3" COMPILER_RT_HAS_MSSE3_FLAG)
check_cxx_compiler_flag("-Werror -msse4.2" COMPILER_RT_HAS_MSSE4_2_FLAG)
check_cxx_compiler_flag(--sysroot=. COMPILER_RT_HAS_SYSROOT_FLAG)
diff --git a/compiler-rt/lib/scudo/CMakeLists.txt
b/compiler-rt/lib/scudo/CMakeLists.txt
index 995e853e2a4d7..31a6976960f76 100644
--- a/compiler-rt/lib/scudo/CMakeLists.txt
+++ b/compiler-rt/lib/scudo/CMakeLists.txt
@@ -86,8 +86,11 @@ set(SCUDO_HEADERS
scudo_tsd_shared.inc
scudo_utils.h)
-# Enable the SSE 4.2 instruction set for scudo_crc32.cpp, if available.
-if (COMPILER_RT_HAS_MSSE4_2_FLAG)
+# Enable the necessary instruction set for scudo_crc32.cpp, if available.
+# Newer compiler versions use -mcrc32 rather than -msse4.2.
+if (COMPILER_RT_HAS_MCRC32_FLAG)
+ set_source_files_properties(scudo_crc32.cpp PROPERTIES COMPILE_FLAGS -mcrc32)
+elseif (COMPILER_RT_HAS_MSSE4_2_FLAG)
set_source_files_properties(scudo_crc32.cpp PROPERTIES COMPILE_FLAGS
-msse4.2)
endif()
diff --git a/compiler-rt/lib/scudo/scudo_allocator.cpp
b/compiler-rt/lib/scudo/scudo_allocator.cpp
index 5b6ac8b354934..6a6b577ab0025 100644
--- a/compiler-rt/lib/scudo/scudo_allocator.cpp
+++ b/compiler-rt/lib/scudo/scudo_allocator.cpp
@@ -49,7 +49,7 @@ inline u32 computeCRC32(u32 Crc, uptr Value, uptr *Array,
uptr ArraySize) {
// as opposed to only for scudo_crc32.cpp. This means that other hardware
// specific instructions were likely emitted at other places, and as a
// result there is no reason to not
[llvm-branch-commits] [llvm] c620539 - [AArch64] Fix the upper limit for folded address offsets for COFF
Author: Martin Storsjö
Date: 2022-04-11T16:44:22-07:00
New Revision: c62053979489ccb002efe411c3af059addcb5d7d
URL:
https://github.com/llvm/llvm-project/commit/c62053979489ccb002efe411c3af059addcb5d7d
DIFF:
https://github.com/llvm/llvm-project/commit/c62053979489ccb002efe411c3af059addcb5d7d.diff
LOG: [AArch64] Fix the upper limit for folded address offsets for COFF
In COFF, the immediates in IMAGE_REL_ARM64_PAGEBASE_REL21 relocations
are limited to 21 bit signed, i.e. the offset has to be less than
(1 << 20). The previous limit did intend to cover for this case, but
had missed that the 21 bit field was signed.
This fixes issue https://github.com/llvm/llvm-project/issues/54753.
Differential Revision: https://reviews.llvm.org/D123160
(cherry picked from commit 8d7a17b7c8b7151b8453903db96fc7f45d9b1bae)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
llvm/test/CodeGen/AArch64/fold-global-offsets.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 3008466159bb2..77260c89df115 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17115,13 +17115,14 @@ static SDValue performGlobalAddressCombine(SDNode *N,
SelectionDAG &DAG,
// Check whether folding this offset is legal. It must not go out of bounds
of
// the referenced object to avoid violating the code model, and must be
- // smaller than 2^21 because this is the largest offset expressible in all
- // object formats.
+ // smaller than 2^20 because this is the largest offset expressible in all
+ // object formats. (The IMAGE_REL_ARM64_PAGEBASE_REL21 relocation in COFF
+ // stores an immediate signed 21 bit offset.)
//
// This check also prevents us from folding negative offsets, which will end
// up being treated in the same way as large positive ones. They could also
// cause code model violations, and aren't really common enough to matter.
- if (Offset >= (1 << 21))
+ if (Offset >= (1 << 20))
return SDValue();
const GlobalValue *GV = GN->getGlobal();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index d3f4130d2ba14..3730030aa140e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -162,13 +162,14 @@ static bool matchFoldGlobalOffset(MachineInstr &MI,
MachineRegisterInfo &MRI,
// Check whether folding this offset is legal. It must not go out of bounds
of
// the referenced object to avoid violating the code model, and must be
- // smaller than 2^21 because this is the largest offset expressible in all
- // object formats.
+ // smaller than 2^20 because this is the largest offset expressible in all
+ // object formats. (The IMAGE_REL_ARM64_PAGEBASE_REL21 relocation in COFF
+ // stores an immediate signed 21 bit offset.)
//
// This check also prevents us from folding negative offsets, which will end
// up being treated in the same way as large positive ones. They could also
// cause code model violations, and aren't really common enough to matter.
- if (NewOffset >= (1 << 21))
+ if (NewOffset >= (1 << 20))
return false;
Type *T = GV->getValueType();
diff --git a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
index c57de0d796bda..aa5435c4fd6b3 100644
--- a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
+++ b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
@@ -84,23 +84,23 @@ define [2 x i64] @f4() {
define i64 @f5() {
; CHECK-LABEL: f5:
; CHECK: // %bb.0:
-; CHECK-NEXT:adrp x8, x2+2097144
-; CHECK-NEXT:ldr x0, [x8, :lo12:x2+2097144]
+; CHECK-NEXT:adrp x8, x2+1048568
+; CHECK-NEXT:ldr x0, [x8, :lo12:x2+1048568]
; CHECK-NEXT:ret
;
; GISEL-LABEL: f5:
; GISEL: // %bb.0:
-; GISEL-NEXT:adrp x8, x2+2097144
-; GISEL-NEXT:ldr x0, [x8, :lo12:x2+2097144]
+; GISEL-NEXT:adrp x8, x2+1048568
+; GISEL-NEXT:ldr x0, [x8, :lo12:x2+1048568]
; GISEL-NEXT:ret
- %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2,
i64 0, i64 262143)
+ %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2,
i64 0, i64 131071)
ret i64 %l
}
define i64 @f6() {
; CHECK-LABEL: f6:
; CHECK: // %bb.0:
-; CHECK-NEXT:mov w8, #2097152
+; CHECK-NEXT:mov w8, #1048576
; CHECK-NEXT:adrp x9, x2
; CHECK-NEXT:add x9, x9, :lo12:x2
; CHECK-NEXT:ldr x0, [x9, x8]
@@ -108,12 +108,12 @@ define i64 @f6() {
;
; GISEL-LABEL: f6:
; GISEL: // %bb.0:
-; GISEL-NEXT:mov w8, #2097152
+; GISEL-NEXT:mov w8, #1048576
; GISEL
