Author: Krzysztof Parzyszek
Date: 2022-03-11T12:02:04-08:00
New Revision: 69ba522c58d0cf43097a08087b1b31d6edb46706
URL:
https://github.com/llvm/llvm-project/commit/69ba522c58d0cf43097a08087b1b31d6edb46706
DIFF:
https://github.com/llvm/llvm-project/commit/69ba522c58d0cf43097a08087b1b31d6edb46706.diff
LOG: [Hexagon] Fix crash with shuffle_vector of v128f16
(cherry picked from commit 7403c02f06d4c405215aa97452f1af18dfc02dc0)
Added:
llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll
Modified:
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Removed:
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 0ba75a544c048..14b4f7c56c57b 100755
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -118,9 +118,10 @@ HexagonTargetLowering::initializeHVXLowering() {
setOperationAction(ISD::SPLAT_VECTOR, MVT::v32f32, Legal);
// Vector shuffle is always promoted to ByteV and a bitcast to f16 is
// generated.
-setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV);
-setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW);
-setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV);
+setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW);
+setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV);
+setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW);
+setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV);
// Custom-lower BUILD_VECTOR for vector pairs. The standard (target-
// independent) handling of it would convert it to a load, which is
@@ -780,7 +781,6 @@ HexagonTargetLowering::buildHvxVectorReg(ArrayRef
Values,
SDValue N = HalfV0;
SDValue M = HalfV1;
for (unsigned i = 0; i != NumWords/2; ++i) {
-
// Rotate by element count since last insertion.
if (Words[i] != Words[n] || VecHist[n] <= 1) {
Sn = DAG.getConstant(Rn, dl, MVT::i32);
diff --git a/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll
b/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll
new file mode 100644
index 0..726ee8f061714
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll
@@ -0,0 +1,51 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Test that code is generated for the vector sint_to_fp node. The compiler
+; asserts with a cannot select message if the node is not expanded. When
+; expanded, the generated code is very inefficient, so iwe need to find a more
+; efficient code sequence to generate.
+
+; CHECK: convert_w2sf
+; CHECK: call floorf
+
+target triple = "hexagon"
+
+define dllexport void @f0() #0 {
+b0:
+ br label %b1
+
+b1: ; preds = %b1, %b0
+ %v0 = phi i32 [ 0, %b0 ], [ %v17, %b1 ]
+ %v1 = mul nsw i32 %v0, 2
+ %v2 = add nsw i32 undef, %v1
+ %v3 = insertelement <64 x i32> undef, i32 %v2, i32 0
+ %v4 = shufflevector <64 x i32> %v3, <64 x i32> undef, <64 x i32>
zeroinitializer
+ %v5 = add nsw <64 x i32> %v4,
+ %v6 = sitofp <64 x i32> %v5 to <64 x float>
+ %v7 = fmul <64 x float> %v6,
+ %v8 = fsub <64 x float> %v7, zeroinitializer
+ %v9 = call <64 x float> @llvm.floor.v64f32(<64 x float> %v8)
+ %v10 = fsub <64 x float> zeroinitializer, %v9
+ %v11 = fptrunc <64 x float> %v10 to <64 x half>
+ %v12 = call <64 x half> @llvm.fmuladd.v64f16(<64 x half> %v11, <64 x half>
zeroinitializer, <64 x half> zeroinitializer)
+ %v13 = fsub <64 x half> %v12, zeroinitializer
+ %v14 = call <64 x half> @llvm.fmuladd.v64f16(<64 x half> zeroinitializer,
<64 x half> %v13, <64 x half> zeroinitializer)
+ %v15 = shufflevector <64 x half> %v14, <64 x half> undef, <128 x i32>
+ %v16 = shufflevector <128 x half> %v15, <128 x half> undef, <64 x i32>
+ call void @llvm.masked.store.v64f16.p0v64f16(<64 x half> %v16, <64 x half>*
undef, i32 64, <64 x i1> )
+ %v17 = add nsw i32 %v0, 1
+ br label %b1
+}
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare <64 x float> @llvm.floor.v64f32(<64 x float>) #1
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare <64 x half> @llvm.fmuladd.v64f16(<64 x half>, <64 x half>, <64 x
half>) #1
+
+; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+declare void @llvm.masked.store.v64f16.p0v64f16(<64 x half>, <64 x half>*, i32
immarg, <64 x i1>) #2
+
+attributes #0 = { "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }
+attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
+attributes #2 = { argmemonly nofree nosync nounwind willreturn writeonly }
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