[llvm-branch-commits] [llvm] 9d54fe2 - [docs] Add RISC-V release notes for LLVM 14
Author: Alex Bradbury Date: 2022-03-07T10:58:20Z New Revision: 9d54fe21c67fdb76bfd95c329a31bda2cb91c520 URL: https://github.com/llvm/llvm-project/commit/9d54fe21c67fdb76bfd95c329a31bda2cb91c520 DIFF: https://github.com/llvm/llvm-project/commit/9d54fe21c67fdb76bfd95c329a31bda2cb91c520.diff LOG: [docs] Add RISC-V release notes for LLVM 14 Differential Revision: https://reviews.llvm.org/D120047 Added: Modified: llvm/docs/ReleaseNotes.rst Removed: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 28282c54e7390..e8934f79181a7 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -135,6 +135,30 @@ AIX Support/improvements: * AIX 64-bit code generation now uses fast-isel for O0. * Added DWARF support for 32-bit XCOFF. +Changes to the RISC-V Target + + +* Codegen improvements for RV64 around the selection of addw/subw/mulw/slliw + instructions and removal of redundant sext.w instructions (using the new + RISCVSExtWRemoval pass). +* The various RISC-V vector extensions were updated to version 1.0 and are no + longer experimental. +* The Zba, Zbb, Zbc, and Zbs bit-manipulation extensions were updated to + version 1.0 and are no longer experimental. +* Added MC layer support for the ratified scalar cryptography extensions. +* The Zfh and Zfhmin extensions for half-precision floating point were updated + to version 1.0 and are no longer experimental. +* Added support for the ``.insn`` directive. +* Various improvements to immediate materialisation, including when + bit-manipulation extensions are enabled. Additionally, the constant pool is + now used for large integers. +* Added support for constrained FP intrinsics for scalar types. +* Added support for CSRs introduced in the Sscofpmf, Smstateen, and Sstc + extensions. +* The experimental 'Zbproposedc' extension was removed, as was the 'B' + extension (including all bit-manipulation sub-extensions). Individual 'Zb*' + extensions should be used instead. + Changes to the X86 Target - ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] f6a4df3 - [WebAssembly] Covert llvm/test/MC/WebAssembly/reloc-code.ll to asm. NFC
Author: Sam Clegg
Date: 2022-03-07T14:30:23-08:00
New Revision: f6a4df3a0a3d570c65231187a730595b1cf8dc71
URL:
https://github.com/llvm/llvm-project/commit/f6a4df3a0a3d570c65231187a730595b1cf8dc71
DIFF:
https://github.com/llvm/llvm-project/commit/f6a4df3a0a3d570c65231187a730595b1cf8dc71.diff
LOG: [WebAssembly] Covert llvm/test/MC/WebAssembly/reloc-code.ll to asm. NFC
Also increase coverage of call_indirect via explict function table
(enabled when reference types is enabled) in
llvm/test/CodeGen/WebAssembly/call-indirect.ll (I believe this
was an oversight that it was not added in https://reviews.llvm.org/D90948)
Differential Revision: https://reviews.llvm.org/D120521
(cherry picked from commit db7b1af8ef8f59600cbb6e529164acdbe4c8f0a2)
Added:
llvm/test/MC/WebAssembly/reloc-code.s
Modified:
llvm/test/CodeGen/WebAssembly/call-indirect.ll
Removed:
llvm/test/MC/WebAssembly/reloc-code.ll
diff --git a/llvm/test/CodeGen/WebAssembly/call-indirect.ll
b/llvm/test/CodeGen/WebAssembly/call-indirect.ll
index 7a174318d4732..d5bb749d8a1d7 100644
--- a/llvm/test/CodeGen/WebAssembly/call-indirect.ll
+++ b/llvm/test/CodeGen/WebAssembly/call-indirect.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -asm-verbose=false -O2 | FileCheck --check-prefix=CHECK %s
+; RUN: llc < %s -asm-verbose=false -O2 | FileCheck
--check-prefixes=CHECK,NOREF %s
+; RUN: llc < %s -asm-verbose=false -mattr=+reference-types -O2 | FileCheck
--check-prefixes=CHECK,REF %s
; RUN: llc < %s -asm-verbose=false -O2 --filetype=obj | obj2yaml | FileCheck
--check-prefix=OBJ %s
; Test that compilation units with call_indirect but without any
@@ -9,7 +10,8 @@ target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: call_indirect_void:
; CHECK-NEXT: .functype call_indirect_void (i32) -> ()
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: call_indirect () -> ()
+; REF:call_indirect __indirect_function_table, () -> ()
+; NOREF: call_indirect () -> ()
; CHECK-NEXT: end_function
define void @call_indirect_void(void ()* %callee) {
call void %callee()
diff --git a/llvm/test/MC/WebAssembly/reloc-code.ll
b/llvm/test/MC/WebAssembly/reloc-code.ll
deleted file mode 100644
index e80fbcf80cd35..0
--- a/llvm/test/MC/WebAssembly/reloc-code.ll
+++ /dev/null
@@ -1,110 +0,0 @@
-; RUN: llc -filetype=obj %s -o - | llvm-readobj -r --expand-relocs - |
FileCheck %s
-; RUN: llc -filetype=obj -mattr=+reference-types %s -o - | llvm-readobj -r
--expand-relocs - | FileCheck --check-prefix=REF %s
-
-target triple = "wasm32-unknown-unknown"
-
-; Pointers to functions of two
diff erent types
-@a = global i64 ()* inttoptr (i64 5 to i64 ()*), align 8
-@b = global i32 ()* inttoptr (i32 7 to i32 ()*), align 8
-
-; External functions
-declare i32 @c()
-declare i32 @d()
-
-define i32 @f1() {
-entry:
-%aa = load i64 ()*, i64 ()** @a, align 8
-%bb = load i32 ()*, i32 ()** @b, align 8
-%tmp1 = call i64 %aa()
-%tmp2 = call i32 %bb()
-%tmp3 = call i32 @c()
-%tmp4 = call i32 @d()
-ret i32 %tmp2
-}
-
-
-; CHECK: Format: WASM
-; CHECK: Relocations [
-; CHECK-NEXT: Section (5) CODE {
-; CHECK-NEXT: Relocation {
-; CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3)
-; CHECK-NEXT: Offset: 0x9
-; CHECK-NEXT: Symbol: b
-; CHECK-NEXT: Addend: 0
-; CHECK-NEXT: }
-; CHECK-NEXT: Relocation {
-; CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3)
-; CHECK-NEXT: Offset: 0x14
-; CHECK-NEXT: Symbol: a
-; CHECK-NEXT: Addend: 0
-; CHECK-NEXT: }
-; CHECK-NEXT: Relocation {
-; CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6)
-; CHECK-NEXT: Offset: 0x1A
-; CHECK-NEXT: Index: 0x1
-; CHECK-NEXT: }
-; CHECK-NEXT: Relocation {
-; CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6)
-; CHECK-NEXT: Offset: 0x24
-; CHECK-NEXT: Index: 0x0
-; CHECK-NEXT: }
-; CHECK-NEXT: Relocation {
-; CHECK-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0)
-; CHECK-NEXT: Offset: 0x2D
-; CHECK-NEXT: Symbol: c
-; CHECK-NEXT: }
-; CHECK-NEXT: Relocation {
-; CHECK-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0)
-; CHECK-NEXT: Offset: 0x34
-; CHECK-NEXT: Symbol: d
-; CHECK-NEXT: }
-; CHECK-NEXT: }
-; CHECK-NEXT: ]
-
-; REF: Format: WASM
-; REF: Relocations [
-; REF-NEXT: Section (5) CODE {
-; REF-NEXT: Relocation {
-; REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3)
-; REF-NEXT: Offset: 0x9
-; REF-NEXT: Symbol: b
-; REF-NEXT: Addend: 0
-; REF-NEXT: }
-; REF-NEXT: Relocation {
-; REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3)
-; REF-NEXT: Offset: 0x14
-; REF-NEXT: Symbol: a
-; REF-NEXT: Addend: 0
-; REF-NEXT: }
-; REF-NEXT: Relocation {
-; REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6)
-; REF-NEXT: Offset: 0x1A
-; REF-NEXT: Index: 0x1
-; REF-NEXT: }
-; REF-NEXT: Relocation {
-; REF-NEXT:
[llvm-branch-commits] [lld] e6d2aa9 - [MC][WebAssembly] Fix crash when relocation addend underlows U32
Author: Sam Clegg
Date: 2022-03-07T14:30:23-08:00
New Revision: e6d2aa9b0f131a141166d1d90560f1a2d1d9ec5c
URL:
https://github.com/llvm/llvm-project/commit/e6d2aa9b0f131a141166d1d90560f1a2d1d9ec5c
DIFF:
https://github.com/llvm/llvm-project/commit/e6d2aa9b0f131a141166d1d90560f1a2d1d9ec5c.diff
LOG: [MC][WebAssembly] Fix crash when relocation addend underlows U32
For the object file writer we need to allow the underflow (ar write
zero), but for the final linker output we should probably generate an
error (I've left that as a TODO for now).
Fixes: https://github.com/llvm/llvm-project/issues/54012
Differential Revision: https://reviews.llvm.org/D120522
(cherry picked from commit 4c75521ce0b1ac55fba1a91ef5156fc811f5dfcb)
Added:
Modified:
lld/test/wasm/reloc-addend.s
lld/wasm/InputChunks.cpp
lld/wasm/InputFiles.cpp
lld/wasm/InputFiles.h
llvm/lib/MC/WasmObjectWriter.cpp
llvm/test/MC/WebAssembly/reloc-code.s
Removed:
diff --git a/lld/test/wasm/reloc-addend.s b/lld/test/wasm/reloc-addend.s
index acd57ce357a72..4b23ed1120faa 100644
--- a/lld/test/wasm/reloc-addend.s
+++ b/lld/test/wasm/reloc-addend.s
@@ -1,6 +1,7 @@
# RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown -o %t.o %s
# RUN: wasm-ld -r -o %t.wasm %t.o
# RUN: obj2yaml %t.wasm | FileCheck %s
+# RUN: llvm-objdump --disassemble-symbols=_start --no-show-raw-insn
--no-leading-addr %t.wasm | FileCheck %s --check-prefixes DIS
.hidden foo
.hidden bar
@@ -30,6 +31,39 @@ negative_addend:
.int32 foo-16
.size negative_addend, 4
+.globl _start
+.section .text,"",@
+_start:
+ .functype _start () -> ()
+ i32.const 0
+ i32.load foo + 10
+ drop
+ i32.const 0
+ i32.load foo - 10
+ drop
+ i32.const 0
+ # This will underflow because i32.load (and the
+ # corresponding relocation type) take an unsgiend (U32)
+ # immediate.
+ i32.load foo - 2048
+ drop
+ end_function
+
+# CHECK: - Type:CODE
+# CHECK-NEXT:Relocations:
+# CHECK-NEXT: - Type:R_WASM_MEMORY_ADDR_LEB
+# CHECK-NEXT:Index: 0
+# CHECK-NEXT:Offset: 0x7
+# CHECK-NEXT:Addend: 10
+# CHECK-NEXT: - Type:R_WASM_MEMORY_ADDR_LEB
+# CHECK-NEXT:Index: 0
+# CHECK-NEXT:Offset: 0x11
+# CHECK-NEXT:Addend: -10
+# CHECK-NEXT: - Type:R_WASM_MEMORY_ADDR_LEB
+# CHECK-NEXT:Index: 0
+# CHECK-NEXT:Offset: 0x1B
+# CHECK-NEXT:Addend: -2048
+
# CHECK:- Type:DATA
# CHECK-NEXT: Relocations:
# CHECK-NEXT: - Type:R_WASM_MEMORY_ADDR_I32
@@ -40,3 +74,17 @@ negative_addend:
# CHECK-NEXT: Index: 0
# CHECK-NEXT: Offset: 0xF
# CHECK-NEXT: Addend: -16
+
+# DIS: <_start>:
+# DIS-EMPTY:
+# DIS-NEXT:i32.const 0
+# DIS-NEXT:i32.load 26
+# DIS-NEXT:drop
+# DIS-NEXT:i32.const 0
+# DIS-NEXT:i32.load 6
+# DIS-NEXT:drop
+# DIS-NEXT:i32.const 0
+# TODO(sbc): We should probably error here rather than allowing u32 to wrap
+# DIS-NEXT:i32.load 4294965264
+# DIS-NEXT:drop
+# DIS-NEXT:end
diff --git a/lld/wasm/InputChunks.cpp b/lld/wasm/InputChunks.cpp
index 7973dce6827e2..242378504c3b8 100644
--- a/lld/wasm/InputChunks.cpp
+++ b/lld/wasm/InputChunks.cpp
@@ -116,7 +116,10 @@ void InputChunk::relocate(uint8_t *buf) const {
LLVM_DEBUG(dbgs() << " sym=" <<
file->getSymbols()[rel.Index]->getName());
LLVM_DEBUG(dbgs() << " addend=" << rel.Addend << " index=" << rel.Index
<< " offset=" << rel.Offset << "\n");
-auto value = file->calcNewValue(rel, tombstone, this);
+// TODO(sbc): Check that the value is within the range of the
+// relocation type below. Most likely we must error out here
+// if its not with range.
+uint64_t value = file->calcNewValue(rel, tombstone, this);
switch (rel.Type) {
case R_WASM_TYPE_INDEX_LEB:
@@ -125,7 +128,7 @@ void InputChunk::relocate(uint8_t *buf) const {
case R_WASM_TAG_INDEX_LEB:
case R_WASM_MEMORY_ADDR_LEB:
case R_WASM_TABLE_NUMBER_LEB:
- encodeULEB128(value, loc, 5);
+ encodeULEB128(static_cast(value), loc, 5);
break;
case R_WASM_MEMORY_ADDR_LEB64:
encodeULEB128(value, loc, 10);
diff --git a/lld/wasm/InputFiles.cpp b/lld/wasm/InputFiles.cpp
index 0758bb922a3bc..1e69f16cc5f97 100644
--- a/lld/wasm/InputFiles.cpp
+++ b/lld/wasm/InputFiles.cpp
@@ -106,7 +106,7 @@ uint32_t ObjFile::calcNewIndex(const WasmRelocation &reloc)
const {
// Relocations can contain addend for combined sections. This function takes a
// relocation and returns updated addend by offset in the output section.
-uint64_t ObjFile::calcNewAddend(const WasmRelocation &reloc) const {
+int64_t ObjFile::calcNewAddend(const WasmRelocatio
[llvm-branch-commits] [lld] 43b4544 - [LLD] [COFF] Order .debug_* sections at the end, to avoid leaving gaps if stripped
Author: Martin Storsjö
Date: 2022-03-07T14:38:09-08:00
New Revision: 43b4544023b73d334b5f60edaf7e1dcce4c75d3f
URL:
https://github.com/llvm/llvm-project/commit/43b4544023b73d334b5f60edaf7e1dcce4c75d3f
DIFF:
https://github.com/llvm/llvm-project/commit/43b4544023b73d334b5f60edaf7e1dcce4c75d3f.diff
LOG: [LLD] [COFF] Order .debug_* sections at the end, to avoid leaving gaps if
stripped
So far, we sort all discardable sections at the end, with only some
extra logic to make sure that the .reloc section is at the start
of that group of sections. But if there are other discardable
sections, other than .reloc, they must also be ordered before
.debug_* sections, to avoid leaving gaps if the executable is
stripped.
(Stripping executables doesn't remove all discardable sections,
only the ones named .debug_*).
Rust binaries seem to include a .rmeta section, which is marked
discardable. This fixes stripping such binaries if built with
dwarf debug info included.
This fixes issues observed in MSYS2 in
https://github.com/msys2/MINGW-packages/pull/10555.
Differential Revision: https://reviews.llvm.org/D120805
(cherry picked from commit 4c3b74b7f5d6192d1731c88f1aeb396bc51d4949)
Added:
Modified:
lld/COFF/Writer.cpp
lld/test/COFF/sort-debug.test
Removed:
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index 12db942f1db55..1ed2327ea630d 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -926,8 +926,14 @@ void Writer::createSections() {
// Move DISCARDABLE (or non-memory-mapped) sections to the end of file
// because the loader cannot handle holes. Stripping can remove other
// discardable ones than .reloc, which is first of them (created early).
-if (s->header.Characteristics & IMAGE_SCN_MEM_DISCARDABLE)
+if (s->header.Characteristics & IMAGE_SCN_MEM_DISCARDABLE) {
+ // Move discardable sections named .debug_ to the end, after other
+ // discardable sections. Stripping only removes the sections named
+ // .debug_* - thus try to avoid leaving holes after stripping.
+ if (s->name.startswith(".debug_"))
+return 3;
return 2;
+}
// .rsrc should come at the end of the non-discardable sections because its
// size may change by the Win32 UpdateResources() function, causing
// subsequent sections to move (see https://crbug.com/827082).
diff --git a/lld/test/COFF/sort-debug.test b/lld/test/COFF/sort-debug.test
index d8fd7ae605645..bbe2ecd0efd8d 100644
--- a/lld/test/COFF/sort-debug.test
+++ b/lld/test/COFF/sort-debug.test
@@ -10,6 +10,7 @@
# CHECK: Name: .text
# CHECK: Name: .reloc
+# CHECK: Name: .rmeta
# CHECK: Name: .debug_abbrev
# CHECK: Name: .debug_info
# CHECK: Name: .debug_line
@@ -18,6 +19,7 @@
# NODEBUG: Name: .text
# NODEBUG: Name: .reloc
+# NODEBUG: Name: .rmeta
# NODEBUG-NOT: Name: .debug_abbrev
# NODEBUG-NOT: Name: .debug_info
# NODEBUG-NOT: Name: .debug_line
@@ -183,6 +185,10 @@ sections:
- VirtualAddress: 43
SymbolName: .text
Type:IMAGE_REL_I386_DIR32
+ - Name:.rmeta
+Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA,
IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ]
+Alignment: 1
+SectionData: 00112233
symbols:
- Name:.text
Value: 0
___
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[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] c832edf - [WebAssembly] Add new target feature in support of 'extended-const' proposal
Author: Sam Clegg
Date: 2022-03-07T16:45:42-08:00
New Revision: c832edfd3fbccfac6d5212d6495f0dde851dbdde
URL:
https://github.com/llvm/llvm-project/commit/c832edfd3fbccfac6d5212d6495f0dde851dbdde
DIFF:
https://github.com/llvm/llvm-project/commit/c832edfd3fbccfac6d5212d6495f0dde851dbdde.diff
LOG: [WebAssembly] Add new target feature in support of 'extended-const'
proposal
We don't yet do anything when this feature is enabled, this change
just lays the ground work by accepting that there is such a feature.
See https://github.com/WebAssembly/extended-const
Differential Revision: https://reviews.llvm.org/D121151
Added:
Modified:
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/WebAssembly.cpp
clang/lib/Basic/Targets/WebAssembly.h
clang/test/Preprocessor/wasm-target-features.c
llvm/lib/Target/WebAssembly/WebAssembly.td
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
Removed:
diff --git a/clang/docs/ClangCommandLineReference.rst
b/clang/docs/ClangCommandLineReference.rst
index 77c20d3646500..6815dca1f1529 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -3629,6 +3629,8 @@ WebAssembly
.. option:: -mtail-call, -mno-tail-call
+.. option:: -mextended-const, -mno-extended-const
+
WebAssembly Driver
--
.. option:: -mexec-model=
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 24e2069711be5..06802ae424f7a 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3468,6 +3468,8 @@ def mtail_call : Flag<["-"], "mtail-call">,
Group;
def mno_tail_call : Flag<["-"], "mno-tail-call">, Group;
def mreference_types : Flag<["-"], "mreference-types">,
Group;
def mno_reference_types : Flag<["-"], "mno-reference-types">,
Group;
+def mextended_const : Flag<["-"], "mextended-const">,
Group;
+def mno_extended_const : Flag<["-"], "mno-extended-const">,
Group;
def mexec_model_EQ : Joined<["-"], "mexec-model=">,
Group,
Values<"command,reactor">,
HelpText<"Execution model (WebAssembly only)">;
diff --git a/clang/lib/Basic/Targets/WebAssembly.cpp
b/clang/lib/Basic/Targets/WebAssembly.cpp
index 18ff109bf2d39..b3b6c2be5c134 100644
--- a/clang/lib/Basic/Targets/WebAssembly.cpp
+++ b/clang/lib/Basic/Targets/WebAssembly.cpp
@@ -56,6 +56,7 @@ bool WebAssemblyTargetInfo::hasFeature(StringRef Feature)
const {
.Case("multivalue", HasMultivalue)
.Case("tail-call", HasTailCall)
.Case("reference-types", HasReferenceTypes)
+ .Case("extended-const", HasExtendedConst)
.Default(false);
}
@@ -93,6 +94,8 @@ void WebAssemblyTargetInfo::getTargetDefines(const
LangOptions &Opts,
Builder.defineMacro("__wasm_tail_call__");
if (HasReferenceTypes)
Builder.defineMacro("__wasm_reference_types__");
+ if (HasExtendedConst)
+Builder.defineMacro("__wasm_extended_const__");
}
void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap &Features,
@@ -240,6 +243,14 @@ bool WebAssemblyTargetInfo::handleTargetFeatures(
HasReferenceTypes = false;
continue;
}
+if (Feature == "+extended-const") {
+ HasExtendedConst = true;
+ continue;
+}
+if (Feature == "-extended-const") {
+ HasExtendedConst = false;
+ continue;
+}
Diags.Report(diag::err_opt_not_valid_with_opt)
<< Feature << "-target-feature";
diff --git a/clang/lib/Basic/Targets/WebAssembly.h
b/clang/lib/Basic/Targets/WebAssembly.h
index 075486990558b..63418869d10ac 100644
--- a/clang/lib/Basic/Targets/WebAssembly.h
+++ b/clang/lib/Basic/Targets/WebAssembly.h
@@ -39,6 +39,7 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public
TargetInfo {
bool HasMultivalue = false;
bool HasTailCall = false;
bool HasReferenceTypes = false;
+ bool HasExtendedConst = false;
std::string ABI;
diff --git a/clang/test/Preprocessor/wasm-target-features.c
b/clang/test/Preprocessor/wasm-target-features.c
index 3c743142a3e38..c05b26a0c2278 100644
--- a/clang/test/Preprocessor/wasm-target-features.c
+++ b/clang/test/Preprocessor/wasm-target-features.c
@@ -105,6 +105,15 @@
// RUN: | FileCheck %s -check-prefix=REFERENCE-TYPES
//
// REFERENCE-TYPES:#define __wasm_reference_types__ 1{{$}}
+//
+// RUN: %clang -E -dM %s -o - 2>&1 \
+// RUN: -target wasm32-unknown-unknown -mextended-const \
+// RUN: | FileCheck %s -check-prefix=EXTENDED-CONST
+// RUN: %clang -E -dM %s -o - 2>&1 \
+// RUN: -target wasm64-unknown-unknown -mextended-const \
+// RUN: | FileCheck %s -check-prefix=EXTENDED-CONST
+//
+// EXTENDED-CONST:#define __wasm_extended_const__ 1{{$}}
// RUN: %clang -E -dM %s -o - 2>&1 \
// RUN: -target wasm
[llvm-branch-commits] [llvm] 1e4fd59 - [CodeGen] Add test for PR53990 (NFC)
Author: Nikita Popov
Date: 2022-03-07T21:02:28-08:00
New Revision: 1e4fd59253c60c78a222f85c42501302142a3586
URL:
https://github.com/llvm/llvm-project/commit/1e4fd59253c60c78a222f85c42501302142a3586
DIFF:
https://github.com/llvm/llvm-project/commit/1e4fd59253c60c78a222f85c42501302142a3586.diff
LOG: [CodeGen] Add test for PR53990 (NFC)
(cherry picked from commit e075bf6bdbcaa2652891ebff3e7ce9ca00cadd8a)
Added:
llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll
b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll
new file mode 100644
index 0..3d7ff6cbe676a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+
+declare void @clobber()
+
+define void @test(i1 %c, i64* %p, i64* noalias %p2) nounwind {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:pushq %rbp
+; CHECK-NEXT:pushq %r15
+; CHECK-NEXT:pushq %r14
+; CHECK-NEXT:pushq %rbx
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:movq %rdx, %rbx
+; CHECK-NEXT:movq %rsi, %r14
+; CHECK-NEXT:movl %edi, %r15d
+; CHECK-NEXT:xorl %eax, %eax
+; CHECK-NEXT:jmpq *.LJTI0_0(,%rax,8)
+; CHECK-NEXT: .LBB0_1: # %split.3
+; CHECK-NEXT:movq (%r14), %rbp
+; CHECK-NEXT:testb $1, %r15b
+; CHECK-NEXT:je .LBB0_3
+; CHECK-NEXT: # %bb.2: # %clobber
+; CHECK-NEXT:callq clobber@PLT
+; CHECK-NEXT: .LBB0_3: # %sink
+; CHECK-NEXT:movq %rbp, (%rbx)
+; CHECK-NEXT: .LBB0_4: # %latch
+; CHECK-NEXT:# =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:xorl %eax, %eax
+; CHECK-NEXT:jmpq *.LJTI0_0(,%rax,8)
+entry:
+ %val = load i64, i64* %p, align 8
+ br label %loop
+
+loop:
+ switch i8 undef, label %unreachable [
+i8 0, label %latch
+i8 1, label %split.1
+i8 2, label %split.2
+i8 3, label %split.3
+ ]
+
+unreachable:
+ unreachable
+
+split.3:
+ br i1 %c, label %clobber, label %sink
+
+split.1:
+ br label %latch
+
+split.2:
+ br label %latch
+
+clobber:
+ call void @clobber()
+ br label %sink
+
+sink:
+ store i64 %val, i64* %p2, align 8
+ br label %latch
+
+latch:
+ %phi = phi i64 [ 0, %sink ], [ 0, %split.2 ], [ 1, %split.1 ], [ 0, %loop ]
+ %phi.live = add i64 %phi, 0
+ br label %loop
+}
___
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[llvm-branch-commits] [llvm] 6755510 - [MachineSink] Disable if there are any irreducible cycles
Author: Nikita Popov
Date: 2022-03-07T21:02:28-08:00
New Revision: 67555104d23aaef9b4ce4995ccb98b2ba9aff07d
URL:
https://github.com/llvm/llvm-project/commit/67555104d23aaef9b4ce4995ccb98b2ba9aff07d
DIFF:
https://github.com/llvm/llvm-project/commit/67555104d23aaef9b4ce4995ccb98b2ba9aff07d.diff
LOG: [MachineSink] Disable if there are any irreducible cycles
This is an alternative to D120330, which disables MachineSink for
functions with irreducible cycles entirely. This avoids both the
correctness problem, and ensures we don't perform non-profitable
sinks into cycles. At the same time, it may also disable
profitable sinks in the same function. This can be made more
precise by using MachineCycleInfo in the future.
Fixes https://github.com/llvm/llvm-project/issues/53990.
Differential Revision: https://reviews.llvm.org/D120800
(cherry picked from commit 6fde0439512580df793f3f48f95757b47de40d2b)
Added:
Modified:
llvm/lib/CodeGen/MachineSink.cpp
llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
llvm/test/CodeGen/X86/pr38795.ll
llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
Removed:
diff --git a/llvm/lib/CodeGen/MachineSink.cpp
b/llvm/lib/CodeGen/MachineSink.cpp
index 0dbbc218e9464..bc03776bde19d 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -18,12 +18,14 @@
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/PointerIntPair.h"
+#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/CFG.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
@@ -429,6 +431,16 @@ bool MachineSinking::runOnMachineFunction(MachineFunction
&MF) {
AA = &getAnalysis().getAAResults();
RegClassInfo.runOnMachineFunction(MF);
+ // MachineSink currently uses MachineLoopInfo, which only recognizes natural
+ // loops. As such, we could sink instructions into irreducible cycles, which
+ // would be non-profitable.
+ // WARNING: The current implementation of hasStoreBetween() is incorrect for
+ // sinking into irreducible cycles (PR53990), this bailout is currently
+ // necessary for correctness, not just profitability.
+ ReversePostOrderTraversal RPOT(&*MF.begin());
+ if (containsIrreducibleCFG(RPOT, *LI))
+return false;
+
bool EverMadeChange = false;
while (true) {
diff --git a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
index 024b6c608abab..f93e181d157c7 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
@@ -24,7 +24,7 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT:movq %r15, %rdi
; CHECK-NEXT:callq l
; CHECK-NEXT:testl %eax, %eax
-; CHECK-NEXT:jne .LBB0_10
+; CHECK-NEXT:jne .LBB0_9
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT:movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; CHECK-NEXT:cmpl $0, e(%rip)
@@ -44,21 +44,19 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT:callq i
; CHECK-NEXT:movl %eax, %ebp
; CHECK-NEXT:orl %r14d, %ebp
-; CHECK-NEXT:testl %r13d, %r13d
-; CHECK-NEXT:je .LBB0_6
-; CHECK-NEXT: # %bb.5:
; CHECK-NEXT:andl $4, %ebx
-; CHECK-NEXT:jmp .LBB0_3
-; CHECK-NEXT: .LBB0_6: # %if.end12
+; CHECK-NEXT:testl %r13d, %r13d
+; CHECK-NEXT:jne .LBB0_3
+; CHECK-NEXT: # %bb.5: # %if.end12
; CHECK-NEXT:testl %ebp, %ebp
-; CHECK-NEXT:je .LBB0_9
-; CHECK-NEXT: # %bb.7: # %if.then14
+; CHECK-NEXT:je .LBB0_8
+; CHECK-NEXT: # %bb.6: # %if.then14
; CHECK-NEXT:movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; CHECK-NEXT:#APP
; CHECK-NEXT:#NO_APP
-; CHECK-NEXT:jmp .LBB0_10
+; CHECK-NEXT:jmp .LBB0_9
; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: # %bb.8: # %if.then20.critedge
+; CHECK-NEXT: # %bb.7: # %if.then20.critedge
; CHECK-NEXT:movl j(%rip), %edi
; CHECK-NEXT:movslq %eax, %rcx
; CHECK-NEXT:movl $1, %esi
@@ -71,9 +69,9 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT:popq %r15
; CHECK-NEXT:popq %rbp
; CHECK-NEXT:jmp k # TAILCALL
-; CHECK-NEXT: .LBB0_9: # %if.else
+; CHECK-NEXT: .LBB0_8: # %if.else
; CHECK-NEXT:incq 0
-; CHECK-NEXT: .LBB0_10: # %cleanup
+; CHECK-NEXT: .LBB0_9: # %cleanup
; CHECK-NEXT:addq $8, %rsp
; CHECK-NEXT:popq %rbx
; CHECK-NEXT:popq %r12
diff --git a/llvm/test/CodeGen/X86/pr38795.ll
b/llvm/test/CodeGen/X86/pr38795
[llvm-branch-commits] [llvm] 36bf1a9 - [NFC][PhaseOrdering] Precommit tests from D119965
Author: William S. Moses
Date: 2022-03-07T21:02:28-08:00
New Revision: 36bf1a9e628dd086537ec14db3fcf4feed1393e9
URL:
https://github.com/llvm/llvm-project/commit/36bf1a9e628dd086537ec14db3fcf4feed1393e9
DIFF:
https://github.com/llvm/llvm-project/commit/36bf1a9e628dd086537ec14db3fcf4feed1393e9.diff
LOG: [NFC][PhaseOrdering] Precommit tests from D119965
(cherry picked from commit 73ee82871e60ab87af7a722ef089ede17e97ea9f)
Added:
llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
Modified:
Removed:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
new file mode 100644
index 0..6b349b57e5faa
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
@@ -0,0 +1,228 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1
%s
+; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2
%s
+; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3
%s
+
+target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; We should retain the TBAA on the load here, not lose it.
+
+define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64
%numElem) {
+; OLDPM_O1-LABEL: @licm(
+; OLDPM_O1-NEXT: entry:
+; OLDPM_O1-NEXT:[[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]],
align 8
+; OLDPM_O1-NEXT:[[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0
+; OLDPM_O1-NEXT:br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label
[[FOR_BODY:%.*]]
+; OLDPM_O1: for.body:
+; OLDPM_O1-NEXT:[[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0,
[[ENTRY:%.*]] ]
+; OLDPM_O1-NEXT:[[ADD_PTR_I:%.*]] = getelementptr inbounds double, double*
[[TMP0]], i64 [[K_02]]
+; OLDPM_O1-NEXT:store double 2.00e+00, double* [[ADD_PTR_I]], align 8,
!tbaa [[TBAA3:![0-9]+]]
+; OLDPM_O1-NEXT:[[INC]] = add nuw i64 [[K_02]], 1
+; OLDPM_O1-NEXT:[[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]]
+; OLDPM_O1-NEXT:br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label
[[FOR_BODY]]
+; OLDPM_O1: for.cond.cleanup:
+; OLDPM_O1-NEXT:ret void
+;
+; OLDPM_O2-LABEL: @licm(
+; OLDPM_O2-NEXT: entry:
+; OLDPM_O2-NEXT:[[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]],
align 8
+; OLDPM_O2-NEXT:[[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0
+; OLDPM_O2-NEXT:br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label
[[FOR_BODY_PREHEADER:%.*]]
+; OLDPM_O2: for.body.preheader:
+; OLDPM_O2-NEXT:[[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4
+; OLDPM_O2-NEXT:br i1 [[MIN_ITERS_CHECK]], label
[[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]]
+; OLDPM_O2: vector.ph:
+; OLDPM_O2-NEXT:[[N_VEC:%.*]] = and i64 [[NUMELEM]], -4
+; OLDPM_O2-NEXT:br label [[VECTOR_BODY:%.*]]
+; OLDPM_O2: vector.body:
+; OLDPM_O2-NEXT:[[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [
[[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; OLDPM_O2-NEXT:[[TMP1:%.*]] = getelementptr inbounds double, double*
[[TMP0]], i64 [[INDEX]]
+; OLDPM_O2-NEXT:[[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>*
+; OLDPM_O2-NEXT:store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]]
+; OLDPM_O2-NEXT:[[TMP3:%.*]] = getelementptr inbounds double, double*
[[TMP1]], i64 2
+; OLDPM_O2-NEXT:[[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>*
+; OLDPM_O2-NEXT:store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]]
+; OLDPM_O2-NEXT:[[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; OLDPM_O2-NEXT:[[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; OLDPM_O2-NEXT:br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label
[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; OLDPM_O2: middle.block:
+; OLDPM_O2-NEXT:[[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]]
+; OLDPM_O2-NEXT:br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label
[[FOR_BODY_PREHEADER3]]
+; OLDPM_O2: for.body.preheader3:
+; OLDPM_O2-NEXT:[[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [
[[N_VEC]], [[MIDDLE_BLOCK]] ]
+; OLDPM_O2-NEXT:br label [[FOR_BODY:%.*]]
+; OLDPM_O2: for.body:
+; OLDPM_O2-NEXT:[[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [
[[K_02_PH]], [[FOR_BODY_PREHEADER3]] ]
+; OLDPM_O2-NEXT:[[ADD_PTR_I:%.*]] = getelementptr inbounds double, double*
[[TMP0]], i64 [[K_02]]
+; OLDPM_O2-NEXT:store
[llvm-branch-commits] [llvm] 1f46136 - [NFC][PhaseOrdering] spurious-peeling.ll: also test -O1/-O2 results
Author: Roman Lebedev
Date: 2022-03-07T21:02:28-08:00
New Revision: 1f4613675051f029a769c21996f19aa451ed17db
URL:
https://github.com/llvm/llvm-project/commit/1f4613675051f029a769c21996f19aa451ed17db
DIFF:
https://github.com/llvm/llvm-project/commit/1f4613675051f029a769c21996f19aa451ed17db.diff
LOG: [NFC][PhaseOrdering] spurious-peeling.ll: also test -O1/-O2 results
(cherry picked from commit a5b9987aab7601176902bf939fed2653f978450c)
Added:
Modified:
llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
Removed:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
index 4661bd8a36cce..e8e5ed90e60f1 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
@@ -1,6 +1,10 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck %s --check-prefixes=OLDPM
-; RUN: opt -passes='default' -S < %s | FileCheck %s --check-prefixes=NEWPM
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --function-signature
+; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1
%s
+; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2
%s
+; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3
%s
target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@@ -12,67 +16,170 @@ target triple = "x86_64-unknown-linux-gnu"
$_ZN12FloatVecPair6vecIncEv = comdat any
define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair*
%FVP) {
-; OLDPM-LABEL: @_Z13vecIncFromPtrP12FloatVecPair(
-; OLDPM-NEXT: entry:
-; OLDPM-NEXT:[[BASE_I_I:%.*]] = getelementptr inbounds
[[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP:%.*]], i64 0, i32 1, i32 0
-; OLDPM-NEXT:[[TMP0:%.*]] = load %class.HomemadeVector.0*,
%class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
-; OLDPM-NEXT:[[SIZE4_I:%.*]] = getelementptr inbounds
[[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef,
i32 1
-; OLDPM-NEXT:[[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa
[[TBAA6:![0-9]+]]
-; OLDPM-NEXT:[[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
-; OLDPM-NEXT:br i1 [[CMP510_NOT_I]], label
[[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
-; OLDPM: for.body7.lr.ph.i:
-; OLDPM-NEXT:[[BASE_I4_I:%.*]] = getelementptr inbounds
[[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0
-; OLDPM-NEXT:[[BASE_I6_I:%.*]] = getelementptr inbounds
[[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0
-; OLDPM-NEXT:[[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8,
!tbaa [[TBAA8:![0-9]+]]
-; OLDPM-NEXT:[[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float*
[[TMP2]], i64 undef
-; OLDPM-NEXT:[[TMP3:%.*]] = load %class.HomemadeVector.0*,
%class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]]
-; OLDPM-NEXT:[[BASE_I2_I:%.*]] = getelementptr inbounds
[[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0
-; OLDPM-NEXT:[[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8,
!tbaa [[TBAA8]]
-; OLDPM-NEXT:[[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float*
[[TMP4]], i64 undef
-; OLDPM-NEXT:[[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]],
align 4, !tbaa [[TBAA9:![0-9]+]]
-; OLDPM-NEXT:br label [[FOR_BODY7_I:%.*]]
-; OLDPM: for.body7.i:
-; OLDPM-NEXT:[[TMP5:%.*]] = phi float [ [[DOTPRE_I]],
[[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ]
-; OLDPM-NEXT:[[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [
[[INC_I:%.*]], [[FOR_BODY7_I]] ]
-; OLDPM-NEXT:[[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4,
!tbaa [[TBAA9]]
-; OLDPM-NEXT:[[ADD_I]] = fadd float [[TMP5]], [[TMP6]]
-; OLDPM-NEXT:store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4,
!tbaa [[TBAA9]]
-; OLDPM-NEXT:[[INC_I]] = add nuw i32 [[J_011_I]], 1
-; OLDPM-NEXT:[[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
-; OLDPM-NEXT:br i1 [[EXITCOND_NOT_I]], label
[[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop
[[LOOP11:![0-9]+]]
-; OLDPM: _ZN12FloatVecPair6vecIncEv.exit:
-; OLDPM-NEXT:ret void
+; OLDPM_O1-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair
+; OLDPM_O1-SAME: (%class.Flo
[llvm-branch-commits] [llvm] 7d1cd33 - [NFC][PhaseOrdering] Improve test coverage for D119975
Author: Roman Lebedev
Date: 2022-03-07T21:02:28-08:00
New Revision: 7d1cd3380add0e3ab6e8040717fc1413604d78bf
URL:
https://github.com/llvm/llvm-project/commit/7d1cd3380add0e3ab6e8040717fc1413604d78bf
DIFF:
https://github.com/llvm/llvm-project/commit/7d1cd3380add0e3ab6e8040717fc1413604d78bf.diff
LOG: [NFC][PhaseOrdering] Improve test coverage for D119975
(cherry picked from commit 07cf95942f57a85d9626a1c9ef8b90deb123bdb6)
Added:
llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
Modified:
llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
Removed:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
new file mode 100644
index 0..20c3cb029d2ae
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
@@ -0,0 +1,398 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --function-signature
+; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1
%s
+; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2
%s
+; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2
%s
+; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3
%s
+
+target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%"class.std::vector" = type { %"struct.std::_Vector_base" }
+%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base>::_Vector_impl" }
+%"struct.std::_Vector_base>::_Vector_impl" = type {
%"struct.std::_Vector_base>::_Vector_impl_data" }
+%"struct.std::_Vector_base>::_Vector_impl_data" =
type { i32*, i32*, i32* }
+
+$_ZNSt6vectorIiSaIiEEixEm = comdat any
+
+define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"*
noundef nonnull align 8 dereferenceable(24) %data, i64 noundef %numElems) {
+; OLDPM_O1-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy
+; OLDPM_O1-SAME: (%"class.std::vector"* noundef nonnull align 8
dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]])
local_unnamed_addr {
+; OLDPM_O1-NEXT: entry:
+; OLDPM_O1-NEXT:[[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
+; OLDPM_O1-NEXT:br label [[FOR_COND1_PREHEADER:%.*]]
+; OLDPM_O1: for.cond1.preheader:
+; OLDPM_O1-NEXT:[[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [
[[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ]
+; OLDPM_O1-NEXT:br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label
[[FOR_BODY4:%.*]]
+; OLDPM_O1: for.cond.cleanup:
+; OLDPM_O1-NEXT:ret void
+; OLDPM_O1: for.cond.cleanup3:
+; OLDPM_O1-NEXT:[[INC7]] = add nuw nsw i64 [[I_08]], 1
+; OLDPM_O1-NEXT:[[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100
+; OLDPM_O1-NEXT:br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]],
label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
+; OLDPM_O1: for.body4:
+; OLDPM_O1-NEXT:[[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [
0, [[FOR_COND1_PREHEADER]] ]
+; OLDPM_O1-NEXT:[[CALL:%.*]] = call noundef nonnull align 4
dereferenceable(4) i32* @_ZNSt6vectorIiSaIiEEixEm(%"class.std::vector"* noundef
nonnull align 8 dereferenceable(24) [[DATA]], i64 noundef [[J_07]])
+; OLDPM_O1-NEXT:[[TMP0:%.*]] = load i32, i32* [[CALL]], align 4, !tbaa
[[TBAA2:![0-9]+]]
+; OLDPM_O1-NEXT:[[INC:%.*]] = add nsw i32 [[TMP0]], 1
+; OLDPM_O1-NEXT:store i32 [[INC]], i32* [[CALL]], align 4, !tbaa [[TBAA2]]
+; OLDPM_O1-NEXT:[[INC5]] = add nuw i64 [[J_07]], 1
+; OLDPM_O1-NEXT:[[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]]
+; OLDPM_O1-NEXT:br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label
[[FOR_BODY4]], !llvm.loop [[LOOP6:![0-9]+]]
+;
+; OLDPM_O2-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy
+; OLDPM_O2-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly
align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; OLDPM_O2-NEXT: entry:
+; OLDPM_O2-NEXT:[[_M_START_I:%.*]] = getelementptr inbounds
%"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32
0, i32 0
+; OLDPM_O2-NEXT:[[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
+; OLDPM_O2-NEXT:[[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8
+; OLDPM_O2-NEXT:[[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8
+; OLDPM_O2-NEXT:[[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]]
+; OLDPM_O2-NEXT:br label [[FOR_COND1_PREHEADER:%.*]]
+; OLDPM_O2: for.cond1.preheader:
+; OLDPM_O2-NEXT:[[I_08:%
[llvm-branch-commits] [llvm] 2de2a2b - [LICM][PhaseOrder] Don't speculate in LICM until after running loop rotate
Author: William S. Moses
Date: 2022-03-07T21:02:29-08:00
New Revision: 2de2a2bba998f4145cfd4298d39bfd5e98485bdd
URL:
https://github.com/llvm/llvm-project/commit/2de2a2bba998f4145cfd4298d39bfd5e98485bdd
DIFF:
https://github.com/llvm/llvm-project/commit/2de2a2bba998f4145cfd4298d39bfd5e98485bdd.diff
LOG: [LICM][PhaseOrder] Don't speculate in LICM until after running loop rotate
LICM will speculatively hoist code outside of loops. This requires removing
information, like alias analysis
(https://github.com/llvm/llvm-project/issues/53794), range information
(https://bugs.llvm.org/show_bug.cgi?id=50550), among others. Prior to
https://reviews.llvm.org/D99249 , LICM would only be run after LoopRotate.
Running Loop Rotate prior to LICM prevents a instruction hoist from being
speculative, if it was conditionally executed by the iteration (as is commonly
emitted by clang and other frontends). Adding the additional LICM pass first,
however, forces all of these instructions to be considered speculative, even if
they are not speculative after LoopRotate. This destroys information, resulting
in performance losses for discarding this additional information.
This PR modifies LICM to accept a ``speculative'' parameter which allows LICM
to be set to perform information-loss speculative hoists or not. Phase ordering
is then modified to not perform the information-losing speculative hoists until
after loop rotate is performed, preserving this additional information.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D119965
(cherry picked from commit d9da6a535f21946cfaac1516ef28ac7646211d56)
Added:
Modified:
llvm/include/llvm/Transforms/Scalar.h
llvm/include/llvm/Transforms/Scalar/LICM.h
llvm/include/llvm/Transforms/Utils/LoopUtils.h
llvm/lib/Passes/PassBuilderPipelines.cpp
llvm/lib/Transforms/IPO/PassManagerBuilder.cpp
llvm/lib/Transforms/Scalar/LICM.cpp
llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
Removed:
diff --git a/llvm/include/llvm/Transforms/Scalar.h
b/llvm/include/llvm/Transforms/Scalar.h
index d6228700aa9ac..4d6874f784efb 100644
--- a/llvm/include/llvm/Transforms/Scalar.h
+++ b/llvm/include/llvm/Transforms/Scalar.h
@@ -133,7 +133,8 @@ Pass *createIndVarSimplifyPass();
//
Pass *createLICMPass();
Pass *createLICMPass(unsigned LicmMssaOptCap,
- unsigned LicmMssaNoAccForPromotionCap);
+ unsigned LicmMssaNoAccForPromotionCap,
+ bool AllowSpeculation);
//===--===//
//
diff --git a/llvm/include/llvm/Transforms/Scalar/LICM.h
b/llvm/include/llvm/Transforms/Scalar/LICM.h
index 751f75c0ccb24..503c8792d3092 100644
--- a/llvm/include/llvm/Transforms/Scalar/LICM.h
+++ b/llvm/include/llvm/Transforms/Scalar/LICM.h
@@ -46,14 +46,18 @@ extern cl::opt SetLicmMssaNoAccForPromotionCap;
class LICMPass : public PassInfoMixin {
unsigned LicmMssaOptCap;
unsigned LicmMssaNoAccForPromotionCap;
+ bool LicmAllowSpeculation;
public:
LICMPass()
: LicmMssaOptCap(SetLicmMssaOptCap),
-LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap) {}
- LICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap)
+LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap),
+LicmAllowSpeculation(true) {}
+ LICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap,
+ bool LicmAllowSpeculation)
: LicmMssaOptCap(LicmMssaOptCap),
-LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap) {}
+LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap),
+LicmAllowSpeculation(LicmAllowSpeculation) {}
PreservedAnalyses run(Loop &L, LoopAnalysisManager &AM,
LoopStandardAnalysisResults &AR, LPMUpdater &U);
};
@@ -62,14 +66,18 @@ class LICMPass : public PassInfoMixin {
class LNICMPass : public PassInfoMixin {
unsigned LicmMssaOptCap;
unsigned LicmMssaNoAccForPromotionCap;
+ bool LicmAllowSpeculation;
public:
LNICMPass()
: LicmMssaOptCap(SetLicmMssaOptCap),
-LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap) {}
- LNICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap)
+LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap),
+LicmAllowSpeculation(true) {}
+ LNICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap,
+bool LicmAllowSpeculation)
: LicmMssaOptCap(LicmMssaOptCap),
-LicmMssaNoAccForPromotionCap(LicmM
[llvm-branch-commits] [llvm] 6a71312 - [llvm] [bindings/OCaml] Remove unused dep on ounit2
Author: Michał Górny
Date: 2022-03-07T21:02:29-08:00
New Revision: 6a713120502abc0a42b8d518edea345b60e829f3
URL:
https://github.com/llvm/llvm-project/commit/6a713120502abc0a42b8d518edea345b60e829f3
DIFF:
https://github.com/llvm/llvm-project/commit/6a713120502abc0a42b8d518edea345b60e829f3.diff
LOG: [llvm] [bindings/OCaml] Remove unused dep on ounit2
Remove the dependency on ounit2 and the relevant lit code. It seems
that ounit2 is not used at all and all OCaml binding tests pass without
it installed.
Thanks for Shiwei Weng and Josh Berdine for bringing this to
my attention.
Differential Revision: https://reviews.llvm.org/D119884
(cherry picked from commit 2c5c243bb5152de35c41f5880271451fce6165d0)
Added:
Modified:
llvm/bindings/ocaml/README.txt
llvm/cmake/config-ix.cmake
llvm/test/Bindings/OCaml/lit.local.cfg
llvm/test/CMakeLists.txt
llvm/test/lit.site.cfg.py.in
llvm/utils/gn/secondary/llvm/test/BUILD.gn
Removed:
diff --git a/llvm/bindings/ocaml/README.txt b/llvm/bindings/ocaml/README.txt
index a6a595e75bb5f..08b5514e0a664 100644
--- a/llvm/bindings/ocaml/README.txt
+++ b/llvm/bindings/ocaml/README.txt
@@ -6,7 +6,6 @@ Prerequisites
* OCaml 4.00.0+.
* ctypes 0.4+.
-* oUnit 2+ (only required for tests).
* CMake (to build LLVM).
Building the bindings
diff --git a/llvm/cmake/config-ix.cmake b/llvm/cmake/config-ix.cmake
index c70b8b3787a0a..18d78879c968f 100644
--- a/llvm/cmake/config-ix.cmake
+++ b/llvm/cmake/config-ix.cmake
@@ -650,12 +650,6 @@ else()
find_ocamlfind_package(ctypes VERSION 0.4 OPTIONAL)
if( HAVE_OCAML_CTYPES )
message(STATUS "OCaml bindings enabled.")
-find_ocamlfind_package(ounit2 OPTIONAL)
-if ( HAVE_OCAML_OUNIT2 )
- set(HAVE_OCAML_OUNIT TRUE)
-else()
- find_ocamlfind_package(oUnit VERSION 2 OPTIONAL)
-endif()
set(LLVM_BINDINGS "${LLVM_BINDINGS} ocaml")
set(LLVM_OCAML_INSTALL_PATH "${OCAML_STDLIB_PATH}" CACHE STRING
diff --git a/llvm/test/Bindings/OCaml/lit.local.cfg
b/llvm/test/Bindings/OCaml/lit.local.cfg
index fd9e1c50e990c..364b97c632e83 100644
--- a/llvm/test/Bindings/OCaml/lit.local.cfg
+++ b/llvm/test/Bindings/OCaml/lit.local.cfg
@@ -2,6 +2,3 @@ config.suffixes = ['.ml']
if not 'ocaml' in config.root.llvm_bindings:
config.unsupported = True
-
-if not config.root.have_ocaml_ounit:
-config.unsupported = True
diff --git a/llvm/test/CMakeLists.txt b/llvm/test/CMakeLists.txt
index 2d18625e86133..495dccc392046 100644
--- a/llvm/test/CMakeLists.txt
+++ b/llvm/test/CMakeLists.txt
@@ -2,7 +2,6 @@ llvm_canonicalize_cmake_booleans(
BUILD_SHARED_LIBS
LLVM_HAVE_LIBXAR
HAVE_OCAMLOPT
- HAVE_OCAML_OUNIT
LLVM_ENABLE_DIA_SDK
LLVM_ENABLE_FFI
LLVM_ENABLE_THREADS
diff --git a/llvm/test/lit.site.cfg.py.in b/llvm/test/lit.site.cfg.py.in
index e92cb0caa4e1c..5836c8e62b0d4 100644
--- a/llvm/test/lit.site.cfg.py.in
+++ b/llvm/test/lit.site.cfg.py.in
@@ -20,7 +20,6 @@ config.ld64_executable = "@LD64_EXECUTABLE@"
config.osx_sysroot = path(r"@CMAKE_OSX_SYSROOT@")
config.ocamlfind_executable = "@OCAMLFIND@"
config.have_ocamlopt = @HAVE_OCAMLOPT@
-config.have_ocaml_ounit = @HAVE_OCAML_OUNIT@
config.ocaml_flags = "@OCAMLFLAGS@"
config.include_go_tests = @LLVM_INCLUDE_GO_TESTS@
config.go_executable = "@GO_EXECUTABLE@"
diff --git a/llvm/utils/gn/secondary/llvm/test/BUILD.gn
b/llvm/utils/gn/secondary/llvm/test/BUILD.gn
index 042972aff276f..41abe22ef5710 100644
--- a/llvm/utils/gn/secondary/llvm/test/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/test/BUILD.gn
@@ -84,7 +84,6 @@ write_lit_config("lit_site_cfg") {
"LLVM_INCLUDE_GO_TESTS=0",
"HAVE_OCAMLOPT=0",
-"HAVE_OCAML_OUNIT=0",
"OCAMLFIND=OCAMLFIND-NOTFOUND",
"OCAMLFLAGS=",
"LLVM_BUILD_EXAMPLES=0",
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