[llvm-branch-commits] [clang] 261253a - [Clang][docs] Add preprocessor changes to ReleaseNotes.

2022-03-02 Thread Michael Kruse via llvm-branch-commits 

Author: Michael Kruse
Date: 2022-03-02T13:01:28-06:00
New Revision: 261253aa60cc10f21788fb55ae27152242a65989

URL: 
https://github.com/llvm/llvm-project/commit/261253aa60cc10f21788fb55ae27152242a65989
DIFF: 
https://github.com/llvm/llvm-project/commit/261253aa60cc10f21788fb55ae27152242a65989.diff

LOG: [Clang][docs] Add preprocessor changes to ReleaseNotes.

Added: 


Modified: 
clang/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 869d62aebfb18..a6cbf25fd48a5 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -76,6 +76,9 @@ Non-comprehensive list of changes in this release
 - Configuration file syntax extended with  token. This expands to
   the base path of the current config file. See :ref:`configuration-files` for
   details.
+- The ``-E -P`` preprocessor output now always omits blank lines, matching
+  gcc behaviour. Previously, up to 8 consecutive blank lines could appear
+  in the output.
 
 New Compiler Flags
 --
@@ -91,6 +94,14 @@ New Compiler Flags
   outside of such a region.
 - ``-falign-loops=N`` (N is a power of 2) is now supported for non-LTO cases.
   (`D106701 `_)
+- The ``-fminimize-whitespace`` flag allows removing redundant whitespace
+  from preprocessor output (``-E`` flag). When combined with ``-P``, this
+  includes newlines. Otherwise, only indention is removed (other horizontal
+  whitespace is always collapsed).
+  The motivation is to improve compiler cache hit rate by becoming invariant
+  to whitespace changes, such as reformatting using clang-format. Patches
+  for `ccache `_ and
+  `sccache `_ are under review.
 
 Deprecated Compiler Flags
 -



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[llvm-branch-commits] [llvm] a98c04d - [Attributor][FIX] Use liveness information of the right function

2022-03-02 Thread Tom Stellard via llvm-branch-commits 

Author: Johannes Doerfert
Date: 2022-03-02T12:48:04-08:00
New Revision: a98c04d58930814f4ff00293ffd14feca57feafa

URL: 
https://github.com/llvm/llvm-project/commit/a98c04d58930814f4ff00293ffd14feca57feafa
DIFF: 
https://github.com/llvm/llvm-project/commit/a98c04d58930814f4ff00293ffd14feca57feafa.diff

LOG: [Attributor][FIX] Use liveness information of the right function

When we use liveness for edges during the `genericValueTraversal` we
need to make sure to use the AAIsDead of the correct function. This
patch adds the proper logic and some simple caching scheme. We also
add an assertion to the `isEdgeDead` call to make sure future misuse
is detected earlier.

Fixes https://github.com/llvm/llvm-project/issues/53872

Added: 


Modified: 
llvm/lib/Transforms/IPO/AttributorAttributes.cpp
llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll
llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll
llvm/test/Transforms/Attributor/align.ll
llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll
llvm/test/Transforms/Attributor/value-simplify.ll

Removed: 




diff  --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp 
b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 5593a297d2d89..61a973f869d41 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -266,13 +266,18 @@ static bool genericValueTraversal(
 function_ref StripCB = nullptr,
 bool Intraprocedural = false) {
 
-  const AAIsDead *LivenessAA = nullptr;
-  if (IRP.getAnchorScope())
-LivenessAA = &A.getAAFor(
-QueryingAA,
-IRPosition::function(*IRP.getAnchorScope(), IRP.getCallBaseContext()),
-DepClassTy::NONE);
-  bool AnyDead = false;
+  struct LivenessInfo {
+const AAIsDead *LivenessAA = nullptr;
+bool AnyDead = false;
+  };
+  DenseMap LivenessAAs;
+  auto GetLivenessInfo = [&](const Function &F) -> LivenessInfo & {
+LivenessInfo &LI = LivenessAAs[&F];
+if (!LI.LivenessAA)
+  LI.LivenessAA = &A.getAAFor(QueryingAA, 
IRPosition::function(F),
+DepClassTy::NONE);
+return LI;
+  };
 
   Value *InitialV = &IRP.getAssociatedValue();
   using Item = std::pair;
@@ -342,13 +347,12 @@ static bool genericValueTraversal(
 
 // Look through phi nodes, visit all live operands.
 if (auto *PHI = dyn_cast(V)) {
-  assert(LivenessAA &&
- "Expected liveness in the presence of instructions!");
+  LivenessInfo &LI = GetLivenessInfo(*PHI->getFunction());
   for (unsigned u = 0, e = PHI->getNumIncomingValues(); u < e; u++) {
 BasicBlock *IncomingBB = PHI->getIncomingBlock(u);
-if (LivenessAA->isEdgeDead(IncomingBB, PHI->getParent())) {
-  AnyDead = true;
-  UsedAssumedInformation |= !LivenessAA->isAtFixpoint();
+if (LI.LivenessAA->isEdgeDead(IncomingBB, PHI->getParent())) {
+  LI.AnyDead = true;
+  UsedAssumedInformation |= !LI.LivenessAA->isAtFixpoint();
   continue;
 }
 Worklist.push_back(
@@ -402,8 +406,10 @@ static bool genericValueTraversal(
   } while (!Worklist.empty());
 
   // If we actually used liveness information so we have to record a 
dependence.
-  if (AnyDead)
-A.recordDependence(*LivenessAA, QueryingAA, DepClassTy::OPTIONAL);
+  for (auto &It : LivenessAAs)
+if (It.second.AnyDead)
+  A.recordDependence(*It.second.LivenessAA, QueryingAA,
+ DepClassTy::OPTIONAL);
 
   // All values have been visited.
   return true;
@@ -1248,11 +1254,13 @@ struct AAPointerInfoImpl
 // Run the user callback on all writes we cannot skip and return if that
 // succeeded for all or not.
 unsigned NumInterferingWrites = InterferingWrites.size();
-for (auto &It : InterferingWrites)
+for (auto &It : InterferingWrites) {
   if (!DT || NumInterferingWrites > MaxInterferingWrites ||
-  !CanSkipAccess(*It.first, It.second))
+  !CanSkipAccess(*It.first, It.second)) {
 if (!UserCB(*It.first, It.second))
   return false;
+  }
+}
 return true;
   }
 
@@ -3839,6 +3847,9 @@ struct AAIsDeadFunction : public AAIsDead {
   ChangeStatus updateImpl(Attributor &A) override;
 
   bool isEdgeDead(const BasicBlock *From, const BasicBlock *To) const override 
{
+assert(From->getParent() == getAnchorScope() &&
+   To->getParent() == getAnchorScope() &&
+   "Used AAIsDead of the wrong function");
 return isValidState() && !AssumedLiveEdges.count(std::make_pair(From, To));
   }
 

diff  --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll 
b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll
index 5eda27957e6b8..cdec3a09fdfb8 100644
--- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll
+++ b/llvm

[llvm-branch-commits] [llvm] 6d5afef - [examples][BuildingAJIT] Use the right layer when adding code in Chapter 3.

2022-03-02 Thread Tom Stellard via llvm-branch-commits 

Author: Lang Hames
Date: 2022-03-02T12:59:20-08:00
New Revision: 6d5afef3a7e6c2c9cc3bdb79e9d0fc88345e0e51

URL: 
https://github.com/llvm/llvm-project/commit/6d5afef3a7e6c2c9cc3bdb79e9d0fc88345e0e51
DIFF: 
https://github.com/llvm/llvm-project/commit/6d5afef3a7e6c2c9cc3bdb79e9d0fc88345e0e51.diff

LOG: [examples][BuildingAJIT] Use the right layer when adding code in Chapter 3.

We were incorrectly using the OptimizeLayer and bypassing the COD layer.

(cherry picked from commit 1e16272ba793e5a6e7308898ecf6ef0dc99e2ad3)

Added: 


Modified: 
llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h

Removed: 




diff  --git 
a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h 
b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
index 130310da92748..de169804b06f3 100644
--- a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
+++ b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
@@ -120,7 +120,7 @@ class KaleidoscopeJIT {
 if (!RT)
   RT = MainJD.getDefaultResourceTracker();
 
-return OptimizeLayer.add(RT, std::move(TSM));
+return CODLayer.add(RT, std::move(TSM));
   }
 
   Expected lookup(StringRef Name) {



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[llvm-branch-commits] [llvm] 4fde843 - [ORC] Set ResolverBlockAddr in EPCIndirectionUtils::writeResolverBlock.

2022-03-02 Thread Tom Stellard via llvm-branch-commits 

Author: Lang Hames
Date: 2022-03-02T12:59:20-08:00
New Revision: 4fde843cd5c08c16f15d11308bdefc7bd2af0302

URL: 
https://github.com/llvm/llvm-project/commit/4fde843cd5c08c16f15d11308bdefc7bd2af0302
DIFF: 
https://github.com/llvm/llvm-project/commit/4fde843cd5c08c16f15d11308bdefc7bd2af0302.diff

LOG: [ORC] Set ResolverBlockAddr in EPCIndirectionUtils::writeResolverBlock.

Without this, EPCIndirectionUtils::getResolverBlockAddr (and lazy compilation
via EPC) won't work.

No test case: lli is still using LocalLazyCallThroughManager. I'll revisit this
soon when I look at adding lazy compilation support to the ORC runtime.

(cherry picked from commit 34e539dcd78ab828210ecf7f7d2e9d2c986511b3)

Added: 


Modified: 
llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h
llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp

Removed: 




diff  --git a/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h 
b/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h
index 92de5882bafe4..354984b540a9f 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h
@@ -148,7 +148,7 @@ class EPCIndirectionUtils {
   std::mutex EPCUIMutex;
   ExecutorProcessControl &EPC;
   std::unique_ptr ABI;
-  JITTargetAddress ResolverBlockAddr;
+  JITTargetAddress ResolverBlockAddr = 0;
   FinalizedAlloc ResolverBlock;
   std::unique_ptr TP;
   std::unique_ptr LCTM;

diff  --git a/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp 
b/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
index b901a2d2da236..249f02f36bae4 100644
--- a/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
@@ -302,7 +302,8 @@ EPCIndirectionUtils::writeResolverBlock(JITTargetAddress 
ReentryFnAddr,
 return Alloc.takeError();
 
   auto SegInfo = Alloc->getSegInfo(MemProt::Read | MemProt::Exec);
-  ABI->writeResolverCode(SegInfo.WorkingMem.data(), SegInfo.Addr.getValue(),
+  ResolverBlockAddr = SegInfo.Addr.getValue();
+  ABI->writeResolverCode(SegInfo.WorkingMem.data(), ResolverBlockAddr,
  ReentryFnAddr, ReentryCtxAddr);
 
   auto FA = Alloc->finalize();
@@ -310,7 +311,7 @@ EPCIndirectionUtils::writeResolverBlock(JITTargetAddress 
ReentryFnAddr,
 return FA.takeError();
 
   ResolverBlock = std::move(*FA);
-  return SegInfo.Addr.getValue();
+  return ResolverBlockAddr;
 }
 
 std::unique_ptr



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[llvm-branch-commits] [clang] f1e7f84 - [clang][tests] Fix ve-toolchain tests with CLANG_DEFAULT_UNWINDLIB

2022-03-02 Thread Tom Stellard via llvm-branch-commits 

Author: Timm Bäder
Date: 2022-03-02T12:59:40-08:00
New Revision: f1e7f848bf3e84906fda52975dbcfc6825710987

URL: 
https://github.com/llvm/llvm-project/commit/f1e7f848bf3e84906fda52975dbcfc6825710987
DIFF: 
https://github.com/llvm/llvm-project/commit/f1e7f848bf3e84906fda52975dbcfc6825710987.diff

LOG: [clang][tests] Fix ve-toolchain tests with CLANG_DEFAULT_UNWINDLIB

Otherwise, the driver will insert e.g. -lgcc_s when
CLANG_DEFAULT_UNWINDLIB=libgcc is set during the clang build.

Differential Revision: https://reviews.llvm.org/D120644

(cherry picked from commit 12d3679256c9a544699f9894c16c2918da17e4af)

Added: 


Modified: 
clang/test/Driver/ve-toolchain.c
clang/test/Driver/ve-toolchain.cpp

Removed: 




diff  --git a/clang/test/Driver/ve-toolchain.c 
b/clang/test/Driver/ve-toolchain.c
index 35af3c81c4c6f..753dee19fcbfb 100644
--- a/clang/test/Driver/ve-toolchain.c
+++ b/clang/test/Driver/ve-toolchain.c
@@ -83,6 +83,7 @@
 // RUN: %clang -### -target ve-unknown-linux-gnu \
 // RUN: --sysroot %S/Inputs/basic_ve_tree \
 // RUN: -resource-dir=%S/Inputs/basic_ve_tree/resource_dir \
+// RUN: --unwindlib=none \
 // RUN: -fuse-ld=ld \
 // RUN: %s 2>&1 | FileCheck -check-prefix=DEF %s
 

diff  --git a/clang/test/Driver/ve-toolchain.cpp 
b/clang/test/Driver/ve-toolchain.cpp
index 7447f34b70e0c..4b2b9c5747fe4 100644
--- a/clang/test/Driver/ve-toolchain.cpp
+++ b/clang/test/Driver/ve-toolchain.cpp
@@ -133,7 +133,8 @@
 // RUN: --sysroot %S/Inputs/basic_ve_tree \
 // RUN: -fuse-ld=ld \
 // RUN: -resource-dir=%S/Inputs/basic_ve_tree/resource_dir \
-// RUN: --stdlib=c++ %s 2>&1 | FileCheck -check-prefix=DEF %s
+// RUN: --unwindlib=none \
+// RUN: --stdlib=libc++ %s 2>&1 | FileCheck -check-prefix=DEF %s
 
 // DEF:  clang{{.*}}" "-cc1"
 // DEF-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"



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[llvm-branch-commits] [llvm] 65d5327 - [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.

2022-03-02 Thread Shao-Ce SUN via llvm-branch-commits 

Author: Shao-Ce SUN
Date: 2022-03-03T14:52:36+08:00
New Revision: 65d53279b1fddeae4bd455d588ea7527aed50bb9

URL: 
https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9
DIFF: 
https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9.diff

LOG: [RISCV] More correctly ignore Zfinx register classes in 
getRegForInlineAsmConstraint.

Until Zfinx is supported in CodeGen we need to convert all Zfinx
register classes to GPR.

Remove the zfinx-types.ll test which didn't test anything meaningful
since -mattr=zfinx isn't implemented completely in llc.

Follow up to D93298.

(cherry picked from commit 6cb42cd6669785f3b611106e1b6b38bbe65733a9)

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

Removed: 
llvm/test/CodeGen/RISCV/zfinx-types.ll



diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 19935caa34dfb..e7672a7652cdd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10469,24 +10469,13 @@ 
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   std::pair Res =
   TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 
-  if (Res.second == &RISCV::GPRF32RegClass) {
-if (!Subtarget.is64Bit() || VT == MVT::Other)
-  return std::make_pair(Res.first, &RISCV::GPRRegClass);
-return std::make_pair(0, nullptr);
-  }
-
-  if (Res.second == &RISCV::GPRF64RegClass ||
-  Res.second == &RISCV::GPRPF64RegClass) {
-if (Subtarget.is64Bit() || VT == MVT::Other)
-  return std::make_pair(Res.first, &RISCV::GPRRegClass);
-return std::make_pair(0, nullptr);
-  }
-
-  if (Res.second == &RISCV::GPRF16RegClass) {
-if (VT == MVT::Other)
-  return std::make_pair(Res.first, &RISCV::GPRRegClass);
-return std::make_pair(0, nullptr);
-  }
+  // If we picked one of the Zfinx register classes, remap it to the GPR class.
+  // FIXME: When Zfinx is supported in CodeGen this will need to take the
+  // Subtarget into account.
+  if (Res.second == &RISCV::GPRF16RegClass ||
+  Res.second == &RISCV::GPRF32RegClass ||
+  Res.second == &RISCV::GPRF64RegClass)
+return std::make_pair(Res.first, &RISCV::GPRRegClass);
 
   return Res;
 }

diff  --git a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll 
b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
index 37ce0f89e7ec5..2e7ae0847f20f 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
@@ -71,3 +71,37 @@ define double @constraint_f_double_abi_name(double %a) 
nounwind {
   %2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double 
%a, double %1)
   ret double %2
 }
+
+define double @constraint_gpr(double %x) {
+; RV32F-LABEL: constraint_gpr:
+; RV32F:   # %bb.0:
+; RV32F-NEXT:addi sp, sp, -32
+; RV32F-NEXT:.cfi_def_cfa_offset 32
+; RV32F-NEXT:sw a0, 8(sp)
+; RV32F-NEXT:sw a1, 12(sp)
+; RV32F-NEXT:fld ft0, 8(sp)
+; RV32F-NEXT:fsd ft0, 24(sp)
+; RV32F-NEXT:lw a0, 24(sp)
+; RV32F-NEXT:lw a1, 28(sp)
+; RV32F-NEXT:#APP
+; RV32F-NEXT:mv a0, a0
+; RV32F-NEXT:#NO_APP
+; RV32F-NEXT:sw a1, 20(sp)
+; RV32F-NEXT:sw a0, 16(sp)
+; RV32F-NEXT:fld ft0, 16(sp)
+; RV32F-NEXT:fsd ft0, 8(sp)
+; RV32F-NEXT:lw a0, 8(sp)
+; RV32F-NEXT:lw a1, 12(sp)
+; RV32F-NEXT:addi sp, sp, 32
+; RV32F-NEXT:ret
+;
+; RV64F-LABEL: constraint_gpr:
+; RV64F:   # %bb.0:
+; RV64F-NEXT:.cfi_def_cfa_offset 0
+; RV64F-NEXT:#APP
+; RV64F-NEXT:mv a0, a0
+; RV64F-NEXT:#NO_APP
+; RV64F-NEXT:ret
+  %1 = tail call double asm sideeffect alignstack "mv $0, $1", 
"={x10},{x10}"(double %x)
+  ret double %1
+}

diff  --git a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll 
b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
index 07d6d1a365cd8..d6df31e878313 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
@@ -63,3 +63,23 @@ define float @constraint_f_float_abi_name(float %a) nounwind 
{
   %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, 
float %1)
   ret float %2
 }
+
+define float @constraint_gpr(float %x) {
+; RV32F-LABEL: constraint_gpr:
+; RV32F:   # %bb.0:
+; RV32F-NEXT:.cfi_def_cfa_offset 0
+; RV32F-NEXT:#APP
+; RV32F-NEXT:mv a0, a0
+; RV32F-NEXT:#NO_APP
+; RV32F-NEXT:ret
+;
+; RV64F-LABEL: constraint_gpr:
+; RV64F:   # %bb.0:
+; RV64F-NEXT:.cfi_def_cfa_offset 0
+; RV64F-NEXT:#APP
+; RV64F-NEXT:mv a0, a0
+; RV64F-NEXT:#NO_APP
+; RV64F-NEXT:ret
+  %1 = t