date:20211216

[llvm-branch-commits] [llvm] ce69b89 - [llvm][docs] Describe how to work with patch series on Phabricator

2021-12-16 Thread David Spickett via llvm-branch-commits


Author: David Spickett
Date: 2021-12-16T15:30:39Z
New Revision: ce69b89471804542b57aa62c5c6ac1be9f2954ea

URL: 
https://github.com/llvm/llvm-project/commit/ce69b89471804542b57aa62c5c6ac1be9f2954ea
DIFF: 
https://github.com/llvm/llvm-project/commit/ce69b89471804542b57aa62c5c6ac1be9f2954ea.diff

LOG: [llvm][docs] Describe how to work with patch series on Phabricator

Differential Revision: https://reviews.llvm.org/D115519

Added: 


Modified: 
llvm/docs/Phabricator.rst

Removed: 




diff  --git a/llvm/docs/Phabricator.rst b/llvm/docs/Phabricator.rst
index 21964d8227d91..40dab7e6d91e4 100644
--- a/llvm/docs/Phabricator.rst
+++ b/llvm/docs/Phabricator.rst
@@ -128,6 +128,95 @@ them to participate. Many people will see the email 
notification on cfe-commits
 or llvm-commits, and if the subject line suggests the patch is something they
 should look at, they will.
 
+.. _creating-a-patch-series:
+
+Creating a patch series
+---
+
+Chaining reviews together requires some manual work. There are two ways to do 
it
+(these are also described `here 
`_
+along with some screenshots of what to expect).
+
+.. _using-the-web-interface:
+
+Using the web interface
+^^^
+
+This assumes that you've already created a Phabricator review for each commit,
+using `arc` or the web interface.
+
+* Go to what will be the last review in the series (the most recent).
+* Click "Edit Related Revisions" then "Edit Parent Revisions".
+* This will open a dialog where you will enter the patch number of the parent 
patch
+  (or patches). The patch number is of the form D and you can find it 
by
+  looking at the URL for the review e.g. reviews.llvm/org/D12345.
+* Click "Save Parent Revisions" after entering them.
+* You should now see a "Stack" tab in the "Revision Contents" section of the 
web
+  interface, showing the parent patch that you added.
+
+Repeat this with each previous review until you reach the first in the series. 
This
+one won't have a parent since it's the start of the series.
+
+If you prefer to start with the first in the series and go forward, you can 
use the
+"Edit Child Revisions" option instead.
+
+.. _using-patch-summaries:
+
+Using patch summaries
+^
+
+This applies to new and existing reviews, uploaded with `arc` or the web 
interface.
+
+* Upload the first review and note its patch number, either with the web 
interface
+  or `arc`.
+* For each commit after that, add the following line to the commit message or 
patch
+  summary: "Depends on D", where "" is the patch number of the 
previous review.
+  This must be entirely on its own line, with a blank line before it.
+  For example::
+
+[llvm] Example commit
+
+Depends on D12345
+
+* If you want a single review to have multiple parent reviews then
+  add more with "and", for example: "Depends on D12344 and D12345".
+* Upload the commit with the web interface or `arc`
+  (``arc 
diff  --verbatim`` to update an existing review).
+* You will see a "Stack" tab in the "Revision Contents" section of the review
+  in the web interface, showing the parent review.
+* Repeat these steps until you've uploaded or updated all the patches in
+  your series.
+
+When you push the patches, please remove the "Depends on" lines from the
+commit messages, since they add noise and duplicate git's implicit ordering.
+
+One frequently used workflow for creating a series of patches using patch 
summaries
+is based on git's rebasing. These steps assume that you have a series of 
commits that
+you have not posted for review, but can be adapted to update existing reviews.
+
+* git interactive rebase back to the first commit you want to upload for 
review::
+
+git rebase -i HEAD~
+
+* Mark all commits for editing by changing "pick" to "edit" in the instructions
+  git shows.
+* Start the rebase (usually by writing and closing the instructions).
+* For the first commit:
+
+  - Upload the current commit for a review (with ``arc 
diff `` or the web
+interface).
+
+  - Continue to the next commit with ``git rebase --continue``
+
+* For the rest:
+
+  - Add the "Depends on..." line using ``git commit --amend``
+
+  - Upload for review.
+
+  - Continue the rebase.
+
+* Once the rebase is complete, you've created your patch series.
 
 .. _finding-potential-reviewers:
 



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[llvm-branch-commits] [llvm] 87ca22c - [Support] Attempt to fix deadlock in ThreadGroup

2021-12-16 Thread Tom Stellard via llvm-branch-commits


Author: Alexandre Ganea
Date: 2021-12-16T11:02:34-08:00
New Revision: 87ca22cba2fad9bbf553a74eced3b7bb69e187be

URL: 
https://github.com/llvm/llvm-project/commit/87ca22cba2fad9bbf553a74eced3b7bb69e187be
DIFF: 
https://github.com/llvm/llvm-project/commit/87ca22cba2fad9bbf553a74eced3b7bb69e187be.diff

LOG: [Support] Attempt to fix deadlock in ThreadGroup

This is an attempt to fix the situation described by 
https://reviews.llvm.org/D104207#2826290 and PR41508.
See sequence of operations leading to the bug in 
https://reviews.llvm.org/D104207#3004689

We ensure that the Latch is completely "free" before decrementing the number of 
TaskGroupInstances.

Differential revision: https://reviews.llvm.org/D109914

(cherry picked from commit 7b25fa8c7a151e94be46ed8f0a56bf4e2af1c104)

Added: 


Modified: 
llvm/include/llvm/Support/Parallel.h
llvm/lib/Support/Parallel.cpp

Removed: 




diff  --git a/llvm/include/llvm/Support/Parallel.h 
b/llvm/include/llvm/Support/Parallel.h
index 28d171d452560..5c3b26d5754c2 100644
--- a/llvm/include/llvm/Support/Parallel.h
+++ b/llvm/include/llvm/Support/Parallel.h
@@ -40,7 +40,10 @@ class Latch {
 
 public:
   explicit Latch(uint32_t Count = 0) : Count(Count) {}
-  ~Latch() { sync(); }
+  ~Latch() {
+// Ensure at least that sync() was called.
+assert(Count == 0);
+  }
 
   void inc() {
 std::lock_guard lock(Mutex);

diff  --git a/llvm/lib/Support/Parallel.cpp b/llvm/lib/Support/Parallel.cpp
index 9a2e1003da5a2..71e3a1362f7eb 100644
--- a/llvm/lib/Support/Parallel.cpp
+++ b/llvm/lib/Support/Parallel.cpp
@@ -151,7 +151,12 @@ static std::atomic TaskGroupInstances;
 // lock, only allow the first TaskGroup to run tasks parallelly. In the 
scenario
 // of nested parallel_for_each(), only the outermost one runs parallelly.
 TaskGroup::TaskGroup() : Parallel(TaskGroupInstances++ == 0) {}
-TaskGroup::~TaskGroup() { --TaskGroupInstances; }
+TaskGroup::~TaskGroup() {
+  // We must ensure that all the workloads have finished before decrementing 
the
+  // instances count.
+  L.sync();
+  --TaskGroupInstances;
+}
 
 void TaskGroup::spawn(std::function F) {
   if (Parallel) {



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[llvm-branch-commits] [lld] e68f640 - [ELF][PPC32] Make R_PPC32_PLTREL retain .got

2021-12-16 Thread Fangrui Song via llvm-branch-commits


Author: George Koehler
Date: 2021-12-16T18:06:50-08:00
New Revision: e68f640deecc4cc6318c14468101f4d819f93727

URL: 
https://github.com/llvm/llvm-project/commit/e68f640deecc4cc6318c14468101f4d819f93727
DIFF: 
https://github.com/llvm/llvm-project/commit/e68f640deecc4cc6318c14468101f4d819f93727.diff

LOG: [ELF][PPC32] Make R_PPC32_PLTREL retain .got

PLT usage needs the first 12 bytes of the .got section. We need to keep .got and
DT_GOT_PPC even if .got/_GLOBAL_OFFSET_TABLE_ are not referenced (large PIC code
may only reference .got2), which is the case in OpenBSD's ld.so, leading
to a misleading error, "unsupported insecure BSS PLT object".

Fix this by adding R_PPC32_PLTREL to the list of hasGotOffRel.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D114982

(cherry picked from commit 885fb9a257faa14ec33ad972df81801483c85da2)

Added: 
lld/test/ELF/ppc32-reloc-pltrel.s

Modified: 
lld/ELF/Relocations.cpp
lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s

Removed: 




diff  --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index fefd6f21f590e..71249188afe3e 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1409,8 +1409,8 @@ static void scanReloc(InputSectionBase &sec, OffsetGetter 
&getOffset, RelTy *&i,
   // The 4 types that relative GOTPLT are all x86 and x86-64 specific.
   if (oneof(expr)) {
 in.gotPlt->hasGotPltOffRel = true;
-  } else if (oneof(
- expr)) {
+  } else if (oneof( expr)) {
 in.got->hasGotOffRel = true;
   }
 

diff  --git a/lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s 
b/lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s
index a88927fdfd75e..a4b7c8bf97b84 100644
--- a/lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s
+++ b/lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s
@@ -7,12 +7,12 @@
 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 
 # RELOC:  .rela.dyn {
-# RELOC-NEXT:   0x30248 R_PPC_RELATIVE - 0x101A8
-# RELOC-NEXT:   0x3024C R_PPC_IRELATIVE - 0x10188
+# RELOC-NEXT:   0x30254 R_PPC_RELATIVE - 0x101A8
+# RELOC-NEXT:   0x30258 R_PPC_IRELATIVE - 0x10188
 # RELOC-NEXT: }
 
 # SYM: 000101a8 0 FUNC GLOBAL DEFAULT {{.*}} func
-# HEX: 0x00030248 
+# HEX: 0x00030254 
 
 .section .got2,"aw"
 .long func

diff  --git a/lld/test/ELF/ppc32-reloc-pltrel.s 
b/lld/test/ELF/ppc32-reloc-pltrel.s
new file mode 100644
index 0..17418482871c4
--- /dev/null
+++ b/lld/test/ELF/ppc32-reloc-pltrel.s
@@ -0,0 +1,35 @@
+# REQUIRES: ppc
+
+## Ensure R_PPC_PLTREL retains .got even in the absence of
+## .got/_GLOBAL_OFFSET_TABLE_ references.
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
+# RUN: ld.lld -shared %t.o -o %t.so
+# RUN: llvm-readobj -Sdr %t.so | FileCheck %s
+
+.section .got2,"aw",@progbits
+.set .LTOC, .+0x8000
+
+.text
+.L0:
+addis 30,30,.LTOC-.L0@ha
+addi 30,30,.LTOC-.L0@l
+bl baz+0x8000@plt
+
+## DT_PPC_GOT must point to .got, which must have the 12-byte header.
+## The only relocation is an R_PPC_JMP_SLOT.
+
+# CHECK:  Sections [
+# CHECK:Name: .got (
+# CHECK:Address:
+# CHECK-SAME:   {{ }}[[#%x,GOT:]]
+# CHECK:Size:
+# CHECK-SAME:   {{ 12$}}
+# CHECK:  DynamicSection [
+# CHECK-NEXT:   TagType Name/Value
+# CHECK:0x7000 PPC_GOT  [[#GOT]]
+# CHECK:  Relocations [
+# CHECK-NEXT:   Section ([[#]]) .rela.plt {
+# CHECK-NEXT: 0x[[#%x,]] R_PPC_JMP_SLOT baz 0x0
+# CHECK-NEXT:   }
+# CHECK-NEXT: ]



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[llvm-branch-commits] [llvm] 9fb79e6 - [PowerPC] Handle base load with reservation mnemonic

2021-12-16 Thread Tom Stellard via llvm-branch-commits


Author: Nemanja Ivanovic
Date: 2021-12-16T18:51:01-08:00
New Revision: 9fb79e6940b26145fdcaa79e9d74a76c61d6c2d4

URL: 
https://github.com/llvm/llvm-project/commit/9fb79e6940b26145fdcaa79e9d74a76c61d6c2d4
DIFF: 
https://github.com/llvm/llvm-project/commit/9fb79e6940b26145fdcaa79e9d74a76c61d6c2d4.diff

LOG: [PowerPC] Handle base load with reservation mnemonic

The Power ISA defined l[bhwdq]arx as both base and
extended mnemonics. The base mnemonic takes the EH
bit as an operand and the extended mnemonic omits
it, making it implicitly zero. The existing
implementation only handles the base mnemonic when
EH is 1 and internally produces a different
instruction. There are historical reasons for this.
This patch simply removes the limitation introduced
by this implementation that disallows the base
mnemonic with EH = 0 in the ASM parser.

This resolves an issue that prevented some files
in the Linux kernel from being built with
-fintegrated-as.

Also fix a crash if the value is not an integer immediate.

(cherry picked from commit d6c0ef78876dc3204b0a6d92119b15aa9cd12af3)

Added: 


Modified: 
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/test/CodeGen/PowerPC/inline-asm-label.ll
llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
llvm/test/MC/PowerPC/ppc64-errors.s

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 
b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 7631bb4bccfb6..392de0f251a27 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1576,6 +1576,16 @@ bool PPCAsmParser::ParseInstruction(ParseInstructionInfo 
&Info, StringRef Name,
 std::swap(Operands[2], Operands[1]);
   }
 
+  // Handle base mnemonic for atomic loads where the EH bit is zero.
+  if (Name == "lqarx" || Name == "ldarx" || Name == "lwarx" ||
+  Name == "lharx" || Name == "lbarx") {
+if (Operands.size() != 5)
+  return false;
+PPCOperand &EHOp = (PPCOperand &)*Operands[4];
+if (EHOp.isU1Imm() && EHOp.getImm() == 0)
+  Operands.pop_back();
+  }
+
   return false;
 }
 
@@ -1745,7 +1755,7 @@ unsigned 
PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
   }
 
   PPCOperand &Op = static_cast(AsmOp);
-  if (Op.isImm() && Op.getImm() == ImmVal)
+  if (Op.isU3Imm() && Op.getImm() == ImmVal)
 return Match_Success;
 
   return Match_InvalidOperand;

diff  --git a/llvm/test/CodeGen/PowerPC/inline-asm-label.ll 
b/llvm/test/CodeGen/PowerPC/inline-asm-label.ll
index 6bacbd77aba2c..33d0fdc926d29 100644
--- a/llvm/test/CodeGen/PowerPC/inline-asm-label.ll
+++ b/llvm/test/CodeGen/PowerPC/inline-asm-label.ll
@@ -45,3 +45,39 @@ entry:
   ret i32 %4
 }
 
+define dso_local signext i32 @NoBarrier_CompareAndSwapExtMne(i32* %ptr, i32 
signext %old_value, i32 signext %new_value) #0 {
+; CHECK-LABEL: NoBarrier_CompareAndSwapExtMne:
+; CHECK:#APP
+; CHECK-NEXT:  L..tmp2:
+; CHECK-NEXT:lwarx 6, 0, 3
+; CHECK-NEXT:cmpw 4, 6
+; CHECK-NEXT:bne- 0, L..tmp3
+; CHECK-NEXT:stwcx. 5, 0, 3
+; CHECK-NEXT:bne- 0, L..tmp2
+; CHECK-NEXT:  L..tmp3:
+
+; NOIS-LABEL: NoBarrier_CompareAndSwapExtMne:
+; NOIS:#APP
+; NOIS-NEXT: 1: lwarx 6, 0, 3
+; NOIS-NEXT:cmpw 4, 6
+; NOIS-NEXT:bne- 2f
+; NOIS-NEXT:stwcx. 5, 0, 3
+; NOIS-NEXT:bne- 1b
+; NOIS-NEXT: 2:
+
+entry:
+  %ptr.addr = alloca i32*, align 8 

   %old_value.addr = alloca i32, align 4
+  %new_value.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32* %ptr, i32** %ptr.addr, align 8
+  store i32 %old_value, i32* %old_value.addr, align 4
+  store i32 %new_value, i32* %new_value.addr, align 4
+  %0 = load i32*, i32** %ptr.addr, align 8
+  %1 = load i32, i32* %old_value.addr, align 4
+  %2 = load i32, i32* %new_value.addr, align 4
+  %3 = call i32 asm sideeffect "1: lwarx $0, $4, $1, 0   \0A\09   cmpw 
$2, $0 \0A\09   bne- 2f \0A\09   
stwcx. $3, $4, $1  \0A\09   bne- 1b \0A\092:
 \0A\09", "=&b,b,b,b,i,~{cr0},~{ctr}"(i32* %0, i32 
%1, i32 %2, i32 0)
+  store i32 %3, i32* %result, align 4
+  %4 = load i32, i32* %result, align 4
+  ret i32 %4
+}
+

diff  --git a/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s 
b/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
index 447542fba672e..bd50e2321ffdf 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
@@ -130,18 +130,34 @@
 # CHECK-LE: lbarx 2, 3, 4   # encoding: [0x68,0x20,0x43,0x7c]
 lbarx 2, 3, 4
 
+# CHECK-BE: lbarx 2, 3, 4   # encoding: [0x7c,0x43,0x20,0x68]
+# CHECK-LE: lbarx 2, 3, 4   # encoding: [0x68,0

[llvm-branch-commits] [llvm] ce69b89 - [llvm][docs] Describe how to work with patch series on Phabricator

[llvm-branch-commits] [llvm] 87ca22c - [Support] Attempt to fix deadlock in ThreadGroup

[llvm-branch-commits] [lld] e68f640 - [ELF][PPC32] Make R_PPC32_PLTREL retain .got

[llvm-branch-commits] [llvm] 9fb79e6 - [PowerPC] Handle base load with reservation mnemonic

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