[llvm-branch-commits] [clang-tools-extra] 979228f - [clangd][fuzzyFind] Do not show stale symbols in the result.

[Aleksandr Platonov via llvm-branch-commits]

Author: Aleksandr Platonov
Date: 2021-01-06T11:17:12+03:00
New Revision: 979228f120f4aa1265648b1c06f65a84bcca1ed6

URL: 
https://github.com/llvm/llvm-project/commit/979228f120f4aa1265648b1c06f65a84bcca1ed6
DIFF: 
https://github.com/llvm/llvm-project/commit/979228f120f4aa1265648b1c06f65a84bcca1ed6.diff

LOG: [clangd][fuzzyFind] Do not show stale symbols in the result.

This is follow up to D93393.
Without this patch `MergedIndex::fuzzyFind()` returns stale symbols from the 
static index even if these symbols were removed.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D93796

Added: 


Modified: 
clang-tools-extra/clangd/index/Merge.cpp
clang-tools-extra/clangd/index/Merge.h
clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
clang-tools-extra/clangd/unittests/IndexTests.cpp

Removed: 




diff  --git a/clang-tools-extra/clangd/index/Merge.cpp 
b/clang-tools-extra/clangd/index/Merge.cpp
index f66f47499624..29174ff0d354 100644
--- a/clang-tools-extra/clangd/index/Merge.cpp
+++ b/clang-tools-extra/clangd/index/Merge.cpp
@@ -22,11 +22,6 @@
 namespace clang {
 namespace clangd {
 
-// FIXME: Deleted symbols in dirty files are still returned (from Static).
-//To identify these eliminate these, we should:
-//  - find the generating file from each Symbol which is Static-only
-//  - ask Dynamic if it has that file (needs new SymbolIndex method)
-//  - if so, drop the Symbol.
 bool MergedIndex::fuzzyFind(
 const FuzzyFindRequest &Req,
 llvm::function_ref Callback) const {
@@ -49,7 +44,13 @@ bool MergedIndex::fuzzyFind(
   SymbolSlab Dyn = std::move(DynB).build();
 
   llvm::DenseSet SeenDynamicSymbols;
+  auto DynamicContainsFile = Dynamic->indexedFiles();
   More |= Static->fuzzyFind(Req, [&](const Symbol &S) {
+// We expect the definition to see the canonical declaration, so it seems
+// to be enough to check only the definition if it exists.
+if (DynamicContainsFile(S.Definition ? S.Definition.FileURI
+ : S.CanonicalDeclaration.FileURI))
+  return;
 auto DynS = Dyn.find(S.ID);
 ++StaticCount;
 if (DynS == Dyn.end())

diff  --git a/clang-tools-extra/clangd/index/Merge.h 
b/clang-tools-extra/clangd/index/Merge.h
index 0cdff38f0678..f8696b460c90 100644
--- a/clang-tools-extra/clangd/index/Merge.h
+++ b/clang-tools-extra/clangd/index/Merge.h
@@ -23,10 +23,6 @@ Symbol mergeSymbol(const Symbol &L, const Symbol &R);
 //  - the Dynamic index covers few files, but is relatively up-to-date.
 //  - the Static index covers a bigger set of files, but is relatively stale.
 // The returned index attempts to combine results, and avoid duplicates.
-//
-// FIXME: We don't have a mechanism in Index to track deleted symbols and
-// refs in dirty files, so the merged index may return stale symbols
-// and refs from Static index.
 class MergedIndex : public SymbolIndex {
   const SymbolIndex *Dynamic, *Static;
 

diff  --git a/clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp 
b/clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
index 43658284937e..bdd3ddca1a61 100644
--- a/clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
@@ -52,7 +52,17 @@ std::vector getSymbols(TestTU &TU, 
llvm::StringRef Query,
   return *SymbolInfos;
 }
 
-TEST(WorkspaceSymbols, Macros) {
+// FIXME: We update two indexes during main file processing:
+//- preamble index (static)
+//- main-file index (dynamic)
+//The macro in this test appears to be in the preamble index and not
+//in the main-file index. According to our logic of indexes merging, we
+//do not take this macro from the static (preamble) index, because it
+//location within the file from the dynamic (main-file) index.
+//
+//Possible solution is to exclude main-file symbols from the preamble
+//index, after that we can enable this test again.
+TEST(WorkspaceSymbols, DISABLED_Macros) {
   TestTU TU;
   TU.Code = R"cpp(
#define MACRO X

diff  --git a/clang-tools-extra/clangd/unittests/IndexTests.cpp 
b/clang-tools-extra/clangd/unittests/IndexTests.cpp
index ce4845e3e144..33b0414275ca 100644
--- a/clang-tools-extra/clangd/unittests/IndexTests.cpp
+++ b/clang-tools-extra/clangd/unittests/IndexTests.cpp
@@ -335,6 +335,39 @@ TEST(MergeIndexTest, FuzzyFind) {
   UnorderedElementsAre("ns::A", "ns::B", "ns::C"));
 }
 
+TEST(MergeIndexTest, FuzzyFindRemovedSymbol) {
+  FileIndex DynamicIndex, StaticIndex;
+  MergedIndex Merge(&DynamicIndex, &StaticIndex);
+
+  const char *HeaderCode = "class Foo;";
+  auto HeaderSymbols = TestTU::withHeaderCode(HeaderCode).headerSymbols();
+  auto Foo = findSymbol(HeaderSymbols, "Foo");
+
+  // Build static index for test.cc with Foo symbol
+  TestTU Test;
+  Test.HeaderCode = 

[llvm-branch-commits] [llvm] 30d314a - [MC][WebAssembly] Avoid recalculating indexes in -gsplit-dwarf mode

[Sam Clegg via llvm-branch-commits]

Author: Sam Clegg
Date: 2021-01-06T01:35:06-08:00
New Revision: 30d314aae10eee1e66aff6515a764ee696a03e8d

URL: 
https://github.com/llvm/llvm-project/commit/30d314aae10eee1e66aff6515a764ee696a03e8d
DIFF: 
https://github.com/llvm/llvm-project/commit/30d314aae10eee1e66aff6515a764ee696a03e8d.diff

LOG: [MC][WebAssembly] Avoid recalculating indexes in -gsplit-dwarf mode

Be consistent about asserting before setting WasmIndices.  Adding
these assertions revealed that we were duplicating a lot of work
and setting these indexed twice when running in DWO mode.

Differential Revision: https://reviews.llvm.org/D93650

Added: 


Modified: 
llvm/lib/MC/WasmObjectWriter.cpp

Removed: 




diff  --git a/llvm/lib/MC/WasmObjectWriter.cpp 
b/llvm/lib/MC/WasmObjectWriter.cpp
index 683678b70ebc..112c5b3f120b 100644
--- a/llvm/lib/MC/WasmObjectWriter.cpp
+++ b/llvm/lib/MC/WasmObjectWriter.cpp
@@ -1212,6 +1212,7 @@ static bool isInSymtab(const MCSymbolWasm &Sym) {
 
   return true;
 }
+
 void WasmObjectWriter::prepareImports(
 SmallVectorImpl &Imports, MCAssembler &Asm,
 const MCAsmLayout &Layout) {
@@ -1363,6 +1364,7 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler 
&Asm,
   if (Mode != DwoMode::DwoOnly) {
 prepareImports(Imports, Asm, Layout);
   }
+
   // Populate DataSegments and CustomSections, which must be done before
   // populating DataLocations.
   for (MCSection &Sec : Asm) {
@@ -1417,6 +1419,7 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler 
&Asm,
 
   MCSymbol *Begin = Sec.getBeginSymbol();
   if (Begin) {
+assert(WasmIndices.count(cast(Begin)) == 0);
 WasmIndices[cast(Begin)] = CustomSections.size();
   }
 
@@ -1445,214 +1448,218 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler 
&Asm,
 }
   }
 
-  // Populate WasmIndices and DataLocations for defined symbols.
-  for (const MCSymbol &S : Asm.symbols()) {
-// Ignore unnamed temporary symbols, which aren't ever exported, imported,
-// or used in relocations.
-if (S.isTemporary() && S.getName().empty())
-  continue;
+  if (Mode != DwoMode::DwoOnly) {
+// Populate WasmIndices and DataLocations for defined symbols.
+for (const MCSymbol &S : Asm.symbols()) {
+  // Ignore unnamed temporary symbols, which aren't ever exported, 
imported,
+  // or used in relocations.
+  if (S.isTemporary() && S.getName().empty())
+continue;
 
-const auto &WS = static_cast(S);
-LLVM_DEBUG(
-dbgs() << "MCSymbol: " << toString(WS.getType()) << " '" << S << "'"
-   << " isDefined=" << S.isDefined() << " isExternal="
-   << S.isExternal() << " isTemporary=" << S.isTemporary()
-   << " isWeak=" << WS.isWeak() << " isHidden=" << WS.isHidden()
-   << " isVariable=" << WS.isVariable() << "\n");
-
-if (WS.isVariable())
-  continue;
-if (WS.isComdat() && !WS.isDefined())
-  continue;
+  const auto &WS = static_cast(S);
+  LLVM_DEBUG(
+  dbgs() << "MCSymbol: " << toString(WS.getType()) << " '" << S << "'"
+ << " isDefined=" << S.isDefined() << " isExternal="
+ << S.isExternal() << " isTemporary=" << S.isTemporary()
+ << " isWeak=" << WS.isWeak() << " isHidden=" << WS.isHidden()
+ << " isVariable=" << WS.isVariable() << "\n");
 
-if (WS.isFunction()) {
-  unsigned Index;
-  if (WS.isDefined()) {
-if (WS.getOffset() != 0)
-  report_fatal_error(
-  "function sections must contain one function each");
-
-if (WS.getSize() == nullptr)
-  report_fatal_error(
-  "function symbols must have a size set with .size");
-
-// A definition. Write out the function body.
-Index = NumFunctionImports + Functions.size();
-WasmFunction Func;
-Func.SigIndex = getFunctionType(WS);
-Func.Sym = &WS;
-WasmIndices[&WS] = Index;
-Functions.push_back(Func);
-
-auto &Section = static_cast(WS.getSection());
-if (const MCSymbolWasm *C = Section.getGroup()) {
-  Comdats[C->getName()].emplace_back(
-  WasmComdatEntry{wasm::WASM_COMDAT_FUNCTION, Index});
+  if (WS.isVariable())
+continue;
+  if (WS.isComdat() && !WS.isDefined())
+continue;
+
+  if (WS.isFunction()) {
+unsigned Index;
+if (WS.isDefined()) {
+  if (WS.getOffset() != 0)
+report_fatal_error(
+"function sections must contain one function each");
+
+  if (WS.getSize() == nullptr)
+report_fatal_error(
+"function symbols must have a size set with .size");
+
+  // A definition. Write out the function body.
+  Index = NumFunctionImports + Functions.size();
+  WasmFunction Func;
+  Func.SigIndex = getFunctionType(WS);

[llvm-branch-commits] [llvm] a9f5e43 - [AArch64] Use faddp to implement fadd reductions.

[Sander de Smalen via llvm-branch-commits]

Author: Sander de Smalen
Date: 2021-01-06T09:36:51Z
New Revision: a9f5e4375b36e5316b8d6f9731be6bfa5a70e276

URL: 
https://github.com/llvm/llvm-project/commit/a9f5e4375b36e5316b8d6f9731be6bfa5a70e276
DIFF: 
https://github.com/llvm/llvm-project/commit/a9f5e4375b36e5316b8d6f9731be6bfa5a70e276.diff

LOG: [AArch64] Use faddp to implement fadd reductions.

Custom-expand legal VECREDUCE_FADD SDNodes
to benefit from pair-wise faddp instructions.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D59259

Added: 


Modified: 
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

Removed: 




diff  --git a/llvm/include/llvm/Target/TargetSelectionDAG.td 
b/llvm/include/llvm/Target/TargetSelectionDAG.td
index d5b8aeb1055d..0c6eef939ea4 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -250,6 +250,10 @@ def SDTVecInsert : SDTypeProfile<1, 3, [// vector 
insert
 def SDTVecReduce : SDTypeProfile<1, 1, [// vector reduction
   SDTCisInt<0>, SDTCisVec<1>
 ]>;
+def SDTFPVecReduce : SDTypeProfile<1, 1, [  // FP vector reduction
+  SDTCisFP<0>, SDTCisVec<1>
+]>;
+
 
 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
   SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
@@ -439,6 +443,7 @@ def vecreduce_smax  : SDNode<"ISD::VECREDUCE_SMAX", 
SDTVecReduce>;
 def vecreduce_umax  : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>;
 def vecreduce_smin  : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
 def vecreduce_umin  : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
+def vecreduce_fadd  : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>;
 
 def fadd   : SDNode<"ISD::FADD"   , SDTFPBinOp, [SDNPCommutative]>;
 def fsub   : SDNode<"ISD::FSUB"   , SDTFPBinOp>;

diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index faed7c64a15e..2b9dc84a06cc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -999,6 +999,9 @@ AArch64TargetLowering::AArch64TargetLowering(const 
TargetMachine &TM,
 MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
   setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
   setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
+
+  if (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16())
+setOperationAction(ISD::VECREDUCE_FADD, VT, Legal);
 }
 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
 MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {

diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td 
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 4d70fb334828..7e9f2fb95188 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4989,6 +4989,26 @@ defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, 
"fmaxnmp">;
 defm FMAXP   : SIMDFPPairwiseScalar<0, 0b0, "fmaxp">;
 defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">;
 defm FMINP   : SIMDFPPairwiseScalar<1, 0b0, "fminp">;
+
+let Predicates = [HasFullFP16] in {
+def : Pat<(f16 (vecreduce_fadd (v8f16 V128:$Rn))),
+(FADDPv2i16p
+  (EXTRACT_SUBREG
+ (FADDPv8f16 (FADDPv8f16 V128:$Rn, (v8f16 (IMPLICIT_DEF))), 
(v8f16 (IMPLICIT_DEF))),
+   dsub))>;
+def : Pat<(f16 (vecreduce_fadd (v4f16 V64:$Rn))),
+  (FADDPv2i16p (FADDPv4f16 V64:$Rn, (v4f16 (IMPLICIT_DEF>;
+}
+def : Pat<(f32 (vecreduce_fadd (v4f32 V128:$Rn))),
+  (FADDPv2i32p
+(EXTRACT_SUBREG
+  (FADDPv4f32 V128:$Rn, (v4f32 (IMPLICIT_DEF))),
+ dsub))>;
+def : Pat<(f32 (vecreduce_fadd (v2f32 V64:$Rn))),
+  (FADDPv2i32p V64:$Rn)>;
+def : Pat<(f64 (vecreduce_fadd (v2f64 V128:$Rn))),
+  (FADDPv2i64p V128:$Rn)>;
+
 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
   (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),

diff  --git a/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll 
b/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
index 69b9c3e22d7a..2b5fcd4b839a 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
@@ -51,8 +51,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
 ; CHECK-NEXT:mov w8, #-2147483648
 ; CHECK-NEXT:fmov s1, w8
 ; CHECK-NEXT:mov v0.s[3], v1.s[0]
-; CHECK-NEXT:ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:fadd v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:faddp v0.4s, v0.4s, v0.4s
 ; CHECK-NEXT:faddp s0, v0.2s
 ; CHECK-NEXT:ret
   %b = call reassoc float @l

[llvm-branch-commits] [llvm] a7e3339 - [AArch64][SVE] Emit DWARF location expression for SVE stack objects.

[Sander de Smalen via llvm-branch-commits]

Author: Sander de Smalen
Date: 2021-01-06T09:40:53Z
New Revision: a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf

URL: 
https://github.com/llvm/llvm-project/commit/a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf
DIFF: 
https://github.com/llvm/llvm-project/commit/a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf.diff

LOG: [AArch64][SVE] Emit DWARF location expression for SVE stack objects.

Extend PEI to emit a DWARF expression for StackOffsets that have
a fixed and scalable component. This means the expression that needs
to be added is either:
   + offset
or:
   + offset + scalable_offset * scalereg

where for SVE, the scale reg is the Vector Granule Dwarf register, which
encodes the number of 64bit 'granules' in an SVE vector and which
the debugger can evaluate at runtime.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D90020

Added: 
llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

Modified: 
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.h

Removed: 




diff  --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h 
b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index de2c1b069784..6f32729a1e83 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -34,6 +34,7 @@
 namespace llvm {
 
 class BitVector;
+class DIExpression;
 class LiveRegMatrix;
 class MachineFunction;
 class MachineInstr;
@@ -923,6 +924,15 @@ class TargetRegisterInfo : public MCRegisterInfo {
 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
   }
 
+  /// Gets the DWARF expression opcodes for \p Offset.
+  virtual void getOffsetOpcodes(const StackOffset &Offset,
+SmallVectorImpl &Ops) const;
+
+  /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
+  DIExpression *
+  prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
+  const StackOffset &Offset) const;
+
   /// Spill the register so it can be used by the register scavenger.
   /// Return true if the register was spilled, false otherwise.
   /// If this function does not spill the register, the scavenger

diff  --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp 
b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 7c38b193a980..65b2165bf2a0 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1211,8 +1211,6 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, 
MachineFunction &MF,
 
 StackOffset Offset =
 TFI->getFrameIndexReference(MF, FrameIdx, Reg);
-assert(!Offset.getScalable() &&
-   "Frame offsets with a scalable component are not supported");
 MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
 MI.getOperand(0).setIsDebug();
 
@@ -1238,7 +1236,8 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, 
MachineFunction &MF,
   // Make the DBG_VALUE direct.
   MI.getDebugOffset().ChangeToRegister(0, false);
 }
-DIExpr = DIExpression::prepend(DIExpr, PrependFlags, 
Offset.getFixed());
+
+DIExpr = TRI.prependOffsetExpression(DIExpr, PrependFlags, Offset);
 MI.getDebugExpressionOp().setMetadata(DIExpr);
 continue;
   }

diff  --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp 
b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index e89353c9ad27..4a190c9f50af 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -26,6 +26,7 @@
 #include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/IR/Attributes.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
@@ -532,6 +533,31 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
   }
 }
 
+void TargetRegisterInfo::getOffsetOpcodes(
+const StackOffset &Offset, SmallVectorImpl &Ops) const {
+  assert(!Offset.getScalable() && "Scalable offsets are not handled");
+  DIExpression::appendOffset(Ops, Offset.getFixed());
+}
+
+DIExpression *
+TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
+unsigned PrependFlags,
+const StackOffset &Offset) const {
+  assert((PrependFlags &
+  ~(DIExpression::DerefBefore | DIExpression::DerefAfter |
+DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
+ "Unsupported prepend flag");
+  SmallVector OffsetExpr;
+  if (PrependFlags & DIExpression::DerefBefore)
+OffsetExpr.push_back(dwarf::DW_OP_deref);
+  getOffsetOpcodes(Offset, OffsetExpr);
+  if (PrependFlags & D

[llvm-branch-commits] [llvm] 78d8a82 - [AArch64] Handle any extend whilst lowering mull

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-06T10:08:43Z
New Revision: 78d8a821e23e42d13dcbb3467747e480fb889b8a

URL: 
https://github.com/llvm/llvm-project/commit/78d8a821e23e42d13dcbb3467747e480fb889b8a
DIFF: 
https://github.com/llvm/llvm-project/commit/78d8a821e23e42d13dcbb3467747e480fb889b8a.diff

LOG: [AArch64] Handle any extend whilst lowering mull

Demanded bits may turn a sext or zext into an anyext if the top bits are
not needed. This currently prevents the lowering to instructions like
mull, addl and addw. This patch fixes the mull generation by keeping it
simple and treating them like zextends.

Differential Revision: https://reviews.llvm.org/D93832

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/aarch64-smull.ll
llvm/test/CodeGen/AArch64/lowerMUL-newload.ll

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2b9dc84a06cc..41dc285a368d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3347,7 +3347,8 @@ static bool isExtendedBUILD_VECTOR(SDNode *N, 
SelectionDAG &DAG,
 }
 
 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
-  if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
+  if (N->getOpcode() == ISD::SIGN_EXTEND ||
+  N->getOpcode() == ISD::ZERO_EXTEND || N->getOpcode() == ISD::ANY_EXTEND)
 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
  N->getOperand(0)->getValueType(0),
  N->getValueType(0),
@@ -3377,6 +3378,7 @@ static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
 
 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
   return N->getOpcode() == ISD::ZERO_EXTEND ||
+ N->getOpcode() == ISD::ANY_EXTEND ||
  isExtendedBUILD_VECTOR(N, DAG, false);
 }
 

diff  --git a/llvm/test/CodeGen/AArch64/aarch64-smull.ll 
b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
index 17a21e566ec4..0a692192ec8b 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
@@ -96,9 +96,7 @@ define <8 x i16> @amull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* 
%B) nounwind {
 ; CHECK:   // %bb.0:
 ; CHECK-NEXT:ldr d0, [x0]
 ; CHECK-NEXT:ldr d1, [x1]
-; CHECK-NEXT:ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:ushll v1.8h, v1.8b, #0
-; CHECK-NEXT:mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:umull v0.8h, v0.8b, v1.8b
 ; CHECK-NEXT:bic v0.8h, #255, lsl #8
 ; CHECK-NEXT:ret
   %tmp1 = load <8 x i8>, <8 x i8>* %A
@@ -115,9 +113,7 @@ define <4 x i32> @amull_v4i16_v4i32(<4 x i16>* %A, <4 x 
i16>* %B) nounwind {
 ; CHECK:   // %bb.0:
 ; CHECK-NEXT:ldr d0, [x0]
 ; CHECK-NEXT:ldr d1, [x1]
-; CHECK-NEXT:ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:ushll v1.4s, v1.4h, #0
-; CHECK-NEXT:mul v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:umull v0.4s, v0.4h, v1.4h
 ; CHECK-NEXT:movi v1.2d, #0x00
 ; CHECK-NEXT:and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:ret
@@ -135,16 +131,7 @@ define <2 x i64> @amull_v2i32_v2i64(<2 x i32>* %A, <2 x 
i32>* %B) nounwind {
 ; CHECK:   // %bb.0:
 ; CHECK-NEXT:ldr d0, [x0]
 ; CHECK-NEXT:ldr d1, [x1]
-; CHECK-NEXT:ushll v0.2d, v0.2s, #0
-; CHECK-NEXT:ushll v1.2d, v1.2s, #0
-; CHECK-NEXT:fmov x10, d1
-; CHECK-NEXT:fmov x11, d0
-; CHECK-NEXT:mov x8, v1.d[1]
-; CHECK-NEXT:mov x9, v0.d[1]
-; CHECK-NEXT:mul x10, x11, x10
-; CHECK-NEXT:mul x8, x9, x8
-; CHECK-NEXT:fmov d0, x10
-; CHECK-NEXT:mov v0.d[1], x8
+; CHECK-NEXT:umull v0.2d, v0.2s, v1.2s
 ; CHECK-NEXT:movi v1.2d, #0x00
 ; CHECK-NEXT:and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:ret
@@ -268,12 +255,10 @@ define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x 
i32>* %B, <2 x i32>* %C)
 define <8 x i16> @amlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) 
nounwind {
 ; CHECK-LABEL: amlal_v8i8_v8i16:
 ; CHECK:   // %bb.0:
+; CHECK-NEXT:ldr q0, [x0]
 ; CHECK-NEXT:ldr d1, [x1]
 ; CHECK-NEXT:ldr d2, [x2]
-; CHECK-NEXT:ldr q0, [x0]
-; CHECK-NEXT:ushll v1.8h, v1.8b, #0
-; CHECK-NEXT:ushll v2.8h, v2.8b, #0
-; CHECK-NEXT:mla v0.8h, v1.8h, v2.8h
+; CHECK-NEXT:umlal v0.8h, v1.8b, v2.8b
 ; CHECK-NEXT:bic v0.8h, #255, lsl #8
 ; CHECK-NEXT:ret
   %tmp1 = load <8 x i16>, <8 x i16>* %A
@@ -290,14 +275,12 @@ define <8 x i16> @amlal_v8i8_v8i16(<8 x i16>* %A, <8 x 
i8>* %B, <8 x i8>* %C) no
 define <4 x i32> @amlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* 
%C) nounwind {
 ; CHECK-LABEL: amlal_v4i16_v4i32:
 ; CHECK:   // %bb.0:
-; CHECK-NEXT:ldr d0, [x1]
-; CHECK-NEXT:ldr d1, [x2]
-; CHECK-NEXT:ldr q2, [x0]
-; CHECK-NEXT:ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:ushll

[llvm-branch-commits] [flang] e49dc29 - [flang][driver] Add checks for errors from `Prescan` and `Parse`

[Andrzej Warzynski via llvm-branch-commits]

Author: Andrzej Warzynski
Date: 2021-01-06T10:19:44Z
New Revision: e49dc2981cb311ac2b696ebb016fac9a8cd60922

URL: 
https://github.com/llvm/llvm-project/commit/e49dc2981cb311ac2b696ebb016fac9a8cd60922
DIFF: 
https://github.com/llvm/llvm-project/commit/e49dc2981cb311ac2b696ebb016fac9a8cd60922.diff

LOG: [flang][driver] Add checks for errors from `Prescan` and `Parse`

If either `Prescan` or `Parse` generate any fatal errors, the new driver
will:
  * report it (i.e. issue an error diagnostic)
  * exit early
  * return non-zero exit code
This behaviour is consistent with f18 (i.e. the old driver).

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D93712

Added: 
flang/test/Flang-Driver/parse-error.f95
flang/test/Flang-Driver/scanning-error.f95

Modified: 
flang/lib/Frontend/FrontendAction.cpp
flang/lib/Frontend/FrontendActions.cpp

Removed: 




diff  --git a/flang/lib/Frontend/FrontendAction.cpp 
b/flang/lib/Frontend/FrontendAction.cpp
index ad1079d47db1..4972669bec87 100644
--- a/flang/lib/Frontend/FrontendAction.cpp
+++ b/flang/lib/Frontend/FrontendAction.cpp
@@ -45,12 +45,24 @@ bool FrontendAction::ShouldEraseOutputFiles() {
 }
 
 llvm::Error FrontendAction::Execute() {
+  CompilerInstance &ci = this->instance();
+
   std::string currentInputPath{GetCurrentFileOrBufferName()};
 
   Fortran::parser::Options parserOptions =
   this->instance().invocation().fortranOpts();
 
-  this->instance().parsing().Prescan(currentInputPath, parserOptions);
+  // Prescan. In case of failure, report and return.
+  ci.parsing().Prescan(currentInputPath, parserOptions);
+
+  if (ci.parsing().messages().AnyFatalError()) {
+const unsigned diagID = ci.diagnostics().getCustomDiagID(
+clang::DiagnosticsEngine::Error, "could not scan %0");
+ci.diagnostics().Report(diagID) << GetCurrentFileOrBufferName();
+ci.parsing().messages().Emit(llvm::errs(), ci.allCookedSources());
+
+return llvm::Error::success();
+  }
 
   ExecuteAction();
 

diff  --git a/flang/lib/Frontend/FrontendActions.cpp 
b/flang/lib/Frontend/FrontendActions.cpp
index b34dae7cbf17..fe21fc5e3d2e 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -78,8 +78,19 @@ void ParseSyntaxOnlyAction::ExecuteAction() {
   common::LanguageFeatureControl features;
   Fortran::common::IntrinsicTypeDefaultKinds defaultKinds;
 
-  // Parse
+  // Parse. In case of failure, report and return.
   ci.parsing().Parse(llvm::outs());
+
+  if (ci.parsing().messages().AnyFatalError()) {
+unsigned diagID = ci.diagnostics().getCustomDiagID(
+clang::DiagnosticsEngine::Error, "could not parse %0");
+ci.diagnostics().Report(diagID) << GetCurrentFileOrBufferName();
+
+ci.parsing().messages().Emit(
+llvm::errs(), this->instance().allCookedSources());
+return;
+  }
+
   auto &parseTree{*ci.parsing().parseTree()};
 
   // Prepare semantics

diff  --git a/flang/test/Flang-Driver/parse-error.f95 
b/flang/test/Flang-Driver/parse-error.f95
new file mode 100644
index ..34af7e2d2ed6
--- /dev/null
+++ b/flang/test/Flang-Driver/parse-error.f95
@@ -0,0 +1,8 @@
+! RUN: not %flang-new -fc1 -fsyntax-only %s 2>&1 | FileCheck %s 
--check-prefix=ERROR
+! RUN: not %f18 -parse-only %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+! REQUIRES: new-flang-driver
+
+! ERROR: could not parse {{.*}}parse-error.f95
+
+"This file will not parse"

diff  --git a/flang/test/Flang-Driver/scanning-error.f95 
b/flang/test/Flang-Driver/scanning-error.f95
new file mode 100644
index ..5fcf89d569c1
--- /dev/null
+++ b/flang/test/Flang-Driver/scanning-error.f95
@@ -0,0 +1,8 @@
+! RUN: not %flang-new -fc1 -E %s 2>&1 | FileCheck %s --check-prefix=ERROR
+! RUN: not %f18 -E %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+! REQUIRES: new-flang-driver
+
+! ERROR: could not scan {{.*}}scanning-error.f95
+
+#NOT-PP-DIRECTIVE



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[llvm-branch-commits] [compiler-rt] 4839378 - Revert "[sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX feature detection and support musl"

[Oliver Stannard via llvm-branch-commits]

Author: Oliver Stannard
Date: 2021-01-06T10:31:59Z
New Revision: 4839378ca05f88faed53ea25457fd93fcad93460

URL: 
https://github.com/llvm/llvm-project/commit/4839378ca05f88faed53ea25457fd93fcad93460
DIFF: 
https://github.com/llvm/llvm-project/commit/4839378ca05f88faed53ea25457fd93fcad93460.diff

LOG: Revert "[sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX 
feature detection and support musl"

This reverts commit b7718b617557aa9827f994a16267537236634095, because it
is causing build failures on all 32-bit ARM bots which build
compiler-rt.

Added: 


Modified: 
compiler-rt/cmake/Modules/AddCompilerRT.cmake
compiler-rt/lib/asan/asan_interceptors.h
compiler-rt/lib/asan/tests/asan_test.cpp
compiler-rt/lib/interception/interception_linux.cpp
compiler-rt/lib/interception/interception_linux.h
compiler-rt/lib/msan/tests/msan_test.cpp
compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
compiler-rt/lib/sanitizer_common/sanitizer_platform.h
compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp

Removed: 




diff  --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake 
b/compiler-rt/cmake/Modules/AddCompilerRT.cmake
index 361538a58e47..0b8db6a868a1 100644
--- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake
+++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake
@@ -583,7 +583,6 @@ macro(add_custom_libcxx name prefix)
 CMAKE_OBJDUMP
 CMAKE_STRIP
 CMAKE_SYSROOT
-LIBCXX_HAS_MUSL_LIBC
 PYTHON_EXECUTABLE
 Python3_EXECUTABLE
 Python2_EXECUTABLE

diff  --git a/compiler-rt/lib/asan/asan_interceptors.h 
b/compiler-rt/lib/asan/asan_interceptors.h
index 45cdb80b1b64..4266a31cecb9 100644
--- a/compiler-rt/lib/asan/asan_interceptors.h
+++ b/compiler-rt/lib/asan/asan_interceptors.h
@@ -60,7 +60,7 @@ void InitializePlatformInterceptors();
 # define ASAN_USE_ALIAS_ATTRIBUTE_FOR_INDEX 0
 #endif
 
-#if SANITIZER_GLIBC || SANITIZER_SOLARIS
+#if (SANITIZER_LINUX && !SANITIZER_ANDROID) || SANITIZER_SOLARIS
 # define ASAN_INTERCEPT_SWAPCONTEXT 1
 #else
 # define ASAN_INTERCEPT_SWAPCONTEXT 0
@@ -72,7 +72,7 @@ void InitializePlatformInterceptors();
 # define ASAN_INTERCEPT_SIGLONGJMP 0
 #endif
 
-#if SANITIZER_GLIBC
+#if SANITIZER_LINUX && !SANITIZER_ANDROID
 # define ASAN_INTERCEPT___LONGJMP_CHK 1
 #else
 # define ASAN_INTERCEPT___LONGJMP_CHK 0
@@ -106,7 +106,7 @@ void InitializePlatformInterceptors();
 # define ASAN_INTERCEPT_ATEXIT 0
 #endif
 
-#if SANITIZER_GLIBC
+#if SANITIZER_LINUX && !SANITIZER_ANDROID
 # define ASAN_INTERCEPT___STRDUP 1
 #else
 # define ASAN_INTERCEPT___STRDUP 0

diff  --git a/compiler-rt/lib/asan/tests/asan_test.cpp 
b/compiler-rt/lib/asan/tests/asan_test.cpp
index c0b79bba48ff..51a527359b49 100644
--- a/compiler-rt/lib/asan/tests/asan_test.cpp
+++ b/compiler-rt/lib/asan/tests/asan_test.cpp
@@ -804,7 +804,7 @@ char* MallocAndMemsetString(size_t size) {
   return MallocAndMemsetString(size, 'z');
 }
 
-#if SANITIZER_GLIBC
+#if defined(__linux__) && !defined(__ANDROID__)
 #define READ_TEST(READ_N_BYTES)  \
   char *x = new char[10];\
   int fd = open("/proc/self/stat", O_RDONLY);\
@@ -827,7 +827,7 @@ TEST(AddressSanitizer, pread64) {
 TEST(AddressSanitizer, read) {
   READ_TEST(read(fd, x, 15));
 }
-#endif  // SANITIZER_GLIBC
+#endif  // defined(__linux__) && !defined(__ANDROID__)
 
 // This test case fails
 // Clang optimizes memcpy/memset calls which lead to unaligned access

diff  --git a/compiler-rt/lib/interception/interception_linux.cpp 
b/compiler-rt/lib/interception/interception_linux.cpp
index 5111a87f0a6c..6883608d44f3 100644
--- a/compiler-rt/lib/interception/interception_linux.cpp
+++ b/compiler-rt/lib/interception/interception_linux.cpp
@@ -63,8 +63,8 @@ bool InterceptFunction(const char *name, uptr *ptr_to_real, 
uptr func,
   return addr && (func == wrapper);
 }
 
-// dlvsym is a GNU extension supported by some other platforms.
-#if SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD
+// Android and Solaris do not have dlvsym
+#if !SANITIZER_ANDROID && !SANITIZER_SOLARIS
 static void *GetFuncAddr(const char *name, const char *ver) {
   return dlvsym(RTLD_NEXT, name, ver);
 }
@@ -75,7 +75,7 @@ bool InterceptFunction(const char *name, const char *ver, 
uptr *ptr_to_real,
   *ptr_to_real = (uptr)addr;
   return addr && (func == wrapper);
 }
-#endif  // SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD
+#endif  // !SANITIZER_ANDROID
 
 }  // namespace __interception
 

diff  --git a/compiler-rt/lib/interception/interception_linux.h

[llvm-branch-commits] [llvm] a9b6440 - [AArch64] Handle any extend whilst lowering addw/addl/subw/subl

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-06T10:35:23Z
New Revision: a9b6440eddde920920141d8ade9090273271a79b

URL: 
https://github.com/llvm/llvm-project/commit/a9b6440eddde920920141d8ade9090273271a79b
DIFF: 
https://github.com/llvm/llvm-project/commit/a9b6440eddde920920141d8ade9090273271a79b.diff

LOG: [AArch64] Handle any extend whilst lowering addw/addl/subw/subl

This adds an extra tablegen PatFrag, zanyext, which matches either any
extend or zext and uses that in the aarch64 backend to handle any
extends in addw/addl/subw/subl patterns.

Differential Revision: https://reviews.llvm.org/D93833

Added: 


Modified: 
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
llvm/test/CodeGen/AArch64/lowerMUL-newload.ll

Removed: 




diff  --git a/llvm/include/llvm/Target/TargetSelectionDAG.td 
b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 0c6eef939ea4..a1e961aa9cb5 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -920,6 +920,10 @@ def not  : PatFrag<(ops node:$in), (xor node:$in, -1)>;
 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
 
+def zanyext : PatFrags<(ops node:$op),
+   [(zext node:$op),
+(anyext node:$op)]>;
+
 // null_frag - The null pattern operator is used in multiclass instantiations
 // which accept an SDPatternOperator for use in matching patterns for internal
 // definitions. When expanding a pattern, if the null fragment is referenced

diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td 
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 7e9f2fb95188..6209f51b1631 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4765,18 +4765,18 @@ defm SSUBW   : SIMDWideThreeVectorBHS<0, 0b0011, 
"ssubw",
 defm UABAL   : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
   AArch64uabd>;
 defm UADDL   : SIMDLongThreeVectorBHS<1, 0b, "uaddl",
- BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
+ BinOpFrag<(add (zanyext node:$LHS), (zanyext node:$RHS))>>;
 defm UADDW   : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
- BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
+ BinOpFrag<(add node:$LHS, (zanyext node:$RHS))>>;
 defm UMLAL   : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
 defm UMLSL   : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
 defm UMULL   : SIMDLongThreeVectorBHS<1, 0b1100, "umull", 
int_aarch64_neon_umull>;
 defm USUBL   : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
- BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
+ BinOpFrag<(sub (zanyext node:$LHS), (zanyext node:$RHS))>>;
 defm USUBW   : SIMDWideThreeVectorBHS<   1, 0b0011, "usubw",
- BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
+ BinOpFrag<(sub node:$LHS, (zanyext node:$RHS))>>;
 
 // Additional patterns for SMULL and UMULL
 multiclass Neon_mul_widen_patterns @test_vaddl_a8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vaddl_a8:
 ; CHECK:   // %bb.0: // %entry
-; CHECK-NEXT:ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:ushll v1.8h, v1.8b, #0
-; CHECK-NEXT:add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:uaddl v0.8h, v0.8b, v1.8b
 ; CHECK-NEXT:bic v0.8h, #255, lsl #8
 ; CHECK-NEXT:ret
 entry:
@@ -119,9 +117,7 @@ entry:
 define <4 x i32> @test_vaddl_a16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vaddl_a16:
 ; CHECK:   // %bb.0: // %entry
-; CHECK-NEXT:ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:ushll v1.4s, v1.4h, #0
-; CHECK-NEXT:add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:uaddl v0.4s, v0.4h, v1.4h
 ; CHECK-NEXT:movi v1.2d, #0x00
 ; CHECK-NEXT:and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:ret
@@ -136,9 +132,7 @@ entry:
 define <2 x i64> @test_vaddl_a32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vaddl_a32:
 ; CHECK:   // %bb.0: // %entry
-; CHECK-NEXT:ushll v0.2d, v0.2s, #0
-; CHECK-NEXT:ushll v1.2d, v1.2s, #0
-; CHECK-NEXT:add v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:uaddl v0.2d, v0.2s, v1.2s
 ; CHECK-NEXT:movi v1.2d, #0x00
 ; CHECK-NEXT:and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:ret
@@ -237,9 +231,7 @@ entry:
 define <8 x i16> @test_vaddl_high_a8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vaddl_high_a8:
 ; CHECK:   // %bb.0: // %entry
-; CHECK-NEXT:ushll2 v0.8h, v0.16b, #0
-; CHECK-NEXT:ushll2 v1.8h, v1.16b, #0
-; CHECK-NEXT:add v0.8h, v0.8h, v1.8h
+; CHE

[llvm-branch-commits] [flang] fa1e543 - [flang][driver] Update error messages (nfc)

[Andrzej Warzynski via llvm-branch-commits]

Author: Andrzej Warzynski
Date: 2021-01-06T10:41:27Z
New Revision: fa1e543e0b8c625bf2625598d9a16c484e349884

URL: 
https://github.com/llvm/llvm-project/commit/fa1e543e0b8c625bf2625598d9a16c484e349884
DIFF: 
https://github.com/llvm/llvm-project/commit/fa1e543e0b8c625bf2625598d9a16c484e349884.diff

LOG: [flang][driver] Update error messages (nfc)

As per Flang's coding guidelines
(flang/docs/C++style.md#error-messages):
```
Messages should start with a capital letter.
```

This patch updates error messages in the driver (new and old) so that
they conform with the guideline above.

This change was suggested in one of the recent reviews:
https://reviews.llvm.org/D93712. It felt like this deserved a dedicated
patch, so sending it separately.

Added: 


Modified: 
flang/lib/Frontend/FrontendAction.cpp
flang/lib/Frontend/FrontendActions.cpp
flang/test/Flang-Driver/parse-error.f95
flang/test/Flang-Driver/scanning-error.f95
flang/test/Flang-Driver/syntax-only.f90
flang/tools/f18/f18.cpp

Removed: 




diff  --git a/flang/lib/Frontend/FrontendAction.cpp 
b/flang/lib/Frontend/FrontendAction.cpp
index 4972669bec87..4d8a9d43d114 100644
--- a/flang/lib/Frontend/FrontendAction.cpp
+++ b/flang/lib/Frontend/FrontendAction.cpp
@@ -57,7 +57,7 @@ llvm::Error FrontendAction::Execute() {
 
   if (ci.parsing().messages().AnyFatalError()) {
 const unsigned diagID = ci.diagnostics().getCustomDiagID(
-clang::DiagnosticsEngine::Error, "could not scan %0");
+clang::DiagnosticsEngine::Error, "Could not scan %0");
 ci.diagnostics().Report(diagID) << GetCurrentFileOrBufferName();
 ci.parsing().messages().Emit(llvm::errs(), ci.allCookedSources());
 

diff  --git a/flang/lib/Frontend/FrontendActions.cpp 
b/flang/lib/Frontend/FrontendActions.cpp
index fe21fc5e3d2e..acb9988611e6 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -83,7 +83,7 @@ void ParseSyntaxOnlyAction::ExecuteAction() {
 
   if (ci.parsing().messages().AnyFatalError()) {
 unsigned diagID = ci.diagnostics().getCustomDiagID(
-clang::DiagnosticsEngine::Error, "could not parse %0");
+clang::DiagnosticsEngine::Error, "Could not parse %0");
 ci.diagnostics().Report(diagID) << GetCurrentFileOrBufferName();
 
 ci.parsing().messages().Emit(
@@ -107,7 +107,7 @@ void ParseSyntaxOnlyAction::ExecuteAction() {
 
   if (semantics.AnyFatalError()) {
 unsigned DiagID = ci.diagnostics().getCustomDiagID(
-clang::DiagnosticsEngine::Error, "semantic errors in %0");
+clang::DiagnosticsEngine::Error, "Semantic errors in %0");
 ci.diagnostics().Report(DiagID) << GetCurrentFileOrBufferName();
   }
 }

diff  --git a/flang/test/Flang-Driver/parse-error.f95 
b/flang/test/Flang-Driver/parse-error.f95
index 34af7e2d2ed6..84a63665659d 100644
--- a/flang/test/Flang-Driver/parse-error.f95
+++ b/flang/test/Flang-Driver/parse-error.f95
@@ -3,6 +3,6 @@
 
 ! REQUIRES: new-flang-driver
 
-! ERROR: could not parse {{.*}}parse-error.f95
+! ERROR: Could not parse {{.*}}parse-error.f95
 
 "This file will not parse"

diff  --git a/flang/test/Flang-Driver/scanning-error.f95 
b/flang/test/Flang-Driver/scanning-error.f95
index 5fcf89d569c1..dbbd222def08 100644
--- a/flang/test/Flang-Driver/scanning-error.f95
+++ b/flang/test/Flang-Driver/scanning-error.f95
@@ -3,6 +3,6 @@
 
 ! REQUIRES: new-flang-driver
 
-! ERROR: could not scan {{.*}}scanning-error.f95
+! ERROR: Could not scan {{.*}}scanning-error.f95
 
 #NOT-PP-DIRECTIVE

diff  --git a/flang/test/Flang-Driver/syntax-only.f90 
b/flang/test/Flang-Driver/syntax-only.f90
index 4b435e779d56..f04dd713aeab 100644
--- a/flang/test/Flang-Driver/syntax-only.f90
+++ b/flang/test/Flang-Driver/syntax-only.f90
@@ -4,6 +4,6 @@
 ! REQUIRES: new-flang-driver
 
 ! CHECK: IF statement is not allowed in IF statement
-! CHECK: semantic errors in {{.*}}syntax-only.f90
+! CHECK: Semantic errors in {{.*}}syntax-only.f90
 IF (A > 0.0) IF (B < 0.0) A = LOG (A)
 END

diff  --git a/flang/tools/f18/f18.cpp b/flang/tools/f18/f18.cpp
index b0cc2298005e..8b7cc099bac1 100644
--- a/flang/tools/f18/f18.cpp
+++ b/flang/tools/f18/f18.cpp
@@ -209,7 +209,7 @@ std::string CompileFortran(std::string path, 
Fortran::parser::Options options,
   parsing.Prescan(path, options);
   if (!parsing.messages().empty() &&
   (driver.warningsAreErrors || parsing.messages().AnyFatalError())) {
-llvm::errs() << driver.prefix << "could not scan " << path << '\n';
+llvm::errs() << driver.prefix << "Could not scan " << path << '\n';
 parsing.messages().Emit(llvm::errs(), allCookedSources);
 exitStatus = EXIT_FAILURE;
 return {};
@@ -232,14 +232,14 @@ std::string CompileFortran(std::string path, 
Fortran::parser::Options options,
   parsing.messages().Emit(llvm::errs(), allCookedSources);
   if (!parsing.consumedWholeFile()) {
 parsing.EmitMessage(llvm::err

[llvm-branch-commits] [llvm] e4cda13 - Fix test failure in a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf

[Sander de Smalen via llvm-branch-commits]

Author: Sander de Smalen
Date: 2021-01-06T10:43:48Z
New Revision: e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5

URL: 
https://github.com/llvm/llvm-project/commit/e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5
DIFF: 
https://github.com/llvm/llvm-project/commit/e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5.diff

LOG: Fix test failure in a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf

Set the target-triple to aarch64 in debug-info-sve-dbg-value.mir
to avoid "'+sve' is not a recognized feature for this target"
diagnostic.

Added: 


Modified: 
llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

Removed: 




diff  --git a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir 
b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
index ffce40c9c4f4..84d34ce3d2ac 100644
--- a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
+++ b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
@@ -27,6 +27,7 @@
 --- |
   ; ModuleID = 'bla.mir'
   source_filename = "bla.mir"
+  target triple = "aarch64-unknown-linux-gnu"
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
   define void @foo() #0 !dbg !5 {



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[llvm-branch-commits] [llvm] f73c09c - [VPlan] Use public VPValue constructor in VPPRedInstPHIRecipe (NFC).

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-06T10:47:09Z
New Revision: f73c09caa2a86fa9fe6f88b4a4c438c005fea32c

URL: 
https://github.com/llvm/llvm-project/commit/f73c09caa2a86fa9fe6f88b4a4c438c005fea32c
DIFF: 
https://github.com/llvm/llvm-project/commit/f73c09caa2a86fa9fe6f88b4a4c438c005fea32c.diff

LOG: [VPlan] Use public VPValue constructor in VPPRedInstPHIRecipe (NFC).

VPPredInstPHIRecipe does not need access to VPValue via friendship. It
can just use the public constructor,

Discussed as part of D92281.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/VPlan.h
llvm/lib/Transforms/Vectorize/VPlanValue.h

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/VPlan.h 
b/llvm/lib/Transforms/Vectorize/VPlan.h
index e6635e788e18..01c2894f6b80 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1242,7 +1242,7 @@ class VPPredInstPHIRecipe : public VPRecipeBase, public 
VPUser {
   /// nodes after merging back from a Branch-on-Mask.
   VPPredInstPHIRecipe(VPValue *PredV)
   : VPRecipeBase(VPPredInstPHISC), VPUser(PredV) {
-new VPValue(VPValue::VPValueSC, PredV->getUnderlyingValue(), this);
+new VPValue(PredV->getUnderlyingValue(), this);
   }
   ~VPPredInstPHIRecipe() override = default;
 

diff  --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h 
b/llvm/lib/Transforms/Vectorize/VPlanValue.h
index 1ebe1f8204a5..5bafe220785d 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanValue.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h
@@ -35,7 +35,6 @@ class VPDef;
 class VPSlotTracker;
 class VPUser;
 class VPRecipeBase;
-class VPPredInstPHIRecipe;
 class VPWidenMemoryInstructionRecipe;
 
 // This is the base class of the VPlan Def/Use graph, used for modeling the 
data
@@ -51,7 +50,6 @@ class VPValue {
   friend class VPInterleavedAccessInfo;
   friend class VPSlotTracker;
   friend class VPRecipeBase;
-  friend class VPPredInstPHIRecipe;
   friend class VPWidenMemoryInstructionRecipe;
 
   const unsigned char SubclassID; ///< Subclass identifier (for isa/dyn_cast).



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[llvm-branch-commits] [llvm] ddb82fc - [ARM] Handle any extend whilst lowering mull

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-06T10:51:12Z
New Revision: ddb82fc76ceb92e6f361d35f1ee8dedaee756854

URL: 
https://github.com/llvm/llvm-project/commit/ddb82fc76ceb92e6f361d35f1ee8dedaee756854
DIFF: 
https://github.com/llvm/llvm-project/commit/ddb82fc76ceb92e6f361d35f1ee8dedaee756854.diff

LOG: [ARM] Handle any extend whilst lowering mull

Similar to 78d8a821e23e but for ARM, this handles any_extend whilst
creating MULL nodes, treating them as zextends.

Differential Revision: https://reviews.llvm.org/D93834

Added: 


Modified: 
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/ARM/vmla.ll
llvm/test/CodeGen/ARM/vmls.ll
llvm/test/CodeGen/ARM/vmul.ll

Removed: 




diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp 
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 6a8355f0c3e8..efe2efe91bcf 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8724,10 +8724,11 @@ static bool isSignExtended(SDNode *N, SelectionDAG 
&DAG) {
   return false;
 }
 
-/// isZeroExtended - Check if a node is a vector value that is zero-extended
-/// or a constant BUILD_VECTOR with zero-extended elements.
+/// isZeroExtended - Check if a node is a vector value that is zero-extended 
(or
+/// any-extended) or a constant BUILD_VECTOR with zero-extended elements.
 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
-  if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
+  if (N->getOpcode() == ISD::ZERO_EXTEND || N->getOpcode() == ISD::ANY_EXTEND 
||
+  ISD::isZEXTLoad(N))
 return true;
   if (isExtendedBUILD_VECTOR(N, DAG, false))
 return true;
@@ -8795,13 +8796,14 @@ static SDValue SkipLoadExtensionForVMULL(LoadSDNode 
*LD, SelectionDAG& DAG) {
 }
 
 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
-/// extending load, or BUILD_VECTOR with extended elements, return the
-/// unextended value. The unextended vector should be 64 bits so that it can
+/// ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return
+/// the unextended value. The unextended vector should be 64 bits so that it 
can
 /// be used as an operand to a VMULL instruction. If the original vector size
 /// before extension is less than 64 bits we add a an extension to resize
 /// the vector to 64 bits.
 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
-  if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
+  if (N->getOpcode() == ISD::SIGN_EXTEND ||
+  N->getOpcode() == ISD::ZERO_EXTEND || N->getOpcode() == ISD::ANY_EXTEND)
 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
 N->getOperand(0)->getValueType(0),
 N->getValueType(0),

diff  --git a/llvm/test/CodeGen/ARM/vmla.ll b/llvm/test/CodeGen/ARM/vmla.ll
index 14d425da2df4..43474efdf86b 100644
--- a/llvm/test/CodeGen/ARM/vmla.ll
+++ b/llvm/test/CodeGen/ARM/vmla.ll
@@ -156,9 +156,7 @@ define <2 x i64> @vmlalu32(<2 x i64> %A, <2 x i32> %B, <2 x 
i32> %C) nounwind {
 define <8 x i16> @vmlala8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
 ; CHECK-LABEL: vmlala8:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:vmovl.u8 q8, d3
-; CHECK-NEXT:vmovl.u8 q9, d2
-; CHECK-NEXT:vmla.i16 q0, q9, q8
+; CHECK-NEXT:vmlal.u8 q0, d2, d3
 ; CHECK-NEXT:vbic.i16 q0, #0xff00
 ; CHECK-NEXT:bx lr
   %tmp4 = zext <8 x i8> %B to <8 x i16>
@@ -172,9 +170,7 @@ define <8 x i16> @vmlala8(<8 x i16> %A, <8 x i8> %B, <8 x 
i8> %C) nounwind {
 define <4 x i32> @vmlala16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
 ; CHECK-LABEL: vmlala16:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:vmovl.u16 q8, d3
-; CHECK-NEXT:vmovl.u16 q9, d2
-; CHECK-NEXT:vmla.i32 q0, q9, q8
+; CHECK-NEXT:vmlal.u16 q0, d2, d3
 ; CHECK-NEXT:vmov.i32 q8, #0x
 ; CHECK-NEXT:vand q0, q0, q8
 ; CHECK-NEXT:bx lr
@@ -189,32 +185,10 @@ define <4 x i32> @vmlala16(<4 x i32> %A, <4 x i16> %B, <4 
x i16> %C) nounwind {
 define <2 x i64> @vmlala32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
 ; CHECK-LABEL: vmlala32:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:.save {r4, r5, r6, r7, r11, lr}
-; CHECK-NEXT:push {r4, r5, r6, r7, r11, lr}
-; CHECK-NEXT:vmovl.u32 q8, d3
-; CHECK-NEXT:vmovl.u32 q9, d2
-; CHECK-NEXT:vmov.32 r0, d16[0]
-; CHECK-NEXT:vmov.32 r1, d18[0]
-; CHECK-NEXT:vmov.32 r12, d16[1]
-; CHECK-NEXT:vmov.32 r3, d17[0]
-; CHECK-NEXT:vmov.32 r2, d19[0]
-; CHECK-NEXT:vmov.32 lr, d17[1]
-; CHECK-NEXT:vmov.32 r6, d19[1]
-; CHECK-NEXT:umull r7, r5, r1, r0
-; CHECK-NEXT:mla r1, r1, r12, r5
-; CHECK-NEXT:umull r5, r4, r2, r3
-; CHECK-NEXT:mla r2, r2, lr, r4
-; CHECK-NEXT:vmov.32 r4, d18[1]
-; CHECK-NEXT:vmov.i64 q9, #0x
-; CHECK-NEXT:mla r2, r6, r3, r2
-; CHECK-NEXT:vmov.32 d17[0],

[llvm-branch-commits] [llvm] 351a45c - [RISCV][NFC] Add new test cases for mul

[Ben Shi via llvm-branch-commits]

Author: Ben Shi
Date: 2021-01-06T18:55:56+08:00
New Revision: 351a45ca73de3ec4524d2194674e2a92f8b7d9b5

URL: 
https://github.com/llvm/llvm-project/commit/351a45ca73de3ec4524d2194674e2a92f8b7d9b5
DIFF: 
https://github.com/llvm/llvm-project/commit/351a45ca73de3ec4524d2194674e2a92f8b7d9b5.diff

LOG: [RISCV][NFC] Add new test cases for mul

Added: 


Modified: 
llvm/test/CodeGen/RISCV/mul.ll

Removed: 




diff  --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 9104b4089ab9..3703e4128c69 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -972,3 +972,207 @@ define i64 @muli64_m3840(i64 %a) nounwind {
   %1 = mul i64 %a, -3840
   ret i64 %1
 }
+
+define i128 @muli128_m3840(i128 %a) nounwind {
+; RV32I-LABEL: muli128_m3840:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:addi sp, sp, -64
+; RV32I-NEXT:sw ra, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT:sw s0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT:lw a3, 0(a1)
+; RV32I-NEXT:lw a2, 4(a1)
+; RV32I-NEXT:lw a4, 8(a1)
+; RV32I-NEXT:lw a1, 12(a1)
+; RV32I-NEXT:mv s0, a0
+; RV32I-NEXT:addi a0, zero, -1
+; RV32I-NEXT:sw a0, 20(sp)
+; RV32I-NEXT:sw a0, 16(sp)
+; RV32I-NEXT:sw a0, 12(sp)
+; RV32I-NEXT:lui a0, 1048575
+; RV32I-NEXT:addi a0, a0, 256
+; RV32I-NEXT:sw a0, 8(sp)
+; RV32I-NEXT:sw a1, 36(sp)
+; RV32I-NEXT:sw a4, 32(sp)
+; RV32I-NEXT:sw a2, 28(sp)
+; RV32I-NEXT:addi a0, sp, 40
+; RV32I-NEXT:addi a1, sp, 24
+; RV32I-NEXT:addi a2, sp, 8
+; RV32I-NEXT:sw a3, 24(sp)
+; RV32I-NEXT:call __multi3@plt
+; RV32I-NEXT:lw a0, 52(sp)
+; RV32I-NEXT:lw a1, 48(sp)
+; RV32I-NEXT:lw a2, 44(sp)
+; RV32I-NEXT:lw a3, 40(sp)
+; RV32I-NEXT:sw a0, 12(s0)
+; RV32I-NEXT:sw a1, 8(s0)
+; RV32I-NEXT:sw a2, 4(s0)
+; RV32I-NEXT:sw a3, 0(s0)
+; RV32I-NEXT:lw s0, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT:lw ra, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT:addi sp, sp, 64
+; RV32I-NEXT:ret
+;
+; RV32IM-LABEL: muli128_m3840:
+; RV32IM:   # %bb.0:
+; RV32IM-NEXT:addi sp, sp, -64
+; RV32IM-NEXT:sw ra, 60(sp) # 4-byte Folded Spill
+; RV32IM-NEXT:sw s0, 56(sp) # 4-byte Folded Spill
+; RV32IM-NEXT:lw a3, 0(a1)
+; RV32IM-NEXT:lw a2, 4(a1)
+; RV32IM-NEXT:lw a4, 8(a1)
+; RV32IM-NEXT:lw a1, 12(a1)
+; RV32IM-NEXT:mv s0, a0
+; RV32IM-NEXT:addi a0, zero, -1
+; RV32IM-NEXT:sw a0, 20(sp)
+; RV32IM-NEXT:sw a0, 16(sp)
+; RV32IM-NEXT:sw a0, 12(sp)
+; RV32IM-NEXT:lui a0, 1048575
+; RV32IM-NEXT:addi a0, a0, 256
+; RV32IM-NEXT:sw a0, 8(sp)
+; RV32IM-NEXT:sw a1, 36(sp)
+; RV32IM-NEXT:sw a4, 32(sp)
+; RV32IM-NEXT:sw a2, 28(sp)
+; RV32IM-NEXT:addi a0, sp, 40
+; RV32IM-NEXT:addi a1, sp, 24
+; RV32IM-NEXT:addi a2, sp, 8
+; RV32IM-NEXT:sw a3, 24(sp)
+; RV32IM-NEXT:call __multi3@plt
+; RV32IM-NEXT:lw a0, 52(sp)
+; RV32IM-NEXT:lw a1, 48(sp)
+; RV32IM-NEXT:lw a2, 44(sp)
+; RV32IM-NEXT:lw a3, 40(sp)
+; RV32IM-NEXT:sw a0, 12(s0)
+; RV32IM-NEXT:sw a1, 8(s0)
+; RV32IM-NEXT:sw a2, 4(s0)
+; RV32IM-NEXT:sw a3, 0(s0)
+; RV32IM-NEXT:lw s0, 56(sp) # 4-byte Folded Reload
+; RV32IM-NEXT:lw ra, 60(sp) # 4-byte Folded Reload
+; RV32IM-NEXT:addi sp, sp, 64
+; RV32IM-NEXT:ret
+;
+; RV64I-LABEL: muli128_m3840:
+; RV64I:   # %bb.0:
+; RV64I-NEXT:addi sp, sp, -16
+; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:lui a2, 1048575
+; RV64I-NEXT:addiw a2, a2, 256
+; RV64I-NEXT:addi a3, zero, -1
+; RV64I-NEXT:call __multi3@plt
+; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:addi sp, sp, 16
+; RV64I-NEXT:ret
+;
+; RV64IM-LABEL: muli128_m3840:
+; RV64IM:   # %bb.0:
+; RV64IM-NEXT:lui a2, 1048575
+; RV64IM-NEXT:addiw a2, a2, 256
+; RV64IM-NEXT:mul a1, a1, a2
+; RV64IM-NEXT:mulhu a3, a0, a2
+; RV64IM-NEXT:sub a3, a3, a0
+; RV64IM-NEXT:add a1, a3, a1
+; RV64IM-NEXT:mul a0, a0, a2
+; RV64IM-NEXT:ret
+  %1 = mul i128 %a, -3840
+  ret i128 %1
+}
+
+define i128 @muli128_m63(i128 %a) nounwind {
+; RV32I-LABEL: muli128_m63:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:addi sp, sp, -64
+; RV32I-NEXT:sw ra, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT:sw s0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT:lw a3, 0(a1)
+; RV32I-NEXT:lw a2, 4(a1)
+; RV32I-NEXT:lw a4, 8(a1)
+; RV32I-NEXT:lw a1, 12(a1)
+; RV32I-NEXT:mv s0, a0
+; RV32I-NEXT:addi a0, zero, -1
+; RV32I-NEXT:sw a0, 20(sp)
+; RV32I-NEXT:sw a0, 16(sp)
+; RV32I-NEXT:sw a0, 12(sp)
+; RV32I-NEXT:addi a0, zero, -63
+; RV32I-NEXT:sw a0, 8(sp)
+; RV32I-NEXT:sw a1, 36(sp)
+; RV32I-NEXT:sw a4, 32(sp)
+; RV32I-NEXT:sw a2, 28(sp)
+; RV32I-NEXT:addi a0, sp, 40
+; RV32I-NEXT:addi a1, sp, 24
+; RV32I-NEXT:addi a2, sp, 8
+; RV3

[llvm-branch-commits] [mlir] 74438ef - [mlir] Use thread_local stack in LLVM dialect type parsing and printing

[Alex Zinenko via llvm-branch-commits]

Author: Alex Zinenko
Date: 2021-01-06T12:05:24+01:00
New Revision: 74438eff511e71dc33841546d89cb34206551d55

URL: 
https://github.com/llvm/llvm-project/commit/74438eff511e71dc33841546d89cb34206551d55
DIFF: 
https://github.com/llvm/llvm-project/commit/74438eff511e71dc33841546d89cb34206551d55.diff

LOG: [mlir] Use thread_local stack in LLVM dialect type parsing and printing

LLVM dialect type parsing and printing have been using a local stack object
forwarded between recursive functions responsible for parsing or printing
specific types. This stack is necessary to intercept (mutually) recursive
structure types and avoid inifinite recursion. This approach works only thanks
to the closedness of the LLVM dialect type system: types that don't belong to
the dialect are not allowed. Switch the approach to using a `thread_local`
stack inside the functions parsing the structure types. This makes the code
slightly cleaner by avoiding the need to pass the stack object around and, more
importantly, makes it possible to reconsider the closedness of the LLVM dialect
type system. As a nice side effect of this change, container LLVM dialect types
now support type aliases in their body (although it is currently impossible to
also use the alises when printing).

Depends On D93713

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93714

Added: 


Modified: 
mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
mlir/test/Dialect/LLVMIR/types-invalid.mlir
mlir/test/Dialect/LLVMIR/types.mlir

Removed: 




diff  --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp 
b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
index 3d72e254f338..08c00befcf18 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
@@ -9,6 +9,7 @@
 #include "mlir/Dialect/LLVMIR/LLVMTypes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/DialectImplementation.h"
+#include "llvm/ADT/ScopeExit.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/TypeSwitch.h"
 
@@ -19,8 +20,14 @@ using namespace mlir::LLVM;
 // Printing.
 
//===--===//
 
-static void printTypeImpl(llvm::raw_ostream &os, Type type,
-  llvm::SetVector &stack);
+/// If the given type is compatible with the LLVM dialect, prints it using
+/// internal functions to avoid getting a verbose `!llvm` prefix. Otherwise
+/// prints it as usual.
+static void dispatchPrint(DialectAsmPrinter &printer, Type type) {
+  if (isCompatibleType(type))
+return mlir::LLVM::detail::printType(type, printer);
+  printer.printType(type);
+}
 
 /// Returns the keyword to use for the given type.
 static StringRef getTypeKeyword(Type type) {
@@ -48,76 +55,79 @@ static StringRef getTypeKeyword(Type type) {
   });
 }
 
-/// Prints the body of a structure type. Uses `stack` to avoid printing
-/// recursive structs indefinitely.
-static void printStructTypeBody(llvm::raw_ostream &os, LLVMStructType type,
-llvm::SetVector &stack) {
-  if (type.isIdentified() && type.isOpaque()) {
-os << "opaque";
-return;
-  }
-
-  if (type.isPacked())
-os << "packed ";
-
-  // Put the current type on stack to avoid infinite recursion.
-  os << '(';
-  if (type.isIdentified())
-stack.insert(type.getName());
-  llvm::interleaveComma(type.getBody(), os, [&](Type subtype) {
-printTypeImpl(os, subtype, stack);
+/// Prints a structure type. Keeps track of known struct names to handle self-
+/// or mutually-referring structs without falling into infinite recursion.
+static void printStructType(DialectAsmPrinter &printer, LLVMStructType type) {
+  // This keeps track of the names of identified structure types that are
+  // currently being printed. Since such types can refer themselves, this
+  // tracking is necessary to stop the recursion: the current function may be
+  // called recursively from DialectAsmPrinter::printType after the appropriate
+  // dispatch. We maintain the invariant of this storage being modified
+  // exclusively in this function, and at most one name being added per call.
+  // TODO: consider having such functionality inside DialectAsmPrinter.
+  thread_local llvm::SetVector knownStructNames;
+  unsigned stackSize = knownStructNames.size();
+  (void)stackSize;
+  auto guard = llvm::make_scope_exit([&]() {
+assert(knownStructNames.size() == stackSize &&
+   "malformed identified stack when printing recursive structs");
   });
-  if (type.isIdentified())
-stack.pop_back();
-  os << ')';
-}
 
-/// Prints a structure type. Uses `stack` to keep track of the identifiers of
-/// the structs being printed. Checks if the identifier of a struct is 
contained
-/// in `stack`, i.e. whether a self-reference to a recursive stack is being
-/// printed, and only prints the name to avoid infinite recursio

[llvm-branch-commits] [llvm] 0ce5f40 - [VPlan] Add getLiveInIRValue accessor to VPValue.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-06T11:20:42Z
New Revision: 0ce5f402e0166a33bea01d577ce8ee32189d80e3

URL: 
https://github.com/llvm/llvm-project/commit/0ce5f402e0166a33bea01d577ce8ee32189d80e3
DIFF: 
https://github.com/llvm/llvm-project/commit/0ce5f402e0166a33bea01d577ce8ee32189d80e3.diff

LOG: [VPlan] Add getLiveInIRValue accessor to VPValue.

This patch adds a new getLiveInIRValue accessor to VPValue, which
returns the underlying value, if the VPValue is defined outside of
VPlan. This is required to handle scalars in VPTransformState, which
requires dealing with scalars defined outside of VPlan.

We can simply check VPValue::Def to determine if the value is defined
inside a VPlan.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D92281

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/VPlanValue.h

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h 
b/llvm/lib/Transforms/Vectorize/VPlanValue.h
index 5bafe220785d..fdedafef2edd 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanValue.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h
@@ -166,6 +166,15 @@ class VPValue {
   void replaceAllUsesWith(VPValue *New);
 
   VPDef *getDef() { return Def; }
+
+  /// Returns the underlying IR value, if this VPValue is defined outside the
+  /// scope of VPlan. Returns nullptr if the VPValue is defined by a VPDef
+  /// inside a VPlan.
+  Value *getLiveInIRValue() {
+assert(!getDef() &&
+   "VPValue is not a live-in; it is defined by a VPDef inside a 
VPlan");
+return getUnderlyingValue();
+  }
 };
 
 typedef DenseMap Value2VPValueTy;



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[llvm-branch-commits] [llvm] 63dce70 - [ARM] Handle any extend whilst lowering addw/addl/subw/subl

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-06T11:26:39Z
New Revision: 63dce70b794eb99ebbfdeed3ca9aafca2b8fe5c4

URL: 
https://github.com/llvm/llvm-project/commit/63dce70b794eb99ebbfdeed3ca9aafca2b8fe5c4
DIFF: 
https://github.com/llvm/llvm-project/commit/63dce70b794eb99ebbfdeed3ca9aafca2b8fe5c4.diff

LOG: [ARM] Handle any extend whilst lowering addw/addl/subw/subl

Same as a9b6440edd, use zanyext to treat any_extends as zero extends
during lowering to create addw/addl/subw/subl nodes.

Differential Revision: https://reviews.llvm.org/D93835

Added: 


Modified: 
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/test/CodeGen/ARM/vadd.ll
llvm/test/CodeGen/ARM/vsub.ll

Removed: 




diff  --git a/llvm/lib/Target/ARM/ARMInstrNEON.td 
b/llvm/lib/Target/ARM/ARMInstrNEON.td
index bb30dbd3a5c9..a8c0d05d91c4 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -4197,10 +4197,10 @@ def  VADDhq   : N3VQ<0, 0, 0b01, 0b1101, 0, IIC_VBINQ, 
"vadd", "f16",
 defm VADDLs   : N3VLExt_QHS<0,1,0b,0, IIC_VSHLiD, IIC_VSHLiD,
 "vaddl", "s", add, sext, 1>;
 defm VADDLu   : N3VLExt_QHS<1,1,0b,0, IIC_VSHLiD, IIC_VSHLiD,
-"vaddl", "u", add, zext, 1>;
+"vaddl", "u", add, zanyext, 1>;
 //   VADDW: Vector Add Wide (Q = Q + D)
 defm VADDWs   : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
-defm VADDWu   : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
+defm VADDWu   : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zanyext, 0>;
 //   VHADD: Vector Halving Add
 defm VHADDs   : N3VInt_QHS<0, 0, 0b, 0, N3RegFrm,
IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
@@ -5045,10 +5045,10 @@ def  VSUBhq   : N3VQ<0, 0, 0b11, 0b1101, 0, IIC_VBINQ, 
"vsub", "f16",
 defm VSUBLs   : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
 "vsubl", "s", sub, sext, 0>;
 defm VSUBLu   : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
-"vsubl", "u", sub, zext, 0>;
+"vsubl", "u", sub, zanyext, 0>;
 //   VSUBW: Vector Subtract Wide (Q = Q - D)
 defm VSUBWs   : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
-defm VSUBWu   : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
+defm VSUBWu   : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zanyext, 0>;
 //   VHSUB: Vector Halving Subtract
 defm VHSUBs   : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,

diff  --git a/llvm/test/CodeGen/ARM/vadd.ll b/llvm/test/CodeGen/ARM/vadd.ll
index 5f0ddd17c8c7..282108244e5c 100644
--- a/llvm/test/CodeGen/ARM/vadd.ll
+++ b/llvm/test/CodeGen/ARM/vadd.ll
@@ -224,9 +224,7 @@ define <2 x i64> @vaddlu32(<2 x i32> %A, <2 x i32> %B) {
 define <8 x i16> @vaddla8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: vaddla8:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:vmovl.u8 q8, d1
-; CHECK-NEXT:vmovl.u8 q9, d0
-; CHECK-NEXT:vadd.i16 q0, q9, q8
+; CHECK-NEXT:vaddl.u8 q0, d0, d1
 ; CHECK-NEXT:vbic.i16 q0, #0xff00
 ; CHECK-NEXT:bx lr
   %tmp3 = zext <8 x i8> %A to <8 x i16>
@@ -239,11 +237,9 @@ define <8 x i16> @vaddla8(<8 x i8> %A, <8 x i8> %B) {
 define <4 x i32> @vaddla16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: vaddla16:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:vmovl.u16 q8, d1
-; CHECK-NEXT:vmovl.u16 q9, d0
-; CHECK-NEXT:vmov.i32 q10, #0x
-; CHECK-NEXT:vadd.i32 q8, q9, q8
-; CHECK-NEXT:vand q0, q8, q10
+; CHECK-NEXT:vmov.i32 q8, #0x
+; CHECK-NEXT:vaddl.u16 q9, d0, d1
+; CHECK-NEXT:vand q0, q9, q8
 ; CHECK-NEXT:bx lr
   %tmp3 = zext <4 x i16> %A to <4 x i32>
   %tmp4 = zext <4 x i16> %B to <4 x i32>
@@ -255,11 +251,9 @@ define <4 x i32> @vaddla16(<4 x i16> %A, <4 x i16> %B) {
 define <2 x i64> @vaddla32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: vaddla32:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:vmovl.u32 q8, d1
-; CHECK-NEXT:vmovl.u32 q9, d0
-; CHECK-NEXT:vmov.i64 q10, #0x
-; CHECK-NEXT:vadd.i64 q8, q9, q8
-; CHECK-NEXT:vand q0, q8, q10
+; CHECK-NEXT:vmov.i64 q8, #0x
+; CHECK-NEXT:vaddl.u32 q9, d0, d1
+; CHECK-NEXT:vand q0, q9, q8
 ; CHECK-NEXT:bx lr
   %tmp3 = zext <2 x i32> %A to <2 x i64>
   %tmp4 = zext <2 x i32> %B to <2 x i64>
@@ -331,8 +325,7 @@ define <2 x i64> @vaddwu32(<2 x i64> %A, <2 x i32> %B) {
 define <8 x i16> @vaddwa8(<8 x i16> %A, <8 x i8> %B) {
 ; CHECK-LABEL: vaddwa8:
 ; CHECK:   @ %bb.0:
-; CHECK-NEXT:vmovl.u8 q8, d2
-; CHECK-NEXT:vadd.i16 q0, q0, q8
+; CHECK-NEXT:vaddw.u8 q0, q0, d2
 ; CHECK-NEXT:vbic.i16 q0, #0xff00
 ; CHECK-NEXT:bx lr
   %tmp3 = zext <8 x i8> %B to <8 x i16>
@@ -344,10 +337,9 @@ define <8 x i16> @vaddwa8(<8 x i16> %A, <8 x i8> %B) {
 define <4 x i32> @vaddwa16(<4 x i32> %A, <4 x i16> %B) {
 ; CHEC

[llvm-branch-commits] [llvm] 84a1120 - [LiveDebugValues] Handle spill locations with a fixed and scalable component.

[Sander de Smalen via llvm-branch-commits]

Author: Sander de Smalen
Date: 2021-01-06T11:30:13Z
New Revision: 84a1120943a651184bae507fed5d648fee381ae4

URL: 
https://github.com/llvm/llvm-project/commit/84a1120943a651184bae507fed5d648fee381ae4
DIFF: 
https://github.com/llvm/llvm-project/commit/84a1120943a651184bae507fed5d648fee381ae4.diff

LOG: [LiveDebugValues] Handle spill locations with a fixed and scalable 
component.

This patch fixes the two LiveDebugValues implementations
(InstrRef/VarLoc)Based to handle cases where the StackOffset contains
both a fixed and scalable component.

This depends on the `TargetRegisterInfo::prependOffsetExpression` being
added in D90020. Feel free to leave comments on that patch if you have them.

Reviewed By: djtodoro, jmorse

Differential Revision: https://reviews.llvm.org/D90046

Added: 
llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir

Modified: 
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp 
b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 04ead18cc3de2..b6f46daf8bba9 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -182,6 +182,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/TypeSize.h"
 #include "llvm/Support/raw_ostream.h"
 #include 
 #include 
@@ -221,14 +222,16 @@ namespace {
 // an offset.
 struct SpillLoc {
   unsigned SpillBase;
-  int SpillOffset;
+  StackOffset SpillOffset;
   bool operator==(const SpillLoc &Other) const {
-return std::tie(SpillBase, SpillOffset) ==
-   std::tie(Other.SpillBase, Other.SpillOffset);
+return std::make_pair(SpillBase, SpillOffset) ==
+   std::make_pair(Other.SpillBase, Other.SpillOffset);
   }
   bool operator<(const SpillLoc &Other) const {
-return std::tie(SpillBase, SpillOffset) <
-   std::tie(Other.SpillBase, Other.SpillOffset);
+return std::make_tuple(SpillBase, SpillOffset.getFixed(),
+SpillOffset.getScalable()) <
+   std::make_tuple(Other.SpillBase, Other.SpillOffset.getFixed(),
+Other.SpillOffset.getScalable());
   }
 };
 
@@ -769,8 +772,10 @@ class MLocTracker {
 } else if (LocIdxToLocID[*MLoc] >= NumRegs) {
   unsigned LocID = LocIdxToLocID[*MLoc];
   const SpillLoc &Spill = SpillLocs[LocID - NumRegs + 1];
-  Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset,
-   Spill.SpillOffset);
+
+  auto *TRI = MF.getSubtarget().getRegisterInfo();
+  Expr = TRI->prependOffsetExpression(Expr, DIExpression::ApplyOffset,
+  Spill.SpillOffset);
   unsigned Base = Spill.SpillBase;
   MIB.addReg(Base, RegState::Debug);
   MIB.addImm(0);
@@ -1579,9 +1584,7 @@ InstrRefBasedLDV::extractSpillBaseRegAndOffset(const 
MachineInstr &MI) {
   const MachineBasicBlock *MBB = MI.getParent();
   Register Reg;
   StackOffset Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg);
-  assert(!Offset.getScalable() &&
- "Frame offsets with a scalable component are not supported");
-  return {Reg, static_cast(Offset.getFixed())};
+  return {Reg, Offset};
 }
 
 /// End all previous ranges related to @MI and start a new range from @MI

diff  --git a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp 
b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
index ed7f04e571acc..4811b80467973 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
@@ -145,6 +145,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/TypeSize.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include 
@@ -292,7 +293,7 @@ class VarLocBasedLDV : public LDVImpl {
 // register and an offset.
 struct SpillLoc {
   unsigned SpillBase;
-  int SpillOffset;
+  StackOffset SpillOffset;
   bool operator==(const SpillLoc &Other) const {
 return SpillBase == Other.SpillBase && SpillOffset == 
Other.SpillOffset;
   }
@@ -323,21 +324,20 @@ class VarLocBasedLDV : public LDVImpl {
 
 /// The value location. Stored separately to avoid repeatedly
 /// extracting it from MI.
-union {
+union LocUnion {
   uint64_t RegNo;
   SpillLoc SpillLocation;
   uint64_t Hash;
   int64_t Immediate;
   const ConstantFP *FPImm;
   const ConstantInt *CImm;
+  LocUnion() : Hash(0) {}
 } Loc;
 
 VarLoc(const MachineInstr &MI, LexicalScopes &LS)
 : Var(MI.getDebugVariable(), MI.getDebugExpression(),
   MI.getDebugLoc()->getInlinedAt()),

[llvm-branch-commits] [llvm] 6e6e24b - [ValueTypes] Fix formatting on scalable vector warning (NFC)

[Fraser Cormack via llvm-branch-commits]

Author: Fraser Cormack
Date: 2021-01-06T11:27:44Z
New Revision: 6e6e24bb09c7845bfa89772527d30cea36ebf19b

URL: 
https://github.com/llvm/llvm-project/commit/6e6e24bb09c7845bfa89772527d30cea36ebf19b
DIFF: 
https://github.com/llvm/llvm-project/commit/6e6e24bb09c7845bfa89772527d30cea36ebf19b.diff

LOG: [ValueTypes] Fix formatting on scalable vector warning (NFC)

Added: 


Modified: 
llvm/include/llvm/CodeGen/ValueTypes.h

Removed: 




diff  --git a/llvm/include/llvm/CodeGen/ValueTypes.h 
b/llvm/include/llvm/CodeGen/ValueTypes.h
index a03ec010f0477..888b83d6f736f 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -303,7 +303,7 @@ namespace llvm {
   if (isScalableVector())
 WithColor::warning()
 << "Possible incorrect use of EVT::getVectorNumElements() for "
-   "scalable vector. Scalable flag may be dropped, use"
+   "scalable vector. Scalable flag may be dropped, use "
"EVT::getVectorElementCount() instead\n";
 #endif
   if (isSimple())



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[llvm-branch-commits] [llvm] aa280c9 - [AArch64][SVE] Emit DWARF location expr for SVE (dbg.declare)

[Sander de Smalen via llvm-branch-commits]

Author: Sander de Smalen
Date: 2021-01-06T11:45:05Z
New Revision: aa280c99f708dca9dea96bc9070d6194d2622529

URL: 
https://github.com/llvm/llvm-project/commit/aa280c99f708dca9dea96bc9070d6194d2622529
DIFF: 
https://github.com/llvm/llvm-project/commit/aa280c99f708dca9dea96bc9070d6194d2622529.diff

LOG: [AArch64][SVE] Emit DWARF location expr for SVE (dbg.declare)

When using dbg.declare, the debug-info is generated from a list of
locals rather than through DBG_VALUE instructions in the MIR.
This patch is different from D90020 because it emits the DWARF
location expressions from that list of locals directly.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D90044

Added: 
llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

Modified: 
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp 
b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
index 02791f2280d2..ea279e4914b0 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -739,11 +739,10 @@ DIE *DwarfCompileUnit::constructVariableDIEImpl(const 
DbgVariable &DV,
 TFI->getFrameIndexReference(*Asm->MF, Fragment.FI, FrameReg);
 DwarfExpr.addFragmentOffset(Expr);
 
-assert(!Offset.getScalable() &&
-   "Frame offsets with a scalable component are not supported");
-
+auto *TRI = Asm->MF->getSubtarget().getRegisterInfo();
 SmallVector Ops;
-DIExpression::appendOffset(Ops, Offset.getFixed());
+TRI->getOffsetOpcodes(Offset, Ops);
+
 // According to
 // 
https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf
 // cuda-gdb requires DW_AT_address_class for all variables to be able to

diff  --git a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir 
b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
new file mode 100644
index ..39b11ef7bfea
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
@@ -0,0 +1,222 @@
+# RUN: llc -o %t -filetype=obj -start-before=prologepilog %s
+# RUN: llvm-dwarfdump --name="z0" %t | FileCheck %s --check-prefix=CHECKZ0
+# RUN: llvm-dwarfdump --name="z1" %t | FileCheck %s --check-prefix=CHECKZ1
+# RUN: llvm-dwarfdump --name="p0" %t | FileCheck %s --check-prefix=CHECKP0
+# RUN: llvm-dwarfdump --name="p1" %t | FileCheck %s --check-prefix=CHECKP1
+# RUN: llvm-dwarfdump --name="localv0" %t | FileCheck %s 
--check-prefix=CHECKLV0
+# RUN: llvm-dwarfdump --name="localv1" %t | FileCheck %s 
--check-prefix=CHECKLV1
+# RUN: llvm-dwarfdump --name="localp0" %t | FileCheck %s 
--check-prefix=CHECKLP0
+# RUN: llvm-dwarfdump --name="localp1" %t | FileCheck %s 
--check-prefix=CHECKLP1
+#
+# CHECKZ0:   DW_AT_location(DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx 
VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKZ0-NEXT:  DW_AT_name("z0")
+# CHECKZ1:   DW_AT_location(DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx 
VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKZ1-NEXT:  DW_AT_name("z1")
+# CHECKP0:   DW_AT_location(DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx 
VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKP0-NEXT:  DW_AT_name("p0")
+# CHECKP1:   DW_AT_location(DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx 
VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKP1-NEXT:  DW_AT_name("p1")
+# CHECKLV0:  DW_AT_location(DW_OP_fbreg +0, DW_OP_constu 0x20, 
DW_OP_bregx VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKLV0-NEXT: DW_AT_name("localv0")
+# CHECKLV1:  DW_AT_location(DW_OP_fbreg +0, DW_OP_constu 0x28, 
DW_OP_bregx VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKLV1-NEXT: DW_AT_name("localv1")
+# CHECKLP0:  DW_AT_location(DW_OP_fbreg +0, DW_OP_constu 0x29, 
DW_OP_bregx VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKLP0-NEXT: DW_AT_name("localp0")
+# CHECKLP1:  DW_AT_location(DW_OP_fbreg +0, DW_OP_constu 0x2a, 
DW_OP_bregx VG+0, DW_OP_mul, DW_OP_minus)
+# CHECKLP1-NEXT: DW_AT_name("localp1")
+--- |
+  ; ModuleID = 't.c'
+  source_filename = "t.c"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-linux-gnu"
+
+  ; Function Attrs: noinline nounwind optnone
+  define dso_local  @foo( %z0,  %z1,  %p0,  %p1, i32 %w0) #0 !dbg 
!11 {
+  entry:
+%z0.addr = alloca , align 16
+%z1.addr = alloca , align 16
+%p0.addr = alloca , align 2
+%p1.addr = alloca , align 2
+%w0.addr = alloca i32, align 4
+%local_gpr0 = alloca i32, align 4
+%localv0 = alloca , align 16
+%localv1 = alloca , align 16
+%localp0 = alloca , align 2
+%localp1 = alloca , align 2
+store  %z0, * %z0.addr, align 16
+call void @llvm.dbg.declare(metadata * %z0.addr, 
metadata !29, metadata !DIExpression()), !dbg !30
+store  %z1, * %z1.addr, align 16
+call 

[llvm-branch-commits] [llvm] 816dba4 - [VPlan] Keep start value in VPWidenIntOrFpInductionRecipe (NFC).

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-06T11:47:33Z
New Revision: 816dba48af49050625adec6ed696983618346b11

URL: 
https://github.com/llvm/llvm-project/commit/816dba48af49050625adec6ed696983618346b11
DIFF: 
https://github.com/llvm/llvm-project/commit/816dba48af49050625adec6ed696983618346b11.diff

LOG: [VPlan] Keep start value in VPWidenIntOrFpInductionRecipe (NFC).

This patch updates VPWidenIntOrFpInductionRecipe to hold the start value
for the induction variable. This makes the start value explicit and
allows for adjusting the start value for a VPlan.

The flexibility will be used in further patches.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D92129

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
llvm/lib/Transforms/Vectorize/VPlan.h
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp 
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 14011daa554a..1518b757186d 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -526,7 +526,8 @@ class InnerLoopVectorizer {
   /// Widen an integer or floating-point induction variable \p IV. If \p Trunc
   /// is provided, the integer induction variable will first be truncated to
   /// the corresponding type.
-  void widenIntOrFpInduction(PHINode *IV, TruncInst *Trunc = nullptr);
+  void widenIntOrFpInduction(PHINode *IV, Value *Start,
+ TruncInst *Trunc = nullptr);
 
   /// getOrCreateVectorValue and getOrCreateScalarValue coordinate to generate 
a
   /// vector or scalar value on-demand if one is not yet available. When
@@ -666,7 +667,8 @@ class InnerLoopVectorizer {
   /// truncate instruction, instead of widening the original IV, we widen a
   /// version of the IV truncated to \p EntryVal's type.
   void createVectorIntOrFpInductionPHI(const InductionDescriptor &II,
-   Value *Step, Instruction *EntryVal);
+   Value *Step, Value *Start,
+   Instruction *EntryVal);
 
   /// Returns true if an instruction \p I should be scalarized instead of
   /// vectorized for the chosen vectorization factor.
@@ -2005,10 +2007,10 @@ Value *InnerLoopVectorizer::getBroadcastInstrs(Value 
*V) {
 }
 
 void InnerLoopVectorizer::createVectorIntOrFpInductionPHI(
-const InductionDescriptor &II, Value *Step, Instruction *EntryVal) {
+const InductionDescriptor &II, Value *Step, Value *Start,
+Instruction *EntryVal) {
   assert((isa(EntryVal) || isa(EntryVal)) &&
  "Expected either an induction phi-node or a truncate of it!");
-  Value *Start = II.getStartValue();
 
   // Construct the initial value of the vector IV in the vector loop preheader
   auto CurrIP = Builder.saveIP();
@@ -2126,7 +2128,8 @@ void 
InnerLoopVectorizer::recordVectorLoopValueForInductionCast(
 VectorLoopValueMap.setVectorValue(CastInst, Part, VectorLoopVal);
 }
 
-void InnerLoopVectorizer::widenIntOrFpInduction(PHINode *IV, TruncInst *Trunc) 
{
+void InnerLoopVectorizer::widenIntOrFpInduction(PHINode *IV, Value *Start,
+TruncInst *Trunc) {
   assert((IV->getType()->isIntegerTy() || IV != OldInduction) &&
  "Primary induction variable must have an integer type");
 
@@ -2208,7 +2211,7 @@ void InnerLoopVectorizer::widenIntOrFpInduction(PHINode 
*IV, TruncInst *Trunc) {
   // least one user in the loop that is not widened.
   auto NeedsScalarIV = needsScalarInduction(EntryVal);
   if (!NeedsScalarIV) {
-createVectorIntOrFpInductionPHI(ID, Step, EntryVal);
+createVectorIntOrFpInductionPHI(ID, Step, Start, EntryVal);
 return;
   }
 
@@ -2216,7 +2219,7 @@ void InnerLoopVectorizer::widenIntOrFpInduction(PHINode 
*IV, TruncInst *Trunc) {
   // create the phi node, we will splat the scalar induction variable in each
   // loop iteration.
   if (!shouldScalarizeInstruction(EntryVal)) {
-createVectorIntOrFpInductionPHI(ID, Step, EntryVal);
+createVectorIntOrFpInductionPHI(ID, Step, Start, EntryVal);
 Value *ScalarIV = CreateScalarIV(Step);
 // Create scalar steps that can be used by instructions we will later
 // scalarize. Note that the addition of the scalar steps will not increase
@@ -8061,20 +8064,22 @@ VPRecipeBase 
*VPRecipeBuilder::tryToWidenMemory(Instruction *I, VFRange &Range,
 }
 
 VPWidenIntOrFpInductionRecipe *
-VPRecipeBuilder::tryToOptimizeInductionPHI(PHINode *Phi) const {
+VPRecipeBuilder::tryToOptimizeInductionPHI(PHINode *Phi, VPlan &Plan) const {
   // Check if this is an integer or fp induction. If so, build the recipe that
   // produces its scalar and vector values.
   InductionDescriptor II = Legal->getInductionVars().lookup(Phi);

[llvm-branch-commits] [llvm] cb0c034 - [PowerPC] Fix issue where vsrq is given incorrect shift vector

[Stefan Pintilie via llvm-branch-commits]

Author: Stefan Pintilie
Date: 2021-01-06T05:56:09-06:00
New Revision: cb0c034edc98b32691ea25b70fc3cc2e9d6d2a86

URL: 
https://github.com/llvm/llvm-project/commit/cb0c034edc98b32691ea25b70fc3cc2e9d6d2a86
DIFF: 
https://github.com/llvm/llvm-project/commit/cb0c034edc98b32691ea25b70fc3cc2e9d6d2a86.diff

LOG: [PowerPC] Fix issue where vsrq is given incorrect shift vector

The new Power10 instruction vsrq was being given the wrong shift vector.
The original code assumed that the shift would be found in bits 121 to 127.
This is not correct. The shift is found in bits 57 to 63.
This can be fixed by swaping the first and second double words.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D94113

Added: 


Modified: 
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 2f29811b20d8..b6e9562dd0f6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2521,18 +2521,6 @@ let Predicates = [IsISA3_1] in {
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
-  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
-(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
-  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
-(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
-  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
-(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
-  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
-(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
-  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
-(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
-  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
-(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
 
   def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 8)),
  (v1i128 (COPY_TO_REGCLASS (LXVRBX xoaddr:$src), VRRC))>;
@@ -2570,6 +2558,35 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, 
IsLittleEndian] in {
 (STXVRDX $src, xoaddr:$dst)>;
  }
 
+// FIXME: The swap is overkill when the shift amount is a constant.
+// We should just fix the constant in the DAG.
+let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA,
+ (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
+   (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
+  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSLQ v1i128:$VRA,
+ (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
+   (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
+  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA,
+ (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
+   (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
+  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRQ v1i128:$VRA,
+ (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
+   (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
+  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA,
+ (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
+   (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
+  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
+(v1i128 (VSRAQ v1i128:$VRA,
+ (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
+   (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
+}
+
 class xxevalPattern  imm> :
   Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
 

diff  --git a/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll 
b/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
index 5055c02786ac..f02f263c0b43 100644
--- a/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
@@ -13,6 +13,7 @@
 define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
 ; CHECK-LABEL: test_vec_vslq:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xxswapd v3, v3
 ; CHECK-NEXT:vslq v2, v2, v3
 ; CHECK-NEXT:blr
 entry:
@@ -24,6 +25,7 @@ entry:
 define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
 ; CHECK-LABEL: test_vec_vsrq:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xxswapd v3, v3
 ; CHECK-NEXT:vsrq v2, v2, v3
 ; CHECK-NEXT:blr
 entry:
@@ -35,6 +37,7 @@ entry:
 define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
 ; CHECK-LABEL: test_vec_vsraq:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT

[llvm-branch-commits] [llvm] dfcb872 - [X86] Add scalar/vector test coverage for D93599

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T11:58:27Z
New Revision: dfcb872c3e82c821bb32a2dd53ab73314d38ce38

URL: 
https://github.com/llvm/llvm-project/commit/dfcb872c3e82c821bb32a2dd53ab73314d38ce38
DIFF: 
https://github.com/llvm/llvm-project/commit/dfcb872c3e82c821bb32a2dd53ab73314d38ce38.diff

LOG: [X86] Add scalar/vector test coverage for D93599

This expands the test coverage beyond just the boolvector/movmsk concat pattern

Added: 
llvm/test/CodeGen/X86/cmp-concat.ll

Modified: 


Removed: 




diff  --git a/llvm/test/CodeGen/X86/cmp-concat.ll 
b/llvm/test/CodeGen/X86/cmp-concat.ll
new file mode 100644
index ..a622ad7faff7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/cmp-concat.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s
+
+define i1 @cmp_allbits_concat_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: cmp_allbits_concat_i8:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:movzbl %sil, %eax
+; CHECK-NEXT:shll $8, %edi
+; CHECK-NEXT:orl %eax, %edi
+; CHECK-NEXT:cmpw $-1, %di
+; CHECK-NEXT:sete %al
+; CHECK-NEXT:retq
+  %zx = zext i8 %x to i16
+  %zy = zext i8 %y to i16
+  %sh = shl i16 %zx, 8
+  %or = or i16 %zy, %sh
+  %r = icmp eq i16 %or, -1
+  ret i1 %r
+}
+
+define i1 @cmp_anybits_concat_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: cmp_anybits_concat_i32:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:# kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:movl %esi, %eax
+; CHECK-NEXT:shlq $32, %rdi
+; CHECK-NEXT:orq %rax, %rdi
+; CHECK-NEXT:setne %al
+; CHECK-NEXT:retq
+  %zx = zext i32 %x to i64
+  %zy = zext i32 %y to i64
+  %sh = shl i64 %zx, 32
+  %or = or i64 %zy, %sh
+  %r = icmp ne i64 %or, 0
+  ret i1 %r
+}
+
+define <16 x i8> @cmp_allbits_concat_v16i8(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: cmp_allbits_concat_v16i8:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:movdqa %xmm1, %xmm2
+; CHECK-NEXT:punpcklbw {{.*#+}} xmm2 = 
xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; CHECK-NEXT:punpckhbw {{.*#+}} xmm1 = 
xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; CHECK-NEXT:pcmpeqd %xmm0, %xmm0
+; CHECK-NEXT:pcmpeqw %xmm0, %xmm1
+; CHECK-NEXT:pcmpeqw %xmm2, %xmm0
+; CHECK-NEXT:packsswb %xmm1, %xmm0
+; CHECK-NEXT:retq
+  %zx = zext <16 x i8> %x to <16 x i16>
+  %zy = zext <16 x i8> %y to <16 x i16>
+  %sh = shl <16 x i16> %zx, 
+  %or = or <16 x i16> %zy, %sh
+  %r = icmp eq <16 x i16> %or, 
+  %s = sext <16 x i1> %r to <16 x i8>
+  ret <16 x i8> %s
+}
+
+define <2 x i64> @cmp_nobits_concat_v2i64(<2 x i64> %x, <2 x i64> %y) {
+; CHECK-LABEL: cmp_nobits_concat_v2i64:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:movq %xmm0, %rax
+; CHECK-NEXT:pextrq $1, %xmm0, %rcx
+; CHECK-NEXT:movq %xmm1, %rdx
+; CHECK-NEXT:pextrq $1, %xmm1, %rsi
+; CHECK-NEXT:xorl %edi, %edi
+; CHECK-NEXT:orq %rcx, %rsi
+; CHECK-NEXT:sete %dil
+; CHECK-NEXT:negq %rdi
+; CHECK-NEXT:movq %rdi, %xmm1
+; CHECK-NEXT:xorl %ecx, %ecx
+; CHECK-NEXT:orq %rax, %rdx
+; CHECK-NEXT:sete %cl
+; CHECK-NEXT:negq %rcx
+; CHECK-NEXT:movq %rcx, %xmm0
+; CHECK-NEXT:punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:retq
+  %zx = zext <2 x i64> %x to <2 x i128>
+  %zy = zext <2 x i64> %y to <2 x i128>
+  %sh = shl <2 x i128> %zx, 
+  %or = or <2 x i128> %zy, %sh
+  %r = icmp eq <2 x i128> %or, zeroinitializer
+  %s = sext <2 x i1> %r to <2 x i64>
+  ret <2 x i64> %s
+}



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[llvm-branch-commits] [libc] 223a6f9 - [libc] remove modulo from CircularArrayRef iterator

[Guillaume Chatelet via llvm-branch-commits]

Author: Guillaume Chatelet
Date: 2021-01-06T12:03:52Z
New Revision: 223a6f94c59c00733763bacc43f5b9458b4cc6f4

URL: 
https://github.com/llvm/llvm-project/commit/223a6f94c59c00733763bacc43f5b9458b4cc6f4
DIFF: 
https://github.com/llvm/llvm-project/commit/223a6f94c59c00733763bacc43f5b9458b4cc6f4.diff

LOG: [libc] remove modulo from CircularArrayRef iterator

Added: 


Modified: 
libc/benchmarks/LibcBenchmark.h

Removed: 




diff  --git a/libc/benchmarks/LibcBenchmark.h b/libc/benchmarks/LibcBenchmark.h
index 6516e5f8be94..af6173ab41a0 100644
--- a/libc/benchmarks/LibcBenchmark.h
+++ b/libc/benchmarks/LibcBenchmark.h
@@ -275,17 +275,21 @@ template  class CircularArrayRef {
   : public std::iterator {
 llvm::ArrayRef Array;
 size_t Index;
+size_t Offset;
 
   public:
 explicit const_iterator(llvm::ArrayRef Array, size_t Index = 0)
-: Array(Array), Index(Index) {}
+: Array(Array), Index(Index), Offset(Index % Array.size()) {}
 const_iterator &operator++() {
   ++Index;
+  ++Offset;
+  if (Offset == Array.size())
+Offset = 0;
   return *this;
 }
 bool operator==(const_iterator Other) const { return Index == Other.Index; 
}
 bool operator!=(const_iterator Other) const { return !(*this == Other); }
-const T &operator*() const { return Array[Index % Array.size()]; }
+const T &operator*() const { return Array[Offset]; }
   };
 
   CircularArrayRef(llvm::ArrayRef Array, size_t Size)



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[llvm-branch-commits] [libc] aa9db51 - [libc] Align src buffer instead of dst buffer

[Guillaume Chatelet via llvm-branch-commits]

Author: Guillaume Chatelet
Date: 2021-01-06T12:04:53Z
New Revision: aa9db51ef69f36775e9babd2f4b23142967784ee

URL: 
https://github.com/llvm/llvm-project/commit/aa9db51ef69f36775e9babd2f4b23142967784ee
DIFF: 
https://github.com/llvm/llvm-project/commit/aa9db51ef69f36775e9babd2f4b23142967784ee.diff

LOG: [libc] Align src buffer instead of dst buffer

We used to align destination buffer instead of source buffer for the loop of 
block copy.
This is a mistake.

Differential Revision: https://reviews.llvm.org/D93457

Added: 


Modified: 
libc/src/string/memory_utils/memcpy_utils.h
libc/test/src/string/memory_utils/memcpy_utils_test.cpp

Removed: 




diff  --git a/libc/src/string/memory_utils/memcpy_utils.h 
b/libc/src/string/memory_utils/memcpy_utils.h
index aa27b3c38dbd..1e7d907d2333 100644
--- a/libc/src/string/memory_utils/memcpy_utils.h
+++ b/libc/src/string/memory_utils/memcpy_utils.h
@@ -90,7 +90,7 @@ static void CopyAlignedBlocks(char *__restrict dst, const 
char *__restrict src,
   CopyBlock(dst, src); // Copy first block
 
   // Copy aligned blocks
-  const size_t ofla = offset_from_last_aligned(dst);
+  const size_t ofla = offset_from_last_aligned(src);
   const size_t limit = count + ofla - kBlockSize;
   for (size_t offset = kBlockSize; offset < limit; offset += kBlockSize)
 CopyBlock(dst - ofla + offset, src - ofla + offset);

diff  --git a/libc/test/src/string/memory_utils/memcpy_utils_test.cpp 
b/libc/test/src/string/memory_utils/memcpy_utils_test.cpp
index 93c0c48c8976..d466495357c2 100644
--- a/libc/test/src/string/memory_utils/memcpy_utils_test.cpp
+++ b/libc/test/src/string/memory_utils/memcpy_utils_test.cpp
@@ -162,14 +162,14 @@ TEST(MemcpyUtilsTest, CopyBlockOverlap) {
 
 TEST(MemcpyUtilsTest, CopyAlignedBlocks) {
   auto &trace = GetTrace();
-  // Destination is aligned and multiple of alignment.
+  // Source is aligned and multiple of alignment.
   //   ""
   trace.Clear();
   CopyAlignedBlocks<4>(I(0), I(0), 4);
   EXPECT_STREQ(trace.Write(), "");
   EXPECT_STREQ(trace.Read(), "");
 
-  // Destination is aligned and multiple of alignment.
+  // Source is aligned and multiple of alignment.
   //   ""
   // + ""
   // = ""
@@ -178,7 +178,7 @@ TEST(MemcpyUtilsTest, CopyAlignedBlocks) {
   EXPECT_STREQ(trace.Write(), "");
   EXPECT_STREQ(trace.Read(), "");
 
-  // Destination is aligned already overlap at end.
+  // Source is aligned already overlap at end.
   //   "0"
   // + "0"
   // + "0"
@@ -189,26 +189,26 @@ TEST(MemcpyUtilsTest, CopyAlignedBlocks) {
   EXPECT_STREQ(trace.Write(), "12221");
   EXPECT_STREQ(trace.Read(), "12221");
 
-  // Misaligned destination.
+  // Misaligned source.
   //   "00"
   // + "00"
   // + "00"
   // + "00"
   // = "0111212211"
   trace.Clear();
-  CopyAlignedBlocks<4>(I(1), I(0), 13);
-  EXPECT_STREQ(trace.Write(), "0111212211");
-  EXPECT_STREQ(trace.Read(), "111212211");
+  CopyAlignedBlocks<4>(I(0), I(1), 13);
+  EXPECT_STREQ(trace.Write(), "111212211");
+  EXPECT_STREQ(trace.Read(), "0111212211");
 
-  // Misaligned destination aligned at end.
+  // Misaligned source aligned at end.
   //   "0000"
   // + ""
   // + ""
   // = "01112111"
   trace.Clear();
-  CopyAlignedBlocks<4>(I(1), I(0), 11);
-  EXPECT_STREQ(trace.Write(), "01112111");
-  EXPECT_STREQ(trace.Read(), "1112111");
+  CopyAlignedBlocks<4>(I(0), I(1), 11);
+  EXPECT_STREQ(trace.Write(), "1112111");
+  EXPECT_STREQ(trace.Read(), "01112111");
 }
 
 TEST(MemcpyUtilsTest, MaxReloads) {



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[llvm-branch-commits] [llvm] 643e3c9 - [AArch64] Add BRB IALL and BRB INJ instructions

[Tomas Matheson via llvm-branch-commits]

Author: Tomas Matheson
Date: 2021-01-06T12:10:22Z
New Revision: 643e3c90761f30194a76671065d221d3cb71a199

URL: 
https://github.com/llvm/llvm-project/commit/643e3c90761f30194a76671065d221d3cb71a199
DIFF: 
https://github.com/llvm/llvm-project/commit/643e3c90761f30194a76671065d221d3cb71a199.diff

LOG: [AArch64] Add BRB IALL and BRB INJ instructions

BRB IALL: Invalidate the Branch Record Buffer
BRB INJ: Branch Record Injection into the Branch Record Buffer

Parser changes based on work by Simon Tatham.

These are two-word mnemonics. The assembly parser works by special-casing
the mnemonic in order to parse the second word as a plain identifier token.

Reviewed by: MarkMurrayARM

Differential Revision: https://reviews.llvm.org/D93899

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/brbe.s

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td 
b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 6209f51b1631..efc38292842c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -813,7 +813,21 @@ def WFET : RegInputSystemI<0b, 0b000, "wfet">;
 def WFIT : RegInputSystemI<0b, 0b001, "wfit">;
 }
 
+// Branch Record Buffer two-word mnemonic instructions
+class BRBEI op2, string keyword>
+: SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> {
+  let Inst{31-8} = 0b11010101100101110010;
+  let Inst{7-5} = op2;
+  let Predicates = [HasBRBE];
 }
+def BRB_IALL: BRBEI<0b100, "\tiall">;
+def BRB_INJ:  BRBEI<0b101, "\tinj">;
+
+}
+
+// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ
+def : TokenAlias<"INJ", "inj">;
+def : TokenAlias<"IALL", "iall">;
 
 // ARMv8.2-A Dot Product
 let Predicates = [HasDotProd] in {

diff  --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 26e093bf4ce7..0916cf92640b 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -159,6 +159,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
   bool parseSymbolicImmVal(const MCExpr *&ImmVal);
   bool parseNeonVectorList(OperandVector &Operands);
   bool parseOptionalMulOperand(OperandVector &Operands);
+  bool parseKeywordOperand(OperandVector &Operands);
   bool parseOperand(OperandVector &Operands, bool isCondCode,
 bool invertCondCode);
   bool parseImmExpr(int64_t &Out);
@@ -3701,6 +3702,17 @@ bool 
AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
   return Error(getLoc(), "expected 'vl' or '#'");
 }
 
+bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  auto Tok = Parser.getTok();
+  if (Tok.isNot(AsmToken::Identifier))
+return true;
+  Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
+ Tok.getLoc(), getContext()));
+  Parser.Lex();
+  return false;
+}
+
 /// parseOperand - Parse a arm instruction operand.  For now this parses the
 /// operand regardless of the mnemonic.
 bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
@@ -3765,6 +3777,11 @@ bool AArch64AsmParser::parseOperand(OperandVector 
&Operands, bool isCondCode,
 if (GotShift != MatchOperand_NoMatch)
   return GotShift;
 
+// If this is a two-word mnemonic, parse its special keyword
+// operand as an identifier.
+if (Mnemonic == "brb")
+  return parseKeywordOperand(Operands);
+
 // This was not a register so parse other operands that start with an
 // identifier (like labels) as expressions and create them as immediates.
 const MCExpr *IdVal;

diff  --git a/llvm/test/MC/AArch64/brbe.s b/llvm/test/MC/AArch64/brbe.s
index 7b0dfe4955ad..f02017dae8e5 100644
--- a/llvm/test/MC/AArch64/brbe.s
+++ b/llvm/test/MC/AArch64/brbe.s
@@ -133,3 +133,17 @@ mrs x5, BRBTGT31_EL1
 // CHECK: mrs x5, BRBTGT31_EL1// encoding: [0xc5,0x8f,0x31,0xd5]
 // ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
 // ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
+
+brb iall
+brb inj
+// CHECK: brb iall  // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj   // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+
+brb IALL
+brb INJ
+// CHECK: brb iall  // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj   // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe



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[llvm-branch-commits] [llvm] 37ac4f8 - [Hexagon] Regenerate zext-v4i1.ll tests

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T12:56:06Z
New Revision: 37ac4f865fba451d969bd9b4b1e28ce296e093da

URL: 
https://github.com/llvm/llvm-project/commit/37ac4f865fba451d969bd9b4b1e28ce296e093da
DIFF: 
https://github.com/llvm/llvm-project/commit/37ac4f865fba451d969bd9b4b1e28ce296e093da.diff

LOG: [Hexagon] Regenerate zext-v4i1.ll tests

This will be improved by part of the work for D86578

Added: 


Modified: 
llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll

Removed: 




diff  --git a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll 
b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
index e5394d929bb1..5f9a1522a2f6 100644
--- a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
@@ -1,12 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s
 
 ; Check that this compiles successfully.
-; CHECK: vcmph.eq
 
 target datalayout = 
"e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon"
 
 define i32 @fred(<8 x i16>* %a0) #0 {
+; CHECK-LABEL: fred:
+; CHECK:   // %bb.0: // %b0
+; CHECK-NEXT:{
+; CHECK-NEXT: if (p0) jump:nt .LBB0_2
+; CHECK-NEXT:}
+; CHECK-NEXT:  // %bb.1: // %b2
+; CHECK-NEXT:{
+; CHECK-NEXT: r3:2 = combine(#0,#0)
+; CHECK-NEXT: r1:0 = memd(r0+#0)
+; CHECK-NEXT:}
+; CHECK-NEXT:{
+; CHECK-NEXT: p0 = vcmph.eq(r1:0,r3:2)
+; CHECK-NEXT:}
+; CHECK-NEXT:{
+; CHECK-NEXT: r1:0 = mask(p0)
+; CHECK-NEXT:}
+; CHECK-NEXT:{
+; CHECK-NEXT: r0 = and(r0,#1)
+; CHECK-NEXT:}
+; CHECK-NEXT:{
+; CHECK-NEXT: p0 = cmp.eq(r0,#11)
+; CHECK-NEXT: r0 = #1
+; CHECK-NEXT:}
+; CHECK-NEXT:{
+; CHECK-NEXT: if (p0) r0 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT:}
+; CHECK-NEXT:  .LBB0_2: // %b14
+; CHECK-NEXT:{
+; CHECK-NEXT: r0 = #0
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT:}
 b0:
   switch i32 undef, label %b14 [
 i32 5, label %b2



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[llvm-branch-commits] [clang] 29d375f - [OpenCL][NFC] Improve OpenCL test file naming

[Sven van Haastregt via llvm-branch-commits]

Author: Sven van Haastregt
Date: 2021-01-06T14:16:44Z
New Revision: 29d375f5ff27dc49c2c88c2ec1093cfcd826d449

URL: 
https://github.com/llvm/llvm-project/commit/29d375f5ff27dc49c2c88c2ec1093cfcd826d449
DIFF: 
https://github.com/llvm/llvm-project/commit/29d375f5ff27dc49c2c88c2ec1093cfcd826d449.diff

LOG: [OpenCL][NFC] Improve OpenCL test file naming

Change "negative" into "invalid" and put "invalid" at the beginning of
the file name, following the bulk of the invalid tests in the
SemaOpenCL directory.

Use the "invalid-" prefix only for tests that contain only invalid
constructs.

Drop the "valid" suffix for CodeGen tests, as inputs in this directory
are supposed to be valid anyway.

Added: 
clang/test/CodeGenOpenCL/vector_literals.cl
clang/test/CodeGenOpenCL/vector_shufflevector.cl
clang/test/SemaOpenCL/invalid-pipes-cl1.2.cl
clang/test/SemaOpenCL/invalid-vector-literals.cl
clang/test/SemaOpenCL/vector-conv.cl
clang/test/SemaOpenCLCXX/invalid-kernel.cl

Modified: 


Removed: 
clang/test/CodeGenOpenCL/vector_literals_valid.cl
clang/test/CodeGenOpenCL/vector_shufflevector_valid.cl
clang/test/SemaOpenCL/pipes-1.2-negative.cl
clang/test/SemaOpenCL/vector_conv_invalid.cl
clang/test/SemaOpenCL/vector_literals_invalid.cl
clang/test/SemaOpenCLCXX/kernel_invalid.cl



diff  --git a/clang/test/CodeGenOpenCL/vector_literals_valid.cl 
b/clang/test/CodeGenOpenCL/vector_literals.cl
similarity index 100%
rename from clang/test/CodeGenOpenCL/vector_literals_valid.cl
rename to clang/test/CodeGenOpenCL/vector_literals.cl

diff  --git a/clang/test/CodeGenOpenCL/vector_shufflevector_valid.cl 
b/clang/test/CodeGenOpenCL/vector_shufflevector.cl
similarity index 100%
rename from clang/test/CodeGenOpenCL/vector_shufflevector_valid.cl
rename to clang/test/CodeGenOpenCL/vector_shufflevector.cl

diff  --git a/clang/test/SemaOpenCL/pipes-1.2-negative.cl 
b/clang/test/SemaOpenCL/invalid-pipes-cl1.2.cl
similarity index 100%
rename from clang/test/SemaOpenCL/pipes-1.2-negative.cl
rename to clang/test/SemaOpenCL/invalid-pipes-cl1.2.cl

diff  --git a/clang/test/SemaOpenCL/vector_literals_invalid.cl 
b/clang/test/SemaOpenCL/invalid-vector-literals.cl
similarity index 100%
rename from clang/test/SemaOpenCL/vector_literals_invalid.cl
rename to clang/test/SemaOpenCL/invalid-vector-literals.cl

diff  --git a/clang/test/SemaOpenCL/vector_conv_invalid.cl 
b/clang/test/SemaOpenCL/vector-conv.cl
similarity index 100%
rename from clang/test/SemaOpenCL/vector_conv_invalid.cl
rename to clang/test/SemaOpenCL/vector-conv.cl

diff  --git a/clang/test/SemaOpenCLCXX/kernel_invalid.cl 
b/clang/test/SemaOpenCLCXX/invalid-kernel.cl
similarity index 100%
rename from clang/test/SemaOpenCLCXX/kernel_invalid.cl
rename to clang/test/SemaOpenCLCXX/invalid-kernel.cl



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[llvm-branch-commits] [llvm] 396dd6c - [ProfileData] Pass Twine by const reference instead of by value.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T14:22:03Z
New Revision: 396dd6cd3d8bdcda9dcb606ad4c054560bf0649f

URL: 
https://github.com/llvm/llvm-project/commit/396dd6cd3d8bdcda9dcb606ad4c054560bf0649f
DIFF: 
https://github.com/llvm/llvm-project/commit/396dd6cd3d8bdcda9dcb606ad4c054560bf0649f.diff

LOG: [ProfileData] Pass Twine by const reference instead of by value.

Its only used by DiagnosticInfoSampleProfile which takes a const reference 
anyhow.

Added: 


Modified: 
llvm/include/llvm/ProfileData/SampleProfReader.h

Removed: 




diff  --git a/llvm/include/llvm/ProfileData/SampleProfReader.h 
b/llvm/include/llvm/ProfileData/SampleProfReader.h
index 35e71f336c27..92fe825beefc 100644
--- a/llvm/include/llvm/ProfileData/SampleProfReader.h
+++ b/llvm/include/llvm/ProfileData/SampleProfReader.h
@@ -226,7 +226,6 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Twine.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/LLVMContext.h"
@@ -247,6 +246,7 @@
 namespace llvm {
 
 class raw_ostream;
+class Twine;
 
 namespace sampleprof {
 
@@ -408,7 +408,7 @@ class SampleProfileReader {
   StringMap &getProfiles() { return Profiles; }
 
   /// Report a parse error message.
-  void reportError(int64_t LineNumber, Twine Msg) const {
+  void reportError(int64_t LineNumber, const Twine &Msg) const {
 Ctx.diagnose(DiagnosticInfoSampleProfile(Buffer->getBufferIdentifier(),
  LineNumber, Msg));
   }



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[llvm-branch-commits] [llvm] df5c2ca - [MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. NFCI.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T14:22:04Z
New Revision: df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a

URL: 
https://github.com/llvm/llvm-project/commit/df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a
DIFF: 
https://github.com/llvm/llvm-project/commit/df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a.diff

LOG: [MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. 
NFCI.

Added: 


Modified: 
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Removed: 




diff  --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 9dbbdeb34dba..e4d61f8c210e 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -352,8 +352,8 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
  const MCSubtargetInfo *STI);
 
-  bool reportParseError(Twine ErrorMsg);
-  bool reportParseError(SMLoc Loc, Twine ErrorMsg);
+  bool reportParseError(const Twine &ErrorMsg);
+  bool reportParseError(SMLoc Loc, const Twine &ErrorMsg);
 
   bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
 
@@ -6982,12 +6982,12 @@ bool 
MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 
 // FIXME: Given that these have the same name, these should both be
 // consistent on affecting the Parser.
-bool MipsAsmParser::reportParseError(Twine ErrorMsg) {
+bool MipsAsmParser::reportParseError(const Twine &ErrorMsg) {
   SMLoc Loc = getLexer().getLoc();
   return Error(Loc, ErrorMsg);
 }
 
-bool MipsAsmParser::reportParseError(SMLoc Loc, Twine ErrorMsg) {
+bool MipsAsmParser::reportParseError(SMLoc Loc, const Twine &ErrorMsg) {
   return Error(Loc, ErrorMsg);
 }
 



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[llvm-branch-commits] [llvm] 26c486c - [TableGen] RegisterBankEmitter - Pass Twine by const reference instead of by value. NFCI.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T14:22:05Z
New Revision: 26c486c2eb1a0f302eb60a4b959456f09adbbacb

URL: 
https://github.com/llvm/llvm-project/commit/26c486c2eb1a0f302eb60a4b959456f09adbbacb
DIFF: 
https://github.com/llvm/llvm-project/commit/26c486c2eb1a0f302eb60a4b959456f09adbbacb.diff

LOG: [TableGen] RegisterBankEmitter - Pass Twine by const reference instead of 
by value. NFCI.

Added: 


Modified: 
llvm/utils/TableGen/RegisterBankEmitter.cpp

Removed: 




diff  --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp 
b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 6a45213e1d66..0725657150f8 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -168,7 +168,7 @@ void RegisterBankEmitter::emitBaseClassDefinition(
 ///to the class.
 static void visitRegisterBankClasses(
 const CodeGenRegBank &RegisterClassHierarchy,
-const CodeGenRegisterClass *RC, const Twine Kind,
+const CodeGenRegisterClass *RC, const Twine &Kind,
 std::function VisitFn,
 SmallPtrSetImpl &VisitedRCs) {
 
@@ -182,7 +182,7 @@ static void visitRegisterBankClasses(
 
   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
 std::string TmpKind =
-(Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();
+(Kind + " (" + PossibleSubclass.getName() + ")").str();
 
 // Visit each subclass of an explicitly named class.
 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))



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[llvm-branch-commits] [mlir] f60e0a9 - [MLIR][SPIRV] Add `UnsignedOp` trait.

[via llvm-branch-commits]

Author: KareemErgawy-TomTom
Date: 2021-01-06T15:28:41+01:00
New Revision: f60e0a91fbdd8e3409f5ee883a05a6c77f70720c

URL: 
https://github.com/llvm/llvm-project/commit/f60e0a91fbdd8e3409f5ee883a05a6c77f70720c
DIFF: 
https://github.com/llvm/llvm-project/commit/f60e0a91fbdd8e3409f5ee883a05a6c77f70720c.diff

LOG: [MLIR][SPIRV] Add `UnsignedOp` trait.

This commit adds a new trait that can be attached to ops that have
unsigned semantics.

TODO:
- Check if other places in code can use the new attribute (possibly in this 
patch).
- Add a similar `SignedOp` attribute (in a new patch).

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D94068

Added: 
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOpTraits.h

Modified: 
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp

Removed: 




diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td 
b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
index 0d6dd015b7e3..609f5105e11b 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
@@ -514,7 +514,7 @@ def SPV_SRemOp : SPV_ArithmeticBinaryOp<"SRem", 
SPV_Integer, []> {
 
 // -
 
-def SPV_UDivOp : SPV_ArithmeticBinaryOp<"UDiv", SPV_Integer, []> {
+def SPV_UDivOp : SPV_ArithmeticBinaryOp<"UDiv", SPV_Integer, [UnsignedOp]> {
   let summary = "Unsigned-integer division of Operand 1 divided by Operand 2.";
 
   let description = [{
@@ -546,7 +546,7 @@ def SPV_UDivOp : SPV_ArithmeticBinaryOp<"UDiv", 
SPV_Integer, []> {
 
 // -
 
-def SPV_UModOp : SPV_ArithmeticBinaryOp<"UMod", SPV_Integer> {
+def SPV_UModOp : SPV_ArithmeticBinaryOp<"UMod", SPV_Integer, [UnsignedOp]> {
   let summary = "Unsigned modulo operation of Operand 1 modulo Operand 2.";
 
   let description = [{

diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td 
b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
index 1c9dbd758857..289e9a23bb35 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
@@ -438,7 +438,7 @@ def SPV_AtomicSMinOp : 
SPV_AtomicUpdateWithValueOp<"AtomicSMin", []> {
 
 // -
 
-def SPV_AtomicUMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicUMax", []> {
+def SPV_AtomicUMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicUMax", [UnsignedOp]> 
{
   let summary = [{
 Perform the following steps atomically with respect to any other atomic
 accesses within Scope to the same location:
@@ -480,7 +480,7 @@ def SPV_AtomicUMaxOp : 
SPV_AtomicUpdateWithValueOp<"AtomicUMax", []> {
 
 // -
 
-def SPV_AtomicUMinOp : SPV_AtomicUpdateWithValueOp<"AtomicUMin", []> {
+def SPV_AtomicUMinOp : SPV_AtomicUpdateWithValueOp<"AtomicUMin", [UnsignedOp]> 
{
   let summary = [{
 Perform the following steps atomically with respect to any other atomic
 accesses within Scope to the same location:

diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td 
b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index 2ed11015b960..a9603adc3df0 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -3115,6 +3115,8 @@ def InModuleScope : PredOpTrait<
   "op must appear in a module-like op's block",
   CPred<"isDirectInModuleLikeOp($_op.getParentOp())">>;
 
+def UnsignedOp : NativeOpTrait<"spirv::UnsignedOp">;
+
 
//===--===//
 // SPIR-V opcode specification
 
//===--===//

diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td 
b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
index 3df9798c4d81..173a031ebaee 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
@@ -232,7 +232,8 @@ def SPV_BitFieldSExtractOp : 
SPV_BitFieldExtractOp<"BitFieldSExtract", []> {
 
 // -
 
-def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract", []> {
+def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract",
+   [UnsignedOp]> {
   let summary = "Extract a bit field from an object, without sign extension.";
 
   let description = [{

diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td 
b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td
index 726f79f94fa1..20d4afd87035 100644
--- a/mlir

[llvm-branch-commits] [lldb] 4e0e79d - [lldb] Simplify some lldb-server tests

[Pavel Labath via llvm-branch-commits]

Author: Pavel Labath
Date: 2021-01-06T15:39:51+01:00
New Revision: 4e0e79dd349a208384449fd8dcdc9bf1644ee0f3

URL: 
https://github.com/llvm/llvm-project/commit/4e0e79dd349a208384449fd8dcdc9bf1644ee0f3
DIFF: 
https://github.com/llvm/llvm-project/commit/4e0e79dd349a208384449fd8dcdc9bf1644ee0f3.diff

LOG: [lldb] Simplify some lldb-server tests

Remove manual test duplication.

Added: 


Modified: 
lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py

lldb/test/API/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.py

lldb/test/API/tools/lldb-server/memory-allocation/TestGdbRemoteMemoryAllocation.py
lldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
lldb/test/API/tools/lldb-server/thread-name/TestGdbRemoteThreadName.py

Removed: 




diff  --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py 
b/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
index 9d9c4d89e0b5..a16ba6dc3443 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
@@ -3,7 +3,6 @@
 from lldbsuite.test.lldbtest import *
 from lldbsuite.test import lldbutil
 
-
 class TestGdbRemoteAuxvSupport(gdbremote_testcase.GdbRemoteTestCaseBase):
 
 mydir = TestBase.compute_mydir(__file__)
@@ -11,25 +10,9 @@ class 
TestGdbRemoteAuxvSupport(gdbremote_testcase.GdbRemoteTestCaseBase):
 AUXV_SUPPORT_FEATURE_NAME = "qXfer:auxv:read"
 
 def has_auxv_support(self):
-inferior_args = ["message:main entered", "sleep:5"]
-procs = self.prep_debug_monitor_and_inferior(
-inferior_args=inferior_args)
-
-# Don't do anything until we match the launched inferior main entry 
output.
-# Then immediately interrupt the process.
-# This prevents auxv data being asked for before it's ready and leaves
-# us in a stopped state.
-self.test_sequence.add_log_lines([
-# Start the inferior...
-"read packet: $c#63",
-# ... match output
-{"type": "output_match", "regex": self.maybe_strict_output_regex(
-r"message:main entered\r\n")},
-], True)
-# ... then interrupt.
-self.add_interrupt_packets()
-self.add_qSupported_packets()
+procs = self.prep_debug_monitor_and_inferior()
 
+self.add_qSupported_packets()
 context = self.expect_gdbremote_sequence()
 self.assertIsNotNone(context)
 
@@ -87,27 +70,19 @@ def get_raw_auxv_data(self):
 self.assertIsNotNone(content_raw)
 return (word_size, self.decode_gdbremote_binary(content_raw))
 
-def supports_auxv(self):
-# When non-auxv platforms support llgs, skip the test on platforms
-# that don't support auxv.
+@skipIfWindows # no auxv support.
+@skipIfDarwin
+def test_supports_auxv(self):
+self.build()
+self.set_inferior_startup_launch()
 self.assertTrue(self.has_auxv_support())
 
-#
-# We skip the "supports_auxv" test on debugserver.  The rest of the tests
-# appropriately skip the auxv tests if the support flag is not present
-# in the qSupported response, so the debugserver test bits are still there
-# in case debugserver code one day does have auxv support and thus those
-# tests don't get skipped.
-#
-
-@skipIfWindows # no auxv support.
-@llgs_test
-def test_supports_auxv_llgs(self):
+@skipIfWindows
+@expectedFailureNetBSD
+def test_auxv_data_is_correct_size(self):
 self.build()
 self.set_inferior_startup_launch()
-self.supports_auxv()
 
-def auxv_data_is_correct_size(self):
 (word_size, auxv_data) = self.get_raw_auxv_data()
 self.assertIsNotNone(auxv_data)
 
@@ -116,21 +91,12 @@ def auxv_data_is_correct_size(self):
 self.assertEqual(len(auxv_data) % (2 * word_size), 0)
 self.trace("auxv contains {} entries".format(len(auxv_data) / 
(2*word_size)))
 
-@debugserver_test
-def test_auxv_data_is_correct_size_debugserver(self):
-self.build()
-self.set_inferior_startup_launch()
-self.auxv_data_is_correct_size()
-
 @skipIfWindows
 @expectedFailureNetBSD
-@llgs_test
-def test_auxv_data_is_correct_size_llgs(self):
+def test_auxv_keys_look_valid(self):
 self.build()
 self.set_inferior_startup_launch()
-self.auxv_data_is_correct_size()
 
-def auxv_keys_look_valid(self):
 (word_size, auxv_data) = self.get_raw_auxv_data()
 self.assertIsNotNone(auxv_data)
 
@@ -154,21 +120,12 @@ def auxv_keys_look_valid(self):
 self.assertTrue(auxv_key <= 1000)
 self.trace("auxv dict: {}".format(auxv_dict))
 
-@debugserver_test
-def test_auxv_keys_look_valid_debugserver(self):
-self.build()
-self

[llvm-branch-commits] [llvm] 494db38 - [LoopDeletion] Also consider loops with subloops for deletion.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-06T14:49:00Z
New Revision: 494db3816b0ece5b6722054f75cc2622ae1b840a

URL: 
https://github.com/llvm/llvm-project/commit/494db3816b0ece5b6722054f75cc2622ae1b840a
DIFF: 
https://github.com/llvm/llvm-project/commit/494db3816b0ece5b6722054f75cc2622ae1b840a.diff

LOG: [LoopDeletion] Also consider loops with subloops for deletion.

Currently, LoopDeletion does skip loops that have sub-loops, but this
means we currently fail to remove some no-op loops.

One example are inner loops with live-out values. Those cannot be
removed by itself. But the containing loop may itself be a no-op and the
whole loop-nest can be deleted.

The legality checks do not seem to rely on analyzing inner-loops only
for correctness.

With LoopDeletion being a LoopPass, the change means that we now
unfortunately need to do some extra work in parent loops, by checking
some conditions we already checked. But there appears to be no
noticeable compile time impact:
http://llvm-compile-time-tracker.com/compare.php?from=02d11f3cda2ab5b8bf4fc02639fd1f4b8c45963e&to=843201e9cf3b6871e18c52aede5897a22994c36c&stat=instructions

This changes patch leads to ~10 more loops being deleted on
MultiSource, SPEC2000, SPEC2006 with -O3 & LTO

This patch is also required (together with a few others) to eliminate a
no-op loop in omnetpp as discussed on llvm-dev 'LoopDeletion / removal of
empty loops.' 
(http://lists.llvm.org/pipermail/llvm-dev/2020-December/147462.html)

This change becomes relevant after removing potentially infinite loops
is made possible in 'must-progress' loops (D86844).

Note that I added a function call with side-effects to an outer loop in
`llvm/test/Transforms/LoopDeletion/update-scev.ll` to preserve the
original spirit of the test.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D93716

Added: 


Modified: 
llvm/lib/Transforms/Scalar/LoopDeletion.cpp
llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
llvm/test/Transforms/LoopDeletion/unreachable-loops.ll
llvm/test/Transforms/LoopDeletion/update-scev.ll

Removed: 




diff  --git a/llvm/lib/Transforms/Scalar/LoopDeletion.cpp 
b/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
index 814cfc7ac6a9..a94676eadeab 100644
--- a/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
@@ -156,13 +156,6 @@ static LoopDeletionResult deleteLoopIfDead(Loop *L, 
DominatorTree &DT,
 << "Deletion requires Loop with preheader and dedicated exits.\n");
 return LoopDeletionResult::Unmodified;
   }
-  // We can't remove loops that contain subloops.  If the subloops were dead,
-  // they would already have been removed in earlier executions of this pass.
-  if (L->begin() != L->end()) {
-LLVM_DEBUG(dbgs() << "Loop contains subloops.\n");
-return LoopDeletionResult::Unmodified;
-  }
-
 
   BasicBlock *ExitBlock = L->getUniqueExitBlock();
 

diff  --git a/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll 
b/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
index 464c12f453a7..b7a921a8dd51 100644
--- a/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
+++ b/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
@@ -10,24 +10,7 @@ target datalayout = 
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define void @test1(i64 %N, i64 %M, %pair_t* %ptr) willreturn {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:br label [[OUTER_HEADER:%.*]]
-; CHECK:   outer.header:
-; CHECK-NEXT:[[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ 
[[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
-; CHECK-NEXT:br label [[INNER:%.*]]
-; CHECK:   inner:
-; CHECK-NEXT:[[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ 
[[INNER_IV_NEXT:%.*]], [[INNER]] ]
-; CHECK-NEXT:[[GEP:%.*]] = getelementptr [[PAIR_T:%.*]], %pair_t* 
[[PTR:%.*]], i64 [[INNER_IV]]
-; CHECK-NEXT:[[P:%.*]] = load [[PAIR_T]], %pair_t* [[GEP]], align 4
-; CHECK-NEXT:[[V_0:%.*]] = extractvalue [[PAIR_T]] [[P]], 0
-; CHECK-NEXT:[[V_1:%.*]] = extractvalue [[PAIR_T]] [[P]], 1
-; CHECK-NEXT:[[INNER_EC:%.*]] = icmp ult i64 [[V_0]], [[V_1]]
-; CHECK-NEXT:[[INNER_IV_NEXT]] = add i64 [[INNER_IV]], 1
-; CHECK-NEXT:br i1 [[INNER_EC]], label [[OUTER_LATCH]], label [[INNER]]
-; CHECK:   outer.latch:
-; CHECK-NEXT:[[LCSSA:%.*]] = phi i64 [ [[V_1]], [[INNER]] ]
-; CHECK-NEXT:[[OUTER_EC:%.*]] = icmp ult i64 [[OUTER_IV]], [[LCSSA]]
-; CHECK-NEXT:[[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
-; CHECK-NEXT:br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
+; CHECK-NEXT:br label [[EXIT:%.*]]
 ; CHECK:   exit:
 ; CHECK-NEXT:ret void
 ;

diff  --git a/llvm/test/Transforms/LoopDeletion/unreachable-loops.ll 
b/llvm/test/Transforms/LoopDeletion/unreachable-loops.ll
index a74ddf99285e..c9e178fbf586 100644
--- a/llvm/

[llvm-branch-commits] [clang] 0c41b1c - [Driver][MachineOutliner] Support outlining option with LTO

[Yvan Roux via llvm-branch-commits]

Author: Yvan Roux
Date: 2021-01-06T16:01:38+01:00
New Revision: 0c41b1c9f93c09966b87126820d3cf41d8eebbf9

URL: 
https://github.com/llvm/llvm-project/commit/0c41b1c9f93c09966b87126820d3cf41d8eebbf9
DIFF: 
https://github.com/llvm/llvm-project/commit/0c41b1c9f93c09966b87126820d3cf41d8eebbf9.diff

LOG: [Driver][MachineOutliner] Support outlining option with LTO

This patch propagates the -moutline flag when LTO is enabled and avoids
passing it explicitly to the linker plugin.

Differential Revision: https://reviews.llvm.org/D93385

Added: 
clang/test/Driver/arm-machine-outliner.c

Modified: 
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/CommonArgs.cpp
clang/lib/Driver/ToolChains/CommonArgs.h

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index f8b9bf25373e..917601836c0a 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6396,26 +6396,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction 
&JA,
 options::OPT_fno_cxx_static_destructors, true))
 CmdArgs.push_back("-fno-c++-static-destructors");
 
-  if (Arg *A = Args.getLastArg(options::OPT_moutline,
-   options::OPT_mno_outline)) {
-if (A->getOption().matches(options::OPT_moutline)) {
-  // We only support -moutline in AArch64 and ARM targets right now. If
-  // we're not compiling for these, emit a warning and ignore the flag.
-  // Otherwise, add the proper mllvm flags.
-  if (!(Triple.isARM() || Triple.isThumb() ||
-Triple.getArch() == llvm::Triple::aarch64 ||
-Triple.getArch() == llvm::Triple::aarch64_32)) {
-D.Diag(diag::warn_drv_moutline_unsupported_opt) << 
Triple.getArchName();
-  } else {
-CmdArgs.push_back("-mllvm");
-CmdArgs.push_back("-enable-machine-outliner");
-  }
-} else {
-  // Disable all outlining behaviour.
-  CmdArgs.push_back("-mllvm");
-  CmdArgs.push_back("-enable-machine-outliner=never");
-}
-  }
+  addMachineOutlinerArgs(D, Args, CmdArgs, Triple, /*IsLTO=*/false);
 
   if (Arg *A = Args.getLastArg(options::OPT_moutline_atomics,
options::OPT_mno_outline_atomics)) {

diff  --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index fe5e7536d380..6a95aa5ec628 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -624,6 +624,9 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const 
ArgList &Args,
 
   // Handle remarks hotness/threshold related options.
   renderRemarksHotnessOptions(Args, CmdArgs);
+
+  addMachineOutlinerArgs(D, Args, CmdArgs, ToolChain.getEffectiveTriple(),
+ /*IsLTO=*/true);
 }
 
 void tools::addArchSpecificRPath(const ToolChain &TC, const ArgList &Args,
@@ -1586,3 +1589,36 @@ unsigned tools::getOrCheckAMDGPUCodeObjectVersion(
   }
   return CodeObjVer;
 }
+
+void tools::addMachineOutlinerArgs(const Driver &D,
+   const llvm::opt::ArgList &Args,
+   llvm::opt::ArgStringList &CmdArgs,
+   const llvm::Triple &Triple, bool IsLTO) {
+  auto addArg = [&, IsLTO](const Twine &Arg) {
+if (IsLTO) {
+  CmdArgs.push_back(Args.MakeArgString("-plugin-opt=" + Arg));
+} else {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back(Args.MakeArgString(Arg));
+}
+  };
+
+  if (Arg *A = Args.getLastArg(options::OPT_moutline,
+   options::OPT_mno_outline)) {
+if (A->getOption().matches(options::OPT_moutline)) {
+  // We only support -moutline in AArch64 and ARM targets right now. If
+  // we're not compiling for these, emit a warning and ignore the flag.
+  // Otherwise, add the proper mllvm flags.
+  if (!(Triple.isARM() || Triple.isThumb() ||
+Triple.getArch() == llvm::Triple::aarch64 ||
+Triple.getArch() == llvm::Triple::aarch64_32)) {
+D.Diag(diag::warn_drv_moutline_unsupported_opt) << 
Triple.getArchName();
+  } else {
+addArg(Twine("-enable-machine-outliner"));
+  }
+} else {
+  // Disable all outlining behaviour.
+  addArg(Twine("-enable-machine-outliner=never"));
+}
+  }
+}

diff  --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 9a365f376022..187c340d1c3c 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -141,6 +141,10 @@ void addX86AlignBranchArgs(const Driver &D, const 
llvm::opt::ArgList &Args,
 unsigned getOrCheckAMDGPUCodeObjectVersion(const Driver &D,
const llvm::opt::ArgList &Args,
  

[llvm-branch-commits] [clang] 3fa6ced - Fix MaterializeTemporaryExpr's type when its an incomplete array.

[Erich Keane via llvm-branch-commits]

Author: Erich Keane
Date: 2021-01-06T07:17:12-08:00
New Revision: 3fa6cedb6be809092f8a8b27e63bd4f6dc526a08

URL: 
https://github.com/llvm/llvm-project/commit/3fa6cedb6be809092f8a8b27e63bd4f6dc526a08
DIFF: 
https://github.com/llvm/llvm-project/commit/3fa6cedb6be809092f8a8b27e63bd4f6dc526a08.diff

LOG: Fix MaterializeTemporaryExpr's type when its an incomplete array.

Like the VarDecl that gets its type updated based on an init-list, this
patch corrects the MaterializeTemporaryExpr's type to make sure it isn't
creating an incomplete type, which leads to a handful of CodeGen crashes
(see PR 47636).

Based on @rsmith 's comments on D88236

Differential Revision: https://reviews.llvm.org/D88298

Added: 
clang/test/AST/pr47636.cpp

Modified: 
clang/lib/Sema/SemaInit.cpp
clang/test/CodeGenCXX/pr47636.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index b5f31bf403d4..38f6a5975ea3 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -8200,9 +8200,21 @@ ExprResult InitializationSequence::Perform(Sema &S,
   if (S.CheckExceptionSpecCompatibility(CurInit.get(), DestType))
 return ExprError();
 
+  QualType MTETy = Step->Type;
+
+  // When this is an incomplete array type (such as when this is
+  // initializing an array of unknown bounds from an init list), use THAT
+  // type instead so that we propogate the array bounds.
+  if (MTETy->isIncompleteArrayType() &&
+  !CurInit.get()->getType()->isIncompleteArrayType() &&
+  S.Context.hasSameType(
+  MTETy->getPointeeOrArrayElementType(),
+  CurInit.get()->getType()->getPointeeOrArrayElementType()))
+MTETy = CurInit.get()->getType();
+
   // Materialize the temporary into memory.
   MaterializeTemporaryExpr *MTE = S.CreateMaterializeTemporaryExpr(
-  Step->Type, CurInit.get(), 
Entity.getType()->isLValueReferenceType());
+  MTETy, CurInit.get(), Entity.getType()->isLValueReferenceType());
   CurInit = MTE;
 
   // If we're extending this temporary to automatic storage duration -- we

diff  --git a/clang/test/AST/pr47636.cpp b/clang/test/AST/pr47636.cpp
new file mode 100644
index ..29d2a0a06e79
--- /dev/null
+++ b/clang/test/AST/pr47636.cpp
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -fsyntax-only %s -ast-dump | FileCheck %s
+
+int(&&intu_rvref)[] {1,2,3,4};
+// CHECK: VarDecl 0x[[GLOB_ADDR:[0-9a-f]+]] {{.*}} intu_rvref 'int (&&)[4]' 
listinit
+// CHECK-NEXT: ExprWithCleanups {{.*}} 'int [4]' xvalue
+// CHECK-NEXT: MaterializeTemporaryExpr {{.*}} 'int [4]' xvalue extended by 
Var 0x[[GLOB_ADDR]] 'intu_rvref' 'int (&&)[4]'
+// CHECK-NEXT: InitListExpr {{.*}} 'int [4]'
+
+// CHECK: FunctionDecl {{.*}} static_const
+void static_const() {
+  static const int(&&intu_rvref)[] {1,2,3,4};
+  // CHECK: VarDecl 0x[[STATIC_ADDR:[0-9a-f]+]] {{.*}} intu_rvref 'const int 
(&&)[4]' static listinit
+  // CHECK-NEXT: ExprWithCleanups {{.*}} 'const int [4]' xvalue
+  // CHECK-NEXT: MaterializeTemporaryExpr {{.*}} 'const int [4]' xvalue 
extended by Var 0x[[STATIC_ADDR]] 'intu_rvref' 'const int (&&)[4]'
+  // CHECK-NEXT: InitListExpr {{.*}} 'const int [4]'
+}
+
+// CHECK: FunctionDecl {{.*}} const_expr
+constexpr int const_expr() {
+  int(&&intu_rvref)[]{1, 2, 3, 4};
+  // CHECK: VarDecl 0x[[CE_ADDR:[0-9a-f]+]] {{.*}} intu_rvref 'int (&&)[4]' 
listinit
+  // CHECK-NEXT: ExprWithCleanups {{.*}} 'int [4]' xvalue
+  // CHECK-NEXT: MaterializeTemporaryExpr {{.*}} 'int [4]' xvalue extended by 
Var 0x[[CE_ADDR]] 'intu_rvref' 'int (&&)[4]'
+  // CHECK-NEXT: InitListExpr {{.*}} 'int [4]'
+  return intu_rvref[0];
+}

diff  --git a/clang/test/CodeGenCXX/pr47636.cpp 
b/clang/test/CodeGenCXX/pr47636.cpp
index 64fb44114bd2..b6b31d623761 100644
--- a/clang/test/CodeGenCXX/pr47636.cpp
+++ b/clang/test/CodeGenCXX/pr47636.cpp
@@ -8,3 +8,15 @@ void foo() {
   // CHECK: @_ZZ3foovE10intu_rvref = internal constant [4 x i32]* 
@_ZGRZ3foovE10intu_rvref_
   // CHECK: @_ZGRZ3foovE10intu_rvref_ = internal constant [4 x i32] [i32 1, 
i32 2, i32 3, i32 4]
 }
+
+// Example given on review, ensure this doesn't crash as well.
+constexpr int f() {
+  // CHECK: i32 @_Z1fv()
+  int(&&intu_rvref)[]{1, 2, 3, 4};
+  // CHECK: %{{.*}} = alloca [4 x i32]*
+  return intu_rvref[2];
+}
+
+void use_f() {
+  int i = f();
+}



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[llvm-branch-commits] [mlir] 25c78de - [mlir][spirv] Update pass docs

[Lei Zhang via llvm-branch-commits]

Author: Lei Zhang
Date: 2021-01-06T10:28:55-05:00
New Revision: 25c78de6d2a50d6f90fd6cd3f0010eb3df157a6c

URL: 
https://github.com/llvm/llvm-project/commit/25c78de6d2a50d6f90fd6cd3f0010eb3df157a6c
DIFF: 
https://github.com/llvm/llvm-project/commit/25c78de6d2a50d6f90fd6cd3f0010eb3df157a6c.diff

LOG: [mlir][spirv] Update pass docs

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D94174

Added: 


Modified: 
mlir/include/mlir/Conversion/Passes.td

Removed: 




diff  --git a/mlir/include/mlir/Conversion/Passes.td 
b/mlir/include/mlir/Conversion/Passes.td
index 2dc438534a44..6a6ba6bbb371 100644
--- a/mlir/include/mlir/Conversion/Passes.td
+++ b/mlir/include/mlir/Conversion/Passes.td
@@ -144,6 +144,18 @@ def ConvertGpuOpsToROCDLOps : Pass<"convert-gpu-to-rocdl", 
"gpu::GPUModuleOp"> {
 
 def ConvertGPUToSPIRV : Pass<"convert-gpu-to-spirv", "ModuleOp"> {
   let summary = "Convert GPU dialect to SPIR-V dialect";
+  let description = [{
+This pass converts supported GPU device ops to SPIR-V ops. It does not
+handle GPU host ops.
+
+A `gpu.func` op can have parameters to pass in resources. But in SPIR-V
+entry functions cannot take parameters; they use descriptors to access
+resources. By default, parameters to a `gpu.func` op will be converted to
+global variables. These global variables will be assigned sequential 
binding
+numbers following their order in the original `gpu.func` op, starting from
+0, in set 0. One can attach `spv.interface_var_abi` to those parameters
+to control the set and binding if wanted.
+  }];
   let constructor = "mlir::createConvertGPUToSPIRVPass()";
   let dependentDialects = ["spirv::SPIRVDialect"];
 }
@@ -155,6 +167,9 @@ def ConvertGPUToSPIRV : Pass<"convert-gpu-to-spirv", 
"ModuleOp"> {
 def ConvertGpuLaunchFuncToVulkanLaunchFunc
 : Pass<"convert-gpu-launch-to-vulkan-launch", "ModuleOp"> {
   let summary = "Convert gpu.launch_func to vulkanLaunch external call";
+  let description = [{
+This pass is only intended for the mlir-vulkan-runner.
+  }];
   let constructor = "mlir::createConvertGpuLaunchFuncToVulkanLaunchFuncPass()";
   let dependentDialects = ["spirv::SPIRVDialect"];
 }
@@ -163,6 +178,9 @@ def ConvertVulkanLaunchFuncToVulkanCalls
 : Pass<"launch-func-to-vulkan", "ModuleOp"> {
   let summary = "Convert vulkanLaunch external call to Vulkan runtime external 
"
 "calls";
+  let description = [{
+This pass is only intended for the mlir-vulkan-runner.
+  }];
   let constructor = "mlir::createConvertVulkanLaunchFuncToVulkanCallsPass()";
   let dependentDialects = ["LLVM::LLVMDialect"];
 }
@@ -194,7 +212,11 @@ def ConvertLinalgToStandard : 
Pass<"convert-linalg-to-std", "ModuleOp"> {
 
//===--===//
 
 def ConvertLinalgToSPIRV : Pass<"convert-linalg-to-spirv", "ModuleOp"> {
-  let summary = "Convert Linalg ops to SPIR-V ops";
+  let summary = "Convert Linalg dialect to SPIR-V dialect";
+  let description = [{
+This pass converts supported Linalg ops to SPIR-V ops. It's quite
+experimental and are expected to migrate to other proper conversions.
+  }];
   let constructor = "mlir::createLinalgToSPIRVPass()";
   let dependentDialects = ["spirv::SPIRVDialect"];
 }
@@ -312,6 +334,10 @@ def ConvertShapeConstraints: 
Pass<"convert-shape-constraints", "FuncOp"> {
 
 def ConvertSPIRVToLLVM : Pass<"convert-spirv-to-llvm", "ModuleOp"> {
   let summary = "Convert SPIR-V dialect to LLVM dialect";
+  let description = [{
+See https://mlir.llvm.org/docs/SPIRVToLLVMDialectConversion/
+for more details.
+  }];
   let constructor = "mlir::createConvertSPIRVToLLVMPass()";
   let dependentDialects = ["LLVM::LLVMDialect"];
 }
@@ -375,12 +401,17 @@ def ConvertStandardToLLVM : Pass<"convert-std-to-llvm", 
"ModuleOp"> {
 
 def LegalizeStandardForSPIRV : Pass<"legalize-std-for-spirv"> {
   let summary = "Legalize standard ops for SPIR-V lowering";
+  let description = [{
+The pass contains certain intra standard op conversions that are meant for
+lowering to SPIR-V ops, e.g., folding subviews loads/stores to the original
+loads/stores from/to the original memref.
+  }];
   let constructor = "mlir::createLegalizeStdOpsForSPIRVLoweringPass()";
   let dependentDialects = ["spirv::SPIRVDialect"];
 }
 
 def ConvertStandardToSPIRV : Pass<"convert-std-to-spirv", "ModuleOp"> {
-  let summary = "Convert Standard Ops to SPIR-V dialect";
+  let summary = "Convert Standard dialect to SPIR-V dialect";
   let constructor = "mlir::createConvertStandardToSPIRVPass()";
   let dependentDialects = ["spirv::SPIRVDialect"];
 }
@@ -459,8 +490,7 @@ def ConvertVectorToROCDL : Pass<"convert-vector-to-rocdl", 
"ModuleOp"> {
 
//===--===//
 
 def ConvertVectorToSPIRV : Pass<"convert-vector-

[llvm-branch-commits] [llvm] 46975b5 - [Hexagon] Wrap functions only used in asserts in ifndef NDEBUG

[Krzysztof Parzyszek via llvm-branch-commits]

Author: Krzysztof Parzyszek
Date: 2021-01-06T09:40:38-06:00
New Revision: 46975b5b29e2ecbf97eb7be2b124d94f0ce4b45e

URL: 
https://github.com/llvm/llvm-project/commit/46975b5b29e2ecbf97eb7be2b124d94f0ce4b45e
DIFF: 
https://github.com/llvm/llvm-project/commit/46975b5b29e2ecbf97eb7be2b124d94f0ce4b45e.diff

LOG: [Hexagon] Wrap functions only used in asserts in ifndef NDEBUG

Added: 


Modified: 
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp

Removed: 




diff  --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp 
b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 05269d37f812..01fd8a9ef9ce 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -117,8 +117,11 @@ class HexagonVectorCombine {
   const HexagonSubtarget &HST;
 
 private:
+#ifndef NDEBUG
+  // These two functions are only used for assertions at the moment.
   bool isByteVecTy(Type *Ty) const;
-  bool isSectorTy(Type *Ty) const LLVM_ATTRIBUTE_UNUSED;
+  bool isSectorTy(Type *Ty) const;
+#endif
   Value *getElementRange(IRBuilder<> &Builder, Value *Lo, Value *Hi, int Start,
  int Length) const;
 };
@@ -1406,6 +1409,7 @@ auto HexagonVectorCombine::isSafeToMoveBeforeInBB(const 
Instruction &In,
   return true;
 }
 
+#ifndef NDEBUG
 auto HexagonVectorCombine::isByteVecTy(Type *Ty) const -> bool {
   if (auto *VecTy = dyn_cast(Ty))
 return VecTy->getElementType() == getByteTy();
@@ -1420,6 +1424,7 @@ auto HexagonVectorCombine::isSectorTy(Type *Ty) const -> 
bool {
 return Size == static_cast(HST.getVectorLength());
   return Size == 4 || Size == 8;
 }
+#endif
 
 auto HexagonVectorCombine::getElementRange(IRBuilder<> &Builder, Value *Lo,
Value *Hi, int Start,



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[llvm-branch-commits] [llvm] b69fe6a - [X86] Add icmp ne/eq (srl (ctlz x), log2(bw)) test coverage.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T15:50:29Z
New Revision: b69fe6a85db43df27ebb260716d41a3e1b0d7534

URL: 
https://github.com/llvm/llvm-project/commit/b69fe6a85db43df27ebb260716d41a3e1b0d7534
DIFF: 
https://github.com/llvm/llvm-project/commit/b69fe6a85db43df27ebb260716d41a3e1b0d7534.diff

LOG: [X86] Add icmp ne/eq (srl (ctlz x), log2(bw)) test coverage.

Add vector coverage as well (which isn't currently supported).

Added: 
llvm/test/CodeGen/X86/lzcnt-cmp.ll

Modified: 


Removed: 




diff  --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll 
b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
new file mode 100644
index ..435b09dd5d08
--- /dev/null
+++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
@@ -0,0 +1,258 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt | FileCheck %s 
--check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+lzcnt | FileCheck %s 
--check-prefix=X64
+
+define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) {
+; X86-LABEL: lshr_ctlz_cmpeq_one_i64:
+; X86:   # %bb.0:
+; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:sete %al
+; X86-NEXT:retl
+;
+; X64-LABEL: lshr_ctlz_cmpeq_one_i64:
+; X64:   # %bb.0:
+; X64-NEXT:testq %rdi, %rdi
+; X64-NEXT:sete %al
+; X64-NEXT:retq
+  %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 0)
+  %lshr = lshr i64 %ctlz, 6
+  %icmp = icmp eq i64 %lshr, 1
+  ret i1 %icmp
+}
+
+define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) {
+; X86-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
+; X86:   # %bb.0:
+; X86-NEXT:xorl %eax, %eax
+; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:jne .LBB1_2
+; X86-NEXT:  # %bb.1:
+; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:addl $32, %eax
+; X86-NEXT:  .LBB1_2:
+; X86-NEXT:testb $64, %al
+; X86-NEXT:setne %al
+; X86-NEXT:retl
+;
+; X64-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
+; X64:   # %bb.0:
+; X64-NEXT:lzcntq %rdi, %rax
+; X64-NEXT:shrq $6, %rax
+; X64-NEXT:cmpl $1, %eax
+; X64-NEXT:sete %al
+; X64-NEXT:retq
+  %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1)
+  %lshr = lshr i64 %ctlz, 6
+  %icmp = icmp eq i64 %lshr, 1
+  ret i1 %icmp
+}
+
+define i1 @lshr_ctlz_cmpne_zero_i64(i64 %in) {
+; X86-LABEL: lshr_ctlz_cmpne_zero_i64:
+; X86:   # %bb.0:
+; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:sete %al
+; X86-NEXT:retl
+;
+; X64-LABEL: lshr_ctlz_cmpne_zero_i64:
+; X64:   # %bb.0:
+; X64-NEXT:testq %rdi, %rdi
+; X64-NEXT:sete %al
+; X64-NEXT:retq
+  %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 0)
+  %lshr = lshr i64 %ctlz, 6
+  %icmp = icmp ne i64 %lshr, 0
+  ret i1 %icmp
+}
+
+define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) {
+; X86-LABEL: lshr_ctlz_undef_cmpne_zero_i64:
+; X86:   # %bb.0:
+; X86-NEXT:xorl %eax, %eax
+; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:jne .LBB3_2
+; X86-NEXT:  # %bb.1:
+; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:addl $32, %eax
+; X86-NEXT:  .LBB3_2:
+; X86-NEXT:testb $64, %al
+; X86-NEXT:setne %al
+; X86-NEXT:retl
+;
+; X64-LABEL: lshr_ctlz_undef_cmpne_zero_i64:
+; X64:   # %bb.0:
+; X64-NEXT:lzcntq %rdi, %rax
+; X64-NEXT:testb $64, %al
+; X64-NEXT:setne %al
+; X64-NEXT:retq
+  %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1)
+  %lshr = lshr i64 %ctlz, 6
+  %icmp = icmp ne i64 %lshr, 0
+  ret i1 %icmp
+}
+
+define <2 x i64> @lshr_ctlz_cmpeq_zero_v2i64(<2 x i64> %in) {
+; X86-LABEL: lshr_ctlz_cmpeq_zero_v2i64:
+; X86:   # %bb.0:
+; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:xorl %edx, %edx
+; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:movl $0, %ecx
+; X86-NEXT:jne .LBB4_2
+; X86-NEXT:  # %bb.1:
+; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:addl $32, %ecx
+; X86-NEXT:  .LBB4_2:
+; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:jne .LBB4_4
+; X86-NEXT:  # %bb.3:
+; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %edx
+; X86-NEXT:addl $32, %edx
+; X86-NEXT:  .LBB4_4:
+; X86-NEXT:andl $-64, %edx
+; X86-NEXT:cmpl $1, %edx
+; X86-NEXT:sbbl %edx, %edx
+; X86-NEXT:andl $-64, %ecx
+; X86-NEXT:cmpl $1, %ecx
+; X86-NEXT:sbbl %ecx, %ecx
+; X86-NEXT:movl %ecx, 12(%eax)
+; X86-NEXT:movl %ecx, 8(%eax)
+; X86-NEXT:movl %edx, 4(%eax)
+; X86-NEXT:movl %edx, (%eax)
+; X86-NEXT:retl $4
+;
+; X64-LABEL: lshr_ctlz_cmpeq_zero_v2i64:
+; X64:   # %bb.0:
+; X64-NEXT:movdqa %xmm0, %xmm1
+; X64-NEXT:psrlq $1, %xmm1
+; X64-NEXT:por %xmm0, %xmm1
+; X64-NEXT:movdqa %xmm1, %xmm0
+; X64-NEXT:psrlq $2, %xmm0
+; X64-NEXT:por %xmm1, %xmm0
+; X64-NEXT:movdqa %xmm0, %xmm1
+; X64-NEXT:psrlq $4, %xmm1
+; X64-NEXT:por %xmm0, %xmm1
+; X64-NEXT:movdqa %xmm1, %xmm0
+; X64-NEXT:ps

[llvm-branch-commits] [llvm] 500864f - Remove some unused includes. NFCI.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T15:50:29Z
New Revision: 500864f928c272e8ebfd6493cb749083124bfd8b

URL: 
https://github.com/llvm/llvm-project/commit/500864f928c272e8ebfd6493cb749083124bfd8b
DIFF: 
https://github.com/llvm/llvm-project/commit/500864f928c272e8ebfd6493cb749083124bfd8b.diff

LOG: Remove some unused  includes. NFCI.

 (unlike many other c++ headers) is relatively clean, so if the file 
doesn't use std::vector then it shouldn't need the header.

Added: 


Modified: 
llvm/include/llvm/Analysis/InlineAdvisor.h
llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
llvm/include/llvm/ExecutionEngine/JITEventListener.h

Removed: 




diff  --git a/llvm/include/llvm/Analysis/InlineAdvisor.h 
b/llvm/include/llvm/Analysis/InlineAdvisor.h
index 4dbd5786ac7d..f051706dca16 100644
--- a/llvm/include/llvm/Analysis/InlineAdvisor.h
+++ b/llvm/include/llvm/Analysis/InlineAdvisor.h
@@ -9,13 +9,11 @@
 #ifndef LLVM_INLINEADVISOR_H_
 #define LLVM_INLINEADVISOR_H_
 
-#include 
-#include 
-#include 
-
 #include "llvm/Analysis/InlineCost.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/IR/PassManager.h"
+#include 
+#include 
 
 namespace llvm {
 class BasicBlock;

diff  --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h 
b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index b47aaa53eb89..893bc6e013f4 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -57,7 +57,6 @@
 #include 
 #include 
 #include 
-#include 
 
 namespace llvm {
 

diff  --git a/llvm/include/llvm/ExecutionEngine/JITEventListener.h 
b/llvm/include/llvm/ExecutionEngine/JITEventListener.h
index 606b6f7cc128..4eefd993de2b 100644
--- a/llvm/include/llvm/ExecutionEngine/JITEventListener.h
+++ b/llvm/include/llvm/ExecutionEngine/JITEventListener.h
@@ -20,7 +20,6 @@
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Support/CBindingWrapping.h"
 #include 
-#include 
 
 namespace llvm {
 



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[llvm-branch-commits] [llvm] 350247a - [AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup))

[Nicholas Guy via llvm-branch-commits]

Author: Nicholas Guy
Date: 2021-01-06T16:02:16Z
New Revision: 350247a93c07906300b79955ff882004a92ae368

URL: 
https://github.com/llvm/llvm-project/commit/350247a93c07906300b79955ff882004a92ae368
DIFF: 
https://github.com/llvm/llvm-project/commit/350247a93c07906300b79955ff882004a92ae368.diff

LOG: [AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup))

Performing this rearrangement allows for existing patterns
to match cases where the vector may be built after an extend,
instead of before.

Differential Revision: https://reviews.llvm.org/D91255

Added: 
llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

Modified: 
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 41dc285a368d..40435c12ca3b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11705,9 +11705,152 @@ static bool IsSVECntIntrinsic(SDValue S) {
   return false;
 }
 
+/// Calculates what the pre-extend type is, based on the extension
+/// operation node provided by \p Extend.
+///
+/// In the case that \p Extend is a SIGN_EXTEND or a ZERO_EXTEND, the
+/// pre-extend type is pulled directly from the operand, while other extend
+/// operations need a bit more inspection to get this information.
+///
+/// \param Extend The SDNode from the DAG that represents the extend operation
+/// \param DAG The SelectionDAG hosting the \p Extend node
+///
+/// \returns The type representing the \p Extend source type, or \p MVT::Other
+/// if no valid type can be determined
+static EVT calculatePreExtendType(SDValue Extend, SelectionDAG &DAG) {
+  switch (Extend.getOpcode()) {
+  case ISD::SIGN_EXTEND:
+  case ISD::ZERO_EXTEND:
+return Extend.getOperand(0).getValueType();
+  case ISD::AssertSext:
+  case ISD::AssertZext:
+  case ISD::SIGN_EXTEND_INREG: {
+VTSDNode *TypeNode = dyn_cast(Extend.getOperand(1));
+if (!TypeNode)
+  return MVT::Other;
+return TypeNode->getVT();
+  }
+  case ISD::AND: {
+ConstantSDNode *Constant =
+dyn_cast(Extend.getOperand(1).getNode());
+if (!Constant)
+  return MVT::Other;
+
+uint32_t Mask = Constant->getZExtValue();
+
+if (Mask == UCHAR_MAX)
+  return MVT::i8;
+else if (Mask == USHRT_MAX)
+  return MVT::i16;
+else if (Mask == UINT_MAX)
+  return MVT::i32;
+
+return MVT::Other;
+  }
+  default:
+return MVT::Other;
+  }
+
+  llvm_unreachable("Code path unhandled in calculatePreExtendType!");
+}
+
+/// Combines a dup(sext/zext) node pattern into sext/zext(dup)
+/// making use of the vector SExt/ZExt rather than the scalar SExt/ZExt
+static SDValue performCommonVectorExtendCombine(SDValue VectorShuffle,
+SelectionDAG &DAG) {
+
+  ShuffleVectorSDNode *ShuffleNode =
+  dyn_cast(VectorShuffle.getNode());
+  if (!ShuffleNode)
+return SDValue();
+
+  // Ensuring the mask is zero before continuing
+  if (!ShuffleNode->isSplat() || ShuffleNode->getSplatIndex() != 0)
+return SDValue();
+
+  SDValue InsertVectorElt = VectorShuffle.getOperand(0);
+
+  if (InsertVectorElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
+return SDValue();
+
+  SDValue InsertLane = InsertVectorElt.getOperand(2);
+  ConstantSDNode *Constant = dyn_cast(InsertLane.getNode());
+  // Ensures the insert is inserting into lane 0
+  if (!Constant || Constant->getZExtValue() != 0)
+return SDValue();
+
+  SDValue Extend = InsertVectorElt.getOperand(1);
+  unsigned ExtendOpcode = Extend.getOpcode();
+
+  bool IsSExt = ExtendOpcode == ISD::SIGN_EXTEND ||
+ExtendOpcode == ISD::SIGN_EXTEND_INREG ||
+ExtendOpcode == ISD::AssertSext;
+  if (!IsSExt && ExtendOpcode != ISD::ZERO_EXTEND &&
+  ExtendOpcode != ISD::AssertZext && ExtendOpcode != ISD::AND)
+return SDValue();
+
+  EVT TargetType = VectorShuffle.getValueType();
+  EVT PreExtendType = calculatePreExtendType(Extend, DAG);
+
+  if ((TargetType != MVT::v8i16 && TargetType != MVT::v4i32 &&
+   TargetType != MVT::v2i64) ||
+  (PreExtendType == MVT::Other))
+return SDValue();
+
+  EVT PreExtendVT = TargetType.changeVectorElementType(PreExtendType);
+
+  if (PreExtendVT.getVectorElementCount() != 
TargetType.getVectorElementCount())
+return SDValue();
+
+  if (TargetType.getScalarSizeInBits() != PreExtendVT.getScalarSizeInBits() * 
2)
+return SDValue();
+
+  SDLoc DL(VectorShuffle);
+
+  SDValue InsertVectorNode = DAG.getNode(
+  InsertVectorElt.getOpcode(), DL, PreExtendVT, DAG.getUNDEF(PreExtendVT),
+  Extend.getOperand(0), DAG.getConstant(0, DL, MVT::i64));
+
+  std::vector ShuffleMask(TargetType.getVectorElementCount().getValue());
+
+  SDValue VectorShuffleNode =
+  DAG.getVector

[llvm-branch-commits] [llvm] 1307e3f - [TargetLowering] Add icmp ne/eq (srl (ctlz x), log2(bw)) vector support.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T16:13:51Z
New Revision: 1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e

URL: 
https://github.com/llvm/llvm-project/commit/1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e
DIFF: 
https://github.com/llvm/llvm-project/commit/1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e.diff

LOG: [TargetLowering] Add icmp ne/eq (srl (ctlz x), log2(bw)) vector support.

Added: 


Modified: 
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/X86/lzcnt-cmp.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp 
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index d895a53e5a83..f5abb2c513fb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3486,35 +3486,36 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue 
N0, SDValue N1,
 // Optimize some CTPOP cases.
 if (SDValue V = simplifySetCCWithCTPOP(*this, VT, N0, C1, Cond, dl, DAG))
   return V;
-  }
-
-  // FIXME: Support vectors.
-  if (auto *N1C = dyn_cast(N1.getNode())) {
-const APInt &C1 = N1C->getAPIntValue();
 
 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
 // equality comparison, then we're just comparing whether X itself is
 // zero.
 if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
-N0.getOperand(1).getOpcode() == ISD::Constant) {
-  const APInt &ShAmt = N0.getConstantOperandAPInt(1);
-  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
-  ShAmt == Log2_32(N0.getValueSizeInBits())) {
-if ((C1 == 0) == (Cond == ISD::SETEQ)) {
-  // (srl (ctlz x), 5) == 0  -> X != 0
-  // (srl (ctlz x), 5) != 1  -> X != 0
-  Cond = ISD::SETNE;
-} else {
-  // (srl (ctlz x), 5) != 0  -> X == 0
-  // (srl (ctlz x), 5) == 1  -> X == 0
-  Cond = ISD::SETEQ;
+isPowerOf2_32(N0.getScalarValueSizeInBits())) {
+  if (ConstantSDNode *ShAmt = isConstOrConstSplat(N0.getOperand(1))) {
+if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+ShAmt->getAPIntValue() == Log2_32(N0.getScalarValueSizeInBits())) {
+  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
+// (srl (ctlz x), 5) == 0  -> X != 0
+// (srl (ctlz x), 5) != 1  -> X != 0
+Cond = ISD::SETNE;
+  } else {
+// (srl (ctlz x), 5) != 0  -> X == 0
+// (srl (ctlz x), 5) == 1  -> X == 0
+Cond = ISD::SETEQ;
+  }
+  SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
+  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), Zero,
+  Cond);
 }
-SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
-return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
-Zero, Cond);
   }
 }
+  }
+
+  // FIXME: Support vectors.
+  if (auto *N1C = dyn_cast(N1.getNode())) {
+const APInt &C1 = N1C->getAPIntValue();
 
 // (zext x) == C --> x == (trunc C)
 // (sext x) == C --> x == (trunc C)

diff  --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll 
b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
index 435b09dd5d08..3823524f552a 100644
--- a/llvm/test/CodeGen/X86/lzcnt-cmp.ll
+++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
@@ -96,75 +96,36 @@ define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) {
 define <2 x i64> @lshr_ctlz_cmpeq_zero_v2i64(<2 x i64> %in) {
 ; X86-LABEL: lshr_ctlz_cmpeq_zero_v2i64:
 ; X86:   # %bb.0:
+; X86-NEXT:pushl %esi
+; X86-NEXT:.cfi_def_cfa_offset 8
+; X86-NEXT:.cfi_offset %esi, -8
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT:xorl %ecx, %ecx
+; X86-NEXT:orl {{[0-9]+}}(%esp), %edx
+; X86-NEXT:setne %cl
+; X86-NEXT:negl %ecx
 ; X86-NEXT:xorl %edx, %edx
-; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:movl $0, %ecx
-; X86-NEXT:jne .LBB4_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:addl $32, %ecx
-; X86-NEXT:  .LBB4_2:
-; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:jne .LBB4_4
-; X86-NEXT:  # %bb.3:
-; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:addl $32, %edx
-; X86-NEXT:  .LBB4_4:
-; X86-NEXT:andl $-64, %edx
-; X86-NEXT:cmpl $1, %edx
-; X86-NEXT:sbbl %edx, %edx
-; X86-NEXT:andl $-64, %ecx
-; X86-NEXT:cmpl $1, %ecx
-; X86-NEXT:sbbl %ecx, %ecx
-; X86-NEXT:movl %ecx, 12(%eax)
-; X86-NEXT:movl %ecx, 8(%eax)
-; X86-NEXT:movl %edx, 4(%eax)
-; X86-NEXT:movl %edx, (%eax)
+; X86-NEXT:orl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:setne %dl
+; X86-NEXT:negl %edx
+; X86-NEXT:movl %edx, 12(%eax)
+; X86-NEXT:movl %edx, 8(%eax)
+; X86

[llvm-branch-commits] [clang] 7809fa2 - [flang][driver] Add support for `-D`, `-U`

[Andrzej Warzynski via llvm-branch-commits]

Author: Faris Rehman
Date: 2021-01-06T16:17:13Z
New Revision: 7809fa2040fd40b4a4b56696c7fbcd0f0fa9

URL: 
https://github.com/llvm/llvm-project/commit/7809fa2040fd40b4a4b56696c7fbcd0f0fa9
DIFF: 
https://github.com/llvm/llvm-project/commit/7809fa2040fd40b4a4b56696c7fbcd0f0fa9.diff

LOG: [flang][driver] Add support for `-D`, `-U`

Add support for options -D and -U in the new Flang driver.

Summary of changes:
  - Create PreprocessorOptions, to be used by the driver then translated
into Fortran::parser::Options
  - Create CompilerInvocation::setFortranOpts to pass preprocessor
options into the parser options
  - Add a dedicated method, Flang::AddPreprocessingOptions, to extract
preprocessing options from the driver arguments into the preprocessor
command arguments

Macros specified like -DName will default to definition 1.

When defining macros, the new driver will drop anything after an
end-of-line character. This is consistent with gfortran and clang, but
different to what currently f18 does. However, flang (which is a bash
wrapper for f18), also drops everything after an end-of-line character.
So gfortran-like behaviour felt like the natural choice. Test is added
to demonstrate this behaviour.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D93401

Added: 
flang/include/flang/Frontend/PreprocessorOptions.h
flang/test/Flang-Driver/macro_def_undef.f90
flang/test/Flang-Driver/macro_multiline.f90

Modified: 
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Flang.cpp
clang/lib/Driver/ToolChains/Flang.h
flang/include/flang/Frontend/CompilerInstance.h
flang/include/flang/Frontend/CompilerInvocation.h
flang/lib/Frontend/CompilerInstance.cpp
flang/lib/Frontend/CompilerInvocation.cpp
flang/test/Flang-Driver/driver-help-hidden.f90
flang/test/Flang-Driver/driver-help.f90

Removed: 




diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 3c2a9f307c65..428c14a7d9bb 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -631,7 +631,7 @@ def C : Flag<["-"], "C">, Flags<[CC1Option]>, 
Group,
 HelpText<"Include comments in preprocessed output">,
 MarshallingInfoFlag<"PreprocessorOutputOpts.ShowComments">;
 def D : JoinedOrSeparate<["-"], "D">, Group,
-Flags<[CC1Option]>, MetaVarName<"=">,
+Flags<[CC1Option, FlangOption, FC1Option]>, MetaVarName<"=">,
 HelpText<"Define  to  (or 1 if  omitted)">;
 def E : Flag<["-"], "E">, Flags<[NoXarchOption,CC1Option, FlangOption, 
FC1Option]>, Group,
 HelpText<"Only run the preprocessor">;
@@ -730,7 +730,7 @@ def Ttext : JoinedOrSeparate<["-"], "Ttext">, 
Group,
 def T : JoinedOrSeparate<["-"], "T">, Group,
   MetaVarName<"

[llvm-branch-commits] [llvm] 136f498 - AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests

[Matt Arsenault via llvm-branch-commits]

Author: Matt Arsenault
Date: 2021-01-06T11:37:00-05:00
New Revision: 136f49891953ce232be2f4a8bc98e83bb2cd6462

URL: 
https://github.com/llvm/llvm-project/commit/136f49891953ce232be2f4a8bc98e83bb2cd6462
DIFF: 
https://github.com/llvm/llvm-project/commit/136f49891953ce232be2f4a8bc98e83bb2cd6462.diff

LOG: AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests

GlobalISel will probably not support the legacy buffer intrinsics, so
don't fail when the default is switched.

Added: 


Modified: 
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.ll

Removed: 




diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
index aadd9a448a1b..d5bdb62354ca 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | 
FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s 
| FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX81 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s 
| FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX9 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=tonga 
-verify-machineinstrs < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,UNPACKED %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 
-verify-machineinstrs < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,PACKED,GFX81 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 
-verify-machineinstrs < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,PACKED,GFX9 %s
 
 ; GCN-LABEL: {{^}}buffer_store_format_d16_x:
 ; GCN: s_load_dword s[[LO:[0-9]+]]

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
index 78c5281ed73e..1a13e0bdd802 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
@@ -1,5 +1,5 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck 
-check-prefix=VERDE %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+;RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=verde -verify-machineinstrs 
| FileCheck -check-prefix=VERDE %s
+;RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs 
| FileCheck %s
 
 ;CHECK-LABEL: {{^}}buffer_store:
 ;CHECK-NOT: s_waitcnt

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
index 2839f92d2aae..ef6b1fb883ec 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs 
-show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN 
-check-prefix=UNPACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck 
-enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck 
-enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
+; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs 
-show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN 
-check-prefix=UNPACKED %s
+; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=gfx810 
-verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN 
-check-prefix=PACKED %s
+; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=gfx900 
-verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN 
-check-prefix=PACKED %s
 
 ; GCN-LABEL: {{^}}tbuffer_load_d16_x:
 ; GCN: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 
format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
index b04f3c09729a..07a7a69a96c0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
@@ -1,5 +1,5 @@
-;RUN: llc < %s -march=amdgcn -mcpu=gfx600 -

[llvm-branch-commits] [llvm] dfd3384 - [InstCombine] Update valueCoversEntireFragment to use TypeSize

[Peter Waller via llvm-branch-commits]

Author: Francesco Petrogalli
Date: 2021-01-06T17:14:59Z
New Revision: dfd3384feeca334c59b5a32254e425491acd716a

URL: 
https://github.com/llvm/llvm-project/commit/dfd3384feeca334c59b5a32254e425491acd716a
DIFF: 
https://github.com/llvm/llvm-project/commit/dfd3384feeca334c59b5a32254e425491acd716a.diff

LOG: [InstCombine] Update valueCoversEntireFragment to use TypeSize

* Update valueCoversEntireFragment to use TypeSize.
* Add a regression test.
* Assertions have been added to protect untested codepaths.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D91806

Added: 
llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll

Modified: 
llvm/lib/Transforms/Utils/Local.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/Local.cpp 
b/llvm/lib/Transforms/Utils/Local.cpp
index f2bc8a801a75..e3bdfbae9287 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1340,16 +1340,22 @@ static bool PhiHasDebugValue(DILocalVariable *DIVar,
 /// least n bits.
 static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
   const DataLayout &DL = DII->getModule()->getDataLayout();
-  uint64_t ValueSize = DL.getTypeAllocSizeInBits(ValTy);
-  if (auto FragmentSize = DII->getFragmentSizeInBits())
-return ValueSize >= *FragmentSize;
+  TypeSize ValueSize = DL.getTypeAllocSizeInBits(ValTy);
+  if (Optional FragmentSize = DII->getFragmentSizeInBits()) {
+assert(!ValueSize.isScalable() &&
+   "Fragments don't work on scalable types.");
+return ValueSize.getFixedSize() >= *FragmentSize;
+  }
   // We can't always calculate the size of the DI variable (e.g. if it is a
   // VLA). Try to use the size of the alloca that the dbg intrinsic describes
   // intead.
   if (DII->isAddressOfVariable())
 if (auto *AI = dyn_cast_or_null(DII->getVariableLocation()))
-  if (auto FragmentSize = AI->getAllocationSizeInBits(DL))
-return ValueSize >= *FragmentSize;
+  if (Optional FragmentSize = AI->getAllocationSizeInBits(DL)) {
+assert(ValueSize.isScalable() == FragmentSize->isScalable() &&
+   "Both sizes should agree on the scalable flag.");
+return TypeSize::isKnownGE(ValueSize, *FragmentSize);
+  }
   // Could not determine size of variable. Conservatively return false.
   return false;
 }

diff  --git a/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll 
b/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
new file mode 100644
index ..8b96fccdd9e9
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
@@ -0,0 +1,36 @@
+; RUN: opt -instcombine -S < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; This test is defending against a TypeSize message raised in the method
+; `valueCoversEntireFragment` in Local.cpp because of an implicit cast from
+; `TypeSize` to `uint64_t`. This particular TypeSize message only occurred when
+; debug info was available.
+
+; If this check fails please read
+; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on
+; how to resolve it.
+; This test must not produce any warnings. Prior to this test being introduced,
+; it produced a warning containing the text "TypeSize is not scalable".
+; WARN-NOT: warning:
+
+; CHECK-LABEL: @debug_local_scalable(
+define  @debug_local_scalable( 
%tostore) {
+  %vx = alloca , align 16
+  call void @llvm.dbg.declare(metadata * %vx, metadata 
!3, metadata !DIExpression()), !dbg !5
+  store  %tostore, * %vx, align 16
+  %ret = call  @f(* %vx)
+  ret  %ret
+}
+
+declare  @f(*)
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1)
+!1 = !DIFile(filename: "/tmp/test.c", directory: "/tmp/")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !DILocalVariable(scope: !4)
+!4 = distinct !DISubprogram(unit: !0)
+!5 = !DILocation(scope: !4)



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[llvm-branch-commits] [llvm] 3e357ec - [llvm][NFC] Disallow all warnings in TypeSize tests

[Peter Waller via llvm-branch-commits]

Author: Peter Waller
Date: 2021-01-06T17:17:07Z
New Revision: 3e357ecd44a610ab39c33c85a15cf6437891655b

URL: 
https://github.com/llvm/llvm-project/commit/3e357ecd44a610ab39c33c85a15cf6437891655b
DIFF: 
https://github.com/llvm/llvm-project/commit/3e357ecd44a610ab39c33c85a15cf6437891655b.diff

LOG: [llvm][NFC] Disallow all warnings in TypeSize tests

This is a follow-up to a request from a reviewer [0]. The text may change in
the future and these tests should not produce any warning output.

[0] https://reviews.llvm.org/D91806#inline-879243

Reviewed By: sdesmalen, david-arm

Differential Revision: https://reviews.llvm.org/D94161

Added: 


Modified: 
llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll

llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll

llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
llvm/test/CodeGen/AArch64/sve-redundant-store.ll

llvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-scalable-load-in-loop.ll

Removed: 




diff  --git a/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll 
b/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
index 4bc6889e3fdd..019aa0148365 100644
--- a/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
@@ -6,7 +6,7 @@
 ; warning when performing cost analysis.
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions 
on how to resolve it.
-; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+; WARN-NOT: warning:
 
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %retval = 
getelementptr
 define * @gep_scalable_vector(* %ptr) {

diff  --git 
a/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
 
b/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
index 7e4e5bacd12b..050b09925b46 100644
--- 
a/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
+++ 
b/llvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
@@ -6,7 +6,7 @@
 ; warning in the llvm::getGEPInductionOperand function.
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions 
on how to resolve it.
-; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+; WARN-NOT: warning:
 
 define void @get_gep_induction_operand_typesize_warning(i64 %n, * %a) {
 entry:

diff  --git 
a/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
 
b/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
index d1a980f51c37..e8d25883a6cc 100644
--- 
a/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
+++ 
b/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll
@@ -7,7 +7,7 @@
 ; this function was previously unaware of scalable types.
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions 
on how to resolve it.
-; CHECK-NOT: warning: {{.*}}TypeSize is not scalable
+; CHECK-NOT: warning:
 
 define void @runtime_pointer_checking_insert_typesize(* %a,
   * %b) {

diff  --git 
a/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll 
b/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
index fd5b85a57de1..ba8d8cb0a0d2 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
@@ -5,7 +5,7 @@
 ; node linked to a scalable store.
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions 
on how to resolve it.
-; CHECK-NOT: warning: {{.*}}TypeSize is not scalable
+; CHECK-NOT: warning:
 
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)

diff  --git a/llvm/test/CodeGen/AArch64/sve-redundant-store.ll 
b/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
index 65fd1e22de02..0673272c19be 100644
--- a/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
+++ b/llvm/test/CodeGen/AArch64/sve-redundant-store.ll
@@ -3,7 +3,7 @@
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions 
on how to resolve it.
-; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+; WARN-NOT: warning:
 
 ; #include 
 ; #include 

diff  --git 
a/llvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
 
b/llvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
index c20128d5fe02..68e840bfe251 100644
--- 
a/llvm/test/Trans

[llvm-branch-commits] [llvm] ab3a3f5 - AMDGPU/GlobalISel: Update fdiv lowering for denormal/ulp interaction

[Matt Arsenault via llvm-branch-commits]

Author: Matt Arsenault
Date: 2021-01-06T12:32:01-05:00
New Revision: ab3a3f543b18d36cec98faa9ca2a68cc9a6ecc65

URL: 
https://github.com/llvm/llvm-project/commit/ab3a3f543b18d36cec98faa9ca2a68cc9a6ecc65
DIFF: 
https://github.com/llvm/llvm-project/commit/ab3a3f543b18d36cec98faa9ca2a68cc9a6ecc65.diff

LOG: AMDGPU/GlobalISel: Update fdiv lowering for denormal/ulp interaction

Change the GlobalISel fast fdiv handling to match the changes in
2531535984ad989ce88aeee23cb92a827da6686e and
884acbb9e167d5668e43581630239d688edec8ad

Added: 


Modified: 
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

Removed: 




diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 8c733a2afa03..a8e6f27e032b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3053,22 +3053,14 @@ bool 
AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(MachineInstr &MI,
   Register Res = MI.getOperand(0).getReg();
   Register LHS = MI.getOperand(1).getReg();
   Register RHS = MI.getOperand(2).getReg();
-
   uint16_t Flags = MI.getFlags();
-
   LLT ResTy = MRI.getType(Res);
-  LLT S32 = LLT::scalar(32);
-  LLT S64 = LLT::scalar(64);
 
   const MachineFunction &MF = B.getMF();
-  bool Unsafe =
-MF.getTarget().Options.UnsafeFPMath || MI.getFlag(MachineInstr::FmArcp);
+  bool AllowInaccurateRcp = MF.getTarget().Options.UnsafeFPMath ||
+MI.getFlag(MachineInstr::FmAfn);
 
-  if (!MF.getTarget().Options.UnsafeFPMath && ResTy == S64)
-return false;
-
-  if (!Unsafe && ResTy == S32 &&
-  MF.getInfo()->getMode().allFP32Denormals())
+  if (!AllowInaccurateRcp)
 return false;
 
   if (auto CLHS = getConstantFPVRegVal(LHS, MRI)) {
@@ -3095,17 +3087,13 @@ bool 
AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(MachineInstr &MI,
   }
 
   // x / y -> x * (1.0 / y)
-  if (Unsafe) {
-auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy}, false)
-  .addUse(RHS)
-  .setMIFlags(Flags);
-B.buildFMul(Res, LHS, RCP, Flags);
-
-MI.eraseFromParent();
-return true;
-  }
+  auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy}, false)
+.addUse(RHS)
+.setMIFlags(Flags);
+  B.buildFMul(Res, LHS, RCP, Flags);
 
-  return false;
+  MI.eraseFromParent();
+  return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeFDIV16(MachineInstr &MI,

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 7775789bd0d2..c7b9b4f60bc6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -66,7 +66,28 @@ define half @v_fdiv_f16(half %a, half %b) {
 }
 
 define half @v_fdiv_f16_afn(half %a, half %b) {
-; GFX6-IEEE-LABEL: v_fdiv_f16_afn:
+; GFX6-LABEL: v_fdiv_f16_afn:
+; GFX6:   ; %bb.0:
+; GFX6-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:v_cvt_f32_f16_e32 v1, v1
+; GFX6-NEXT:v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT:v_rcp_f32_e32 v1, v1
+; GFX6-NEXT:v_mul_f32_e32 v0, v0, v1
+; GFX6-NEXT:v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX89-LABEL: v_fdiv_f16_afn:
+; GFX89:   ; %bb.0:
+; GFX89-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT:v_rcp_f16_e32 v1, v1
+; GFX89-NEXT:v_mul_f16_e32 v0, v0, v1
+; GFX89-NEXT:s_setpc_b64 s[30:31]
+  %fdiv = fdiv afn half %a, %b
+  ret half %fdiv
+}
+
+define half @v_fdiv_f16_ulp25(half %a, half %b) {
+; GFX6-IEEE-LABEL: v_fdiv_f16_ulp25:
 ; GFX6-IEEE:   ; %bb.0:
 ; GFX6-IEEE-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-IEEE-NEXT:v_cvt_f32_f16_e32 v0, v0
@@ -85,7 +106,7 @@ define half @v_fdiv_f16_afn(half %a, half %b) {
 ; GFX6-IEEE-NEXT:v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:s_setpc_b64 s[30:31]
 ;
-; GFX6-FLUSH-LABEL: v_fdiv_f16_afn:
+; GFX6-FLUSH-LABEL: v_fdiv_f16_ulp25:
 ; GFX6-FLUSH:   ; %bb.0:
 ; GFX6-FLUSH-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-FLUSH-NEXT:v_cvt_f32_f16_e32 v0, v0
@@ -107,25 +128,29 @@ define half @v_fdiv_f16_afn(half %a, half %b) {
 ; GFX6-FLUSH-NEXT:v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:s_setpc_b64 s[30:31]
 ;
-; GFX89-LABEL: v_fdiv_f16_afn:
+; GFX89-LABEL: v_fdiv_f16_ulp25:
 ; GFX89:   ; %bb.0:
 ; GFX89-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT:v_rcp_f16_e32 v1, v1
-; GFX89-NEXT:v_mul_f16_e32 v0, v0, v1
+; GFX89-NEXT:v_cvt_f32_f16_e32 v2, v1
+; GFX89-NEXT:v_cvt_f32_f16_e32 v3, v0
+; GFX89-NEXT:v_rcp_f32_e32 v2, v2
+; GFX89-NEXT:v_mul_f32_e32 v2, v3, v2
+; GFX89-NEXT:v_cvt_f16_f32_e32 v2, v2
+; GFX89-NEXT:v_di

[llvm-branch-commits] [llvm] b470630 - [NFC] Removed unused prefixes from CodeGen/AMDGPU

[Mircea Trofin via llvm-branch-commits]

Author: Mircea Trofin
Date: 2021-01-06T09:34:11-08:00
New Revision: b47063091304410e77cf2e03913d9f093b3ef60d

URL: 
https://github.com/llvm/llvm-project/commit/b47063091304410e77cf2e03913d9f093b3ef60d
DIFF: 
https://github.com/llvm/llvm-project/commit/b47063091304410e77cf2e03913d9f093b3ef60d.diff

LOG: [NFC] Removed unused prefixes from CodeGen/AMDGPU

All the 'l'-starting tests.

Differential Revision: https://reviews.llvm.org/D94151

Added: 


Modified: 
llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
llvm/test/CodeGen/AMDGPU/lds-alignment.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.log.ll
llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.log10.ll
llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.round.ll
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
llvm/test/CodeGen/AMDGPU/load-global-f32.ll
llvm/test/CodeGen/AMDGPU/load-global-f64.ll
llvm/test/CodeGen/AMDGPU/load-global-i16.ll
llvm/test/CodeGen/AMDGPU/load-global-i64.ll
llvm/test/CodeGen/AMDGPU/load-lo16.ll
llvm/test/CodeGen/AMDGPU/load-local-f64.ll
llvm/test/CodeGen/AMDGPU/load-local-i32.ll
llvm/test/CodeGen/AMDGPU/load-local.128.ll
llvm/test/CodeGen/AMDGPU/load-local.96.ll
llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
llvm/test/CodeGen/AMDGPU/local-atomics64.ll
llvm/test/CodeGen/AMDGPU/local-memory.ll
llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

Removed: 




diff  --git a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll 
b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
index c9e6147302ea..7a784611df8f 100644
--- a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
@@ -1,9 +1,9 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck 
-check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
-; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck 
-check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck 
-check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=

[llvm-branch-commits] [mlir] 2b638ed - [mlir] NFC: fix trivial typos

[Kazuaki Ishizaki via llvm-branch-commits]

Author: Kazuaki Ishizaki
Date: 2021-01-07T02:36:02+09:00
New Revision: 2b638ed5a127c8e1820d68fcc91333fb9c553904

URL: 
https://github.com/llvm/llvm-project/commit/2b638ed5a127c8e1820d68fcc91333fb9c553904
DIFF: 
https://github.com/llvm/llvm-project/commit/2b638ed5a127c8e1820d68fcc91333fb9c553904.diff

LOG: [mlir] NFC: fix trivial typos
fix typos under docs, test, and tools directories

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94158

Added: 


Modified: 
mlir/docs/CAPI.md
mlir/docs/ConversionToLLVMDialect.md
mlir/docs/Dialects/LLVM.md
mlir/docs/Dialects/TOSA.md
mlir/docs/PassManagement.md
mlir/test/Dialect/Async/async-ref-counting-optimization.mlir
mlir/test/Transforms/buffer-deallocation.mlir
mlir/test/Transforms/normalize-memrefs-ops.mlir
mlir/test/Transforms/promote-buffers-to-stack.mlir
mlir/test/lib/Dialect/Test/TestPatterns.cpp
mlir/test/lib/Transforms/TestSparsification.cpp
mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
mlir/tools/mlir-tblgen/TypeDefGen.cpp

Removed: 




diff  --git a/mlir/docs/CAPI.md b/mlir/docs/CAPI.md
index a292c1fc1833..4feb1faf1b8e 100644
--- a/mlir/docs/CAPI.md
+++ b/mlir/docs/CAPI.md
@@ -107,7 +107,7 @@ these are represented as instances of `MlirStringRef` 
structure that contains a
 pointer to the first character of the string fragment (`str`) and the fragment
 length (`length`). Note that the fragment is _not necessarily_ null-terminated,
 the `length` field must be used to identify the last character. `MlirStringRef`
-is a non-owning pointer, the caller is in charge of perfoming the copy or
+is a non-owning pointer, the caller is in charge of performing the copy or
 ensuring that the pointee outlives all uses of `MlirStringRef`.
 
 ### Printing

diff  --git a/mlir/docs/ConversionToLLVMDialect.md 
b/mlir/docs/ConversionToLLVMDialect.md
index 2b5f98b37686..55b62ff70376 100644
--- a/mlir/docs/ConversionToLLVMDialect.md
+++ b/mlir/docs/ConversionToLLVMDialect.md
@@ -126,7 +126,7 @@ memref<1x? x vector<4xf32>> -> !llvm.struct<(ptr>,
 
 Ranked memrefs with static shape and default layout can be converted into an
 LLVM dialect pointer to their element type. Only the default alignment is
-supported in such cases, e.g. the `alloc` operation cannot have an alignemnt
+supported in such cases, e.g. the `alloc` operation cannot have an alignment
 attribute.
 
 Examples:
@@ -233,11 +233,11 @@ Examples:
 
 When used as function arguments, both ranked and unranked memrefs are converted
 into a list of arguments that represents each _scalar_ component of their
-descriptor. This is intended for some comaptibility with C ABI, in which
+descriptor. This is intended for some compatibility with C ABI, in which
 structure types would need to be passed by-pointer leading to the need for
 allocations and related issues, as well as for aliasing annotations, which are
 currently attached to pointer in function arguments. Having scalar components
-means that each size and stride is passed as an invidivual value.
+means that each size and stride is passed as an individual value.
 
 When used as function results, memrefs are converted as usual, i.e. each memref
 is converted to a descriptor struct (default convention) or to a pointer (bare

diff  --git a/mlir/docs/Dialects/LLVM.md b/mlir/docs/Dialects/LLVM.md
index 3b9150f0e69d..0f5b69104775 100644
--- a/mlir/docs/Dialects/LLVM.md
+++ b/mlir/docs/Dialects/LLVM.md
@@ -385,7 +385,7 @@ structure `A` is represented as `!llvm.struct<"A", 
(ptr<"B", (ptr<"A">)>,
 ptr<"B", (ptr<"A">))>`. Note that the structure `B` is "unrolled" for both
 elements. _A structure with the same name but 
diff erent body is a syntax error._
 **The user must ensure structure name uniqueness across all modules processed 
in
-a given MLIR context.** Stucture names are arbitrary string literals and may
+a given MLIR context.** Structure names are arbitrary string literals and may
 include, e.g., spaces and keywords.
 
 Identified structs may be _opaque_. In this case, the body is unknown but the

diff  --git a/mlir/docs/Dialects/TOSA.md b/mlir/docs/Dialects/TOSA.md
index e0d9eaf32818..cd95f4da69cd 100644
--- a/mlir/docs/Dialects/TOSA.md
+++ b/mlir/docs/Dialects/TOSA.md
@@ -17,14 +17,14 @@ that attempt to manage both sets of requirements.
 ## TOSA and Tensor Level Expressiveness
 
 TOSA endeavors to provide an operator set that tries to fulfil the following
-expressivenes goals at the *tensor level of abstraction* :
+expressiveness goals at the *tensor level of abstraction* :
 
 ### Complete
 
 This is driven by the top-down perspective, needing to express as much of
 multiple high level frameworks fully in TOSA, as possible. This was originally
 done from an operator frequency analysis done upon dozens of high level
-networks in 
diff erent frameworks, to select

[llvm-branch-commits] [mlir] bd166c8 - Nit: fix spacing

[Sanjoy Das via llvm-branch-commits]

Author: Sanjoy Das
Date: 2021-01-06T09:40:50-08:00
New Revision: bd166c813c55b0e1703d17d87bf71a9e3966a25a

URL: 
https://github.com/llvm/llvm-project/commit/bd166c813c55b0e1703d17d87bf71a9e3966a25a
DIFF: 
https://github.com/llvm/llvm-project/commit/bd166c813c55b0e1703d17d87bf71a9e3966a25a.diff

LOG: Nit: fix spacing

Differential Revision: https://reviews.llvm.org/D93996

Added: 


Modified: 
mlir/test/Dialect/GPU/async-region.mlir

Removed: 




diff  --git a/mlir/test/Dialect/GPU/async-region.mlir 
b/mlir/test/Dialect/GPU/async-region.mlir
index 216ccceda1f0..84a0356975b0 100644
--- a/mlir/test/Dialect/GPU/async-region.mlir
+++ b/mlir/test/Dialect/GPU/async-region.mlir
@@ -103,7 +103,7 @@ module attributes {gpu.container_module} {
 return
   }
 
- // CHECK-LABEL:func @async_execute_with_result(%{{.*}}: index)
+  // CHECK-LABEL:func @async_execute_with_result(%{{.*}}: index)
   func @async_execute_with_result(%sz : index) -> index {
 // CHECK: %[[a0:.*]], %[[f0:.*]]:2 = async.execute
 // CHECK-SAME: -> (!async.value, !async.value)



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[llvm-branch-commits] [mlir] 6173d12 - Remove allow-unregistered-dialect from some tests that don't need it

[Sanjoy Das via llvm-branch-commits]

Author: Sanjoy Das
Date: 2021-01-06T09:40:50-08:00
New Revision: 6173d1277be04739bc5d977546309f7c765156c8

URL: 
https://github.com/llvm/llvm-project/commit/6173d1277be04739bc5d977546309f7c765156c8
DIFF: 
https://github.com/llvm/llvm-project/commit/6173d1277be04739bc5d977546309f7c765156c8.diff

LOG: Remove allow-unregistered-dialect from some tests that don't need it

Differential Revision: https://reviews.llvm.org/D93982

Added: 


Modified: 
mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir
mlir/test/Conversion/GPUCommon/lower-launch-func-to-gpu-runtime-calls.mlir
mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
mlir/test/Conversion/GPUCommon/lower-wait-to-gpu-runtime-calls.mlir

Removed: 




diff  --git 
a/mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir 
b/mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir
index 06ccd1e8f4ee..d1b1af813163 100644
--- a/mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir
+++ b/mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt -allow-unregistered-dialect %s --gpu-to-llvm | FileCheck %s
+// RUN: mlir-opt %s --gpu-to-llvm | FileCheck %s
 
 module attributes {gpu.container_module} {
   func @main() {

diff  --git 
a/mlir/test/Conversion/GPUCommon/lower-launch-func-to-gpu-runtime-calls.mlir 
b/mlir/test/Conversion/GPUCommon/lower-launch-func-to-gpu-runtime-calls.mlir
index c63936848e9a..3fcf3a00ab9a 100644
--- a/mlir/test/Conversion/GPUCommon/lower-launch-func-to-gpu-runtime-calls.mlir
+++ b/mlir/test/Conversion/GPUCommon/lower-launch-func-to-gpu-runtime-calls.mlir
@@ -1,5 +1,5 @@
-// RUN: mlir-opt -allow-unregistered-dialect %s 
--gpu-to-llvm="gpu-binary-annotation=nvvm.cubin" | FileCheck %s
-// RUN: mlir-opt -allow-unregistered-dialect %s 
--gpu-to-llvm="gpu-binary-annotation=rocdl.hsaco" | FileCheck %s 
--check-prefix=ROCDL
+// RUN: mlir-opt %s --gpu-to-llvm="gpu-binary-annotation=nvvm.cubin" | 
FileCheck %s
+// RUN: mlir-opt %s --gpu-to-llvm="gpu-binary-annotation=rocdl.hsaco" | 
FileCheck %s --check-prefix=ROCDL
 
 module attributes {gpu.container_module} {
 

diff  --git 
a/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir 
b/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
index 790c92f92ec9..162c2f4e838a 100644
--- a/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
+++ b/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt -allow-unregistered-dialect %s --gpu-to-llvm | FileCheck %s
+// RUN: mlir-opt %s --gpu-to-llvm | FileCheck %s
 
 module attributes {gpu.container_module} {
 

diff  --git 
a/mlir/test/Conversion/GPUCommon/lower-wait-to-gpu-runtime-calls.mlir 
b/mlir/test/Conversion/GPUCommon/lower-wait-to-gpu-runtime-calls.mlir
index b6eacfb969dd..3234e885185e 100644
--- a/mlir/test/Conversion/GPUCommon/lower-wait-to-gpu-runtime-calls.mlir
+++ b/mlir/test/Conversion/GPUCommon/lower-wait-to-gpu-runtime-calls.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt -allow-unregistered-dialect %s --gpu-to-llvm | FileCheck %s
+// RUN: mlir-opt %s --gpu-to-llvm | FileCheck %s
 
 module attributes {gpu.container_module} {
 



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[llvm-branch-commits] [llvm] 08e5e91 - [X86] Remove [ER]SP from all CSR lists

[Reid Kleckner via llvm-branch-commits]

Author: Reid Kleckner
Date: 2021-01-06T09:50:46-08:00
New Revision: 08e5e91e45af96e564f3c19be7ed4cb00bac3034

URL: 
https://github.com/llvm/llvm-project/commit/08e5e91e45af96e564f3c19be7ed4cb00bac3034
DIFF: 
https://github.com/llvm/llvm-project/commit/08e5e91e45af96e564f3c19be7ed4cb00bac3034.diff

LOG: [X86] Remove [ER]SP from all CSR lists

The CSR lists control which registers are spilled and reloaded in the
prologue and epilogue. The stack pointer is managed explicitly, and
should never be pushed or popped. Remove it from these lists. This
affected regcall and preserves all / most.

Differential Revision: https://reviews.llvm.org/D94118

Added: 


Modified: 
llvm/lib/Target/X86/X86CallingConv.td
llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/test/CodeGen/X86/dynamic-regmask.ll
llvm/test/CodeGen/X86/ipra-reg-usage.ll

Removed: 




diff  --git a/llvm/lib/Target/X86/X86CallingConv.td 
b/llvm/lib/Target/X86/X86CallingConv.td
index 9e414ceeb781..3735fab818ce 100644
--- a/llvm/lib/Target/X86/X86CallingConv.td
+++ b/llvm/lib/Target/X86/X86CallingConv.td
@@ -1102,7 +1102,7 @@ def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub 
CSR_64_TLS_Darwin, RBP)
 
 // All GPRs - except r11
 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
-  R8, R9, R10, RSP)>;
+  R8, R9, R10)>;
 
 // All registers - except r11
 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
@@ -1160,17 +1160,16 @@ def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add 
RBX, RSI, R14, R15,
 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;
 
 // Register calling convention preserves few GPR and XMM8-15
-def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>;
+def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
 def CSR_32_RegCall   : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,
(sequence "XMM%u", 4, 7))>;
 def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 
ECX)>;
 def CSR_Win32_CFGuard_Check   : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>;
-def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
+def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP,
   (sequence "R%u", 10, 15))>;
 def CSR_Win64_RegCall   : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE,
  
   (sequence "XMM%u", 8, 15))>;
-def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
+def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP,
(sequence "R%u", 12, 15))>;
 def CSR_SysV64_RegCall   : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE,  
 
(sequence "XMM%u", 8, 15))>;
-   

diff  --git a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll 
b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
index 799747b2aba6..ffe5ffb64af1 100644
--- a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
+++ b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
@@ -283,8 +283,7 @@ declare i32 @test_argv32i1helper(<32 x i1> %x0, <32 x i1> 
%x1, <32 x i1> %x2)
 define dso_local x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> 
%x1, <32 x i1> %x2)  {
 ; X32-LABEL: test_argv32i1:
 ; X32:   # %bb.0: # %entry
-; X32-NEXT:pushl %esp
-; X32-NEXT:subl $72, %esp
+; X32-NEXT:subl $76, %esp
 ; X32-NEXT:vmovups %xmm7, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
 ; X32-NEXT:vmovups %xmm6, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
 ; X32-NEXT:vmovups %xmm5, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
@@ -303,8 +302,7 @@ define dso_local x86_regcallcc i32 @test_argv32i1(<32 x i1> 
%x0, <32 x i1> %x1,
 ; X32-NEXT:vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm5 # 16-byte Reload
 ; X32-NEXT:vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm6 # 16-byte Reload
 ; X32-NEXT:vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm7 # 16-byte Reload
-; X32-NEXT:addl $72, %esp
-; X32-NEXT:popl %esp
+; X32-NEXT:addl $76, %esp
 ; X32-NEXT:vzeroupper
 ; X32-NEXT:retl
 ;
@@ -316,10 +314,8 @@ define dso_local x86_regcallcc i32 @test_argv32i1(<32 x 
i1> %x0, <32 x i1> %x1,
 ; WIN64-NEXT:.seh_pushreg %r11
 ; WIN64-NEXT:pushq %r10
 ; WIN64-NEXT:.seh_pushreg %r10
-; WIN64-NEXT:pushq %rsp
-; WIN64-NEXT:.seh_pushreg %rsp
-; WIN64-NEXT:subq $152, %rsp
-; WIN64-NEXT:.seh_stackalloc 152
+; WIN64-NEXT:subq $128, %rsp
+; WIN64-NEXT:.seh_stackalloc 128
 ; WIN64-NEXT:leaq {{[0-9]+}}(%rsp), %rbp
 ; WIN64-NEXT:.seh_setframe %rbp, 128
 ; WIN64-NEXT:.seh_endprologue
@@ -339,8 +335,7 @@ define dso_

[llvm-branch-commits] [clang] 7ef9139 - [Clang] Remove unnecessary Attr.isArgIdent checks.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-06T18:01:41Z
New Revision: 7ef9139a391a6d526afab0216a97f9d65a6b5563

URL: 
https://github.com/llvm/llvm-project/commit/7ef9139a391a6d526afab0216a97f9d65a6b5563
DIFF: 
https://github.com/llvm/llvm-project/commit/7ef9139a391a6d526afab0216a97f9d65a6b5563.diff

LOG: [Clang] Remove unnecessary Attr.isArgIdent checks.

The MatrixType, ExtVectorType, VectorSize and AddressSpace attributes
have arguments defined as ExprArguments in Attr.td. So their arguments
should never be ArgIdents and the logic to handle this case can be
removed.

The logic has been replaced by an assertion to ensure the arguments
are always ArgExpressions

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D94092

Added: 


Modified: 
clang/lib/Sema/SemaType.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index 00ec0c4a0cee..3f564541d41d 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -6434,25 +6434,7 @@ static void HandleAddressSpaceTypeAttribute(QualType 
&Type,
   return;
 }
 
-Expr *ASArgExpr;
-if (Attr.isArgIdent(0)) {
-  // Special case where the argument is a template id.
-  CXXScopeSpec SS;
-  SourceLocation TemplateKWLoc;
-  UnqualifiedId id;
-  id.setIdentifier(Attr.getArgAsIdent(0)->Ident, Attr.getLoc());
-
-  ExprResult AddrSpace = S.ActOnIdExpression(
-  S.getCurScope(), SS, TemplateKWLoc, id, /*HasTrailingLParen=*/false,
-  /*IsAddressOfOperand=*/false);
-  if (AddrSpace.isInvalid())
-return;
-
-  ASArgExpr = static_cast(AddrSpace.get());
-} else {
-  ASArgExpr = static_cast(Attr.getArgAsExpr(0));
-}
-
+Expr *ASArgExpr = static_cast(Attr.getArgAsExpr(0));
 LangAS ASIdx;
 if (!BuildAddressSpaceIndex(S, ASIdx, ASArgExpr, Attr.getLoc())) {
   Attr.setInvalid();
@@ -7658,25 +7640,7 @@ static void HandleVectorSizeAttr(QualType &CurType, 
const ParsedAttr &Attr,
 return;
   }
 
-  Expr *SizeExpr;
-  // Special case where the argument is a template id.
-  if (Attr.isArgIdent(0)) {
-CXXScopeSpec SS;
-SourceLocation TemplateKWLoc;
-UnqualifiedId Id;
-Id.setIdentifier(Attr.getArgAsIdent(0)->Ident, Attr.getLoc());
-
-ExprResult Size = S.ActOnIdExpression(S.getCurScope(), SS, TemplateKWLoc,
-  Id, /*HasTrailingLParen=*/false,
-  /*IsAddressOfOperand=*/false);
-
-if (Size.isInvalid())
-  return;
-SizeExpr = Size.get();
-  } else {
-SizeExpr = Attr.getArgAsExpr(0);
-  }
-
+  Expr *SizeExpr = Attr.getArgAsExpr(0);
   QualType T = S.BuildVectorType(CurType, SizeExpr, Attr.getLoc());
   if (!T.isNull())
 CurType = T;
@@ -7695,28 +7659,8 @@ static void HandleExtVectorTypeAttr(QualType &CurType, 
const ParsedAttr &Attr,
 return;
   }
 
-  Expr *sizeExpr;
-
-  // Special case where the argument is a template id.
-  if (Attr.isArgIdent(0)) {
-CXXScopeSpec SS;
-SourceLocation TemplateKWLoc;
-UnqualifiedId id;
-id.setIdentifier(Attr.getArgAsIdent(0)->Ident, Attr.getLoc());
-
-ExprResult Size = S.ActOnIdExpression(S.getCurScope(), SS, TemplateKWLoc,
-  id, /*HasTrailingLParen=*/false,
-  /*IsAddressOfOperand=*/false);
-if (Size.isInvalid())
-  return;
-
-sizeExpr = Size.get();
-  } else {
-sizeExpr = Attr.getArgAsExpr(0);
-  }
-
-  // Create the vector type.
-  QualType T = S.BuildExtVectorType(CurType, sizeExpr, Attr.getLoc());
+  Expr *SizeExpr = Attr.getArgAsExpr(0);
+  QualType T = S.BuildExtVectorType(CurType, SizeExpr, Attr.getLoc());
   if (!T.isNull())
 CurType = T;
 }
@@ -7988,49 +7932,8 @@ static void HandleMatrixTypeAttr(QualType &CurType, 
const ParsedAttr &Attr,
 return;
   }
 
-  Expr *RowsExpr = nullptr;
-  Expr *ColsExpr = nullptr;
-
-  // TODO: Refactor parameter extraction into separate function
-  // Get the number of rows
-  if (Attr.isArgIdent(0)) {
-CXXScopeSpec SS;
-SourceLocation TemplateKeywordLoc;
-UnqualifiedId id;
-id.setIdentifier(Attr.getArgAsIdent(0)->Ident, Attr.getLoc());
-ExprResult Rows = S.ActOnIdExpression(S.getCurScope(), SS,
-  TemplateKeywordLoc, id, false, 
false);
-
-if (Rows.isInvalid())
-  // TODO: maybe a good error message would be nice here
-  return;
-RowsExpr = Rows.get();
-  } else {
-assert(Attr.isArgExpr(0) &&
-   "Argument to should either be an identity or expression");
-RowsExpr = Attr.getArgAsExpr(0);
-  }
-
-  // Get the number of columns
-  if (Attr.isArgIdent(1)) {
-CXXScopeSpec SS;
-SourceLocation TemplateKeywordLoc;
-UnqualifiedId id;
-id.setIdentifier(Attr.getArgAsIdent(1)->Ident, Attr.getLoc());
-ExprResult Columns =

[llvm-branch-commits] [llvm] 3f8c252 - [X86] Add commuted patterns test coverage for D93599

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-06T18:03:20Z
New Revision: 3f8c2520c0424860b4bd3ae7b20f8033ed09363a

URL: 
https://github.com/llvm/llvm-project/commit/3f8c2520c0424860b4bd3ae7b20f8033ed09363a
DIFF: 
https://github.com/llvm/llvm-project/commit/3f8c2520c0424860b4bd3ae7b20f8033ed09363a.diff

LOG: [X86] Add commuted patterns test coverage for D93599

Suggested by @spatel

Added: 


Modified: 
llvm/test/CodeGen/X86/cmp-concat.ll

Removed: 




diff  --git a/llvm/test/CodeGen/X86/cmp-concat.ll 
b/llvm/test/CodeGen/X86/cmp-concat.ll
index a622ad7faff7..e3a69df86563 100644
--- a/llvm/test/CodeGen/X86/cmp-concat.ll
+++ b/llvm/test/CodeGen/X86/cmp-concat.ll
@@ -35,6 +35,46 @@ define i1 @cmp_anybits_concat_i32(i32 %x, i32 %y) {
   ret i1 %r
 }
 
+define i1 @cmp_anybits_concat_shl_shl_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: cmp_anybits_concat_shl_shl_i16:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:# kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:movzwl %di, %eax
+; CHECK-NEXT:movzwl %si, %ecx
+; CHECK-NEXT:shlq $32, %rax
+; CHECK-NEXT:shlq $8, %rcx
+; CHECK-NEXT:orq %rax, %rcx
+; CHECK-NEXT:sete %al
+; CHECK-NEXT:retq
+  %zx = zext i16 %x to i64
+  %zy = zext i16 %y to i64
+  %sx = shl i64 %zx, 32
+  %sy = shl i64 %zy, 8
+  %or = or i64 %sx, %sy
+  %r = icmp eq i64 %or, 0
+  ret i1 %r
+}
+
+define i1 @cmp_anybits_concat_shl_shl_i16_commute(i16 %x, i16 %y) {
+; CHECK-LABEL: cmp_anybits_concat_shl_shl_i16_commute:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:# kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:movzwl %di, %eax
+; CHECK-NEXT:movzwl %si, %ecx
+; CHECK-NEXT:shlq $32, %rax
+; CHECK-NEXT:shlq $8, %rcx
+; CHECK-NEXT:orq %rax, %rcx
+; CHECK-NEXT:sete %al
+; CHECK-NEXT:retq
+  %zx = zext i16 %x to i64
+  %zy = zext i16 %y to i64
+  %sx = shl i64 %zx, 32
+  %sy = shl i64 %zy, 8
+  %or = or i64 %sy, %sx
+  %r = icmp eq i64 %or, 0
+  ret i1 %r
+}
+
 define <16 x i8> @cmp_allbits_concat_v16i8(<16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: cmp_allbits_concat_v16i8:
 ; CHECK:   # %bb.0:



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[llvm-branch-commits] [llvm] 90347ab - [NFC] Removed unused prefixes in CodeGen/AMDGPU

[Mircea Trofin via llvm-branch-commits]

Author: Mircea Trofin
Date: 2021-01-06T10:32:44-08:00
New Revision: 90347ab96f25c913c832b86c69efa525db7bd039

URL: 
https://github.com/llvm/llvm-project/commit/90347ab96f25c913c832b86c69efa525db7bd039
DIFF: 
https://github.com/llvm/llvm-project/commit/90347ab96f25c913c832b86c69efa525db7bd039.diff

LOG: [NFC] Removed unused prefixes in CodeGen/AMDGPU

This covers tests starting with m-r.

Differential Revision: https://reviews.llvm.org/D94181

Added: 


Modified: 
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
llvm/test/CodeGen/AMDGPU/max.i16.ll
llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
llvm/test/CodeGen/AMDGPU/min.ll
llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
llvm/test/CodeGen/AMDGPU/mul.i16.ll
llvm/test/CodeGen/AMDGPU/nand.ll
llvm/test/CodeGen/AMDGPU/nested-calls.ll
llvm/test/CodeGen/AMDGPU/nor.ll
llvm/test/CodeGen/AMDGPU/omod.ll
llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
llvm/test/CodeGen/AMDGPU/private-element-size.ll
llvm/test/CodeGen/AMDGPU/r600.bitcast.ll
llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll

Removed: 




diff  --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll 
b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index f20e29f17849..2b3bdf1974c4 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck 
-enable-var-scope -check-prefixes=GCN,GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck 
-enable-var-scope -check-prefixes=GCN,CIVI,VI %s
-; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck 
-enable-var-scope -check-prefixes=GCN,CIVI,CI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck 
-enable-var-scope --check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck 
-enable-var-scope --check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
 ; GFX9: s_waitcnt

diff  --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll 
b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index db2ed78a15f0..f08ed4843417 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs 
-enable-misched=false < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs 
-enable-misched=false < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,CIVI,VI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs 
-enable-misched=false < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,CIVI %s
 ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs 
-enable-misched=false < %s | FileCheck -enable-var-scope 
-check-prefixes=GCN,CIVI,CI %s
 
 ; GCN-LABEL: mixlo_simple:

diff  --git a/llvm/test/CodeGen/AMDGPU/max.i16.ll 
b/llvm/test/CodeGen/AMDGPU/max.i16.ll
index 90e565020688..dfbdd2b1f92a 100644
--- a/llvm/test/CodeGen/AMDGPU/max.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/max.i16.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global 
-verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,VI
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global 
-verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,GFX9
+; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global 
-verify-machineinstrs < %s | FileCheck %s --check-prefix=VI
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global 
-verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX9
 
 ; FIXME: Need to handle non-uniform case for function below (load without gep).
 define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 
addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {

diff  --git a/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll 
b/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
index 0d00c9a5e8e5..efa104b732f5 100644
--- a/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
+++ b/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-scalar-ir-passes=false 
< %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global 
-verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | F

[llvm-branch-commits] [clang] 1ca5e68 - [NVPTX] Fix debugging information being added to NVPTX target if remarks are enabled

[via llvm-branch-commits]

Author: Joseph Huber
Date: 2021-01-06T13:43:22-05:00
New Revision: 1ca5e68aa07e30567c6aa2409c5641e0a2d77355

URL: 
https://github.com/llvm/llvm-project/commit/1ca5e68aa07e30567c6aa2409c5641e0a2d77355
DIFF: 
https://github.com/llvm/llvm-project/commit/1ca5e68aa07e30567c6aa2409c5641e0a2d77355.diff

LOG: [NVPTX] Fix debugging information being added to NVPTX target if remarks 
are enabled
Summary:
Optimized debugging is not supported by ptxas. Debugging information is 
degraded to line information only if optimizations are enabled, but debugging 
information would be added back in by the driver if remarks were enabled. This 
solves https://bugs.llvm.org/show_bug.cgi?id=48153.

Reviewers: jdoerfert tra jholewinski serge-sans-paille

Differential Revision: https://reviews.llvm.org/D94123

Added: 


Modified: 
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/Cuda.cpp

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 917601836c0a..a462758bf1c2 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -3940,14 +3940,14 @@ static void RenderDebugOptions(const ToolChain &TC, 
const Driver &D,
 CmdArgs.push_back("-gno-inline-line-tables");
   }
 
-  // Adjust the debug info kind for the given toolchain.
-  TC.adjustDebugInfoKind(DebugInfoKind, Args);
-
   // When emitting remarks, we need at least debug lines in the output.
   if (willEmitRemarks(Args) &&
   DebugInfoKind <= codegenoptions::DebugDirectivesOnly)
 DebugInfoKind = codegenoptions::DebugLineTablesOnly;
 
+  // Adjust the debug info kind for the given toolchain.
+  TC.adjustDebugInfoKind(DebugInfoKind, Args);
+
   RenderDebugEnablingArgs(Args, CmdArgs, DebugInfoKind, EffectiveDWARFVersion,
   DebuggerTuning);
 

diff  --git a/clang/lib/Driver/ToolChains/Cuda.cpp 
b/clang/lib/Driver/ToolChains/Cuda.cpp
index 58178d5d11bc..95fd5a1fbfee 100644
--- a/clang/lib/Driver/ToolChains/Cuda.cpp
+++ b/clang/lib/Driver/ToolChains/Cuda.cpp
@@ -384,7 +384,7 @@ static DeviceDebugInfoLevel mustEmitDebugInfo(const ArgList 
&Args) {
 }
 return IsDebugEnabled ? EmitSameDebugInfoAsHost : DebugDirectivesOnly;
   }
-  return DisableDebugInfo;
+  return willEmitRemarks(Args) ? DebugDirectivesOnly : DisableDebugInfo;
 }
 
 void NVPTX::Assembler::ConstructJob(Compilation &C, const JobAction &JA,



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[llvm-branch-commits] [compiler-rt] 7afdc89 - [sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX feature detection and support musl

[Fangrui Song via llvm-branch-commits]

Author: Fangrui Song
Date: 2021-01-06T10:55:40-08:00
New Revision: 7afdc89c2054d6fa3a6c2f2f24411becfc764676

URL: 
https://github.com/llvm/llvm-project/commit/7afdc89c2054d6fa3a6c2f2f24411becfc764676
DIFF: 
https://github.com/llvm/llvm-project/commit/7afdc89c2054d6fa3a6c2f2f24411becfc764676.diff

LOG: [sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX feature 
detection and support musl

Several `#if SANITIZER_LINUX && !SANITIZER_ANDROID` guards are replaced
with the more appropriate `#if SANITIZER_GLIBC` (the headers are glibc
extensions, not specific to Linux (i.e. if we ever support GNU/kFreeBSD
or Hurd, the guards may automatically work)).

Several `#if SANITIZER_LINUX && !SANITIZER_ANDROID` guards are refined
with `#if SANITIZER_GLIBC` (the definitions are available on Linux glibc,
but may not be available on other libc (e.g. musl) implementations).

This patch makes `ninja asan cfi lsan msan stats tsan ubsan xray` build on a 
musl based Linux distribution (apk install musl-libintl)
Notes about disabled interceptors for musl:

* `SANITIZER_INTERCEPT_GLOB`: musl does not implement `GLOB_ALTDIRFUNC` (GNU 
extension)
* Some ioctl structs and functions operating on them.
* `SANITIZER_INTERCEPT___PRINTF_CHK`: `_FORTIFY_SOURCE` functions are GNU 
extension
* `SANITIZER_INTERCEPT___STRNDUP`: `dlsym(RTLD_NEXT, "__strndup")` errors so a 
diagnostic is formed. The diagnostic uses `write` which hasn't been intercepted 
=> SIGSEGV
* `SANITIZER_INTERCEPT_*64`: the `_LARGEFILE64_SOURCE` functions are glibc 
specific. musl does something like `#define pread64 pread`
* Disabled `msg_iovlen msg_controllen cmsg_len` checks: musl is conforming 
while many implementations (Linux/FreeBSD/NetBSD/Solaris) are non-conforming. 
Since we pick the glibc definition, exclude the checks for musl (incompatible 
sizes but compatible offsets)

Pass through LIBCXX_HAS_MUSL_LIBC to make check-msan/check-tsan able to build 
libc++ (https://bugs.llvm.org/show_bug.cgi?id=48618).

Many sanitizer features are available now.

```
% ninja check-asan
(known issues:
* ASAN_OPTIONS=fast_unwind_on_malloc=0 odr-violations hangs
)
...
Testing Time: 53.69s
  Unsupported  : 185
  Passed   : 512
  Expectedly Failed:   1
  Failed   :  12

% ninja check-ubsan check-ubsan-minimal check-memprof # all passed

% ninja check-cfi
( all cross-dso/)
...
Testing Time: 8.68s
  Unsupported  : 264
  Passed   :  80
  Expectedly Failed:   8
  Failed   :  32

% ninja check-lsan
(With GetTls (D93972), 10 failures)
Testing Time: 4.09s
  Unsupported:  7
  Passed : 65
  Failed : 22

% ninja check-msan
(Many are due to functions not marked unsupported.)
Testing Time: 23.09s
  Unsupported  :   6
  Passed   : 764
  Expectedly Failed:   2
  Failed   :  58

% ninja check-tsan
Testing Time: 23.21s
  Unsupported  :  86
  Passed   : 295
  Expectedly Failed:   1
  Failed   :  25
```

Used `ASAN_OPTIONS=verbosity=2` to verify there is no unneeded interceptor.

Partly based on Jari Ronkainen's https://reviews.llvm.org/D63785#1921014

Note: we need to place `_FILE_OFFSET_BITS` above `#include 
"sanitizer_platform.h"` to avoid `#define __USE_FILE_OFFSET64 1` in 32-bit ARM 
`features.h`

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D93848

Added: 


Modified: 
compiler-rt/cmake/Modules/AddCompilerRT.cmake
compiler-rt/lib/asan/asan_interceptors.h
compiler-rt/lib/asan/tests/asan_test.cpp
compiler-rt/lib/interception/interception_linux.cpp
compiler-rt/lib/interception/interception_linux.h
compiler-rt/lib/msan/tests/msan_test.cpp
compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
compiler-rt/lib/sanitizer_common/sanitizer_platform.h
compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
compiler-rt/lib/sanitizer_common/sanitizer_procmaps_solaris.cpp
compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake 
b/compiler-rt/cmake/Modules/AddCompilerRT.cmake
index 0b8db6a868a1..361538a58e47 100644
--- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake
+++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake
@@ -583,6 +583,7 @@ macro(add_custom_libcxx name prefix)
 CMAKE_OBJDUMP
 CMAKE_STRIP
 CMAKE_SYSROOT
+LIBCXX_HAS_MUSL_LIBC
 PYTHON_EXECUTABLE
 Python3_EXECUTABLE
 Python2_EXECUTABLE

diff  --git a/compiler-rt/lib/asan/asan_interceptors.h 
b/compiler-rt/lib/asan/asan_interceptors.h
index 4266a31cecb9..45cdb80b1b64 100644
--- a/compiler-rt/lib/asan/asan_interceptors.h
+++ b/compiler

[llvm-branch-commits] [lld] 7916fd7 - [lld-macho] Fix GCC -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off build

[Fangrui Song via llvm-branch-commits]

Author: Fangrui Song
Date: 2021-01-06T10:58:46-08:00
New Revision: 7916fd71e9431829b22aed77711e11ea1dc225e3

URL: 
https://github.com/llvm/llvm-project/commit/7916fd71e9431829b22aed77711e11ea1dc225e3
DIFF: 
https://github.com/llvm/llvm-project/commit/7916fd71e9431829b22aed77711e11ea1dc225e3.diff

LOG: [lld-macho] Fix GCC -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off build

Added: 


Modified: 
lld/MachO/SyntheticSections.cpp

Removed: 




diff  --git a/lld/MachO/SyntheticSections.cpp b/lld/MachO/SyntheticSections.cpp
index 2ed1f2eb34fb..3f5413696d4b 100644
--- a/lld/MachO/SyntheticSections.cpp
+++ b/lld/MachO/SyntheticSections.cpp
@@ -722,6 +722,7 @@ void SymtabSection::finalizeContents() {
   for (Symbol *sym : symtab->getSymbols()) {
 if (auto *defined = dyn_cast(sym)) {
   assert(defined->isExternal());
+  (void)defined;
   addSymbol(externalSymbols, sym);
 } else if (auto *dysym = dyn_cast(sym)) {
   if (dysym->isReferenced())



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[llvm-branch-commits] [flang] 322e98b - [flang][openacc] Add more parsing/sema tests for init and shutdown directives

[via llvm-branch-commits]

Author: Valentin Clement
Date: 2021-01-06T14:15:19-05:00
New Revision: 322e98bc279989a6fb7f181b6f6a2d9a6927dd67

URL: 
https://github.com/llvm/llvm-project/commit/322e98bc279989a6fb7f181b6f6a2d9a6927dd67
DIFF: 
https://github.com/llvm/llvm-project/commit/322e98bc279989a6fb7f181b6f6a2d9a6927dd67.diff

LOG: [flang][openacc] Add more parsing/sema tests for init and shutdown 
directives

This patch adds some positive and failure tests for init and shutdown 
directives.

Reviewed By: kiranktp

Differential Revision: https://reviews.llvm.org/D90786

Added: 


Modified: 
flang/test/Semantics/acc-clause-validity.f90

Removed: 




diff  --git a/flang/test/Semantics/acc-clause-validity.f90 
b/flang/test/Semantics/acc-clause-validity.f90
index d410c5b4bf85..167051d18760 100644
--- a/flang/test/Semantics/acc-clause-validity.f90
+++ b/flang/test/Semantics/acc-clause-validity.f90
@@ -16,6 +16,8 @@
 !   2.11 Kernels Loop
 !   2.11 Serial Loop
 !   2.14.3 Set
+!   2.14.1 Init
+!   2.14.2 Shutdown
 !   2.16.13 Wait
 
 program openacc_clause_validity
@@ -267,6 +269,32 @@ program openacc_clause_validity
   !$acc set device_type(i)
   !$acc set device_type(2, i, j)
   !$acc set device_num(1) default_async(2) device_type(2, i, j)
+  !ERROR: At most one IF clause can appear on the INIT directive
+  !$acc init if(.TRUE.) if(ifCondition)
+
+  !ERROR: At most one DEVICE_NUM clause can appear on the INIT directive
+  !$acc init device_num(1) device_num(i)
+
+  !ERROR: At most one DEVICE_TYPE clause can appear on the INIT directive
+  !$acc init device_type(2) device_type(i, j)
+
+  !$acc shutdown
+  !$acc shutdown if(.TRUE.)
+  !$acc shutdown if(ifCondition)
+  !$acc shutdown device_num(1)
+  !$acc shutdown device_num(i)
+  !$acc shutdown device_type(i)
+  !$acc shutdown device_type(2, i, j)
+  !$acc shutdown device_num(i) device_type(i, j) if(ifCondition)
+
+  !ERROR: At most one IF clause can appear on the SHUTDOWN directive
+  !$acc shutdown if(.TRUE.) if(ifCondition)
+
+  !ERROR: At most one DEVICE_NUM clause can appear on the SHUTDOWN directive
+  !$acc shutdown device_num(1) device_num(i)
+
+  !ERROR: At most one DEVICE_TYPE clause can appear on the SHUTDOWN directive
+  !$acc shutdown device_type(2) device_type(i, j)
 
   !ERROR: At least one of ATTACH, COPYIN, CREATE clause must appear on the 
ENTER DATA directive
   !$acc enter data



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[llvm-branch-commits] [llvm] 7fea561 - [CGSCC][Coroutine][NewPM] Properly support function splitting/outlining

[Arthur Eubanks via llvm-branch-commits]

Author: Arthur Eubanks
Date: 2021-01-06T11:19:15-08:00
New Revision: 7fea561eb1ce0a339f3c47f6d89d2e9fa8706ab0

URL: 
https://github.com/llvm/llvm-project/commit/7fea561eb1ce0a339f3c47f6d89d2e9fa8706ab0
DIFF: 
https://github.com/llvm/llvm-project/commit/7fea561eb1ce0a339f3c47f6d89d2e9fa8706ab0.diff

LOG: [CGSCC][Coroutine][NewPM] Properly support function splitting/outlining

Previously when trying to support CoroSplit's function splitting, we
added in a hack that simply added the new function's node into the
original function's SCC (https://reviews.llvm.org/D87798). This is
incorrect since it might be in its own SCC.

Now, more similar to the previous design, we have callers explicitly
notify the LazyCallGraph that a function has been split out from another
one.

In order to properly support CoroSplit, there are two ways functions can
be split out.

One is the normal expected "outlining" of one function into a new one.
The new function may only contain references to other functions that the
original did. The original function must reference the new function. The
new function may reference the original function, which can result in
the new function being in the same SCC as the original function. The
weird case is when the original function indirectly references the new
function, but the new function directly calls the original function,
resulting in the new SCC being a parent of the original function's SCC.
This form of function splitting works with CoroSplit's Switch ABI.

The second way of splitting is more specific to CoroSplit. CoroSplit's
Retcon and Async ABIs split the original function into multiple
functions that all reference each other and are referenced by the
original function. In order to keep the LazyCallGraph in a valid state,
all new functions must be processed together, else some nodes won't be
populated. To keep things simple, this only supports the case where all
new edges are ref edges, and every new function references every other
new function. There can be a reference back from any new function to the
original function, putting all functions in the same RefSCC.

This also adds asserts that all nodes in a (Ref)SCC can reach all other
nodes to prevent future incorrect hacks.

The original hacks in https://reviews.llvm.org/D87798 are no longer
necessary since all new functions should have been registered before
calling updateCGAndAnalysisManagerForPass.

This fixes all coroutine tests when opt's -enable-new-pm is true by
default. This also fixes PR48190, which was likely due to the previous
hack breaking SCC invariants.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D93828

Added: 
llvm/test/Transforms/Coroutines/coro-split-recursive.ll

Modified: 
llvm/include/llvm/Analysis/LazyCallGraph.h
llvm/include/llvm/Transforms/Utils/CallGraphUpdater.h
llvm/lib/Analysis/CGSCCPassManager.cpp
llvm/lib/Analysis/LazyCallGraph.cpp
llvm/lib/Transforms/Coroutines/CoroSplit.cpp
llvm/lib/Transforms/IPO/OpenMPOpt.cpp
llvm/lib/Transforms/Utils/CallGraphUpdater.cpp
llvm/test/Transforms/Coroutines/coro-async.ll
llvm/test/Transforms/Coroutines/coro-retcon-resume-values2.ll
llvm/unittests/Analysis/CGSCCPassManagerTest.cpp
llvm/unittests/Analysis/LazyCallGraphTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/Analysis/LazyCallGraph.h 
b/llvm/include/llvm/Analysis/LazyCallGraph.h
index e92134d074e5..f7a5adac2b43 100644
--- a/llvm/include/llvm/Analysis/LazyCallGraph.h
+++ b/llvm/include/llvm/Analysis/LazyCallGraph.h
@@ -997,10 +997,6 @@ class LazyCallGraph {
   /// remain active and reachable.
   bool isLibFunction(Function &F) const { return LibFunctions.count(&F); }
 
-  /// Helper to initialize a new node created outside of creating SCCs and add
-  /// it to the NodeMap. e.g. when a function is outlined.
-  Node &initNode(Node &N, LazyCallGraph::SCC &C);
-
   ///@{
   /// \name Pre-SCC Mutation API
   ///
@@ -1050,6 +1046,30 @@ class LazyCallGraph {
   /// fully visited by the DFS prior to calling this routine.
   void removeDeadFunction(Function &F);
 
+  /// Add a new function split/outlined from an existing function.
+  ///
+  /// The new function may only reference other functions that the original
+  /// function did.
+  ///
+  /// The original function must reference (either directly or indirectly) the
+  /// new function.
+  ///
+  /// The new function may also reference the original function.
+  /// It may end up in a parent SCC in the case that the original function's
+  /// edge to the new function is a ref edge, and the edge back is a call edge.
+  void addSplitFunction(Function &OriginalFunction, Function &NewFunction);
+
+  /// Add new ref-recursive functions split/outlined from an existing function.
+  ///
+  /// The new functions may only reference other functions that the original
+  /// function did. The new functions may reference (not cal

[llvm-branch-commits] [llvm] 5d24089 - [SLP] reduce code for propagating flags on reductions; NFC

[Sanjay Patel via llvm-branch-commits]

Author: Sanjay Patel
Date: 2021-01-06T14:37:44-05:00
New Revision: 5d24089a7001e9fb4c0e665e93312916d88aaef9

URL: 
https://github.com/llvm/llvm-project/commit/5d24089a7001e9fb4c0e665e93312916d88aaef9
DIFF: 
https://github.com/llvm/llvm-project/commit/5d24089a7001e9fb4c0e665e93312916d88aaef9.diff

LOG: [SLP] reduce code for propagating flags on reductions; NFC

If we add/change to match intrinsics, this might get more
wordy, but there's no need to list each kind currently.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp 
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 75f881dc7d4b..c4278722418b 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6637,28 +6637,15 @@ class HorizontalReduction {
 const ReductionOpsListType &ReductionOps) const {
   assert(isVectorizable() &&
  "Expected add|fadd or min/max reduction operation.");
-  auto *Op = createOp(Builder, LHS, RHS, Name);
-  switch (Kind) {
-  case RecurKind::Add:
-  case RecurKind::Mul:
-  case RecurKind::Or:
-  case RecurKind::And:
-  case RecurKind::Xor:
-  case RecurKind::FAdd:
-  case RecurKind::FMul:
-propagateIRFlags(Op, ReductionOps[0]);
-return Op;
-  case RecurKind::SMax:
-  case RecurKind::SMin:
-  case RecurKind::UMax:
-  case RecurKind::UMin:
-if (auto *SI = dyn_cast(Op))
-  propagateIRFlags(SI->getCondition(), ReductionOps[0]);
+  Value *Op = createOp(Builder, LHS, RHS, Name);
+  if (RecurrenceDescriptor::isIntMinMaxRecurrenceKind(Kind)) {
+if (auto *Sel = dyn_cast(Op))
+  propagateIRFlags(Sel->getCondition(), ReductionOps[0]);
 propagateIRFlags(Op, ReductionOps[1]);
 return Op;
-  default:
-llvm_unreachable("Unknown reduction operation.");
   }
+  propagateIRFlags(Op, ReductionOps[0]);
+  return Op;
 }
 /// Creates reduction operation with the current opcode with the IR flags
 /// from \p I.
@@ -,30 +6653,15 @@ class HorizontalReduction {
 const Twine &Name, Instruction *I) const {
   assert(isVectorizable() &&
  "Expected add|fadd or min/max reduction operation.");
-  auto *Op = createOp(Builder, LHS, RHS, Name);
-  switch (Kind) {
-  case RecurKind::Add:
-  case RecurKind::Mul:
-  case RecurKind::Or:
-  case RecurKind::And:
-  case RecurKind::Xor:
-  case RecurKind::FAdd:
-  case RecurKind::FMul:
-propagateIRFlags(Op, I);
-return Op;
-  case RecurKind::SMax:
-  case RecurKind::SMin:
-  case RecurKind::UMax:
-  case RecurKind::UMin:
-if (auto *SI = dyn_cast(Op)) {
-  propagateIRFlags(SI->getCondition(),
+  Value *Op = createOp(Builder, LHS, RHS, Name);
+  if (RecurrenceDescriptor::isIntMinMaxRecurrenceKind(Kind)) {
+if (auto *Sel = dyn_cast(Op)) {
+  propagateIRFlags(Sel->getCondition(),
cast(I)->getCondition());
 }
-propagateIRFlags(Op, I);
-return Op;
-  default:
-llvm_unreachable("Unknown reduction operation.");
   }
+  propagateIRFlags(Op, I);
+  return Op;
 }
   };
 



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[llvm-branch-commits] [llvm] 4c022b5 - [SLP] use reduction kind's opcode to create new instructions; NFC

[Sanjay Patel via llvm-branch-commits]

Author: Sanjay Patel
Date: 2021-01-06T14:37:44-05:00
New Revision: 4c022b5a41dee998ae50cdad4e8b6548acbeee9f

URL: 
https://github.com/llvm/llvm-project/commit/4c022b5a41dee998ae50cdad4e8b6548acbeee9f
DIFF: 
https://github.com/llvm/llvm-project/commit/4c022b5a41dee998ae50cdad4e8b6548acbeee9f.diff

LOG: [SLP] use reduction kind's opcode to create new instructions; NFC

Similar to 5a1d31a28 -
This should be no-functional-change because the reduction kind
opcodes are 1-for-1 mappings to the instructions we are matching
as reductions. But we want to remove the need for the
`OperationData` opcode field because that does not work when
we start matching intrinsics (eg, maxnum) as reduction candidates.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp 
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index c4278722418b..7b77aef2a75c 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6457,6 +6457,7 @@ class HorizontalReduction {
 Value *createOp(IRBuilder<> &Builder, Value *LHS, Value *RHS,
 const Twine &Name) const {
   assert(isVectorizable() && "Unhandled reduction operation.");
+  unsigned RdxOpcode = RecurrenceDescriptor::getOpcode(Kind);
   switch (Kind) {
   case RecurKind::Add:
   case RecurKind::Mul:
@@ -6465,26 +6466,22 @@ class HorizontalReduction {
   case RecurKind::Xor:
   case RecurKind::FAdd:
   case RecurKind::FMul:
-return Builder.CreateBinOp((Instruction::BinaryOps)Opcode, LHS, RHS,
+return Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, LHS, RHS,
Name);
 
   case RecurKind::SMax: {
-assert(Opcode == Instruction::ICmp && "Expected integer types.");
 Value *Cmp = Builder.CreateICmpSGT(LHS, RHS, Name);
 return Builder.CreateSelect(Cmp, LHS, RHS, Name);
   }
   case RecurKind::SMin: {
-assert(Opcode == Instruction::ICmp && "Expected integer types.");
 Value *Cmp = Builder.CreateICmpSLT(LHS, RHS, Name);
 return Builder.CreateSelect(Cmp, LHS, RHS, Name);
   }
   case RecurKind::UMax: {
-assert(Opcode == Instruction::ICmp && "Expected integer types.");
 Value *Cmp = Builder.CreateICmpUGT(LHS, RHS, Name);
 return Builder.CreateSelect(Cmp, LHS, RHS, Name);
   }
   case RecurKind::UMin: {
-assert(Opcode == Instruction::ICmp && "Expected integer types.");
 Value *Cmp = Builder.CreateICmpULT(LHS, RHS, Name);
 return Builder.CreateSelect(Cmp, LHS, RHS, Name);
   }



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[llvm-branch-commits] [llvm] 8f9da24 - [GVN] Regenerate test checks (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-06T20:41:36+01:00
New Revision: 8f9da24fa7fffd52ccc2c66e3e2c1e7e87ed0336

URL: 
https://github.com/llvm/llvm-project/commit/8f9da24fa7fffd52ccc2c66e3e2c1e7e87ed0336
DIFF: 
https://github.com/llvm/llvm-project/commit/8f9da24fa7fffd52ccc2c66e3e2c1e7e87ed0336.diff

LOG: [GVN] Regenerate test checks (NFC)

Added: 


Modified: 
llvm/test/Transforms/GVN/PRE/volatile.ll

Removed: 




diff  --git a/llvm/test/Transforms/GVN/PRE/volatile.ll 
b/llvm/test/Transforms/GVN/PRE/volatile.ll
index ef1799646318..fe417e38830f 100644
--- a/llvm/test/Transforms/GVN/PRE/volatile.ll
+++ b/llvm/test/Transforms/GVN/PRE/volatile.ll
@@ -8,7 +8,7 @@
 define i32 @test1(i32* nocapture %p, i32* nocapture %q) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT:[[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
 ; CHECK-NEXT:ret i32 0
 ;
 entry:
@@ -24,8 +24,8 @@ entry:
 define i32 @test2(i32* nocapture %p, i32* nocapture %q) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[X:%.*]] = load i32, i32* [[P:%.*]]
-; CHECK-NEXT:[[Y:%.*]] = load volatile i32, i32* [[P]]
+; CHECK-NEXT:[[X:%.*]] = load i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT:[[Y:%.*]] = load volatile i32, i32* [[P]], align 4
 ; CHECK-NEXT:[[ADD:%.*]] = sub i32 [[Y]], [[X]]
 ; CHECK-NEXT:ret i32 [[ADD]]
 ;
@@ -41,9 +41,9 @@ entry:
 define i32 @test3(i32* noalias nocapture %p, i32* noalias nocapture %q) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[X:%.*]] = load i32, i32* [[P:%.*]]
-; CHECK-NEXT:[[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]]
-; CHECK-NEXT:[[Y:%.*]] = load volatile i32, i32* [[P]]
+; CHECK-NEXT:[[X:%.*]] = load i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT:[[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
+; CHECK-NEXT:[[Y:%.*]] = load volatile i32, i32* [[P]], align 4
 ; CHECK-NEXT:[[ADD:%.*]] = sub i32 [[Y]], [[X]]
 ; CHECK-NEXT:ret i32 [[ADD]]
 ;
@@ -79,7 +79,7 @@ entry:
 define i32 @test5(i32* nocapture %p, i32* nocapture %q) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[X:%.*]] = load volatile i32, i32* [[P:%.*]]
+; CHECK-NEXT:[[X:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:ret i32 0
 ;
 entry:
@@ -93,11 +93,11 @@ entry:
 define i32 @test6(i32* noalias nocapture %p, i32* noalias nocapture %q) {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[Y1:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT:[[Y1:%.*]] = load i32, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:call void @use(i32 [[Y1]])
 ; CHECK-NEXT:br label [[HEADER:%.*]]
 ; CHECK:   header:
-; CHECK-NEXT:[[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT:[[X:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
 ; CHECK-NEXT:[[ADD:%.*]] = sub i32 [[Y1]], [[X]]
 ; CHECK-NEXT:[[CND:%.*]] = icmp eq i32 [[ADD]], 0
 ; CHECK-NEXT:br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
@@ -124,15 +124,15 @@ define i32 @test7(i1 %c, i32* noalias nocapture %p, i32* 
noalias nocapture %q) {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:br i1 [[C:%.*]], label [[ENTRY_HEADER_CRIT_EDGE:%.*]], label 
[[SKIP:%.*]]
 ; CHECK:   entry.header_crit_edge:
-; CHECK-NEXT:[[Y_PRE:%.*]] = load i32, i32* [[P:%.*]]
+; CHECK-NEXT:[[Y_PRE:%.*]] = load i32, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:br label [[HEADER:%.*]]
 ; CHECK:   skip:
-; CHECK-NEXT:[[Y1:%.*]] = load i32, i32* [[P]]
+; CHECK-NEXT:[[Y1:%.*]] = load i32, i32* [[P]], align 4
 ; CHECK-NEXT:call void @use(i32 [[Y1]])
 ; CHECK-NEXT:br label [[HEADER]]
 ; CHECK:   header:
 ; CHECK-NEXT:[[Y:%.*]] = phi i32 [ [[Y_PRE]], [[ENTRY_HEADER_CRIT_EDGE]] 
], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[SKIP]] ]
-; CHECK-NEXT:[[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
+; CHECK-NEXT:[[X:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
 ; CHECK-NEXT:[[ADD:%.*]] = sub i32 [[Y]], [[X]]
 ; CHECK-NEXT:[[CND:%.*]] = icmp eq i32 [[ADD]], 0
 ; CHECK-NEXT:br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
@@ -172,7 +172,7 @@ define i32 @test8(i1 %b, i1 %c, i32* noalias %p, i32* 
noalias %q) {
 ; CHECK-NEXT:call void @clobber(i32* [[P]], i32* [[Q]])
 ; CHECK-NEXT:br i1 [[C:%.*]], label [[SKIP_HEADER_CRIT_EDGE]], label 
[[EXIT:%.*]]
 ; CHECK:   skip.header_crit_edge:
-; CHECK-NEXT:[[Y_PRE]] = load i32, i32* [[P]]
+; CHECK-NEXT:[[Y_PRE]] = load i32, i32* [[P]], align 4
 ; CHECK-NEXT:br label [[HEADER]]
 ; CHECK:   exit:
 ; CHECK-NEXT:[[ADD:%.*]] = sub i32 [[Y]], [[X]]



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[llvm-branch-commits] [llvm] a6df392 - [InstSimplify] Fold out-of-bounds shift to poison

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-06T20:41:37+01:00
New Revision: a6df39236fdc6e422f6794935e5e08e05f566e23

URL: 
https://github.com/llvm/llvm-project/commit/a6df39236fdc6e422f6794935e5e08e05f566e23
DIFF: 
https://github.com/llvm/llvm-project/commit/a6df39236fdc6e422f6794935e5e08e05f566e23.diff

LOG: [InstSimplify] Fold out-of-bounds shift to poison

Make InstSimplify return poison rather than undef for out-of-bounds
shifts, as specified by LandRef:

> If op2 is (statically or dynamically) equal to or larger than the
> number of bits in op1, this instruction returns a poison value.

Differential Revision: https://reviews.llvm.org/D93998

Added: 


Modified: 
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
llvm/test/Transforms/InstCombine/out-of-bounds-indexes.ll
llvm/test/Transforms/InstCombine/phi-shifts.ll
llvm/test/Transforms/InstCombine/shift.ll
llvm/test/Transforms/InstSimplify/shift-knownbits.ll
llvm/test/Transforms/InstSimplify/shift.ll
llvm/test/Transforms/InstSimplify/undef.ll

Removed: 




diff  --git a/llvm/lib/Analysis/InstructionSimplify.cpp 
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 659b71fae6a0..1304f0e78b29 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -1197,13 +1197,13 @@ Value *llvm::SimplifyURemInst(Value *Op0, Value *Op1, 
const SimplifyQuery &Q) {
   return ::SimplifyURemInst(Op0, Op1, Q, RecursionLimit);
 }
 
-/// Returns true if a shift by \c Amount always yields undef.
-static bool isUndefShift(Value *Amount, const SimplifyQuery &Q) {
+/// Returns true if a shift by \c Amount always yields poison.
+static bool isPoisonShift(Value *Amount, const SimplifyQuery &Q) {
   Constant *C = dyn_cast(Amount);
   if (!C)
 return false;
 
-  // X shift by undef -> undef because it may shift by the bitwidth.
+  // X shift by undef -> poison because it may shift by the bitwidth.
   if (Q.isUndefValue(C))
 return true;
 
@@ -1218,7 +1218,7 @@ static bool isUndefShift(Value *Amount, const 
SimplifyQuery &Q) {
 for (unsigned I = 0,
   E = cast(C->getType())->getNumElements();
  I != E; ++I)
-  if (!isUndefShift(C->getAggregateElement(I), Q))
+  if (!isPoisonShift(C->getAggregateElement(I), Q))
 return false;
 return true;
   }
@@ -1246,8 +1246,8 @@ static Value *SimplifyShift(Instruction::BinaryOps 
Opcode, Value *Op0,
 return Op0;
 
   // Fold undefined shifts.
-  if (isUndefShift(Op1, Q))
-return UndefValue::get(Op0->getType());
+  if (isPoisonShift(Op1, Q))
+return PoisonValue::get(Op0->getType());
 
   // If the operation is with the result of a select instruction, check whether
   // operating on either branch of the select always yields the same value.
@@ -1265,7 +1265,7 @@ static Value *SimplifyShift(Instruction::BinaryOps 
Opcode, Value *Op0,
   // the number of bits in the type, the shift is undefined.
   KnownBits Known = computeKnownBits(Op1, Q.DL, 0, Q.AC, Q.CxtI, Q.DT);
   if (Known.One.getLimitedValue() >= Known.getBitWidth())
-return UndefValue::get(Op0->getType());
+return PoisonValue::get(Op0->getType());
 
   // If all valid bits in the shift amount are known zero, the first operand is
   // unchanged.

diff  --git a/llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll 
b/llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
index 1dee5eb90ea1..3157cde6d95f 100644
--- a/llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
+++ b/llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
@@ -200,7 +200,7 @@ define <3 x i8> @add-shl-sdiv-negative3(<3 x i8> %x) {
 
 define <2 x i64> @add-shl-sdiv-negative4(<2 x i64> %x) {
 ; CHECK-LABEL: @add-shl-sdiv-negative4(
-; CHECK-NEXT:ret <2 x i64> undef
+; CHECK-NEXT:ret <2 x i64> poison
 ;
   %sd = sdiv <2 x i64> %x, 
   %sl = shl <2 x i64> %sd, 

diff  --git a/llvm/test/Transforms/InstCombine/out-of-bounds-indexes.ll 
b/llvm/test/Transforms/InstCombine/out-of-bounds-indexes.ll
index f3b95ed07d44..269e795d8f23 100644
--- a/llvm/test/Transforms/InstCombine/out-of-bounds-indexes.ll
+++ b/llvm/test/Transforms/InstCombine/out-of-bounds-indexes.ll
@@ -6,7 +6,7 @@ define i32 @test_out_of_bounds(i32 %a, i1 %x, i1 %y) {
 ; CHECK-LABEL: @test_out_of_bounds(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:[[AND1:%.*]] = and i32 [[A:%.*]], 3
-; CHECK-NEXT:tail call void @llvm.assume(i1 undef)
+; CHECK-NEXT:tail call void @llvm.assume(i1 poison)
 ; CHECK-NEXT:ret i32 [[AND1]]
 ;
 entry:
@@ -20,7 +20,7 @@ entry:
 define i128 @test_non64bit(i128 %a) {
 ; CHECK-LABEL: @test_non64bit(
 ; CHECK-NEXT:[[AND1:%.*]] = and i128 [[A:%.*]], 3
-; CHECK-NEXT:tail call void @llvm.assume(i1 undef)
+; CHECK-NEXT:tail call void @llvm.assume(i1 poison)
 ; CHECK-NEXT:ret i128 [[AND1]]
 ;
   %and1 = and i128 %a, 3

diff  --git

[llvm-branch-commits] [llvm] 54c0105 - Fix non-assert builds after D93828

[Arthur Eubanks via llvm-branch-commits]

Author: Arthur Eubanks
Date: 2021-01-06T11:42:03-08:00
New Revision: 54c01057b68d2a0e565f289cfa9edb8cca7f5980

URL: 
https://github.com/llvm/llvm-project/commit/54c01057b68d2a0e565f289cfa9edb8cca7f5980
DIFF: 
https://github.com/llvm/llvm-project/commit/54c01057b68d2a0e565f289cfa9edb8cca7f5980.diff

LOG: Fix non-assert builds after D93828

Added: 


Modified: 
llvm/lib/Analysis/LazyCallGraph.cpp

Removed: 




diff  --git a/llvm/lib/Analysis/LazyCallGraph.cpp 
b/llvm/lib/Analysis/LazyCallGraph.cpp
index beb8b7f0b1d8..ef16f94822a3 100644
--- a/llvm/lib/Analysis/LazyCallGraph.cpp
+++ b/llvm/lib/Analysis/LazyCallGraph.cpp
@@ -1791,8 +1791,8 @@ void LazyCallGraph::addSplitRefRecursiveFunctions(
   assert(!N1->lookup(N2)->isCall() &&
  "Edges between new functions must be ref edges");
 }
-#endif
   }
+#endif
 }
 
 LazyCallGraph::Node &LazyCallGraph::insertInto(Function &F, Node *&MappedN) {



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[llvm-branch-commits] [llvm] a515342 - [test] Pin AMDGPU/opt-pipeline.ll to legacy PM

[Arthur Eubanks via llvm-branch-commits]

Author: Arthur Eubanks
Date: 2021-01-06T11:44:16-08:00
New Revision: a515342de9c578ed2d9b5414be008ca4a876c903

URL: 
https://github.com/llvm/llvm-project/commit/a515342de9c578ed2d9b5414be008ca4a876c903
DIFF: 
https://github.com/llvm/llvm-project/commit/a515342de9c578ed2d9b5414be008ca4a876c903.diff

LOG: [test] Pin AMDGPU/opt-pipeline.ll to legacy PM

The pipeline being tested is specifically the legacy PM pipeline.

Added: 


Modified: 
llvm/test/CodeGen/AMDGPU/opt-pipeline.ll

Removed: 




diff  --git a/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll 
b/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll
index 8a8ce1e0c185..506ab37f8f66 100644
--- a/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll
@@ -1,7 +1,7 @@
-; RUN: opt -O0 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure %s 2>&1 | FileCheck -check-prefix=GCN-O0 %s
-; RUN: opt -O1 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure %s 2>&1 | FileCheck -check-prefix=GCN-O1 %s
-; RUN: opt -O2 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure %s 2>&1 | FileCheck -check-prefix=GCN-O2 %s
-; RUN: opt -O3 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure %s 2>&1 | FileCheck -check-prefix=GCN-O3 %s
+; RUN: opt -O0 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure -enable-new-pm=0 %s 2>&1 | FileCheck -check-prefix=GCN-O0 
%s
+; RUN: opt -O1 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure -enable-new-pm=0 %s 2>&1 | FileCheck -check-prefix=GCN-O1 
%s
+; RUN: opt -O2 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure -enable-new-pm=0 %s 2>&1 | FileCheck -check-prefix=GCN-O2 
%s
+; RUN: opt -O3 -mtriple=amdgcn--amdhsa -disable-output -disable-verify 
-debug-pass=Structure -enable-new-pm=0 %s 2>&1 | FileCheck -check-prefix=GCN-O3 
%s
 
 ; REQUIRES: asserts
 



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[llvm-branch-commits] [llvm] c68faed - [RISCV] Return a vXi1 vector type from getSetCCResultType if V extension is enabled.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-06T11:50:15-08:00
New Revision: c68faed041e664be5b289eae00ee4ca855ddf1c9

URL: 
https://github.com/llvm/llvm-project/commit/c68faed041e664be5b289eae00ee4ca855ddf1c9
DIFF: 
https://github.com/llvm/llvm-project/commit/c68faed041e664be5b289eae00ee4ca855ddf1c9.diff

LOG: [RISCV] Return a vXi1 vector type from getSetCCResultType if V extension 
is enabled.

nvxXi1 types are legal with V extension and that's the result
vmseq/vmsne/vmslt/etc instructions return.

No test cases yet because the setcc isel patterns aren't in
and we'll need more than basic tests to observe this. I locally
tested that this plus D947078, D94168, D94142, and D94149
was enough to be able to handle the overflow result from
llvm.sadd.overflow.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a097df996ad2..ba6548e48303 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -398,6 +398,8 @@ EVT RISCVTargetLowering::getSetCCResultType(const 
DataLayout &DL, LLVMContext &,
 EVT VT) const {
   if (!VT.isVector())
 return getPointerTy(DL);
+  if (Subtarget.hasStdExtV())
+return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
   return VT.changeVectorElementTypeToInteger();
 }
 



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[llvm-branch-commits] [llvm] 47fba9e - [test] Pin partial-unswitch.ll to legacy PM

[Arthur Eubanks via llvm-branch-commits]

Author: Arthur Eubanks
Date: 2021-01-06T11:53:07-08:00
New Revision: 47fba9e1eae63fa30c9f9a7d9ca42e694ba74b0a

URL: 
https://github.com/llvm/llvm-project/commit/47fba9e1eae63fa30c9f9a7d9ca42e694ba74b0a
DIFF: 
https://github.com/llvm/llvm-project/commit/47fba9e1eae63fa30c9f9a7d9ca42e694ba74b0a.diff

LOG: [test] Pin partial-unswitch.ll to legacy PM

The new PM does not have loop-unswitch, it only has simple-loop-unswitch.

Added: 


Modified: 
llvm/test/Transforms/LoopUnswitch/partial-unswitch.ll

Removed: 




diff  --git a/llvm/test/Transforms/LoopUnswitch/partial-unswitch.ll 
b/llvm/test/Transforms/LoopUnswitch/partial-unswitch.ll
index 742e35a99b5d..c7dcacbedd3a 100644
--- a/llvm/test/Transforms/LoopUnswitch/partial-unswitch.ll
+++ b/llvm/test/Transforms/LoopUnswitch/partial-unswitch.ll
@@ -1,4 +1,4 @@
-; RUN: opt -loop-unswitch -verify-dom-info -verify-memoryssa -S %s | FileCheck 
%s
+; RUN: opt -loop-unswitch -verify-dom-info -verify-memoryssa -S 
-enable-new-pm=0 %s | FileCheck %s
 
 declare void @clobber()
 



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[llvm-branch-commits] [clang-tools-extra] 0bfe100 - [NFC] Test case refactor

[Nathan James via llvm-branch-commits]

Author: Nathan James
Date: 2021-01-06T20:00:15Z
New Revision: 0bfe100145634988e4a914da776b55509ba0bec0

URL: 
https://github.com/llvm/llvm-project/commit/0bfe100145634988e4a914da776b55509ba0bec0
DIFF: 
https://github.com/llvm/llvm-project/commit/0bfe100145634988e4a914da776b55509ba0bec0.diff

LOG: [NFC] Test case refactor

Added: 


Modified: 
clang-tools-extra/clangd/unittests/TUSchedulerTests.cpp

Removed: 




diff  --git a/clang-tools-extra/clangd/unittests/TUSchedulerTests.cpp 
b/clang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
index a51067896432..c87c1be6f8e9 100644
--- a/clang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
+++ b/clang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
@@ -1042,7 +1042,7 @@ TEST_F(TUSchedulerTests, CommandLineWarnings) {
 
 TEST(DebouncePolicy, Compute) {
   namespace c = std::chrono;
-  std::vector History = {
+  DebouncePolicy::clock::duration History[] = {
   c::seconds(0),
   c::seconds(5),
   c::seconds(10),
@@ -1053,8 +1053,9 @@ TEST(DebouncePolicy, Compute) {
   Policy.Max = c::seconds(25);
   // Call Policy.compute(History) and return seconds as a float.
   auto Compute = [&](llvm::ArrayRef History) {
-using FloatingSeconds = c::duration;
-return static_cast(Policy.compute(History) / FloatingSeconds(1));
+return c::duration_cast>(
+   Policy.compute(History))
+.count();
   };
   EXPECT_NEAR(10, Compute(History), 0.01) << "(upper) median = 10";
   Policy.RebuildRatio = 1.5;



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[llvm-branch-commits] [llvm] 7d48eff - [PowerPC] Avoid call to undef in test (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-06T21:09:02+01:00
New Revision: 7d48eff8ba172216fca3649a3c452de4c7c16c00

URL: 
https://github.com/llvm/llvm-project/commit/7d48eff8ba172216fca3649a3c452de4c7c16c00
DIFF: 
https://github.com/llvm/llvm-project/commit/7d48eff8ba172216fca3649a3c452de4c7c16c00.diff

LOG: [PowerPC] Avoid call to undef in test (NFC)

Replace call to undef with a dummy function, to avoid affecting
this change by changes to call undef folding.

Added: 


Modified: 
llvm/test/CodeGen/PowerPC/spe.ll

Removed: 




diff  --git a/llvm/test/CodeGen/PowerPC/spe.ll 
b/llvm/test/CodeGen/PowerPC/spe.ll
index 1e4cecb1d136..94a8539aedde 100644
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -1425,48 +1425,53 @@ attributes #1 = { nounwind readnone speculatable 
willreturn }
 
 %struct.a = type { float, float }
 
+declare i32 @foo(double)
+
 define void @d(%struct.a* %e, %struct.a* %f) {
 ; CHECK-LABEL: d:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:mflr 0
 ; CHECK-NEXT:stw 0, 4(1)
-; CHECK-NEXT:stwu 1, -48(1)
-; CHECK-NEXT:.cfi_def_cfa_offset 48
+; CHECK-NEXT:stwu 1, -64(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 64
 ; CHECK-NEXT:.cfi_offset lr, 4
+; CHECK-NEXT:.cfi_offset r28, -16
 ; CHECK-NEXT:.cfi_offset r29, -12
 ; CHECK-NEXT:.cfi_offset r30, -8
+; CHECK-NEXT:.cfi_offset r28, -48
 ; CHECK-NEXT:.cfi_offset r29, -40
 ; CHECK-NEXT:.cfi_offset r30, -32
 ; CHECK-NEXT:lwz 4, 0(4)
 ; CHECK-NEXT:lwz 3, 0(3)
-; CHECK-NEXT:stw 29, 36(1) # 4-byte Folded Spill
-; CHECK-NEXT:evstdd 29, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT:stw 29, 52(1) # 4-byte Folded Spill
+; CHECK-NEXT:evstdd 29, 24(1) # 8-byte Folded Spill
 ; CHECK-NEXT:efdcfs 29, 4
-; CHECK-NEXT:stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT:stw 28, 48(1) # 4-byte Folded Spill
 ; CHECK-NEXT:mr 4, 29
-; CHECK-NEXT:evstdd 30, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT:stw 30, 56(1) # 4-byte Folded Spill
+; CHECK-NEXT:evstdd 28, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT:evstdd 30, 32(1) # 8-byte Folded Spill
 ; CHECK-NEXT:efdcfs 30, 3
 ; CHECK-NEXT:evmergehi 3, 29, 29
-; CHECK-NEXT:mtctr 3
 ; CHECK-NEXT:# kill: def $r3 killed $r3 killed $s3
-; CHECK-NEXT:bctrl
+; CHECK-NEXT:bl foo
+; CHECK-NEXT:mr 28, 3
 ; CHECK-NEXT:evmergehi 3, 30, 30
 ; CHECK-NEXT:mr 4, 30
-; CHECK-NEXT:mtctr 3
 ; CHECK-NEXT:# kill: def $r3 killed $r3 killed $s3
-; CHECK-NEXT:bctrl
-; CHECK-NEXT:li 3, .LCPI58_0@l
-; CHECK-NEXT:lis 4, .LCPI58_0@ha
-; CHECK-NEXT:evlddx 3, 4, 3
-; CHECK-NEXT:evldd 30, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:bl foo
+; CHECK-NEXT:efdcfsi 3, 28
+; CHECK-NEXT:evldd 30, 32(1) # 8-byte Folded Reload
 ; CHECK-NEXT:efdmul 3, 29, 3
-; CHECK-NEXT:evldd 29, 8(1) # 8-byte Folded Reload
 ; CHECK-NEXT:efscfd 3, 3
+; CHECK-NEXT:evldd 29, 24(1) # 8-byte Folded Reload
 ; CHECK-NEXT:stw 3, 0(3)
-; CHECK-NEXT:lwz 30, 40(1) # 4-byte Folded Reload
-; CHECK-NEXT:lwz 29, 36(1) # 4-byte Folded Reload
-; CHECK-NEXT:lwz 0, 52(1)
-; CHECK-NEXT:addi 1, 1, 48
+; CHECK-NEXT:evldd 28, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:lwz 30, 56(1) # 4-byte Folded Reload
+; CHECK-NEXT:lwz 29, 52(1) # 4-byte Folded Reload
+; CHECK-NEXT:lwz 28, 48(1) # 4-byte Folded Reload
+; CHECK-NEXT:lwz 0, 68(1)
+; CHECK-NEXT:addi 1, 1, 64
 ; CHECK-NEXT:mtlr 0
 ; CHECK-NEXT:blr
 entry:
@@ -1475,8 +1480,8 @@ entry:
   %conv = fpext float %1 to double
   %2 = load float, float* %0
   %g = fpext float %2 to double
-  %3 = call i32 undef(double %g)
-  %h = call i32 undef(double %conv)
+  %3 = call i32 @foo(double %g)
+  %h = call i32 @foo(double %conv)
   %n = sitofp i32 %3 to double
   %k = fmul double %g, %n
   %l = fptrunc double %k to float



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[llvm-branch-commits] [llvm] d042f2d - [InstSimplify] Fold call null/undef to poison

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-06T21:09:30+01:00
New Revision: d042f2db5bf0a852bdbef53ab0310d363031f56f

URL: 
https://github.com/llvm/llvm-project/commit/d042f2db5bf0a852bdbef53ab0310d363031f56f
DIFF: 
https://github.com/llvm/llvm-project/commit/d042f2db5bf0a852bdbef53ab0310d363031f56f.diff

LOG: [InstSimplify] Fold call null/undef to poison

Calling null or undef results in immediate undefined behavior.
Return poison instead of undef in this case, similar to what
we do for immediate UB due to division by zero.

Added: 


Modified: 
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/GVN/PRE/volatile.ll
llvm/test/Transforms/InstSimplify/call.ll
llvm/test/Transforms/InstSimplify/undef.ll

Removed: 




diff  --git a/llvm/lib/Analysis/InstructionSimplify.cpp 
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 1304f0e78b29..4de9085e8233 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -5690,11 +5690,11 @@ Value *llvm::SimplifyCall(CallBase *Call, const 
SimplifyQuery &Q) {
   if (Call->isMustTailCall())
 return nullptr;
 
-  // call undef -> undef
-  // call null -> undef
+  // call undef -> poison
+  // call null -> poison
   Value *Callee = Call->getCalledOperand();
   if (isa(Callee) || isa(Callee))
-return UndefValue::get(Call->getType());
+return PoisonValue::get(Call->getType());
 
   if (Value *V = tryConstantFoldCall(Call, Q))
 return V;

diff  --git a/llvm/test/Transforms/GVN/PRE/volatile.ll 
b/llvm/test/Transforms/GVN/PRE/volatile.ll
index fe417e38830f..1a51388723f1 100644
--- a/llvm/test/Transforms/GVN/PRE/volatile.ll
+++ b/llvm/test/Transforms/GVN/PRE/volatile.ll
@@ -204,7 +204,7 @@ define i32 @test9(i32* %V) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:[[LOAD:%.*]] = call i32 undef()
-; CHECK-NEXT:ret i32 undef
+; CHECK-NEXT:ret i32 poison
 ;
 entry:
   %load = call i32 undef()

diff  --git a/llvm/test/Transforms/InstSimplify/call.ll 
b/llvm/test/Transforms/InstSimplify/call.ll
index bb7410ada7d5..328626e4d1ce 100644
--- a/llvm/test/Transforms/InstSimplify/call.ll
+++ b/llvm/test/Transforms/InstSimplify/call.ll
@@ -454,7 +454,7 @@ define i32 @call_null() {
 ; CHECK-LABEL: @call_null(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:[[CALL:%.*]] = call i32 null()
-; CHECK-NEXT:ret i32 undef
+; CHECK-NEXT:ret i32 poison
 ;
 entry:
   %call = call i32 null()
@@ -465,7 +465,7 @@ define i32 @call_undef() {
 ; CHECK-LABEL: @call_undef(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:[[CALL:%.*]] = call i32 undef()
-; CHECK-NEXT:ret i32 undef
+; CHECK-NEXT:ret i32 poison
 ;
 entry:
   %call = call i32 undef()

diff  --git a/llvm/test/Transforms/InstSimplify/undef.ll 
b/llvm/test/Transforms/InstSimplify/undef.ll
index fe40f2ce319e..d09dc43da091 100644
--- a/llvm/test/Transforms/InstSimplify/undef.ll
+++ b/llvm/test/Transforms/InstSimplify/undef.ll
@@ -172,7 +172,7 @@ define i64 @test17(i64 %a) {
 define i64 @test18(i64 %a) {
 ; CHECK-LABEL: @test18(
 ; CHECK-NEXT:[[R:%.*]] = call i64 undef(i64 [[A:%.*]])
-; CHECK-NEXT:ret i64 undef
+; CHECK-NEXT:ret i64 poison
 ;
   %r = call i64 (i64) undef(i64 %a)
   ret i64 %r



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[llvm-branch-commits] [llvm] 221c3b1 - [InstSimplify] Canonicalize non-demanded shuffle op to poison (NFCI)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-06T21:22:27+01:00
New Revision: 221c3b174b15855ec941ef60a551f22ac96a254e

URL: 
https://github.com/llvm/llvm-project/commit/221c3b174b15855ec941ef60a551f22ac96a254e
DIFF: 
https://github.com/llvm/llvm-project/commit/221c3b174b15855ec941ef60a551f22ac96a254e.diff

LOG: [InstSimplify] Canonicalize non-demanded shuffle op to poison (NFCI)

I don't believe this has an observable effect, because the only
thing we care about here is replacing the operand with a constant
so following folds can apply. This change is just to make the
representation follow canonical unary shuffle form.

Added: 


Modified: 
llvm/lib/Analysis/InstructionSimplify.cpp

Removed: 




diff  --git a/llvm/lib/Analysis/InstructionSimplify.cpp 
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 4de9085e82330..5c251452e96d1 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4631,7 +4631,7 @@ static Value *SimplifyShuffleVectorInst(Value *Op0, Value 
*Op1,
   Indices.assign(Mask.begin(), Mask.end());
 
   // Canonicalization: If mask does not select elements from an input vector,
-  // replace that input vector with undef.
+  // replace that input vector with poison.
   if (!Scalable) {
 bool MaskSelects0 = false, MaskSelects1 = false;
 unsigned InVecNumElts = InVecEltCount.getKnownMinValue();
@@ -4644,9 +4644,9 @@ static Value *SimplifyShuffleVectorInst(Value *Op0, Value 
*Op1,
 MaskSelects1 = true;
 }
 if (!MaskSelects0)
-  Op0 = UndefValue::get(InVecTy);
+  Op0 = PoisonValue::get(InVecTy);
 if (!MaskSelects1)
-  Op1 = UndefValue::get(InVecTy);
+  Op1 = PoisonValue::get(InVecTy);
   }
 
   auto *Op0Const = dyn_cast(Op0);



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[llvm-branch-commits] [mlir] badc760 - [mlir] Remove a number of methods from mlir::OpState that just forward to mlir::Operation. All call sites have been converted in previous changes.

[Christian Sigg via llvm-branch-commits]

Author: Christian Sigg
Date: 2021-01-06T21:36:38+01:00
New Revision: badc7606b0f622f06efc466c86fecc8b45a165fd

URL: 
https://github.com/llvm/llvm-project/commit/badc7606b0f622f06efc466c86fecc8b45a165fd
DIFF: 
https://github.com/llvm/llvm-project/commit/badc7606b0f622f06efc466c86fecc8b45a165fd.diff

LOG: [mlir] Remove a number of methods from mlir::OpState that just forward to 
mlir::Operation. All call sites have been converted in previous changes.

Added: 


Modified: 
mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
mlir/test/lib/Dialect/Shape/TestShapeFunctions.cpp

Removed: 




diff  --git a/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp 
b/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
index 8721e6b96ed7..896fc411bcdd 100644
--- a/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
+++ b/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
@@ -334,7 +334,7 @@ class AffineYieldOpLowering : public 
OpRewritePattern {
 
   LogicalResult matchAndRewrite(AffineYieldOp op,
 PatternRewriter &rewriter) const override {
-if (isa(op.getParentOp())) {
+if (isa(op->getParentOp())) {
   // scf.parallel does not yield any values via its terminator scf.yield 
but
   // models reductions 
diff erently using additional ops in its region.
   rewriter.replaceOpWithNewOp(op);

diff  --git a/mlir/test/lib/Dialect/Shape/TestShapeFunctions.cpp 
b/mlir/test/lib/Dialect/Shape/TestShapeFunctions.cpp
index 4477eb1eda6d..a8851832d881 100644
--- a/mlir/test/lib/Dialect/Shape/TestShapeFunctions.cpp
+++ b/mlir/test/lib/Dialect/Shape/TestShapeFunctions.cpp
@@ -49,7 +49,7 @@ void ReportShapeFnPass::runOnOperation() {
 
   // Lookup shape function library.
   SmallVector libraries;
-  auto attr = module.getAttr("shape.lib");
+  auto attr = module->getAttr("shape.lib");
   if (attr) {
 auto lookup = [&](Attribute attr) {
   return cast(



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[llvm-branch-commits] [clang] 0e874fc - [OpenCL] Add clang extension for variadic functions.

[Anastasia Stulova via llvm-branch-commits]

Author: Anastasia Stulova
Date: 2021-01-06T20:39:57Z
New Revision: 0e874fc014be818a9c6782729f2c8e8273a7a906

URL: 
https://github.com/llvm/llvm-project/commit/0e874fc014be818a9c6782729f2c8e8273a7a906
DIFF: 
https://github.com/llvm/llvm-project/commit/0e874fc014be818a9c6782729f2c8e8273a7a906.diff

LOG: [OpenCL] Add clang extension for variadic functions.

With the internal clang extension '__cl_clang_variadic_functions'
variadic functions are accepted by the frontend.

This is not a fully supported vendor/Khronos extension
as it can only be used on targets with variadic prototype
support or in metaprogramming to represent functions with
generic prototype without calling such functions in the
kernel code.

Tags: #clang

Differential Revision: https://reviews.llvm.org/D94027

Added: 


Modified: 
clang/docs/LanguageExtensions.rst
clang/include/clang/Basic/OpenCLExtensions.def
clang/lib/Basic/Targets/AMDGPU.h
clang/lib/Basic/Targets/NVPTX.h
clang/lib/Sema/SemaType.cpp
clang/test/Misc/amdgcn.languageOptsOpenCL.cl
clang/test/Misc/nvptx.languageOptsOpenCL.cl
clang/test/Misc/r600.languageOptsOpenCL.cl
clang/test/SemaOpenCL/extension-version.cl
clang/test/SemaOpenCL/func.cl

Removed: 




diff  --git a/clang/docs/LanguageExtensions.rst 
b/clang/docs/LanguageExtensions.rst
index fd011b101b6e..0c01a2bbc52b 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -1773,6 +1773,31 @@ correctly in any circumstances. It can be used if:
 void (*fp)(); // error - pointers to function are not allowed
   }
 
+``__cl_clang_variadic_functions``
+-
+
+With this extension it is possible to enable variadic arguments in functions
+using regular OpenCL extension pragma mechanism detailed in `the OpenCL
+Extension Specification, section 1.2
+`_.
+
+This is not conformant behavior and it can only be used portably when the
+functions with variadic prototypes do not get generated in binary e.g. the
+variadic prototype is used to spesify a function type with any number of
+arguments in metaprogramming algorithms in C++ for OpenCL.
+
+This extensions can also be used when the kernel code is intended for targets
+supporting the variadic arguments e.g. majority of CPU targets.
+
+**Example of Use**:
+
+.. code-block:: c++
+
+  #pragma OPENCL EXTENSION __cl_clang_variadic_functions : enable
+  void foo(int a, ...); // compiled - no diagnostic generated
+
+  #pragma OPENCL EXTENSION __cl_clang_variadic_functions : disable
+  void bar(int a, ...); // error - variadic prototype is not allowed
 
 Builtin Functions
 =

diff  --git a/clang/include/clang/Basic/OpenCLExtensions.def 
b/clang/include/clang/Basic/OpenCLExtensions.def
index 149594ed40b0..9353be1753b0 100644
--- a/clang/include/clang/Basic/OpenCLExtensions.def
+++ b/clang/include/clang/Basic/OpenCLExtensions.def
@@ -70,6 +70,7 @@ OPENCLEXT_INTERNAL(cl_khr_subgroups, 200, ~0U)
 // Clang Extensions.
 OPENCLEXT_INTERNAL(cl_clang_storage_class_specifiers, 100, ~0U)
 OPENCLEXT_INTERNAL(__cl_clang_function_pointers, 100, ~0U)
+OPENCLEXT_INTERNAL(__cl_clang_variadic_functions, 100, ~0U)
 
 // AMD OpenCL extensions
 OPENCLEXT_INTERNAL(cl_amd_media_ops, 100, ~0U)

diff  --git a/clang/lib/Basic/Targets/AMDGPU.h 
b/clang/lib/Basic/Targets/AMDGPU.h
index 3fdbf320a329..fba1e4288ed1 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -286,6 +286,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : 
public TargetInfo {
 auto &Opts = getSupportedOpenCLOpts();
 Opts.support("cl_clang_storage_class_specifiers");
 Opts.support("__cl_clang_function_pointers");
+Opts.support("__cl_clang_variadic_functions");
 
 bool IsAMDGCN = isAMDGCN(getTriple());
 

diff  --git a/clang/lib/Basic/Targets/NVPTX.h b/clang/lib/Basic/Targets/NVPTX.h
index 8e0da6554708..c4320e86e0db 100644
--- a/clang/lib/Basic/Targets/NVPTX.h
+++ b/clang/lib/Basic/Targets/NVPTX.h
@@ -129,6 +129,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public 
TargetInfo {
 auto &Opts = getSupportedOpenCLOpts();
 Opts.support("cl_clang_storage_class_specifiers");
 Opts.support("__cl_clang_function_pointers");
+Opts.support("__cl_clang_variadic_functions");
 
 Opts.support("cl_khr_fp64");
 Opts.support("cl_khr_byte_addressable_store");

diff  --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index 31018dc1d0e7..f51c616169f5 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -5019,6 +5019,7 @@ static TypeSourceInfo 
*GetFullTypeForDeclarator(TypeProcessingState &state,
 // (s6.9.e and s6.12.5 OpenCL v2.0) except for printf.
 // We also allow here any toolchain reserved identifiers.
 if (FTI.

[llvm-branch-commits] [clang] 4fde2b6 - [OpenCL] Add clang extension for function pointers.

[Anastasia Stulova via llvm-branch-commits]

Author: Anastasia Stulova
Date: 2021-01-06T20:39:57Z
New Revision: 4fde2b6a0c080cb2a598383b5850038d67ca6833

URL: 
https://github.com/llvm/llvm-project/commit/4fde2b6a0c080cb2a598383b5850038d67ca6833
DIFF: 
https://github.com/llvm/llvm-project/commit/4fde2b6a0c080cb2a598383b5850038d67ca6833.diff

LOG: [OpenCL] Add clang extension for function pointers.

The new clang internal extension '__cl_clang_function_pointers'
allows use of function pointers and other features that have
the same functionality:
- Use of member function pointers;
- Unrestricted use of references to functions;
- Virtual member functions.

This not a vendor extension and therefore it doesn't require any
special target support. Exposing this functionality fully
will require vendor or Khronos extension.

Tags: #clang

Differential Revision: https://reviews.llvm.org/D94021

Added: 


Modified: 
clang/docs/LanguageExtensions.rst
clang/include/clang/Basic/OpenCLExtensions.def
clang/lib/Basic/Targets/AMDGPU.h
clang/lib/Basic/Targets/NVPTX.h
clang/lib/Parse/ParseDecl.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaType.cpp
clang/test/Misc/amdgcn.languageOptsOpenCL.cl
clang/test/Misc/nvptx.languageOptsOpenCL.cl
clang/test/Misc/r600.languageOptsOpenCL.cl
clang/test/Parser/opencl-cxx-virtual.cl
clang/test/SemaOpenCL/extension-version.cl
clang/test/SemaOpenCL/func.cl
clang/test/SemaOpenCLCXX/members.cl

Removed: 




diff  --git a/clang/docs/LanguageExtensions.rst 
b/clang/docs/LanguageExtensions.rst
index 6280c486ccbb..fd011b101b6e 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -1722,6 +1722,58 @@ syntax to be used with ``std::complex`` with the same 
meaning.)
 For GCC compatibility, ``__builtin_complex(re, im)`` can also be used to
 construct a complex number from the given real and imaginary components.
 
+OpenCL Features
+===
+
+Clang supports internal OpenCL extensions documented below.
+
+``__cl_clang_function_pointers``
+
+
+With this extension it is possible to enable various language features that
+are relying on function pointers using regular OpenCL extension pragma
+mechanism detailed in `the OpenCL Extension Specification,
+section 1.2
+`_.
+
+In C++ for OpenCL this also enables:
+
+- Use of member function pointers;
+
+- Unrestricted use of references to functions;
+
+- Virtual member functions.
+
+Such functionality is not conformant and does not guarantee to compile
+correctly in any circumstances. It can be used if:
+
+- the kernel source does not contain call expressions to (member-) function
+  pointers, or virtual functions. For example this extension can be used in
+  metaprogramming algorithms to be able to specify/detect types generically.
+
+- the generated kernel binary does not contain indirect calls because they
+  are eliminated using compiler optimizations e.g. devirtualization. 
+
+- the selected target supports the function pointer like functionality e.g.
+  most CPU targets.
+
+**Example of Use**:
+
+.. code-block:: c++
+
+  #pragma OPENCL EXTENSION __cl_clang_function_pointers : enable
+  void foo()
+  {
+void (*fp)(); // compiled - no diagnostic generated
+  }
+
+  #pragma OPENCL EXTENSION __cl_clang_function_pointers : disable
+  void bar()
+  {
+void (*fp)(); // error - pointers to function are not allowed
+  }
+
+
 Builtin Functions
 =
 

diff  --git a/clang/include/clang/Basic/OpenCLExtensions.def 
b/clang/include/clang/Basic/OpenCLExtensions.def
index 17d402f300f1..149594ed40b0 100644
--- a/clang/include/clang/Basic/OpenCLExtensions.def
+++ b/clang/include/clang/Basic/OpenCLExtensions.def
@@ -69,6 +69,7 @@ OPENCLEXT_INTERNAL(cl_khr_subgroups, 200, ~0U)
 
 // Clang Extensions.
 OPENCLEXT_INTERNAL(cl_clang_storage_class_specifiers, 100, ~0U)
+OPENCLEXT_INTERNAL(__cl_clang_function_pointers, 100, ~0U)
 
 // AMD OpenCL extensions
 OPENCLEXT_INTERNAL(cl_amd_media_ops, 100, ~0U)

diff  --git a/clang/lib/Basic/Targets/AMDGPU.h 
b/clang/lib/Basic/Targets/AMDGPU.h
index 8b3f30ed70e9..3fdbf320a329 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -285,6 +285,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : 
public TargetInfo {
   void setSupportedOpenCLOpts() override {
 auto &Opts = getSupportedOpenCLOpts();
 Opts.support("cl_clang_storage_class_specifiers");
+Opts.support("__cl_clang_function_pointers");
 
 bool IsAMDGCN = isAMDGCN(getTriple());
 

diff  --git a/clang/lib/Basic/Targets/NVPTX.h b/clang/lib/Basic/Targets/NVPTX.h
index f8d0afdcceae..8e0da6554708 100644
--- a/clang/lib/Basic/Targets/NVPTX.h
+++ b/clang/lib/Basic/Targets/NVPTX.h
@@ -128,6 +128,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXTarget

[llvm-branch-commits] [llvm] f6f6f63 - [BasicAA] Fix BatchAA results for phi-phi assumptions

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-06T22:15:30+01:00
New Revision: f6f6f6375d1a4bced8a6e79a78726ab32b8dd879

URL: 
https://github.com/llvm/llvm-project/commit/f6f6f6375d1a4bced8a6e79a78726ab32b8dd879
DIFF: 
https://github.com/llvm/llvm-project/commit/f6f6f6375d1a4bced8a6e79a78726ab32b8dd879.diff

LOG: [BasicAA] Fix BatchAA results for phi-phi assumptions

Change the way NoAlias assumptions in BasicAA are handled. Instead of
handling this inside the phi-phi code, always initially insert a
NoAlias result into the map and keep track whether it is used.
If it is used, then we require that we also get back NoAlias from
the recursive queries. Otherwise, the entry is changed to MayAlias.

Additionally, keep track of all location pairs we inserted that may
still be based on assumptions higher up. If it turns out one of those
assumptions is incorrect, we flush them from the cache.

The compile-time impact for the new implementation is significantly
higher than the previous iteration of this patch:
https://llvm-compile-time-tracker.com/compare.php?from=c0bb9859de6991cc233e2dedb978dd118da8c382&to=c07112373279143e37568b5bcd293daf81a35973&stat=instructions
However, it should avoid the exponential runtime cases we run into
if we don't cache assumption-based results entirely.

This also produces better results in some cases, because NoAlias
assumptions can now start at any root, rather than just phi-phi pairs.
This is not just relevant for analysis quality, but also for BatchAA
consistency: Otherwise, results would once again depend on query order,
though at least they wouldn't be wrong.

This ended up both more complicated and more expensive than I hoped,
but I wasn't able to come up with another solution that satisfies all
the constraints.

Differential Revision: https://reviews.llvm.org/D91936

Added: 


Modified: 
llvm/include/llvm/Analysis/AliasAnalysis.h
llvm/include/llvm/Analysis/BasicAliasAnalysis.h
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/test/Analysis/BasicAA/phi-speculation.ll
llvm/unittests/Analysis/AliasAnalysisTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/Analysis/AliasAnalysis.h 
b/llvm/include/llvm/Analysis/AliasAnalysis.h
index 98a2a7fb075a..8a3ea62ff154 100644
--- a/llvm/include/llvm/Analysis/AliasAnalysis.h
+++ b/llvm/include/llvm/Analysis/AliasAnalysis.h
@@ -346,19 +346,21 @@ createModRefInfo(const FunctionModRefBehavior FMRB) {
 class AAQueryInfo {
 public:
   using LocPair = std::pair;
-  using AliasCacheT = SmallDenseMap;
+  struct CacheEntry {
+AliasResult Result;
+/// Number of times a NoAlias assumption has been used.
+/// 0 for assumptions that have not been used, -1 for definitive results.
+int NumAssumptionUses;
+/// Whether this is a definitive (non-assumption) result.
+bool isDefinitive() const { return NumAssumptionUses < 0; }
+  };
+  using AliasCacheT = SmallDenseMap;
   AliasCacheT AliasCache;
 
   using IsCapturedCacheT = SmallDenseMap;
   IsCapturedCacheT IsCapturedCache;
 
   AAQueryInfo() : AliasCache(), IsCapturedCache() {}
-
-  AliasResult updateResult(const LocPair &Locs, AliasResult Result) {
-auto It = AliasCache.find(Locs);
-assert(It != AliasCache.end() && "Entry must have existed");
-return It->second = Result;
-  }
 };
 
 class BatchAAResults;

diff  --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h 
b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
index cffe9ed3c738..635c35585f81 100644
--- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
+++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
@@ -190,6 +190,14 @@ class BasicAAResult : public AAResultBase {
   /// Tracks instructions visited by pointsToConstantMemory.
   SmallPtrSet Visited;
 
+  /// How many active NoAlias assumption uses there are.
+  int NumAssumptionUses = 0;
+
+  /// Location pairs for which an assumption based result is currently stored.
+  /// Used to remove all potentially incorrect results from the cache if an
+  /// assumption is disproven.
+  SmallVector AssumptionBasedResults;
+
   static const Value *
   GetLinearExpression(const Value *V, APInt &Scale, APInt &Offset,
   unsigned &ZExtBits, unsigned &SExtBits,
@@ -244,6 +252,12 @@ class BasicAAResult : public AAResultBase {
  LocationSize V2Size, const AAMDNodes &V2AATag,
  AAQueryInfo &AAQI, const Value *O1 = nullptr,
  const Value *O2 = nullptr);
+
+  AliasResult aliasCheckRecursive(const Value *V1, LocationSize V1Size,
+  const AAMDNodes &V1AATag, const Value *V2,
+  LocationSize V2Size, const AAMDNodes 
&V2AATag,
+  AAQueryInfo &AAQI, const Value *O1,
+  const Value *O2);
 };
 
 /// Analysis pass providing a never-invalidated alias analysis result.

diff  --git

[llvm-branch-commits] [clang] 90bf3ec - [clang-offload-bundler] Add option -list

[Yaxun Liu via llvm-branch-commits]

Author: Yaxun (Sam) Liu
Date: 2021-01-06T16:23:01-05:00
New Revision: 90bf3ecef4bb1e214a718aebcee730c24199c8ba

URL: 
https://github.com/llvm/llvm-project/commit/90bf3ecef4bb1e214a718aebcee730c24199c8ba
DIFF: 
https://github.com/llvm/llvm-project/commit/90bf3ecef4bb1e214a718aebcee730c24199c8ba.diff

LOG: [clang-offload-bundler] Add option -list

clang-offload-bundler is not only used by clang driver
to bundle/unbundle files for offloading toolchains,
but also used by out of tree tools to unbundle
fat binaries generated by clang. It is important
to be able to list the bundle IDs in a bundled
file so that the bundles can be extracted.

This patch adds an option -list to list bundle
ID's in a bundled file. Each bundle ID is separated
by new line. If the file is not a bundled file
nothing is output and returns 0.

Differential Revision: https://reviews.llvm.org/D92954

Added: 


Modified: 
clang/test/Driver/clang-offload-bundler.c
clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp

Removed: 




diff  --git a/clang/test/Driver/clang-offload-bundler.c 
b/clang/test/Driver/clang-offload-bundler.c
index b4bab6bbd1e8..3e1fab25d754 100644
--- a/clang/test/Driver/clang-offload-bundler.c
+++ b/clang/test/Driver/clang-offload-bundler.c
@@ -35,6 +35,7 @@
 // CK-HELP: {{.*}}USAGE: clang-offload-bundler [options]
 // CK-HELP: {{.*}}-allow-missing-bundles {{.*}}- Create empty files if bundles 
are missing when unbundling
 // CK-HELP: {{.*}}-inputs=  - [,...]
+// CK-HELP: {{.*}}-list {{.*}}- List bundle IDs in the bundled file.
 // CK-HELP: {{.*}}-outputs= - [,...]
 // CK-HELP: {{.*}}-targets= - [-,...]
 // CK-HELP: {{.*}}-type=- Type of the files to be 
bundled/unbundled.
@@ -54,7 +55,9 @@
 //
 // RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu
 -inputs=%t.i,%t.tgt1,%t.tgt2 -outputs=%t.bundle.i -unbundle 2>&1 | FileCheck 
%s --check-prefix CK-ERR1
 // CK-ERR1: error: only one input file supported in unbundling mode
-// CK-ERR1: error: number of output files and targets should match in 
unbundling mode
+
+// RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu
 -inputs=%t.i -outputs=%t.bundle.i -unbundle 2>&1 | FileCheck %s --check-prefix 
CK-ERR1A
+// CK-ERR1A: error: number of output files and targets should match in 
unbundling mode
 
 // RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu 
-inputs=%t.i,%t.tgt1,%t.tgt2 -outputs=%t.bundle.i 2>&1 | FileCheck %s 
--check-prefix CK-ERR2
 // RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu
 -inputs=%t.i,%t.tgt1 -outputs=%t.bundle.i 2>&1 | FileCheck %s --check-prefix 
CK-ERR2
@@ -62,7 +65,6 @@
 
 // RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu
 -outputs=%t.i,%t.tgt1,%t.tgt2 -inputs=%t.bundle.i 2>&1 | FileCheck %s 
--check-prefix CK-ERR3
 // CK-ERR3: error: only one output file supported in bundling mode
-// CK-ERR3: error: number of input files and targets should match in bundling 
mode
 
 // RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu 
-outputs=%t.i,%t.tgt1,%t.tgt2 -inputs=%t.bundle.i -unbundle 2>&1 | FileCheck %s 
--check-prefix CK-ERR4
 // RUN: not clang-offload-bundler -type=i 
-targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu
 -outputs=%t.i,%t.tgt1 -inputs=%t.bundle.i -unbundle 2>&1 | FileCheck %s 
--check-prefix CK-ERR4
@@ -76,19 +78,27 @@
 // CK-ERR6: error: '[[TYPE]]': invalid file type specified
 
 // RUN: not clang-offload-bundler 2>&1 | FileCheck %s --check-prefix CK-ERR7
-// CK-ERR7-DAG: clang-offload-bundler: for the --type option: must be 
specified at least once!
-// CK-ERR7-DAG: clang-offload-bundler: for the --inputs option: must be 
specified at least once!
-// CK-ERR7-DAG: clang-offload-bundler: for the --outputs option: must be 
specified at least once!
-// CK-ERR7-DAG: clang-offload-bundler: for the --targets option: must be 
specified at least once!
+// CK-ERR7: clang-offload-bundler: for the --type option: must be specified at 
least once!
+
+// RUN: not clang-offload-bundler -type=i -inputs=%t.i,%t.tgt1,%t.tgt2 2>&1 | 
FileCheck %s -check-prefix=CK-ERR7A
+// CK-ERR7A: error: for the --outputs option: must be specified at least once!
+
+// RUN: not clang-offload-bundler -type=i -inputs=%t.i,%t.tgt1,%t.tgt2 
-outputs=%t.bundle.i 2>&1 | FileCheck %s -check-prefix=CK-ERR7B
+// CK-ERR7B: error: for the --targets option: must be specified at least once!
 
 // RUN: not clang-offload-bundler -type=i 
-targets=hxst-powerpcxxle-ibm-linux-gnu,openxp-pxxerpc64le-ib

[llvm-branch-commits] [mlir] f9190c8 - [mlir][vector] Support unrolling for transfer ops using tensors

[Thomas Raoux via llvm-branch-commits]

Author: Thomas Raoux
Date: 2021-01-06T13:28:04-08:00
New Revision: f9190c868137dcf43833db2c8e1e00c7acca67bc

URL: 
https://github.com/llvm/llvm-project/commit/f9190c868137dcf43833db2c8e1e00c7acca67bc
DIFF: 
https://github.com/llvm/llvm-project/commit/f9190c868137dcf43833db2c8e1e00c7acca67bc.diff

LOG: [mlir][vector] Support unrolling for transfer ops using tensors

Differential Revision: https://reviews.llvm.org/D93904

Added: 


Modified: 
mlir/include/mlir/Dialect/Vector/VectorTransforms.h
mlir/lib/Dialect/Vector/VectorTransforms.cpp
mlir/test/Dialect/Vector/vector-transfer-unroll.mlir
mlir/test/Dialect/Vector/vector-transforms.mlir
mlir/test/lib/Transforms/TestVectorTransforms.cpp

Removed: 




diff  --git a/mlir/include/mlir/Dialect/Vector/VectorTransforms.h 
b/mlir/include/mlir/Dialect/Vector/VectorTransforms.h
index c88aa7f5bc65..a258903d5a3a 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorTransforms.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorTransforms.h
@@ -71,7 +71,8 @@ SmallVector unrollSingleResultVectorOp(OpBuilder 
&builder,
 
 /// Unroll a transfer_write op. Break up the vector source into a tuple of
 /// vectors matching the given shape. Then store each element with its own
-/// transfer_write.
+/// transfer_write. If the transfer_write takes a tensor source, return the
+/// unrolled Value in result.
 ///
 /// Example:
 /// vector.transfer_write %A, %M[%c0, %c0] : vector<4x4xf32>, memref<4x4xf32>
@@ -83,7 +84,8 @@ SmallVector unrollSingleResultVectorOp(OpBuilder 
&builder,
 /// %2 = vector.tuple_get %0, 1 : tuple, vector<2x4xf32>>
 /// vector.transfer_write %2, %M[%c2, %c0] : vector<2x4xf32>, memref<4x4xf32>
 LogicalResult unrollTransferWriteOp(OpBuilder &builder, Operation *op,
-ArrayRef targetShape);
+ArrayRef targetShape,
+SmallVector &result);
 
 /// Options that control the vector unrolling.
 struct UnrollVectorOptions {
@@ -143,9 +145,10 @@ struct UnrollVectorPattern : public RewritePattern {
 llvm::all_of(*maybeShapeRatio, [](int64_t v) { return v == 1; }))
   return failure();
 if (isa(op)) {
-  if (failed(unrollTransferWriteOp(rewriter, op, *targetShape)))
+  SmallVector result;
+  if (failed(unrollTransferWriteOp(rewriter, op, *targetShape, result)))
 return failure();
-  rewriter.eraseOp(op);
+  rewriter.replaceOp(op, result);
   return success();
 }
 if (op->getNumResults() != 1)

diff  --git a/mlir/lib/Dialect/Vector/VectorTransforms.cpp 
b/mlir/lib/Dialect/Vector/VectorTransforms.cpp
index f1708db113d4..ca6e92d95ed0 100644
--- a/mlir/lib/Dialect/Vector/VectorTransforms.cpp
+++ b/mlir/lib/Dialect/Vector/VectorTransforms.cpp
@@ -515,7 +515,7 @@ static void getVectorElementwiseOpUnrollState(Operation *op,
 /// Generates slices of 'vectorType' according to 'sizes' and 'strides, and
 /// calls 'fn' with linear index and indices for each slice.
 static void generateTransferOpSlices(
-Type memrefElementType, VectorType vectorType, TupleType tupleType,
+Type shapedElementType, VectorType vectorType, TupleType tupleType,
 ArrayRef sizes, ArrayRef strides, ArrayRef 
indices,
 OpBuilder &builder, function_ref)> fn) {
   // Compute strides w.r.t. to slice counts in each dimension.
@@ -539,9 +539,9 @@ static void generateTransferOpSlices(
   //   vector rank is 4 - 2 = 2, and so 'indexOffset' = 3 - 2 = 1.
   //
   unsigned vectorRank = vectorType.getRank();
-  if (auto memrefVectorElementType = memrefElementType.dyn_cast()) 
{
-assert(vectorRank >= memrefVectorElementType.getRank());
-vectorRank -= memrefVectorElementType.getRank();
+  if (auto sourceVectorElementType = shapedElementType.dyn_cast()) 
{
+assert(vectorRank >= sourceVectorElementType.getRank());
+vectorRank -= sourceVectorElementType.getRank();
   }
   unsigned indexOffset = numSliceIndices - vectorRank;
 
@@ -598,8 +598,8 @@ static Value unrollTransferReadOp(vector::TransferReadOp 
readOp,
   SmallVector strides(targetShape.size(), 1);
 
   Location loc = readOp.getLoc();
-  auto memrefElementType =
-  readOp.source().getType().cast().getElementType();
+  auto shapedElementType =
+  readOp.source().getType().cast().getElementType();
   auto tupleType = generateExtractSlicesOpResultType(
   sourceVectorType, targetShape, strides, builder);
   int64_t numSlices = tupleType.size();
@@ -618,7 +618,7 @@ static Value unrollTransferReadOp(vector::TransferReadOp 
readOp,
 readOp.permutation_map(), readOp.padding(),
 readOp.masked() ? *readOp.masked() : ArrayAttr());
   };
-  generateTransferOpSlices(memrefElementType, sourceVectorType, tupleType,
+  generateTransferOpSlices(shapedElementType, sourceVectorType, tupleType,
targetShape, strides, indices, builder, 
createSli

[llvm-branch-commits] [clang] 2a29ce3 - [hip] Fix HIP version parsing.

[Michael Liao via llvm-branch-commits]

Author: Michael Liao
Date: 2021-01-06T17:00:14-05:00
New Revision: 2a29ce303451375bbf1de7c971296553ef5d9beb

URL: 
https://github.com/llvm/llvm-project/commit/2a29ce303451375bbf1de7c971296553ef5d9beb
DIFF: 
https://github.com/llvm/llvm-project/commit/2a29ce303451375bbf1de7c971296553ef5d9beb.diff

LOG: [hip] Fix HIP version parsing.

- Need trimming before parsing major or minor version numbers. This's required
  due to the different line ending on Windows.
- In addition, the integer conversion may fail due to invalid char. Return that
  parsing function return `true` when the parsing fails.

Differential Revision: https://reviews.llvm.org/D93587

Added: 


Modified: 
clang/lib/Driver/ToolChains/AMDGPU.cpp
clang/lib/Driver/ToolChains/ROCm.h
clang/test/Driver/Inputs/rocm/bin/.hipVersion

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp 
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 565a77e07fd8..0971a2da62a3 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -88,23 +88,30 @@ void 
RocmInstallationDetector::scanLibDevicePath(llvm::StringRef Path) {
   }
 }
 
-void RocmInstallationDetector::ParseHIPVersionFile(llvm::StringRef V) {
+// Parse and extract version numbers from `.hipVersion`. Return `true` if
+// the parsing fails.
+bool RocmInstallationDetector::parseHIPVersionFile(llvm::StringRef V) {
   SmallVector VersionParts;
   V.split(VersionParts, '\n');
-  unsigned Major;
-  unsigned Minor;
+  unsigned Major = ~0U;
+  unsigned Minor = ~0U;
   for (auto Part : VersionParts) {
-auto Splits = Part.split('=');
-if (Splits.first == "HIP_VERSION_MAJOR")
-  Splits.second.getAsInteger(0, Major);
-else if (Splits.first == "HIP_VERSION_MINOR")
-  Splits.second.getAsInteger(0, Minor);
-else if (Splits.first == "HIP_VERSION_PATCH")
+auto Splits = Part.rtrim().split('=');
+if (Splits.first == "HIP_VERSION_MAJOR") {
+  if (Splits.second.getAsInteger(0, Major))
+return true;
+} else if (Splits.first == "HIP_VERSION_MINOR") {
+  if (Splits.second.getAsInteger(0, Minor))
+return true;
+} else if (Splits.first == "HIP_VERSION_PATCH")
   VersionPatch = Splits.second.str();
   }
+  if (Major == ~0U || Minor == ~0U)
+return true;
   VersionMajorMinor = llvm::VersionTuple(Major, Minor);
   DetectedVersion =
   (Twine(Major) + "." + Twine(Minor) + "." + VersionPatch).str();
+  return false;
 }
 
 // For candidate specified by --rocm-path we do not do strict check.
@@ -290,7 +297,8 @@ void RocmInstallationDetector::detectHIPRuntime() {
   continue;
 
 if (HIPVersionArg.empty() && VersionFile)
-  ParseHIPVersionFile((*VersionFile)->getBuffer());
+  if (parseHIPVersionFile((*VersionFile)->getBuffer()))
+continue;
 
 HasHIPRuntime = true;
 return;

diff  --git a/clang/lib/Driver/ToolChains/ROCm.h 
b/clang/lib/Driver/ToolChains/ROCm.h
index 27c7d8b0ee54..21e62a465d7b 100644
--- a/clang/lib/Driver/ToolChains/ROCm.h
+++ b/clang/lib/Driver/ToolChains/ROCm.h
@@ -103,7 +103,7 @@ class RocmInstallationDetector {
   }
 
   void scanLibDevicePath(llvm::StringRef Path);
-  void ParseHIPVersionFile(llvm::StringRef V);
+  bool parseHIPVersionFile(llvm::StringRef V);
   SmallVector getInstallationPathCandidates();
 
 public:

diff  --git a/clang/test/Driver/Inputs/rocm/bin/.hipVersion 
b/clang/test/Driver/Inputs/rocm/bin/.hipVersion
index 48ee6f10c3e4..677293c09139 100644
--- a/clang/test/Driver/Inputs/rocm/bin/.hipVersion
+++ b/clang/test/Driver/Inputs/rocm/bin/.hipVersion
@@ -1,4 +1,6 @@
 # Auto-generated by cmake
-HIP_VERSION_MAJOR=3
+# NOTE: The trailing whitespace is added on purpose to verify that these
+# whitespaces are trimmed before paring.
+HIP_VERSION_MAJOR=3 
 HIP_VERSION_MINOR=6
 HIP_VERSION_PATCH=20214-a2917cd



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[llvm-branch-commits] [openmp] e2a6230 - [OpenMP] Fixed the test environment when building along with LLVM

[Shilei Tian via llvm-branch-commits]

Author: Shilei Tian
Date: 2021-01-06T17:06:16-05:00
New Revision: e2a623094f6bc1b01f9661043b3df908ca1bd037

URL: 
https://github.com/llvm/llvm-project/commit/e2a623094f6bc1b01f9661043b3df908ca1bd037
DIFF: 
https://github.com/llvm/llvm-project/commit/e2a623094f6bc1b01f9661043b3df908ca1bd037.diff

LOG: [OpenMP] Fixed the test environment when building along with LLVM

Currently all built libraries in OpenMP are anywhere if building along
with LLVM. It is not an issue if we don't execute any test. However, almost all
tests for `libomptarget` fails because in the lit configuration, we only set
`/libomptarget` to `LD_LIBRARY_PATH` and `LIBRARY_PATH`. Since those
libraries are everywhere, `clang` can no longer find `libomptarget.so` or those
deviceRTLs anymore.

In this patch, we set a unified path for all built libraries, no matter whether
it is built along with LLVM or not. In this way, our lit configuration can work
propoerly.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D93736

Added: 


Modified: 
openmp/libomptarget/CMakeLists.txt
openmp/libomptarget/src/CMakeLists.txt

Removed: 




diff  --git a/openmp/libomptarget/CMakeLists.txt 
b/openmp/libomptarget/CMakeLists.txt
index 4d6ebb4381bc..06db7b4c35e2 100644
--- a/openmp/libomptarget/CMakeLists.txt
+++ b/openmp/libomptarget/CMakeLists.txt
@@ -1,9 +1,9 @@
 
##===--===##
-# 
+#
 # Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-# 
+#
 
##===--===##
 #
 # Build offloading library and related plugins.
@@ -17,11 +17,12 @@ endif()
 # Add cmake directory to search for custom cmake functions.
 set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake/Modules 
${CMAKE_MODULE_PATH})
 
-if(OPENMP_STANDALONE_BUILD)
-  # Build all libraries into a common place so that tests can find them.
-  set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
-  set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
-endif()
+# Set the path of all resulting libraries to a unified location so that it can
+# be used for testing.
+set(LIBOMPTARGET_LIBRARY_DIR ${CMAKE_CURRENT_BINARY_DIR})
+set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR})
+set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR})
+set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR})
 
 # Message utilities.
 include(LibomptargetUtils)
@@ -66,13 +67,6 @@ include_directories(${LIBOMPTARGET_INCLUDE_DIR})
 set(LIBOMPTARGET_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/src)
 add_subdirectory(${LIBOMPTARGET_SRC_DIR})
 
-# Retrieve the path to the resulting library so that it can be used for 
-# testing.
-get_target_property(LIBOMPTARGET_LIBRARY_DIR omptarget 
LIBRARY_OUTPUT_DIRECTORY)
-if(NOT LIBOMPTARGET_LIBRARY_DIR)
-  set(LIBOMPTARGET_LIBRARY_DIR ${CMAKE_CURRENT_BINARY_DIR})
-endif()
-
 # Definitions for testing, for reuse when testing libomptarget-nvptx.
 if(OPENMP_STANDALONE_BUILD)
   set(LIBOMPTARGET_OPENMP_HEADER_FOLDER 
"${CMAKE_CURRENT_BINARY_DIR}/../runtime/src" CACHE STRING

diff  --git a/openmp/libomptarget/src/CMakeLists.txt 
b/openmp/libomptarget/src/CMakeLists.txt
index 894b5ec6f21b..35ff4ed549cc 100644
--- a/openmp/libomptarget/src/CMakeLists.txt
+++ b/openmp/libomptarget/src/CMakeLists.txt
@@ -39,6 +39,12 @@ else()
   target_compile_definitions(omptarget PUBLIC OMPTARGET_PROFILE_ENABLED)
 endif()
 
+# libomptarget needs to be set separately because add_llvm_library doesn't
+# conform with location configuration of its parent scope.
+set_target_properties(omptarget
+  PROPERTIES
+  LIBRARY_OUTPUT_DIRECTORY ${LIBOMPTARGET_LIBRARY_DIR})
+
 # Install libomptarget under the lib destination folder.
 install(TARGETS omptarget LIBRARY COMPONENT omptarget
   DESTINATION "${OPENMP_INSTALL_LIBDIR}")



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[llvm-branch-commits] [openmp] 5acdae1 - [OpenMP] Fixed an issue that wrong LLVM headers might be included when building libomptarget

[Shilei Tian via llvm-branch-commits]

Author: Shilei Tian
Date: 2021-01-06T17:07:36-05:00
New Revision: 5acdae1f9a772e16850b0ee9648d79a7c3becf23

URL: 
https://github.com/llvm/llvm-project/commit/5acdae1f9a772e16850b0ee9648d79a7c3becf23
DIFF: 
https://github.com/llvm/llvm-project/commit/5acdae1f9a772e16850b0ee9648d79a7c3becf23.diff

LOG: [OpenMP] Fixed an issue that wrong LLVM headers might be included when 
building libomptarget

Wrong LLVM headers might be included if we don't set `include_directories`
to a right place. This will cause a compilation error if LLVM is installed in
system directories.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D93737

Added: 


Modified: 
openmp/libomptarget/src/CMakeLists.txt

Removed: 




diff  --git a/openmp/libomptarget/src/CMakeLists.txt 
b/openmp/libomptarget/src/CMakeLists.txt
index 35ff4ed549cc..3fc7278f7fbd 100644
--- a/openmp/libomptarget/src/CMakeLists.txt
+++ b/openmp/libomptarget/src/CMakeLists.txt
@@ -21,6 +21,8 @@ set(LIBOMPTARGET_SRC_FILES
   ${CMAKE_CURRENT_SOURCE_DIR}/omptarget.cpp
 )
 
+include_directories(${LIBOMPTARGET_LLVM_MAIN_INCLUDE_DIR})
+
 # Build libomptarget library with libdl dependency. Add LLVMSupport
 # dependency if building in-tree with profiling enabled.
 if(OPENMP_STANDALONE_BUILD OR (NOT OPENMP_ENABLE_LIBOMPTARGET_PROFILING))



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[llvm-branch-commits] [libc] 4726bec - [libc] Add implementation of fmaf.

[Tue Ly via llvm-branch-commits]

Author: Tue Ly
Date: 2021-01-06T17:14:20-05:00
New Revision: 4726bec8f29bd535e2709b491d223d42bd20c120

URL: 
https://github.com/llvm/llvm-project/commit/4726bec8f29bd535e2709b491d223d42bd20c120
DIFF: 
https://github.com/llvm/llvm-project/commit/4726bec8f29bd535e2709b491d223d42bd20c120.diff

LOG: [libc] Add implementation of fmaf.

Differential Revision: https://reviews.llvm.org/D94018

Added: 
libc/src/math/fmaf.cpp
libc/src/math/fmaf.h
libc/test/src/math/FmaTest.h
libc/test/src/math/fmaf_test.cpp

Modified: 
libc/config/linux/aarch64/entrypoints.txt
libc/config/linux/x86_64/entrypoints.txt
libc/spec/stdc.td
libc/src/math/CMakeLists.txt
libc/test/src/math/CMakeLists.txt
libc/utils/FPUtil/FPBits.h
libc/utils/MPFRWrapper/MPFRUtils.cpp
libc/utils/MPFRWrapper/MPFRUtils.h

Removed: 




diff  --git a/libc/config/linux/aarch64/entrypoints.txt 
b/libc/config/linux/aarch64/entrypoints.txt
index b9042625e666..0db8c4b39caa 100644
--- a/libc/config/linux/aarch64/entrypoints.txt
+++ b/libc/config/linux/aarch64/entrypoints.txt
@@ -65,6 +65,7 @@ set(TARGET_LIBM_ENTRYPOINTS
 libc.src.math.floor
 libc.src.math.floorf
 libc.src.math.floorl
+libc.src.math.fmaf
 libc.src.math.fmax
 libc.src.math.fmaxf
 libc.src.math.fmaxl

diff  --git a/libc/config/linux/x86_64/entrypoints.txt 
b/libc/config/linux/x86_64/entrypoints.txt
index a34c59646149..a80a8b4f105b 100644
--- a/libc/config/linux/x86_64/entrypoints.txt
+++ b/libc/config/linux/x86_64/entrypoints.txt
@@ -106,6 +106,7 @@ set(TARGET_LIBM_ENTRYPOINTS
 libc.src.math.floor
 libc.src.math.floorf
 libc.src.math.floorl
+libc.src.math.fmaf
 libc.src.math.fmin
 libc.src.math.fminf
 libc.src.math.fminl

diff  --git a/libc/spec/stdc.td b/libc/spec/stdc.td
index 41f6083a2336..e89d16633ae3 100644
--- a/libc/spec/stdc.td
+++ b/libc/spec/stdc.td
@@ -322,6 +322,8 @@ def StdC : StandardSpec<"stdc"> {
   FunctionSpec<"fmaxf", RetValSpec, [ArgSpec, 
ArgSpec]>,
   FunctionSpec<"fmaxl", RetValSpec, 
[ArgSpec, ArgSpec]>,
 
+  FunctionSpec<"fmaf", RetValSpec, [ArgSpec, 
ArgSpec, ArgSpec]>,
+
   FunctionSpec<"frexp", RetValSpec, [ArgSpec, 
ArgSpec]>,
   FunctionSpec<"frexpf", RetValSpec, [ArgSpec, 
ArgSpec]>,
   FunctionSpec<"frexpl", RetValSpec, 
[ArgSpec, ArgSpec]>,

diff  --git a/libc/src/math/CMakeLists.txt b/libc/src/math/CMakeLists.txt
index 15a2e4645edd..34b7dfcd4306 100644
--- a/libc/src/math/CMakeLists.txt
+++ b/libc/src/math/CMakeLists.txt
@@ -978,3 +978,14 @@ add_entrypoint_object(
 -O2
 )
 
+add_entrypoint_object(
+  fmaf
+  SRCS
+fmaf.cpp
+  HDRS
+fmaf.h
+  DEPENDS
+libc.utils.FPUtil.fputil
+  COMPILE_OPTIONS
+-O2
+)

diff  --git a/libc/src/math/fmaf.cpp b/libc/src/math/fmaf.cpp
new file mode 100644
index ..1860d887d630
--- /dev/null
+++ b/libc/src/math/fmaf.cpp
@@ -0,0 +1,64 @@
+//===-- Implementation of fmaf function 
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "src/__support/common.h"
+
+#include "utils/FPUtil/FEnv.h"
+#include "utils/FPUtil/FPBits.h"
+
+namespace __llvm_libc {
+
+float LLVM_LIBC_ENTRYPOINT(fmaf)(float x, float y, float z) {
+  // Product is exact.
+  double prod = static_cast(x) * static_cast(y);
+  double z_d = static_cast(z);
+  double sum = prod + z_d;
+  fputil::FPBits bit_prod(prod), bitz(z_d), bit_sum(sum);
+
+  if (!(bit_sum.isInfOrNaN() || bit_sum.isZero())) {
+// Since the sum is computed in double precision, rounding might happen
+// (for instance, when bitz.exponent > bit_prod.exponent + 5, or
+// bit_prod.exponent > bitz.exponent + 40).  In that case, when we round
+// the sum back to float, double rounding error might occur.
+// A concrete example of this phenomenon is as follows:
+//   x = y = 1 + 2^(-12), z = 2^(-53)
+// The exact value of x*y + z is 1 + 2^(-11) + 2^(-24) + 2^(-53)
+// So when rounding to float, fmaf(x, y, z) = 1 + 2^(-11) + 2^(-23)
+// On the other hand, with the default rounding mode,
+//   double(x*y + z) = 1 + 2^(-11) + 2^(-24)
+// and casting again to float gives us:
+//   float(double(x*y + z)) = 1 + 2^(-11).
+//
+// In order to correct this possible double rounding error, first we use
+// Dekker's 2Sum algorithm to find t such that sum - t = prod + z exactly,
+// assuming the (default) rounding mode is round-to-the-nearest,
+// tie-to-even.  Moreover, t satisfies the condition that t < eps(sum),
+// i.e., t.exponent < sum.exponent - 52. So if t is not 0, meaning rounding
+// occurs when com

[llvm-branch-commits] [mlir] c42cee0 - [mlir][ODS] Fix the use of cppClassName in Type constraints for TypeDefs

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2021-01-06T14:18:58-08:00
New Revision: c42cee0c64fe20235123ba44aac12d7e38117a7e

URL: 
https://github.com/llvm/llvm-project/commit/c42cee0c64fe20235123ba44aac12d7e38117a7e
DIFF: 
https://github.com/llvm/llvm-project/commit/c42cee0c64fe20235123ba44aac12d7e38117a7e.diff

LOG: [mlir][ODS] Fix the use of cppClassName in Type constraints for TypeDefs

This field is currently being used to mean "Fully resolved class name", which 
breaks the usage by TypeDefs. This revision prefixes the name with the dialect 
namespace when necessary.

Differential Revision: https://reviews.llvm.org/D94192

Added: 


Modified: 
mlir/include/mlir/IR/OpBase.td
mlir/include/mlir/TableGen/Type.h
mlir/lib/TableGen/Type.cpp
mlir/test/mlir-tblgen/op-decl.td

Removed: 




diff  --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td
index 17996dfde5ae..dc3e8a6367cd 100644
--- a/mlir/include/mlir/IR/OpBase.td
+++ b/mlir/include/mlir/IR/OpBase.td
@@ -345,7 +345,8 @@ class AnyTypeOf allowedTypes, string summary = 
"",
 Or,
 !if(!eq(summary, ""),
 !interleave(!foreach(t, allowedTypes, t.summary), " or "),
-summary)>;
+summary),
+cppClassName>;
 
 // Integer types.
 

diff  --git a/mlir/include/mlir/TableGen/Type.h 
b/mlir/include/mlir/TableGen/Type.h
index c604a4bd7009..6af6d05076a2 100644
--- a/mlir/include/mlir/TableGen/Type.h
+++ b/mlir/include/mlir/TableGen/Type.h
@@ -49,7 +49,7 @@ class TypeConstraint : public Constraint {
   Optional getBuilderCall() const;
 
   // Return the C++ class name for this type (which may just be ::mlir::Type).
-  StringRef getCPPClassName() const;
+  std::string getCPPClassName() const;
 };
 
 // Wrapper class with helper methods for accessing Types defined in TableGen.

diff  --git a/mlir/lib/TableGen/Type.cpp b/mlir/lib/TableGen/Type.cpp
index d7b129e83ee7..fd5a0f705897 100644
--- a/mlir/lib/TableGen/Type.cpp
+++ b/mlir/lib/TableGen/Type.cpp
@@ -11,6 +11,8 @@
 
//===--===//
 
 #include "mlir/TableGen/Type.h"
+#include "mlir/TableGen/Dialect.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/ADT/TypeSwitch.h"
 #include "llvm/TableGen/Record.h"
 
@@ -54,8 +56,19 @@ Optional TypeConstraint::getBuilderCall() const {
 }
 
 // Return the C++ class name for this type (which may just be ::mlir::Type).
-StringRef TypeConstraint::getCPPClassName() const {
-  return def->getValueAsString("cppClassName");
+std::string TypeConstraint::getCPPClassName() const {
+  StringRef className = def->getValueAsString("cppClassName");
+
+  // If the class name is already namespace resolved, use it.
+  if (className.contains("::"))
+return className.str();
+
+  // Otherwise, check to see if there is a namespace from a dialect to prepend.
+  if (const llvm::RecordVal *value = def->getValue("dialect")) {
+Dialect dialect(cast(value->getValue())->getDef());
+return (dialect.getCppNamespace() + "::" + className).str();
+  }
+  return className.str();
 }
 
 Type::Type(const llvm::Record *record) : TypeConstraint(record) {}

diff  --git a/mlir/test/mlir-tblgen/op-decl.td 
b/mlir/test/mlir-tblgen/op-decl.td
index 3d4d46ceb42f..91e46b59c2e6 100644
--- a/mlir/test/mlir-tblgen/op-decl.td
+++ b/mlir/test/mlir-tblgen/op-decl.td
@@ -248,6 +248,23 @@ def NS_JOp : 
NS_Op<"op_with_InferTypeOpInterface_interface", [DeclareOpInterface
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState 
&odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, 
::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, 
::mlir::OperationState &odsState, ::mlir::ValueRange operands, 
::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 
+// Test that type defs have the proper namespaces when used as a constraint.
+// ---
+
+def Test_Dialect2 : Dialect {
+  let name = "test";
+  let cppNamespace = "::mlir::dialect2";
+}
+def TestDialect2Type : TypeDef;
+
+def NS_ResultWithDialectTypeOp : NS_Op<"op_with_dialect_type", []> {
+  let results = (outs TestDialect2Type);
+}
+
+// CHECK-LABEL: NS::ResultWithDialectTypeOp declarations
+// CHECK: class ResultWithDialectTypeOp :
+// CHECK-SAME: 
::mlir::OpTrait::OneTypedResult<::mlir::dialect2::Dialect2TypeType>
+
 // Check that default builders can be suppressed.
 // ---
 



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[llvm-branch-commits] [mlir] e0a93e4 - [mlir][ODS] Rename several uses of 'description' to 'summary'

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2021-01-06T14:18:58-08:00
New Revision: e0a93e4b65b63b0ae0fbde826790dc1728789fab

URL: 
https://github.com/llvm/llvm-project/commit/e0a93e4b65b63b0ae0fbde826790dc1728789fab
DIFF: 
https://github.com/llvm/llvm-project/commit/e0a93e4b65b63b0ae0fbde826790dc1728789fab.diff

LOG: [mlir][ODS] Rename several uses of 'description' to 'summary'

Right now constraint/predicate traits/etc. use their "description" field as a 
one line human readable string. This breaks the current convention, by which a 
"description" may be multi-line. This revision renames the "description" field 
in these cases to "summary" which matches what the string is actually used as. 
This also unbreaks the use of TypeDefs(and eventually AttrDefs) in conjunction 
with existing type constraint facilities like `Optional`.

Differential Revision: https://reviews.llvm.org/D94133

Added: 


Modified: 
mlir/docs/OpDefinitions.md
mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td
mlir/include/mlir/Dialect/Async/IR/AsyncBase.td
mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
mlir/include/mlir/Dialect/Quant/QuantOpsBase.td
mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
mlir/include/mlir/IR/OpBase.td
mlir/include/mlir/TableGen/Constraint.h
mlir/include/mlir/TableGen/OpTrait.h
mlir/include/mlir/TableGen/Type.h
mlir/include/mlir/TableGen/TypeDef.h
mlir/lib/TableGen/Constraint.cpp
mlir/lib/TableGen/OpTrait.cpp
mlir/lib/TableGen/Type.cpp
mlir/lib/TableGen/TypeDef.cpp
mlir/test/mlir-tblgen/op-attribute.td
mlir/tools/mlir-tblgen/EnumsGen.cpp
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
mlir/tools/mlir-tblgen/OpDocGen.cpp
mlir/tools/mlir-tblgen/OpFormatGen.cpp
mlir/tools/mlir-tblgen/RewriterGen.cpp
mlir/tools/mlir-tblgen/StructsGen.cpp
mlir/unittests/TableGen/structs.td

Removed: 




diff  --git a/mlir/docs/OpDefinitions.md b/mlir/docs/OpDefinitions.md
index 0b235f993e3d..bfd3d43c60b9 100644
--- a/mlir/docs/OpDefinitions.md
+++ b/mlir/docs/OpDefinitions.md
@@ -4,16 +4,17 @@ In addition to specializing the `mlir::Op` C++ template, MLIR 
also supports
 defining operations and data types in a table-driven manner. This is achieved
 via [TableGen][TableGen], which is both a generic language and its tooling to
 maintain records of domain-specific information. Facts regarding an operation
-are specified concisely into a TableGen record, which will be expanded into
-an equivalent `mlir::Op` C++ template specialization at compiler build time.
+are specified concisely into a TableGen record, which will be expanded into an
+equivalent `mlir::Op` C++ template specialization at compiler build time.
 
 This manual explains in detail all the available mechanisms for defining
 operations in such a table-driven manner. It aims to be a specification instead
-of a tutorial. Please refer to [Quickstart tutorial to adding MLIR graph
-rewrite](Tutorials/QuickstartRewrites.md) for the latter.
+of a tutorial. Please refer to
+[Quickstart tutorial to adding MLIR graph 
rewrite](Tutorials/QuickstartRewrites.md)
+for the latter.
 
-In addition to detailing each mechanism, this manual also tries to capture
-best practices. They are rendered as quoted bullet points.
+In addition to detailing each mechanism, this manual also tries to capture best
+practices. They are rendered as quoted bullet points.
 
 ## Motivation
 
@@ -22,12 +23,12 @@ operations. This open and extensible ecosystem leads to the 
"stringly" type IR
 problem, e.g., repetitive string comparisons during optimization and analysis
 passes, unintuitive accessor methods (e.g., generic/error prone `getOperand(3)`
 vs self-documenting `getStride()`) with more generic return types, verbose and
-generic constructors without default arguments, verbose textual IR dump, and
-so on. Furthermore, operation verification is:
+generic constructors without default arguments, verbose textual IR dump, and so
+on. Furthermore, operation verification is:
 
-1. best case: a central string-to-verification-function map,
-1. middle case: duplication of verification across the code base, or
-1. worst case: no verification functions.
+1.  best case: a central string-to-verification-function map,
+1.  middle case: duplication of verification across the code base, or
+1.  worst case: no verification functions.
 
 The fix is to support defining ops in a table-driven manner. Then for each
 dialect, we can have a central place that contains everything you need to know
@@ -40,17 +41,17 @@ building, verification, parsing, printing, analysis, and 
many more.
 Compared to the C++ template, this table-driven approach has several benefits
 including but not limited to:
 
-* **Single source of truth**: We strive to encode all facts regarding an
-  operation into the record, so that readers don't need to jump amon

[llvm-branch-commits] [mlir] efd0504 - [mlir] Add hoisting transformation for transfer ops on tensor

[Thomas Raoux via llvm-branch-commits]

Author: Thomas Raoux
Date: 2021-01-06T14:23:59-08:00
New Revision: efd05040e13e942a4fbb79eb798fb9833e319b51

URL: 
https://github.com/llvm/llvm-project/commit/efd05040e13e942a4fbb79eb798fb9833e319b51
DIFF: 
https://github.com/llvm/llvm-project/commit/efd05040e13e942a4fbb79eb798fb9833e319b51.diff

LOG: [mlir] Add hoisting transformation for transfer ops on tensor

Add same hoisting transformation existing for transfer ops on buffers for
transfer_ops on tensor. The logic is significantly different so this is done as
a separate transformation and it is expect that user would know which
transformation to use based on the flow.

Differential Revision: https://reviews.llvm.org/D94115

Added: 


Modified: 
mlir/include/mlir/Dialect/Linalg/Transforms/Hoisting.h
mlir/include/mlir/Dialect/Vector/VectorUtils.h
mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
mlir/lib/Dialect/Vector/VectorUtils.cpp
mlir/test/Dialect/Linalg/hoisting.mlir
mlir/test/lib/Transforms/TestLinalgHoisting.cpp

Removed: 




diff  --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Hoisting.h 
b/mlir/include/mlir/Dialect/Linalg/Transforms/Hoisting.h
index 32693555ff40..ed585d1f5cf5 100644
--- a/mlir/include/mlir/Dialect/Linalg/Transforms/Hoisting.h
+++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Hoisting.h
@@ -21,8 +21,9 @@ namespace linalg {
 // TODO: generalize on a per-need basis.
 void hoistViewAllocOps(FuncOp func);
 
-/// Hoist vector.transfer_read/vector.transfer_write pairs out of immediately
-/// enclosing scf::ForOp iteratively, if the following conditions are true:
+/// Hoist vector.transfer_read/vector.transfer_write on buffers pairs out of
+/// immediately enclosing scf::ForOp iteratively, if the following conditions
+/// are true:
 ///   1. The two ops access the same memref with the same indices.
 ///   2. All operands are invariant under the enclosing scf::ForOp.
 ///   3. No uses of the memref either dominate the transfer_read or are
@@ -35,6 +36,10 @@ void hoistViewAllocOps(FuncOp func);
 // TODO: generalize on a per-need basis.
 void hoistRedundantVectorTransfers(FuncOp func);
 
+/// Same behavior as `hoistRedundantVectorTransfers` but works on tensors
+/// instead of buffers.
+void hoistRedundantVectorTransfersOnTensor(FuncOp func);
+
 } // namespace linalg
 } // namespace mlir
 

diff  --git a/mlir/include/mlir/Dialect/Vector/VectorUtils.h 
b/mlir/include/mlir/Dialect/Vector/VectorUtils.h
index a06bc8cf6562..03250f0a 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorUtils.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorUtils.h
@@ -165,6 +165,12 @@ AffineMap getTransferMinorIdentityMap(ShapedType 
shapedType,
 bool isDisjointTransferSet(VectorTransferOpInterface transferA,
VectorTransferOpInterface transferB);
 
+/// Same behavior as `isDisjointTransferSet` but doesn't require the operations
+/// to have the same tensor/memref. This allows comparing operations accessing
+/// 
diff erent tensors.
+bool isDisjointTransferIndices(VectorTransferOpInterface transferA,
+   VectorTransferOpInterface transferB);
+
 namespace matcher {
 
 /// Matches vector.transfer_read, vector.transfer_write and ops that return a

diff  --git a/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp 
b/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
index a1797fde7da6..98d61fa6a8d9 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
@@ -81,12 +81,151 @@ void mlir::linalg::hoistViewAllocOps(FuncOp func) {
   }
 }
 
+/// Look for a transfer_read, in the given tensor uses, accessing the same
+/// offset as the transfer_write.
+static vector::TransferReadOp
+findMatchingTransferRead(vector::TransferWriteOp write, Value srcTensor) {
+  for (Operation *user : srcTensor.getUsers()) {
+auto read = dyn_cast(user);
+if (read && read.indices() == write.indices() &&
+read.getVectorType() == write.getVectorType()) {
+  return read;
+}
+  }
+  return nullptr;
+}
+
+/// Check if the chunk of data inserted by the transfer_write in the given
+/// tensor are read by any other op than the read candidate.
+static bool tensorChunkAccessedByUnknownOp(vector::TransferWriteOp write,
+   vector::TransferReadOp 
candidateRead,
+   Value srcTensor) {
+  // Make sure none of the other uses read the part of the tensor modified
+  // by the transfer_write.
+  llvm::SmallVector uses;
+  uses.push_back(srcTensor.getUses());
+  while (!uses.empty()) {
+for (OpOperand &use : uses.pop_back_val()) {
+  Operation *user = use.getOwner();
+  // Skip the candidate use, only inspect the "other" uses.
+  if (user == candidateRead.getOperation() || user == write.getOperation())
+continue;
+  // Consider all transitive uses through a ve

[llvm-branch-commits] [openmp] fb1c528 - [OpenMP] Use c_int/c_size_t in Fortran target memory routine interface

[Hansang Bae via llvm-branch-commits]

Author: Hansang Bae
Date: 2021-01-06T16:28:30-06:00
New Revision: fb1c52852690cb6ad6f7f2a7b5c35bf4d0c56e44

URL: 
https://github.com/llvm/llvm-project/commit/fb1c52852690cb6ad6f7f2a7b5c35bf4d0c56e44
DIFF: 
https://github.com/llvm/llvm-project/commit/fb1c52852690cb6ad6f7f2a7b5c35bf4d0c56e44.diff

LOG: [OpenMP] Use c_int/c_size_t in Fortran target memory routine interface

The Fortran interface is now in line with 5.1 specification.

Differential Revision: https://reviews.llvm.org/D94042

Added: 


Modified: 
openmp/runtime/src/include/omp_lib.f90.var
openmp/runtime/src/include/omp_lib.h.var

Removed: 




diff  --git a/openmp/runtime/src/include/omp_lib.f90.var 
b/openmp/runtime/src/include/omp_lib.f90.var
index 1bde868a505b..24f8a2af4c5e 100644
--- a/openmp/runtime/src/include/omp_lib.f90.var
+++ b/openmp/runtime/src/include/omp_lib.f90.var
@@ -512,59 +512,54 @@
   function omp_target_alloc(size, device_num) bind(c)
 use omp_lib_kinds
 type(c_ptr) omp_target_alloc
-integer (kind=kmp_size_t_kind), value :: size
-integer (kind=omp_integer_kind), value :: device_num
+integer(c_size_t), value :: size
+integer(c_int), value :: device_num
   end function omp_target_alloc
 
   subroutine omp_target_free(device_ptr, device_num) bind(c)
 use omp_lib_kinds
 type(c_ptr), value :: device_ptr
-integer (kind=omp_integer_kind), value :: device_num
+integer(c_int), value :: device_num
   end subroutine omp_target_free
 
   function omp_target_is_present(ptr, device_num) bind(c)
 use omp_lib_kinds
-integer (kind=omp_integer_kind) omp_target_is_present
+integer(c_int) omp_target_is_present
 type(c_ptr), value :: ptr
-integer (kind=omp_integer_kind), value :: device_num
+integer(c_int), value :: device_num
   end function omp_target_is_present
 
   function omp_target_memcpy(dst, src, length, dst_offset, src_offset, 
&
   dst_device_num, src_device_num) bind(c)
 use omp_lib_kinds
-integer (kind=omp_integer_kind) omp_target_memcpy
+integer(c_int) omp_target_memcpy
 type(c_ptr), value :: dst, src
-integer (kind=kmp_size_t_kind), value :: length, dst_offset,   
&
-src_offset
-integer (kind=omp_integer_kind), value :: dst_device_num,  
&
-src_device_num
+integer(c_size_t), value :: length, dst_offset, src_offset
+integer(c_int), value :: dst_device_num, src_device_num
   end function omp_target_memcpy
 
   function omp_target_memcpy_rect(dst, src, element_size, num_dims,
&
   volume, dst_offsets, src_offsets, dst_dimensions,
&
   src_dimensions, dst_device_num, src_device_num) bind(c)
 use omp_lib_kinds
-integer (kind=omp_integer_kind) omp_target_memcpy_rect
+integer(c_int) omp_target_memcpy_rect
 type(c_ptr), value :: dst, src
-integer (kind=kmp_size_t_kind), value :: element_size
-integer (kind=omp_integer_kind), value :: num_dims,
&
-dst_device_num, src_device_num
-integer (kind=kmp_size_t_kind), intent(in) :: volume(*),   
&
-dst_offsets(*), src_offsets(*), dst_dimensions(*), 
&
-src_dimensions(*)
+integer(c_size_t), value :: element_size
+integer(c_int), value :: num_dims, dst_device_num, src_device_num
+integer(c_size_t), intent(in) :: volume(*), dst_offsets(*),
&
+src_offsets(*), dst_dimensions(*), src_dimensions(*)
   end function omp_target_memcpy_rect
 
   function omp_target_memcpy_async(dst, src, length, dst_offset,   
&
   src_offset, dst_device_num, src_device_num, depobj_count,
&
   depobj_list) bind(c)
 use omp_lib_kinds
-integer (kind=omp_integer_kind) omp_target_memcpy_async
+integer(c_int) omp_target_memcpy_async
 type(c_ptr), value :: dst, src
-integer (kind=kmp_size_t_kind), value :: length, dst_offset,   
&
-src_offset
-integer (kind=omp_integer_kind), value :: dst_device_num,  
&
-src_device_num, depobj_count
-integer (kind=omp_depend_kind), optional :: depobj_list(*)
+integer(c_size_t), value :: length, dst_offset, src_offset
+integer(c_int), value :: dst_device_num, src_device_num,   
&
+depobj_count
+integer(omp_depend_kind), optional :: depobj_list(*)
   end function omp_target_memcpy_asyn

[llvm-branch-commits] [llvm] 63aeaf7 - [DominatorTree] Add support for mixed pre/post CFG views.

[Alina Sbirlea via llvm-branch-commits]

Author: Alina Sbirlea
Date: 2021-01-06T14:53:09-08:00
New Revision: 63aeaf754a78c67ca3f8343d525dfb7a378dfa9e

URL: 
https://github.com/llvm/llvm-project/commit/63aeaf754a78c67ca3f8343d525dfb7a378dfa9e
DIFF: 
https://github.com/llvm/llvm-project/commit/63aeaf754a78c67ca3f8343d525dfb7a378dfa9e.diff

LOG: [DominatorTree] Add support for mixed pre/post CFG views.

Add support for mixed pre/post CFG views.

Update usages of the MemorySSAUpdater to use the new DT API by
requesting the DT updates to be done by the MSSAUpdater.

Differential Revision: https://reviews.llvm.org/D93371

Added: 


Modified: 
llvm/include/llvm/Analysis/MemorySSAUpdater.h
llvm/include/llvm/Support/GenericDomTree.h
llvm/lib/Analysis/MemorySSAUpdater.cpp
llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
llvm/lib/Transforms/Utils/LoopRotationUtils.cpp

Removed: 




diff  --git a/llvm/include/llvm/Analysis/MemorySSAUpdater.h 
b/llvm/include/llvm/Analysis/MemorySSAUpdater.h
index d41b93209979..b0bf2e5ead62 100644
--- a/llvm/include/llvm/Analysis/MemorySSAUpdater.h
+++ b/llvm/include/llvm/Analysis/MemorySSAUpdater.h
@@ -119,8 +119,11 @@ class MemorySSAUpdater {
   ArrayRef ExitBlocks,
   ArrayRef> VMaps, DominatorTree &DT);
 
-  /// Apply CFG updates, analogous with the DT edge updates.
-  void applyUpdates(ArrayRef Updates, DominatorTree &DT);
+  /// Apply CFG updates, analogous with the DT edge updates. By default, the
+  /// DT is assumed to be already up to date. If UpdateDTFirst is true, first
+  /// update the DT with the same updates.
+  void applyUpdates(ArrayRef Updates, DominatorTree &DT,
+bool UpdateDTFirst = false);
   /// Apply CFG insert updates, analogous with the DT edge updates.
   void applyInsertUpdates(ArrayRef Updates, DominatorTree &DT);
 

diff  --git a/llvm/include/llvm/Support/GenericDomTree.h 
b/llvm/include/llvm/Support/GenericDomTree.h
index d2d7c8c4481d..28b2537bc481 100644
--- a/llvm/include/llvm/Support/GenericDomTree.h
+++ b/llvm/include/llvm/Support/GenericDomTree.h
@@ -550,7 +550,7 @@ class DominatorTreeBase {
   /// \param Updates An unordered sequence of updates to perform. The current
   /// CFG and the reverse of these updates provides the pre-view of the CFG.
   /// \param PostViewUpdates An unordered sequence of update to perform in 
order
-  /// to obtain a post-view of the CFG. The DT will be updates assuming the
+  /// to obtain a post-view of the CFG. The DT will be updated assuming the
   /// obtained PostViewCFG is the desired end state.
   void applyUpdates(ArrayRef Updates,
 ArrayRef PostViewUpdates) {
@@ -558,14 +558,18 @@ class DominatorTreeBase {
   GraphDiff PostViewCFG(PostViewUpdates);
   DomTreeBuilder::ApplyUpdates(*this, PostViewCFG, &PostViewCFG);
 } else {
-  // TODO:
   // PreViewCFG needs to merge Updates and PostViewCFG. The updates in
   // Updates need to be reversed, and match the direction in PostViewCFG.
-  // Normally, a PostViewCFG is created without reversing updates, so one
-  // of the internal vectors needs reversing in order to do the
-  // legalization of the merged vector of updates.
-  llvm_unreachable("Currently unsupported to update given a set of "
-   "updates towards a PostView");
+  // The PostViewCFG is created with updates reversed (equivalent to 
changes
+  // made to the CFG), so the PreViewCFG needs all the updates reverse
+  // applied.
+  SmallVector AllUpdates(Updates.begin(), Updates.end());
+  for (auto &Update : PostViewUpdates)
+AllUpdates.push_back(Update);
+  GraphDiff PreViewCFG(AllUpdates,
+   /*ReverseApplyUpdates=*/true);
+  GraphDiff PostViewCFG(PostViewUpdates);
+  DomTreeBuilder::ApplyUpdates(*this, PreViewCFG, &PostViewCFG);
 }
   }
 

diff  --git a/llvm/lib/Analysis/MemorySSAUpdater.cpp 
b/llvm/lib/Analysis/MemorySSAUpdater.cpp
index 4ff61d4324f8..99fa58b8872a 100644
--- a/llvm/lib/Analysis/MemorySSAUpdater.cpp
+++ b/llvm/lib/Analysis/MemorySSAUpdater.cpp
@@ -811,7 +811,7 @@ void MemorySSAUpdater::updateExitBlocksForClonedLoop(
 }
 
 void MemorySSAUpdater::applyUpdates(ArrayRef Updates,
-DominatorTree &DT) {
+DominatorTree &DT, bool UpdateDT) {
   SmallVector DeleteUpdates;
   SmallVector RevDeleteUpdates;
   SmallVector InsertUpdates;
@@ -825,10 +825,15 @@ void MemorySSAUpdater::applyUpdates(ArrayRef 
Updates,
   }
 
   if (!DeleteUpdates.empty()) {
-SmallVector Empty;
-// Deletes are reversed applied, because this CFGView is pretending the
-// deletes did not happen yet, hence the edges still exist.
-DT.applyUpdates(Empty, RevDeleteUpdates);
+if (!U

[llvm-branch-commits] [llvm] a126569 - Fix failing triple test for macOS 11 with non-zero minor versions.

[Amara Emerson via llvm-branch-commits]

Author: Amara Emerson
Date: 2021-01-06T14:57:37-08:00
New Revision: a1265690cf614bde8a7fd1d503c5f13c184dc786

URL: 
https://github.com/llvm/llvm-project/commit/a1265690cf614bde8a7fd1d503c5f13c184dc786
DIFF: 
https://github.com/llvm/llvm-project/commit/a1265690cf614bde8a7fd1d503c5f13c184dc786.diff

LOG: Fix failing triple test for macOS 11 with non-zero minor versions.

Differential Revision: https://reviews.llvm.org/D94197

Added: 


Modified: 
llvm/unittests/ADT/TripleTest.cpp
llvm/unittests/Support/Host.cpp

Removed: 




diff  --git a/llvm/unittests/ADT/TripleTest.cpp 
b/llvm/unittests/ADT/TripleTest.cpp
index ffce07ba2b12..ff6c2dde4b16 100644
--- a/llvm/unittests/ADT/TripleTest.cpp
+++ b/llvm/unittests/ADT/TripleTest.cpp
@@ -1264,6 +1264,14 @@ TEST(TripleTest, getOSVersion) {
   EXPECT_EQ((unsigned)0, Minor);
   EXPECT_EQ((unsigned)0, Micro);
 
+  // For darwin triples on macOS 11, only compare the major version.
+  T = Triple("x86_64-apple-darwin20.2");
+  EXPECT_TRUE(T.isMacOSX());
+  T.getMacOSXVersion(Major, Minor, Micro);
+  EXPECT_EQ((unsigned)11, Major);
+  EXPECT_EQ((unsigned)0, Minor);
+  EXPECT_EQ((unsigned)0, Micro);
+
   T = Triple("armv7-apple-ios");
   EXPECT_FALSE(T.isMacOSX());
   EXPECT_TRUE(T.isiOS());

diff  --git a/llvm/unittests/Support/Host.cpp b/llvm/unittests/Support/Host.cpp
index 8029bb5830fc..b452048361db 100644
--- a/llvm/unittests/Support/Host.cpp
+++ b/llvm/unittests/Support/Host.cpp
@@ -348,9 +348,15 @@ TEST_F(HostTest, getMacOSHostVersion) {
   unsigned HostMajor, HostMinor, HostMicro;
   ASSERT_EQ(HostTriple.getMacOSXVersion(HostMajor, HostMinor, HostMicro), 
true);
 
-  // Don't compare the 'Micro' version, as it's always '0' for the 'Darwin'
-  // triples.
-  ASSERT_EQ(std::tie(SystemMajor, SystemMinor), std::tie(HostMajor, 
HostMinor));
+  if (SystemMajor > 10) {
+// Don't compare the 'Minor' and 'Micro' versions, as they're always '0' 
for
+// the 'Darwin' triples on 11.x.
+ASSERT_EQ(SystemMajor, HostMajor);
+  } else {
+// Don't compare the 'Micro' version, as it's always '0' for the 'Darwin'
+// triples.
+ASSERT_EQ(std::tie(SystemMajor, SystemMinor), std::tie(HostMajor, 
HostMinor));
+  }
 }
 #endif
 



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[llvm-branch-commits] [mlir] 41d919a - [mlir][TypeDefGen] Remove the need to define parser/printer for singleton types

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2021-01-06T15:00:14-08:00
New Revision: 41d919aa29468ac072755b8449b8a38ff26f6979

URL: 
https://github.com/llvm/llvm-project/commit/41d919aa29468ac072755b8449b8a38ff26f6979
DIFF: 
https://github.com/llvm/llvm-project/commit/41d919aa29468ac072755b8449b8a38ff26f6979.diff

LOG: [mlir][TypeDefGen] Remove the need to define parser/printer for singleton 
types

This allows for singleton types without an explicit parser/printer to simply use
the mnemonic as the assembly format, removing the need for these types to 
provide the parser/printer
fields.

Differential Revision: https://reviews.llvm.org/D94194

Added: 


Modified: 
mlir/test/lib/Dialect/Test/TestTypeDefs.td
mlir/tools/mlir-tblgen/TypeDefGen.cpp

Removed: 




diff  --git a/mlir/test/lib/Dialect/Test/TestTypeDefs.td 
b/mlir/test/lib/Dialect/Test/TestTypeDefs.td
index 75fffa11cb21..80927dff62c2 100644
--- a/mlir/test/lib/Dialect/Test/TestTypeDefs.td
+++ b/mlir/test/lib/Dialect/Test/TestTypeDefs.td
@@ -21,9 +21,6 @@ class Test_Type : TypeDef { }
 
 def SimpleTypeA : Test_Type<"SimpleA"> {
   let mnemonic = "smpla";
-
-  let printer = [{ $_printer << "smpla"; }];
-  let parser = [{ return get($_ctxt); }];
 }
 
 // A more complex parameterized type.

diff  --git a/mlir/tools/mlir-tblgen/TypeDefGen.cpp 
b/mlir/tools/mlir-tblgen/TypeDefGen.cpp
index 8fdb5f4feeaf..20168168bc8d 100644
--- a/mlir/tools/mlir-tblgen/TypeDefGen.cpp
+++ b/mlir/tools/mlir-tblgen/TypeDefGen.cpp
@@ -537,12 +537,21 @@ static void emitParsePrintDispatch(ArrayRef 
types, raw_ostream &os) {
   os << "static ::mlir::Type generatedTypeParser(::mlir::MLIRContext* "
 "ctxt, "
 "::mlir::DialectAsmParser& parser, ::llvm::StringRef mnemonic) {\n";
-  for (const TypeDef &type : types)
-if (type.getMnemonic())
+  for (const TypeDef &type : types) {
+if (type.getMnemonic()) {
   os << formatv("  if (mnemonic == {0}::{1}::getMnemonic()) return "
-"{0}::{1}::parse(ctxt, parser);\n",
+"{0}::{1}::",
 type.getDialect().getCppNamespace(),
 type.getCppClassName());
+
+  // If the type has no parameters and no parser code, just invoke a normal
+  // `get`.
+  if (type.getNumParameters() == 0 && !type.getParserCode())
+os << "get(ctxt);\n";
+  else
+os << "parse(ctxt, parser);\n";
+}
+  }
   os << "  return ::mlir::Type();\n";
   os << "}\n\n";
 
@@ -551,17 +560,26 @@ static void emitParsePrintDispatch(ArrayRef 
types, raw_ostream &os) {
   os << "static ::mlir::LogicalResult generatedTypePrinter(::mlir::Type "
 "type, "
 "::mlir::DialectAsmPrinter& printer) {\n"
- << "  ::mlir::LogicalResult found = ::mlir::success();\n"
- << "  ::llvm::TypeSwitch<::mlir::Type>(type)\n";
-  for (const TypeDef &type : types)
-if (type.getMnemonic())
-  os << formatv(".Case<{0}::{1}>([&](::mlir::Type t) {{ "
-"t.dyn_cast<{0}::{1}>().print(printer); })\n",
-type.getDialect().getCppNamespace(),
-type.getCppClassName());
-  os << ".Default([&found](::mlir::Type) { found = ::mlir::failure(); "
-"});\n"
- << "  return found;\n"
+ << "  return ::llvm::TypeSwitch<::mlir::Type, "
+"::mlir::LogicalResult>(type)\n";
+  for (const TypeDef &type : types) {
+if (Optional mnemonic = type.getMnemonic()) {
+  StringRef cppNamespace = type.getDialect().getCppNamespace();
+  StringRef cppClassName = type.getCppClassName();
+  os << formatv(".Case<{0}::{1}>([&]({0}::{1} t) {{\n  ",
+cppNamespace, cppClassName);
+
+  // If the type has no parameters and no printer code, just print the
+  // mnemonic.
+  if (type.getNumParameters() == 0 && !type.getPrinterCode())
+os << formatv("printer << {0}::{1}::getMnemonic();", cppNamespace,
+  cppClassName);
+  else
+os << "t.print(printer);";
+  os << "\n  return ::mlir::success();\n})\n";
+}
+  }
+  os << ".Default([](::mlir::Type) { return ::mlir::failure(); });\n"
  << "}\n\n";
 }
 



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[llvm-branch-commits] [libc] f9e858f - [libc] Use a wrapper for rand instead of calling std::rand in fma tests.

[Siva Chandra Reddy via llvm-branch-commits]

Author: Siva Chandra Reddy
Date: 2021-01-06T15:07:44-08:00
New Revision: f9e858f5fd74d0a1b127bf8979dc36bcad8b06d2

URL: 
https://github.com/llvm/llvm-project/commit/f9e858f5fd74d0a1b127bf8979dc36bcad8b06d2
DIFF: 
https://github.com/llvm/llvm-project/commit/f9e858f5fd74d0a1b127bf8979dc36bcad8b06d2.diff

LOG: [libc] Use a wrapper for rand instead of calling std::rand in fma tests.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D94198

Added: 
libc/utils/testutils/RandUtils.cpp
libc/utils/testutils/RandUtils.h

Modified: 
libc/test/src/math/FmaTest.h
libc/utils/testutils/CMakeLists.txt

Removed: 




diff  --git a/libc/test/src/math/FmaTest.h b/libc/test/src/math/FmaTest.h
index c39c4ad0f1da..9f90c8627af9 100644
--- a/libc/test/src/math/FmaTest.h
+++ b/libc/test/src/math/FmaTest.h
@@ -13,8 +13,7 @@
 #include "utils/FPUtil/TestHelpers.h"
 #include "utils/MPFRWrapper/MPFRUtils.h"
 #include "utils/UnitTest/Test.h"
-
-#include 
+#include "utils/testutils/RandUtils.h"
 
 namespace mpfr = __llvm_libc::testing::mpfr;
 
@@ -32,8 +31,9 @@ class FmaTestTemplate : public __llvm_libc::testing::Test {
 
   UIntType getRandomBitPattern() {
 UIntType bits{0};
-for (size_t i = 0; i < sizeof(UIntType) / 2; ++i) {
-  bits = (bits << 2) + static_cast(std::rand());
+for (UIntType i = 0; i < sizeof(UIntType) / 2; ++i) {
+  bits =
+  (bits << 2) + static_cast(__llvm_libc::testutils::rand());
 }
 return bits;
   }

diff  --git a/libc/utils/testutils/CMakeLists.txt 
b/libc/utils/testutils/CMakeLists.txt
index 70237ddc1f8d..c39a8399895d 100644
--- a/libc/utils/testutils/CMakeLists.txt
+++ b/libc/utils/testutils/CMakeLists.txt
@@ -5,6 +5,8 @@ endif()
 
 add_llvm_library(
   libc_test_utils
+  RandUtils.cpp
+  RandUtils.h
   StreamWrapper.cpp
   StreamWrapper.h
   ${EFFile}

diff  --git a/libc/utils/testutils/RandUtils.cpp 
b/libc/utils/testutils/RandUtils.cpp
new file mode 100644
index ..0ccc62327f05
--- /dev/null
+++ b/libc/utils/testutils/RandUtils.cpp
@@ -0,0 +1,19 @@
+//===-- RandUtils.cpp 
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "RandUtils.h"
+
+#include 
+
+namespace __llvm_libc {
+namespace testutils {
+
+int rand() { return std::rand(); }
+
+} // namespace testutils
+} // namespace __llvm_libc

diff  --git a/libc/utils/testutils/RandUtils.h 
b/libc/utils/testutils/RandUtils.h
new file mode 100644
index ..b65a98bfed21
--- /dev/null
+++ b/libc/utils/testutils/RandUtils.h
@@ -0,0 +1,16 @@
+//===-- RandUtils.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+namespace __llvm_libc {
+namespace testutils {
+
+// Wrapper for std::rand.
+int rand();
+
+} // namespace testutils
+} // namespace __llvm_libc



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[llvm-branch-commits] [mlir] 080943f - [mlir][vector] Support transfer op on tensor optimizations

[Thomas Raoux via llvm-branch-commits]

Author: Thomas Raoux
Date: 2021-01-06T15:09:03-08:00
New Revision: 080943f7525f277579a000cf30364cc96fba6773

URL: 
https://github.com/llvm/llvm-project/commit/080943f7525f277579a000cf30364cc96fba6773
DIFF: 
https://github.com/llvm/llvm-project/commit/080943f7525f277579a000cf30364cc96fba6773.diff

LOG: [mlir][vector] Support transfer op on tensor optimizations

Support store to load forwarding and dead store transformations for transfer op
on tensor.

Differential Revision: https://reviews.llvm.org/D94148

Added: 


Modified: 
mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
mlir/test/Dialect/Vector/vector-transferop-opt.mlir

Removed: 




diff  --git a/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp 
b/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
index ea1189d53b31..161d02cd3435 100644
--- a/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
+++ b/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
@@ -34,13 +34,33 @@ static Operation *findAncestorOpInRegion(Region *region, 
Operation *op) {
   return op;
 }
 
+/// Return true if the transfer_write fully writes the data accessed by the
+/// transfer_read.
+static bool transferEncompasses(vector::TransferWriteOp defWrite,
+vector::TransferReadOp read) {
+  return !defWrite.hasMaskedDim() && defWrite.indices() == read.indices() &&
+ defWrite.getVectorType() == read.getVectorType() &&
+ defWrite.permutation_map() == read.permutation_map();
+}
+
+/// Return true if the write op fully over-write the priorWrite transfer_write
+/// op.
+static bool transferEncompasses(vector::TransferWriteOp write,
+vector::TransferWriteOp priorWrite) {
+  return priorWrite.indices() == write.indices() &&
+ priorWrite.getVectorType() == write.getVectorType() &&
+ priorWrite.permutation_map() == write.permutation_map();
+}
+
 namespace {
 
 class TransferOptimization {
 public:
   TransferOptimization(FuncOp func) : dominators(func), postDominators(func) {}
   void deadStoreOp(vector::TransferWriteOp);
+  void deadStoreOpTensor(vector::TransferWriteOp);
   void storeToLoadForwarding(vector::TransferReadOp);
+  void storeToLoadForwardingTensor(vector::TransferReadOp);
   void removeDeadOp() {
 for (Operation *op : opToErase)
   op->erase();
@@ -99,9 +119,7 @@ void 
TransferOptimization::deadStoreOp(vector::TransferWriteOp write) {
   continue;
 if (auto nextWrite = dyn_cast(user)) {
   // Check candidate that can override the store.
-  if (write.indices() == nextWrite.indices() &&
-  write.getVectorType() == nextWrite.getVectorType() &&
-  write.permutation_map() == write.permutation_map() &&
+  if (transferEncompasses(nextWrite, write) &&
   postDominators.postDominates(nextWrite, write)) {
 if (firstOverwriteCandidate == nullptr ||
 postDominators.postDominates(firstOverwriteCandidate, nextWrite))
@@ -173,10 +191,8 @@ void 
TransferOptimization::storeToLoadForwarding(vector::TransferReadOp read) {
   cast(write.getOperation()),
   cast(read.getOperation(
 continue;
-  if (dominators.dominates(write, read) && !write.hasMaskedDim() &&
-  write.indices() == read.indices() &&
-  write.getVectorType() == read.getVectorType() &&
-  write.permutation_map() == read.permutation_map()) {
+  if (dominators.dominates(write, read) &&
+  transferEncompasses(write, read)) {
 if (lastwrite == nullptr || dominators.dominates(lastwrite, write))
   lastwrite = write;
 else
@@ -214,15 +230,62 @@ void 
TransferOptimization::storeToLoadForwarding(vector::TransferReadOp read) {
   opToErase.push_back(read.getOperation());
 }
 
+/// Walk up the SSA links, if any write gets fully overwritten we can skip it.
+/// If it has no more uses it becomes dead.
+void TransferOptimization::deadStoreOpTensor(vector::TransferWriteOp write) {
+  auto defWrite = write.source().getDefiningOp();
+  while (defWrite) {
+if (transferEncompasses(write, defWrite)) {
+  write.sourceMutable().assign(defWrite.source());
+  if (defWrite->use_empty())
+opToErase.push_back(defWrite.getOperation());
+  return;
+}
+if (!isDisjointTransferIndices(
+cast(defWrite.getOperation()),
+cast(write.getOperation(
+  break;
+defWrite = defWrite.source().getDefiningOp();
+  }
+}
+
+/// Walk up the SSA links, if any write fully match the written vector we can
+/// replace the read by the vector. The read becomes dead and can be removed.
+void TransferOptimization::storeToLoadForwardingTensor(
+vector::TransferReadOp read) {
+  auto defWrite = read.source().getDefiningOp();
+  while (defWrite) {
+if (transferEncompasses(defWrite, read)) {
+  read.replaceAllUsesWith(defWrite.vector

[llvm-branch-commits] [llvm] b37de2a - [Support] Untie the llvm::Signpost interface from llvm::Timer

[Jonas Devlieghere via llvm-branch-commits]

Author: Jonas Devlieghere
Date: 2021-01-06T15:16:09-08:00
New Revision: b37de2afa30fe4312aa9b87b11208bd7e05c8fa1

URL: 
https://github.com/llvm/llvm-project/commit/b37de2afa30fe4312aa9b87b11208bd7e05c8fa1
DIFF: 
https://github.com/llvm/llvm-project/commit/b37de2afa30fe4312aa9b87b11208bd7e05c8fa1.diff

LOG: [Support] Untie the llvm::Signpost interface from llvm::Timer

Make llvm::Signpost more generic by untying from llvm::Timer. This
allows signposts to be used in a different context.

My motivation for doing this is being able to use signposts in LLDB.

Differential revision: https://reviews.llvm.org/D93655

Added: 


Modified: 
llvm/include/llvm/Support/Signposts.h
llvm/lib/Support/Signposts.cpp
llvm/lib/Support/Timer.cpp

Removed: 




diff  --git a/llvm/include/llvm/Support/Signposts.h 
b/llvm/include/llvm/Support/Signposts.h
index b5a8c3d61e3e..8036b1f53663 100644
--- a/llvm/include/llvm/Support/Signposts.h
+++ b/llvm/include/llvm/Support/Signposts.h
@@ -17,9 +17,10 @@
 #ifndef LLVM_SUPPORT_SIGNPOSTS_H
 #define LLVM_SUPPORT_SIGNPOSTS_H
 
+#include "llvm/ADT/StringRef.h"
+
 namespace llvm {
 class SignpostEmitterImpl;
-class Timer;
 
 /// Manages the emission of signposts into the recording method supported by
 /// the OS.
@@ -32,10 +33,10 @@ class SignpostEmitter {
 
   bool isEnabled() const;
 
-  /// Begin a signposted interval for the given timer.
-  void startTimerInterval(Timer *T);
-  /// End a signposted interval for the given timer.
-  void endTimerInterval(Timer *T);
+  /// Begin a signposted interval for a given object.
+  void startInterval(const void *O, StringRef Name);
+  /// End a signposted interval for a given object.
+  void endInterval(const void *O, StringRef Name);
 };
 
 } // end namespace llvm

diff  --git a/llvm/lib/Support/Signposts.cpp b/llvm/lib/Support/Signposts.cpp
index aa159e1da2ae..91ce909c7dcb 100644
--- a/llvm/lib/Support/Signposts.cpp
+++ b/llvm/lib/Support/Signposts.cpp
@@ -33,21 +33,20 @@ void LogDeleter(os_log_t *X) {
 
 namespace llvm {
 class SignpostEmitterImpl {
-  using LogPtrTy =
-  std::unique_ptr>;
+  using LogPtrTy = std::unique_ptr>;
   using LogTy = LogPtrTy::element_type;
 
   LogPtrTy SignpostLog;
-  DenseMap Signposts;
+  DenseMap Signposts;
 
   LogTy &getLogger() const { return *SignpostLog; }
-  os_signpost_id_t getSignpostForTimer(const Timer *T) {
-const auto &I = Signposts.find(T);
+  os_signpost_id_t getSignpostForObject(const void *O) {
+const auto &I = Signposts.find(O);
 if (I != Signposts.end())
   return I->second;
 
 const auto &Inserted = Signposts.insert(
-std::make_pair(T, os_signpost_id_make_with_pointer(getLogger(), T)));
+std::make_pair(O, os_signpost_id_make_with_pointer(getLogger(), O)));
 return Inserted.first->second;
   }
 
@@ -56,20 +55,19 @@ class SignpostEmitterImpl {
 
   bool isEnabled() const { return os_signpost_enabled(*SignpostLog); }
 
-  void startTimerInterval(Timer *T) {
+  void startInterval(const void *O, llvm::StringRef Name) {
 if (isEnabled()) {
-  // Both strings used here are required to be constant literal strings
-  os_signpost_interval_begin(getLogger(), getSignpostForTimer(T),
- "Pass Timers", "Begin %s",
- T->getName().c_str());
+  // Both strings used here are required to be constant literal strings.
+  os_signpost_interval_begin(getLogger(), getSignpostForObject(O),
+ "LLVM Timers", "Begin %s", Name.data());
 }
   }
 
-  void endTimerInterval(Timer *T) {
+  void endInterval(const void *O, llvm::StringRef Name) {
 if (isEnabled()) {
-  // Both strings used here are required to be constant literal strings
-  os_signpost_interval_end(getLogger(), getSignpostForTimer(T),
-   "Pass Timers", "End %s", T->getName().c_str());
+  // Both strings used here are required to be constant literal strings.
+  os_signpost_interval_end(getLogger(), getSignpostForObject(O),
+   "LLVM Timers", "End %s", Name.data());
 }
   }
 };
@@ -85,7 +83,7 @@ class SignpostEmitterImpl {
 SignpostEmitter::SignpostEmitter() {
 #if HAVE_ANY_SIGNPOST_IMPL
   Impl = new SignpostEmitterImpl();
-#else // if HAVE_ANY_SIGNPOST_IMPL
+#else  // if HAVE_ANY_SIGNPOST_IMPL
   Impl = nullptr;
 #endif // if !HAVE_ANY_SIGNPOST_IMPL
 }
@@ -104,18 +102,18 @@ bool SignpostEmitter::isEnabled() const {
 #endif // if !HAVE_ANY_SIGNPOST_IMPL
 }
 
-void SignpostEmitter::startTimerInterval(Timer *T) {
+void SignpostEmitter::startInterval(const void *O, StringRef Name) {
 #if HAVE_ANY_SIGNPOST_IMPL
   if (Impl == nullptr)
 return;
-  return Impl->startTimerInterval(T);
+  return Impl->startInterval(O, Name);
 #endif // if !HAVE_ANY_SIGNPOST_IMPL
 }
 
-void SignpostEmitter::endTimerInterval(Timer *T) {
+void SignpostE

[llvm-branch-commits] [lldb] 6d94eea - [lldb] Ad os_signpost support to lldb_private::Timer

[Jonas Devlieghere via llvm-branch-commits]

Author: Jonas Devlieghere
Date: 2021-01-06T15:16:09-08:00
New Revision: 6d94eeadd28af4d488b5875778a3ebfa0d749b52

URL: 
https://github.com/llvm/llvm-project/commit/6d94eeadd28af4d488b5875778a3ebfa0d749b52
DIFF: 
https://github.com/llvm/llvm-project/commit/6d94eeadd28af4d488b5875778a3ebfa0d749b52.diff

LOG: [lldb] Ad os_signpost support to lldb_private::Timer

Emit os_signposts when supported from LLDB's timer class. A vast amount
of performance sensitive places in LLDB are already instrumented with
the Timer class.

By emitting signposts we can examine this information in Instruments. I
recommend looking at Daniel's differential for why this is so powerful:
https://reviews.llvm.org/D52954.

Differential revision: https://reviews.llvm.org/D93657

Added: 


Modified: 
lldb/include/lldb/Utility/Timer.h
lldb/source/Utility/Timer.cpp

Removed: 




diff  --git a/lldb/include/lldb/Utility/Timer.h 
b/lldb/include/lldb/Utility/Timer.h
index 91f9c57c03c1..edc064b23b57 100644
--- a/lldb/include/lldb/Utility/Timer.h
+++ b/lldb/include/lldb/Utility/Timer.h
@@ -25,6 +25,7 @@ class Timer {
   class Category {
   public:
 explicit Category(const char *category_name);
+llvm::StringRef GetName() { return m_name; }
 
   private:
 friend class Timer;

diff  --git a/lldb/source/Utility/Timer.cpp b/lldb/source/Utility/Timer.cpp
index d55c9863117b..7ead51069529 100644
--- a/lldb/source/Utility/Timer.cpp
+++ b/lldb/source/Utility/Timer.cpp
@@ -7,6 +7,8 @@
 
//===--===//
 #include "lldb/Utility/Timer.h"
 #include "lldb/Utility/Stream.h"
+#include "llvm/Support/ManagedStatic.h"
+#include "llvm/Support/Signposts.h"
 
 #include 
 #include 
@@ -28,6 +30,9 @@ typedef std::vector TimerStack;
 static std::atomic g_categories;
 } // end of anonymous namespace
 
+/// Allows llvm::Timer to emit signposts when supported.
+static llvm::ManagedStatic Signposts;
+
 std::atomic Timer::g_quiet(true);
 std::atomic Timer::g_display_depth(0);
 static std::mutex &GetFileMutex() {
@@ -54,6 +59,7 @@ void Timer::SetQuiet(bool value) { g_quiet = value; }
 
 Timer::Timer(Timer::Category &category, const char *format, ...)
 : m_category(category), m_total_start(std::chrono::steady_clock::now()) {
+  Signposts->startInterval(this, m_category.GetName());
   TimerStack &stack = GetTimerStackForCurrentThread();
 
   stack.push_back(this);
@@ -80,6 +86,8 @@ Timer::~Timer() {
   auto total_dur = stop_time - m_total_start;
   auto timer_dur = total_dur - m_child_duration;
 
+  Signposts->endInterval(this, m_category.GetName());
+
   TimerStack &stack = GetTimerStackForCurrentThread();
   if (g_quiet && stack.size() <= g_display_depth) {
 std::lock_guard lock(GetFileMutex());



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[llvm-branch-commits] [libcxx] 781c476 - [libc++] ADL-proof vector by adding _VSTD:: qualification on calls.

[Arthur O'Dwyer via llvm-branch-commits]

Author: Arthur O'Dwyer
Date: 2021-01-06T18:23:50-05:00
New Revision: 781c476ce09ed983477885e33b8acbb2220ad3a1

URL: 
https://github.com/llvm/llvm-project/commit/781c476ce09ed983477885e33b8acbb2220ad3a1
DIFF: 
https://github.com/llvm/llvm-project/commit/781c476ce09ed983477885e33b8acbb2220ad3a1.diff

LOG: [libc++] ADL-proof vector by adding _VSTD:: qualification on calls.

This affects only vectors with weird/malicious allocators,
the same corner case covered in D91708, but for `vector` this time.

Also ADL-proof <__tree>, which affects only sets and maps with weird/malicious
allocators where the ADL trap is in the *fancy pointer type*.

Also drive-by _VSTD:: qualification in the guts of std::bind,
std::packaged_task, std::condition_variable.

Differential Revision: https://reviews.llvm.org/D93424

Added: 


Modified: 
libcxx/include/__bit_reference
libcxx/include/__mutex_base
libcxx/include/__tree
libcxx/include/array
libcxx/include/bitset
libcxx/include/functional
libcxx/include/future
libcxx/include/iomanip
libcxx/include/mutex
libcxx/test/libcxx/containers/sequences/vector/robust_against_adl.pass.cpp

Removed: 




diff  --git a/libcxx/include/__bit_reference b/libcxx/include/__bit_reference
index 4a2b82064b3c9..284ed0fb0d54b 100644
--- a/libcxx/include/__bit_reference
+++ b/libcxx/include/__bit_reference
@@ -239,8 +239,8 @@ __bit_iterator<_Cp, _IsConst>
 find(__bit_iterator<_Cp, _IsConst> __first, __bit_iterator<_Cp, _IsConst> 
__last, const _Tp& __value_)
 {
 if (static_cast(__value_))
-return __find_bool_true(__first, static_cast(__last - __first));
-return __find_bool_false(__first, static_cast(__last - __first));
+return _VSTD::__find_bool_true(__first, static_cast(__last - __first));
+return _VSTD::__find_bool_false(__first, static_cast(__last - __first));
 }
 
 // count
@@ -313,8 +313,8 @@ typename __bit_iterator<_Cp, _IsConst>::
diff erence_type
 count(__bit_iterator<_Cp, _IsConst> __first, __bit_iterator<_Cp, _IsConst> 
__last, const _Tp& __value_)
 {
 if (static_cast(__value_))
-return __count_bool_true(__first, static_cast(__last - __first));
-return __count_bool_false(__first, static_cast(__last - __first));
+return _VSTD::__count_bool_true(__first, static_cast(__last - __first));
+return _VSTD::__count_bool_false(__first, static_cast(__last - __first));
 }
 
 // fill_n
@@ -387,9 +387,9 @@ fill_n(__bit_iterator<_Cp, false> __first, typename 
_Cp::size_type __n, bool __v
 if (__n > 0)
 {
 if (__value_)
-__fill_n_true(__first, __n);
+_VSTD::__fill_n_true(__first, __n);
 else
-__fill_n_false(__first, __n);
+_VSTD::__fill_n_false(__first, __n);
 }
 }
 
@@ -538,8 +538,8 @@ __bit_iterator<_Cp, false>
 copy(__bit_iterator<_Cp, _IsConst> __first, __bit_iterator<_Cp, _IsConst> 
__last, __bit_iterator<_Cp, false> __result)
 {
 if (__first.__ctz_ == __result.__ctz_)
-return __copy_aligned(__first, __last, __result);
-return __copy_unaligned(__first, __last, __result);
+return _VSTD::__copy_aligned(__first, __last, __result);
+return _VSTD::__copy_unaligned(__first, __last, __result);
 }
 
 // copy_backward
@@ -685,8 +685,8 @@ __bit_iterator<_Cp, false>
 copy_backward(__bit_iterator<_Cp, _IsConst> __first, __bit_iterator<_Cp, 
_IsConst> __last, __bit_iterator<_Cp, false> __result)
 {
 if (__last.__ctz_ == __result.__ctz_)
-return __copy_backward_aligned(__first, __last, __result);
-return __copy_backward_unaligned(__first, __last, __result);
+return _VSTD::__copy_backward_aligned(__first, __last, __result);
+return _VSTD::__copy_backward_unaligned(__first, __last, __result);
 }
 
 // move
@@ -868,8 +868,8 @@ swap_ranges(__bit_iterator<__C1, false> __first1, 
__bit_iterator<__C1, false> __
 __bit_iterator<__C2, false> __first2)
 {
 if (__first1.__ctz_ == __first2.__ctz_)
-return __swap_ranges_aligned(__first1, __last1, __first2);
-return __swap_ranges_unaligned(__first1, __last1, __first2);
+return _VSTD::__swap_ranges_aligned(__first1, __last1, __first2);
+return _VSTD::__swap_ranges_unaligned(__first1, __last1, __first2);
 }
 
 // rotate
@@ -1083,8 +1083,8 @@ bool
 equal(__bit_iterator<_Cp, _IC1> __first1, __bit_iterator<_Cp, _IC1> __last1, 
__bit_iterator<_Cp, _IC2> __first2)
 {
 if (__first1.__ctz_ == __first2.__ctz_)
-return __equal_aligned(__first1, __last1, __first2);
-return __equal_unaligned(__first1, __last1, __first2);
+return _VSTD::__equal_aligned(__first1, __last1, __first2);
+return _VSTD::__equal_unaligned(__first1, __last1, __first2);
 }
 
 template & __lk,
 if (__t <= __now)
 return cv_status::timeout;
 
-__clock_tp_ns __t_ns = 
__clock_tp_ns(__safe_nanosecond_cast(__t.time_since_epoch()));
+  

[llvm-branch-commits] [llvm] 4bdab54 - [PPC] Remove old PPCSubTarget variable.

[Kit Barton via llvm-branch-commits]

Author: Kit Barton
Date: 2021-01-06T17:44:07-06:00
New Revision: 4bdab5482667784247aa4fc72d2f6f810ad44260

URL: 
https://github.com/llvm/llvm-project/commit/4bdab5482667784247aa4fc72d2f6f810ad44260
DIFF: 
https://github.com/llvm/llvm-project/commit/4bdab5482667784247aa4fc72d2f6f810ad44260.diff

LOG: [PPC] Remove old PPCSubTarget variable.

The PPCSubTarget variable has been replaced with the Subtarget variable. This
removes the remaining instances of PPCSubTarget as they are no longer necessary.

Added: 


Modified: 
llvm/lib/Target/PowerPC/PPCFastISel.cpp
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp 
b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 85ae195e58e8..c181816e31c6 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -86,7 +86,6 @@ typedef struct Address {
 class PPCFastISel final : public FastISel {
 
   const TargetMachine &TM;
-  const PPCSubtarget *PPCSubTarget;
   const PPCSubtarget *Subtarget;
   PPCFunctionInfo *PPCFuncInfo;
   const TargetInstrInfo &TII;
@@ -97,7 +96,6 @@ class PPCFastISel final : public FastISel {
 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
  const TargetLibraryInfo *LibInfo)
 : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
-  PPCSubTarget(&FuncInfo.MF->getSubtarget()),
   Subtarget(&FuncInfo.MF->getSubtarget()),
   PPCFuncInfo(FuncInfo.MF->getInfo()),
   TII(*Subtarget->getInstrInfo()), 
TLI(*Subtarget->getTargetLowering()),

diff  --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 4ecadfbb1b8a..07b81a4325fc 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -139,7 +139,6 @@ namespace {
   ///
   class PPCDAGToDAGISel : public SelectionDAGISel {
 const PPCTargetMachine &TM;
-const PPCSubtarget *PPCSubTarget = nullptr;
 const PPCSubtarget *Subtarget = nullptr;
 const PPCTargetLowering *PPCLowering = nullptr;
 unsigned GlobalBaseReg = 0;
@@ -151,7 +150,6 @@ namespace {
 bool runOnMachineFunction(MachineFunction &MF) override {
   // Make sure we re-emit a set of the global base reg if necessary
   GlobalBaseReg = 0;
-  PPCSubTarget = &MF.getSubtarget();
   Subtarget = &MF.getSubtarget();
   PPCLowering = Subtarget->getTargetLowering();
   SelectionDAGISel::runOnMachineFunction(MF);



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[llvm-branch-commits] [clang] 8deaec1 - [analyzer] Update Fuchsia checker to catch releasing unowned handles.

[Haowei Wu via llvm-branch-commits]

Author: Daniel Hwang
Date: 2021-01-06T16:23:49-08:00
New Revision: 8deaec122ec68746c53ec2afb893873124053d8d

URL: 
https://github.com/llvm/llvm-project/commit/8deaec122ec68746c53ec2afb893873124053d8d
DIFF: 
https://github.com/llvm/llvm-project/commit/8deaec122ec68746c53ec2afb893873124053d8d.diff

LOG: [analyzer] Update Fuchsia checker to catch releasing unowned handles.

Certain Fuchsia functions may return handles that are not owned by the
current closure. This adds a check in order to determine when these
handles are released.

Differential Revision: https://reviews.llvm.org/D93868

Added: 


Modified: 
clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp
clang/test/Analysis/fuchsia_handle.cpp

Removed: 




diff  --git a/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp 
b/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp
index c246a8db3067..e3f4be0726c8 100644
--- a/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp
@@ -20,29 +20,39 @@
 // Art:
 //
 //
-//  +-+-v-+ ++
-//   acquire_func succeeded | | Escape  ||
-//+->  Allocated  +->  Escaped   <--+
-//| | | ||  |
-//| +-+--++ ++  |
-//|   |  |  |
-//| release_func  |  +--+   |
-//|   | | handle  ++|
-//|   | | dies|||
-//|  +v-+   +-> Leaked ||
-//|  |  | |(REPORT)||
-// +--+--+   | Released | Escape  ++|
-// | |   |  +---+
-// | Not tracked <--+++---+-+
-// | |  | |   |As argument by value
-// +--+--+  |release_func |   +--+ in function call
-//| | |  | or by reference in
-//| | |  | use_func call
-//+-++v-+| +---+
-//acquire_func failed| Double   |+-> Use after |
-//   | released |  | released  |
-//   | (REPORT) |  | (REPORT)  |
-//   +--+  +---+
+// +-+ ++
+//  acquire_func succeeded | | Escape  ||
+//   +->  Allocated  +->  Escaped   <--+
+//   | | | ||  |
+//   | +-+--++ ++  |
+//   |   |  |  |
+// acquire_func  | release_func  |  +--+   |
+//failed |   | | handle  ++|
+// +-+   |   | | dies|||
+// | |   |  +v-+   +-> Leaked ||
+// | |   |  |  | |(REPORT)||
+// |  +--+--+   | Released | Escape  ++|
+// |  | |   |  +---+
+// +--> Not tracked |   ++---+-+
+//| ||   |As argument by value
+//+--+--+   release_func |   +--+ in function call
+//   |   |  | or by reference in
+//   |   |  | use_func call
+//unowned|  +v-+| +---+
+//  acquire_func |  | Double   |+-> Use after |
+//   succeeded   |  | released |  | released  |
+//   |  | (REPORT) |  | (REPORT)  |
+//+---+ +--+  +---+
+//| Allocated |
+//| Unowned   |  release_func
+//|   +-+
+//+---+ |
+//  |
+//+-v--+
+//| Release of |
+//| unowned handle |
+//| (REPORT)   |
+//++
 //
 // acquire_func represents the 

[llvm-branch-commits] [llvm] 8871a4b - [Constant] Update ConstantVector::get to return poison if all input elems are poison

[Juneyoung Lee via llvm-branch-commits]

Author: Juneyoung Lee
Date: 2021-01-07T09:26:07+09:00
New Revision: 8871a4b4cab8a56fd6ff12fd024002c3c79128b3

URL: 
https://github.com/llvm/llvm-project/commit/8871a4b4cab8a56fd6ff12fd024002c3c79128b3
DIFF: 
https://github.com/llvm/llvm-project/commit/8871a4b4cab8a56fd6ff12fd024002c3c79128b3.diff

LOG: [Constant] Update ConstantVector::get to return poison if all input elems 
are poison

The diff was reviewed at D93994

Added: 


Modified: 
llvm/lib/IR/Constants.cpp
llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
llvm/test/Transforms/PhaseOrdering/X86/scalarization.ll
llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
llvm/test/Transforms/VectorCombine/X86/insert-binop.ll

Removed: 




diff  --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index 5aa819dda2b3..ba5e1ca3cdfb 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -1339,17 +1339,20 @@ Constant *ConstantVector::getImpl(ArrayRef 
V) {
   Constant *C = V[0];
   bool isZero = C->isNullValue();
   bool isUndef = isa(C);
+  bool isPoison = isa(C);
 
   if (isZero || isUndef) {
 for (unsigned i = 1, e = V.size(); i != e; ++i)
   if (V[i] != C) {
-isZero = isUndef = false;
+isZero = isUndef = isPoison = false;
 break;
   }
   }
 
   if (isZero)
 return ConstantAggregateZero::get(T);
+  if (isPoison)
+return PoisonValue::get(T);
   if (isUndef)
 return UndefValue::get(T);
 

diff  --git a/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll 
b/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
index 4cc89fc80f29..0327e2866625 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
@@ -244,7 +244,7 @@ define <16 x i8> @elts_packsswb_128(<8 x i16> %a0, <8 x 
i16> %a1) {
 
 define <16 x i8> @elts_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) {
 ; CHECK-LABEL: @elts_packuswb_128(
-; CHECK-NEXT:ret <16 x i8> undef
+; CHECK-NEXT:ret <16 x i8> poison
 ;
   %1 = insertelement <8 x i16> poison, i16 0, i32 0
   %2 = insertelement <8 x i16> poison, i16 0, i32 0
@@ -293,7 +293,7 @@ define <32 x i8> @elts_packsswb_256(<16 x i16> %a0, <16 x 
i16> %a1) {
 
 define <32 x i8> @elts_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) {
 ; CHECK-LABEL: @elts_packuswb_256(
-; CHECK-NEXT:ret <32 x i8> undef
+; CHECK-NEXT:ret <32 x i8> poison
 ;
   %1 = insertelement <16 x i16> poison, i16 0, i32 1
   %2 = insertelement <16 x i16> poison, i16 0, i32 0
@@ -344,7 +344,7 @@ define <64 x i8> @elts_packsswb_512(<32 x i16> %a0, <32 x 
i16> %a1) {
 
 define <64 x i8> @elts_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) {
 ; CHECK-LABEL: @elts_packuswb_512(
-; CHECK-NEXT:ret <64 x i8> undef
+; CHECK-NEXT:ret <64 x i8> poison
 ;
   %1 = insertelement <32 x i16> poison, i16 0, i32 1
   %2 = insertelement <32 x i16> poison, i16 0, i32 0

diff  --git a/llvm/test/Transforms/PhaseOrdering/X86/scalarization.ll 
b/llvm/test/Transforms/PhaseOrdering/X86/scalarization.ll
index 505f16786b60..fd97b2ea6b4a 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/scalarization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/scalarization.ll
@@ -27,7 +27,7 @@ define <4 x i32> @square(<4 x i32> %num, i32 %y, i32 %x, i32 
%h, i32 %k, i32 %w,
 ; CHECK-NEXT:[[DOTSCALAR6:%.*]] = add i32 [[DOTSCALAR5]], [[DIV9]]
 ; CHECK-NEXT:[[DOTSCALAR7:%.*]] = add i32 [[DOTSCALAR6]], [[MUL21]]
 ; CHECK-NEXT:[[DOTSCALAR8:%.*]] = add i32 [[DOTSCALAR7]], 317425
-; CHECK-NEXT:[[TMP1:%.*]] = insertelement <4 x i32> undef, i32 
[[DOTSCALAR8]], i64 0
+; CHECK-NEXT:[[TMP1:%.*]] = insertelement <4 x i32> poison, i32 
[[DOTSCALAR8]], i64 0
 ; CHECK-NEXT:[[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> 
poison, <4 x i32> zeroinitializer
 ; CHECK-NEXT:[[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]]
 ; CHECK-NEXT:ret <4 x i32> [[ADD29]]

diff  --git 
a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll 
b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
index ac6ece368ff0..54e84394d30d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
@@ -425,7 +425,7 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
 ; CHECK-NEXT:[[AB5:%.*]] = sdiv i32 [[A5]], 4
 ; CHECK-NEXT:[[AB6:%.*]] = sdiv i32 [[A6]], 8
 ; CHECK-NEXT:[[AB7:%.*]] = sdiv i32 [[A7]], 16
-; CHECK-NEXT:[[TMP1:%.*]] = insertelement <8 x i32> , i32 [[AB1]], i32 1
+; CHECK-NEXT:[[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[AB1]], 
i32 1
 ; CHECK-NEXT:[[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], 

[llvm-branch-commits] [lldb] d853bd7 - [lldb/Lua] add support for multiline scripted breakpoints

[Pedro Tammela via llvm-branch-commits]

Author: Pedro Tammela
Date: 2021-01-07T00:31:36Z
New Revision: d853bd7a4e86a50f7d7e6a5f397fcbd1e7d844b4

URL: 
https://github.com/llvm/llvm-project/commit/d853bd7a4e86a50f7d7e6a5f397fcbd1e7d844b4
DIFF: 
https://github.com/llvm/llvm-project/commit/d853bd7a4e86a50f7d7e6a5f397fcbd1e7d844b4.diff

LOG: [lldb/Lua] add support for multiline scripted breakpoints

1 - Partial Statements

The interpreter loop runs every line it receives, so partial
Lua statements are not being handled properly. This is a problem for
multiline breakpoint scripts since the interpreter loop, for this
particular case, is just an abstraction to a partially parsed function
body declaration.

This patch addresses this issue and as a side effect improves the
general Lua interpreter loop as well. It's now possible to write partial
statements in the 'script' command.

Example:
   (lldb) script
   >>>   do
   ..>   local a = 123
   ..>   print(a)
   ..>   end
   123

The technique implemented is the same as the one employed by Lua's own REPL 
implementation.
Partial statements always errors out with the '' tag in the error
message.

2 - CheckSyntax in Lua.h

In order to support (1), we need an API for just checking the syntax of string 
buffers.

3 - Multiline scripted breakpoints

Finally, with all the base features implemented this feature is
straightforward. The interpreter loop behaves exactly the same, the
difference is that it will aggregate all Lua statements into the body of
the breakpoint function. An explicit 'quit' statement is needed to exit the
interpreter loop.

Example:
   (lldb) breakpoint command add -s lua
   Enter your Lua command(s). Type 'quit' to end.
   The commands are compiled as the body of the following Lua function
   function (frame, bp_loc, ...) end
   ..> print(456)
   ..> a = 123
   ..> quit

Differential Revision: https://reviews.llvm.org/D93481

Added: 
lldb/test/Shell/ScriptInterpreter/Lua/partial_statements.test

Modified: 
lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
lldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.h
lldb/test/Shell/ScriptInterpreter/Lua/breakpoint_callback.test

Removed: 




diff  --git a/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp 
b/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
index fb3628a3107c..ec946d1b97e4 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
+++ b/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
@@ -105,6 +105,23 @@ Lua::CallBreakpointCallback(void *baton, 
lldb::StackFrameSP stop_frame_sp,
bp_loc_sp);
 }
 
+llvm::Error Lua::CheckSyntax(llvm::StringRef buffer) {
+  int error =
+  luaL_loadbuffer(m_lua_state, buffer.data(), buffer.size(), "buffer");
+  if (error == LUA_OK) {
+// Pop buffer
+lua_pop(m_lua_state, 1);
+return llvm::Error::success();
+  }
+
+  llvm::Error e = llvm::make_error(
+  llvm::formatv("{0}\n", lua_tostring(m_lua_state, -1)),
+  llvm::inconvertibleErrorCode());
+  // Pop error message from the stack.
+  lua_pop(m_lua_state, 1);
+  return e;
+}
+
 llvm::Error Lua::LoadModule(llvm::StringRef filename) {
   FileSpec file(filename);
   if (!FileSystem::Instance().Exists(file)) {

diff  --git a/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.h 
b/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
index 39c39e1c43b8..84cc0148a7eb 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
+++ b/lldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
@@ -36,6 +36,7 @@ class Lua {
   CallBreakpointCallback(void *baton, lldb::StackFrameSP stop_frame_sp,
  lldb::BreakpointLocationSP bp_loc_sp);
   llvm::Error LoadModule(llvm::StringRef filename);
+  llvm::Error CheckSyntax(llvm::StringRef buffer);
   llvm::Error ChangeIO(FILE *out, FILE *err);
 
 private:

diff  --git 
a/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp 
b/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
index 239b409ac695..1dbadb90813c 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
+++ b/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
@@ -17,23 +17,33 @@
 #include "lldb/Utility/Stream.h"
 #include "lldb/Utility/StringList.h"
 #include "lldb/Utility/Timer.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/Support/FormatAdapters.h"
 #include 
+#include 
 
 using namespace lldb;
 using namespace lldb_private;
 
 LLDB_PLUGIN_DEFINE(ScriptInterpreterLua)
 
+enum ActiveIOHandler {
+  eIOHandlerNone,
+  eIOHandlerBreakpoint,
+  eIOHandlerWatchpoint
+};
+
 class IOHandlerLuaInterpreter : public IOHandlerDelegate,
 public IOHandlerEditline {
 public:
   IOHandlerLuaInterpreter(Debugger &debugger,
-  ScriptInterpret

[llvm-branch-commits] [llvm] 7a8ced4 - [RISCV] Fix a few section number comments in RISCVInstrInfoVPseudos.td to match the V extension 1.0 draft spec. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-06T16:38:30-08:00
New Revision: 7a8ced43d7ec60f184ed88cc2dd085aba900ce3b

URL: 
https://github.com/llvm/llvm-project/commit/7a8ced43d7ec60f184ed88cc2dd085aba900ce3b
DIFF: 
https://github.com/llvm/llvm-project/commit/7a8ced43d7ec60f184ed88cc2dd085aba900ce3b.diff

LOG: [RISCV] Fix a few section number comments in RISCVInstrInfoVPseudos.td to 
match the V extension 1.0 draft spec. NFC

The majority of the comments use the 1.0 draft spec section numbers.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index d10c2a2c70ab..62d887524950 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2671,7 +2671,7 @@ defm PseudoVFWMSAC : 
VPseudoTernaryW_VV_VX;
 defm PseudoVFWNMSAC: VPseudoTernaryW_VV_VX;
 
 
//===--===//
-// 14.9. Vector Floating-Point Min/Max Instructions
+// 14.11. Vector Floating-Point Min/Max Instructions
 
//===--===//
 defm PseudoVFMIN   : VPseudoBinaryV_VV_VX;
 defm PseudoVFMAX   : VPseudoBinaryV_VV_VX;
@@ -2693,17 +2693,17 @@ defm PseudoVMFLE   : 
VPseudoBinaryM_VV_VX;
 defm PseudoVMFGT   : VPseudoBinaryM_VX;
 defm PseudoVMFGE   : VPseudoBinaryM_VX;
 
-//===--===//
-// 14.14. Vector Floating-Point Move Instruction
-//===--===//
-defm PseudoVFMV_V  : VPseudoUnaryV_F_NoDummyMask;
-
 
//===--===//
 // 14.15. Vector Floating-Point Merge Instruction
 
//===--===//
 defm PseudoVFMERGE : VPseudoBinaryV_XM;
 
+//===--===//
+// 14.16. Vector Floating-Point Move Instruction
+//===--===//
+defm PseudoVFMV_V  : VPseudoUnaryV_F_NoDummyMask;
+
 
//===--===//
 // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
 
//===--===//
@@ -3307,7 +3307,7 @@ defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", 
"PseudoVFWMSAC", AllWidenableF
 defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", 
AllWidenableFloatVectors>;
 
 
//===--===//
-// 14.9. Vector Floating-Point Min/Max Instructions
+// 14.11. Vector Floating-Point Min/Max Instructions
 
//===--===//
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>;
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>;
@@ -3330,7 +3330,16 @@ defm "" : VPatBinaryM_VX<"int_riscv_vmfgt", 
"PseudoVMFGT", AllFloatVectors>;
 defm "" : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>;
 
 
//===--===//
-// 14.14. Vector Floating-Point Move Instruction
+// 14.15. Vector Floating-Point Merge Instruction
+//===--===//
+// We can use vmerge.vvm to support vector-vector vfmerge.
+defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE",
+ /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
+defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE",
+ /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
+
+//===--===//
+// 14.16. Vector Floating-Point Move Instruction
 
//===--===//
 foreach fvti = AllFloatVectors in {
   // If we're splatting fpimm0, use vmv.v.x vd, x0.
@@ -3346,15 +3355,6 @@ foreach fvti = AllFloatVectors in {
  (NoX0 GPR:$vl), fvti.SEW)>;
 }
 
-//===--===//
-// 14.15. Vector Floating-Point Merge Instruction
-//===--===//
-// We can use vmerge.vvm to support vector-vector vfmerge.
-defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE",
- /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
-defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE",
- /*CarryOut = */0, /*vtilist=*/AllF

[llvm-branch-commits] [clang] 37e83bc - [NFC] Move readAPValue/writeAPValue up the inheritance hierarchy

[Varun Gandhi via llvm-branch-commits]

Author: Varun Gandhi
Date: 2021-01-06T16:44:50-08:00
New Revision: 37e83bc6db3ad7d9a5d182694ebe71ebbc6120de

URL: 
https://github.com/llvm/llvm-project/commit/37e83bc6db3ad7d9a5d182694ebe71ebbc6120de
DIFF: 
https://github.com/llvm/llvm-project/commit/37e83bc6db3ad7d9a5d182694ebe71ebbc6120de.diff

LOG: [NFC] Move readAPValue/writeAPValue up the inheritance hierarchy

The implementation for (de)serialization of APValues can be shared
between Clang and Swift, so we prefer pushing the methods up
the inheritance hierarchy, instead of having the methods live in
ASTReader/ASTWriter. Fixes rdar://72592937.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D94196

Added: 


Modified: 
clang/include/clang/AST/APValue.h
clang/include/clang/AST/AbstractBasicReader.h
clang/include/clang/AST/AbstractBasicWriter.h
clang/include/clang/AST/PropertiesBase.td
clang/include/clang/Serialization/ASTRecordReader.h
clang/include/clang/Serialization/ASTRecordWriter.h
clang/include/clang/Serialization/ASTWriter.h
clang/lib/AST/APValue.cpp
clang/lib/Serialization/ASTReader.cpp
clang/lib/Serialization/ASTWriter.cpp
clang/utils/TableGen/ClangASTPropertiesEmitter.cpp

Removed: 




diff  --git a/clang/include/clang/AST/APValue.h 
b/clang/include/clang/AST/APValue.h
index eded34808ad7..f9b189926c76 100644
--- a/clang/include/clang/AST/APValue.h
+++ b/clang/include/clang/AST/APValue.h
@@ -23,6 +23,10 @@
 #include "llvm/Support/AlignOf.h"
 
 namespace clang {
+namespace serialization {
+template  class BasicReaderBase;
+} // end namespace serialization
+
   class AddrLabelExpr;
   class ASTContext;
   class CharUnits;
@@ -233,12 +237,20 @@ class APValue {
   return llvm::hash_value(A.Value);
 }
   };
+  class LValuePathSerializationHelper {
+const void *ElemTy;
+
+  public:
+ArrayRef Path;
+
+LValuePathSerializationHelper(ArrayRef, QualType);
+QualType getType();
+  };
   struct NoLValuePath {};
   struct UninitArray {};
   struct UninitStruct {};
 
-  friend class ASTRecordReader;
-  friend class ASTWriter;
+  template  friend class clang::serialization::BasicReaderBase;
   friend class ASTImporter;
   friend class ASTNodeImporter;
 

diff  --git a/clang/include/clang/AST/AbstractBasicReader.h 
b/clang/include/clang/AST/AbstractBasicReader.h
index d7b3a9da88ec..5505d661b44e 100644
--- a/clang/include/clang/AST/AbstractBasicReader.h
+++ b/clang/include/clang/AST/AbstractBasicReader.h
@@ -177,6 +177,40 @@ class DataStreamBasicReader : public BasicReaderBase 
{
 return llvm::APInt(bitWidth, numWords, &data[0]);
   }
 
+  llvm::FixedPointSemantics readFixedPointSemantics() {
+unsigned width = asImpl().readUInt32();
+unsigned scale = asImpl().readUInt32();
+unsigned tmp = asImpl().readUInt32();
+bool isSigned = tmp & 0x1;
+bool isSaturated = tmp & 0x2;
+bool hasUnsignedPadding = tmp & 0x4;
+return llvm::FixedPointSemantics(width, scale, isSigned, isSaturated,
+ hasUnsignedPadding);
+  }
+
+  APValue::LValuePathSerializationHelper readLValuePathSerializationHelper(
+  SmallVectorImpl &path) {
+auto elemTy = asImpl().readQualType();
+unsigned pathLength = asImpl().readUInt32();
+for (unsigned i = 0; i < pathLength; ++i) {
+  if (elemTy->template getAs()) {
+unsigned int_ = asImpl().readUInt32();
+Decl *decl = asImpl().template readDeclAs();
+if (auto *recordDecl = dyn_cast(decl))
+  elemTy = getASTContext().getRecordType(recordDecl);
+else
+  elemTy = cast(decl)->getType();
+path.push_back(
+APValue::LValuePathEntry(APValue::BaseOrMemberType(decl, int_)));
+  } else {
+elemTy = getASTContext().getAsArrayType(elemTy)->getElementType();
+path.push_back(
+APValue::LValuePathEntry::ArrayIndex(asImpl().readUInt32()));
+  }
+}
+return APValue::LValuePathSerializationHelper(path, elemTy);
+  }
+
   Qualifiers readQualifiers() {
 static_assert(sizeof(Qualifiers().getAsOpaqueValue()) <= sizeof(uint32_t),
   "update this if the value size changes");

diff  --git a/clang/include/clang/AST/AbstractBasicWriter.h 
b/clang/include/clang/AST/AbstractBasicWriter.h
index 0a6730c86bbf..75aef734ba9b 100644
--- a/clang/include/clang/AST/AbstractBasicWriter.h
+++ b/clang/include/clang/AST/AbstractBasicWriter.h
@@ -9,6 +9,7 @@
 #ifndef CLANG_AST_ABSTRACTBASICWRITER_H
 #define CLANG_AST_ABSTRACTBASICWRITER_H
 
+#include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclTemplate.h"
 
 namespace clang {
@@ -121,6 +122,7 @@ template 
 class DataStreamBasicWriter : public BasicWriterBase {
 protected:
   using BasicWriterBase::asImpl;
+  DataStreamBasicWriter(ASTContext &ctx) : BasicWriterBase(ctx) {}
 
 public:
   /// Implement property-find by ignoring it.  We rely on properties

[llvm-branch-commits] [llvm] c95f398 - [Constant] Add tests for ConstantVector::get (NFC)

[Juneyoung Lee via llvm-branch-commits]

Author: Juneyoung Lee
Date: 2021-01-07T10:08:01+09:00
New Revision: c95f39891a282ebf36199c73b705d4a2c78a46ce

URL: 
https://github.com/llvm/llvm-project/commit/c95f39891a282ebf36199c73b705d4a2c78a46ce
DIFF: 
https://github.com/llvm/llvm-project/commit/c95f39891a282ebf36199c73b705d4a2c78a46ce.diff

LOG: [Constant] Add tests for ConstantVector::get (NFC)

Added: 


Modified: 
llvm/unittests/IR/ConstantsTest.cpp

Removed: 




diff  --git a/llvm/unittests/IR/ConstantsTest.cpp 
b/llvm/unittests/IR/ConstantsTest.cpp
index afae154cca90..9eabc7c55638 100644
--- a/llvm/unittests/IR/ConstantsTest.cpp
+++ b/llvm/unittests/IR/ConstantsTest.cpp
@@ -631,9 +631,17 @@ TEST(ConstantsTest, isElementWiseEqual) {
 
   Type *Int32Ty = Type::getInt32Ty(Context);
   Constant *CU = UndefValue::get(Int32Ty);
+  Constant *CP = PoisonValue::get(Int32Ty);
   Constant *C1 = ConstantInt::get(Int32Ty, 1);
   Constant *C2 = ConstantInt::get(Int32Ty, 2);
 
+  Constant *CUU = ConstantVector::get({CU, CU});
+  Constant *CPP = ConstantVector::get({CP, CP});
+  Constant *CUP = ConstantVector::get({CU, CP});
+  EXPECT_EQ(CUU, UndefValue::get(CUU->getType()));
+  EXPECT_EQ(CPP, PoisonValue::get(CPP->getType()));
+  EXPECT_NE(CUP, UndefValue::get(CUP->getType()));
+
   Constant *C1211 = ConstantVector::get({C1, C2, C1, C1});
   Constant *C12U1 = ConstantVector::get({C1, C2, CU, C1});
   Constant *C12U2 = ConstantVector::get({C1, C2, CU, C2});



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